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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.31 97.99 95.95 93.38 100.00 98.55 99.00 96.29


Total test records in report: 991
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T820 /workspace/coverage/default/20.lc_ctrl_jtag_access.2729901718 Jul 11 06:21:23 PM PDT 24 Jul 11 06:21:35 PM PDT 24 1352428454 ps
T821 /workspace/coverage/default/47.lc_ctrl_sec_token_mux.635420693 Jul 11 06:22:29 PM PDT 24 Jul 11 06:22:49 PM PDT 24 375462363 ps
T822 /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3435656378 Jul 11 06:22:35 PM PDT 24 Jul 11 06:22:53 PM PDT 24 1236646300 ps
T823 /workspace/coverage/default/40.lc_ctrl_alert_test.3681524071 Jul 11 06:22:10 PM PDT 24 Jul 11 06:22:16 PM PDT 24 86966438 ps
T824 /workspace/coverage/default/13.lc_ctrl_smoke.3296361379 Jul 11 06:20:59 PM PDT 24 Jul 11 06:21:06 PM PDT 24 69510796 ps
T825 /workspace/coverage/default/34.lc_ctrl_state_failure.1766506901 Jul 11 06:21:54 PM PDT 24 Jul 11 06:22:32 PM PDT 24 2653390674 ps
T826 /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.43560273 Jul 11 06:20:53 PM PDT 24 Jul 11 06:21:02 PM PDT 24 1181750167 ps
T184 /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1843102758 Jul 11 06:20:24 PM PDT 24 Jul 11 06:20:27 PM PDT 24 23621378 ps
T827 /workspace/coverage/default/49.lc_ctrl_state_failure.3132451712 Jul 11 06:22:36 PM PDT 24 Jul 11 06:23:12 PM PDT 24 230434324 ps
T828 /workspace/coverage/default/29.lc_ctrl_state_post_trans.2679452725 Jul 11 06:21:50 PM PDT 24 Jul 11 06:21:59 PM PDT 24 66059682 ps
T829 /workspace/coverage/default/17.lc_ctrl_state_failure.2221105314 Jul 11 06:21:07 PM PDT 24 Jul 11 06:21:36 PM PDT 24 189496673 ps
T111 /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.3524172046 Jul 11 06:21:17 PM PDT 24 Jul 11 06:27:18 PM PDT 24 12248589914 ps
T151 /workspace/coverage/default/37.lc_ctrl_state_failure.2161502998 Jul 11 06:22:13 PM PDT 24 Jul 11 06:22:48 PM PDT 24 236569663 ps
T152 /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2340517280 Jul 11 06:20:49 PM PDT 24 Jul 11 06:21:00 PM PDT 24 246418830 ps
T153 /workspace/coverage/default/1.lc_ctrl_jtag_priority.3531352019 Jul 11 06:20:07 PM PDT 24 Jul 11 06:20:12 PM PDT 24 227119596 ps
T154 /workspace/coverage/default/9.lc_ctrl_prog_failure.2546142089 Jul 11 06:20:53 PM PDT 24 Jul 11 06:20:59 PM PDT 24 46879755 ps
T155 /workspace/coverage/default/8.lc_ctrl_stress_all.3766402509 Jul 11 06:20:46 PM PDT 24 Jul 11 06:21:56 PM PDT 24 3966756293 ps
T156 /workspace/coverage/default/43.lc_ctrl_sec_mubi.3003600492 Jul 11 06:22:18 PM PDT 24 Jul 11 06:22:32 PM PDT 24 207357194 ps
T157 /workspace/coverage/default/1.lc_ctrl_claim_transition_if.4272269602 Jul 11 06:20:02 PM PDT 24 Jul 11 06:20:05 PM PDT 24 46877075 ps
T158 /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.4073710949 Jul 11 06:19:57 PM PDT 24 Jul 11 06:21:03 PM PDT 24 2638127875 ps
T159 /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3189826480 Jul 11 06:21:55 PM PDT 24 Jul 11 06:22:07 PM PDT 24 1558168182 ps
T830 /workspace/coverage/default/34.lc_ctrl_errors.587619318 Jul 11 06:21:59 PM PDT 24 Jul 11 06:22:14 PM PDT 24 780031392 ps
T831 /workspace/coverage/default/18.lc_ctrl_smoke.849214873 Jul 11 06:21:16 PM PDT 24 Jul 11 06:21:21 PM PDT 24 16879124 ps
T832 /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.427098303 Jul 11 06:20:52 PM PDT 24 Jul 11 06:21:12 PM PDT 24 668426056 ps
T833 /workspace/coverage/default/38.lc_ctrl_sec_mubi.3257119582 Jul 11 06:22:04 PM PDT 24 Jul 11 06:22:22 PM PDT 24 650325569 ps
T834 /workspace/coverage/default/23.lc_ctrl_state_failure.2457559339 Jul 11 06:21:36 PM PDT 24 Jul 11 06:22:05 PM PDT 24 1039802819 ps
T835 /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2864674656 Jul 11 06:21:12 PM PDT 24 Jul 11 06:22:14 PM PDT 24 1257510415 ps
T836 /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.161258985 Jul 11 06:21:58 PM PDT 24 Jul 11 06:22:03 PM PDT 24 12451647 ps
T837 /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.467121580 Jul 11 06:20:58 PM PDT 24 Jul 11 06:21:17 PM PDT 24 2103853627 ps
T838 /workspace/coverage/default/9.lc_ctrl_jtag_errors.524708191 Jul 11 06:20:51 PM PDT 24 Jul 11 06:21:27 PM PDT 24 7571933874 ps
T839 /workspace/coverage/default/13.lc_ctrl_state_failure.979909835 Jul 11 06:20:59 PM PDT 24 Jul 11 06:21:28 PM PDT 24 1072860999 ps
T840 /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3338513052 Jul 11 06:21:06 PM PDT 24 Jul 11 06:21:20 PM PDT 24 344994948 ps
T145 /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1064300181 Jul 11 06:21:21 PM PDT 24 Jul 11 06:43:19 PM PDT 24 158032572425 ps
T841 /workspace/coverage/default/13.lc_ctrl_sec_mubi.2071171318 Jul 11 06:20:59 PM PDT 24 Jul 11 06:21:15 PM PDT 24 3324683699 ps
T842 /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3099866796 Jul 11 06:21:23 PM PDT 24 Jul 11 06:21:27 PM PDT 24 21276758 ps
T843 /workspace/coverage/default/23.lc_ctrl_state_post_trans.3741444845 Jul 11 06:21:35 PM PDT 24 Jul 11 06:21:45 PM PDT 24 60646134 ps
T844 /workspace/coverage/default/48.lc_ctrl_state_post_trans.1030920412 Jul 11 06:22:28 PM PDT 24 Jul 11 06:22:42 PM PDT 24 74679804 ps
T845 /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1210265028 Jul 11 06:21:51 PM PDT 24 Jul 11 06:22:03 PM PDT 24 348408873 ps
T846 /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3821623129 Jul 11 06:21:53 PM PDT 24 Jul 11 06:21:57 PM PDT 24 12604893 ps
T847 /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1144123798 Jul 11 06:20:47 PM PDT 24 Jul 11 06:20:58 PM PDT 24 677121190 ps
T848 /workspace/coverage/default/13.lc_ctrl_state_post_trans.2014499544 Jul 11 06:20:57 PM PDT 24 Jul 11 06:21:09 PM PDT 24 143752022 ps
T849 /workspace/coverage/default/29.lc_ctrl_errors.1345819783 Jul 11 06:21:45 PM PDT 24 Jul 11 06:21:59 PM PDT 24 461430737 ps
T850 /workspace/coverage/default/37.lc_ctrl_smoke.382668257 Jul 11 06:22:07 PM PDT 24 Jul 11 06:22:15 PM PDT 24 66457652 ps
T851 /workspace/coverage/default/40.lc_ctrl_errors.2494746664 Jul 11 06:22:11 PM PDT 24 Jul 11 06:22:29 PM PDT 24 262136767 ps
T852 /workspace/coverage/default/2.lc_ctrl_security_escalation.1536917950 Jul 11 06:20:12 PM PDT 24 Jul 11 06:20:27 PM PDT 24 386131732 ps
T853 /workspace/coverage/default/10.lc_ctrl_jtag_access.786638233 Jul 11 06:20:56 PM PDT 24 Jul 11 06:21:23 PM PDT 24 4096059344 ps
T854 /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2040707122 Jul 11 06:20:11 PM PDT 24 Jul 11 06:20:30 PM PDT 24 2148484555 ps
T855 /workspace/coverage/default/7.lc_ctrl_smoke.123712264 Jul 11 06:20:36 PM PDT 24 Jul 11 06:20:39 PM PDT 24 34653060 ps
T856 /workspace/coverage/default/45.lc_ctrl_stress_all.2367667881 Jul 11 06:22:23 PM PDT 24 Jul 11 06:23:37 PM PDT 24 1864603670 ps
T857 /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.4258375184 Jul 11 06:20:47 PM PDT 24 Jul 11 06:21:39 PM PDT 24 12155711161 ps
T858 /workspace/coverage/default/8.lc_ctrl_prog_failure.708614617 Jul 11 06:20:41 PM PDT 24 Jul 11 06:20:45 PM PDT 24 36096580 ps
T859 /workspace/coverage/default/23.lc_ctrl_sec_mubi.4049692252 Jul 11 06:21:35 PM PDT 24 Jul 11 06:21:53 PM PDT 24 364884359 ps
T860 /workspace/coverage/default/1.lc_ctrl_jtag_errors.592302372 Jul 11 06:20:07 PM PDT 24 Jul 11 06:20:45 PM PDT 24 4224282712 ps
T861 /workspace/coverage/default/20.lc_ctrl_security_escalation.4017310323 Jul 11 06:21:22 PM PDT 24 Jul 11 06:21:37 PM PDT 24 371807919 ps
T862 /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1632232461 Jul 11 06:21:45 PM PDT 24 Jul 11 06:21:49 PM PDT 24 12883179 ps
T863 /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2123806309 Jul 11 06:21:36 PM PDT 24 Jul 11 06:21:48 PM PDT 24 3185876250 ps
T116 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.906860527 Jul 11 06:19:12 PM PDT 24 Jul 11 06:19:14 PM PDT 24 45461444 ps
T108 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3282482250 Jul 11 06:18:58 PM PDT 24 Jul 11 06:19:02 PM PDT 24 50103497 ps
T105 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2038971153 Jul 11 06:19:45 PM PDT 24 Jul 11 06:19:49 PM PDT 24 45871425 ps
T106 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2431466515 Jul 11 06:19:17 PM PDT 24 Jul 11 06:19:22 PM PDT 24 59699991 ps
T136 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.233037881 Jul 11 06:19:03 PM PDT 24 Jul 11 06:19:05 PM PDT 24 167172940 ps
T132 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3948246998 Jul 11 06:18:47 PM PDT 24 Jul 11 06:18:49 PM PDT 24 12741863 ps
T175 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3092007252 Jul 11 06:19:27 PM PDT 24 Jul 11 06:19:29 PM PDT 24 17295764 ps
T107 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.329872267 Jul 11 06:19:29 PM PDT 24 Jul 11 06:19:35 PM PDT 24 1557159630 ps
T109 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.564690988 Jul 11 06:19:30 PM PDT 24 Jul 11 06:19:35 PM PDT 24 48287541 ps
T864 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1628818457 Jul 11 06:18:40 PM PDT 24 Jul 11 06:18:43 PM PDT 24 18322192 ps
T865 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2703368852 Jul 11 06:19:12 PM PDT 24 Jul 11 06:19:14 PM PDT 24 68479352 ps
T146 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1401789763 Jul 11 06:19:27 PM PDT 24 Jul 11 06:19:30 PM PDT 24 31862261 ps
T162 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3798704330 Jul 11 06:18:31 PM PDT 24 Jul 11 06:18:34 PM PDT 24 43725659 ps
T121 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3683121105 Jul 11 06:19:17 PM PDT 24 Jul 11 06:19:21 PM PDT 24 73895831 ps
T113 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1812477917 Jul 11 06:19:33 PM PDT 24 Jul 11 06:19:39 PM PDT 24 73317265 ps
T112 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4268486066 Jul 11 06:18:58 PM PDT 24 Jul 11 06:19:01 PM PDT 24 163483852 ps
T148 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.525592004 Jul 11 06:19:31 PM PDT 24 Jul 11 06:19:35 PM PDT 24 22223352 ps
T149 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.399095633 Jul 11 06:18:34 PM PDT 24 Jul 11 06:18:38 PM PDT 24 383964446 ps
T150 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2314680371 Jul 11 06:19:13 PM PDT 24 Jul 11 06:19:15 PM PDT 24 33009051 ps
T866 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2635585280 Jul 11 06:19:15 PM PDT 24 Jul 11 06:19:17 PM PDT 24 17297155 ps
T867 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3928663309 Jul 11 06:19:05 PM PDT 24 Jul 11 06:19:09 PM PDT 24 36537271 ps
T119 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3160986082 Jul 11 06:18:37 PM PDT 24 Jul 11 06:18:42 PM PDT 24 96105452 ps
T868 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.566601297 Jul 11 06:19:15 PM PDT 24 Jul 11 06:19:18 PM PDT 24 50348537 ps
T869 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.504573681 Jul 11 06:18:55 PM PDT 24 Jul 11 06:18:59 PM PDT 24 84078825 ps
T176 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1617419963 Jul 11 06:18:59 PM PDT 24 Jul 11 06:19:02 PM PDT 24 36473988 ps
T110 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.189717105 Jul 11 06:19:25 PM PDT 24 Jul 11 06:19:29 PM PDT 24 241151956 ps
T870 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1210191324 Jul 11 06:18:34 PM PDT 24 Jul 11 06:18:38 PM PDT 24 149396824 ps
T177 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3502641176 Jul 11 06:19:04 PM PDT 24 Jul 11 06:19:07 PM PDT 24 44498887 ps
T114 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3352690225 Jul 11 06:19:03 PM PDT 24 Jul 11 06:19:07 PM PDT 24 230741991 ps
T871 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1600135018 Jul 11 06:18:43 PM PDT 24 Jul 11 06:18:46 PM PDT 24 30586151 ps
T133 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2262765005 Jul 11 06:19:00 PM PDT 24 Jul 11 06:19:03 PM PDT 24 524967368 ps
T134 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.743092278 Jul 11 06:18:43 PM PDT 24 Jul 11 06:18:49 PM PDT 24 847204259 ps
T115 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2715453437 Jul 11 06:19:17 PM PDT 24 Jul 11 06:19:23 PM PDT 24 226805511 ps
T872 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3376991282 Jul 11 06:18:42 PM PDT 24 Jul 11 06:18:45 PM PDT 24 63711741 ps
T135 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1444923857 Jul 11 06:18:30 PM PDT 24 Jul 11 06:18:50 PM PDT 24 1758950459 ps
T163 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3486872738 Jul 11 06:19:29 PM PDT 24 Jul 11 06:19:31 PM PDT 24 39511183 ps
T117 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1158834893 Jul 11 06:18:42 PM PDT 24 Jul 11 06:18:47 PM PDT 24 139243849 ps
T178 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3866154508 Jul 11 06:18:43 PM PDT 24 Jul 11 06:18:47 PM PDT 24 21805189 ps
T873 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3268796429 Jul 11 06:19:29 PM PDT 24 Jul 11 06:19:33 PM PDT 24 54759745 ps
T179 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1955422196 Jul 11 06:19:38 PM PDT 24 Jul 11 06:19:40 PM PDT 24 27342259 ps
T120 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1372795271 Jul 11 06:19:31 PM PDT 24 Jul 11 06:19:37 PM PDT 24 300790257 ps
T874 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1832947518 Jul 11 06:19:17 PM PDT 24 Jul 11 06:19:25 PM PDT 24 117802750 ps
T875 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.957144312 Jul 11 06:19:01 PM PDT 24 Jul 11 06:19:03 PM PDT 24 18613332 ps
T180 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2507955736 Jul 11 06:19:04 PM PDT 24 Jul 11 06:19:07 PM PDT 24 37493922 ps
T181 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2539776124 Jul 11 06:19:19 PM PDT 24 Jul 11 06:19:24 PM PDT 24 105332171 ps
T876 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1466178602 Jul 11 06:19:16 PM PDT 24 Jul 11 06:19:20 PM PDT 24 51341722 ps
T877 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.143796952 Jul 11 06:18:58 PM PDT 24 Jul 11 06:19:02 PM PDT 24 58708451 ps
T182 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.572104900 Jul 11 06:18:31 PM PDT 24 Jul 11 06:18:33 PM PDT 24 12075504 ps
T878 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3236720113 Jul 11 06:18:35 PM PDT 24 Jul 11 06:18:38 PM PDT 24 570953032 ps
T879 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1674502626 Jul 11 06:19:36 PM PDT 24 Jul 11 06:19:39 PM PDT 24 45492955 ps
T124 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.4005856981 Jul 11 06:18:33 PM PDT 24 Jul 11 06:18:36 PM PDT 24 56328282 ps
T880 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3194091313 Jul 11 06:18:38 PM PDT 24 Jul 11 06:18:41 PM PDT 24 148192340 ps
T881 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1629777353 Jul 11 06:18:59 PM PDT 24 Jul 11 06:19:02 PM PDT 24 22863805 ps
T186 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.706685047 Jul 11 06:18:42 PM PDT 24 Jul 11 06:18:46 PM PDT 24 538305353 ps
T882 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.76844931 Jul 11 06:18:38 PM PDT 24 Jul 11 06:18:41 PM PDT 24 55970359 ps
T883 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3375505807 Jul 11 06:18:58 PM PDT 24 Jul 11 06:19:02 PM PDT 24 58824663 ps
T884 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2538297681 Jul 11 06:19:08 PM PDT 24 Jul 11 06:19:19 PM PDT 24 766877505 ps
T123 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2904588672 Jul 11 06:19:16 PM PDT 24 Jul 11 06:19:21 PM PDT 24 105207375 ps
T885 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2830524647 Jul 11 06:18:55 PM PDT 24 Jul 11 06:18:58 PM PDT 24 248188515 ps
T164 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2715732836 Jul 11 06:19:24 PM PDT 24 Jul 11 06:19:27 PM PDT 24 18387274 ps
T886 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1280551614 Jul 11 06:19:17 PM PDT 24 Jul 11 06:19:21 PM PDT 24 17512645 ps
T887 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2249747875 Jul 11 06:19:24 PM PDT 24 Jul 11 06:19:28 PM PDT 24 42287010 ps
T888 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.350874021 Jul 11 06:18:32 PM PDT 24 Jul 11 06:18:34 PM PDT 24 251179180 ps
T889 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1850722834 Jul 11 06:18:49 PM PDT 24 Jul 11 06:19:00 PM PDT 24 3892518252 ps
T165 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1327599841 Jul 11 06:18:52 PM PDT 24 Jul 11 06:18:54 PM PDT 24 15298385 ps
T890 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3601122813 Jul 11 06:19:04 PM PDT 24 Jul 11 06:19:08 PM PDT 24 225722256 ps
T891 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2139115627 Jul 11 06:18:48 PM PDT 24 Jul 11 06:18:51 PM PDT 24 60753290 ps
T892 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2302979248 Jul 11 06:19:11 PM PDT 24 Jul 11 06:19:14 PM PDT 24 82516946 ps
T893 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2709769435 Jul 11 06:19:00 PM PDT 24 Jul 11 06:19:07 PM PDT 24 759823559 ps
T894 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1647541798 Jul 11 06:18:33 PM PDT 24 Jul 11 06:18:36 PM PDT 24 32036019 ps
T895 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4011911832 Jul 11 06:18:32 PM PDT 24 Jul 11 06:18:36 PM PDT 24 63484246 ps
T896 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.64736548 Jul 11 06:19:10 PM PDT 24 Jul 11 06:19:13 PM PDT 24 57650268 ps
T897 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.542206947 Jul 11 06:18:31 PM PDT 24 Jul 11 06:18:34 PM PDT 24 207661887 ps
T898 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2279869228 Jul 11 06:18:35 PM PDT 24 Jul 11 06:18:39 PM PDT 24 152802670 ps
T166 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3180578077 Jul 11 06:18:51 PM PDT 24 Jul 11 06:18:54 PM PDT 24 138055225 ps
T899 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3066625543 Jul 11 06:18:55 PM PDT 24 Jul 11 06:18:59 PM PDT 24 416953186 ps
T900 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1369148722 Jul 11 06:18:41 PM PDT 24 Jul 11 06:18:44 PM PDT 24 116124822 ps
T901 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3838050526 Jul 11 06:18:43 PM PDT 24 Jul 11 06:18:47 PM PDT 24 94818743 ps
T902 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3393869341 Jul 11 06:18:36 PM PDT 24 Jul 11 06:18:42 PM PDT 24 805954280 ps
T129 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.738740629 Jul 11 06:19:04 PM PDT 24 Jul 11 06:19:09 PM PDT 24 280383030 ps
T903 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1560686837 Jul 11 06:18:42 PM PDT 24 Jul 11 06:18:45 PM PDT 24 59958182 ps
T904 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.935643823 Jul 11 06:18:57 PM PDT 24 Jul 11 06:19:01 PM PDT 24 83590748 ps
T127 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2639898378 Jul 11 06:19:19 PM PDT 24 Jul 11 06:19:24 PM PDT 24 68864905 ps
T905 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.384628795 Jul 11 06:18:38 PM PDT 24 Jul 11 06:18:56 PM PDT 24 961474558 ps
T906 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3788852470 Jul 11 06:19:30 PM PDT 24 Jul 11 06:19:34 PM PDT 24 32936853 ps
T125 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3801889852 Jul 11 06:19:33 PM PDT 24 Jul 11 06:19:39 PM PDT 24 207341095 ps
T907 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1586688465 Jul 11 06:18:32 PM PDT 24 Jul 11 06:18:35 PM PDT 24 71674790 ps
T908 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2194799771 Jul 11 06:19:15 PM PDT 24 Jul 11 06:19:19 PM PDT 24 241875009 ps
T909 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2642566521 Jul 11 06:19:24 PM PDT 24 Jul 11 06:19:29 PM PDT 24 57434499 ps
T910 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.913013426 Jul 11 06:18:47 PM PDT 24 Jul 11 06:18:49 PM PDT 24 33844430 ps
T911 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.471389658 Jul 11 06:19:29 PM PDT 24 Jul 11 06:19:32 PM PDT 24 16491404 ps
T912 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1069645313 Jul 11 06:18:34 PM PDT 24 Jul 11 06:18:37 PM PDT 24 54545395 ps
T913 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.655321558 Jul 11 06:19:17 PM PDT 24 Jul 11 06:19:20 PM PDT 24 20919380 ps
T914 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1239436285 Jul 11 06:19:25 PM PDT 24 Jul 11 06:19:28 PM PDT 24 33735643 ps
T915 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3418908022 Jul 11 06:18:36 PM PDT 24 Jul 11 06:18:38 PM PDT 24 210557229 ps
T916 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2779230905 Jul 11 06:19:04 PM PDT 24 Jul 11 06:19:08 PM PDT 24 237655851 ps
T917 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2655479474 Jul 11 06:19:05 PM PDT 24 Jul 11 06:19:08 PM PDT 24 67051577 ps
T918 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1657428432 Jul 11 06:18:51 PM PDT 24 Jul 11 06:18:54 PM PDT 24 24970826 ps
T919 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.745984114 Jul 11 06:19:31 PM PDT 24 Jul 11 06:19:39 PM PDT 24 291019288 ps
T167 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3446082165 Jul 11 06:19:29 PM PDT 24 Jul 11 06:19:32 PM PDT 24 162818645 ps
T920 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1421970000 Jul 11 06:18:35 PM PDT 24 Jul 11 06:18:39 PM PDT 24 358372745 ps
T921 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3836724646 Jul 11 06:18:42 PM PDT 24 Jul 11 06:18:46 PM PDT 24 723263189 ps
T922 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3335705820 Jul 11 06:18:35 PM PDT 24 Jul 11 06:18:41 PM PDT 24 1021046359 ps
T923 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1756891933 Jul 11 06:18:36 PM PDT 24 Jul 11 06:18:39 PM PDT 24 124171413 ps
T924 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2562239759 Jul 11 06:19:05 PM PDT 24 Jul 11 06:19:08 PM PDT 24 94062530 ps
T925 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.407490724 Jul 11 06:19:13 PM PDT 24 Jul 11 06:19:43 PM PDT 24 2655728643 ps
T168 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.755576439 Jul 11 06:18:40 PM PDT 24 Jul 11 06:18:43 PM PDT 24 59565212 ps
T926 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4084757660 Jul 11 06:18:35 PM PDT 24 Jul 11 06:18:43 PM PDT 24 2428678774 ps
T927 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4171078332 Jul 11 06:18:29 PM PDT 24 Jul 11 06:18:31 PM PDT 24 124623300 ps
T928 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2747912586 Jul 11 06:18:55 PM PDT 24 Jul 11 06:18:58 PM PDT 24 29771855 ps
T929 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2027757795 Jul 11 06:19:05 PM PDT 24 Jul 11 06:19:10 PM PDT 24 384341315 ps
T930 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.321061871 Jul 11 06:18:44 PM PDT 24 Jul 11 06:18:47 PM PDT 24 79790769 ps
T931 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4134728283 Jul 11 06:18:40 PM PDT 24 Jul 11 06:18:43 PM PDT 24 580895365 ps
T932 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1750545069 Jul 11 06:19:16 PM PDT 24 Jul 11 06:19:20 PM PDT 24 102685204 ps
T933 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2092631045 Jul 11 06:19:32 PM PDT 24 Jul 11 06:19:37 PM PDT 24 94766545 ps
T934 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.416053123 Jul 11 06:18:54 PM PDT 24 Jul 11 06:18:56 PM PDT 24 21900766 ps
T935 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2649060309 Jul 11 06:19:16 PM PDT 24 Jul 11 06:19:20 PM PDT 24 24376959 ps
T936 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1414236316 Jul 11 06:19:10 PM PDT 24 Jul 11 06:19:16 PM PDT 24 219581595 ps
T937 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.771950410 Jul 11 06:19:16 PM PDT 24 Jul 11 06:19:19 PM PDT 24 72798928 ps
T938 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1368719653 Jul 11 06:18:42 PM PDT 24 Jul 11 06:18:50 PM PDT 24 1299829526 ps
T126 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1547097557 Jul 11 06:19:32 PM PDT 24 Jul 11 06:19:37 PM PDT 24 238538241 ps
T171 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.4047195101 Jul 11 06:18:45 PM PDT 24 Jul 11 06:18:48 PM PDT 24 22410477 ps
T939 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2888306131 Jul 11 06:18:58 PM PDT 24 Jul 11 06:19:19 PM PDT 24 698675397 ps
T940 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2657796030 Jul 11 06:19:12 PM PDT 24 Jul 11 06:19:33 PM PDT 24 1398754543 ps
T941 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4248906264 Jul 11 06:18:40 PM PDT 24 Jul 11 06:18:44 PM PDT 24 39073980 ps
T942 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4114758274 Jul 11 06:18:38 PM PDT 24 Jul 11 06:18:41 PM PDT 24 167528584 ps
T943 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3738873766 Jul 11 06:19:16 PM PDT 24 Jul 11 06:19:18 PM PDT 24 29764746 ps
T944 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.505537699 Jul 11 06:18:30 PM PDT 24 Jul 11 06:18:33 PM PDT 24 223148149 ps
T945 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3345899210 Jul 11 06:19:24 PM PDT 24 Jul 11 06:19:33 PM PDT 24 2459174761 ps
T946 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3763252206 Jul 11 06:19:04 PM PDT 24 Jul 11 06:19:08 PM PDT 24 26051718 ps
T947 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1402110093 Jul 11 06:19:21 PM PDT 24 Jul 11 06:19:26 PM PDT 24 345704423 ps
T130 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3492171730 Jul 11 06:19:28 PM PDT 24 Jul 11 06:19:31 PM PDT 24 229968055 ps
T948 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3125379164 Jul 11 06:19:20 PM PDT 24 Jul 11 06:19:24 PM PDT 24 22045670 ps
T949 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.809721835 Jul 11 06:19:33 PM PDT 24 Jul 11 06:19:37 PM PDT 24 75079992 ps
T950 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.520041036 Jul 11 06:19:43 PM PDT 24 Jul 11 06:19:47 PM PDT 24 18093072 ps
T951 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.59225136 Jul 11 06:18:41 PM PDT 24 Jul 11 06:18:59 PM PDT 24 694410378 ps
T952 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3967456080 Jul 11 06:19:11 PM PDT 24 Jul 11 06:19:15 PM PDT 24 243034201 ps
T953 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1423209710 Jul 11 06:19:14 PM PDT 24 Jul 11 06:19:27 PM PDT 24 947645098 ps
T169 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.118741351 Jul 11 06:19:23 PM PDT 24 Jul 11 06:19:26 PM PDT 24 15011978 ps
T170 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2384947259 Jul 11 06:19:26 PM PDT 24 Jul 11 06:19:29 PM PDT 24 68518925 ps
T954 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3780063093 Jul 11 06:18:54 PM PDT 24 Jul 11 06:19:01 PM PDT 24 4918318396 ps
T172 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.810689096 Jul 11 06:18:36 PM PDT 24 Jul 11 06:18:39 PM PDT 24 21003204 ps
T955 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2248255611 Jul 11 06:18:31 PM PDT 24 Jul 11 06:18:34 PM PDT 24 59088673 ps
T118 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1863991371 Jul 11 06:18:55 PM PDT 24 Jul 11 06:18:59 PM PDT 24 118175113 ps
T128 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1471108260 Jul 11 06:18:59 PM PDT 24 Jul 11 06:19:03 PM PDT 24 297036890 ps
T956 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1548418512 Jul 11 06:19:17 PM PDT 24 Jul 11 06:19:21 PM PDT 24 63555593 ps
T957 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.462475725 Jul 11 06:18:36 PM PDT 24 Jul 11 06:18:39 PM PDT 24 65496243 ps
T958 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.553382677 Jul 11 06:19:04 PM PDT 24 Jul 11 06:19:08 PM PDT 24 48003257 ps
T959 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.801857154 Jul 11 06:19:10 PM PDT 24 Jul 11 06:19:13 PM PDT 24 43857420 ps
T960 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1719991779 Jul 11 06:19:25 PM PDT 24 Jul 11 06:19:28 PM PDT 24 14010434 ps
T961 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3138973963 Jul 11 06:18:40 PM PDT 24 Jul 11 06:18:44 PM PDT 24 78044722 ps
T962 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3886560230 Jul 11 06:18:55 PM PDT 24 Jul 11 06:18:58 PM PDT 24 56869571 ps
T173 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.714924030 Jul 11 06:18:37 PM PDT 24 Jul 11 06:18:40 PM PDT 24 25245325 ps
T131 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.816114327 Jul 11 06:19:25 PM PDT 24 Jul 11 06:19:31 PM PDT 24 106178870 ps
T963 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4128917878 Jul 11 06:18:43 PM PDT 24 Jul 11 06:18:46 PM PDT 24 249571803 ps
T122 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2039671890 Jul 11 06:19:08 PM PDT 24 Jul 11 06:19:12 PM PDT 24 116262284 ps
T964 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2323695046 Jul 11 06:19:04 PM PDT 24 Jul 11 06:19:08 PM PDT 24 51826979 ps
T965 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2869360734 Jul 11 06:19:10 PM PDT 24 Jul 11 06:19:15 PM PDT 24 2129804432 ps
T966 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1064691122 Jul 11 06:19:10 PM PDT 24 Jul 11 06:19:13 PM PDT 24 12531025 ps
T967 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2395736092 Jul 11 06:18:48 PM PDT 24 Jul 11 06:18:55 PM PDT 24 2494831487 ps
T968 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2025836195 Jul 11 06:18:53 PM PDT 24 Jul 11 06:18:57 PM PDT 24 1065355225 ps
T969 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.910059799 Jul 11 06:18:47 PM PDT 24 Jul 11 06:18:50 PM PDT 24 40698640 ps
T970 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1584842477 Jul 11 06:18:49 PM PDT 24 Jul 11 06:18:51 PM PDT 24 18717614 ps
T971 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.392027709 Jul 11 06:19:24 PM PDT 24 Jul 11 06:19:27 PM PDT 24 105107604 ps
T972 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1482170635 Jul 11 06:18:47 PM PDT 24 Jul 11 06:18:50 PM PDT 24 151148638 ps
T973 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.179585379 Jul 11 06:18:57 PM PDT 24 Jul 11 06:19:00 PM PDT 24 109379646 ps
T974 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2682325884 Jul 11 06:19:16 PM PDT 24 Jul 11 06:19:19 PM PDT 24 93475261 ps
T174 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.380855647 Jul 11 06:18:44 PM PDT 24 Jul 11 06:18:47 PM PDT 24 23795730 ps
T975 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3658404617 Jul 11 06:19:32 PM PDT 24 Jul 11 06:19:37 PM PDT 24 19351995 ps
T976 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.417214782 Jul 11 06:18:32 PM PDT 24 Jul 11 06:19:15 PM PDT 24 23134156169 ps
T977 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1034245310 Jul 11 06:19:10 PM PDT 24 Jul 11 06:19:13 PM PDT 24 125124456 ps
T978 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.613417444 Jul 11 06:19:18 PM PDT 24 Jul 11 06:19:23 PM PDT 24 549086696 ps
T979 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1206136409 Jul 11 06:19:24 PM PDT 24 Jul 11 06:19:28 PM PDT 24 386968821 ps
T980 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.47744408 Jul 11 06:19:05 PM PDT 24 Jul 11 06:19:48 PM PDT 24 12326371263 ps
T981 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1378535420 Jul 11 06:18:48 PM PDT 24 Jul 11 06:18:50 PM PDT 24 74904811 ps
T982 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3980972394 Jul 11 06:19:10 PM PDT 24 Jul 11 06:19:13 PM PDT 24 67209107 ps
T983 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4104017427 Jul 11 06:18:39 PM PDT 24 Jul 11 06:18:52 PM PDT 24 1922737279 ps
T984 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1262702940 Jul 11 06:18:46 PM PDT 24 Jul 11 06:18:49 PM PDT 24 581216863 ps
T985 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1027035212 Jul 11 06:19:33 PM PDT 24 Jul 11 06:19:37 PM PDT 24 23307989 ps
T986 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.296481291 Jul 11 06:18:30 PM PDT 24 Jul 11 06:18:33 PM PDT 24 105348099 ps
T987 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.624290347 Jul 11 06:18:57 PM PDT 24 Jul 11 06:19:01 PM PDT 24 71136136 ps
T988 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.762446364 Jul 11 06:19:31 PM PDT 24 Jul 11 06:19:36 PM PDT 24 36821225 ps
T989 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.85430661 Jul 11 06:18:49 PM PDT 24 Jul 11 06:18:51 PM PDT 24 44291339 ps
T990 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1409567928 Jul 11 06:19:31 PM PDT 24 Jul 11 06:19:35 PM PDT 24 45843147 ps
T991 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1139923211 Jul 11 06:18:45 PM PDT 24 Jul 11 06:18:49 PM PDT 24 83357845 ps

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2022135880
Short name T1
Test name
Test status
Simulation time 167511937240 ps
CPU time 2260.9 seconds
Started Jul 11 06:20:55 PM PDT 24
Finished Jul 11 06:58:40 PM PDT 24
Peak memory 926400 kb
Host smart-1e613155-27ef-423b-b872-6e6a7b52b0ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2022135880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.2022135880
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2002066624
Short name T15
Test name
Test status
Simulation time 3098296339 ps
CPU time 10.08 seconds
Started Jul 11 06:21:54 PM PDT 24
Finished Jul 11 06:22:08 PM PDT 24
Peak memory 225420 kb
Host smart-799369b4-4ce5-4a66-aec2-28c74f01bc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002066624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2002066624
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.582923038
Short name T11
Test name
Test status
Simulation time 2013078516 ps
CPU time 16.97 seconds
Started Jul 11 06:20:51 PM PDT 24
Finished Jul 11 06:21:12 PM PDT 24
Peak memory 225576 kb
Host smart-1c9a40f8-d59c-41df-b51f-30b671bd97c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582923038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.582923038
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3712972737
Short name T27
Test name
Test status
Simulation time 90767511 ps
CPU time 0.78 seconds
Started Jul 11 06:21:16 PM PDT 24
Finished Jul 11 06:21:21 PM PDT 24
Peak memory 208436 kb
Host smart-e4ed0b9c-2441-410d-ab42-2167a8e124af
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712972737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.3712972737
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.580217928
Short name T46
Test name
Test status
Simulation time 236349647 ps
CPU time 40.37 seconds
Started Jul 11 06:20:12 PM PDT 24
Finished Jul 11 06:20:54 PM PDT 24
Peak memory 282160 kb
Host smart-ed717310-f9dc-4ca0-afba-a85d863c106b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580217928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.580217928
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.4165605374
Short name T143
Test name
Test status
Simulation time 26583301432 ps
CPU time 275 seconds
Started Jul 11 06:20:51 PM PDT 24
Finished Jul 11 06:25:29 PM PDT 24
Peak memory 283480 kb
Host smart-3e5557d6-f660-430f-9606-70f84ccfcf23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4165605374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.4165605374
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3597232992
Short name T6
Test name
Test status
Simulation time 2483042773 ps
CPU time 7.35 seconds
Started Jul 11 06:22:17 PM PDT 24
Finished Jul 11 06:22:28 PM PDT 24
Peak memory 217116 kb
Host smart-b2e18563-dc4f-424c-90c6-a97535b84f31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597232992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3597232992
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.133087735
Short name T41
Test name
Test status
Simulation time 1515795901 ps
CPU time 9.61 seconds
Started Jul 11 06:22:23 PM PDT 24
Finished Jul 11 06:22:41 PM PDT 24
Peak memory 225588 kb
Host smart-d9bef53f-41c0-4f29-82aa-4df1dbc1e70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133087735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.133087735
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2431466515
Short name T106
Test name
Test status
Simulation time 59699991 ps
CPU time 2.56 seconds
Started Jul 11 06:19:17 PM PDT 24
Finished Jul 11 06:19:22 PM PDT 24
Peak memory 217696 kb
Host smart-bd1afa6e-8d2e-4d79-a072-1e733b530b85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431466515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2431466515
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.399095633
Short name T149
Test name
Test status
Simulation time 383964446 ps
CPU time 1.9 seconds
Started Jul 11 06:18:34 PM PDT 24
Finished Jul 11 06:18:38 PM PDT 24
Peak memory 217780 kb
Host smart-70c1730e-2180-4561-8bc6-cb9408da5344
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399095
633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.399095633
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2731927218
Short name T54
Test name
Test status
Simulation time 321160629 ps
CPU time 9.49 seconds
Started Jul 11 06:20:58 PM PDT 24
Finished Jul 11 06:21:11 PM PDT 24
Peak memory 217672 kb
Host smart-9bcd25dc-9cac-4581-8418-dcf716b0c992
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731927218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2731927218
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3798704330
Short name T162
Test name
Test status
Simulation time 43725659 ps
CPU time 0.93 seconds
Started Jul 11 06:18:31 PM PDT 24
Finished Jul 11 06:18:34 PM PDT 24
Peak memory 209732 kb
Host smart-1088fb7b-50f1-43f4-bae7-e7264088e4f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798704330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3798704330
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1633975557
Short name T85
Test name
Test status
Simulation time 167012441 ps
CPU time 1.01 seconds
Started Jul 11 06:21:14 PM PDT 24
Finished Jul 11 06:21:19 PM PDT 24
Peak memory 208588 kb
Host smart-c4dd56a1-698e-4af5-824c-259c4f5b856d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633975557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1633975557
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.564690988
Short name T109
Test name
Test status
Simulation time 48287541 ps
CPU time 3.48 seconds
Started Jul 11 06:19:30 PM PDT 24
Finished Jul 11 06:19:35 PM PDT 24
Peak memory 218132 kb
Host smart-3fd99725-477d-475f-bd1a-3bd9601bac46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564690988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.564690988
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1863991371
Short name T118
Test name
Test status
Simulation time 118175113 ps
CPU time 3.5 seconds
Started Jul 11 06:18:55 PM PDT 24
Finished Jul 11 06:18:59 PM PDT 24
Peak memory 222372 kb
Host smart-5b7a59a0-b12d-467d-a221-cc3563079c58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863991371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1863991371
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.4283190425
Short name T12
Test name
Test status
Simulation time 36146009866 ps
CPU time 289.47 seconds
Started Jul 11 06:21:36 PM PDT 24
Finished Jul 11 06:26:28 PM PDT 24
Peak memory 269612 kb
Host smart-cfe95896-429f-4e9a-bba7-77d85bf8ab1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4283190425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.4283190425
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1158834893
Short name T117
Test name
Test status
Simulation time 139243849 ps
CPU time 2.94 seconds
Started Jul 11 06:18:42 PM PDT 24
Finished Jul 11 06:18:47 PM PDT 24
Peak memory 221960 kb
Host smart-89554ad5-e296-45cf-8b6f-4602a04a8fb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158834893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1158834893
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.738740629
Short name T129
Test name
Test status
Simulation time 280383030 ps
CPU time 3.04 seconds
Started Jul 11 06:19:04 PM PDT 24
Finished Jul 11 06:19:09 PM PDT 24
Peak memory 222372 kb
Host smart-89ab86c9-bb94-428c-893f-77da91469f23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738740629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.738740629
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1427521207
Short name T9
Test name
Test status
Simulation time 55300802 ps
CPU time 7.54 seconds
Started Jul 11 06:21:05 PM PDT 24
Finished Jul 11 06:21:18 PM PDT 24
Peak memory 250472 kb
Host smart-bfd7a728-2fb5-4fb1-b6d7-5623e8936152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427521207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1427521207
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3593059396
Short name T103
Test name
Test status
Simulation time 723664028678 ps
CPU time 1948.24 seconds
Started Jul 11 06:22:30 PM PDT 24
Finished Jul 11 06:55:05 PM PDT 24
Peak memory 578384 kb
Host smart-51523d61-04e7-46cd-8687-031c7a783e00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3593059396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.3593059396
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3801889852
Short name T125
Test name
Test status
Simulation time 207341095 ps
CPU time 2.38 seconds
Started Jul 11 06:19:33 PM PDT 24
Finished Jul 11 06:19:39 PM PDT 24
Peak memory 217472 kb
Host smart-c26cbfae-e6fe-447e-bdc2-fe99f310c50b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801889852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3801889852
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.572104900
Short name T182
Test name
Test status
Simulation time 12075504 ps
CPU time 0.82 seconds
Started Jul 11 06:18:31 PM PDT 24
Finished Jul 11 06:18:33 PM PDT 24
Peak memory 209196 kb
Host smart-6446d527-e0c5-4663-a1e6-d461fb7c3b39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572104900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.572104900
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.2499289243
Short name T37
Test name
Test status
Simulation time 146467462663 ps
CPU time 660.64 seconds
Started Jul 11 06:21:38 PM PDT 24
Finished Jul 11 06:32:42 PM PDT 24
Peak memory 316216 kb
Host smart-3a843aeb-21a1-4afc-95a8-cad27e2dd587
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2499289243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.2499289243
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2715453437
Short name T115
Test name
Test status
Simulation time 226805511 ps
CPU time 2.85 seconds
Started Jul 11 06:19:17 PM PDT 24
Finished Jul 11 06:19:23 PM PDT 24
Peak memory 222076 kb
Host smart-b2c09182-3c02-4958-8b3b-4eae2bcc9dd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715453437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2715453437
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2904588672
Short name T123
Test name
Test status
Simulation time 105207375 ps
CPU time 4.13 seconds
Started Jul 11 06:19:16 PM PDT 24
Finished Jul 11 06:19:21 PM PDT 24
Peak memory 217496 kb
Host smart-98d0d414-73ac-438c-bafc-940039feeb53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904588672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2904588672
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1547097557
Short name T126
Test name
Test status
Simulation time 238538241 ps
CPU time 1.96 seconds
Started Jul 11 06:19:32 PM PDT 24
Finished Jul 11 06:19:37 PM PDT 24
Peak memory 221988 kb
Host smart-5109a1ac-f43c-4884-abeb-da229d098b4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547097557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1547097557
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.4272269602
Short name T157
Test name
Test status
Simulation time 46877075 ps
CPU time 0.84 seconds
Started Jul 11 06:20:02 PM PDT 24
Finished Jul 11 06:20:05 PM PDT 24
Peak memory 208304 kb
Host smart-33e9a60a-dcdf-4e59-ad4b-a0e7eae0f908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272269602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.4272269602
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1571566370
Short name T185
Test name
Test status
Simulation time 29324770 ps
CPU time 0.86 seconds
Started Jul 11 06:20:16 PM PDT 24
Finished Jul 11 06:20:19 PM PDT 24
Peak memory 208428 kb
Host smart-5b9c617c-fb91-4e44-9f88-cb8ba3969bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571566370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1571566370
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1882336587
Short name T97
Test name
Test status
Simulation time 35868831 ps
CPU time 0.8 seconds
Started Jul 11 06:20:19 PM PDT 24
Finished Jul 11 06:20:21 PM PDT 24
Peak memory 208488 kb
Host smart-b215e1fc-195e-40e3-bea7-db84b54c3a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882336587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1882336587
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1843102758
Short name T184
Test name
Test status
Simulation time 23621378 ps
CPU time 0.91 seconds
Started Jul 11 06:20:24 PM PDT 24
Finished Jul 11 06:20:27 PM PDT 24
Peak memory 208528 kb
Host smart-4eec4fba-4da2-4b02-b2a9-241fcc5203d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843102758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1843102758
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.810102282
Short name T55
Test name
Test status
Simulation time 320379684 ps
CPU time 15.06 seconds
Started Jul 11 06:21:47 PM PDT 24
Finished Jul 11 06:22:04 PM PDT 24
Peak memory 219420 kb
Host smart-75089846-6353-4328-b49b-ab750b30489d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810102282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.810102282
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1444923857
Short name T135
Test name
Test status
Simulation time 1758950459 ps
CPU time 19.23 seconds
Started Jul 11 06:18:30 PM PDT 24
Finished Jul 11 06:18:50 PM PDT 24
Peak memory 217124 kb
Host smart-3f120f01-db4d-434d-bd43-fd7dea89debd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444923857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1444923857
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.189717105
Short name T110
Test name
Test status
Simulation time 241151956 ps
CPU time 2.49 seconds
Started Jul 11 06:19:25 PM PDT 24
Finished Jul 11 06:19:29 PM PDT 24
Peak memory 217516 kb
Host smart-4cbdf5bb-2436-4ea3-af84-5ab4bc013d34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189717105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_
err.189717105
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1372795271
Short name T120
Test name
Test status
Simulation time 300790257 ps
CPU time 1.91 seconds
Started Jul 11 06:19:31 PM PDT 24
Finished Jul 11 06:19:37 PM PDT 24
Peak memory 217476 kb
Host smart-ff90bf16-b177-4416-a5c9-b10a2afc8fc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372795271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1372795271
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3352690225
Short name T114
Test name
Test status
Simulation time 230741991 ps
CPU time 2.99 seconds
Started Jul 11 06:19:03 PM PDT 24
Finished Jul 11 06:19:07 PM PDT 24
Peak memory 222148 kb
Host smart-2b71e364-9b05-4193-9a48-46e4c14bce69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352690225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.3352690225
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2039671890
Short name T122
Test name
Test status
Simulation time 116262284 ps
CPU time 2.85 seconds
Started Jul 11 06:19:08 PM PDT 24
Finished Jul 11 06:19:12 PM PDT 24
Peak memory 221988 kb
Host smart-09828829-cd78-4ff3-a4b6-658e07ef4d96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039671890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2039671890
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2896380075
Short name T39
Test name
Test status
Simulation time 1013407000 ps
CPU time 11.02 seconds
Started Jul 11 06:20:07 PM PDT 24
Finished Jul 11 06:20:20 PM PDT 24
Peak memory 217796 kb
Host smart-14eb774f-3c25-46f7-9149-11ad7445dc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896380075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2896380075
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3799243818
Short name T57
Test name
Test status
Simulation time 53774215 ps
CPU time 2.56 seconds
Started Jul 11 06:21:29 PM PDT 24
Finished Jul 11 06:21:34 PM PDT 24
Peak memory 213832 kb
Host smart-21ab308e-2e85-494c-9023-1982aafd8084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799243818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3799243818
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1586688465
Short name T907
Test name
Test status
Simulation time 71674790 ps
CPU time 1.1 seconds
Started Jul 11 06:18:32 PM PDT 24
Finished Jul 11 06:18:35 PM PDT 24
Peak memory 209368 kb
Host smart-831dd02a-76df-46f8-b8a3-cf1f95b2e41d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586688465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1586688465
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.350874021
Short name T888
Test name
Test status
Simulation time 251179180 ps
CPU time 1.29 seconds
Started Jul 11 06:18:32 PM PDT 24
Finished Jul 11 06:18:34 PM PDT 24
Peak memory 209304 kb
Host smart-c793d5eb-f3d8-4525-ac8c-0f501347223c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350874021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash
.350874021
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3418908022
Short name T915
Test name
Test status
Simulation time 210557229 ps
CPU time 0.93 seconds
Started Jul 11 06:18:36 PM PDT 24
Finished Jul 11 06:18:38 PM PDT 24
Peak memory 217492 kb
Host smart-a2a084dc-65ba-4e43-af2b-415330485256
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418908022 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3418908022
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1647541798
Short name T894
Test name
Test status
Simulation time 32036019 ps
CPU time 1.47 seconds
Started Jul 11 06:18:33 PM PDT 24
Finished Jul 11 06:18:36 PM PDT 24
Peak memory 209284 kb
Host smart-0db60f39-8152-4c25-9012-1707527c6dd1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647541798 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1647541798
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.417214782
Short name T976
Test name
Test status
Simulation time 23134156169 ps
CPU time 41.03 seconds
Started Jul 11 06:18:32 PM PDT 24
Finished Jul 11 06:19:15 PM PDT 24
Peak memory 209320 kb
Host smart-760cc566-0a22-41fc-bdb8-c9f3d386a99c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417214782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.417214782
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.505537699
Short name T944
Test name
Test status
Simulation time 223148149 ps
CPU time 1.75 seconds
Started Jul 11 06:18:30 PM PDT 24
Finished Jul 11 06:18:33 PM PDT 24
Peak memory 217436 kb
Host smart-c0e5f9d6-09f0-4588-9080-899eecbc0441
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505537699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.505537699
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2248255611
Short name T955
Test name
Test status
Simulation time 59088673 ps
CPU time 1.67 seconds
Started Jul 11 06:18:31 PM PDT 24
Finished Jul 11 06:18:34 PM PDT 24
Peak memory 217668 kb
Host smart-2ad01581-c6af-481c-adbf-cb8ae2e88cdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224825
5611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2248255611
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4011911832
Short name T895
Test name
Test status
Simulation time 63484246 ps
CPU time 2.28 seconds
Started Jul 11 06:18:32 PM PDT 24
Finished Jul 11 06:18:36 PM PDT 24
Peak memory 209236 kb
Host smart-c67057e4-9472-4b67-8d0a-e5de5099d5d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011911832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.4011911832
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.296481291
Short name T986
Test name
Test status
Simulation time 105348099 ps
CPU time 1.42 seconds
Started Jul 11 06:18:30 PM PDT 24
Finished Jul 11 06:18:33 PM PDT 24
Peak memory 209424 kb
Host smart-a1f1a38f-41ad-42a4-aff1-15de67b790a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296481291 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.296481291
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4171078332
Short name T927
Test name
Test status
Simulation time 124623300 ps
CPU time 0.97 seconds
Started Jul 11 06:18:29 PM PDT 24
Finished Jul 11 06:18:31 PM PDT 24
Peak memory 217504 kb
Host smart-58c9a5ba-8cb0-4b58-a732-40f9418c959a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171078332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.4171078332
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.542206947
Short name T897
Test name
Test status
Simulation time 207661887 ps
CPU time 2.35 seconds
Started Jul 11 06:18:31 PM PDT 24
Finished Jul 11 06:18:34 PM PDT 24
Peak memory 217516 kb
Host smart-d300ea00-7d1f-4a9f-a492-2ef15f4554f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542206947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.542206947
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.4005856981
Short name T124
Test name
Test status
Simulation time 56328282 ps
CPU time 2.09 seconds
Started Jul 11 06:18:33 PM PDT 24
Finished Jul 11 06:18:36 PM PDT 24
Peak memory 222120 kb
Host smart-3b3fe299-d86b-4689-b549-9f9c86b6d269
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005856981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.4005856981
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.714924030
Short name T173
Test name
Test status
Simulation time 25245325 ps
CPU time 1.33 seconds
Started Jul 11 06:18:37 PM PDT 24
Finished Jul 11 06:18:40 PM PDT 24
Peak memory 209316 kb
Host smart-cf19a03e-491a-4e61-9c22-cde83b7f4007
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714924030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.714924030
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3236720113
Short name T878
Test name
Test status
Simulation time 570953032 ps
CPU time 1.29 seconds
Started Jul 11 06:18:35 PM PDT 24
Finished Jul 11 06:18:38 PM PDT 24
Peak memory 209196 kb
Host smart-ad8a2fdd-1d89-42cf-a2d6-141615c0a25c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236720113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3236720113
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.810689096
Short name T172
Test name
Test status
Simulation time 21003204 ps
CPU time 1.3 seconds
Started Jul 11 06:18:36 PM PDT 24
Finished Jul 11 06:18:39 PM PDT 24
Peak memory 217960 kb
Host smart-fc5027da-87f6-4b98-95de-6da1ad18f8e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810689096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.810689096
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1210191324
Short name T870
Test name
Test status
Simulation time 149396824 ps
CPU time 1.37 seconds
Started Jul 11 06:18:34 PM PDT 24
Finished Jul 11 06:18:38 PM PDT 24
Peak memory 219300 kb
Host smart-bf928002-d1f0-4ebc-aa95-fffb4899d7b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210191324 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1210191324
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1560686837
Short name T903
Test name
Test status
Simulation time 59958182 ps
CPU time 1.05 seconds
Started Jul 11 06:18:42 PM PDT 24
Finished Jul 11 06:18:45 PM PDT 24
Peak memory 209128 kb
Host smart-2345c645-6c2f-4acf-82b6-06f0d6fd2a05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560686837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1560686837
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3376991282
Short name T872
Test name
Test status
Simulation time 63711741 ps
CPU time 2.19 seconds
Started Jul 11 06:18:42 PM PDT 24
Finished Jul 11 06:18:45 PM PDT 24
Peak memory 208708 kb
Host smart-254e6dff-455c-4db5-8b08-9085f4c3bf11
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376991282 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.3376991282
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3393869341
Short name T902
Test name
Test status
Simulation time 805954280 ps
CPU time 4.92 seconds
Started Jul 11 06:18:36 PM PDT 24
Finished Jul 11 06:18:42 PM PDT 24
Peak memory 217112 kb
Host smart-1967008e-9d49-4249-ac9b-62549d2b4cab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393869341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3393869341
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4084757660
Short name T926
Test name
Test status
Simulation time 2428678774 ps
CPU time 6.51 seconds
Started Jul 11 06:18:35 PM PDT 24
Finished Jul 11 06:18:43 PM PDT 24
Peak memory 209240 kb
Host smart-3bc3dbd1-44ef-4810-9a7a-9a6bae406267
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084757660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.4084757660
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1756891933
Short name T923
Test name
Test status
Simulation time 124171413 ps
CPU time 1.39 seconds
Started Jul 11 06:18:36 PM PDT 24
Finished Jul 11 06:18:39 PM PDT 24
Peak memory 210648 kb
Host smart-aed8c9d5-15c0-46b3-878f-94b4a0a90e3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756891933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1756891933
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3836724646
Short name T921
Test name
Test status
Simulation time 723263189 ps
CPU time 2.06 seconds
Started Jul 11 06:18:42 PM PDT 24
Finished Jul 11 06:18:46 PM PDT 24
Peak memory 209208 kb
Host smart-8008434c-fb07-49a4-a167-337c0899426c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836724646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3836724646
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3194091313
Short name T880
Test name
Test status
Simulation time 148192340 ps
CPU time 1.42 seconds
Started Jul 11 06:18:38 PM PDT 24
Finished Jul 11 06:18:41 PM PDT 24
Peak memory 209268 kb
Host smart-714732e0-edc5-428b-a609-48af05f6548c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194091313 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3194091313
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.462475725
Short name T957
Test name
Test status
Simulation time 65496243 ps
CPU time 1 seconds
Started Jul 11 06:18:36 PM PDT 24
Finished Jul 11 06:18:39 PM PDT 24
Peak memory 209296 kb
Host smart-42da54ea-828f-4ee9-9861-aff86922f3f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462475725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.462475725
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3160986082
Short name T119
Test name
Test status
Simulation time 96105452 ps
CPU time 3.59 seconds
Started Jul 11 06:18:37 PM PDT 24
Finished Jul 11 06:18:42 PM PDT 24
Peak memory 217604 kb
Host smart-a0205282-7531-4a5d-b197-ff5eec1f257f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160986082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3160986082
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1421970000
Short name T920
Test name
Test status
Simulation time 358372745 ps
CPU time 2.15 seconds
Started Jul 11 06:18:35 PM PDT 24
Finished Jul 11 06:18:39 PM PDT 24
Peak memory 222316 kb
Host smart-62b7cd20-7ce5-426d-9ffc-638c7ad1f014
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421970000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1421970000
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.566601297
Short name T868
Test name
Test status
Simulation time 50348537 ps
CPU time 2.02 seconds
Started Jul 11 06:19:15 PM PDT 24
Finished Jul 11 06:19:18 PM PDT 24
Peak memory 218848 kb
Host smart-cfd67baf-c70b-4a38-a464-4101476a6a51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566601297 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.566601297
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1719991779
Short name T960
Test name
Test status
Simulation time 14010434 ps
CPU time 0.85 seconds
Started Jul 11 06:19:25 PM PDT 24
Finished Jul 11 06:19:28 PM PDT 24
Peak memory 209124 kb
Host smart-438c11d6-1659-4b2e-92a3-26c078294aba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719991779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1719991779
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2682325884
Short name T974
Test name
Test status
Simulation time 93475261 ps
CPU time 1.21 seconds
Started Jul 11 06:19:16 PM PDT 24
Finished Jul 11 06:19:19 PM PDT 24
Peak memory 209320 kb
Host smart-5cd26322-c5d3-4a8a-a01a-7ace95613f29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682325884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2682325884
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1832947518
Short name T874
Test name
Test status
Simulation time 117802750 ps
CPU time 5.24 seconds
Started Jul 11 06:19:17 PM PDT 24
Finished Jul 11 06:19:25 PM PDT 24
Peak memory 217512 kb
Host smart-577748dc-a2be-4ec1-918f-32a9d814abd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832947518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1832947518
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2639898378
Short name T127
Test name
Test status
Simulation time 68864905 ps
CPU time 2.54 seconds
Started Jul 11 06:19:19 PM PDT 24
Finished Jul 11 06:19:24 PM PDT 24
Peak memory 217408 kb
Host smart-84739ffa-6076-4297-be49-ffd54e7c726b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639898378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2639898378
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2649060309
Short name T935
Test name
Test status
Simulation time 24376959 ps
CPU time 1.14 seconds
Started Jul 11 06:19:16 PM PDT 24
Finished Jul 11 06:19:20 PM PDT 24
Peak memory 221940 kb
Host smart-3f32f17d-5218-409a-a65b-f7b1130c52a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649060309 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2649060309
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1280551614
Short name T886
Test name
Test status
Simulation time 17512645 ps
CPU time 0.91 seconds
Started Jul 11 06:19:17 PM PDT 24
Finished Jul 11 06:19:21 PM PDT 24
Peak memory 209300 kb
Host smart-b287bc11-e2da-4c78-ba3d-282f9a60a708
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280551614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1280551614
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.771950410
Short name T937
Test name
Test status
Simulation time 72798928 ps
CPU time 1.35 seconds
Started Jul 11 06:19:16 PM PDT 24
Finished Jul 11 06:19:19 PM PDT 24
Peak memory 209304 kb
Host smart-ce1a40f7-6c41-4374-a355-60f506d2df57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771950410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.771950410
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3683121105
Short name T121
Test name
Test status
Simulation time 73895831 ps
CPU time 1.51 seconds
Started Jul 11 06:19:17 PM PDT 24
Finished Jul 11 06:19:21 PM PDT 24
Peak memory 218536 kb
Host smart-f3c1e3d7-d849-4b56-9a1d-8ebd1f729ad9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683121105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3683121105
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.655321558
Short name T913
Test name
Test status
Simulation time 20919380 ps
CPU time 1.15 seconds
Started Jul 11 06:19:17 PM PDT 24
Finished Jul 11 06:19:20 PM PDT 24
Peak memory 220044 kb
Host smart-ba11a2c3-4444-4bf4-a4fd-6c0d1ac91869
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655321558 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.655321558
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1466178602
Short name T876
Test name
Test status
Simulation time 51341722 ps
CPU time 1 seconds
Started Jul 11 06:19:16 PM PDT 24
Finished Jul 11 06:19:20 PM PDT 24
Peak memory 209280 kb
Host smart-99a44ebb-64c8-4a5d-ab18-2bf66044f1d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466178602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1466178602
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2539776124
Short name T181
Test name
Test status
Simulation time 105332171 ps
CPU time 2.26 seconds
Started Jul 11 06:19:19 PM PDT 24
Finished Jul 11 06:19:24 PM PDT 24
Peak memory 217488 kb
Host smart-73c800db-f38e-4cc6-bc54-8a334c81a083
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539776124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.2539776124
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2194799771
Short name T908
Test name
Test status
Simulation time 241875009 ps
CPU time 2.65 seconds
Started Jul 11 06:19:15 PM PDT 24
Finished Jul 11 06:19:19 PM PDT 24
Peak memory 217512 kb
Host smart-58a04ebb-6a83-42d1-8bda-2e82ced26520
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194799771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2194799771
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.520041036
Short name T950
Test name
Test status
Simulation time 18093072 ps
CPU time 1.44 seconds
Started Jul 11 06:19:43 PM PDT 24
Finished Jul 11 06:19:47 PM PDT 24
Peak memory 217668 kb
Host smart-c29b70cc-b8e4-40ea-a1e0-00b452aaf3d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520041036 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.520041036
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1239436285
Short name T914
Test name
Test status
Simulation time 33735643 ps
CPU time 0.92 seconds
Started Jul 11 06:19:25 PM PDT 24
Finished Jul 11 06:19:28 PM PDT 24
Peak memory 208840 kb
Host smart-a80972fd-a663-4f86-b4f1-547f97237041
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239436285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1239436285
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.471389658
Short name T911
Test name
Test status
Simulation time 16491404 ps
CPU time 1.19 seconds
Started Jul 11 06:19:29 PM PDT 24
Finished Jul 11 06:19:32 PM PDT 24
Peak memory 209304 kb
Host smart-b23e8aad-518a-4976-ab56-0ca6379f0675
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471389658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.471389658
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.613417444
Short name T978
Test name
Test status
Simulation time 549086696 ps
CPU time 2.71 seconds
Started Jul 11 06:19:18 PM PDT 24
Finished Jul 11 06:19:23 PM PDT 24
Peak memory 217512 kb
Host smart-d03d53e0-a104-4b39-aa1e-85480a848527
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613417444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.613417444
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3788852470
Short name T906
Test name
Test status
Simulation time 32936853 ps
CPU time 2.33 seconds
Started Jul 11 06:19:30 PM PDT 24
Finished Jul 11 06:19:34 PM PDT 24
Peak memory 223176 kb
Host smart-e72db15a-c95a-4070-861f-6926f0c70b3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788852470 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3788852470
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1674502626
Short name T879
Test name
Test status
Simulation time 45492955 ps
CPU time 0.96 seconds
Started Jul 11 06:19:36 PM PDT 24
Finished Jul 11 06:19:39 PM PDT 24
Peak memory 209308 kb
Host smart-8305173f-a664-4c3b-bdc7-6f7de99af459
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674502626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1674502626
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1401789763
Short name T146
Test name
Test status
Simulation time 31862261 ps
CPU time 1.46 seconds
Started Jul 11 06:19:27 PM PDT 24
Finished Jul 11 06:19:30 PM PDT 24
Peak memory 209272 kb
Host smart-0014299a-4983-4e50-9561-651b1e43ff0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401789763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.1401789763
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.329872267
Short name T107
Test name
Test status
Simulation time 1557159630 ps
CPU time 4.15 seconds
Started Jul 11 06:19:29 PM PDT 24
Finished Jul 11 06:19:35 PM PDT 24
Peak memory 217928 kb
Host smart-14dacfa4-f830-48a4-95bb-819dd4c3e0b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329872267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.329872267
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2038971153
Short name T105
Test name
Test status
Simulation time 45871425 ps
CPU time 1.86 seconds
Started Jul 11 06:19:45 PM PDT 24
Finished Jul 11 06:19:49 PM PDT 24
Peak memory 222224 kb
Host smart-945ed7e7-4deb-42d0-8675-a9f29d3a607d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038971153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2038971153
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.809721835
Short name T949
Test name
Test status
Simulation time 75079992 ps
CPU time 1.09 seconds
Started Jul 11 06:19:33 PM PDT 24
Finished Jul 11 06:19:37 PM PDT 24
Peak memory 217556 kb
Host smart-7de41252-2f12-4093-881d-916d02da2050
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809721835 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.809721835
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.118741351
Short name T169
Test name
Test status
Simulation time 15011978 ps
CPU time 0.86 seconds
Started Jul 11 06:19:23 PM PDT 24
Finished Jul 11 06:19:26 PM PDT 24
Peak memory 209240 kb
Host smart-23fde1ee-bbb5-4319-8f56-32269fed89b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118741351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.118741351
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.762446364
Short name T988
Test name
Test status
Simulation time 36821225 ps
CPU time 1.32 seconds
Started Jul 11 06:19:31 PM PDT 24
Finished Jul 11 06:19:36 PM PDT 24
Peak memory 209316 kb
Host smart-40ef3ede-6034-4131-886f-ce55c44a7bc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762446364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.762446364
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1812477917
Short name T113
Test name
Test status
Simulation time 73317265 ps
CPU time 2.69 seconds
Started Jul 11 06:19:33 PM PDT 24
Finished Jul 11 06:19:39 PM PDT 24
Peak memory 217532 kb
Host smart-aaa99bd6-a3be-44fa-80b5-1a60f14e4404
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812477917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1812477917
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.392027709
Short name T971
Test name
Test status
Simulation time 105107604 ps
CPU time 1.41 seconds
Started Jul 11 06:19:24 PM PDT 24
Finished Jul 11 06:19:27 PM PDT 24
Peak memory 219196 kb
Host smart-f9b3b276-2c16-40fd-91cc-9ecbec3a8da5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392027709 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.392027709
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1955422196
Short name T179
Test name
Test status
Simulation time 27342259 ps
CPU time 1 seconds
Started Jul 11 06:19:38 PM PDT 24
Finished Jul 11 06:19:40 PM PDT 24
Peak memory 209052 kb
Host smart-a8ea88e7-727a-428e-a0ec-bc74b60176fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955422196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1955422196
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2092631045
Short name T933
Test name
Test status
Simulation time 94766545 ps
CPU time 1.32 seconds
Started Jul 11 06:19:32 PM PDT 24
Finished Jul 11 06:19:37 PM PDT 24
Peak memory 209308 kb
Host smart-446a23e6-c80c-4fac-92ef-2436e7e84cd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092631045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2092631045
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3492171730
Short name T130
Test name
Test status
Simulation time 229968055 ps
CPU time 2.05 seconds
Started Jul 11 06:19:28 PM PDT 24
Finished Jul 11 06:19:31 PM PDT 24
Peak memory 222064 kb
Host smart-d820569a-7441-4613-a4f0-d33fdd6da6b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492171730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.3492171730
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.525592004
Short name T148
Test name
Test status
Simulation time 22223352 ps
CPU time 1.61 seconds
Started Jul 11 06:19:31 PM PDT 24
Finished Jul 11 06:19:35 PM PDT 24
Peak memory 218756 kb
Host smart-468a4175-45d3-4062-8377-23defedca780
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525592004 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.525592004
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2384947259
Short name T170
Test name
Test status
Simulation time 68518925 ps
CPU time 0.94 seconds
Started Jul 11 06:19:26 PM PDT 24
Finished Jul 11 06:19:29 PM PDT 24
Peak memory 209188 kb
Host smart-32165ba7-957a-4b51-92dd-e39b93e0ad0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384947259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2384947259
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3092007252
Short name T175
Test name
Test status
Simulation time 17295764 ps
CPU time 1.16 seconds
Started Jul 11 06:19:27 PM PDT 24
Finished Jul 11 06:19:29 PM PDT 24
Peak memory 209228 kb
Host smart-a9777f28-c13c-47e9-ae38-d075b8115586
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092007252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3092007252
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.745984114
Short name T919
Test name
Test status
Simulation time 291019288 ps
CPU time 3.79 seconds
Started Jul 11 06:19:31 PM PDT 24
Finished Jul 11 06:19:39 PM PDT 24
Peak memory 217356 kb
Host smart-78d1c3d1-19dd-4412-b644-608f1611a74f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745984114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.745984114
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3658404617
Short name T975
Test name
Test status
Simulation time 19351995 ps
CPU time 1.26 seconds
Started Jul 11 06:19:32 PM PDT 24
Finished Jul 11 06:19:37 PM PDT 24
Peak memory 218696 kb
Host smart-00625eab-1568-42ed-aa89-2981a485afa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658404617 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3658404617
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3486872738
Short name T163
Test name
Test status
Simulation time 39511183 ps
CPU time 0.84 seconds
Started Jul 11 06:19:29 PM PDT 24
Finished Jul 11 06:19:31 PM PDT 24
Peak memory 209208 kb
Host smart-3b944eb8-0fa8-4849-97d2-e1f87d99e6db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486872738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3486872738
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3125379164
Short name T948
Test name
Test status
Simulation time 22045670 ps
CPU time 1.01 seconds
Started Jul 11 06:19:20 PM PDT 24
Finished Jul 11 06:19:24 PM PDT 24
Peak memory 209280 kb
Host smart-1d7140d7-59e5-455e-b01e-e8c031c2514b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125379164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3125379164
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1402110093
Short name T947
Test name
Test status
Simulation time 345704423 ps
CPU time 2.44 seconds
Started Jul 11 06:19:21 PM PDT 24
Finished Jul 11 06:19:26 PM PDT 24
Peak memory 217540 kb
Host smart-0d5f338a-af65-48a7-aed2-c51cafb81f2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402110093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1402110093
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1027035212
Short name T985
Test name
Test status
Simulation time 23307989 ps
CPU time 1.19 seconds
Started Jul 11 06:19:33 PM PDT 24
Finished Jul 11 06:19:37 PM PDT 24
Peak memory 219208 kb
Host smart-bb278bd1-99a7-4627-9ecd-7c621e54fe2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027035212 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1027035212
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3446082165
Short name T167
Test name
Test status
Simulation time 162818645 ps
CPU time 1.08 seconds
Started Jul 11 06:19:29 PM PDT 24
Finished Jul 11 06:19:32 PM PDT 24
Peak memory 209288 kb
Host smart-86bc5ac3-75b9-4914-bb69-1d39c92a23db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446082165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3446082165
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1409567928
Short name T990
Test name
Test status
Simulation time 45843147 ps
CPU time 1.18 seconds
Started Jul 11 06:19:31 PM PDT 24
Finished Jul 11 06:19:35 PM PDT 24
Peak memory 217420 kb
Host smart-8928f025-008f-4430-935a-8242db6f2344
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409567928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1409567928
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3268796429
Short name T873
Test name
Test status
Simulation time 54759745 ps
CPU time 2.54 seconds
Started Jul 11 06:19:29 PM PDT 24
Finished Jul 11 06:19:33 PM PDT 24
Peak memory 217480 kb
Host smart-4ee1d0a9-a78d-46c2-91de-c3c9d4e7044b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268796429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3268796429
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.755576439
Short name T168
Test name
Test status
Simulation time 59565212 ps
CPU time 1.15 seconds
Started Jul 11 06:18:40 PM PDT 24
Finished Jul 11 06:18:43 PM PDT 24
Peak memory 209324 kb
Host smart-06f07f5d-b7eb-400d-9407-297cae7e351e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755576439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.755576439
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4248906264
Short name T941
Test name
Test status
Simulation time 39073980 ps
CPU time 1.19 seconds
Started Jul 11 06:18:40 PM PDT 24
Finished Jul 11 06:18:44 PM PDT 24
Peak memory 209348 kb
Host smart-486e88f7-551e-44ed-b860-a1816f76fd49
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248906264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.4248906264
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1628818457
Short name T864
Test name
Test status
Simulation time 18322192 ps
CPU time 0.93 seconds
Started Jul 11 06:18:40 PM PDT 24
Finished Jul 11 06:18:43 PM PDT 24
Peak memory 209860 kb
Host smart-adcaabe0-5d3c-49df-8574-7e17c9a0b5d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628818457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1628818457
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1600135018
Short name T871
Test name
Test status
Simulation time 30586151 ps
CPU time 1.19 seconds
Started Jul 11 06:18:43 PM PDT 24
Finished Jul 11 06:18:46 PM PDT 24
Peak memory 217560 kb
Host smart-c5c0c963-bf0c-49b0-8443-20d040bd0b2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600135018 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1600135018
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.380855647
Short name T174
Test name
Test status
Simulation time 23795730 ps
CPU time 0.86 seconds
Started Jul 11 06:18:44 PM PDT 24
Finished Jul 11 06:18:47 PM PDT 24
Peak memory 209336 kb
Host smart-d8bbcaf5-5c4c-4cd2-9064-e71371b80933
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380855647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.380855647
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1069645313
Short name T912
Test name
Test status
Simulation time 54545395 ps
CPU time 0.99 seconds
Started Jul 11 06:18:34 PM PDT 24
Finished Jul 11 06:18:37 PM PDT 24
Peak memory 209268 kb
Host smart-d5bf9599-eb42-49ee-b2df-b00c40675760
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069645313 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1069645313
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.384628795
Short name T905
Test name
Test status
Simulation time 961474558 ps
CPU time 17.22 seconds
Started Jul 11 06:18:38 PM PDT 24
Finished Jul 11 06:18:56 PM PDT 24
Peak memory 209052 kb
Host smart-f5f89f47-9f3d-4f3a-b3ba-82e6550b249d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384628795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.384628795
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4104017427
Short name T983
Test name
Test status
Simulation time 1922737279 ps
CPU time 10.56 seconds
Started Jul 11 06:18:39 PM PDT 24
Finished Jul 11 06:18:52 PM PDT 24
Peak memory 209176 kb
Host smart-1f2c82f5-37ec-43cd-ac23-cd3a38b97076
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104017427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.4104017427
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2279869228
Short name T898
Test name
Test status
Simulation time 152802670 ps
CPU time 1.54 seconds
Started Jul 11 06:18:35 PM PDT 24
Finished Jul 11 06:18:39 PM PDT 24
Peak memory 210336 kb
Host smart-02cdf86f-d063-415f-bf8e-ce18149f1bef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279869228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2279869228
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4114758274
Short name T942
Test name
Test status
Simulation time 167528584 ps
CPU time 1.4 seconds
Started Jul 11 06:18:38 PM PDT 24
Finished Jul 11 06:18:41 PM PDT 24
Peak memory 217652 kb
Host smart-7b9d2edc-be95-4504-9fee-6804bc1af4b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411475
8274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4114758274
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.76844931
Short name T882
Test name
Test status
Simulation time 55970359 ps
CPU time 1.27 seconds
Started Jul 11 06:18:38 PM PDT 24
Finished Jul 11 06:18:41 PM PDT 24
Peak memory 209180 kb
Host smart-5f3c554c-60c3-4cec-8675-5aa00a33786d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76844931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 2.lc_ctrl_jtag_csr_rw.76844931
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4134728283
Short name T931
Test name
Test status
Simulation time 580895365 ps
CPU time 1.27 seconds
Started Jul 11 06:18:40 PM PDT 24
Finished Jul 11 06:18:43 PM PDT 24
Peak memory 209344 kb
Host smart-3ff0b7b6-a2a0-4120-b197-c0ae047a4cb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134728283 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.4134728283
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.321061871
Short name T930
Test name
Test status
Simulation time 79790769 ps
CPU time 1.33 seconds
Started Jul 11 06:18:44 PM PDT 24
Finished Jul 11 06:18:47 PM PDT 24
Peak memory 211084 kb
Host smart-2f8e4554-4a21-4922-944c-a1c6d95c5c73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321061871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.321061871
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3335705820
Short name T922
Test name
Test status
Simulation time 1021046359 ps
CPU time 4.1 seconds
Started Jul 11 06:18:35 PM PDT 24
Finished Jul 11 06:18:41 PM PDT 24
Peak memory 217492 kb
Host smart-18231cfa-03d8-4b6c-80cf-5bb876737f28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335705820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3335705820
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.706685047
Short name T186
Test name
Test status
Simulation time 538305353 ps
CPU time 3.25 seconds
Started Jul 11 06:18:42 PM PDT 24
Finished Jul 11 06:18:46 PM PDT 24
Peak memory 222228 kb
Host smart-d96694cf-981e-41ee-8228-7a0d0d032a22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706685047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e
rr.706685047
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.913013426
Short name T910
Test name
Test status
Simulation time 33844430 ps
CPU time 1.33 seconds
Started Jul 11 06:18:47 PM PDT 24
Finished Jul 11 06:18:49 PM PDT 24
Peak memory 209304 kb
Host smart-4e2195b7-141c-4f5c-93c0-6c529f59d18b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913013426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.913013426
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.4047195101
Short name T171
Test name
Test status
Simulation time 22410477 ps
CPU time 1.12 seconds
Started Jul 11 06:18:45 PM PDT 24
Finished Jul 11 06:18:48 PM PDT 24
Peak memory 209192 kb
Host smart-983a9477-4e4a-4a23-96cb-59bab59d8be9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047195101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.4047195101
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.85430661
Short name T989
Test name
Test status
Simulation time 44291339 ps
CPU time 1.01 seconds
Started Jul 11 06:18:49 PM PDT 24
Finished Jul 11 06:18:51 PM PDT 24
Peak memory 210360 kb
Host smart-a8b1793c-043a-4192-8f86-075afe8edf7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85430661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_reset.85430661
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1262702940
Short name T984
Test name
Test status
Simulation time 581216863 ps
CPU time 1.49 seconds
Started Jul 11 06:18:46 PM PDT 24
Finished Jul 11 06:18:49 PM PDT 24
Peak memory 224572 kb
Host smart-d2e182ac-9de3-4978-b4ae-6fa89e8c79fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262702940 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1262702940
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3948246998
Short name T132
Test name
Test status
Simulation time 12741863 ps
CPU time 0.83 seconds
Started Jul 11 06:18:47 PM PDT 24
Finished Jul 11 06:18:49 PM PDT 24
Peak memory 208944 kb
Host smart-727a5a3a-f1fe-4566-9a79-1a71874a126d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948246998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3948246998
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1369148722
Short name T900
Test name
Test status
Simulation time 116124822 ps
CPU time 1.35 seconds
Started Jul 11 06:18:41 PM PDT 24
Finished Jul 11 06:18:44 PM PDT 24
Peak memory 209148 kb
Host smart-8c6a6890-4505-4dd1-80b6-cddb37d9745b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369148722 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1369148722
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1368719653
Short name T938
Test name
Test status
Simulation time 1299829526 ps
CPU time 6.36 seconds
Started Jul 11 06:18:42 PM PDT 24
Finished Jul 11 06:18:50 PM PDT 24
Peak memory 209132 kb
Host smart-72c968ce-6dbe-4760-a296-7707089d60d8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368719653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1368719653
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.59225136
Short name T951
Test name
Test status
Simulation time 694410378 ps
CPU time 16.29 seconds
Started Jul 11 06:18:41 PM PDT 24
Finished Jul 11 06:18:59 PM PDT 24
Peak memory 217112 kb
Host smart-afbe336d-c713-493e-b0c6-6fbb8cc70293
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59225136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.59225136
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.743092278
Short name T134
Test name
Test status
Simulation time 847204259 ps
CPU time 4.9 seconds
Started Jul 11 06:18:43 PM PDT 24
Finished Jul 11 06:18:49 PM PDT 24
Peak memory 210956 kb
Host smart-55ed47f6-7f1c-4b8a-8bbf-3ba2cc997261
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743092278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.743092278
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4128917878
Short name T963
Test name
Test status
Simulation time 249571803 ps
CPU time 1.57 seconds
Started Jul 11 06:18:43 PM PDT 24
Finished Jul 11 06:18:46 PM PDT 24
Peak memory 218716 kb
Host smart-87fb0ddb-69e0-482d-906b-03d90706ada7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412891
7878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4128917878
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3138973963
Short name T961
Test name
Test status
Simulation time 78044722 ps
CPU time 2.08 seconds
Started Jul 11 06:18:40 PM PDT 24
Finished Jul 11 06:18:44 PM PDT 24
Peak memory 209256 kb
Host smart-30652d02-7404-4dbb-b61d-fa2688aca19b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138973963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3138973963
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3866154508
Short name T178
Test name
Test status
Simulation time 21805189 ps
CPU time 1.26 seconds
Started Jul 11 06:18:43 PM PDT 24
Finished Jul 11 06:18:47 PM PDT 24
Peak memory 211348 kb
Host smart-0e8202b0-06b9-4d13-9595-c77701229a75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866154508 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3866154508
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.910059799
Short name T969
Test name
Test status
Simulation time 40698640 ps
CPU time 1.91 seconds
Started Jul 11 06:18:47 PM PDT 24
Finished Jul 11 06:18:50 PM PDT 24
Peak memory 217448 kb
Host smart-b9f9fb59-3916-4dea-8669-97858ebd4aa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910059799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.910059799
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3838050526
Short name T901
Test name
Test status
Simulation time 94818743 ps
CPU time 1.65 seconds
Started Jul 11 06:18:43 PM PDT 24
Finished Jul 11 06:18:47 PM PDT 24
Peak memory 217804 kb
Host smart-51aa6a32-414e-458f-bbd0-3734d2259a5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838050526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3838050526
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3180578077
Short name T166
Test name
Test status
Simulation time 138055225 ps
CPU time 1.75 seconds
Started Jul 11 06:18:51 PM PDT 24
Finished Jul 11 06:18:54 PM PDT 24
Peak memory 209304 kb
Host smart-652197c3-9428-495f-b0b9-687b8394a440
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180578077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.3180578077
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2025836195
Short name T968
Test name
Test status
Simulation time 1065355225 ps
CPU time 2.65 seconds
Started Jul 11 06:18:53 PM PDT 24
Finished Jul 11 06:18:57 PM PDT 24
Peak memory 209016 kb
Host smart-38dde007-3429-4d23-851e-d0901c5fe60a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025836195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2025836195
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.416053123
Short name T934
Test name
Test status
Simulation time 21900766 ps
CPU time 1.01 seconds
Started Jul 11 06:18:54 PM PDT 24
Finished Jul 11 06:18:56 PM PDT 24
Peak memory 218008 kb
Host smart-f9eec6e1-f94e-48f3-bb4e-16e2fffed437
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416053123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.416053123
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2747912586
Short name T928
Test name
Test status
Simulation time 29771855 ps
CPU time 1.83 seconds
Started Jul 11 06:18:55 PM PDT 24
Finished Jul 11 06:18:58 PM PDT 24
Peak memory 217636 kb
Host smart-2fe165dc-256d-4c42-ad11-fc916376aac3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747912586 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2747912586
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1327599841
Short name T165
Test name
Test status
Simulation time 15298385 ps
CPU time 0.89 seconds
Started Jul 11 06:18:52 PM PDT 24
Finished Jul 11 06:18:54 PM PDT 24
Peak memory 209296 kb
Host smart-f082dd20-7d19-40d7-8eea-11f6226455fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327599841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1327599841
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1584842477
Short name T970
Test name
Test status
Simulation time 18717614 ps
CPU time 0.93 seconds
Started Jul 11 06:18:49 PM PDT 24
Finished Jul 11 06:18:51 PM PDT 24
Peak memory 208540 kb
Host smart-1f0065e3-188a-4418-8c9f-44a850d8e2c4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584842477 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1584842477
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2395736092
Short name T967
Test name
Test status
Simulation time 2494831487 ps
CPU time 6.05 seconds
Started Jul 11 06:18:48 PM PDT 24
Finished Jul 11 06:18:55 PM PDT 24
Peak memory 209420 kb
Host smart-baa9b3df-b649-4347-a527-2dce6f90416f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395736092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2395736092
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1850722834
Short name T889
Test name
Test status
Simulation time 3892518252 ps
CPU time 9.68 seconds
Started Jul 11 06:18:49 PM PDT 24
Finished Jul 11 06:19:00 PM PDT 24
Peak memory 209276 kb
Host smart-bc9d9560-f805-41ed-90b9-2fb9f0155256
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850722834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1850722834
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2139115627
Short name T891
Test name
Test status
Simulation time 60753290 ps
CPU time 1.5 seconds
Started Jul 11 06:18:48 PM PDT 24
Finished Jul 11 06:18:51 PM PDT 24
Peak memory 210872 kb
Host smart-e5a9cdde-d70b-4672-8279-8d5c58fad6e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139115627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2139115627
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1139923211
Short name T991
Test name
Test status
Simulation time 83357845 ps
CPU time 2 seconds
Started Jul 11 06:18:45 PM PDT 24
Finished Jul 11 06:18:49 PM PDT 24
Peak memory 222544 kb
Host smart-28714b20-cd34-4200-813c-cb28b8eef110
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113992
3211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1139923211
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1482170635
Short name T972
Test name
Test status
Simulation time 151148638 ps
CPU time 1.54 seconds
Started Jul 11 06:18:47 PM PDT 24
Finished Jul 11 06:18:50 PM PDT 24
Peak memory 217372 kb
Host smart-82cefd2d-e275-476b-94e4-83a5696dacc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482170635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1482170635
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1378535420
Short name T981
Test name
Test status
Simulation time 74904811 ps
CPU time 1.48 seconds
Started Jul 11 06:18:48 PM PDT 24
Finished Jul 11 06:18:50 PM PDT 24
Peak memory 217572 kb
Host smart-dce68f07-3677-44a7-80b8-6617022a45f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378535420 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1378535420
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1657428432
Short name T918
Test name
Test status
Simulation time 24970826 ps
CPU time 1.11 seconds
Started Jul 11 06:18:51 PM PDT 24
Finished Jul 11 06:18:54 PM PDT 24
Peak memory 217452 kb
Host smart-04ec5965-f1f4-4ce4-b49c-2849b9b83959
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657428432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1657428432
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3886560230
Short name T962
Test name
Test status
Simulation time 56869571 ps
CPU time 2.1 seconds
Started Jul 11 06:18:55 PM PDT 24
Finished Jul 11 06:18:58 PM PDT 24
Peak memory 217636 kb
Host smart-8e303a43-9a45-41b2-8080-fa33c16a6e93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886560230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3886560230
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3375505807
Short name T883
Test name
Test status
Simulation time 58824663 ps
CPU time 1.63 seconds
Started Jul 11 06:18:58 PM PDT 24
Finished Jul 11 06:19:02 PM PDT 24
Peak memory 218772 kb
Host smart-1cf6484d-970e-4032-a73f-548946d5ecbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375505807 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3375505807
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.957144312
Short name T875
Test name
Test status
Simulation time 18613332 ps
CPU time 1.16 seconds
Started Jul 11 06:19:01 PM PDT 24
Finished Jul 11 06:19:03 PM PDT 24
Peak memory 209296 kb
Host smart-7d65be16-07fc-4dc2-a017-66563e02754e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957144312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.957144312
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.179585379
Short name T973
Test name
Test status
Simulation time 109379646 ps
CPU time 1.65 seconds
Started Jul 11 06:18:57 PM PDT 24
Finished Jul 11 06:19:00 PM PDT 24
Peak memory 209136 kb
Host smart-40653960-1e85-4ff5-9c8b-53ae14fc81ab
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179585379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.lc_ctrl_jtag_alert_test.179585379
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3066625543
Short name T899
Test name
Test status
Simulation time 416953186 ps
CPU time 3.04 seconds
Started Jul 11 06:18:55 PM PDT 24
Finished Jul 11 06:18:59 PM PDT 24
Peak memory 209240 kb
Host smart-0ef04ba5-cc39-4fe6-b333-2ca0531a7408
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066625543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3066625543
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3780063093
Short name T954
Test name
Test status
Simulation time 4918318396 ps
CPU time 6.3 seconds
Started Jul 11 06:18:54 PM PDT 24
Finished Jul 11 06:19:01 PM PDT 24
Peak memory 209292 kb
Host smart-69adab9f-e723-4d97-8a9a-d84d5ed5658e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780063093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3780063093
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2830524647
Short name T885
Test name
Test status
Simulation time 248188515 ps
CPU time 1.91 seconds
Started Jul 11 06:18:55 PM PDT 24
Finished Jul 11 06:18:58 PM PDT 24
Peak memory 210744 kb
Host smart-cb6e63af-e3e6-40e3-95b4-8447ef14f4e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830524647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2830524647
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2262765005
Short name T133
Test name
Test status
Simulation time 524967368 ps
CPU time 1.51 seconds
Started Jul 11 06:19:00 PM PDT 24
Finished Jul 11 06:19:03 PM PDT 24
Peak memory 218508 kb
Host smart-41bba9ba-a1ce-482c-8651-70ea969d0a4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226276
5005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2262765005
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.504573681
Short name T869
Test name
Test status
Simulation time 84078825 ps
CPU time 2.63 seconds
Started Jul 11 06:18:55 PM PDT 24
Finished Jul 11 06:18:59 PM PDT 24
Peak memory 217336 kb
Host smart-d92c89f8-baa1-4625-94d2-f4e50e50745c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504573681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.504573681
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4268486066
Short name T112
Test name
Test status
Simulation time 163483852 ps
CPU time 1.8 seconds
Started Jul 11 06:18:58 PM PDT 24
Finished Jul 11 06:19:01 PM PDT 24
Peak memory 209516 kb
Host smart-778b1a12-d139-49b6-86f6-17b52018f4c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268486066 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.4268486066
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1629777353
Short name T881
Test name
Test status
Simulation time 22863805 ps
CPU time 1.47 seconds
Started Jul 11 06:18:59 PM PDT 24
Finished Jul 11 06:19:02 PM PDT 24
Peak memory 211192 kb
Host smart-63ea45b5-253e-4bdd-86f1-3c8edfabad85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629777353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1629777353
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.624290347
Short name T987
Test name
Test status
Simulation time 71136136 ps
CPU time 2.15 seconds
Started Jul 11 06:18:57 PM PDT 24
Finished Jul 11 06:19:01 PM PDT 24
Peak memory 218996 kb
Host smart-25f2e5b7-e1ff-4df2-a073-6557ef4c9f5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624290347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.624290347
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1471108260
Short name T128
Test name
Test status
Simulation time 297036890 ps
CPU time 2.58 seconds
Started Jul 11 06:18:59 PM PDT 24
Finished Jul 11 06:19:03 PM PDT 24
Peak memory 217512 kb
Host smart-f4b0e76d-e29e-449a-9a3c-698634a4d3b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471108260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1471108260
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3928663309
Short name T867
Test name
Test status
Simulation time 36537271 ps
CPU time 1.28 seconds
Started Jul 11 06:19:05 PM PDT 24
Finished Jul 11 06:19:09 PM PDT 24
Peak memory 217556 kb
Host smart-bbf0060f-a6a4-48f7-8c97-8f35e8f136f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928663309 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3928663309
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3502641176
Short name T177
Test name
Test status
Simulation time 44498887 ps
CPU time 1.02 seconds
Started Jul 11 06:19:04 PM PDT 24
Finished Jul 11 06:19:07 PM PDT 24
Peak memory 209100 kb
Host smart-7983d6d4-50d9-40d9-99d8-db496bd323ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502641176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3502641176
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.553382677
Short name T958
Test name
Test status
Simulation time 48003257 ps
CPU time 1.19 seconds
Started Jul 11 06:19:04 PM PDT 24
Finished Jul 11 06:19:08 PM PDT 24
Peak memory 209176 kb
Host smart-1d4f6c22-1eeb-418b-b0b0-b164191f6fd1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553382677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.553382677
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2709769435
Short name T893
Test name
Test status
Simulation time 759823559 ps
CPU time 5.61 seconds
Started Jul 11 06:19:00 PM PDT 24
Finished Jul 11 06:19:07 PM PDT 24
Peak memory 209232 kb
Host smart-8ad37da4-b3d8-4110-a058-adca9471bfb2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709769435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2709769435
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2888306131
Short name T939
Test name
Test status
Simulation time 698675397 ps
CPU time 18.08 seconds
Started Jul 11 06:18:58 PM PDT 24
Finished Jul 11 06:19:19 PM PDT 24
Peak memory 209204 kb
Host smart-415402eb-5641-4cc9-baef-4c285fb2b27a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888306131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2888306131
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.143796952
Short name T877
Test name
Test status
Simulation time 58708451 ps
CPU time 1.92 seconds
Started Jul 11 06:18:58 PM PDT 24
Finished Jul 11 06:19:02 PM PDT 24
Peak memory 210924 kb
Host smart-3194e0d2-e871-4147-869a-14340c507bbd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143796952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.143796952
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3282482250
Short name T108
Test name
Test status
Simulation time 50103497 ps
CPU time 2 seconds
Started Jul 11 06:18:58 PM PDT 24
Finished Jul 11 06:19:02 PM PDT 24
Peak memory 217596 kb
Host smart-18329fa2-6ecc-440b-8567-43b64b3450a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328248
2250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3282482250
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.935643823
Short name T904
Test name
Test status
Simulation time 83590748 ps
CPU time 2.58 seconds
Started Jul 11 06:18:57 PM PDT 24
Finished Jul 11 06:19:01 PM PDT 24
Peak memory 209244 kb
Host smart-9ddf8b08-a30e-4b18-b734-31c2cf16338c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935643823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.935643823
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1617419963
Short name T176
Test name
Test status
Simulation time 36473988 ps
CPU time 1.19 seconds
Started Jul 11 06:18:59 PM PDT 24
Finished Jul 11 06:19:02 PM PDT 24
Peak memory 209408 kb
Host smart-936cc0d8-51a5-4d9f-9341-57a8e6888ba0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617419963 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1617419963
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2507955736
Short name T180
Test name
Test status
Simulation time 37493922 ps
CPU time 1.26 seconds
Started Jul 11 06:19:04 PM PDT 24
Finished Jul 11 06:19:07 PM PDT 24
Peak memory 211328 kb
Host smart-d8a3f7ec-78ee-4d37-905f-fd95be3036b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507955736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2507955736
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2027757795
Short name T929
Test name
Test status
Simulation time 384341315 ps
CPU time 2.96 seconds
Started Jul 11 06:19:05 PM PDT 24
Finished Jul 11 06:19:10 PM PDT 24
Peak memory 218552 kb
Host smart-b6d588b5-63b7-49c1-9203-9fd5189f6b2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027757795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2027757795
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.64736548
Short name T896
Test name
Test status
Simulation time 57650268 ps
CPU time 1.32 seconds
Started Jul 11 06:19:10 PM PDT 24
Finished Jul 11 06:19:13 PM PDT 24
Peak memory 217560 kb
Host smart-18425a2b-15ae-4284-a189-3d0520aa7066
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64736548 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.64736548
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2715732836
Short name T164
Test name
Test status
Simulation time 18387274 ps
CPU time 0.99 seconds
Started Jul 11 06:19:24 PM PDT 24
Finished Jul 11 06:19:27 PM PDT 24
Peak memory 209220 kb
Host smart-868a31f0-0e98-459f-937e-cfb6705fc415
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715732836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2715732836
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2655479474
Short name T917
Test name
Test status
Simulation time 67051577 ps
CPU time 1.48 seconds
Started Jul 11 06:19:05 PM PDT 24
Finished Jul 11 06:19:08 PM PDT 24
Peak memory 209160 kb
Host smart-f24ec469-f720-47f6-a302-6aebb23ed368
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655479474 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2655479474
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3601122813
Short name T890
Test name
Test status
Simulation time 225722256 ps
CPU time 3.05 seconds
Started Jul 11 06:19:04 PM PDT 24
Finished Jul 11 06:19:08 PM PDT 24
Peak memory 209236 kb
Host smart-b25b3b11-2c4d-4b9c-9faf-9d3189065bbf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601122813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3601122813
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.47744408
Short name T980
Test name
Test status
Simulation time 12326371263 ps
CPU time 41.75 seconds
Started Jul 11 06:19:05 PM PDT 24
Finished Jul 11 06:19:48 PM PDT 24
Peak memory 209132 kb
Host smart-6977e4c6-7a0b-40d1-ba80-3d5c9e3fb5fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47744408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.47744408
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2779230905
Short name T916
Test name
Test status
Simulation time 237655851 ps
CPU time 1.47 seconds
Started Jul 11 06:19:04 PM PDT 24
Finished Jul 11 06:19:08 PM PDT 24
Peak memory 210692 kb
Host smart-e1d1fb6f-b36b-48c7-be87-7175600bcbff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779230905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2779230905
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2323695046
Short name T964
Test name
Test status
Simulation time 51826979 ps
CPU time 2.28 seconds
Started Jul 11 06:19:04 PM PDT 24
Finished Jul 11 06:19:08 PM PDT 24
Peak memory 219360 kb
Host smart-a9c86add-b34d-448b-835b-b32be83dc581
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232369
5046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2323695046
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.233037881
Short name T136
Test name
Test status
Simulation time 167172940 ps
CPU time 1.37 seconds
Started Jul 11 06:19:03 PM PDT 24
Finished Jul 11 06:19:05 PM PDT 24
Peak memory 209112 kb
Host smart-7871971a-07a3-4ba5-b9f2-aeb0efa2e1d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233037881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.233037881
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2562239759
Short name T924
Test name
Test status
Simulation time 94062530 ps
CPU time 1.08 seconds
Started Jul 11 06:19:05 PM PDT 24
Finished Jul 11 06:19:08 PM PDT 24
Peak memory 217464 kb
Host smart-2fdfe6ef-5235-44f8-acc2-ebf6cb334629
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562239759 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2562239759
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3738873766
Short name T943
Test name
Test status
Simulation time 29764746 ps
CPU time 1.04 seconds
Started Jul 11 06:19:16 PM PDT 24
Finished Jul 11 06:19:18 PM PDT 24
Peak memory 209328 kb
Host smart-45a42673-f9da-4007-a6af-c727e9705986
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738873766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3738873766
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3763252206
Short name T946
Test name
Test status
Simulation time 26051718 ps
CPU time 1.92 seconds
Started Jul 11 06:19:04 PM PDT 24
Finished Jul 11 06:19:08 PM PDT 24
Peak memory 218092 kb
Host smart-50a70875-dc09-41fc-beb0-2389e4945800
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763252206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3763252206
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2314680371
Short name T150
Test name
Test status
Simulation time 33009051 ps
CPU time 1.06 seconds
Started Jul 11 06:19:13 PM PDT 24
Finished Jul 11 06:19:15 PM PDT 24
Peak memory 217528 kb
Host smart-78a7b1d9-77c9-45ec-af0f-44df2b688001
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314680371 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.2314680371
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1064691122
Short name T966
Test name
Test status
Simulation time 12531025 ps
CPU time 0.89 seconds
Started Jul 11 06:19:10 PM PDT 24
Finished Jul 11 06:19:13 PM PDT 24
Peak memory 208964 kb
Host smart-e6489887-3ad3-4ef0-a9c9-c5ef7cc092d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064691122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1064691122
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2703368852
Short name T865
Test name
Test status
Simulation time 68479352 ps
CPU time 1.35 seconds
Started Jul 11 06:19:12 PM PDT 24
Finished Jul 11 06:19:14 PM PDT 24
Peak memory 209152 kb
Host smart-ebbe88fe-9942-4ab0-a087-555b8fa4ee94
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703368852 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2703368852
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.407490724
Short name T925
Test name
Test status
Simulation time 2655728643 ps
CPU time 28.56 seconds
Started Jul 11 06:19:13 PM PDT 24
Finished Jul 11 06:19:43 PM PDT 24
Peak memory 209184 kb
Host smart-18138870-ec9b-45ec-b4c4-578ad206ef4b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407490724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.407490724
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2538297681
Short name T884
Test name
Test status
Simulation time 766877505 ps
CPU time 9.43 seconds
Started Jul 11 06:19:08 PM PDT 24
Finished Jul 11 06:19:19 PM PDT 24
Peak memory 209228 kb
Host smart-6df27c2f-37d2-43fc-896c-d8104f16180b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538297681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2538297681
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.906860527
Short name T116
Test name
Test status
Simulation time 45461444 ps
CPU time 1.28 seconds
Started Jul 11 06:19:12 PM PDT 24
Finished Jul 11 06:19:14 PM PDT 24
Peak memory 217440 kb
Host smart-1715be5d-a4bb-4f9d-8b8d-83d64c1edf0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906860527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.906860527
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2869360734
Short name T965
Test name
Test status
Simulation time 2129804432 ps
CPU time 3.64 seconds
Started Jul 11 06:19:10 PM PDT 24
Finished Jul 11 06:19:15 PM PDT 24
Peak memory 217544 kb
Host smart-7fe879e5-7fda-4eae-8711-d3ef87eda148
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286936
0734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2869360734
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2642566521
Short name T909
Test name
Test status
Simulation time 57434499 ps
CPU time 2.22 seconds
Started Jul 11 06:19:24 PM PDT 24
Finished Jul 11 06:19:29 PM PDT 24
Peak memory 209208 kb
Host smart-50f0e955-7ff6-4109-b314-1c68db555284
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642566521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2642566521
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.801857154
Short name T959
Test name
Test status
Simulation time 43857420 ps
CPU time 1.42 seconds
Started Jul 11 06:19:10 PM PDT 24
Finished Jul 11 06:19:13 PM PDT 24
Peak memory 209172 kb
Host smart-d42b39bb-8ba1-4c5b-b785-d66541be7a57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801857154 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.801857154
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2302979248
Short name T892
Test name
Test status
Simulation time 82516946 ps
CPU time 1.33 seconds
Started Jul 11 06:19:11 PM PDT 24
Finished Jul 11 06:19:14 PM PDT 24
Peak memory 209332 kb
Host smart-dd17fc39-3bb5-4263-95df-8d52816a14d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302979248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2302979248
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3967456080
Short name T952
Test name
Test status
Simulation time 243034201 ps
CPU time 3.07 seconds
Started Jul 11 06:19:11 PM PDT 24
Finished Jul 11 06:19:15 PM PDT 24
Peak memory 217516 kb
Host smart-a48d050e-7f5b-4680-803a-e3e50db86880
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967456080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3967456080
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1750545069
Short name T932
Test name
Test status
Simulation time 102685204 ps
CPU time 1.74 seconds
Started Jul 11 06:19:16 PM PDT 24
Finished Jul 11 06:19:20 PM PDT 24
Peak memory 218332 kb
Host smart-23d92a99-a848-45a9-a7af-f1709102b72d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750545069 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1750545069
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2635585280
Short name T866
Test name
Test status
Simulation time 17297155 ps
CPU time 0.89 seconds
Started Jul 11 06:19:15 PM PDT 24
Finished Jul 11 06:19:17 PM PDT 24
Peak memory 217356 kb
Host smart-ecf2e682-d4d2-4bf3-a80c-c972b9b19c62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635585280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2635585280
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1034245310
Short name T977
Test name
Test status
Simulation time 125124456 ps
CPU time 1.13 seconds
Started Jul 11 06:19:10 PM PDT 24
Finished Jul 11 06:19:13 PM PDT 24
Peak memory 209128 kb
Host smart-ae3b860c-f9f7-448a-abf9-8cf29c32f8c5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034245310 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1034245310
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1423209710
Short name T953
Test name
Test status
Simulation time 947645098 ps
CPU time 11.62 seconds
Started Jul 11 06:19:14 PM PDT 24
Finished Jul 11 06:19:27 PM PDT 24
Peak memory 209120 kb
Host smart-8ea7d577-08a9-4a36-a058-5ba31a3f36ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423209710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1423209710
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2657796030
Short name T940
Test name
Test status
Simulation time 1398754543 ps
CPU time 20.14 seconds
Started Jul 11 06:19:12 PM PDT 24
Finished Jul 11 06:19:33 PM PDT 24
Peak memory 209212 kb
Host smart-a86c06bf-965a-4052-bde8-c911acbf6d1e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657796030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2657796030
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3345899210
Short name T945
Test name
Test status
Simulation time 2459174761 ps
CPU time 6.47 seconds
Started Jul 11 06:19:24 PM PDT 24
Finished Jul 11 06:19:33 PM PDT 24
Peak memory 210944 kb
Host smart-c4da4f0b-52fa-4750-9ac7-1db40fc14e5e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345899210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3345899210
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1206136409
Short name T979
Test name
Test status
Simulation time 386968821 ps
CPU time 2.03 seconds
Started Jul 11 06:19:24 PM PDT 24
Finished Jul 11 06:19:28 PM PDT 24
Peak memory 221712 kb
Host smart-8094a10a-8d84-4ad8-8ea8-cffb86e7f202
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120613
6409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1206136409
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3980972394
Short name T982
Test name
Test status
Simulation time 67209107 ps
CPU time 1.67 seconds
Started Jul 11 06:19:10 PM PDT 24
Finished Jul 11 06:19:13 PM PDT 24
Peak memory 217360 kb
Host smart-7d138bbd-fa05-4bfc-943f-5fb5da240ec4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980972394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3980972394
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2249747875
Short name T887
Test name
Test status
Simulation time 42287010 ps
CPU time 2.03 seconds
Started Jul 11 06:19:24 PM PDT 24
Finished Jul 11 06:19:28 PM PDT 24
Peak memory 217456 kb
Host smart-8107194d-7545-4570-bb6c-8d41b5d7e3d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249747875 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2249747875
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1548418512
Short name T956
Test name
Test status
Simulation time 63555593 ps
CPU time 1.41 seconds
Started Jul 11 06:19:17 PM PDT 24
Finished Jul 11 06:19:21 PM PDT 24
Peak memory 217464 kb
Host smart-cd4b87e5-d7f9-4ee7-bf63-6c89fb6e5597
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548418512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.1548418512
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1414236316
Short name T936
Test name
Test status
Simulation time 219581595 ps
CPU time 4.55 seconds
Started Jul 11 06:19:10 PM PDT 24
Finished Jul 11 06:19:16 PM PDT 24
Peak memory 217528 kb
Host smart-ee8ae264-6e1d-4817-b9e1-fdc1c9177410
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414236316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1414236316
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.816114327
Short name T131
Test name
Test status
Simulation time 106178870 ps
CPU time 3.32 seconds
Started Jul 11 06:19:25 PM PDT 24
Finished Jul 11 06:19:31 PM PDT 24
Peak memory 222172 kb
Host smart-cfce12ac-fe4a-4b70-b5af-151beda37d99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816114327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.816114327
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3885436062
Short name T87
Test name
Test status
Simulation time 32722288 ps
CPU time 1.27 seconds
Started Jul 11 06:20:01 PM PDT 24
Finished Jul 11 06:20:05 PM PDT 24
Peak memory 208616 kb
Host smart-c428dfd9-b160-4ab7-8404-b7851a92e27a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885436062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3885436062
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1086899525
Short name T693
Test name
Test status
Simulation time 39779765 ps
CPU time 0.99 seconds
Started Jul 11 06:19:58 PM PDT 24
Finished Jul 11 06:20:02 PM PDT 24
Peak memory 208436 kb
Host smart-8ecd3ebc-dcdd-4dec-b22e-391c02ff2309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086899525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1086899525
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3029956459
Short name T364
Test name
Test status
Simulation time 1158309482 ps
CPU time 9.32 seconds
Started Jul 11 06:19:58 PM PDT 24
Finished Jul 11 06:20:10 PM PDT 24
Peak memory 217780 kb
Host smart-c96a0099-666c-431a-9c58-2dfe8cd845c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029956459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3029956459
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3053031162
Short name T20
Test name
Test status
Simulation time 834836101 ps
CPU time 4.25 seconds
Started Jul 11 06:19:56 PM PDT 24
Finished Jul 11 06:20:02 PM PDT 24
Peak memory 216764 kb
Host smart-e931bc61-85e3-4dfe-b538-885e66e36947
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053031162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3053031162
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1377072564
Short name T819
Test name
Test status
Simulation time 3086425348 ps
CPU time 44.37 seconds
Started Jul 11 06:19:55 PM PDT 24
Finished Jul 11 06:20:40 PM PDT 24
Peak memory 219424 kb
Host smart-8e3d6ff4-7713-408a-bff8-d4346baea62b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377072564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1377072564
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.3027999872
Short name T417
Test name
Test status
Simulation time 11889254726 ps
CPU time 13.71 seconds
Started Jul 11 06:20:03 PM PDT 24
Finished Jul 11 06:20:19 PM PDT 24
Peak memory 217340 kb
Host smart-94097e24-d6ea-4e74-99bd-4efd15424747
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027999872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.3
027999872
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3131051301
Short name T336
Test name
Test status
Simulation time 2512573593 ps
CPU time 7.27 seconds
Started Jul 11 06:19:56 PM PDT 24
Finished Jul 11 06:20:05 PM PDT 24
Peak memory 224148 kb
Host smart-25b2b260-fe79-4b28-bf00-56f9841253c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131051301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3131051301
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3421415393
Short name T727
Test name
Test status
Simulation time 2854149199 ps
CPU time 36.84 seconds
Started Jul 11 06:20:01 PM PDT 24
Finished Jul 11 06:20:41 PM PDT 24
Peak memory 217204 kb
Host smart-7258b8d8-f003-4ac6-a595-f5dbd660e9e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421415393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3421415393
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1343308670
Short name T483
Test name
Test status
Simulation time 626104068 ps
CPU time 5.35 seconds
Started Jul 11 06:19:56 PM PDT 24
Finished Jul 11 06:20:04 PM PDT 24
Peak memory 217192 kb
Host smart-5689cfd5-5f10-4dde-a39a-76c32b523dfd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343308670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1343308670
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.4073710949
Short name T158
Test name
Test status
Simulation time 2638127875 ps
CPU time 63.06 seconds
Started Jul 11 06:19:57 PM PDT 24
Finished Jul 11 06:21:03 PM PDT 24
Peak memory 266912 kb
Host smart-0f1b7cfa-8f06-4b0a-a6f6-27b2a2f51be6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073710949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.4073710949
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2557291856
Short name T460
Test name
Test status
Simulation time 344595113 ps
CPU time 11.42 seconds
Started Jul 11 06:19:54 PM PDT 24
Finished Jul 11 06:20:07 PM PDT 24
Peak memory 250380 kb
Host smart-ced4d8d8-db90-4467-bef7-8ddc0faf6619
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557291856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2557291856
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.976814257
Short name T190
Test name
Test status
Simulation time 284273331 ps
CPU time 3.16 seconds
Started Jul 11 06:19:57 PM PDT 24
Finished Jul 11 06:20:03 PM PDT 24
Peak memory 222184 kb
Host smart-a528ff62-e3a0-4f46-bd24-36441dcdd7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976814257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.976814257
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.482445815
Short name T63
Test name
Test status
Simulation time 207855321 ps
CPU time 5.47 seconds
Started Jul 11 06:20:06 PM PDT 24
Finished Jul 11 06:20:14 PM PDT 24
Peak memory 217220 kb
Host smart-73dddab0-a00a-4f50-8864-fb3a7d43d7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482445815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.482445815
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2104835058
Short name T95
Test name
Test status
Simulation time 224302628 ps
CPU time 24.35 seconds
Started Jul 11 06:20:01 PM PDT 24
Finished Jul 11 06:20:27 PM PDT 24
Peak memory 268592 kb
Host smart-3c199834-3491-47fc-981c-e549699950e4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104835058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2104835058
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3440198543
Short name T398
Test name
Test status
Simulation time 222912991 ps
CPU time 9 seconds
Started Jul 11 06:20:03 PM PDT 24
Finished Jul 11 06:20:15 PM PDT 24
Peak memory 225128 kb
Host smart-3a15b1fa-cc8c-4410-8258-1877328faf19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440198543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3440198543
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.626335716
Short name T363
Test name
Test status
Simulation time 308335117 ps
CPU time 14.83 seconds
Started Jul 11 06:19:59 PM PDT 24
Finished Jul 11 06:20:16 PM PDT 24
Peak memory 225688 kb
Host smart-b693ef65-9034-46b8-addb-869ede8bff1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626335716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig
est.626335716
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.249957526
Short name T322
Test name
Test status
Simulation time 463380549 ps
CPU time 15.09 seconds
Started Jul 11 06:20:02 PM PDT 24
Finished Jul 11 06:20:19 PM PDT 24
Peak memory 225524 kb
Host smart-b91449ed-e6ce-409f-be5a-c5679ec2dd7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249957526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.249957526
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.1999488447
Short name T253
Test name
Test status
Simulation time 228258745 ps
CPU time 6.81 seconds
Started Jul 11 06:19:56 PM PDT 24
Finished Jul 11 06:20:05 PM PDT 24
Peak memory 217904 kb
Host smart-ee0e6ebc-63bd-486d-ae4f-b3f8c9d28994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999488447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1999488447
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3659272519
Short name T199
Test name
Test status
Simulation time 103506531 ps
CPU time 2.29 seconds
Started Jul 11 06:20:06 PM PDT 24
Finished Jul 11 06:20:10 PM PDT 24
Peak memory 214108 kb
Host smart-f66ff589-68ed-44d6-be7e-fd81edbd5601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659272519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3659272519
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3678112275
Short name T258
Test name
Test status
Simulation time 701621219 ps
CPU time 35.16 seconds
Started Jul 11 06:20:01 PM PDT 24
Finished Jul 11 06:20:39 PM PDT 24
Peak memory 250548 kb
Host smart-51b415bb-2351-41c4-92da-92d8bcbafe39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678112275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3678112275
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2640865247
Short name T713
Test name
Test status
Simulation time 98425961 ps
CPU time 9.18 seconds
Started Jul 11 06:19:54 PM PDT 24
Finished Jul 11 06:20:04 PM PDT 24
Peak memory 250716 kb
Host smart-146d2597-1bc0-47f2-ae93-e8dc5788be23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640865247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2640865247
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1171191131
Short name T637
Test name
Test status
Simulation time 7299510576 ps
CPU time 57.36 seconds
Started Jul 11 06:20:02 PM PDT 24
Finished Jul 11 06:21:01 PM PDT 24
Peak memory 250780 kb
Host smart-90a522c0-f7f9-482c-870e-3110cc664d70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171191131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1171191131
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2803592139
Short name T407
Test name
Test status
Simulation time 86968999 ps
CPU time 1.04 seconds
Started Jul 11 06:19:54 PM PDT 24
Finished Jul 11 06:19:56 PM PDT 24
Peak memory 211420 kb
Host smart-ac0e2bda-2cfe-4c8f-b409-b4e56fcec0f9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803592139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2803592139
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3544291094
Short name T579
Test name
Test status
Simulation time 17988218 ps
CPU time 1.15 seconds
Started Jul 11 06:20:07 PM PDT 24
Finished Jul 11 06:20:10 PM PDT 24
Peak memory 208524 kb
Host smart-e958b444-6ffd-4657-98ca-243c84c1db8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544291094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3544291094
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.924149562
Short name T328
Test name
Test status
Simulation time 1161182854 ps
CPU time 11.49 seconds
Started Jul 11 06:20:00 PM PDT 24
Finished Jul 11 06:20:14 PM PDT 24
Peak memory 225592 kb
Host smart-b80a0c30-7cf5-4267-904e-0672a13e7d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924149562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.924149562
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1682270268
Short name T492
Test name
Test status
Simulation time 1271585703 ps
CPU time 9.14 seconds
Started Jul 11 06:20:05 PM PDT 24
Finished Jul 11 06:20:17 PM PDT 24
Peak memory 217188 kb
Host smart-384b902e-a16d-42b3-b8cd-488c0ea13f3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682270268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1682270268
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.592302372
Short name T860
Test name
Test status
Simulation time 4224282712 ps
CPU time 36.19 seconds
Started Jul 11 06:20:07 PM PDT 24
Finished Jul 11 06:20:45 PM PDT 24
Peak memory 218280 kb
Host smart-d901eff6-5124-4693-b436-d8a356c60480
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592302372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.592302372
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3531352019
Short name T153
Test name
Test status
Simulation time 227119596 ps
CPU time 3.08 seconds
Started Jul 11 06:20:07 PM PDT 24
Finished Jul 11 06:20:12 PM PDT 24
Peak memory 217264 kb
Host smart-347af5f7-f0c7-4d4c-85bc-cb1e1b4002da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531352019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3
531352019
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1322278548
Short name T802
Test name
Test status
Simulation time 3136720153 ps
CPU time 16.32 seconds
Started Jul 11 06:20:12 PM PDT 24
Finished Jul 11 06:20:30 PM PDT 24
Peak memory 224252 kb
Host smart-1799c7e6-74e5-4851-aa29-ffff5ea35f44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322278548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1322278548
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2159352935
Short name T3
Test name
Test status
Simulation time 2373370276 ps
CPU time 19 seconds
Started Jul 11 06:20:05 PM PDT 24
Finished Jul 11 06:20:27 PM PDT 24
Peak memory 217200 kb
Host smart-fc8c8ade-58fc-4395-b31f-ee74c0672916
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159352935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2159352935
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1987998211
Short name T318
Test name
Test status
Simulation time 435967248 ps
CPU time 5.63 seconds
Started Jul 11 06:20:02 PM PDT 24
Finished Jul 11 06:20:10 PM PDT 24
Peak memory 217116 kb
Host smart-4af16a43-4433-4c07-89a1-66429104dee7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987998211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1987998211
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2895240821
Short name T723
Test name
Test status
Simulation time 3958950883 ps
CPU time 71.3 seconds
Started Jul 11 06:20:05 PM PDT 24
Finished Jul 11 06:21:19 PM PDT 24
Peak memory 278312 kb
Host smart-1f08cf54-bbbb-4906-b8a5-1a357e3e0a07
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895240821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2895240821
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2079014061
Short name T623
Test name
Test status
Simulation time 3384846196 ps
CPU time 15.3 seconds
Started Jul 11 06:20:03 PM PDT 24
Finished Jul 11 06:20:20 PM PDT 24
Peak memory 250748 kb
Host smart-7299d7ba-39e0-4c60-8697-0b9e90c5d264
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079014061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2079014061
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1538272961
Short name T8
Test name
Test status
Simulation time 50837151 ps
CPU time 2.84 seconds
Started Jul 11 06:20:03 PM PDT 24
Finished Jul 11 06:20:09 PM PDT 24
Peak memory 221820 kb
Host smart-67b49058-4a3e-4e5f-9b4c-fd2329ee3a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538272961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1538272961
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.558962668
Short name T728
Test name
Test status
Simulation time 1426470457 ps
CPU time 22.64 seconds
Started Jul 11 06:20:02 PM PDT 24
Finished Jul 11 06:20:27 PM PDT 24
Peak memory 214336 kb
Host smart-649cb38f-fd25-4fbc-adc9-90cebc1af6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558962668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.558962668
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2193178638
Short name T410
Test name
Test status
Simulation time 377375777 ps
CPU time 17.01 seconds
Started Jul 11 06:20:05 PM PDT 24
Finished Jul 11 06:20:24 PM PDT 24
Peak memory 218424 kb
Host smart-cedb9f5a-e1b4-469f-b980-931bf0603b4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193178638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2193178638
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.932250504
Short name T378
Test name
Test status
Simulation time 799741869 ps
CPU time 13.34 seconds
Started Jul 11 06:20:04 PM PDT 24
Finished Jul 11 06:20:20 PM PDT 24
Peak memory 225480 kb
Host smart-d810537c-548f-40d5-acf9-76af4656ec15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932250504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.932250504
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3062898743
Short name T569
Test name
Test status
Simulation time 260184769 ps
CPU time 9.19 seconds
Started Jul 11 06:24:35 PM PDT 24
Finished Jul 11 06:24:53 PM PDT 24
Peak memory 217736 kb
Host smart-5221fcda-ec93-46eb-b995-21975af4a07a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062898743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
062898743
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1172434964
Short name T316
Test name
Test status
Simulation time 447263372 ps
CPU time 11.24 seconds
Started Jul 11 06:19:59 PM PDT 24
Finished Jul 11 06:20:13 PM PDT 24
Peak memory 225592 kb
Host smart-21495afc-9bc2-4b70-b056-b704340e1596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172434964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1172434964
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.167812431
Short name T766
Test name
Test status
Simulation time 89752545 ps
CPU time 2.16 seconds
Started Jul 11 06:20:01 PM PDT 24
Finished Jul 11 06:20:06 PM PDT 24
Peak memory 217204 kb
Host smart-6d892aad-076b-4d89-ac53-91a909a1f2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167812431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.167812431
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2244875712
Short name T682
Test name
Test status
Simulation time 1115402777 ps
CPU time 35.61 seconds
Started Jul 11 06:20:02 PM PDT 24
Finished Jul 11 06:20:40 PM PDT 24
Peak memory 246004 kb
Host smart-86aaaa2c-ee5e-4d85-8897-4cf92dc63178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244875712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2244875712
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2932554360
Short name T335
Test name
Test status
Simulation time 193077227 ps
CPU time 9.82 seconds
Started Jul 11 06:19:57 PM PDT 24
Finished Jul 11 06:20:09 PM PDT 24
Peak memory 250552 kb
Host smart-9d2d59c4-d4db-4707-a66e-901d52ba4470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932554360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2932554360
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.1923077543
Short name T749
Test name
Test status
Simulation time 6885175826 ps
CPU time 143.38 seconds
Started Jul 11 06:20:08 PM PDT 24
Finished Jul 11 06:22:33 PM PDT 24
Peak memory 310160 kb
Host smart-7ec3c77b-2d6b-4da0-aa8d-13745212781c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923077543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.1923077543
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2174540386
Short name T548
Test name
Test status
Simulation time 50299077 ps
CPU time 0.95 seconds
Started Jul 11 06:20:03 PM PDT 24
Finished Jul 11 06:20:06 PM PDT 24
Peak memory 208556 kb
Host smart-bb10463c-9387-4f45-b8bc-98a482ba8147
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174540386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2174540386
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3306550628
Short name T633
Test name
Test status
Simulation time 16596327 ps
CPU time 0.86 seconds
Started Jul 11 06:20:50 PM PDT 24
Finished Jul 11 06:20:54 PM PDT 24
Peak memory 208492 kb
Host smart-f453f9d3-212d-48b6-84e4-bdc36f75882e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306550628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3306550628
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3967874388
Short name T192
Test name
Test status
Simulation time 984994088 ps
CPU time 11.84 seconds
Started Jul 11 06:20:51 PM PDT 24
Finished Jul 11 06:21:06 PM PDT 24
Peak memory 217764 kb
Host smart-0e549233-9105-4a0a-8bec-bd70729bb40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967874388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3967874388
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.786638233
Short name T853
Test name
Test status
Simulation time 4096059344 ps
CPU time 23.76 seconds
Started Jul 11 06:20:56 PM PDT 24
Finished Jul 11 06:21:23 PM PDT 24
Peak memory 217280 kb
Host smart-b7232b16-7bfe-4810-9a5a-da4413e77eab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786638233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.786638233
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1184608795
Short name T324
Test name
Test status
Simulation time 2197120464 ps
CPU time 62.23 seconds
Started Jul 11 06:20:54 PM PDT 24
Finished Jul 11 06:22:00 PM PDT 24
Peak memory 218432 kb
Host smart-bf2dd90d-4db3-48bb-8e3d-6e4591c14865
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184608795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1184608795
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.382364766
Short name T297
Test name
Test status
Simulation time 1775566229 ps
CPU time 8.59 seconds
Started Jul 11 06:20:52 PM PDT 24
Finished Jul 11 06:21:04 PM PDT 24
Peak memory 217844 kb
Host smart-929c7da5-f4e3-48fd-ace7-a8eb361a8d4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382364766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_prog_failure.382364766
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1569333257
Short name T218
Test name
Test status
Simulation time 312656203 ps
CPU time 8.6 seconds
Started Jul 11 06:20:53 PM PDT 24
Finished Jul 11 06:21:06 PM PDT 24
Peak memory 217044 kb
Host smart-3c3f82be-1d9c-4a52-ba99-8792297cee76
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569333257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1569333257
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2795501461
Short name T558
Test name
Test status
Simulation time 2698794975 ps
CPU time 84.91 seconds
Started Jul 11 06:20:59 PM PDT 24
Finished Jul 11 06:22:27 PM PDT 24
Peak memory 280268 kb
Host smart-b690515c-9151-44fd-af71-b8a265e6bfcb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795501461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2795501461
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2412808854
Short name T667
Test name
Test status
Simulation time 1242889891 ps
CPU time 10.3 seconds
Started Jul 11 06:20:59 PM PDT 24
Finished Jul 11 06:21:13 PM PDT 24
Peak memory 217708 kb
Host smart-6f0ffbb6-245f-4b8d-aa44-2fdd4bb2b389
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412808854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2412808854
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.3977294107
Short name T659
Test name
Test status
Simulation time 77082856 ps
CPU time 1.75 seconds
Started Jul 11 06:20:50 PM PDT 24
Finished Jul 11 06:20:55 PM PDT 24
Peak memory 221464 kb
Host smart-f8ca9822-14de-45fd-a98e-72c6141a8c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977294107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3977294107
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.379051142
Short name T805
Test name
Test status
Simulation time 3713837898 ps
CPU time 19.04 seconds
Started Jul 11 06:20:52 PM PDT 24
Finished Jul 11 06:21:15 PM PDT 24
Peak memory 225572 kb
Host smart-d9a55bbd-46c6-4a2e-bb82-237671fe75a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379051142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.379051142
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.4195367741
Short name T698
Test name
Test status
Simulation time 383868920 ps
CPU time 9.22 seconds
Started Jul 11 06:20:49 PM PDT 24
Finished Jul 11 06:21:01 PM PDT 24
Peak memory 217744 kb
Host smart-f0f49048-287f-491f-8fd3-0a14b68822c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195367741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
4195367741
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2854873917
Short name T226
Test name
Test status
Simulation time 1376416660 ps
CPU time 8.63 seconds
Started Jul 11 06:20:47 PM PDT 24
Finished Jul 11 06:20:58 PM PDT 24
Peak memory 224168 kb
Host smart-93cfcfc9-933d-43ac-b9f4-4b039f474d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854873917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2854873917
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.2881087172
Short name T333
Test name
Test status
Simulation time 247907231 ps
CPU time 1.5 seconds
Started Jul 11 06:20:52 PM PDT 24
Finished Jul 11 06:20:57 PM PDT 24
Peak memory 213328 kb
Host smart-9ade9f7c-1127-4b93-8de1-af428de4fedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881087172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2881087172
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1644128537
Short name T286
Test name
Test status
Simulation time 214177818 ps
CPU time 25.94 seconds
Started Jul 11 06:20:48 PM PDT 24
Finished Jul 11 06:21:17 PM PDT 24
Peak memory 250712 kb
Host smart-8aaf3ca9-0f32-4c8e-8dd7-8ebd800d29fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644128537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1644128537
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.86449969
Short name T459
Test name
Test status
Simulation time 49181132 ps
CPU time 6.18 seconds
Started Jul 11 06:20:44 PM PDT 24
Finished Jul 11 06:20:53 PM PDT 24
Peak memory 245984 kb
Host smart-72853fcf-8312-48ae-91a8-d9c59ba41789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86449969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.86449969
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.837186264
Short name T685
Test name
Test status
Simulation time 25361144313 ps
CPU time 180.22 seconds
Started Jul 11 06:20:54 PM PDT 24
Finished Jul 11 06:23:58 PM PDT 24
Peak memory 220484 kb
Host smart-272529a5-33ce-497f-b4e9-d4f48bdf0122
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837186264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.837186264
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.691228134
Short name T570
Test name
Test status
Simulation time 28905392823 ps
CPU time 307.93 seconds
Started Jul 11 06:21:03 PM PDT 24
Finished Jul 11 06:26:16 PM PDT 24
Peak memory 283228 kb
Host smart-a9b92f68-2f5d-42de-bbdf-38611eb95538
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=691228134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.691228134
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3610380944
Short name T818
Test name
Test status
Simulation time 31466847 ps
CPU time 1.06 seconds
Started Jul 11 06:20:48 PM PDT 24
Finished Jul 11 06:20:52 PM PDT 24
Peak memory 211388 kb
Host smart-cae92d6a-2c86-4441-8f1e-c70ccbaa5048
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610380944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3610380944
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3463557294
Short name T306
Test name
Test status
Simulation time 72740226 ps
CPU time 0.81 seconds
Started Jul 11 06:20:51 PM PDT 24
Finished Jul 11 06:20:55 PM PDT 24
Peak memory 208624 kb
Host smart-cd12f27b-42ce-41af-b14e-c55fb12ffad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463557294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3463557294
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3683759587
Short name T756
Test name
Test status
Simulation time 976490687 ps
CPU time 10.49 seconds
Started Jul 11 06:20:49 PM PDT 24
Finished Jul 11 06:21:03 PM PDT 24
Peak memory 225596 kb
Host smart-c5e3a997-cd91-4d79-81e7-6854e9c9e518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683759587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3683759587
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3960311292
Short name T476
Test name
Test status
Simulation time 41221187 ps
CPU time 1.73 seconds
Started Jul 11 06:21:05 PM PDT 24
Finished Jul 11 06:21:12 PM PDT 24
Peak memory 217064 kb
Host smart-1ea40026-1448-47ba-aed4-fa7c883cfef3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960311292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3960311292
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2839738508
Short name T781
Test name
Test status
Simulation time 16037000656 ps
CPU time 54.75 seconds
Started Jul 11 06:21:05 PM PDT 24
Finished Jul 11 06:22:06 PM PDT 24
Peak memory 218292 kb
Host smart-da8761ad-176a-4a3b-921d-2bcb5475418a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839738508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2839738508
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.43560273
Short name T826
Test name
Test status
Simulation time 1181750167 ps
CPU time 5.35 seconds
Started Jul 11 06:20:53 PM PDT 24
Finished Jul 11 06:21:02 PM PDT 24
Peak memory 217624 kb
Host smart-29d47737-3db4-4cd7-931a-44d3ae997403
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43560273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_
prog_failure.43560273
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.797040405
Short name T521
Test name
Test status
Simulation time 68431102 ps
CPU time 2.61 seconds
Started Jul 11 06:20:52 PM PDT 24
Finished Jul 11 06:20:59 PM PDT 24
Peak memory 217136 kb
Host smart-0bbfbc4c-f92a-482c-a0c2-bc261e1e3db7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797040405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
797040405
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3853375268
Short name T744
Test name
Test status
Simulation time 1316771056 ps
CPU time 44.58 seconds
Started Jul 11 06:20:49 PM PDT 24
Finished Jul 11 06:21:37 PM PDT 24
Peak memory 250456 kb
Host smart-16129c4a-2bee-4651-83f4-244ea8fc7cc1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853375268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3853375268
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.427098303
Short name T832
Test name
Test status
Simulation time 668426056 ps
CPU time 15.95 seconds
Started Jul 11 06:20:52 PM PDT 24
Finished Jul 11 06:21:12 PM PDT 24
Peak memory 250312 kb
Host smart-448b620b-4db1-4995-bcfa-a9bb20132981
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427098303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
jtag_state_post_trans.427098303
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1953045009
Short name T478
Test name
Test status
Simulation time 281943097 ps
CPU time 3.51 seconds
Started Jul 11 06:20:50 PM PDT 24
Finished Jul 11 06:20:57 PM PDT 24
Peak memory 222040 kb
Host smart-574b3390-1a38-43b3-9ab4-a164b1458b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953045009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1953045009
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1005345129
Short name T607
Test name
Test status
Simulation time 1717469455 ps
CPU time 15.73 seconds
Started Jul 11 06:20:54 PM PDT 24
Finished Jul 11 06:21:13 PM PDT 24
Peak memory 225588 kb
Host smart-ba696855-7515-4e71-985e-dc60c4223038
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005345129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1005345129
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.738086866
Short name T405
Test name
Test status
Simulation time 1619008749 ps
CPU time 13.07 seconds
Started Jul 11 06:20:55 PM PDT 24
Finished Jul 11 06:21:12 PM PDT 24
Peak memory 217804 kb
Host smart-f6f96e4f-e40a-4914-9e46-e4771825e76c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738086866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.738086866
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1930699360
Short name T414
Test name
Test status
Simulation time 386878408 ps
CPU time 9.45 seconds
Started Jul 11 06:20:53 PM PDT 24
Finished Jul 11 06:21:07 PM PDT 24
Peak memory 225564 kb
Host smart-c9c84aa6-1852-4e82-a37f-c0e88bc1c615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930699360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1930699360
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3734083807
Short name T442
Test name
Test status
Simulation time 136141869 ps
CPU time 1.35 seconds
Started Jul 11 06:20:52 PM PDT 24
Finished Jul 11 06:20:57 PM PDT 24
Peak memory 213304 kb
Host smart-e67edc97-fc9d-4786-a447-1eb370d408e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734083807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3734083807
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1164759450
Short name T535
Test name
Test status
Simulation time 2511853645 ps
CPU time 18.31 seconds
Started Jul 11 06:21:05 PM PDT 24
Finished Jul 11 06:21:29 PM PDT 24
Peak memory 250440 kb
Host smart-f6dde4db-2706-464c-8530-511d3b4d671f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164759450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1164759450
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2885552844
Short name T573
Test name
Test status
Simulation time 93396832 ps
CPU time 7.64 seconds
Started Jul 11 06:20:50 PM PDT 24
Finished Jul 11 06:21:02 PM PDT 24
Peak memory 250544 kb
Host smart-08837059-7c93-47a3-85a2-a06560141538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885552844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2885552844
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.166901499
Short name T712
Test name
Test status
Simulation time 23504476744 ps
CPU time 124.97 seconds
Started Jul 11 06:21:05 PM PDT 24
Finished Jul 11 06:23:14 PM PDT 24
Peak memory 274676 kb
Host smart-92482d2b-8416-4720-bb27-015e632aa763
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166901499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.166901499
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1043887403
Short name T210
Test name
Test status
Simulation time 11524527 ps
CPU time 0.91 seconds
Started Jul 11 06:20:51 PM PDT 24
Finished Jul 11 06:20:55 PM PDT 24
Peak memory 208656 kb
Host smart-948a91aa-4145-49bc-92bf-d46e8798c3b7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043887403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1043887403
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3718350467
Short name T62
Test name
Test status
Simulation time 25614901 ps
CPU time 1.4 seconds
Started Jul 11 06:20:58 PM PDT 24
Finished Jul 11 06:21:03 PM PDT 24
Peak memory 208544 kb
Host smart-25a51181-abcc-4e9f-b665-069179ee3aa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718350467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3718350467
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.424015923
Short name T418
Test name
Test status
Simulation time 1545069118 ps
CPU time 14.48 seconds
Started Jul 11 06:20:57 PM PDT 24
Finished Jul 11 06:21:16 PM PDT 24
Peak memory 225572 kb
Host smart-6c677dfa-3864-4d2a-80dc-db7b04ee7582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424015923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.424015923
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.316567577
Short name T609
Test name
Test status
Simulation time 4720834897 ps
CPU time 15.26 seconds
Started Jul 11 06:20:56 PM PDT 24
Finished Jul 11 06:21:15 PM PDT 24
Peak memory 217340 kb
Host smart-ec819654-eec0-4bb5-902b-e1cf5ff34f68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316567577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.316567577
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1281194051
Short name T92
Test name
Test status
Simulation time 2342120775 ps
CPU time 68.08 seconds
Started Jul 11 06:20:56 PM PDT 24
Finished Jul 11 06:22:08 PM PDT 24
Peak memory 218708 kb
Host smart-3b7b2044-b526-4890-8bf2-5b551edd9837
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281194051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1281194051
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.467121580
Short name T837
Test name
Test status
Simulation time 2103853627 ps
CPU time 15.53 seconds
Started Jul 11 06:20:58 PM PDT 24
Finished Jul 11 06:21:17 PM PDT 24
Peak memory 217728 kb
Host smart-8b5b8a7d-e044-4c7a-998e-674dac11eb6e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467121580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.467121580
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3888176155
Short name T666
Test name
Test status
Simulation time 141022271 ps
CPU time 3.68 seconds
Started Jul 11 06:21:00 PM PDT 24
Finished Jul 11 06:21:07 PM PDT 24
Peak memory 217048 kb
Host smart-a3ce414d-53a9-40d2-8027-b1fcc16723f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888176155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3888176155
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.991443601
Short name T797
Test name
Test status
Simulation time 5500362081 ps
CPU time 56.8 seconds
Started Jul 11 06:21:05 PM PDT 24
Finished Jul 11 06:22:07 PM PDT 24
Peak memory 282660 kb
Host smart-757cb64e-71df-4efe-8dbc-f9cd129d4834
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991443601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_state_failure.991443601
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1041682685
Short name T430
Test name
Test status
Simulation time 4080673059 ps
CPU time 18.23 seconds
Started Jul 11 06:21:05 PM PDT 24
Finished Jul 11 06:21:29 PM PDT 24
Peak memory 218436 kb
Host smart-576cb562-89d9-4f64-bf9d-a8e5bf0c9f51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041682685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1041682685
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2044108413
Short name T811
Test name
Test status
Simulation time 60883917 ps
CPU time 2.29 seconds
Started Jul 11 06:20:59 PM PDT 24
Finished Jul 11 06:21:05 PM PDT 24
Peak memory 221628 kb
Host smart-42e408f9-3e3d-4c52-acbc-7bd1bb98abf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044108413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2044108413
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.3242092004
Short name T331
Test name
Test status
Simulation time 1580805481 ps
CPU time 12.75 seconds
Started Jul 11 06:20:59 PM PDT 24
Finished Jul 11 06:21:15 PM PDT 24
Peak memory 218428 kb
Host smart-a9407086-216f-4dad-9440-8b75fc8f345c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242092004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3242092004
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.959375947
Short name T779
Test name
Test status
Simulation time 2394958690 ps
CPU time 14.19 seconds
Started Jul 11 06:20:57 PM PDT 24
Finished Jul 11 06:21:15 PM PDT 24
Peak memory 225536 kb
Host smart-560ced0d-2a9a-4379-a530-d288f6f885e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959375947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.959375947
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3686072899
Short name T45
Test name
Test status
Simulation time 1413289935 ps
CPU time 11.33 seconds
Started Jul 11 06:20:56 PM PDT 24
Finished Jul 11 06:21:12 PM PDT 24
Peak memory 217840 kb
Host smart-9b4c25db-1932-4dd5-b59f-a3bdb1e52111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686072899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3686072899
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1834267535
Short name T589
Test name
Test status
Simulation time 93522584 ps
CPU time 4.66 seconds
Started Jul 11 06:20:48 PM PDT 24
Finished Jul 11 06:20:56 PM PDT 24
Peak memory 217220 kb
Host smart-db207821-d695-4be9-8e6c-8ae93f40b163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834267535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1834267535
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.329147598
Short name T313
Test name
Test status
Simulation time 219774175 ps
CPU time 24.99 seconds
Started Jul 11 06:20:53 PM PDT 24
Finished Jul 11 06:21:21 PM PDT 24
Peak memory 250692 kb
Host smart-65868896-5139-4ba1-84fb-afd3140374c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329147598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.329147598
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1065804645
Short name T229
Test name
Test status
Simulation time 166111122 ps
CPU time 8.34 seconds
Started Jul 11 06:20:51 PM PDT 24
Finished Jul 11 06:21:03 PM PDT 24
Peak memory 249948 kb
Host smart-0d8ab545-8a4a-46bf-8865-5c596efbdc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065804645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1065804645
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2372473097
Short name T580
Test name
Test status
Simulation time 14174259747 ps
CPU time 110.7 seconds
Started Jul 11 06:20:57 PM PDT 24
Finished Jul 11 06:22:52 PM PDT 24
Peak memory 268692 kb
Host smart-480914f8-ed2f-4523-8b10-1d182dfe84c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372473097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2372473097
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1962100343
Short name T421
Test name
Test status
Simulation time 41721506 ps
CPU time 0.8 seconds
Started Jul 11 06:20:52 PM PDT 24
Finished Jul 11 06:20:57 PM PDT 24
Peak memory 208172 kb
Host smart-6e903ed1-1404-48e7-bb6a-40f42c6c3505
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962100343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1962100343
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2610771039
Short name T542
Test name
Test status
Simulation time 172736089 ps
CPU time 1.26 seconds
Started Jul 11 06:20:59 PM PDT 24
Finished Jul 11 06:21:04 PM PDT 24
Peak memory 208616 kb
Host smart-1f5caf93-f8ea-4b8b-9df7-90fbf5edc5b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610771039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2610771039
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1854063551
Short name T520
Test name
Test status
Simulation time 236538933 ps
CPU time 9.99 seconds
Started Jul 11 06:20:58 PM PDT 24
Finished Jul 11 06:21:12 PM PDT 24
Peak memory 217808 kb
Host smart-c1b7fbc8-1bbc-48cf-917e-af3fead180a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854063551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1854063551
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.18310865
Short name T672
Test name
Test status
Simulation time 2323764155 ps
CPU time 7.93 seconds
Started Jul 11 06:20:59 PM PDT 24
Finished Jul 11 06:21:10 PM PDT 24
Peak memory 216868 kb
Host smart-c2d5846f-9530-4c94-bdfd-d05de0dce31c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18310865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.18310865
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1047960967
Short name T99
Test name
Test status
Simulation time 14573118698 ps
CPU time 45.06 seconds
Started Jul 11 06:20:57 PM PDT 24
Finished Jul 11 06:21:46 PM PDT 24
Peak memory 218208 kb
Host smart-a1d2dc73-8848-48b5-9f13-6a1f0ba8c21a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047960967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1047960967
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2628147731
Short name T207
Test name
Test status
Simulation time 312818010 ps
CPU time 9.9 seconds
Started Jul 11 06:20:57 PM PDT 24
Finished Jul 11 06:21:11 PM PDT 24
Peak memory 217724 kb
Host smart-1c5408e1-427e-4f95-9c52-68c813a6eae6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628147731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2628147731
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2384275678
Short name T96
Test name
Test status
Simulation time 1677916592 ps
CPU time 5.5 seconds
Started Jul 11 06:20:56 PM PDT 24
Finished Jul 11 06:21:06 PM PDT 24
Peak memory 217132 kb
Host smart-9af4385e-0925-4054-a2e4-9e879ada7a77
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384275678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2384275678
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1608071583
Short name T406
Test name
Test status
Simulation time 1449177191 ps
CPU time 55.66 seconds
Started Jul 11 06:20:59 PM PDT 24
Finished Jul 11 06:21:58 PM PDT 24
Peak memory 266948 kb
Host smart-0305ec83-8bbe-4dd7-941e-b6c15b437f06
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608071583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1608071583
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3836304176
Short name T211
Test name
Test status
Simulation time 2508872097 ps
CPU time 39.4 seconds
Started Jul 11 06:20:58 PM PDT 24
Finished Jul 11 06:21:41 PM PDT 24
Peak memory 250520 kb
Host smart-b7e10430-099b-4b41-8ace-e5ac149ed2df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836304176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3836304176
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3802633257
Short name T473
Test name
Test status
Simulation time 164055761 ps
CPU time 4.26 seconds
Started Jul 11 06:20:57 PM PDT 24
Finished Jul 11 06:21:05 PM PDT 24
Peak memory 217796 kb
Host smart-1cc91dd1-4f91-4641-8d7b-61ec8d8779f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802633257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3802633257
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2071171318
Short name T841
Test name
Test status
Simulation time 3324683699 ps
CPU time 12.81 seconds
Started Jul 11 06:20:59 PM PDT 24
Finished Jul 11 06:21:15 PM PDT 24
Peak memory 218492 kb
Host smart-5d53db3b-809a-41ca-a861-ae45fbcebf7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071171318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2071171318
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2137355862
Short name T498
Test name
Test status
Simulation time 972952978 ps
CPU time 14.01 seconds
Started Jul 11 06:21:00 PM PDT 24
Finished Jul 11 06:21:17 PM PDT 24
Peak memory 225532 kb
Host smart-e3ca667d-bd67-4b82-8bd9-a7cca23b0ae1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137355862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2137355862
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.828365036
Short name T423
Test name
Test status
Simulation time 414050898 ps
CPU time 9.45 seconds
Started Jul 11 06:20:56 PM PDT 24
Finished Jul 11 06:21:09 PM PDT 24
Peak memory 217740 kb
Host smart-19dbc548-bbe7-4f13-bdd5-8eff1c713bce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828365036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.828365036
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3338726936
Short name T461
Test name
Test status
Simulation time 1266216761 ps
CPU time 10.02 seconds
Started Jul 11 06:20:55 PM PDT 24
Finished Jul 11 06:21:09 PM PDT 24
Peak memory 224300 kb
Host smart-4e0fbf30-320d-4564-a118-57e77bdf0721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338726936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3338726936
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3296361379
Short name T824
Test name
Test status
Simulation time 69510796 ps
CPU time 2.99 seconds
Started Jul 11 06:20:59 PM PDT 24
Finished Jul 11 06:21:06 PM PDT 24
Peak memory 213880 kb
Host smart-d58f9ea0-dadb-45cf-90a4-fd785adb445a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296361379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3296361379
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.979909835
Short name T839
Test name
Test status
Simulation time 1072860999 ps
CPU time 24.97 seconds
Started Jul 11 06:20:59 PM PDT 24
Finished Jul 11 06:21:28 PM PDT 24
Peak memory 250608 kb
Host smart-485572e0-8c95-4ca2-bad9-2a6cf034e1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979909835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.979909835
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2014499544
Short name T848
Test name
Test status
Simulation time 143752022 ps
CPU time 8.31 seconds
Started Jul 11 06:20:57 PM PDT 24
Finished Jul 11 06:21:09 PM PDT 24
Peak memory 250532 kb
Host smart-b0ea87bf-fa44-4cbc-a2bf-15fb23543ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014499544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2014499544
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1355030759
Short name T254
Test name
Test status
Simulation time 6380690231 ps
CPU time 102.78 seconds
Started Jul 11 06:21:00 PM PDT 24
Finished Jul 11 06:22:47 PM PDT 24
Peak memory 221476 kb
Host smart-3949bb3f-bf29-47d8-b19e-5ce4f01114f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355030759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1355030759
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2548622289
Short name T575
Test name
Test status
Simulation time 15037753 ps
CPU time 0.96 seconds
Started Jul 11 06:21:05 PM PDT 24
Finished Jul 11 06:21:12 PM PDT 24
Peak memory 208508 kb
Host smart-23114f22-555e-4934-b71e-2873aab7b2dd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548622289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2548622289
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.356654132
Short name T468
Test name
Test status
Simulation time 24151959 ps
CPU time 0.89 seconds
Started Jul 11 06:21:05 PM PDT 24
Finished Jul 11 06:21:10 PM PDT 24
Peak memory 208576 kb
Host smart-60b65e95-3445-42ce-9c8f-2218a72ccbc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356654132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.356654132
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2175858514
Short name T628
Test name
Test status
Simulation time 993546176 ps
CPU time 9.5 seconds
Started Jul 11 06:21:04 PM PDT 24
Finished Jul 11 06:21:18 PM PDT 24
Peak memory 217648 kb
Host smart-444dca8a-e966-4422-b40b-992a18fb821d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175858514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2175858514
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.162965909
Short name T776
Test name
Test status
Simulation time 208829348 ps
CPU time 2 seconds
Started Jul 11 06:21:01 PM PDT 24
Finished Jul 11 06:21:07 PM PDT 24
Peak memory 216692 kb
Host smart-e3840da4-800c-4a50-95d5-faa0860e2615
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162965909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.162965909
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.982486157
Short name T491
Test name
Test status
Simulation time 6346086831 ps
CPU time 29.68 seconds
Started Jul 11 06:21:03 PM PDT 24
Finished Jul 11 06:21:36 PM PDT 24
Peak memory 218572 kb
Host smart-7924baad-813e-4a64-bcf1-a4fcd779f012
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982486157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.982486157
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3808417468
Short name T479
Test name
Test status
Simulation time 1065041533 ps
CPU time 2.62 seconds
Started Jul 11 06:21:02 PM PDT 24
Finished Jul 11 06:21:08 PM PDT 24
Peak memory 217736 kb
Host smart-0fe95810-99a2-49fd-b718-dab037e03ffd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808417468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3808417468
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2428804905
Short name T247
Test name
Test status
Simulation time 96882132 ps
CPU time 3.48 seconds
Started Jul 11 06:21:08 PM PDT 24
Finished Jul 11 06:21:17 PM PDT 24
Peak memory 217216 kb
Host smart-fcf44ea4-6d85-46dd-b130-e2df30b90e73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428804905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2428804905
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2735642928
Short name T540
Test name
Test status
Simulation time 2333911330 ps
CPU time 42.14 seconds
Started Jul 11 06:21:01 PM PDT 24
Finished Jul 11 06:21:47 PM PDT 24
Peak memory 253196 kb
Host smart-26f22a3c-5af4-4551-b55b-e7d3b03d4a36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735642928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2735642928
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.4038042514
Short name T438
Test name
Test status
Simulation time 1337957208 ps
CPU time 16.42 seconds
Started Jul 11 06:21:06 PM PDT 24
Finished Jul 11 06:21:27 PM PDT 24
Peak memory 250588 kb
Host smart-3afeda1b-8add-44de-8f01-84ec713b9c72
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038042514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.4038042514
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.4134333200
Short name T341
Test name
Test status
Simulation time 55909494 ps
CPU time 2.2 seconds
Started Jul 11 06:21:04 PM PDT 24
Finished Jul 11 06:21:11 PM PDT 24
Peak memory 221580 kb
Host smart-c6d46863-ddf4-424e-985b-1b3be5a96ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134333200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.4134333200
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.4197112117
Short name T400
Test name
Test status
Simulation time 239734543 ps
CPU time 12.3 seconds
Started Jul 11 06:21:06 PM PDT 24
Finished Jul 11 06:21:23 PM PDT 24
Peak memory 225740 kb
Host smart-55f28e4b-3b1b-4059-994c-7dcf09b36ba5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197112117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.4197112117
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3354374800
Short name T191
Test name
Test status
Simulation time 1275197873 ps
CPU time 7.77 seconds
Started Jul 11 06:21:03 PM PDT 24
Finished Jul 11 06:21:14 PM PDT 24
Peak memory 224364 kb
Host smart-da5f85a5-f1fd-4588-9d62-623ee0cff678
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354374800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3354374800
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2731748712
Short name T755
Test name
Test status
Simulation time 322296529 ps
CPU time 13.01 seconds
Started Jul 11 06:21:03 PM PDT 24
Finished Jul 11 06:21:21 PM PDT 24
Peak memory 217752 kb
Host smart-ff1e1d62-ee65-4209-95aa-f50fe881eb50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731748712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2731748712
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1882326988
Short name T279
Test name
Test status
Simulation time 845277019 ps
CPU time 15.84 seconds
Started Jul 11 06:21:05 PM PDT 24
Finished Jul 11 06:21:27 PM PDT 24
Peak memory 217668 kb
Host smart-d2fd7d45-a2f1-441a-9759-48b3be1d164b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882326988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1882326988
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1395841422
Short name T60
Test name
Test status
Simulation time 71949230 ps
CPU time 2.27 seconds
Started Jul 11 06:21:02 PM PDT 24
Finished Jul 11 06:21:07 PM PDT 24
Peak memory 217188 kb
Host smart-bd9637c5-f2ef-47af-8e78-e9c86ae961db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395841422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1395841422
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.487323855
Short name T404
Test name
Test status
Simulation time 307016268 ps
CPU time 17.76 seconds
Started Jul 11 06:21:10 PM PDT 24
Finished Jul 11 06:21:33 PM PDT 24
Peak memory 250540 kb
Host smart-be641672-80ed-454a-918e-01d3867b62a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487323855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.487323855
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.134190452
Short name T369
Test name
Test status
Simulation time 8212958229 ps
CPU time 288.93 seconds
Started Jul 11 06:21:03 PM PDT 24
Finished Jul 11 06:25:57 PM PDT 24
Peak memory 250664 kb
Host smart-7081e705-968c-4d7a-843e-696125f8c27a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134190452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.134190452
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2410702266
Short name T650
Test name
Test status
Simulation time 197088931 ps
CPU time 0.78 seconds
Started Jul 11 06:21:04 PM PDT 24
Finished Jul 11 06:21:09 PM PDT 24
Peak memory 208316 kb
Host smart-4579c32d-3827-4c1b-8488-b2dc0a9da663
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410702266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2410702266
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3018061655
Short name T715
Test name
Test status
Simulation time 75802562 ps
CPU time 0.96 seconds
Started Jul 11 06:21:09 PM PDT 24
Finished Jul 11 06:21:16 PM PDT 24
Peak memory 208552 kb
Host smart-002bdb41-116b-43e6-aab1-a9563c8c446d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018061655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3018061655
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2537752300
Short name T704
Test name
Test status
Simulation time 1200503089 ps
CPU time 9.19 seconds
Started Jul 11 06:21:00 PM PDT 24
Finished Jul 11 06:21:13 PM PDT 24
Peak memory 217748 kb
Host smart-15855a36-e556-4eae-99db-497cf878d366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537752300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2537752300
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.748716347
Short name T5
Test name
Test status
Simulation time 359410907 ps
CPU time 4.67 seconds
Started Jul 11 06:21:05 PM PDT 24
Finished Jul 11 06:21:15 PM PDT 24
Peak memory 216672 kb
Host smart-c21ff18f-d3fd-410f-b9a3-89c99fef6f26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748716347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.748716347
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.4001026449
Short name T583
Test name
Test status
Simulation time 3075749828 ps
CPU time 82.08 seconds
Started Jul 11 06:21:05 PM PDT 24
Finished Jul 11 06:22:33 PM PDT 24
Peak memory 218820 kb
Host smart-dd61d246-d823-4634-99fe-62dbc82bbd23
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001026449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.4001026449
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.437200261
Short name T250
Test name
Test status
Simulation time 2404041335 ps
CPU time 5.92 seconds
Started Jul 11 06:21:04 PM PDT 24
Finished Jul 11 06:21:14 PM PDT 24
Peak memory 222612 kb
Host smart-8d484770-1859-4c10-bf80-a1bba828920d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437200261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.437200261
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3937669733
Short name T413
Test name
Test status
Simulation time 127005916 ps
CPU time 4.12 seconds
Started Jul 11 06:21:06 PM PDT 24
Finished Jul 11 06:21:15 PM PDT 24
Peak memory 217116 kb
Host smart-80cd568a-a141-4e18-8ea9-b5f8b11ea690
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937669733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3937669733
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3774577976
Short name T376
Test name
Test status
Simulation time 2874586415 ps
CPU time 58.07 seconds
Started Jul 11 06:21:05 PM PDT 24
Finished Jul 11 06:22:09 PM PDT 24
Peak memory 282620 kb
Host smart-0620084c-6d13-4a96-8b82-18a609ef301f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774577976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3774577976
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3847091876
Short name T757
Test name
Test status
Simulation time 1279077855 ps
CPU time 11.41 seconds
Started Jul 11 06:21:03 PM PDT 24
Finished Jul 11 06:21:19 PM PDT 24
Peak memory 250452 kb
Host smart-8eb8479a-9445-4dcf-a30f-c153421f0055
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847091876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.3847091876
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.3497185356
Short name T420
Test name
Test status
Simulation time 100603158 ps
CPU time 3.18 seconds
Started Jul 11 06:21:02 PM PDT 24
Finished Jul 11 06:21:09 PM PDT 24
Peak memory 217728 kb
Host smart-ac844165-17ee-4c80-b396-4777c629eabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497185356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3497185356
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3338513052
Short name T840
Test name
Test status
Simulation time 344994948 ps
CPU time 8.76 seconds
Started Jul 11 06:21:06 PM PDT 24
Finished Jul 11 06:21:20 PM PDT 24
Peak memory 225668 kb
Host smart-69b30507-5dd6-4e8e-b869-fbf57b04edb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338513052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3338513052
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1223387125
Short name T717
Test name
Test status
Simulation time 309768793 ps
CPU time 8.82 seconds
Started Jul 11 06:21:03 PM PDT 24
Finished Jul 11 06:21:17 PM PDT 24
Peak memory 225528 kb
Host smart-28fc5a3c-c421-4739-9bc6-3bb3233a3922
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223387125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1223387125
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3512867319
Short name T395
Test name
Test status
Simulation time 197096283 ps
CPU time 5.79 seconds
Started Jul 11 06:21:03 PM PDT 24
Finished Jul 11 06:21:13 PM PDT 24
Peak memory 224180 kb
Host smart-5941ba2a-fef5-4c65-b1f9-c47b4ff12c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512867319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3512867319
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1137450339
Short name T265
Test name
Test status
Simulation time 35500061 ps
CPU time 1.34 seconds
Started Jul 11 06:21:05 PM PDT 24
Finished Jul 11 06:21:12 PM PDT 24
Peak memory 217216 kb
Host smart-95f9f636-8b1a-4ae6-8fb5-5aa430eb5a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137450339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1137450339
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2210376344
Short name T714
Test name
Test status
Simulation time 828881299 ps
CPU time 22.15 seconds
Started Jul 11 06:21:03 PM PDT 24
Finished Jul 11 06:21:30 PM PDT 24
Peak memory 246028 kb
Host smart-9df10fb8-f1cb-4692-a0a8-95f383d5056c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210376344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2210376344
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.892924886
Short name T804
Test name
Test status
Simulation time 133203234 ps
CPU time 7.25 seconds
Started Jul 11 06:21:06 PM PDT 24
Finished Jul 11 06:21:18 PM PDT 24
Peak memory 244204 kb
Host smart-b39609e1-20c6-45d5-a5f4-9625e6b2bbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892924886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.892924886
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.610337363
Short name T244
Test name
Test status
Simulation time 18318886772 ps
CPU time 204.86 seconds
Started Jul 11 06:21:05 PM PDT 24
Finished Jul 11 06:24:34 PM PDT 24
Peak memory 283316 kb
Host smart-0882b29d-014e-40d7-8500-d0b821bff556
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610337363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.610337363
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.3728102691
Short name T34
Test name
Test status
Simulation time 175114475876 ps
CPU time 663.66 seconds
Started Jul 11 06:21:02 PM PDT 24
Finished Jul 11 06:32:10 PM PDT 24
Peak memory 529168 kb
Host smart-2447398c-3db5-4801-b139-59d21b4311c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3728102691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.3728102691
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3602749851
Short name T198
Test name
Test status
Simulation time 35532433 ps
CPU time 0.89 seconds
Started Jul 11 06:21:03 PM PDT 24
Finished Jul 11 06:21:09 PM PDT 24
Peak memory 208408 kb
Host smart-b08808a9-5a83-4786-8e41-f16d99035c8a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602749851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3602749851
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2120939826
Short name T662
Test name
Test status
Simulation time 38078918 ps
CPU time 0.98 seconds
Started Jul 11 06:21:09 PM PDT 24
Finished Jul 11 06:21:16 PM PDT 24
Peak memory 208532 kb
Host smart-e002ed55-76e4-4e56-a1c6-d7f7faa000be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120939826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2120939826
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1994365532
Short name T38
Test name
Test status
Simulation time 380184601 ps
CPU time 16.11 seconds
Started Jul 11 06:21:09 PM PDT 24
Finished Jul 11 06:21:31 PM PDT 24
Peak memory 217872 kb
Host smart-4d491991-62ea-4cb3-bb95-9533cc28de87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994365532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1994365532
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3875692927
Short name T19
Test name
Test status
Simulation time 1473342234 ps
CPU time 11 seconds
Started Jul 11 06:21:09 PM PDT 24
Finished Jul 11 06:21:25 PM PDT 24
Peak memory 216748 kb
Host smart-60c4a8b9-0f01-4354-b127-1e75ddd83072
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875692927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3875692927
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.749571776
Short name T703
Test name
Test status
Simulation time 15670089649 ps
CPU time 106.81 seconds
Started Jul 11 06:21:08 PM PDT 24
Finished Jul 11 06:23:00 PM PDT 24
Peak memory 219508 kb
Host smart-3c95791f-ad4b-4ca1-9832-20bdc1c9f8e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749571776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.749571776
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.810644409
Short name T223
Test name
Test status
Simulation time 2249148963 ps
CPU time 14.9 seconds
Started Jul 11 06:21:08 PM PDT 24
Finished Jul 11 06:21:28 PM PDT 24
Peak memory 217888 kb
Host smart-1f8dc8f5-761f-4c57-8526-748a2fe00c3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810644409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag
_prog_failure.810644409
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2395882822
Short name T389
Test name
Test status
Simulation time 327458069 ps
CPU time 6.4 seconds
Started Jul 11 06:21:07 PM PDT 24
Finished Jul 11 06:21:18 PM PDT 24
Peak memory 217188 kb
Host smart-50b45ee5-4ff8-40d5-b9e7-26c045aae03c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395882822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2395882822
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1014851537
Short name T214
Test name
Test status
Simulation time 16733739810 ps
CPU time 71.02 seconds
Started Jul 11 06:21:10 PM PDT 24
Finished Jul 11 06:22:26 PM PDT 24
Peak memory 283208 kb
Host smart-32e52e94-fc7f-43df-87d0-d60ab17fd400
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014851537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1014851537
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.447113821
Short name T472
Test name
Test status
Simulation time 2333361580 ps
CPU time 11.86 seconds
Started Jul 11 06:21:06 PM PDT 24
Finished Jul 11 06:21:23 PM PDT 24
Peak memory 250560 kb
Host smart-a28b5f6e-cd43-4683-8bd2-3f257d7cf3c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447113821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.447113821
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3223419186
Short name T346
Test name
Test status
Simulation time 57737523 ps
CPU time 1.78 seconds
Started Jul 11 06:21:08 PM PDT 24
Finished Jul 11 06:21:14 PM PDT 24
Peak memory 221644 kb
Host smart-d510417b-96d8-49f2-a68e-a9ae9870eca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223419186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3223419186
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.911335215
Short name T293
Test name
Test status
Simulation time 489505686 ps
CPU time 23.25 seconds
Started Jul 11 06:21:09 PM PDT 24
Finished Jul 11 06:21:38 PM PDT 24
Peak memory 218696 kb
Host smart-d56484db-7950-4eb9-81ed-d9ffb5f6e85f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911335215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.911335215
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.477951262
Short name T411
Test name
Test status
Simulation time 2619323485 ps
CPU time 12.9 seconds
Started Jul 11 06:21:08 PM PDT 24
Finished Jul 11 06:21:25 PM PDT 24
Peak memory 225576 kb
Host smart-d8857240-7f6a-4965-86ca-4a16e58f6b7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477951262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.477951262
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.467854453
Short name T299
Test name
Test status
Simulation time 368945707 ps
CPU time 9.99 seconds
Started Jul 11 06:21:09 PM PDT 24
Finished Jul 11 06:21:25 PM PDT 24
Peak memory 217668 kb
Host smart-32deb544-aa00-45f6-83a7-c5510d3984cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467854453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.467854453
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3169014753
Short name T768
Test name
Test status
Simulation time 338599369 ps
CPU time 10.59 seconds
Started Jul 11 06:21:12 PM PDT 24
Finished Jul 11 06:21:27 PM PDT 24
Peak memory 225592 kb
Host smart-153f9d7e-af9e-49ca-9fea-668fb625f2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169014753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3169014753
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.352713069
Short name T554
Test name
Test status
Simulation time 36287883 ps
CPU time 1.14 seconds
Started Jul 11 06:21:12 PM PDT 24
Finished Jul 11 06:21:18 PM PDT 24
Peak memory 211800 kb
Host smart-466e2381-22a3-42f8-b1d5-e9281f7109da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352713069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.352713069
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1325577111
Short name T83
Test name
Test status
Simulation time 388137521 ps
CPU time 37.8 seconds
Started Jul 11 06:21:08 PM PDT 24
Finished Jul 11 06:21:51 PM PDT 24
Peak memory 250544 kb
Host smart-8d82d93b-76c9-43ba-ae58-f35a3d9791c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325577111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1325577111
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.4253643375
Short name T339
Test name
Test status
Simulation time 349361415 ps
CPU time 6.37 seconds
Started Jul 11 06:21:11 PM PDT 24
Finished Jul 11 06:21:22 PM PDT 24
Peak memory 250092 kb
Host smart-c90a86fb-8a93-4669-818d-a96ba533a9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253643375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.4253643375
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2556596116
Short name T660
Test name
Test status
Simulation time 40180479752 ps
CPU time 186.92 seconds
Started Jul 11 06:21:13 PM PDT 24
Finished Jul 11 06:24:24 PM PDT 24
Peak memory 266968 kb
Host smart-5f371735-e00d-4d35-929c-6532d121a27f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556596116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2556596116
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.787166938
Short name T28
Test name
Test status
Simulation time 12514343 ps
CPU time 0.91 seconds
Started Jul 11 06:21:08 PM PDT 24
Finished Jul 11 06:21:13 PM PDT 24
Peak memory 208592 kb
Host smart-9796e1a3-b8aa-42c9-b464-f749f470465e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787166938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.787166938
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2205949874
Short name T610
Test name
Test status
Simulation time 1274185634 ps
CPU time 9.4 seconds
Started Jul 11 06:21:17 PM PDT 24
Finished Jul 11 06:21:29 PM PDT 24
Peak memory 217792 kb
Host smart-61bd1d61-63d7-4928-ad1c-43443ef6cbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205949874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2205949874
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2141646431
Short name T456
Test name
Test status
Simulation time 1306133010 ps
CPU time 9.14 seconds
Started Jul 11 06:21:13 PM PDT 24
Finished Jul 11 06:21:26 PM PDT 24
Peak memory 217208 kb
Host smart-caef9ff8-9850-40b3-9d4f-9e77f9d79462
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141646431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2141646431
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.144465868
Short name T283
Test name
Test status
Simulation time 2287952945 ps
CPU time 37.38 seconds
Started Jul 11 06:21:13 PM PDT 24
Finished Jul 11 06:21:54 PM PDT 24
Peak memory 217884 kb
Host smart-25ed40b7-7e6b-45bf-9e85-5fc0cb0072bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144465868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er
rors.144465868
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3743252124
Short name T312
Test name
Test status
Simulation time 494810201 ps
CPU time 7.03 seconds
Started Jul 11 06:21:12 PM PDT 24
Finished Jul 11 06:21:24 PM PDT 24
Peak memory 217712 kb
Host smart-36c96673-c54b-492b-852a-53c8405890df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743252124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3743252124
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1543842690
Short name T644
Test name
Test status
Simulation time 1417956204 ps
CPU time 3.67 seconds
Started Jul 11 06:21:12 PM PDT 24
Finished Jul 11 06:21:20 PM PDT 24
Peak memory 217140 kb
Host smart-aaabd718-6dd8-43f0-b86a-4b610a9fba15
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543842690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1543842690
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2864674656
Short name T835
Test name
Test status
Simulation time 1257510415 ps
CPU time 57.73 seconds
Started Jul 11 06:21:12 PM PDT 24
Finished Jul 11 06:22:14 PM PDT 24
Peak memory 266892 kb
Host smart-4f82e225-0f90-4357-ae49-d2c4056543b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864674656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2864674656
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2360403817
Short name T248
Test name
Test status
Simulation time 943665689 ps
CPU time 21.54 seconds
Started Jul 11 06:21:16 PM PDT 24
Finished Jul 11 06:21:41 PM PDT 24
Peak memory 250472 kb
Host smart-0efd9d60-a862-468c-910f-15f3c334c286
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360403817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2360403817
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1729663700
Short name T448
Test name
Test status
Simulation time 297074389 ps
CPU time 3.6 seconds
Started Jul 11 06:21:09 PM PDT 24
Finished Jul 11 06:21:18 PM PDT 24
Peak memory 217776 kb
Host smart-d2c65e29-215a-4019-bf77-d323c657c382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729663700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1729663700
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2530504087
Short name T360
Test name
Test status
Simulation time 829673860 ps
CPU time 10.34 seconds
Started Jul 11 06:21:17 PM PDT 24
Finished Jul 11 06:21:31 PM PDT 24
Peak memory 224988 kb
Host smart-7909d316-1d5f-497b-83be-84c16131242a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530504087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2530504087
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.528171345
Short name T563
Test name
Test status
Simulation time 828593153 ps
CPU time 6.55 seconds
Started Jul 11 06:21:16 PM PDT 24
Finished Jul 11 06:21:26 PM PDT 24
Peak memory 217612 kb
Host smart-821e7cf2-c387-48ba-b9de-af9c483ad1b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528171345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.528171345
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.488314829
Short name T518
Test name
Test status
Simulation time 787732022 ps
CPU time 9.05 seconds
Started Jul 11 06:21:13 PM PDT 24
Finished Jul 11 06:21:26 PM PDT 24
Peak memory 225752 kb
Host smart-ccf8452a-594c-4348-ae82-093d64ce0a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488314829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.488314829
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1925094129
Short name T434
Test name
Test status
Simulation time 484208039 ps
CPU time 2.59 seconds
Started Jul 11 06:21:08 PM PDT 24
Finished Jul 11 06:21:15 PM PDT 24
Peak memory 217276 kb
Host smart-1399a2d5-9092-456f-9e23-b113b935693a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925094129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1925094129
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2221105314
Short name T829
Test name
Test status
Simulation time 189496673 ps
CPU time 23.86 seconds
Started Jul 11 06:21:07 PM PDT 24
Finished Jul 11 06:21:36 PM PDT 24
Peak memory 250588 kb
Host smart-f07adf62-021e-4042-9e76-dbfc3d3e6d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221105314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2221105314
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2283825804
Short name T737
Test name
Test status
Simulation time 94741212 ps
CPU time 6.65 seconds
Started Jul 11 06:21:07 PM PDT 24
Finished Jul 11 06:21:19 PM PDT 24
Peak memory 250076 kb
Host smart-a8f85588-8bef-4af1-b6b1-d99c079a5fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283825804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2283825804
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3459332539
Short name T581
Test name
Test status
Simulation time 5124198786 ps
CPU time 151.02 seconds
Started Jul 11 06:21:14 PM PDT 24
Finished Jul 11 06:23:49 PM PDT 24
Peak memory 225732 kb
Host smart-191b13d5-9845-4614-9920-a5b314f4cd7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459332539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3459332539
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.3524172046
Short name T111
Test name
Test status
Simulation time 12248589914 ps
CPU time 357.05 seconds
Started Jul 11 06:21:17 PM PDT 24
Finished Jul 11 06:27:18 PM PDT 24
Peak memory 286300 kb
Host smart-1b6c2298-61e0-4e2a-b62b-ccccdcd852f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3524172046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.3524172046
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3689211622
Short name T356
Test name
Test status
Simulation time 13950654 ps
CPU time 0.97 seconds
Started Jul 11 06:21:09 PM PDT 24
Finished Jul 11 06:21:15 PM PDT 24
Peak memory 208492 kb
Host smart-4828ec44-8eb3-4337-bfda-807993685c3b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689211622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3689211622
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1732616390
Short name T729
Test name
Test status
Simulation time 31291079 ps
CPU time 1.12 seconds
Started Jul 11 06:21:17 PM PDT 24
Finished Jul 11 06:21:22 PM PDT 24
Peak memory 208596 kb
Host smart-ac79738f-8e78-4e29-8c51-d1f52119f8b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732616390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1732616390
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.4029979866
Short name T14
Test name
Test status
Simulation time 3518059120 ps
CPU time 14.77 seconds
Started Jul 11 06:21:14 PM PDT 24
Finished Jul 11 06:21:33 PM PDT 24
Peak memory 225628 kb
Host smart-9acb9d9e-2d5f-461b-8b7a-fd1965d0e596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029979866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.4029979866
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3801186978
Short name T22
Test name
Test status
Simulation time 1433169860 ps
CPU time 17.28 seconds
Started Jul 11 06:21:19 PM PDT 24
Finished Jul 11 06:21:40 PM PDT 24
Peak memory 216928 kb
Host smart-4fef166f-5103-4e97-b9c4-2a01554531b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801186978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3801186978
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1646446100
Short name T505
Test name
Test status
Simulation time 1525119242 ps
CPU time 44.55 seconds
Started Jul 11 06:21:18 PM PDT 24
Finished Jul 11 06:22:06 PM PDT 24
Peak memory 217744 kb
Host smart-1293057c-ef9a-48d1-a556-98ba1aeb4638
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646446100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1646446100
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1520115804
Short name T428
Test name
Test status
Simulation time 201385986 ps
CPU time 6.99 seconds
Started Jul 11 06:21:22 PM PDT 24
Finished Jul 11 06:21:32 PM PDT 24
Peak memory 222008 kb
Host smart-be17f65c-bb74-448f-b7ca-e3a8565cae9d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520115804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.1520115804
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2189086668
Short name T816
Test name
Test status
Simulation time 700578471 ps
CPU time 1.93 seconds
Started Jul 11 06:21:14 PM PDT 24
Finished Jul 11 06:21:19 PM PDT 24
Peak memory 217064 kb
Host smart-ac59d1ef-d9c8-4ca2-b44e-337e9c74c592
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189086668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2189086668
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.749276433
Short name T212
Test name
Test status
Simulation time 2472656131 ps
CPU time 80.04 seconds
Started Jul 11 06:21:14 PM PDT 24
Finished Jul 11 06:22:38 PM PDT 24
Peak memory 277048 kb
Host smart-db05735d-dc98-4b1d-ae49-785369504619
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749276433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.749276433
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.966260279
Short name T514
Test name
Test status
Simulation time 703003883 ps
CPU time 11.72 seconds
Started Jul 11 06:21:18 PM PDT 24
Finished Jul 11 06:21:34 PM PDT 24
Peak memory 223712 kb
Host smart-8c4514ec-3d70-4ea3-83d1-3d46063c1df0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966260279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
jtag_state_post_trans.966260279
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2192921057
Short name T699
Test name
Test status
Simulation time 71463881 ps
CPU time 3.32 seconds
Started Jul 11 06:21:16 PM PDT 24
Finished Jul 11 06:21:22 PM PDT 24
Peak memory 217788 kb
Host smart-38463aaf-6de4-43d2-8ceb-50063861ac2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192921057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2192921057
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2376850137
Short name T355
Test name
Test status
Simulation time 1843603018 ps
CPU time 17.3 seconds
Started Jul 11 06:21:19 PM PDT 24
Finished Jul 11 06:21:40 PM PDT 24
Peak memory 219436 kb
Host smart-44b031dd-2acf-493d-be4b-9e53be9d4552
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376850137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2376850137
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.2249274136
Short name T679
Test name
Test status
Simulation time 1343626297 ps
CPU time 9.62 seconds
Started Jul 11 06:21:22 PM PDT 24
Finished Jul 11 06:21:34 PM PDT 24
Peak memory 224988 kb
Host smart-111ac9e2-9a00-42ab-a9c3-8a26da8d6726
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249274136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.2249274136
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.4224754583
Short name T775
Test name
Test status
Simulation time 2836802132 ps
CPU time 10.3 seconds
Started Jul 11 06:21:19 PM PDT 24
Finished Jul 11 06:21:33 PM PDT 24
Peak memory 225592 kb
Host smart-3a161bd3-ceda-40f7-b46b-133236ec640c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224754583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
4224754583
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1792323311
Short name T245
Test name
Test status
Simulation time 435363478 ps
CPU time 9.72 seconds
Started Jul 11 06:21:15 PM PDT 24
Finished Jul 11 06:21:29 PM PDT 24
Peak memory 218024 kb
Host smart-99bd105c-c340-4ab0-b308-d4582ce46974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792323311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1792323311
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.849214873
Short name T831
Test name
Test status
Simulation time 16879124 ps
CPU time 1.47 seconds
Started Jul 11 06:21:16 PM PDT 24
Finished Jul 11 06:21:21 PM PDT 24
Peak memory 213128 kb
Host smart-74645ec1-0daf-41c8-a0d1-759072ff963f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849214873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.849214873
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1253693832
Short name T340
Test name
Test status
Simulation time 192663669 ps
CPU time 23.17 seconds
Started Jul 11 06:21:11 PM PDT 24
Finished Jul 11 06:21:39 PM PDT 24
Peak memory 250548 kb
Host smart-3e1bcbe5-bfd9-4227-b835-090ae64cb5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253693832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1253693832
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3829989157
Short name T379
Test name
Test status
Simulation time 229513121 ps
CPU time 8.36 seconds
Started Jul 11 06:21:12 PM PDT 24
Finished Jul 11 06:21:25 PM PDT 24
Peak memory 250536 kb
Host smart-ce7968f4-78e4-4cbf-846b-e16126d9d1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829989157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3829989157
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.761915135
Short name T598
Test name
Test status
Simulation time 12408848946 ps
CPU time 158.53 seconds
Started Jul 11 06:21:20 PM PDT 24
Finished Jul 11 06:24:02 PM PDT 24
Peak memory 252812 kb
Host smart-52818936-1156-4e4c-80a4-49b4b15aaaf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761915135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.761915135
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1064300181
Short name T145
Test name
Test status
Simulation time 158032572425 ps
CPU time 1314.44 seconds
Started Jul 11 06:21:21 PM PDT 24
Finished Jul 11 06:43:19 PM PDT 24
Peak memory 414516 kb
Host smart-6740fc68-e4ee-4b57-b3c8-4d9dfbb1ede8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1064300181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.1064300181
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1099922754
Short name T412
Test name
Test status
Simulation time 217838537 ps
CPU time 0.88 seconds
Started Jul 11 06:21:24 PM PDT 24
Finished Jul 11 06:21:27 PM PDT 24
Peak memory 208504 kb
Host smart-2e46ead9-8400-4685-92f6-7ad41af1ff92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099922754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1099922754
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1472894916
Short name T765
Test name
Test status
Simulation time 241152943 ps
CPU time 11.79 seconds
Started Jul 11 06:21:21 PM PDT 24
Finished Jul 11 06:21:35 PM PDT 24
Peak memory 225592 kb
Host smart-0af4ab60-8c4f-4139-9cfd-0d0c2dabab19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472894916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1472894916
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2148900536
Short name T726
Test name
Test status
Simulation time 197390288 ps
CPU time 1.51 seconds
Started Jul 11 06:21:19 PM PDT 24
Finished Jul 11 06:21:24 PM PDT 24
Peak memory 217228 kb
Host smart-964d3c64-e0a9-4ac7-a36f-375cd0d2a892
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148900536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2148900536
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2137384697
Short name T48
Test name
Test status
Simulation time 7937418620 ps
CPU time 117.49 seconds
Started Jul 11 06:21:19 PM PDT 24
Finished Jul 11 06:23:21 PM PDT 24
Peak memory 218524 kb
Host smart-cc31ff42-2481-460e-a74b-3e2202aed2f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137384697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2137384697
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1856168218
Short name T30
Test name
Test status
Simulation time 287093182 ps
CPU time 9.53 seconds
Started Jul 11 06:21:18 PM PDT 24
Finished Jul 11 06:21:31 PM PDT 24
Peak memory 217736 kb
Host smart-0d70ef56-f138-418e-a404-7d27d82e9fb4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856168218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1856168218
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2897753837
Short name T496
Test name
Test status
Simulation time 727562047 ps
CPU time 5.41 seconds
Started Jul 11 06:21:17 PM PDT 24
Finished Jul 11 06:21:25 PM PDT 24
Peak memory 217088 kb
Host smart-47980269-439e-494b-a8a2-be2139ac1cda
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897753837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2897753837
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.279571069
Short name T101
Test name
Test status
Simulation time 12716656633 ps
CPU time 71.34 seconds
Started Jul 11 06:21:19 PM PDT 24
Finished Jul 11 06:22:34 PM PDT 24
Peak memory 275060 kb
Host smart-eb3a6e21-e628-40d1-9633-99b2ea33394c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279571069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.279571069
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.794074548
Short name T264
Test name
Test status
Simulation time 1892941503 ps
CPU time 33.02 seconds
Started Jul 11 06:21:17 PM PDT 24
Finished Jul 11 06:21:54 PM PDT 24
Peak memory 250632 kb
Host smart-23785fd4-67aa-40c7-aa91-dadcebfe3fd0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794074548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.794074548
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1995605794
Short name T235
Test name
Test status
Simulation time 87531887 ps
CPU time 3.56 seconds
Started Jul 11 06:21:22 PM PDT 24
Finished Jul 11 06:21:28 PM PDT 24
Peak memory 222320 kb
Host smart-b8ce926b-fa73-44b0-9ec8-2e369711df05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995605794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1995605794
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1168856582
Short name T740
Test name
Test status
Simulation time 2679167626 ps
CPU time 12.19 seconds
Started Jul 11 06:21:18 PM PDT 24
Finished Jul 11 06:21:34 PM PDT 24
Peak memory 219828 kb
Host smart-de7e3b26-5924-4955-aa1e-eb9987afd49c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168856582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1168856582
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1194912717
Short name T770
Test name
Test status
Simulation time 1013355340 ps
CPU time 7.66 seconds
Started Jul 11 06:21:25 PM PDT 24
Finished Jul 11 06:21:35 PM PDT 24
Peak memory 225432 kb
Host smart-c2c475d8-cc97-45ce-9488-c7a8a41228ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194912717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1194912717
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1483020233
Short name T246
Test name
Test status
Simulation time 422044123 ps
CPU time 11.03 seconds
Started Jul 11 06:21:27 PM PDT 24
Finished Jul 11 06:21:41 PM PDT 24
Peak memory 217744 kb
Host smart-fb707b5b-1993-4e52-b7cc-9475db997500
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483020233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1483020233
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1729961374
Short name T202
Test name
Test status
Simulation time 1508136249 ps
CPU time 10.3 seconds
Started Jul 11 06:21:19 PM PDT 24
Finished Jul 11 06:21:33 PM PDT 24
Peak memory 224512 kb
Host smart-a38c3cec-7b87-4663-b363-90ae5e9340a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729961374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1729961374
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.4142162586
Short name T595
Test name
Test status
Simulation time 36904026 ps
CPU time 1.66 seconds
Started Jul 11 06:21:20 PM PDT 24
Finished Jul 11 06:21:25 PM PDT 24
Peak memory 217144 kb
Host smart-d6ddcd47-2bb9-4e54-ba8b-223c701a4e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142162586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.4142162586
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.696411139
Short name T402
Test name
Test status
Simulation time 506627095 ps
CPU time 26.24 seconds
Started Jul 11 06:21:20 PM PDT 24
Finished Jul 11 06:21:49 PM PDT 24
Peak memory 250544 kb
Host smart-82e825b8-7d75-41c6-9413-7982015b8fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696411139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.696411139
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1699614714
Short name T681
Test name
Test status
Simulation time 45856766 ps
CPU time 2.73 seconds
Started Jul 11 06:21:18 PM PDT 24
Finished Jul 11 06:21:24 PM PDT 24
Peak memory 217816 kb
Host smart-e9029a4d-87e1-446b-b631-79e969144b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699614714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1699614714
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.3718080034
Short name T93
Test name
Test status
Simulation time 2496892802 ps
CPU time 98.37 seconds
Started Jul 11 06:21:27 PM PDT 24
Finished Jul 11 06:23:08 PM PDT 24
Peak memory 274016 kb
Host smart-16f36c9a-a3b1-447b-94b6-9fe9363d22b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718080034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.3718080034
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2987279410
Short name T555
Test name
Test status
Simulation time 46722318 ps
CPU time 0.98 seconds
Started Jul 11 06:21:19 PM PDT 24
Finished Jul 11 06:21:23 PM PDT 24
Peak memory 211372 kb
Host smart-71bfb40e-a6f3-481d-9d39-89bdee023487
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987279410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2987279410
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.4150019178
Short name T273
Test name
Test status
Simulation time 20195574 ps
CPU time 0.85 seconds
Started Jul 11 06:20:08 PM PDT 24
Finished Jul 11 06:20:11 PM PDT 24
Peak memory 208536 kb
Host smart-dcd22853-13fe-4aeb-92e2-4b10409299a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150019178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.4150019178
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1549719085
Short name T307
Test name
Test status
Simulation time 42786858 ps
CPU time 0.76 seconds
Started Jul 11 06:20:10 PM PDT 24
Finished Jul 11 06:20:13 PM PDT 24
Peak memory 208464 kb
Host smart-6aa39159-38f8-4470-ac48-50ee0ea75be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549719085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1549719085
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.344931175
Short name T502
Test name
Test status
Simulation time 1295341970 ps
CPU time 9.42 seconds
Started Jul 11 06:20:19 PM PDT 24
Finished Jul 11 06:20:30 PM PDT 24
Peak memory 217168 kb
Host smart-19bff02c-79c4-4c10-abe7-df5fc525a842
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344931175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.344931175
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2885632717
Short name T638
Test name
Test status
Simulation time 23405708542 ps
CPU time 99.75 seconds
Started Jul 11 06:20:14 PM PDT 24
Finished Jul 11 06:21:55 PM PDT 24
Peak memory 219620 kb
Host smart-f17c7234-e95b-4bb1-95de-7995ca19aaa5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885632717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2885632717
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3608209439
Short name T453
Test name
Test status
Simulation time 1545120400 ps
CPU time 5.07 seconds
Started Jul 11 06:20:09 PM PDT 24
Finished Jul 11 06:20:17 PM PDT 24
Peak memory 221324 kb
Host smart-53766552-a91a-42bc-881f-19c7c9fe1e9d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608209439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3608209439
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2040707122
Short name T854
Test name
Test status
Simulation time 2148484555 ps
CPU time 17.24 seconds
Started Jul 11 06:20:11 PM PDT 24
Finished Jul 11 06:20:30 PM PDT 24
Peak memory 217260 kb
Host smart-2b151393-dec8-49a1-9e00-530ef821c85f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040707122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2040707122
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2941991425
Short name T635
Test name
Test status
Simulation time 861108583 ps
CPU time 4.48 seconds
Started Jul 11 06:20:12 PM PDT 24
Finished Jul 11 06:20:18 PM PDT 24
Peak memory 217100 kb
Host smart-74a3b4bd-1f77-42e2-b04e-56bdbbffba02
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941991425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2941991425
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.4247923287
Short name T736
Test name
Test status
Simulation time 6788972931 ps
CPU time 66.75 seconds
Started Jul 11 06:20:19 PM PDT 24
Finished Jul 11 06:21:27 PM PDT 24
Peak memory 250496 kb
Host smart-d84f96f2-f7a0-4c0c-97ff-0ef1829961f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247923287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.4247923287
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.113503438
Short name T348
Test name
Test status
Simulation time 1360090366 ps
CPU time 7.11 seconds
Started Jul 11 06:20:09 PM PDT 24
Finished Jul 11 06:20:19 PM PDT 24
Peak memory 223556 kb
Host smart-70b7a8a1-e95c-4159-9d18-95c6aa396923
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113503438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.113503438
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.970426279
Short name T347
Test name
Test status
Simulation time 38677357 ps
CPU time 1.82 seconds
Started Jul 11 06:20:05 PM PDT 24
Finished Jul 11 06:20:10 PM PDT 24
Peak memory 221344 kb
Host smart-5f29d3c0-5ff8-4428-b53f-db07ff606173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970426279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.970426279
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.429968370
Short name T56
Test name
Test status
Simulation time 880490957 ps
CPU time 5.23 seconds
Started Jul 11 06:20:08 PM PDT 24
Finished Jul 11 06:20:15 PM PDT 24
Peak memory 217220 kb
Host smart-8b1cbf44-5012-4fe1-8cfd-7b7d5e589317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429968370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.429968370
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3638945684
Short name T94
Test name
Test status
Simulation time 664479510 ps
CPU time 24.9 seconds
Started Jul 11 06:20:30 PM PDT 24
Finished Jul 11 06:20:57 PM PDT 24
Peak memory 269232 kb
Host smart-ff6ce924-8edc-4f15-8d75-e2a14be869b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638945684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3638945684
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1498394830
Short name T560
Test name
Test status
Simulation time 1712135259 ps
CPU time 17.84 seconds
Started Jul 11 06:20:11 PM PDT 24
Finished Jul 11 06:20:31 PM PDT 24
Peak memory 225588 kb
Host smart-f737a2f3-a4c1-4e03-b12e-f531e92107f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498394830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1498394830
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.141503005
Short name T494
Test name
Test status
Simulation time 254109087 ps
CPU time 10.56 seconds
Started Jul 11 06:20:13 PM PDT 24
Finished Jul 11 06:20:26 PM PDT 24
Peak memory 225688 kb
Host smart-f23d1230-eac6-4e18-b291-f1028da368c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141503005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig
est.141503005
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3249018019
Short name T696
Test name
Test status
Simulation time 1532744630 ps
CPU time 13.24 seconds
Started Jul 11 06:20:08 PM PDT 24
Finished Jul 11 06:20:24 PM PDT 24
Peak memory 225524 kb
Host smart-5e92235f-8d63-42e9-b2ca-22d674f8d1b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249018019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
249018019
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1536917950
Short name T852
Test name
Test status
Simulation time 386131732 ps
CPU time 13.84 seconds
Started Jul 11 06:20:12 PM PDT 24
Finished Jul 11 06:20:27 PM PDT 24
Peak memory 224728 kb
Host smart-7fca1ccb-95e0-483a-82f2-ca1162d131c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536917950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1536917950
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1866756755
Short name T79
Test name
Test status
Simulation time 44799205 ps
CPU time 3.33 seconds
Started Jul 11 06:20:09 PM PDT 24
Finished Jul 11 06:20:14 PM PDT 24
Peak memory 214184 kb
Host smart-91e21bbf-b1fc-4031-a5aa-6815f093ff1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866756755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1866756755
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1812080736
Short name T303
Test name
Test status
Simulation time 178785647 ps
CPU time 23.43 seconds
Started Jul 11 06:20:04 PM PDT 24
Finished Jul 11 06:20:30 PM PDT 24
Peak memory 250544 kb
Host smart-6a8b49d6-2fc6-49bb-acae-470e2897cb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812080736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1812080736
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2013990221
Short name T668
Test name
Test status
Simulation time 92941330 ps
CPU time 5.63 seconds
Started Jul 11 06:20:10 PM PDT 24
Finished Jul 11 06:20:18 PM PDT 24
Peak memory 246228 kb
Host smart-bd26a0d2-2ce8-452d-b45e-10d6b9efb2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013990221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2013990221
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2932209972
Short name T774
Test name
Test status
Simulation time 11662349732 ps
CPU time 209.17 seconds
Started Jul 11 06:20:09 PM PDT 24
Finished Jul 11 06:23:41 PM PDT 24
Peak memory 266948 kb
Host smart-6228ccfb-8586-4070-b5ad-57b24907e663
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932209972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2932209972
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1150237952
Short name T508
Test name
Test status
Simulation time 14326946 ps
CPU time 0.85 seconds
Started Jul 11 06:20:15 PM PDT 24
Finished Jul 11 06:20:18 PM PDT 24
Peak memory 208544 kb
Host smart-33c11e47-6294-4860-96ae-f75f0febd84a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150237952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1150237952
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2332779786
Short name T289
Test name
Test status
Simulation time 20116975 ps
CPU time 0.99 seconds
Started Jul 11 06:21:23 PM PDT 24
Finished Jul 11 06:21:27 PM PDT 24
Peak memory 208608 kb
Host smart-05b2a2b8-7bd0-47f5-beab-607d9687a4e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332779786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2332779786
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3131704540
Short name T269
Test name
Test status
Simulation time 368872937 ps
CPU time 8.53 seconds
Started Jul 11 06:21:22 PM PDT 24
Finished Jul 11 06:21:33 PM PDT 24
Peak memory 217788 kb
Host smart-c011c134-3754-460c-8d02-09ff1a1e44a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131704540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3131704540
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2729901718
Short name T820
Test name
Test status
Simulation time 1352428454 ps
CPU time 9.2 seconds
Started Jul 11 06:21:23 PM PDT 24
Finished Jul 11 06:21:35 PM PDT 24
Peak memory 217212 kb
Host smart-259bf844-6c48-4f12-b7e8-73501593a59e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729901718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2729901718
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2976386950
Short name T268
Test name
Test status
Simulation time 591553528 ps
CPU time 4.76 seconds
Started Jul 11 06:21:22 PM PDT 24
Finished Jul 11 06:21:29 PM PDT 24
Peak memory 217792 kb
Host smart-1ea98d8e-3795-451b-a206-ad90ca7edf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976386950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2976386950
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1855652875
Short name T743
Test name
Test status
Simulation time 869557383 ps
CPU time 13.03 seconds
Started Jul 11 06:21:23 PM PDT 24
Finished Jul 11 06:21:38 PM PDT 24
Peak memory 225592 kb
Host smart-8f9a6146-8a8e-419f-be3e-f8399b7b91b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855652875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1855652875
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.586422254
Short name T485
Test name
Test status
Simulation time 808528214 ps
CPU time 19.33 seconds
Started Jul 11 06:21:25 PM PDT 24
Finished Jul 11 06:21:46 PM PDT 24
Peak memory 225480 kb
Host smart-0e95fc66-44a1-4bc5-ac64-b83210a02447
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586422254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.586422254
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.4022860209
Short name T772
Test name
Test status
Simulation time 4725389135 ps
CPU time 10.87 seconds
Started Jul 11 06:21:27 PM PDT 24
Finished Jul 11 06:21:40 PM PDT 24
Peak memory 225592 kb
Host smart-a9444334-99ab-4428-a246-a60e17611f09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022860209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
4022860209
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.4017310323
Short name T861
Test name
Test status
Simulation time 371807919 ps
CPU time 12.76 seconds
Started Jul 11 06:21:22 PM PDT 24
Finished Jul 11 06:21:37 PM PDT 24
Peak memory 217864 kb
Host smart-200c4ee5-5a59-40e0-9fc9-e34c81c996ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017310323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.4017310323
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1773678160
Short name T452
Test name
Test status
Simulation time 177636406 ps
CPU time 1.95 seconds
Started Jul 11 06:21:28 PM PDT 24
Finished Jul 11 06:21:32 PM PDT 24
Peak memory 213484 kb
Host smart-cefcc261-b324-4ba2-a6be-390a3abec33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773678160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1773678160
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.85977640
Short name T531
Test name
Test status
Simulation time 196604529 ps
CPU time 20.62 seconds
Started Jul 11 06:21:22 PM PDT 24
Finished Jul 11 06:21:45 PM PDT 24
Peak memory 250544 kb
Host smart-240561d2-206b-4a23-8848-68f85f55db0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85977640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.85977640
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.3539005915
Short name T763
Test name
Test status
Simulation time 1713305359 ps
CPU time 8.44 seconds
Started Jul 11 06:21:25 PM PDT 24
Finished Jul 11 06:21:35 PM PDT 24
Peak memory 250100 kb
Host smart-b8f7819f-b889-430e-ab42-685b2ad9230d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539005915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3539005915
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1805236553
Short name T91
Test name
Test status
Simulation time 4909412589 ps
CPU time 52.91 seconds
Started Jul 11 06:21:28 PM PDT 24
Finished Jul 11 06:22:23 PM PDT 24
Peak memory 246124 kb
Host smart-34e3e06b-b30c-4440-b3e6-f196bdcb562e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805236553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1805236553
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2887714337
Short name T305
Test name
Test status
Simulation time 13941747 ps
CPU time 0.98 seconds
Started Jul 11 06:21:23 PM PDT 24
Finished Jul 11 06:21:26 PM PDT 24
Peak memory 211512 kb
Host smart-4f61e03a-7ba0-461e-abd7-a1a2f09ba85f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887714337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2887714337
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2662879841
Short name T233
Test name
Test status
Simulation time 28630965 ps
CPU time 1.11 seconds
Started Jul 11 06:21:32 PM PDT 24
Finished Jul 11 06:21:34 PM PDT 24
Peak memory 208508 kb
Host smart-c3cd8d35-f520-4384-8abc-2f7ea6a83589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662879841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2662879841
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.2794840888
Short name T440
Test name
Test status
Simulation time 585363577 ps
CPU time 14.12 seconds
Started Jul 11 06:21:27 PM PDT 24
Finished Jul 11 06:21:44 PM PDT 24
Peak memory 217804 kb
Host smart-1987d80f-cade-43a9-b037-05fff14573a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794840888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2794840888
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.171327642
Short name T471
Test name
Test status
Simulation time 360491016 ps
CPU time 4.88 seconds
Started Jul 11 06:21:28 PM PDT 24
Finished Jul 11 06:21:35 PM PDT 24
Peak memory 216868 kb
Host smart-37ada968-9522-40b9-bfcc-263208131e4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171327642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.171327642
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.743052736
Short name T345
Test name
Test status
Simulation time 54923389 ps
CPU time 1.93 seconds
Started Jul 11 06:21:27 PM PDT 24
Finished Jul 11 06:21:31 PM PDT 24
Peak memory 217708 kb
Host smart-d9b0b830-2972-401c-8c97-bf1ec387f673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743052736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.743052736
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3239309683
Short name T551
Test name
Test status
Simulation time 1550308238 ps
CPU time 18.36 seconds
Started Jul 11 06:21:32 PM PDT 24
Finished Jul 11 06:21:52 PM PDT 24
Peak memory 225532 kb
Host smart-e36adb6c-80d6-40b2-9d4c-21ebfe7834b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239309683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3239309683
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3800712579
Short name T409
Test name
Test status
Simulation time 673793568 ps
CPU time 10.71 seconds
Started Jul 11 06:21:33 PM PDT 24
Finished Jul 11 06:21:46 PM PDT 24
Peak memory 225524 kb
Host smart-50b0411a-b2dd-4f0b-8a0e-5b3bb6a51558
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800712579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3800712579
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3390106130
Short name T701
Test name
Test status
Simulation time 205403726 ps
CPU time 5.74 seconds
Started Jul 11 06:21:31 PM PDT 24
Finished Jul 11 06:21:38 PM PDT 24
Peak memory 217700 kb
Host smart-990ca759-04b6-4b8d-83a8-d95b3de59eaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390106130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3390106130
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1141375985
Short name T435
Test name
Test status
Simulation time 294366895 ps
CPU time 7.88 seconds
Started Jul 11 06:21:28 PM PDT 24
Finished Jul 11 06:21:38 PM PDT 24
Peak memory 224764 kb
Host smart-eadf0fcd-c3db-4861-b0ff-74a4fda8b364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141375985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1141375985
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1333675482
Short name T334
Test name
Test status
Simulation time 34123792 ps
CPU time 1.19 seconds
Started Jul 11 06:21:25 PM PDT 24
Finished Jul 11 06:21:28 PM PDT 24
Peak memory 213132 kb
Host smart-afb8af68-1167-48df-be91-d503badb4e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333675482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1333675482
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3905649202
Short name T645
Test name
Test status
Simulation time 1536028952 ps
CPU time 34.82 seconds
Started Jul 11 06:21:28 PM PDT 24
Finished Jul 11 06:22:05 PM PDT 24
Peak memory 250500 kb
Host smart-8435eb64-24b9-40af-85d4-931c295e4c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905649202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3905649202
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2651968722
Short name T463
Test name
Test status
Simulation time 45294640 ps
CPU time 7.56 seconds
Started Jul 11 06:21:25 PM PDT 24
Finished Jul 11 06:21:35 PM PDT 24
Peak memory 250524 kb
Host smart-1651eed9-b6b9-47dd-a956-69650c6555d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651968722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2651968722
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1656283924
Short name T738
Test name
Test status
Simulation time 28553848472 ps
CPU time 403.56 seconds
Started Jul 11 06:21:26 PM PDT 24
Finished Jul 11 06:28:11 PM PDT 24
Peak memory 272972 kb
Host smart-7b9ce4be-5ac6-49d1-a195-a999c3f7dc25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656283924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1656283924
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3099866796
Short name T842
Test name
Test status
Simulation time 21276758 ps
CPU time 0.95 seconds
Started Jul 11 06:21:23 PM PDT 24
Finished Jul 11 06:21:27 PM PDT 24
Peak memory 208516 kb
Host smart-ed020637-cccb-4254-bfd5-654e609d1f43
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099866796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3099866796
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.702653499
Short name T67
Test name
Test status
Simulation time 53779486 ps
CPU time 0.89 seconds
Started Jul 11 06:21:35 PM PDT 24
Finished Jul 11 06:21:39 PM PDT 24
Peak memory 208512 kb
Host smart-6da3c0d1-ba52-4cd5-97a6-6e48ae704c51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702653499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.702653499
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.791065693
Short name T647
Test name
Test status
Simulation time 778697052 ps
CPU time 12.07 seconds
Started Jul 11 06:21:30 PM PDT 24
Finished Jul 11 06:21:44 PM PDT 24
Peak memory 217796 kb
Host smart-d3a24452-662e-4137-adf2-d7bd9e14196b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791065693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.791065693
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3655793090
Short name T7
Test name
Test status
Simulation time 855530586 ps
CPU time 20.39 seconds
Started Jul 11 06:21:28 PM PDT 24
Finished Jul 11 06:21:51 PM PDT 24
Peak memory 217216 kb
Host smart-eb0f7333-4693-485d-9c54-83adc9d1d454
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655793090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3655793090
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1054608879
Short name T716
Test name
Test status
Simulation time 48781555 ps
CPU time 2.58 seconds
Started Jul 11 06:21:24 PM PDT 24
Finished Jul 11 06:21:29 PM PDT 24
Peak memory 217792 kb
Host smart-3cb6f44f-8918-4840-91b0-831917c418e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054608879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1054608879
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2254297474
Short name T523
Test name
Test status
Simulation time 6103960259 ps
CPU time 16.34 seconds
Started Jul 11 06:21:31 PM PDT 24
Finished Jul 11 06:21:49 PM PDT 24
Peak memory 219192 kb
Host smart-a5811cda-f38d-4776-968c-4edb478f6ae6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254297474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2254297474
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3779416202
Short name T604
Test name
Test status
Simulation time 3274091147 ps
CPU time 11.23 seconds
Started Jul 11 06:21:33 PM PDT 24
Finished Jul 11 06:21:47 PM PDT 24
Peak memory 225584 kb
Host smart-5b024d09-b193-4a73-a175-a487f2a0bac7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779416202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3779416202
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2848920021
Short name T267
Test name
Test status
Simulation time 3345747257 ps
CPU time 7.16 seconds
Started Jul 11 06:21:29 PM PDT 24
Finished Jul 11 06:21:38 PM PDT 24
Peak memory 217744 kb
Host smart-0c3d140a-c446-44d3-b2b5-7bc244fb2f72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848920021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2848920021
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.2015952370
Short name T674
Test name
Test status
Simulation time 1511927031 ps
CPU time 14.98 seconds
Started Jul 11 06:21:29 PM PDT 24
Finished Jul 11 06:21:46 PM PDT 24
Peak memory 217860 kb
Host smart-75e43e5d-6696-41d6-97f2-1802967137fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015952370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2015952370
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3332984817
Short name T791
Test name
Test status
Simulation time 441885863 ps
CPU time 22.07 seconds
Started Jul 11 06:21:30 PM PDT 24
Finished Jul 11 06:21:53 PM PDT 24
Peak memory 250540 kb
Host smart-82b4717b-7a00-4f4f-8076-96a9739424df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332984817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3332984817
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1057348266
Short name T216
Test name
Test status
Simulation time 76920409 ps
CPU time 3.11 seconds
Started Jul 11 06:21:31 PM PDT 24
Finished Jul 11 06:21:35 PM PDT 24
Peak memory 225552 kb
Host smart-9d3a0d96-d078-410f-97a6-9b964e9b1b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057348266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1057348266
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2303553577
Short name T17
Test name
Test status
Simulation time 10555500531 ps
CPU time 213.43 seconds
Started Jul 11 06:21:33 PM PDT 24
Finished Jul 11 06:25:08 PM PDT 24
Peak memory 283096 kb
Host smart-606622c2-4c8f-4d38-9c84-a5143069881e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303553577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2303553577
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.3014673553
Short name T147
Test name
Test status
Simulation time 20929810812 ps
CPU time 197.3 seconds
Started Jul 11 06:21:33 PM PDT 24
Finished Jul 11 06:24:53 PM PDT 24
Peak memory 281956 kb
Host smart-57b216c7-05db-4a4e-9f7a-2d30f46f683e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3014673553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.3014673553
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3876382645
Short name T586
Test name
Test status
Simulation time 74134148 ps
CPU time 1.11 seconds
Started Jul 11 06:21:32 PM PDT 24
Finished Jul 11 06:21:35 PM PDT 24
Peak memory 217212 kb
Host smart-84eee36e-d03a-4f71-be07-0e6f494ac0ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876382645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3876382645
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2913304467
Short name T773
Test name
Test status
Simulation time 22501696 ps
CPU time 1.02 seconds
Started Jul 11 06:21:35 PM PDT 24
Finished Jul 11 06:21:38 PM PDT 24
Peak memory 208544 kb
Host smart-acc2afa0-94c3-4809-873c-db2d6e3892e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913304467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2913304467
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3750780671
Short name T665
Test name
Test status
Simulation time 1666002514 ps
CPU time 14.86 seconds
Started Jul 11 06:21:34 PM PDT 24
Finished Jul 11 06:21:51 PM PDT 24
Peak memory 217728 kb
Host smart-27479fdc-fcc2-4882-b6db-fb38e8cdfd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750780671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3750780671
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1593231630
Short name T730
Test name
Test status
Simulation time 540489686 ps
CPU time 7.86 seconds
Started Jul 11 06:21:33 PM PDT 24
Finished Jul 11 06:21:43 PM PDT 24
Peak memory 216916 kb
Host smart-8d99b1d3-00ad-49d8-9ec5-acbd3c4e9364
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593231630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1593231630
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1747272108
Short name T349
Test name
Test status
Simulation time 139984517 ps
CPU time 2.92 seconds
Started Jul 11 06:21:36 PM PDT 24
Finished Jul 11 06:21:41 PM PDT 24
Peak memory 217864 kb
Host smart-694daba8-f9ad-41d7-8028-9a57e90ea938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747272108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1747272108
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.4049692252
Short name T859
Test name
Test status
Simulation time 364884359 ps
CPU time 14.74 seconds
Started Jul 11 06:21:35 PM PDT 24
Finished Jul 11 06:21:53 PM PDT 24
Peak memory 225588 kb
Host smart-c9ede4ba-47e1-4ed4-ba01-9b1d7211afcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049692252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.4049692252
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.4162224682
Short name T760
Test name
Test status
Simulation time 2759015589 ps
CPU time 12.44 seconds
Started Jul 11 06:21:32 PM PDT 24
Finished Jul 11 06:21:46 PM PDT 24
Peak memory 225592 kb
Host smart-b36b47ad-ba85-4e8b-b1e6-7bef15d966c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162224682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.4162224682
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2771302633
Short name T280
Test name
Test status
Simulation time 10373675715 ps
CPU time 11.02 seconds
Started Jul 11 06:21:33 PM PDT 24
Finished Jul 11 06:21:46 PM PDT 24
Peak memory 217808 kb
Host smart-f64a929a-81b5-4678-b4da-f12e1ce19c5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771302633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2771302633
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3095052582
Short name T408
Test name
Test status
Simulation time 596152774 ps
CPU time 8.22 seconds
Started Jul 11 06:21:35 PM PDT 24
Finished Jul 11 06:21:45 PM PDT 24
Peak memory 225596 kb
Host smart-f52c10c3-acbc-462d-9b76-4d05f1872ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095052582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3095052582
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1602177155
Short name T616
Test name
Test status
Simulation time 49324092 ps
CPU time 1.59 seconds
Started Jul 11 06:21:32 PM PDT 24
Finished Jul 11 06:21:36 PM PDT 24
Peak memory 213292 kb
Host smart-62bd2590-b17b-4d03-a79f-1b3bc7cf94e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602177155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1602177155
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.2457559339
Short name T834
Test name
Test status
Simulation time 1039802819 ps
CPU time 27.44 seconds
Started Jul 11 06:21:36 PM PDT 24
Finished Jul 11 06:22:05 PM PDT 24
Peak memory 250528 kb
Host smart-8ecdb534-919f-45c8-a0d5-0cd505e7480a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457559339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2457559339
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3741444845
Short name T843
Test name
Test status
Simulation time 60646134 ps
CPU time 7.61 seconds
Started Jul 11 06:21:35 PM PDT 24
Finished Jul 11 06:21:45 PM PDT 24
Peak memory 250520 kb
Host smart-0282bfe2-5d73-485e-be12-9ce521e176bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741444845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3741444845
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.976636018
Short name T626
Test name
Test status
Simulation time 15474456007 ps
CPU time 261.37 seconds
Started Jul 11 06:21:36 PM PDT 24
Finished Jul 11 06:25:59 PM PDT 24
Peak memory 283460 kb
Host smart-1761813a-e772-46d7-8ac5-fe5a9373b3dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976636018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.976636018
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3992821702
Short name T290
Test name
Test status
Simulation time 50075884 ps
CPU time 0.88 seconds
Started Jul 11 06:21:34 PM PDT 24
Finished Jul 11 06:21:37 PM PDT 24
Peak memory 208456 kb
Host smart-52185569-c9f3-4295-beca-bb6b8e475920
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992821702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3992821702
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1560673236
Short name T719
Test name
Test status
Simulation time 29183818 ps
CPU time 1.08 seconds
Started Jul 11 06:21:39 PM PDT 24
Finished Jul 11 06:21:43 PM PDT 24
Peak memory 208544 kb
Host smart-edee4eb2-6906-4843-86aa-9cd2d9240eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560673236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1560673236
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.519833777
Short name T546
Test name
Test status
Simulation time 575496984 ps
CPU time 15.81 seconds
Started Jul 11 06:21:33 PM PDT 24
Finished Jul 11 06:21:52 PM PDT 24
Peak memory 225576 kb
Host smart-73241cf8-a730-4b7a-a65b-c9b4b1fc6b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519833777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.519833777
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.760881781
Short name T161
Test name
Test status
Simulation time 3465894188 ps
CPU time 6.05 seconds
Started Jul 11 06:21:34 PM PDT 24
Finished Jul 11 06:21:42 PM PDT 24
Peak memory 217240 kb
Host smart-3e0078f2-5b9b-4801-a3ab-426ead4fef65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760881781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.760881781
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.524312688
Short name T517
Test name
Test status
Simulation time 41453304 ps
CPU time 1.62 seconds
Started Jul 11 06:21:38 PM PDT 24
Finished Jul 11 06:21:43 PM PDT 24
Peak memory 217800 kb
Host smart-a4eef17c-bbc9-4e17-b500-5f5a002bc592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524312688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.524312688
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.3999130380
Short name T387
Test name
Test status
Simulation time 197273449 ps
CPU time 9.62 seconds
Started Jul 11 06:21:35 PM PDT 24
Finished Jul 11 06:21:47 PM PDT 24
Peak memory 225500 kb
Host smart-104dd836-8bbd-4d68-910d-12b1082c6b06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999130380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3999130380
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1960301299
Short name T506
Test name
Test status
Simulation time 1469822248 ps
CPU time 17.03 seconds
Started Jul 11 06:21:38 PM PDT 24
Finished Jul 11 06:21:57 PM PDT 24
Peak memory 225524 kb
Host smart-85ff81f0-fa10-47f4-91a2-45865f0c25a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960301299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1960301299
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2123806309
Short name T863
Test name
Test status
Simulation time 3185876250 ps
CPU time 9.88 seconds
Started Jul 11 06:21:36 PM PDT 24
Finished Jul 11 06:21:48 PM PDT 24
Peak memory 217804 kb
Host smart-9949bca1-0a7c-4060-a8b2-b47c6b68c28c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123806309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2123806309
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.30727752
Short name T367
Test name
Test status
Simulation time 806461852 ps
CPU time 7.06 seconds
Started Jul 11 06:21:34 PM PDT 24
Finished Jul 11 06:21:43 PM PDT 24
Peak memory 223900 kb
Host smart-01255e03-8fd1-4f6d-aa52-999f7bc7b26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30727752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.30727752
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.242707003
Short name T538
Test name
Test status
Simulation time 239567125 ps
CPU time 2.88 seconds
Started Jul 11 06:21:33 PM PDT 24
Finished Jul 11 06:21:39 PM PDT 24
Peak memory 217172 kb
Host smart-aa46db76-8880-4657-9b54-59b9504d827f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242707003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.242707003
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.899760137
Short name T205
Test name
Test status
Simulation time 1021151875 ps
CPU time 27.45 seconds
Started Jul 11 06:21:36 PM PDT 24
Finished Jul 11 06:22:05 PM PDT 24
Peak memory 250540 kb
Host smart-fcfbc6d3-1abf-48df-9219-da4ad23d665c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899760137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.899760137
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.48106248
Short name T396
Test name
Test status
Simulation time 150910535 ps
CPU time 3.39 seconds
Started Jul 11 06:21:36 PM PDT 24
Finished Jul 11 06:21:41 PM PDT 24
Peak memory 222036 kb
Host smart-3b30d86b-e4e5-4439-bc07-57320dc5e269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48106248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.48106248
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3171490392
Short name T372
Test name
Test status
Simulation time 38096671598 ps
CPU time 191.48 seconds
Started Jul 11 06:21:40 PM PDT 24
Finished Jul 11 06:24:54 PM PDT 24
Peak memory 250512 kb
Host smart-c4abc79a-e60d-465d-b98f-c0f15e1f772a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171490392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3171490392
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2786073482
Short name T778
Test name
Test status
Simulation time 41561659 ps
CPU time 1.02 seconds
Started Jul 11 06:21:34 PM PDT 24
Finished Jul 11 06:21:37 PM PDT 24
Peak memory 211412 kb
Host smart-6350ef29-42b3-42aa-8069-3b0f5fc7bd7e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786073482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2786073482
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3890149028
Short name T66
Test name
Test status
Simulation time 18739310 ps
CPU time 1.12 seconds
Started Jul 11 06:21:43 PM PDT 24
Finished Jul 11 06:21:47 PM PDT 24
Peak memory 208376 kb
Host smart-5aad5074-b691-451a-8b42-ba928fe034a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890149028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3890149028
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.4103983882
Short name T462
Test name
Test status
Simulation time 330906764 ps
CPU time 14.89 seconds
Started Jul 11 06:21:39 PM PDT 24
Finished Jul 11 06:21:58 PM PDT 24
Peak memory 217716 kb
Host smart-9e0530c4-1b83-47c0-b2b8-5b9c89465f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103983882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.4103983882
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3860661485
Short name T488
Test name
Test status
Simulation time 5327345706 ps
CPU time 15.57 seconds
Started Jul 11 06:21:37 PM PDT 24
Finished Jul 11 06:21:56 PM PDT 24
Peak memory 217240 kb
Host smart-edc56cac-2492-447a-ad50-ad977cfaf7b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860661485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3860661485
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.586153599
Short name T795
Test name
Test status
Simulation time 79972613 ps
CPU time 2.81 seconds
Started Jul 11 06:21:44 PM PDT 24
Finished Jul 11 06:21:50 PM PDT 24
Peak memory 217736 kb
Host smart-f4ff8c57-129f-418a-b708-a6a70f209b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586153599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.586153599
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1239089901
Short name T353
Test name
Test status
Simulation time 335566148 ps
CPU time 9.69 seconds
Started Jul 11 06:21:39 PM PDT 24
Finished Jul 11 06:21:52 PM PDT 24
Peak memory 225492 kb
Host smart-ad41dcda-7f80-4c3a-8be7-e1e4a5df435b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239089901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1239089901
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3954751090
Short name T222
Test name
Test status
Simulation time 789323656 ps
CPU time 10.53 seconds
Started Jul 11 06:21:40 PM PDT 24
Finished Jul 11 06:21:54 PM PDT 24
Peak memory 225536 kb
Host smart-05966d9b-9e3f-4865-96f6-1406fd03b165
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954751090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3954751090
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.3315070786
Short name T670
Test name
Test status
Simulation time 634079218 ps
CPU time 11.25 seconds
Started Jul 11 06:21:39 PM PDT 24
Finished Jul 11 06:21:53 PM PDT 24
Peak memory 225504 kb
Host smart-d7a59661-5ebf-44be-be9f-4ae4e11fdfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315070786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.3315070786
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3053752331
Short name T652
Test name
Test status
Simulation time 70084789 ps
CPU time 1.81 seconds
Started Jul 11 06:21:38 PM PDT 24
Finished Jul 11 06:21:42 PM PDT 24
Peak memory 213396 kb
Host smart-0d849dee-5820-4f3a-b1f0-0998f91a5515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053752331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3053752331
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2140566621
Short name T270
Test name
Test status
Simulation time 1731184626 ps
CPU time 32.14 seconds
Started Jul 11 06:21:36 PM PDT 24
Finished Jul 11 06:22:11 PM PDT 24
Peak memory 250472 kb
Host smart-fed30cc2-6007-4a00-b4aa-e64a7ec89708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140566621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2140566621
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.2360514737
Short name T342
Test name
Test status
Simulation time 145022835 ps
CPU time 7.42 seconds
Started Jul 11 06:21:36 PM PDT 24
Finished Jul 11 06:21:46 PM PDT 24
Peak memory 250544 kb
Host smart-446fe233-8d7e-4fdb-861e-e58f81a725b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360514737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2360514737
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.4269605635
Short name T330
Test name
Test status
Simulation time 3094002752 ps
CPU time 95.03 seconds
Started Jul 11 06:21:39 PM PDT 24
Finished Jul 11 06:23:18 PM PDT 24
Peak memory 225648 kb
Host smart-17018270-a882-4ffd-a2f4-48bd50bd761f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269605635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.4269605635
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3693461906
Short name T73
Test name
Test status
Simulation time 23650565 ps
CPU time 1.33 seconds
Started Jul 11 06:21:42 PM PDT 24
Finished Jul 11 06:21:47 PM PDT 24
Peak memory 217172 kb
Host smart-2c986dd6-feee-4131-ae41-36c748f20950
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693461906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3693461906
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2538879774
Short name T655
Test name
Test status
Simulation time 32044502 ps
CPU time 0.8 seconds
Started Jul 11 06:21:41 PM PDT 24
Finished Jul 11 06:21:45 PM PDT 24
Peak memory 208608 kb
Host smart-0e82e28d-a77b-4d64-a33b-c82e1715bfd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538879774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2538879774
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.2870275826
Short name T98
Test name
Test status
Simulation time 295581793 ps
CPU time 8.97 seconds
Started Jul 11 06:21:37 PM PDT 24
Finished Jul 11 06:21:49 PM PDT 24
Peak memory 225600 kb
Host smart-ffc7fa32-4e90-4041-b1e9-f0fee0eeda57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870275826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2870275826
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1488112072
Short name T697
Test name
Test status
Simulation time 2663329453 ps
CPU time 12.8 seconds
Started Jul 11 06:21:39 PM PDT 24
Finished Jul 11 06:21:55 PM PDT 24
Peak memory 217280 kb
Host smart-b0b2eb52-dde4-4826-b074-525989011399
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488112072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1488112072
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1531367381
Short name T559
Test name
Test status
Simulation time 59497472 ps
CPU time 2.11 seconds
Started Jul 11 06:21:38 PM PDT 24
Finished Jul 11 06:21:44 PM PDT 24
Peak memory 217792 kb
Host smart-0fc82418-7965-46ce-a1fa-a7cb5c7794be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531367381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1531367381
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1361182348
Short name T707
Test name
Test status
Simulation time 1818025701 ps
CPU time 16.56 seconds
Started Jul 11 06:21:44 PM PDT 24
Finished Jul 11 06:22:04 PM PDT 24
Peak memory 225464 kb
Host smart-6af7ffbe-d82f-43b0-868f-8f741a8f4373
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361182348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1361182348
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2730337225
Short name T576
Test name
Test status
Simulation time 272358698 ps
CPU time 11.72 seconds
Started Jul 11 06:21:36 PM PDT 24
Finished Jul 11 06:21:50 PM PDT 24
Peak memory 225524 kb
Host smart-a556d350-e529-487c-81e8-32d393bc3aa0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730337225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2730337225
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2973105816
Short name T480
Test name
Test status
Simulation time 691717784 ps
CPU time 13.34 seconds
Started Jul 11 06:21:43 PM PDT 24
Finished Jul 11 06:22:00 PM PDT 24
Peak memory 225080 kb
Host smart-e275cf15-2029-4103-98d4-f9c54eb48c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973105816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2973105816
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.130543320
Short name T464
Test name
Test status
Simulation time 39636252 ps
CPU time 2.79 seconds
Started Jul 11 06:21:38 PM PDT 24
Finished Jul 11 06:21:43 PM PDT 24
Peak memory 223740 kb
Host smart-dd78cadc-e731-4375-bfa5-b7a3ff0b193d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130543320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.130543320
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1788022324
Short name T209
Test name
Test status
Simulation time 714060463 ps
CPU time 32.57 seconds
Started Jul 11 06:21:39 PM PDT 24
Finished Jul 11 06:22:14 PM PDT 24
Peak memory 250608 kb
Host smart-6e18f151-7a5e-4f5a-a4fb-2a1b1105a19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788022324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1788022324
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2029560305
Short name T393
Test name
Test status
Simulation time 353459940 ps
CPU time 7.67 seconds
Started Jul 11 06:21:41 PM PDT 24
Finished Jul 11 06:21:52 PM PDT 24
Peak memory 250460 kb
Host smart-600bf60a-228d-41be-93af-5dac90eb62ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029560305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2029560305
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1301708743
Short name T69
Test name
Test status
Simulation time 6987561723 ps
CPU time 144.33 seconds
Started Jul 11 06:21:40 PM PDT 24
Finished Jul 11 06:24:09 PM PDT 24
Peak memory 250572 kb
Host smart-a9a7fe10-965c-438f-bde6-ca581078c775
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301708743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1301708743
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1632232461
Short name T862
Test name
Test status
Simulation time 12883179 ps
CPU time 0.96 seconds
Started Jul 11 06:21:45 PM PDT 24
Finished Jul 11 06:21:49 PM PDT 24
Peak memory 211396 kb
Host smart-fa77d40b-ddaa-42b8-b8fa-c4eb06f57962
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632232461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1632232461
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.1345941383
Short name T232
Test name
Test status
Simulation time 56967658 ps
CPU time 0.93 seconds
Started Jul 11 06:21:42 PM PDT 24
Finished Jul 11 06:21:47 PM PDT 24
Peak memory 208516 kb
Host smart-a7a41234-358b-4c2a-8d82-0a405cbfae04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345941383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1345941383
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2253915811
Short name T228
Test name
Test status
Simulation time 181027728 ps
CPU time 7.15 seconds
Started Jul 11 06:21:40 PM PDT 24
Finished Jul 11 06:21:50 PM PDT 24
Peak memory 225632 kb
Host smart-1d246de8-c92d-4f06-9812-03eac1ff13e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253915811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2253915811
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.4266919234
Short name T487
Test name
Test status
Simulation time 369418315 ps
CPU time 5.61 seconds
Started Jul 11 06:21:39 PM PDT 24
Finished Jul 11 06:21:47 PM PDT 24
Peak memory 216808 kb
Host smart-2cc8066d-4346-4cd4-aaa9-cfdf15c634ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266919234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.4266919234
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1568529620
Short name T782
Test name
Test status
Simulation time 360725018 ps
CPU time 3.15 seconds
Started Jul 11 06:21:39 PM PDT 24
Finished Jul 11 06:21:45 PM PDT 24
Peak memory 217788 kb
Host smart-2453b617-e45a-455d-b086-d335e508bcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568529620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1568529620
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1246310323
Short name T249
Test name
Test status
Simulation time 951229460 ps
CPU time 19.78 seconds
Started Jul 11 06:21:40 PM PDT 24
Finished Jul 11 06:22:04 PM PDT 24
Peak memory 225492 kb
Host smart-3b8e5fcf-24c8-416f-abb4-42244a4930dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246310323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1246310323
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1901871938
Short name T705
Test name
Test status
Simulation time 275735586 ps
CPU time 11.06 seconds
Started Jul 11 06:21:43 PM PDT 24
Finished Jul 11 06:21:57 PM PDT 24
Peak memory 225532 kb
Host smart-f0a074ee-f2d7-4476-8a3c-e70d75ba9ed5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901871938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1901871938
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2383716650
Short name T315
Test name
Test status
Simulation time 957155332 ps
CPU time 8.72 seconds
Started Jul 11 06:21:40 PM PDT 24
Finished Jul 11 06:21:53 PM PDT 24
Peak memory 217780 kb
Host smart-4a1aeb3e-1b9c-4f49-b8c1-f11edbde96e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383716650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2383716650
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3941880917
Short name T300
Test name
Test status
Simulation time 188428854 ps
CPU time 2.07 seconds
Started Jul 11 06:21:41 PM PDT 24
Finished Jul 11 06:21:47 PM PDT 24
Peak memory 213444 kb
Host smart-323a0138-d147-47ff-b240-8fa5647c67e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941880917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3941880917
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2872844289
Short name T545
Test name
Test status
Simulation time 395739386 ps
CPU time 42.11 seconds
Started Jul 11 06:21:44 PM PDT 24
Finished Jul 11 06:22:29 PM PDT 24
Peak memory 250488 kb
Host smart-2c914fe8-7496-4b16-ba76-63235d33b57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872844289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2872844289
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3969132537
Short name T622
Test name
Test status
Simulation time 717123930 ps
CPU time 8.31 seconds
Started Jul 11 06:21:43 PM PDT 24
Finished Jul 11 06:21:55 PM PDT 24
Peak memory 249924 kb
Host smart-b41aadac-0d19-4dea-b218-42d9ea6cd303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969132537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3969132537
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3744215509
Short name T257
Test name
Test status
Simulation time 3915456760 ps
CPU time 153.5 seconds
Started Jul 11 06:21:43 PM PDT 24
Finished Jul 11 06:24:20 PM PDT 24
Peak memory 278024 kb
Host smart-d3acb870-5f66-4d94-8cc9-ec1031e0d99b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744215509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3744215509
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.4202883991
Short name T497
Test name
Test status
Simulation time 285477814989 ps
CPU time 907.19 seconds
Started Jul 11 06:21:41 PM PDT 24
Finished Jul 11 06:36:52 PM PDT 24
Peak memory 480076 kb
Host smart-eb3e394a-6638-4fa3-b9c9-47b66d55681f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4202883991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.4202883991
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1788527982
Short name T374
Test name
Test status
Simulation time 38967387 ps
CPU time 0.88 seconds
Started Jul 11 06:21:40 PM PDT 24
Finished Jul 11 06:21:45 PM PDT 24
Peak memory 211344 kb
Host smart-23039573-8d85-4ce8-8e16-ca570037a452
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788527982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1788527982
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.502786291
Short name T596
Test name
Test status
Simulation time 23835034 ps
CPU time 0.99 seconds
Started Jul 11 06:21:44 PM PDT 24
Finished Jul 11 06:21:49 PM PDT 24
Peak memory 208608 kb
Host smart-a122d605-7c1e-4604-a596-757b46b23e67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502786291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.502786291
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.1984655937
Short name T686
Test name
Test status
Simulation time 457495736 ps
CPU time 11.37 seconds
Started Jul 11 06:21:40 PM PDT 24
Finished Jul 11 06:21:55 PM PDT 24
Peak memory 217764 kb
Host smart-51cffd04-a751-4b9c-975b-c6611014016f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984655937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.1984655937
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3907529788
Short name T24
Test name
Test status
Simulation time 432208349 ps
CPU time 4.42 seconds
Started Jul 11 06:21:42 PM PDT 24
Finished Jul 11 06:21:50 PM PDT 24
Peak memory 217304 kb
Host smart-a92c3a70-207d-4420-9041-2d5a921a54fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907529788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3907529788
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.1369396980
Short name T319
Test name
Test status
Simulation time 391157444 ps
CPU time 3.31 seconds
Started Jul 11 06:21:40 PM PDT 24
Finished Jul 11 06:21:47 PM PDT 24
Peak memory 217856 kb
Host smart-3da5a53c-09b7-47a4-a2f8-73fb662f58c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369396980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1369396980
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1795699147
Short name T587
Test name
Test status
Simulation time 2091847499 ps
CPU time 12.48 seconds
Started Jul 11 06:21:43 PM PDT 24
Finished Jul 11 06:21:59 PM PDT 24
Peak memory 225508 kb
Host smart-5161f85f-abf6-4ff6-add1-1ceabb449800
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795699147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1795699147
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2580960318
Short name T692
Test name
Test status
Simulation time 283980929 ps
CPU time 10.32 seconds
Started Jul 11 06:21:43 PM PDT 24
Finished Jul 11 06:21:57 PM PDT 24
Peak memory 225512 kb
Host smart-c693db5f-9c13-4395-ae17-86ac9add495e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580960318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
2580960318
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3373744701
Short name T450
Test name
Test status
Simulation time 1021358971 ps
CPU time 9.44 seconds
Started Jul 11 06:21:42 PM PDT 24
Finished Jul 11 06:21:55 PM PDT 24
Peak memory 224660 kb
Host smart-2f764142-692c-43c4-baab-9d687f72e2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373744701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3373744701
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2719115462
Short name T815
Test name
Test status
Simulation time 73159843 ps
CPU time 4.12 seconds
Started Jul 11 06:21:40 PM PDT 24
Finished Jul 11 06:21:48 PM PDT 24
Peak memory 217180 kb
Host smart-14011e27-66ae-48e8-9d54-fe6321522b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719115462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2719115462
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2593708718
Short name T553
Test name
Test status
Simulation time 2919610949 ps
CPU time 35.86 seconds
Started Jul 11 06:21:42 PM PDT 24
Finished Jul 11 06:22:22 PM PDT 24
Peak memory 250572 kb
Host smart-84abd7f6-1bde-419e-9c9d-1a0dfe8839f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593708718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2593708718
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3486531905
Short name T195
Test name
Test status
Simulation time 747694779 ps
CPU time 7.39 seconds
Started Jul 11 06:21:41 PM PDT 24
Finished Jul 11 06:21:52 PM PDT 24
Peak memory 249944 kb
Host smart-d9fd9688-28cc-4fef-946f-11bdc019680b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486531905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3486531905
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2604997106
Short name T519
Test name
Test status
Simulation time 10840075524 ps
CPU time 84.11 seconds
Started Jul 11 06:21:50 PM PDT 24
Finished Jul 11 06:23:16 PM PDT 24
Peak memory 250600 kb
Host smart-56f35adb-7906-4097-9fb3-a13a945e7167
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604997106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2604997106
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1225450677
Short name T808
Test name
Test status
Simulation time 12019180 ps
CPU time 1.05 seconds
Started Jul 11 06:21:43 PM PDT 24
Finished Jul 11 06:21:48 PM PDT 24
Peak memory 211384 kb
Host smart-9385332f-ec15-439b-a737-0a9d310b5338
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225450677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1225450677
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.45355237
Short name T486
Test name
Test status
Simulation time 84666477 ps
CPU time 0.92 seconds
Started Jul 11 06:21:50 PM PDT 24
Finished Jul 11 06:21:54 PM PDT 24
Peak memory 208524 kb
Host smart-64805990-9085-4574-ac88-5ee019db262a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45355237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.45355237
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1345819783
Short name T849
Test name
Test status
Simulation time 461430737 ps
CPU time 10.58 seconds
Started Jul 11 06:21:45 PM PDT 24
Finished Jul 11 06:21:59 PM PDT 24
Peak memory 217804 kb
Host smart-70ce8373-7b77-4021-ac1b-231be222b17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345819783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1345819783
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.4283400083
Short name T549
Test name
Test status
Simulation time 158060330 ps
CPU time 4.83 seconds
Started Jul 11 06:21:47 PM PDT 24
Finished Jul 11 06:21:55 PM PDT 24
Peak memory 217136 kb
Host smart-cc33be12-b33b-4642-bb71-fc725946b777
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283400083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.4283400083
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1152947309
Short name T803
Test name
Test status
Simulation time 131561507 ps
CPU time 2.87 seconds
Started Jul 11 06:22:00 PM PDT 24
Finished Jul 11 06:22:07 PM PDT 24
Peak memory 217736 kb
Host smart-ad686b47-e88f-41ea-a00a-1bdcc29183de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152947309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1152947309
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1283405406
Short name T425
Test name
Test status
Simulation time 395071973 ps
CPU time 16.71 seconds
Started Jul 11 06:21:53 PM PDT 24
Finished Jul 11 06:22:14 PM PDT 24
Peak memory 225500 kb
Host smart-a1bbc3af-94e0-4621-b28e-9cea5c9d72c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283405406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1283405406
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2037555917
Short name T102
Test name
Test status
Simulation time 2294342261 ps
CPU time 13.37 seconds
Started Jul 11 06:21:51 PM PDT 24
Finished Jul 11 06:22:08 PM PDT 24
Peak memory 225580 kb
Host smart-ab86607f-547d-44ba-8908-ada588e6751e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037555917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2037555917
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1551140994
Short name T401
Test name
Test status
Simulation time 1217431037 ps
CPU time 11.25 seconds
Started Jul 11 06:21:47 PM PDT 24
Finished Jul 11 06:22:01 PM PDT 24
Peak memory 217744 kb
Host smart-2add17ff-3f44-47b2-8246-e536b5ffc57e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551140994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1551140994
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2218948831
Short name T739
Test name
Test status
Simulation time 1500069849 ps
CPU time 13.87 seconds
Started Jul 11 06:21:46 PM PDT 24
Finished Jul 11 06:22:03 PM PDT 24
Peak memory 225568 kb
Host smart-03dbbe1b-48b2-4b01-9e61-13d0ac41f3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218948831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2218948831
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1677250730
Short name T526
Test name
Test status
Simulation time 31072072 ps
CPU time 1.12 seconds
Started Jul 11 06:21:46 PM PDT 24
Finished Jul 11 06:21:50 PM PDT 24
Peak memory 217188 kb
Host smart-ce52fa3d-03f0-4810-b08a-09f65b4454e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677250730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1677250730
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.949835372
Short name T718
Test name
Test status
Simulation time 476382207 ps
CPU time 22.01 seconds
Started Jul 11 06:21:44 PM PDT 24
Finished Jul 11 06:22:09 PM PDT 24
Peak memory 250772 kb
Host smart-f0bd8214-5ba4-489d-bccf-8e6ad190596a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949835372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.949835372
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2679452725
Short name T828
Test name
Test status
Simulation time 66059682 ps
CPU time 7.3 seconds
Started Jul 11 06:21:50 PM PDT 24
Finished Jul 11 06:21:59 PM PDT 24
Peak memory 250496 kb
Host smart-4e8b26a1-90e9-455a-a85f-8bce9125d4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679452725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2679452725
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.287630054
Short name T593
Test name
Test status
Simulation time 11563959539 ps
CPU time 67.69 seconds
Started Jul 11 06:21:45 PM PDT 24
Finished Jul 11 06:22:56 PM PDT 24
Peak memory 250196 kb
Host smart-0ff28206-11a7-41cf-9806-23fb2fb27c22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287630054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.287630054
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.2740049046
Short name T144
Test name
Test status
Simulation time 60589718637 ps
CPU time 840.13 seconds
Started Jul 11 06:21:49 PM PDT 24
Finished Jul 11 06:35:51 PM PDT 24
Peak memory 643968 kb
Host smart-a4a2fd01-daba-4c60-bfa5-26bcf9d7238e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2740049046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.2740049046
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.4243175865
Short name T272
Test name
Test status
Simulation time 48352234 ps
CPU time 0.97 seconds
Started Jul 11 06:22:00 PM PDT 24
Finished Jul 11 06:22:05 PM PDT 24
Peak memory 217148 kb
Host smart-ce74f8b9-5c0a-4cb5-bdb8-6d3c3e7ff620
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243175865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.4243175865
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2464330714
Short name T332
Test name
Test status
Simulation time 37662054 ps
CPU time 0.91 seconds
Started Jul 11 06:20:19 PM PDT 24
Finished Jul 11 06:20:22 PM PDT 24
Peak memory 208612 kb
Host smart-547e7865-dac3-4f3a-b74f-3df88fc4f1bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464330714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2464330714
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.526294317
Short name T484
Test name
Test status
Simulation time 323311064 ps
CPU time 9.79 seconds
Started Jul 11 06:20:13 PM PDT 24
Finished Jul 11 06:20:25 PM PDT 24
Peak memory 217960 kb
Host smart-b172b3f1-6e3a-47ad-b142-8f5ac5c53e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526294317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.526294317
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3848975415
Short name T525
Test name
Test status
Simulation time 282167596 ps
CPU time 2.74 seconds
Started Jul 11 06:20:15 PM PDT 24
Finished Jul 11 06:20:19 PM PDT 24
Peak memory 217152 kb
Host smart-e537e3b2-7918-46ca-b26f-399dad12f497
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848975415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3848975415
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2178548282
Short name T636
Test name
Test status
Simulation time 1342361542 ps
CPU time 22.55 seconds
Started Jul 11 06:20:16 PM PDT 24
Finished Jul 11 06:20:41 PM PDT 24
Peak memory 217808 kb
Host smart-342d8cba-a764-495f-b891-334ca0eadf06
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178548282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2178548282
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.719963093
Short name T259
Test name
Test status
Simulation time 444791859 ps
CPU time 7.81 seconds
Started Jul 11 06:20:17 PM PDT 24
Finished Jul 11 06:20:26 PM PDT 24
Peak memory 217280 kb
Host smart-0b7f80e1-626f-40a2-806f-d27ed9a29490
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719963093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.719963093
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1097231730
Short name T282
Test name
Test status
Simulation time 247999562 ps
CPU time 1.92 seconds
Started Jul 11 06:20:17 PM PDT 24
Finished Jul 11 06:20:21 PM PDT 24
Peak memory 221048 kb
Host smart-2044b660-53e7-49dd-b0b8-11574379e71d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097231730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1097231730
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2517124350
Short name T640
Test name
Test status
Simulation time 7168993649 ps
CPU time 31.22 seconds
Started Jul 11 06:20:15 PM PDT 24
Finished Jul 11 06:20:48 PM PDT 24
Peak memory 217196 kb
Host smart-753553f6-b596-487e-a3ed-9fbfac728b81
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517124350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2517124350
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2430186538
Short name T634
Test name
Test status
Simulation time 832906693 ps
CPU time 5.71 seconds
Started Jul 11 06:20:18 PM PDT 24
Finished Jul 11 06:20:26 PM PDT 24
Peak memory 217072 kb
Host smart-80ccd04e-32c2-431a-b761-daa25e70c190
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430186538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2430186538
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3693068076
Short name T601
Test name
Test status
Simulation time 5989044073 ps
CPU time 42.44 seconds
Started Jul 11 06:20:16 PM PDT 24
Finished Jul 11 06:21:00 PM PDT 24
Peak memory 275352 kb
Host smart-01751562-1ba6-4b8d-b972-8a88247b49b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693068076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3693068076
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3630807903
Short name T321
Test name
Test status
Simulation time 1773337568 ps
CPU time 15.78 seconds
Started Jul 11 06:20:14 PM PDT 24
Finished Jul 11 06:20:32 PM PDT 24
Peak memory 250436 kb
Host smart-a3faddfa-90d3-4319-ae02-e6ec2c92cac5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630807903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3630807903
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.4170558088
Short name T673
Test name
Test status
Simulation time 272238419 ps
CPU time 3.37 seconds
Started Jul 11 06:20:14 PM PDT 24
Finished Jul 11 06:20:19 PM PDT 24
Peak memory 217700 kb
Host smart-67b7557c-56ab-4eab-9e2a-e9cf46a389fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170558088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.4170558088
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3713306180
Short name T76
Test name
Test status
Simulation time 405006342 ps
CPU time 9.55 seconds
Started Jul 11 06:20:17 PM PDT 24
Finished Jul 11 06:20:29 PM PDT 24
Peak memory 217196 kb
Host smart-5ac5a4f7-eeb6-4913-9bb2-cec17b1bc289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713306180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3713306180
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1735878460
Short name T47
Test name
Test status
Simulation time 262683216 ps
CPU time 24.74 seconds
Started Jul 11 06:20:15 PM PDT 24
Finished Jul 11 06:20:42 PM PDT 24
Peak memory 282488 kb
Host smart-09e3097f-38ea-4b58-ba35-794825aabd09
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735878460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1735878460
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1959366713
Short name T256
Test name
Test status
Simulation time 984336893 ps
CPU time 11.63 seconds
Started Jul 11 06:20:16 PM PDT 24
Finished Jul 11 06:20:30 PM PDT 24
Peak memory 217860 kb
Host smart-c5c8be66-eb52-4bff-942e-2ee4e98fad33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959366713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1959366713
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2879458437
Short name T564
Test name
Test status
Simulation time 301181951 ps
CPU time 12.63 seconds
Started Jul 11 06:20:16 PM PDT 24
Finished Jul 11 06:20:31 PM PDT 24
Peak memory 225584 kb
Host smart-7d0a0c6d-b4b6-45a4-8243-14a64717e099
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879458437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2879458437
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2178683477
Short name T237
Test name
Test status
Simulation time 714057358 ps
CPU time 6.44 seconds
Started Jul 11 06:20:14 PM PDT 24
Finished Jul 11 06:20:22 PM PDT 24
Peak memory 217684 kb
Host smart-ff24e09d-161c-474c-b5e0-a3e189f58560
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178683477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
178683477
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.8179714
Short name T507
Test name
Test status
Simulation time 1958458638 ps
CPU time 9.63 seconds
Started Jul 11 06:20:12 PM PDT 24
Finished Jul 11 06:20:23 PM PDT 24
Peak memory 224604 kb
Host smart-d58aece4-f22e-40aa-a464-56f9c0404965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8179714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.8179714
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.4282473799
Short name T690
Test name
Test status
Simulation time 23469143 ps
CPU time 1.12 seconds
Started Jul 11 06:20:09 PM PDT 24
Finished Jul 11 06:20:13 PM PDT 24
Peak memory 213240 kb
Host smart-50eeebbe-39a2-4044-b592-58392cc00279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282473799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.4282473799
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.404254989
Short name T654
Test name
Test status
Simulation time 1161383958 ps
CPU time 22.71 seconds
Started Jul 11 06:20:13 PM PDT 24
Finished Jul 11 06:20:37 PM PDT 24
Peak memory 250508 kb
Host smart-677e4ea1-b5c7-4e6d-be31-d663a11278e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404254989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.404254989
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3767015522
Short name T304
Test name
Test status
Simulation time 303805892 ps
CPU time 5.86 seconds
Started Jul 11 06:20:13 PM PDT 24
Finished Jul 11 06:20:21 PM PDT 24
Peak memory 246576 kb
Host smart-5e47eb55-f55b-47e5-b6da-3adfdd19822b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767015522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3767015522
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.734511480
Short name T722
Test name
Test status
Simulation time 2150033964 ps
CPU time 64.24 seconds
Started Jul 11 06:20:15 PM PDT 24
Finished Jul 11 06:21:21 PM PDT 24
Peak memory 246972 kb
Host smart-fedaf812-8938-4544-ad76-5cd74f43d086
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734511480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.734511480
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3934076261
Short name T138
Test name
Test status
Simulation time 28940255634 ps
CPU time 354.73 seconds
Started Jul 11 06:20:16 PM PDT 24
Finished Jul 11 06:26:12 PM PDT 24
Peak memory 356200 kb
Host smart-11706e69-b1b5-4a4e-a7ef-53074430108a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3934076261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.3934076261
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3394047539
Short name T371
Test name
Test status
Simulation time 59717947 ps
CPU time 1.22 seconds
Started Jul 11 06:20:09 PM PDT 24
Finished Jul 11 06:20:12 PM PDT 24
Peak memory 217200 kb
Host smart-589c2742-7fb3-46be-ad97-27dd6ed45c63
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394047539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.3394047539
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.685837408
Short name T539
Test name
Test status
Simulation time 26552642 ps
CPU time 0.92 seconds
Started Jul 11 06:21:51 PM PDT 24
Finished Jul 11 06:21:54 PM PDT 24
Peak memory 208536 kb
Host smart-f80bb1d6-9373-4ee5-8547-b457b697a6bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685837408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.685837408
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2457878708
Short name T631
Test name
Test status
Simulation time 732688027 ps
CPU time 8.28 seconds
Started Jul 11 06:21:56 PM PDT 24
Finished Jul 11 06:22:08 PM PDT 24
Peak memory 225576 kb
Host smart-84d28b8d-ad1d-4a49-bb3a-851148b0d495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457878708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2457878708
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.357264727
Short name T533
Test name
Test status
Simulation time 796462859 ps
CPU time 18.16 seconds
Started Jul 11 06:21:48 PM PDT 24
Finished Jul 11 06:22:08 PM PDT 24
Peak memory 217192 kb
Host smart-24f934d2-4636-40de-b9b1-03a1931e54b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357264727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.357264727
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.498075848
Short name T747
Test name
Test status
Simulation time 84941326 ps
CPU time 2.65 seconds
Started Jul 11 06:21:50 PM PDT 24
Finished Jul 11 06:21:55 PM PDT 24
Peak memory 217700 kb
Host smart-ccd4f2a9-ffe2-4bd8-a388-0ff9b9006fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498075848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.498075848
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.2594032766
Short name T605
Test name
Test status
Simulation time 597049215 ps
CPU time 13.23 seconds
Started Jul 11 06:21:47 PM PDT 24
Finished Jul 11 06:22:03 PM PDT 24
Peak memory 218448 kb
Host smart-fe39d53f-e4d2-4cbe-bf78-9234f1b8e4a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594032766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.2594032766
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2514969099
Short name T769
Test name
Test status
Simulation time 345870637 ps
CPU time 9.75 seconds
Started Jul 11 06:21:47 PM PDT 24
Finished Jul 11 06:21:59 PM PDT 24
Peak memory 225380 kb
Host smart-e1c30d05-52ef-4aaa-a0da-8fccf845663d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514969099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2514969099
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2783959043
Short name T762
Test name
Test status
Simulation time 389377662 ps
CPU time 9.24 seconds
Started Jul 11 06:21:49 PM PDT 24
Finished Jul 11 06:22:00 PM PDT 24
Peak memory 217672 kb
Host smart-2a269cb7-8f59-411c-8413-73da7715f205
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783959043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2783959043
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3873882295
Short name T454
Test name
Test status
Simulation time 283221487 ps
CPU time 8.91 seconds
Started Jul 11 06:21:57 PM PDT 24
Finished Jul 11 06:22:10 PM PDT 24
Peak memory 225536 kb
Host smart-9aae476f-dc02-4cfd-b7c1-a92c43da8629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873882295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3873882295
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3467531118
Short name T78
Test name
Test status
Simulation time 213393000 ps
CPU time 2.51 seconds
Started Jul 11 06:21:57 PM PDT 24
Finished Jul 11 06:22:04 PM PDT 24
Peak memory 217020 kb
Host smart-6018361f-05b3-4e51-b3b2-d5802d068e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467531118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3467531118
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.2999941282
Short name T422
Test name
Test status
Simulation time 641880639 ps
CPU time 21.35 seconds
Started Jul 11 06:21:57 PM PDT 24
Finished Jul 11 06:22:22 PM PDT 24
Peak memory 250520 kb
Host smart-16e8a773-e5f5-4705-8426-90d4720eab95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999941282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2999941282
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1566555859
Short name T511
Test name
Test status
Simulation time 90504872 ps
CPU time 7.42 seconds
Started Jul 11 06:21:57 PM PDT 24
Finished Jul 11 06:22:09 PM PDT 24
Peak memory 242020 kb
Host smart-e8d13ba6-20e6-4466-a921-27522768d3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566555859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1566555859
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3591256652
Short name T547
Test name
Test status
Simulation time 13238984774 ps
CPU time 244.18 seconds
Started Jul 11 06:21:51 PM PDT 24
Finished Jul 11 06:25:58 PM PDT 24
Peak memory 228076 kb
Host smart-7bd789a0-2c7d-4e2f-bc1e-8c68058d5c0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591256652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3591256652
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3692701577
Short name T532
Test name
Test status
Simulation time 14546312 ps
CPU time 0.83 seconds
Started Jul 11 06:21:51 PM PDT 24
Finished Jul 11 06:21:55 PM PDT 24
Peak memory 208516 kb
Host smart-68ea86c1-f868-4398-afc4-6818a4656089
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692701577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3692701577
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1892969407
Short name T557
Test name
Test status
Simulation time 25955918 ps
CPU time 0.94 seconds
Started Jul 11 06:21:53 PM PDT 24
Finished Jul 11 06:21:58 PM PDT 24
Peak memory 208724 kb
Host smart-f872321e-9993-4304-8a93-a1e049396c4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892969407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1892969407
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.578735890
Short name T35
Test name
Test status
Simulation time 448697720 ps
CPU time 12.59 seconds
Started Jul 11 06:21:53 PM PDT 24
Finished Jul 11 06:22:10 PM PDT 24
Peak memory 217732 kb
Host smart-a091d524-10a8-4f56-a695-7ae0724c1513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578735890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.578735890
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1403728234
Short name T742
Test name
Test status
Simulation time 1034880656 ps
CPU time 3.71 seconds
Started Jul 11 06:21:50 PM PDT 24
Finished Jul 11 06:21:57 PM PDT 24
Peak memory 216748 kb
Host smart-88daee14-c282-468f-99bf-9b993b3c5790
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403728234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1403728234
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.35275689
Short name T753
Test name
Test status
Simulation time 95590030 ps
CPU time 4.14 seconds
Started Jul 11 06:21:52 PM PDT 24
Finished Jul 11 06:22:00 PM PDT 24
Peak memory 221908 kb
Host smart-751497a8-691f-4325-8bd4-4def5987cb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35275689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.35275689
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.1834284155
Short name T475
Test name
Test status
Simulation time 502341987 ps
CPU time 13.9 seconds
Started Jul 11 06:21:55 PM PDT 24
Finished Jul 11 06:22:13 PM PDT 24
Peak memory 225592 kb
Host smart-94716eb2-4751-46c0-9cf6-e7df52986abc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834284155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1834284155
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2055733141
Short name T567
Test name
Test status
Simulation time 543112886 ps
CPU time 9.03 seconds
Started Jul 11 06:21:49 PM PDT 24
Finished Jul 11 06:22:00 PM PDT 24
Peak memory 225516 kb
Host smart-090a6fd7-ffb7-4427-8a17-3438afbd5ac4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055733141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2055733141
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3529215290
Short name T53
Test name
Test status
Simulation time 1217880633 ps
CPU time 11.78 seconds
Started Jul 11 06:21:52 PM PDT 24
Finished Jul 11 06:22:07 PM PDT 24
Peak memory 225464 kb
Host smart-e22cf8e2-6cae-4869-a664-ab28f3612ed0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529215290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3529215290
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3158195212
Short name T761
Test name
Test status
Simulation time 157995025 ps
CPU time 2.36 seconds
Started Jul 11 06:21:51 PM PDT 24
Finished Jul 11 06:21:56 PM PDT 24
Peak memory 214148 kb
Host smart-b9703d43-1b9d-456a-9c42-574d99bd77fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158195212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3158195212
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.483937451
Short name T585
Test name
Test status
Simulation time 3069057562 ps
CPU time 19.68 seconds
Started Jul 11 06:21:55 PM PDT 24
Finished Jul 11 06:22:18 PM PDT 24
Peak memory 246356 kb
Host smart-6063906a-44ff-4d0a-841c-40028ee21078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483937451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.483937451
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.892893261
Short name T709
Test name
Test status
Simulation time 54765589 ps
CPU time 3.71 seconds
Started Jul 11 06:21:52 PM PDT 24
Finished Jul 11 06:21:59 PM PDT 24
Peak memory 224116 kb
Host smart-e4aaf103-2513-4103-ab1f-7928b0ed9608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892893261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.892893261
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3482142840
Short name T691
Test name
Test status
Simulation time 4912186672 ps
CPU time 157.73 seconds
Started Jul 11 06:21:51 PM PDT 24
Finished Jul 11 06:24:31 PM PDT 24
Peak memory 250604 kb
Host smart-7abe1087-5f73-4006-9318-64b297047f22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482142840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3482142840
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3821623129
Short name T846
Test name
Test status
Simulation time 12604893 ps
CPU time 0.84 seconds
Started Jul 11 06:21:53 PM PDT 24
Finished Jul 11 06:21:57 PM PDT 24
Peak memory 208344 kb
Host smart-99deb8e5-7eef-44c6-b734-ec4c96930a9c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821623129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3821623129
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3883411189
Short name T702
Test name
Test status
Simulation time 93898089 ps
CPU time 1.05 seconds
Started Jul 11 06:22:00 PM PDT 24
Finished Jul 11 06:22:05 PM PDT 24
Peak memory 208560 kb
Host smart-90e6e98d-e387-4667-bfa9-06faba3ac715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883411189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3883411189
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3796394522
Short name T338
Test name
Test status
Simulation time 528822600 ps
CPU time 11.63 seconds
Started Jul 11 06:21:51 PM PDT 24
Finished Jul 11 06:22:05 PM PDT 24
Peak memory 217716 kb
Host smart-a3bbca7a-cdce-45b0-8f27-6b4882cdd922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796394522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3796394522
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.712024879
Short name T784
Test name
Test status
Simulation time 938691609 ps
CPU time 6.93 seconds
Started Jul 11 06:21:53 PM PDT 24
Finished Jul 11 06:22:04 PM PDT 24
Peak memory 216724 kb
Host smart-4ef1088f-5738-4487-87eb-963d6dc3f539
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712024879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.712024879
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.713629706
Short name T561
Test name
Test status
Simulation time 29801266 ps
CPU time 1.85 seconds
Started Jul 11 06:21:53 PM PDT 24
Finished Jul 11 06:21:59 PM PDT 24
Peak memory 217784 kb
Host smart-31e3a5cd-318e-4f89-b272-bc4f5a0dee72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713629706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.713629706
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.676502576
Short name T201
Test name
Test status
Simulation time 1197282851 ps
CPU time 13.19 seconds
Started Jul 11 06:21:52 PM PDT 24
Finished Jul 11 06:22:09 PM PDT 24
Peak memory 225488 kb
Host smart-d3e6d935-64e0-40d9-b400-5ea6abd07e44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676502576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.676502576
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1210265028
Short name T845
Test name
Test status
Simulation time 348408873 ps
CPU time 9.49 seconds
Started Jul 11 06:21:51 PM PDT 24
Finished Jul 11 06:22:03 PM PDT 24
Peak memory 217748 kb
Host smart-f4271de3-231e-4334-b1e8-4193ab087750
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210265028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1210265028
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.2468109865
Short name T788
Test name
Test status
Simulation time 600192530 ps
CPU time 8.59 seconds
Started Jul 11 06:21:52 PM PDT 24
Finished Jul 11 06:22:04 PM PDT 24
Peak memory 225552 kb
Host smart-65c6d35c-bc52-49e5-aa2c-07b91b78dd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468109865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.2468109865
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2374978685
Short name T675
Test name
Test status
Simulation time 49584618 ps
CPU time 1.18 seconds
Started Jul 11 06:21:51 PM PDT 24
Finished Jul 11 06:21:55 PM PDT 24
Peak memory 217156 kb
Host smart-f364d1e4-cb1f-4653-8a6a-ce5fa3704cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374978685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2374978685
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.527529036
Short name T552
Test name
Test status
Simulation time 325688813 ps
CPU time 29.37 seconds
Started Jul 11 06:21:50 PM PDT 24
Finished Jul 11 06:22:22 PM PDT 24
Peak memory 250492 kb
Host smart-d27eb1cd-c4b6-4857-9124-f9b540f6f70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527529036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.527529036
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.164524074
Short name T653
Test name
Test status
Simulation time 259342990 ps
CPU time 9.29 seconds
Started Jul 11 06:21:53 PM PDT 24
Finished Jul 11 06:22:07 PM PDT 24
Peak memory 248228 kb
Host smart-67ae5a50-62b3-4211-9755-7add0a12ee23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164524074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.164524074
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1849866306
Short name T262
Test name
Test status
Simulation time 3770375554 ps
CPU time 42.21 seconds
Started Jul 11 06:21:53 PM PDT 24
Finished Jul 11 06:22:39 PM PDT 24
Peak memory 250600 kb
Host smart-b2e2d1f9-feb2-4204-8fa2-46cfc2951ca0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849866306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1849866306
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2679956547
Short name T458
Test name
Test status
Simulation time 90839507191 ps
CPU time 752.61 seconds
Started Jul 11 06:21:52 PM PDT 24
Finished Jul 11 06:34:29 PM PDT 24
Peak memory 299832 kb
Host smart-4d5cf029-e370-4973-8562-a035fc74a3c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2679956547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.2679956547
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2820885232
Short name T550
Test name
Test status
Simulation time 30761332 ps
CPU time 0.83 seconds
Started Jul 11 06:21:51 PM PDT 24
Finished Jul 11 06:21:55 PM PDT 24
Peak memory 208420 kb
Host smart-0f5fc0c8-0627-4aa6-bd07-fa800592bbb5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820885232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2820885232
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1119038079
Short name T767
Test name
Test status
Simulation time 18568431 ps
CPU time 0.91 seconds
Started Jul 11 06:21:54 PM PDT 24
Finished Jul 11 06:21:59 PM PDT 24
Peak memory 208528 kb
Host smart-fa88ca1d-a41d-4ee2-990a-2d84a4eea901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119038079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1119038079
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1057332129
Short name T380
Test name
Test status
Simulation time 4126642476 ps
CPU time 22.03 seconds
Started Jul 11 06:21:50 PM PDT 24
Finished Jul 11 06:22:14 PM PDT 24
Peak memory 225664 kb
Host smart-f335e002-837f-418b-9bf6-26e8124d5d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057332129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1057332129
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.4028967806
Short name T745
Test name
Test status
Simulation time 9648743712 ps
CPU time 19.42 seconds
Started Jul 11 06:22:00 PM PDT 24
Finished Jul 11 06:22:24 PM PDT 24
Peak memory 217220 kb
Host smart-530a2e4f-3520-472b-a997-5760320eba9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028967806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.4028967806
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2483774700
Short name T208
Test name
Test status
Simulation time 261546211 ps
CPU time 2.91 seconds
Started Jul 11 06:21:53 PM PDT 24
Finished Jul 11 06:22:00 PM PDT 24
Peak memory 217776 kb
Host smart-2756e5b3-37f4-4ad4-b942-41392350b203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483774700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2483774700
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.3653212385
Short name T197
Test name
Test status
Simulation time 506235951 ps
CPU time 8.62 seconds
Started Jul 11 06:21:58 PM PDT 24
Finished Jul 11 06:22:12 PM PDT 24
Peak memory 217800 kb
Host smart-2727f2f2-11be-4566-bc90-10d1161d3e7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653212385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.3653212385
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1348111484
Short name T100
Test name
Test status
Simulation time 451912190 ps
CPU time 15.46 seconds
Started Jul 11 06:21:56 PM PDT 24
Finished Jul 11 06:22:15 PM PDT 24
Peak memory 225532 kb
Host smart-2c89169b-5ff3-4adc-b162-c4ed5eeed849
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348111484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1348111484
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3189826480
Short name T159
Test name
Test status
Simulation time 1558168182 ps
CPU time 7.79 seconds
Started Jul 11 06:21:55 PM PDT 24
Finished Jul 11 06:22:07 PM PDT 24
Peak memory 225012 kb
Host smart-8a40fffb-89d5-4ded-a58d-235c7a9001a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189826480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3189826480
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.4034537095
Short name T446
Test name
Test status
Simulation time 401463967 ps
CPU time 9.78 seconds
Started Jul 11 06:22:00 PM PDT 24
Finished Jul 11 06:22:14 PM PDT 24
Peak memory 223728 kb
Host smart-327bf448-6074-4199-a08c-149eac9088df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034537095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.4034537095
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.136912514
Short name T424
Test name
Test status
Simulation time 358108165 ps
CPU time 2.02 seconds
Started Jul 11 06:21:50 PM PDT 24
Finished Jul 11 06:21:54 PM PDT 24
Peak memory 223204 kb
Host smart-3c72015f-e1bf-4c9b-a38e-979351440cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136912514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.136912514
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.189247819
Short name T251
Test name
Test status
Simulation time 224973928 ps
CPU time 22.04 seconds
Started Jul 11 06:21:51 PM PDT 24
Finished Jul 11 06:22:16 PM PDT 24
Peak memory 250544 kb
Host smart-93bd3f9d-6174-40d5-82bf-f5cf8ca920e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189247819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.189247819
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3075365974
Short name T568
Test name
Test status
Simulation time 64343709 ps
CPU time 6.52 seconds
Started Jul 11 06:21:50 PM PDT 24
Finished Jul 11 06:21:59 PM PDT 24
Peak memory 246464 kb
Host smart-3a7f984a-23d6-4d00-90cb-fc01c29580b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075365974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3075365974
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.3249290917
Short name T399
Test name
Test status
Simulation time 3293581754 ps
CPU time 77.17 seconds
Started Jul 11 06:21:55 PM PDT 24
Finished Jul 11 06:23:16 PM PDT 24
Peak memory 258672 kb
Host smart-e38220b6-ad0a-4570-b9a4-7db2f9a8fd4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249290917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.3249290917
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2615700831
Short name T357
Test name
Test status
Simulation time 21827239 ps
CPU time 0.97 seconds
Started Jul 11 06:21:54 PM PDT 24
Finished Jul 11 06:21:59 PM PDT 24
Peak memory 208468 kb
Host smart-2e4a363d-bf69-4d55-8093-c5666b2d1d6f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615700831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2615700831
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.33230750
Short name T656
Test name
Test status
Simulation time 21777265 ps
CPU time 0.86 seconds
Started Jul 11 06:21:53 PM PDT 24
Finished Jul 11 06:21:58 PM PDT 24
Peak memory 208528 kb
Host smart-2d385903-c97a-4d01-97a5-792cf39252e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33230750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.33230750
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.587619318
Short name T830
Test name
Test status
Simulation time 780031392 ps
CPU time 10.81 seconds
Started Jul 11 06:21:59 PM PDT 24
Finished Jul 11 06:22:14 PM PDT 24
Peak memory 217780 kb
Host smart-93b66092-9fec-4eba-8572-a4f217ad7876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587619318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.587619318
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1845931909
Short name T386
Test name
Test status
Simulation time 874997478 ps
CPU time 5.54 seconds
Started Jul 11 06:21:54 PM PDT 24
Finished Jul 11 06:22:04 PM PDT 24
Peak memory 217144 kb
Host smart-1cd221d6-7958-42e0-9c72-e18c4627eb3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845931909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1845931909
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1250985102
Short name T457
Test name
Test status
Simulation time 137343614 ps
CPU time 2.08 seconds
Started Jul 11 06:21:58 PM PDT 24
Finished Jul 11 06:22:05 PM PDT 24
Peak memory 217708 kb
Host smart-926c0419-0a96-4219-ab9c-7c392e6d974d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250985102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1250985102
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1920316817
Short name T562
Test name
Test status
Simulation time 410501868 ps
CPU time 15.82 seconds
Started Jul 11 06:21:58 PM PDT 24
Finished Jul 11 06:22:18 PM PDT 24
Peak memory 218440 kb
Host smart-62d98cda-3b7d-4d98-8b6e-77c608989436
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920316817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1920316817
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3757230849
Short name T469
Test name
Test status
Simulation time 285341758 ps
CPU time 9.53 seconds
Started Jul 11 06:21:57 PM PDT 24
Finished Jul 11 06:22:11 PM PDT 24
Peak memory 225520 kb
Host smart-27b02eb3-1a55-441e-ac0b-d056bb5d9dd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757230849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3757230849
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3313360836
Short name T680
Test name
Test status
Simulation time 346662299 ps
CPU time 11.98 seconds
Started Jul 11 06:21:56 PM PDT 24
Finished Jul 11 06:22:12 PM PDT 24
Peak memory 217724 kb
Host smart-dacac621-7673-46b8-b412-3d29aa824956
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313360836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3313360836
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.784590841
Short name T187
Test name
Test status
Simulation time 164139335 ps
CPU time 8.81 seconds
Started Jul 11 06:21:55 PM PDT 24
Finished Jul 11 06:22:08 PM PDT 24
Peak memory 217860 kb
Host smart-6b788122-56ed-4d6a-8c28-63926755e0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784590841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.784590841
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.446332782
Short name T327
Test name
Test status
Simulation time 422190060 ps
CPU time 4.1 seconds
Started Jul 11 06:21:55 PM PDT 24
Finished Jul 11 06:22:03 PM PDT 24
Peak memory 217196 kb
Host smart-5755239b-2675-4f41-baef-0bb21f52826f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446332782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.446332782
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1766506901
Short name T825
Test name
Test status
Simulation time 2653390674 ps
CPU time 33.71 seconds
Started Jul 11 06:21:54 PM PDT 24
Finished Jul 11 06:22:32 PM PDT 24
Peak memory 250624 kb
Host smart-964f4630-c6df-4902-9b0e-f0adf9be80bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766506901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1766506901
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2314652758
Short name T391
Test name
Test status
Simulation time 85569127 ps
CPU time 9.74 seconds
Started Jul 11 06:21:57 PM PDT 24
Finished Jul 11 06:22:12 PM PDT 24
Peak memory 250544 kb
Host smart-deaeabbe-a0a8-4a21-a60e-fac69bb4620b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314652758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2314652758
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.865154290
Short name T732
Test name
Test status
Simulation time 11112921583 ps
CPU time 80.53 seconds
Started Jul 11 06:21:56 PM PDT 24
Finished Jul 11 06:23:21 PM PDT 24
Peak memory 250664 kb
Host smart-9ace4f07-2c4f-40fb-9e50-bdf4ef9fc6d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865154290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.865154290
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.343704526
Short name T219
Test name
Test status
Simulation time 13494099 ps
CPU time 1.14 seconds
Started Jul 11 06:22:14 PM PDT 24
Finished Jul 11 06:22:19 PM PDT 24
Peak memory 211424 kb
Host smart-462aaf28-189c-4288-ab8f-6c71dc3c83ec
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343704526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ct
rl_volatile_unlock_smoke.343704526
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.525634187
Short name T415
Test name
Test status
Simulation time 23644222 ps
CPU time 1.22 seconds
Started Jul 11 06:22:02 PM PDT 24
Finished Jul 11 06:22:08 PM PDT 24
Peak memory 208460 kb
Host smart-9d60936e-6d9d-4b95-bf01-5040d97c6f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525634187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.525634187
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3199897752
Short name T432
Test name
Test status
Simulation time 3339997429 ps
CPU time 20.51 seconds
Started Jul 11 06:21:59 PM PDT 24
Finished Jul 11 06:22:24 PM PDT 24
Peak memory 218572 kb
Host smart-c8b8f519-051d-444c-b09a-89c38eeeb69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199897752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3199897752
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.1138554065
Short name T588
Test name
Test status
Simulation time 5657839218 ps
CPU time 14.34 seconds
Started Jul 11 06:22:02 PM PDT 24
Finished Jul 11 06:22:21 PM PDT 24
Peak memory 217352 kb
Host smart-81d4c721-d8cb-428a-bb0b-74f77ffe4c1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138554065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.1138554065
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1257862375
Short name T445
Test name
Test status
Simulation time 84611342 ps
CPU time 4.04 seconds
Started Jul 11 06:22:01 PM PDT 24
Finished Jul 11 06:22:08 PM PDT 24
Peak memory 217728 kb
Host smart-f61f5dc2-c1cc-4f7f-a5a6-4414e53d44d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257862375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1257862375
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2998628324
Short name T504
Test name
Test status
Simulation time 4738053364 ps
CPU time 21.64 seconds
Started Jul 11 06:21:59 PM PDT 24
Finished Jul 11 06:22:25 PM PDT 24
Peak memory 225660 kb
Host smart-00b39d46-1f96-4d8f-9989-49c1191d8a60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998628324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2998628324
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2769544637
Short name T735
Test name
Test status
Simulation time 500731192 ps
CPU time 12.34 seconds
Started Jul 11 06:22:09 PM PDT 24
Finished Jul 11 06:22:26 PM PDT 24
Peak memory 225520 kb
Host smart-fc723e23-69a4-4841-8018-dfde7100caf7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769544637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2769544637
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.231962471
Short name T281
Test name
Test status
Simulation time 209462659 ps
CPU time 6.45 seconds
Started Jul 11 06:21:58 PM PDT 24
Finished Jul 11 06:22:09 PM PDT 24
Peak memory 217664 kb
Host smart-8b6b9bef-11ba-4366-a0ae-ee40689a8b23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231962471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.231962471
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1906827680
Short name T362
Test name
Test status
Simulation time 1460019809 ps
CPU time 12.43 seconds
Started Jul 11 06:22:01 PM PDT 24
Finished Jul 11 06:22:17 PM PDT 24
Peak memory 225552 kb
Host smart-07ea4956-dcb8-43c2-8667-4fef15b4de29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906827680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1906827680
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2945239014
Short name T441
Test name
Test status
Simulation time 62841690 ps
CPU time 2.66 seconds
Started Jul 11 06:21:55 PM PDT 24
Finished Jul 11 06:22:01 PM PDT 24
Peak memory 217196 kb
Host smart-42ab455b-44ca-4d05-8076-6cd63e4e5e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945239014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2945239014
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3153920228
Short name T651
Test name
Test status
Simulation time 1565399993 ps
CPU time 32.15 seconds
Started Jul 11 06:21:56 PM PDT 24
Finished Jul 11 06:22:33 PM PDT 24
Peak memory 247320 kb
Host smart-ca745631-f139-4e95-9d28-1a07fb1ef81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153920228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3153920228
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1329134755
Short name T706
Test name
Test status
Simulation time 87703304 ps
CPU time 7.72 seconds
Started Jul 11 06:22:09 PM PDT 24
Finished Jul 11 06:22:21 PM PDT 24
Peak memory 250504 kb
Host smart-04a71944-100e-4388-aeb1-60272487c548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329134755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1329134755
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3856088073
Short name T358
Test name
Test status
Simulation time 1007134014 ps
CPU time 16.08 seconds
Started Jul 11 06:22:02 PM PDT 24
Finished Jul 11 06:22:22 PM PDT 24
Peak memory 225496 kb
Host smart-db951209-16a1-4cdf-829f-1b71d6f4b774
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856088073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3856088073
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.418310125
Short name T26
Test name
Test status
Simulation time 32746224 ps
CPU time 0.74 seconds
Started Jul 11 06:21:54 PM PDT 24
Finished Jul 11 06:21:58 PM PDT 24
Peak memory 208228 kb
Host smart-daefa911-eea9-441e-a97a-3c536da82889
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418310125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct
rl_volatile_unlock_smoke.418310125
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.1609429023
Short name T225
Test name
Test status
Simulation time 33004979 ps
CPU time 1 seconds
Started Jul 11 06:22:00 PM PDT 24
Finished Jul 11 06:22:05 PM PDT 24
Peak memory 208540 kb
Host smart-f08946c5-0757-4e02-a3e8-4bd369d34648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609429023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1609429023
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.816504633
Short name T590
Test name
Test status
Simulation time 2289731266 ps
CPU time 14.06 seconds
Started Jul 11 06:22:08 PM PDT 24
Finished Jul 11 06:22:27 PM PDT 24
Peak memory 225652 kb
Host smart-b2427a0c-2faf-44b5-af19-f3506841d1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816504633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.816504633
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.4021800121
Short name T18
Test name
Test status
Simulation time 1007978170 ps
CPU time 6.74 seconds
Started Jul 11 06:22:02 PM PDT 24
Finished Jul 11 06:22:12 PM PDT 24
Peak memory 217208 kb
Host smart-8861757d-d82e-445f-b11e-a4876c461ed1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021800121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.4021800121
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.4057372605
Short name T230
Test name
Test status
Simulation time 87184595 ps
CPU time 1.46 seconds
Started Jul 11 06:21:59 PM PDT 24
Finished Jul 11 06:22:05 PM PDT 24
Peak memory 217772 kb
Host smart-32b406cb-3648-4317-9ebd-55128795e00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057372605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.4057372605
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2129965996
Short name T614
Test name
Test status
Simulation time 276436165 ps
CPU time 9.39 seconds
Started Jul 11 06:22:00 PM PDT 24
Finished Jul 11 06:22:14 PM PDT 24
Peak memory 225524 kb
Host smart-84963362-cd55-4e40-9872-4ba65b8072c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129965996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2129965996
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2957278510
Short name T276
Test name
Test status
Simulation time 2138025419 ps
CPU time 9.73 seconds
Started Jul 11 06:21:59 PM PDT 24
Finished Jul 11 06:22:13 PM PDT 24
Peak memory 217748 kb
Host smart-1dd52d55-3672-4133-920d-ac5de13453b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957278510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2957278510
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3230306673
Short name T806
Test name
Test status
Simulation time 443198277 ps
CPU time 10.61 seconds
Started Jul 11 06:22:00 PM PDT 24
Finished Jul 11 06:22:14 PM PDT 24
Peak memory 225664 kb
Host smart-1aa83bc8-4f91-4c03-8b78-2079729b9ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230306673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3230306673
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.338085891
Short name T51
Test name
Test status
Simulation time 372892562 ps
CPU time 2.65 seconds
Started Jul 11 06:22:09 PM PDT 24
Finished Jul 11 06:22:16 PM PDT 24
Peak memory 214264 kb
Host smart-fea9b7f6-1891-4ec3-8863-373165ea8f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338085891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.338085891
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2520648731
Short name T639
Test name
Test status
Simulation time 1394879331 ps
CPU time 29.96 seconds
Started Jul 11 06:22:00 PM PDT 24
Finished Jul 11 06:22:34 PM PDT 24
Peak memory 250504 kb
Host smart-abc8bc20-6aff-48f5-af6a-16e3ba4109e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520648731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2520648731
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2327458452
Short name T577
Test name
Test status
Simulation time 247059385 ps
CPU time 7.4 seconds
Started Jul 11 06:21:59 PM PDT 24
Finished Jul 11 06:22:10 PM PDT 24
Peak memory 249976 kb
Host smart-c72d361d-ce79-45d4-9c76-0e52f2cd8924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327458452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2327458452
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.128459577
Short name T70
Test name
Test status
Simulation time 3832347904 ps
CPU time 117.41 seconds
Started Jul 11 06:22:01 PM PDT 24
Finished Jul 11 06:24:02 PM PDT 24
Peak memory 225648 kb
Host smart-de2ee2fe-30a9-4dec-a01c-2a4ded5992a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128459577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.128459577
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.161258985
Short name T836
Test name
Test status
Simulation time 12451647 ps
CPU time 0.96 seconds
Started Jul 11 06:21:58 PM PDT 24
Finished Jul 11 06:22:03 PM PDT 24
Peak memory 208432 kb
Host smart-6cdbc37e-575b-4a59-ad1a-e2b255c07171
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161258985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.161258985
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1466818148
Short name T489
Test name
Test status
Simulation time 60669286 ps
CPU time 1.05 seconds
Started Jul 11 06:22:03 PM PDT 24
Finished Jul 11 06:22:08 PM PDT 24
Peak memory 208620 kb
Host smart-de7ade6c-cd43-4749-83d1-8d97556ed59e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466818148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1466818148
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1457655396
Short name T783
Test name
Test status
Simulation time 1072634634 ps
CPU time 9.56 seconds
Started Jul 11 06:22:04 PM PDT 24
Finished Jul 11 06:22:17 PM PDT 24
Peak memory 225592 kb
Host smart-d19f7435-b4b3-4230-bad0-628cfff0932e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457655396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1457655396
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1000111408
Short name T746
Test name
Test status
Simulation time 1318407687 ps
CPU time 16.49 seconds
Started Jul 11 06:22:05 PM PDT 24
Finished Jul 11 06:22:25 PM PDT 24
Peak memory 216992 kb
Host smart-6e022a27-f566-41bb-9510-a34740487280
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000111408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1000111408
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2363362209
Short name T89
Test name
Test status
Simulation time 18453341 ps
CPU time 1.71 seconds
Started Jul 11 06:22:05 PM PDT 24
Finished Jul 11 06:22:11 PM PDT 24
Peak memory 217648 kb
Host smart-bbf79e81-d403-4e31-9175-2735f9a5b502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363362209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2363362209
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2626213304
Short name T392
Test name
Test status
Simulation time 2602427227 ps
CPU time 17.21 seconds
Started Jul 11 06:22:08 PM PDT 24
Finished Jul 11 06:22:30 PM PDT 24
Peak memory 219496 kb
Host smart-0ccaadbb-5380-4b4c-8847-827c20f91fcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626213304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2626213304
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3130672884
Short name T597
Test name
Test status
Simulation time 347110915 ps
CPU time 15.16 seconds
Started Jul 11 06:22:06 PM PDT 24
Finished Jul 11 06:22:25 PM PDT 24
Peak memory 225524 kb
Host smart-58092154-44aa-4c8b-9274-161a746a627a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130672884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3130672884
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.4172049974
Short name T52
Test name
Test status
Simulation time 592027943 ps
CPU time 13.11 seconds
Started Jul 11 06:22:05 PM PDT 24
Finished Jul 11 06:22:23 PM PDT 24
Peak memory 217752 kb
Host smart-4a208698-fcbc-4133-bfa6-b507ce7783ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172049974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
4172049974
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.4087833247
Short name T606
Test name
Test status
Simulation time 352906540 ps
CPU time 8.31 seconds
Started Jul 11 06:22:06 PM PDT 24
Finished Jul 11 06:22:18 PM PDT 24
Peak memory 224288 kb
Host smart-4e759574-fa20-42ce-9194-c817b985c241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087833247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.4087833247
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.382668257
Short name T850
Test name
Test status
Simulation time 66457652 ps
CPU time 3.44 seconds
Started Jul 11 06:22:07 PM PDT 24
Finished Jul 11 06:22:15 PM PDT 24
Peak memory 217212 kb
Host smart-ed022264-70b1-4978-9818-052f1099e378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382668257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.382668257
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2161502998
Short name T151
Test name
Test status
Simulation time 236569663 ps
CPU time 30.84 seconds
Started Jul 11 06:22:13 PM PDT 24
Finished Jul 11 06:22:48 PM PDT 24
Peak memory 250512 kb
Host smart-b195493c-856b-4a30-81f7-6df3e8da7892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161502998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2161502998
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2641476420
Short name T365
Test name
Test status
Simulation time 65785805 ps
CPU time 6.76 seconds
Started Jul 11 06:22:07 PM PDT 24
Finished Jul 11 06:22:18 PM PDT 24
Peak memory 246448 kb
Host smart-5ca20cc7-c79d-47d0-bbb3-b9219aba72ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641476420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2641476420
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.1229203923
Short name T72
Test name
Test status
Simulation time 47151593263 ps
CPU time 186.28 seconds
Started Jul 11 06:22:04 PM PDT 24
Finished Jul 11 06:25:15 PM PDT 24
Peak memory 283276 kb
Host smart-ae3376d5-5c3d-4f0a-8442-c936c691603d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229203923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.1229203923
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.1174731448
Short name T137
Test name
Test status
Simulation time 130296133725 ps
CPU time 847.07 seconds
Started Jul 11 06:22:06 PM PDT 24
Finished Jul 11 06:36:17 PM PDT 24
Peak memory 283460 kb
Host smart-7c22baf3-5f0d-4a9b-adc5-048665060afa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1174731448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.1174731448
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3201810272
Short name T566
Test name
Test status
Simulation time 49228942 ps
CPU time 0.91 seconds
Started Jul 11 06:22:06 PM PDT 24
Finished Jul 11 06:22:11 PM PDT 24
Peak memory 211376 kb
Host smart-f41113c9-f463-4858-83fd-45cf08b68999
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201810272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3201810272
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1687684167
Short name T799
Test name
Test status
Simulation time 40643468 ps
CPU time 1.02 seconds
Started Jul 11 06:22:06 PM PDT 24
Finished Jul 11 06:22:11 PM PDT 24
Peak memory 208400 kb
Host smart-72b51c12-5b57-475e-b526-a9bdfa5e64a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687684167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1687684167
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1876753197
Short name T314
Test name
Test status
Simulation time 445299639 ps
CPU time 12.61 seconds
Started Jul 11 06:22:09 PM PDT 24
Finished Jul 11 06:22:26 PM PDT 24
Peak memory 217696 kb
Host smart-cfb986e1-a8f7-4db0-80a7-d69095546839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876753197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1876753197
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1489257100
Short name T524
Test name
Test status
Simulation time 880927253 ps
CPU time 21.33 seconds
Started Jul 11 06:22:04 PM PDT 24
Finished Jul 11 06:22:30 PM PDT 24
Peak memory 217024 kb
Host smart-0e4aeff1-26e5-41ab-bf9e-1371a4df6a8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489257100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1489257100
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2149230140
Short name T444
Test name
Test status
Simulation time 116976632 ps
CPU time 2.75 seconds
Started Jul 11 06:22:05 PM PDT 24
Finished Jul 11 06:22:13 PM PDT 24
Peak memory 217736 kb
Host smart-df838abf-5c32-437a-85b5-bc3c1dfad776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149230140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2149230140
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3257119582
Short name T833
Test name
Test status
Simulation time 650325569 ps
CPU time 14.03 seconds
Started Jul 11 06:22:04 PM PDT 24
Finished Jul 11 06:22:22 PM PDT 24
Peak memory 225588 kb
Host smart-fe213b9b-b357-48bf-9173-fd2f655c9c03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257119582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3257119582
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3581346616
Short name T29
Test name
Test status
Simulation time 671839792 ps
CPU time 18.2 seconds
Started Jul 11 06:22:06 PM PDT 24
Finished Jul 11 06:22:28 PM PDT 24
Peak memory 225516 kb
Host smart-8af1d518-1261-46dc-9437-f3cf4fb95bf6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581346616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3581346616
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1879619850
Short name T260
Test name
Test status
Simulation time 1395098725 ps
CPU time 6.96 seconds
Started Jul 11 06:22:06 PM PDT 24
Finished Jul 11 06:22:17 PM PDT 24
Peak memory 217736 kb
Host smart-b4541077-265e-44d8-a856-857c339b6f72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879619850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1879619850
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3198629694
Short name T40
Test name
Test status
Simulation time 1530548077 ps
CPU time 8.38 seconds
Started Jul 11 06:22:04 PM PDT 24
Finished Jul 11 06:22:16 PM PDT 24
Peak memory 224880 kb
Host smart-41b84c09-9297-4584-9e2b-1257a3012bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198629694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3198629694
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2139523851
Short name T537
Test name
Test status
Simulation time 64969220 ps
CPU time 2.64 seconds
Started Jul 11 06:22:09 PM PDT 24
Finished Jul 11 06:22:16 PM PDT 24
Peak memory 214124 kb
Host smart-925a80ce-288f-436f-905f-73ed9bfab07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139523851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2139523851
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3813500692
Short name T275
Test name
Test status
Simulation time 348976909 ps
CPU time 23.62 seconds
Started Jul 11 06:22:06 PM PDT 24
Finished Jul 11 06:22:34 PM PDT 24
Peak memory 250520 kb
Host smart-59da7fc1-2b8a-4fd1-9a64-ad4a4fefb312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813500692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3813500692
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1693961778
Short name T193
Test name
Test status
Simulation time 258222603 ps
CPU time 7.15 seconds
Started Jul 11 06:22:04 PM PDT 24
Finished Jul 11 06:22:15 PM PDT 24
Peak memory 250368 kb
Host smart-4e080802-a379-43e5-967c-bd306108d662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693961778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1693961778
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2871688511
Short name T220
Test name
Test status
Simulation time 30072130793 ps
CPU time 41.83 seconds
Started Jul 11 06:22:04 PM PDT 24
Finished Jul 11 06:22:50 PM PDT 24
Peak memory 250560 kb
Host smart-7e8b8eef-3c1d-4d27-974c-d27507965401
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871688511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2871688511
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.1824888490
Short name T789
Test name
Test status
Simulation time 30770302270 ps
CPU time 285.21 seconds
Started Jul 11 06:22:04 PM PDT 24
Finished Jul 11 06:26:54 PM PDT 24
Peak memory 281416 kb
Host smart-a9339db7-fe6e-4c50-97a6-a52b8f5f3667
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1824888490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.1824888490
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2402981604
Short name T578
Test name
Test status
Simulation time 115947804 ps
CPU time 0.85 seconds
Started Jul 11 06:22:02 PM PDT 24
Finished Jul 11 06:22:07 PM PDT 24
Peak memory 208428 kb
Host smart-9b920966-3e5f-48b3-8ce7-a43a8e39e881
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402981604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2402981604
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3223209066
Short name T308
Test name
Test status
Simulation time 58107092 ps
CPU time 0.98 seconds
Started Jul 11 06:22:09 PM PDT 24
Finished Jul 11 06:22:15 PM PDT 24
Peak memory 208548 kb
Host smart-6ebae47b-038b-47f2-a2a1-38a18e51d348
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223209066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3223209066
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.411716959
Short name T751
Test name
Test status
Simulation time 253347740 ps
CPU time 3.87 seconds
Started Jul 11 06:22:14 PM PDT 24
Finished Jul 11 06:22:22 PM PDT 24
Peak memory 217196 kb
Host smart-78be3a9f-94de-42ae-9d5b-f539dc45fea0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411716959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.411716959
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.4238050969
Short name T624
Test name
Test status
Simulation time 148427402 ps
CPU time 2.25 seconds
Started Jul 11 06:22:11 PM PDT 24
Finished Jul 11 06:22:18 PM PDT 24
Peak memory 221648 kb
Host smart-2a6ccd59-6867-4e08-b388-d4a4afc5e2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238050969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.4238050969
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1189721144
Short name T700
Test name
Test status
Simulation time 883561935 ps
CPU time 9.89 seconds
Started Jul 11 06:22:12 PM PDT 24
Finished Jul 11 06:22:26 PM PDT 24
Peak memory 217792 kb
Host smart-ea0cc3a1-6830-403e-8bbd-1a6915d313ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189721144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1189721144
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3705305257
Short name T397
Test name
Test status
Simulation time 1713770069 ps
CPU time 7.42 seconds
Started Jul 11 06:22:11 PM PDT 24
Finished Jul 11 06:22:23 PM PDT 24
Peak memory 225640 kb
Host smart-8f4eec8a-8837-4057-88a6-3e75507fb7aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705305257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3705305257
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.458209583
Short name T329
Test name
Test status
Simulation time 1066326455 ps
CPU time 12.71 seconds
Started Jul 11 06:22:15 PM PDT 24
Finished Jul 11 06:22:31 PM PDT 24
Peak memory 217720 kb
Host smart-9687e647-eac8-4c43-a371-d13446966a79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458209583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.458209583
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2987246010
Short name T296
Test name
Test status
Simulation time 831030781 ps
CPU time 8.47 seconds
Started Jul 11 06:22:12 PM PDT 24
Finished Jul 11 06:22:25 PM PDT 24
Peak memory 225588 kb
Host smart-9c2d16c8-f25e-44e4-82ae-2617c3e5e442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987246010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2987246010
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1642617353
Short name T385
Test name
Test status
Simulation time 32169353 ps
CPU time 2.16 seconds
Started Jul 11 06:22:08 PM PDT 24
Finished Jul 11 06:22:14 PM PDT 24
Peak memory 213572 kb
Host smart-fd17d6b0-cddb-4632-9204-9c936c7eda49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642617353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1642617353
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.851357162
Short name T252
Test name
Test status
Simulation time 1116132698 ps
CPU time 24.64 seconds
Started Jul 11 06:22:04 PM PDT 24
Finished Jul 11 06:22:32 PM PDT 24
Peak memory 250568 kb
Host smart-6272652b-d69e-40a4-861b-adafd7aaad97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851357162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.851357162
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2268397428
Short name T528
Test name
Test status
Simulation time 291917875 ps
CPU time 2.93 seconds
Started Jul 11 06:22:05 PM PDT 24
Finished Jul 11 06:22:13 PM PDT 24
Peak memory 221984 kb
Host smart-7106835a-57ba-438a-9e81-c2f9c3cb499f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268397428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2268397428
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3783247929
Short name T591
Test name
Test status
Simulation time 32759845855 ps
CPU time 155.4 seconds
Started Jul 11 06:22:11 PM PDT 24
Finished Jul 11 06:24:51 PM PDT 24
Peak memory 226784 kb
Host smart-68e9cb61-ab5d-490c-b19a-f79b8aa52ac8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783247929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3783247929
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.2929935834
Short name T141
Test name
Test status
Simulation time 45576792436 ps
CPU time 496.27 seconds
Started Jul 11 06:22:09 PM PDT 24
Finished Jul 11 06:30:30 PM PDT 24
Peak memory 299952 kb
Host smart-8e94d232-e7f3-400a-b9cf-e265c131cc47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2929935834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.2929935834
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2655980904
Short name T77
Test name
Test status
Simulation time 23641235 ps
CPU time 0.91 seconds
Started Jul 11 06:22:08 PM PDT 24
Finished Jul 11 06:22:13 PM PDT 24
Peak memory 211404 kb
Host smart-86ef4e1e-f583-467a-aca4-d8103bccf797
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655980904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2655980904
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.72486227
Short name T86
Test name
Test status
Simulation time 194070034 ps
CPU time 1 seconds
Started Jul 11 06:20:28 PM PDT 24
Finished Jul 11 06:20:31 PM PDT 24
Peak memory 208504 kb
Host smart-71cfc268-0eda-4a73-8c49-4da00014fd65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72486227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.72486227
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.2829462592
Short name T255
Test name
Test status
Simulation time 3174392649 ps
CPU time 18.34 seconds
Started Jul 11 06:20:24 PM PDT 24
Finished Jul 11 06:20:44 PM PDT 24
Peak memory 218668 kb
Host smart-e3c7da00-6956-4150-b3c4-06a10d2e8fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829462592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2829462592
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.4131099135
Short name T683
Test name
Test status
Simulation time 89100889 ps
CPU time 1.85 seconds
Started Jul 11 06:20:22 PM PDT 24
Finished Jul 11 06:20:25 PM PDT 24
Peak memory 217208 kb
Host smart-f7c0a6ba-99e6-4c35-aea0-94d80494cbe1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131099135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.4131099135
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1729309409
Short name T813
Test name
Test status
Simulation time 6753729942 ps
CPU time 23.09 seconds
Started Jul 11 06:20:19 PM PDT 24
Finished Jul 11 06:20:44 PM PDT 24
Peak memory 218420 kb
Host smart-336dbe0d-2a29-4cec-a052-f51d3bc0384c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729309409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1729309409
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3009713563
Short name T160
Test name
Test status
Simulation time 647003313 ps
CPU time 15.49 seconds
Started Jul 11 06:20:27 PM PDT 24
Finished Jul 11 06:20:44 PM PDT 24
Peak memory 217200 kb
Host smart-8fecaae8-89d8-4267-a08c-54201646774e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009713563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.3
009713563
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1273418428
Short name T320
Test name
Test status
Simulation time 162364756 ps
CPU time 2.44 seconds
Started Jul 11 06:20:21 PM PDT 24
Finished Jul 11 06:20:25 PM PDT 24
Peak memory 217728 kb
Host smart-841fc262-3a3f-4880-9b02-7ead6ebc6ed7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273418428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1273418428
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1932912595
Short name T515
Test name
Test status
Simulation time 3944773266 ps
CPU time 12.78 seconds
Started Jul 11 06:20:21 PM PDT 24
Finished Jul 11 06:20:35 PM PDT 24
Peak memory 217200 kb
Host smart-2fc24408-c3aa-4e9a-b33b-1e63a3ee1fb2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932912595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1932912595
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2450069167
Short name T490
Test name
Test status
Simulation time 499526395 ps
CPU time 4 seconds
Started Jul 11 06:20:21 PM PDT 24
Finished Jul 11 06:20:27 PM PDT 24
Peak memory 217136 kb
Host smart-2dc1f0a5-84a2-40db-bf16-5cf9fbac4543
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450069167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2450069167
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2788573674
Short name T721
Test name
Test status
Simulation time 2015698464 ps
CPU time 71.39 seconds
Started Jul 11 06:20:21 PM PDT 24
Finished Jul 11 06:21:34 PM PDT 24
Peak memory 283224 kb
Host smart-f8bef338-2955-46ff-95b0-9ec03aed546c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788573674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2788573674
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.764419964
Short name T351
Test name
Test status
Simulation time 808195117 ps
CPU time 30.45 seconds
Started Jul 11 06:20:24 PM PDT 24
Finished Jul 11 06:20:56 PM PDT 24
Peak memory 250468 kb
Host smart-3629b455-0f29-45a6-adaf-e229fc9526b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764419964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_state_post_trans.764419964
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1541832622
Short name T741
Test name
Test status
Simulation time 599790084 ps
CPU time 2.06 seconds
Started Jul 11 06:20:20 PM PDT 24
Finished Jul 11 06:20:24 PM PDT 24
Peak memory 217744 kb
Host smart-81cc6307-5782-4d47-bcab-1fa65993e8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541832622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1541832622
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3986027807
Short name T500
Test name
Test status
Simulation time 448120693 ps
CPU time 9.89 seconds
Started Jul 11 06:20:20 PM PDT 24
Finished Jul 11 06:20:31 PM PDT 24
Peak memory 217212 kb
Host smart-c5be27fb-c1f2-4777-87cf-7acce96fa5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986027807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3986027807
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1005853007
Short name T84
Test name
Test status
Simulation time 113897482 ps
CPU time 23.29 seconds
Started Jul 11 06:20:30 PM PDT 24
Finished Jul 11 06:20:55 PM PDT 24
Peak memory 268700 kb
Host smart-83169d85-9052-406b-91ba-cc71f5d7b38b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005853007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1005853007
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1681771127
Short name T671
Test name
Test status
Simulation time 666997846 ps
CPU time 10.34 seconds
Started Jul 11 06:20:22 PM PDT 24
Finished Jul 11 06:20:35 PM PDT 24
Peak memory 218444 kb
Host smart-eef11dce-635b-400f-8709-d8969c3088c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681771127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1681771127
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2862783986
Short name T288
Test name
Test status
Simulation time 6665592625 ps
CPU time 11.74 seconds
Started Jul 11 06:20:26 PM PDT 24
Finished Jul 11 06:20:39 PM PDT 24
Peak memory 225588 kb
Host smart-519939c8-da54-4510-a709-4d4c4a306f4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862783986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2862783986
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.583603331
Short name T388
Test name
Test status
Simulation time 309047901 ps
CPU time 11.99 seconds
Started Jul 11 06:20:22 PM PDT 24
Finished Jul 11 06:20:36 PM PDT 24
Peak memory 217740 kb
Host smart-1c55b199-7207-491c-b8e5-eccc46357c57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583603331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.583603331
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1446734930
Short name T42
Test name
Test status
Simulation time 644902704 ps
CPU time 13.05 seconds
Started Jul 11 06:20:27 PM PDT 24
Finished Jul 11 06:20:41 PM PDT 24
Peak memory 225256 kb
Host smart-bc44c315-273d-40c3-bfcf-347382bb0baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446734930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1446734930
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.2774889857
Short name T812
Test name
Test status
Simulation time 25567368 ps
CPU time 1.74 seconds
Started Jul 11 06:20:16 PM PDT 24
Finished Jul 11 06:20:19 PM PDT 24
Peak memory 213248 kb
Host smart-9b393729-7f91-4ecd-a6be-1010c1e31828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774889857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.2774889857
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.4046047120
Short name T82
Test name
Test status
Simulation time 167742784 ps
CPU time 14.22 seconds
Started Jul 11 06:20:21 PM PDT 24
Finished Jul 11 06:20:36 PM PDT 24
Peak memory 250488 kb
Host smart-6551b2dd-afb8-484f-95ec-97eda4832d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046047120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.4046047120
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1714714636
Short name T361
Test name
Test status
Simulation time 109616289 ps
CPU time 6.45 seconds
Started Jul 11 06:20:21 PM PDT 24
Finished Jul 11 06:20:28 PM PDT 24
Peak memory 246672 kb
Host smart-88da9730-a71b-4c04-bda2-83b3027dba6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714714636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1714714636
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1569251817
Short name T375
Test name
Test status
Simulation time 4024640267 ps
CPU time 141.83 seconds
Started Jul 11 06:20:25 PM PDT 24
Finished Jul 11 06:22:48 PM PDT 24
Peak memory 283280 kb
Host smart-8b96462b-3eb5-4d60-9143-56ec935999cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569251817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1569251817
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.4161968327
Short name T436
Test name
Test status
Simulation time 106127892 ps
CPU time 0.83 seconds
Started Jul 11 06:20:16 PM PDT 24
Finished Jul 11 06:20:19 PM PDT 24
Peak memory 208456 kb
Host smart-13aa91f4-0aa9-4ee4-8a60-df53aacbbb91
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161968327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.4161968327
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3681524071
Short name T823
Test name
Test status
Simulation time 86966438 ps
CPU time 1.38 seconds
Started Jul 11 06:22:10 PM PDT 24
Finished Jul 11 06:22:16 PM PDT 24
Peak memory 208480 kb
Host smart-c9a95042-de25-4295-bda4-3995e3bd31e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681524071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3681524071
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2494746664
Short name T851
Test name
Test status
Simulation time 262136767 ps
CPU time 13.36 seconds
Started Jul 11 06:22:11 PM PDT 24
Finished Jul 11 06:22:29 PM PDT 24
Peak memory 217800 kb
Host smart-7beaa9d2-eee0-41ae-851b-18dd66eb71c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494746664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2494746664
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1750332285
Short name T59
Test name
Test status
Simulation time 454593990 ps
CPU time 3.47 seconds
Started Jul 11 06:22:11 PM PDT 24
Finished Jul 11 06:22:19 PM PDT 24
Peak memory 216636 kb
Host smart-95cb2c87-1950-4845-9281-dbf2fad8ca55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750332285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1750332285
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.101617169
Short name T292
Test name
Test status
Simulation time 265521469 ps
CPU time 2.33 seconds
Started Jul 11 06:22:12 PM PDT 24
Finished Jul 11 06:22:19 PM PDT 24
Peak memory 217792 kb
Host smart-d6446cc9-279b-42aa-abfa-7de3cff06c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101617169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.101617169
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1228881628
Short name T196
Test name
Test status
Simulation time 382456994 ps
CPU time 13.03 seconds
Started Jul 11 06:22:09 PM PDT 24
Finished Jul 11 06:22:27 PM PDT 24
Peak memory 225584 kb
Host smart-ebeb9151-fec1-44c0-8e4a-e9b616820f09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228881628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1228881628
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2603874307
Short name T215
Test name
Test status
Simulation time 253395340 ps
CPU time 12.04 seconds
Started Jul 11 06:22:09 PM PDT 24
Finished Jul 11 06:22:26 PM PDT 24
Peak memory 225528 kb
Host smart-5a82861f-538a-4d30-a255-06db2de01458
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603874307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2603874307
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1939748587
Short name T449
Test name
Test status
Simulation time 988539975 ps
CPU time 18.25 seconds
Started Jul 11 06:22:10 PM PDT 24
Finished Jul 11 06:22:32 PM PDT 24
Peak memory 217904 kb
Host smart-8677402f-e02b-4f92-b91e-d3e9829cb5ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939748587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1939748587
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3679161697
Short name T543
Test name
Test status
Simulation time 1330199726 ps
CPU time 8.45 seconds
Started Jul 11 06:22:16 PM PDT 24
Finished Jul 11 06:22:27 PM PDT 24
Peak memory 225568 kb
Host smart-a6518711-a077-493e-986f-3fca812096c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679161697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3679161697
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1951531786
Short name T403
Test name
Test status
Simulation time 319113464 ps
CPU time 2.72 seconds
Started Jul 11 06:22:10 PM PDT 24
Finished Jul 11 06:22:17 PM PDT 24
Peak memory 213732 kb
Host smart-fb235528-7e4c-417d-9523-cfcf985752df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951531786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1951531786
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1051045032
Short name T565
Test name
Test status
Simulation time 241217004 ps
CPU time 28.98 seconds
Started Jul 11 06:22:11 PM PDT 24
Finished Jul 11 06:22:44 PM PDT 24
Peak memory 250544 kb
Host smart-bc074bf4-74a1-4add-8ee8-544735f4136b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051045032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1051045032
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.442282906
Short name T285
Test name
Test status
Simulation time 270570961 ps
CPU time 9.37 seconds
Started Jul 11 06:22:10 PM PDT 24
Finished Jul 11 06:22:24 PM PDT 24
Peak memory 250520 kb
Host smart-2690d88a-a7b5-47c4-a6c3-3e2c7e0420f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442282906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.442282906
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2094210553
Short name T437
Test name
Test status
Simulation time 4582773543 ps
CPU time 137.71 seconds
Started Jul 11 06:22:11 PM PDT 24
Finished Jul 11 06:24:33 PM PDT 24
Peak memory 250692 kb
Host smart-9a51624c-c6fd-40a7-a308-3025c410eaa7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094210553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2094210553
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2292333814
Short name T455
Test name
Test status
Simulation time 23210748 ps
CPU time 0.77 seconds
Started Jul 11 06:22:11 PM PDT 24
Finished Jul 11 06:22:16 PM PDT 24
Peak memory 208340 kb
Host smart-57fbb01d-a489-4a7e-8724-bd348b838de0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292333814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2292333814
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1965632449
Short name T786
Test name
Test status
Simulation time 109499216 ps
CPU time 1.16 seconds
Started Jul 11 06:22:18 PM PDT 24
Finished Jul 11 06:22:22 PM PDT 24
Peak memory 208616 kb
Host smart-8bd67bd4-4ab2-4c7c-8b94-3f826b32a85c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965632449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1965632449
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2669513525
Short name T582
Test name
Test status
Simulation time 204305105 ps
CPU time 8.42 seconds
Started Jul 11 06:22:18 PM PDT 24
Finished Jul 11 06:22:29 PM PDT 24
Peak memory 225600 kb
Host smart-4ea62a15-527e-4a2f-99e8-cb4a01194685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669513525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2669513525
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2291727322
Short name T194
Test name
Test status
Simulation time 50838039 ps
CPU time 2.49 seconds
Started Jul 11 06:22:11 PM PDT 24
Finished Jul 11 06:22:18 PM PDT 24
Peak memory 217880 kb
Host smart-980203e4-5564-4077-a52c-cd0ec9dc5d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291727322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2291727322
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1768112136
Short name T793
Test name
Test status
Simulation time 1411608099 ps
CPU time 17.06 seconds
Started Jul 11 06:22:17 PM PDT 24
Finished Jul 11 06:22:37 PM PDT 24
Peak memory 218452 kb
Host smart-bbf953aa-e717-439c-be4f-92f0a501630b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768112136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1768112136
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3160178016
Short name T277
Test name
Test status
Simulation time 2541008484 ps
CPU time 9.81 seconds
Started Jul 11 06:22:16 PM PDT 24
Finished Jul 11 06:22:29 PM PDT 24
Peak memory 225588 kb
Host smart-8f766909-896c-4c9b-88bc-b9848aec4d60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160178016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.3160178016
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.4226167416
Short name T678
Test name
Test status
Simulation time 357059734 ps
CPU time 9.85 seconds
Started Jul 11 06:22:18 PM PDT 24
Finished Jul 11 06:22:31 PM PDT 24
Peak memory 225256 kb
Host smart-251a4a8e-0ade-444f-bf8e-61d9b2ea75a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226167416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
4226167416
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.731719771
Short name T648
Test name
Test status
Simulation time 166678796 ps
CPU time 7.21 seconds
Started Jul 11 06:22:18 PM PDT 24
Finished Jul 11 06:22:28 PM PDT 24
Peak memory 224468 kb
Host smart-17f15a12-9e54-4241-915e-8f40c948d805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731719771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.731719771
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1253063518
Short name T64
Test name
Test status
Simulation time 18147003 ps
CPU time 1.25 seconds
Started Jul 11 06:22:09 PM PDT 24
Finished Jul 11 06:22:15 PM PDT 24
Peak memory 211652 kb
Host smart-c5c2a1f2-c6d9-4df3-a120-947c3bf2638d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253063518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1253063518
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2403140642
Short name T495
Test name
Test status
Simulation time 200538109 ps
CPU time 23.49 seconds
Started Jul 11 06:22:13 PM PDT 24
Finished Jul 11 06:22:41 PM PDT 24
Peak memory 250528 kb
Host smart-f5ce6ddf-dbea-46d2-8878-0f43ef572de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403140642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2403140642
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1882366362
Short name T711
Test name
Test status
Simulation time 969308649 ps
CPU time 4.46 seconds
Started Jul 11 06:22:13 PM PDT 24
Finished Jul 11 06:22:22 PM PDT 24
Peak memory 225944 kb
Host smart-97a14e73-779b-466f-8298-2bb070c27681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882366362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1882366362
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.3753557114
Short name T81
Test name
Test status
Simulation time 18556493398 ps
CPU time 166 seconds
Started Jul 11 06:22:17 PM PDT 24
Finished Jul 11 06:25:06 PM PDT 24
Peak memory 291548 kb
Host smart-4b6e8811-1b5d-4c41-96dc-490897a5cbdb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753557114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.3753557114
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.3914944817
Short name T142
Test name
Test status
Simulation time 35310855684 ps
CPU time 680.07 seconds
Started Jul 11 06:22:12 PM PDT 24
Finished Jul 11 06:33:37 PM PDT 24
Peak memory 421884 kb
Host smart-24e9208c-9f13-477b-a0ec-8190cb631665
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3914944817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.3914944817
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2403666737
Short name T302
Test name
Test status
Simulation time 16502244 ps
CPU time 1.05 seconds
Started Jul 11 06:22:15 PM PDT 24
Finished Jul 11 06:22:20 PM PDT 24
Peak memory 211440 kb
Host smart-39427956-cdfc-472b-ac6c-5d1acd937c22
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403666737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2403666737
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1364790212
Short name T352
Test name
Test status
Simulation time 71166582 ps
CPU time 0.85 seconds
Started Jul 11 06:22:23 PM PDT 24
Finished Jul 11 06:22:32 PM PDT 24
Peak memory 208408 kb
Host smart-0588d4e1-c262-4040-83d8-bfe030450ca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364790212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1364790212
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1395259953
Short name T621
Test name
Test status
Simulation time 302231457 ps
CPU time 10.29 seconds
Started Jul 11 06:22:17 PM PDT 24
Finished Jul 11 06:22:31 PM PDT 24
Peak memory 217668 kb
Host smart-785c9bfa-db62-4378-a341-aecc01529afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395259953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1395259953
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1444988925
Short name T21
Test name
Test status
Simulation time 363138961 ps
CPU time 4.15 seconds
Started Jul 11 06:22:13 PM PDT 24
Finished Jul 11 06:22:21 PM PDT 24
Peak memory 217204 kb
Host smart-47fad619-220c-40e6-b828-b851ba0b6ebf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444988925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1444988925
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.791319055
Short name T754
Test name
Test status
Simulation time 286701989 ps
CPU time 2.79 seconds
Started Jul 11 06:22:16 PM PDT 24
Finished Jul 11 06:22:22 PM PDT 24
Peak memory 222008 kb
Host smart-78ca7b0c-9b1a-4a46-804f-61268f3df99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791319055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.791319055
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2625404613
Short name T31
Test name
Test status
Simulation time 369642625 ps
CPU time 10.65 seconds
Started Jul 11 06:22:17 PM PDT 24
Finished Jul 11 06:22:30 PM PDT 24
Peak memory 225592 kb
Host smart-fb62aec5-c69b-4857-a66e-ace723bf2027
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625404613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2625404613
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.4100765498
Short name T429
Test name
Test status
Simulation time 1256564456 ps
CPU time 9.23 seconds
Started Jul 11 06:22:16 PM PDT 24
Finished Jul 11 06:22:29 PM PDT 24
Peak memory 225528 kb
Host smart-64c2cfc7-243f-44d7-8b4d-b909e199480c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100765498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
4100765498
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3225967021
Short name T643
Test name
Test status
Simulation time 305890144 ps
CPU time 11.54 seconds
Started Jul 11 06:22:18 PM PDT 24
Finished Jul 11 06:22:33 PM PDT 24
Peak memory 217860 kb
Host smart-033469d6-11d0-45b5-b9fb-d55a982232ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225967021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3225967021
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.568677855
Short name T61
Test name
Test status
Simulation time 135089693 ps
CPU time 2.57 seconds
Started Jul 11 06:22:14 PM PDT 24
Finished Jul 11 06:22:20 PM PDT 24
Peak memory 217216 kb
Host smart-8fc6b560-979e-4878-94f5-7dcfbc28cd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568677855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.568677855
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1958987052
Short name T748
Test name
Test status
Simulation time 225290505 ps
CPU time 20.7 seconds
Started Jul 11 06:22:19 PM PDT 24
Finished Jul 11 06:22:43 PM PDT 24
Peak memory 250548 kb
Host smart-cd8dcedc-648e-47ad-a764-475f2b6e2e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958987052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1958987052
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1496181603
Short name T224
Test name
Test status
Simulation time 381888839 ps
CPU time 3.96 seconds
Started Jul 11 06:22:18 PM PDT 24
Finished Jul 11 06:22:25 PM PDT 24
Peak memory 225960 kb
Host smart-b808afd1-49bc-4eef-bc87-0e96d5d3c96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496181603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1496181603
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1207588155
Short name T594
Test name
Test status
Simulation time 3395305908 ps
CPU time 100.44 seconds
Started Jul 11 06:22:15 PM PDT 24
Finished Jul 11 06:23:59 PM PDT 24
Peak memory 274348 kb
Host smart-24514d1a-0f08-4f28-be0f-1a74728059da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207588155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1207588155
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3658090333
Short name T140
Test name
Test status
Simulation time 44943041935 ps
CPU time 811.49 seconds
Started Jul 11 06:22:17 PM PDT 24
Finished Jul 11 06:35:51 PM PDT 24
Peak memory 283520 kb
Host smart-673902ad-875e-4581-83eb-10d3b6e42f84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3658090333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.3658090333
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.773953208
Short name T384
Test name
Test status
Simulation time 13264551 ps
CPU time 0.94 seconds
Started Jul 11 06:22:18 PM PDT 24
Finished Jul 11 06:22:22 PM PDT 24
Peak memory 208468 kb
Host smart-de124933-4d4e-4bc6-bedc-684e7027d6ec
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773953208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct
rl_volatile_unlock_smoke.773953208
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2916664531
Short name T451
Test name
Test status
Simulation time 312912524 ps
CPU time 1.03 seconds
Started Jul 11 06:22:19 PM PDT 24
Finished Jul 11 06:22:23 PM PDT 24
Peak memory 208528 kb
Host smart-87bef611-5530-4ca8-87ce-83ad10d9b10f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916664531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2916664531
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1161426013
Short name T720
Test name
Test status
Simulation time 1508036111 ps
CPU time 11.75 seconds
Started Jul 11 06:22:20 PM PDT 24
Finished Jul 11 06:22:38 PM PDT 24
Peak memory 217800 kb
Host smart-a8763944-3741-4ca4-b9cc-325db68ab8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161426013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1161426013
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3337806830
Short name T608
Test name
Test status
Simulation time 1071149022 ps
CPU time 7.28 seconds
Started Jul 11 06:22:19 PM PDT 24
Finished Jul 11 06:22:32 PM PDT 24
Peak memory 216664 kb
Host smart-0caa1b34-802f-401d-9630-67ce0f03c04b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337806830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3337806830
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2712166139
Short name T798
Test name
Test status
Simulation time 76434733 ps
CPU time 2.34 seconds
Started Jul 11 06:22:19 PM PDT 24
Finished Jul 11 06:22:24 PM PDT 24
Peak memory 221700 kb
Host smart-06f15cc1-deaf-48bb-9f58-ff24faafdc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712166139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2712166139
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3003600492
Short name T156
Test name
Test status
Simulation time 207357194 ps
CPU time 11.16 seconds
Started Jul 11 06:22:18 PM PDT 24
Finished Jul 11 06:22:32 PM PDT 24
Peak memory 217740 kb
Host smart-56398d47-b16a-438e-8ddb-75377e50b304
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003600492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3003600492
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.249653698
Short name T337
Test name
Test status
Simulation time 1487988922 ps
CPU time 15.53 seconds
Started Jul 11 06:22:24 PM PDT 24
Finished Jul 11 06:22:47 PM PDT 24
Peak memory 225524 kb
Host smart-0a29ea77-4282-4111-ade5-40403d2acb0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249653698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_di
gest.249653698
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1014141552
Short name T366
Test name
Test status
Simulation time 1911406430 ps
CPU time 10.22 seconds
Started Jul 11 06:22:17 PM PDT 24
Finished Jul 11 06:22:30 PM PDT 24
Peak memory 217724 kb
Host smart-5deb689f-6a01-4bf6-a898-736f7d30e015
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014141552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1014141552
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3544918078
Short name T394
Test name
Test status
Simulation time 1126641551 ps
CPU time 10.46 seconds
Started Jul 11 06:22:21 PM PDT 24
Finished Jul 11 06:22:39 PM PDT 24
Peak memory 225520 kb
Host smart-a953ab2f-20cc-4a1c-a709-004cfe7894aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544918078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3544918078
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3608015710
Short name T80
Test name
Test status
Simulation time 60453277 ps
CPU time 2.68 seconds
Started Jul 11 06:22:19 PM PDT 24
Finished Jul 11 06:22:27 PM PDT 24
Peak memory 222996 kb
Host smart-175db5c0-236a-42fc-a64b-9ccdd856cf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608015710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3608015710
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3148605017
Short name T231
Test name
Test status
Simulation time 418031934 ps
CPU time 26.54 seconds
Started Jul 11 06:22:19 PM PDT 24
Finished Jul 11 06:22:53 PM PDT 24
Peak memory 250536 kb
Host smart-a6b7bc22-3d50-41d7-8b45-ce03337bfb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148605017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3148605017
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.4163612096
Short name T780
Test name
Test status
Simulation time 84251184 ps
CPU time 8.35 seconds
Started Jul 11 06:22:20 PM PDT 24
Finished Jul 11 06:22:34 PM PDT 24
Peak memory 250504 kb
Host smart-86f9379f-c2c5-48c5-b3c4-741208bfd8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163612096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.4163612096
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1735554404
Short name T447
Test name
Test status
Simulation time 7368710759 ps
CPU time 60.92 seconds
Started Jul 11 06:22:19 PM PDT 24
Finished Jul 11 06:23:23 PM PDT 24
Peak memory 225648 kb
Host smart-28656660-38f7-4394-bd77-f9b02b2b9e32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735554404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1735554404
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.2115111615
Short name T503
Test name
Test status
Simulation time 58897585784 ps
CPU time 520.7 seconds
Started Jul 11 06:22:18 PM PDT 24
Finished Jul 11 06:31:02 PM PDT 24
Peak memory 283432 kb
Host smart-d123ea01-8a52-4110-b33f-29bf2cb01436
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2115111615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.2115111615
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.108547165
Short name T617
Test name
Test status
Simulation time 13605580 ps
CPU time 0.91 seconds
Started Jul 11 06:22:17 PM PDT 24
Finished Jul 11 06:22:21 PM PDT 24
Peak memory 211480 kb
Host smart-fd63dec6-b09b-413e-a30e-c48660537b8a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108547165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.108547165
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.4238321899
Short name T242
Test name
Test status
Simulation time 155285974 ps
CPU time 1.07 seconds
Started Jul 11 06:22:25 PM PDT 24
Finished Jul 11 06:22:32 PM PDT 24
Peak memory 208508 kb
Host smart-fd296e94-249f-477c-ab74-4f9dc05bc0d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238321899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.4238321899
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.3341850656
Short name T298
Test name
Test status
Simulation time 440432942 ps
CPU time 13.18 seconds
Started Jul 11 06:22:35 PM PDT 24
Finished Jul 11 06:22:56 PM PDT 24
Peak memory 225192 kb
Host smart-10b34ebd-bab0-4542-806d-92d6cb6806a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341850656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3341850656
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1567768206
Short name T541
Test name
Test status
Simulation time 877765336 ps
CPU time 6.98 seconds
Started Jul 11 06:22:27 PM PDT 24
Finished Jul 11 06:22:41 PM PDT 24
Peak memory 217356 kb
Host smart-20b8d0b3-2c1a-4980-896e-7f2d01421e1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567768206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1567768206
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.163341620
Short name T477
Test name
Test status
Simulation time 31318817 ps
CPU time 1.98 seconds
Started Jul 11 06:22:23 PM PDT 24
Finished Jul 11 06:22:33 PM PDT 24
Peak memory 217804 kb
Host smart-6f550455-aff5-465c-a6ba-ba08b1371281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163341620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.163341620
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2676311878
Short name T777
Test name
Test status
Simulation time 331506534 ps
CPU time 11.46 seconds
Started Jul 11 06:22:28 PM PDT 24
Finished Jul 11 06:22:45 PM PDT 24
Peak memory 225576 kb
Host smart-32abe455-4c12-4a4e-b11f-4f6eee230ddd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676311878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2676311878
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3472993823
Short name T794
Test name
Test status
Simulation time 506681944 ps
CPU time 11.54 seconds
Started Jul 11 06:22:27 PM PDT 24
Finished Jul 11 06:22:45 PM PDT 24
Peak memory 225668 kb
Host smart-dd4a5dc4-f1f9-4ecb-a8c0-5309a7d464c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472993823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3472993823
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.848075077
Short name T750
Test name
Test status
Simulation time 1775073468 ps
CPU time 7.82 seconds
Started Jul 11 06:22:28 PM PDT 24
Finished Jul 11 06:22:42 PM PDT 24
Peak memory 217668 kb
Host smart-f3b51f31-a251-4c1a-9938-bcf9abf5f9bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848075077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.848075077
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.285166573
Short name T493
Test name
Test status
Simulation time 4278506139 ps
CPU time 8.03 seconds
Started Jul 11 06:22:27 PM PDT 24
Finished Jul 11 06:22:41 PM PDT 24
Peak memory 225660 kb
Host smart-7ff109bd-002f-488c-b83e-992560bdaf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285166573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.285166573
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.4255506135
Short name T239
Test name
Test status
Simulation time 85659259 ps
CPU time 1.77 seconds
Started Jul 11 06:22:21 PM PDT 24
Finished Jul 11 06:22:30 PM PDT 24
Peak memory 213316 kb
Host smart-2c87e963-76ea-4309-b14b-73a3761159b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255506135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.4255506135
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2483656724
Short name T350
Test name
Test status
Simulation time 275461307 ps
CPU time 26.05 seconds
Started Jul 11 06:22:19 PM PDT 24
Finished Jul 11 06:22:52 PM PDT 24
Peak memory 250540 kb
Host smart-231179dc-28ff-4679-95f5-5fac437f30da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483656724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2483656724
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1535342403
Short name T311
Test name
Test status
Simulation time 85209347 ps
CPU time 6.52 seconds
Started Jul 11 06:22:20 PM PDT 24
Finished Jul 11 06:22:34 PM PDT 24
Peak memory 245504 kb
Host smart-45550bc7-4d4a-4206-b9a4-56a88aba58c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535342403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1535342403
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3601148911
Short name T733
Test name
Test status
Simulation time 4914972224 ps
CPU time 114.75 seconds
Started Jul 11 06:22:23 PM PDT 24
Finished Jul 11 06:24:26 PM PDT 24
Peak memory 272984 kb
Host smart-285bfd1c-a4ca-400b-9457-1d20f9459248
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601148911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3601148911
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.1248543742
Short name T139
Test name
Test status
Simulation time 409844470106 ps
CPU time 382.03 seconds
Started Jul 11 06:22:35 PM PDT 24
Finished Jul 11 06:29:03 PM PDT 24
Peak memory 340880 kb
Host smart-6d6180a3-5b1a-4ab0-800f-117bbb56b506
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1248543742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.1248543742
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.4157781961
Short name T817
Test name
Test status
Simulation time 16338099 ps
CPU time 0.95 seconds
Started Jul 11 06:22:18 PM PDT 24
Finished Jul 11 06:22:22 PM PDT 24
Peak memory 211360 kb
Host smart-ecde9ca7-113f-4c1b-8bb2-f012a75dd270
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157781961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.4157781961
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2357199961
Short name T629
Test name
Test status
Simulation time 42634996 ps
CPU time 0.96 seconds
Started Jul 11 06:22:28 PM PDT 24
Finished Jul 11 06:22:35 PM PDT 24
Peak memory 208528 kb
Host smart-31147892-4361-49b1-bd07-c4e92caffbe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357199961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2357199961
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.192365412
Short name T381
Test name
Test status
Simulation time 1880932553 ps
CPU time 14.07 seconds
Started Jul 11 06:22:24 PM PDT 24
Finished Jul 11 06:22:45 PM PDT 24
Peak memory 217788 kb
Host smart-ced4ab35-ab49-4f0a-bd9e-efe2a07a3948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192365412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.192365412
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.952040080
Short name T632
Test name
Test status
Simulation time 112474901 ps
CPU time 3.77 seconds
Started Jul 11 06:22:22 PM PDT 24
Finished Jul 11 06:22:34 PM PDT 24
Peak memory 216756 kb
Host smart-b664d11a-9912-4da2-bbe9-818be0e6f32f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952040080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.952040080
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.897313442
Short name T509
Test name
Test status
Simulation time 39754557 ps
CPU time 1.47 seconds
Started Jul 11 06:22:25 PM PDT 24
Finished Jul 11 06:22:33 PM PDT 24
Peak memory 217796 kb
Host smart-efc648ee-1961-4c62-9704-f1020045d1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897313442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.897313442
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3438216712
Short name T571
Test name
Test status
Simulation time 355350846 ps
CPU time 13.64 seconds
Started Jul 11 06:22:26 PM PDT 24
Finished Jul 11 06:22:46 PM PDT 24
Peak memory 225596 kb
Host smart-d40ce10d-cc0a-4598-9cc1-2bd0f42a7143
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438216712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3438216712
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.146611206
Short name T694
Test name
Test status
Simulation time 262815739 ps
CPU time 9.15 seconds
Started Jul 11 06:22:24 PM PDT 24
Finished Jul 11 06:22:40 PM PDT 24
Peak memory 225548 kb
Host smart-d1a7123b-b2a5-4f74-8645-af7ee0650000
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146611206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.146611206
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3617877331
Short name T513
Test name
Test status
Simulation time 814850499 ps
CPU time 6.53 seconds
Started Jul 11 06:22:25 PM PDT 24
Finished Jul 11 06:22:38 PM PDT 24
Peak memory 217744 kb
Host smart-47900169-02ff-4a4a-8480-7f7a4147dba1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617877331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
3617877331
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2956189286
Short name T433
Test name
Test status
Simulation time 219617218 ps
CPU time 6.86 seconds
Started Jul 11 06:22:25 PM PDT 24
Finished Jul 11 06:22:38 PM PDT 24
Peak memory 225648 kb
Host smart-3762c061-d9b3-494b-a327-de1960608cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956189286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2956189286
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3323794698
Short name T687
Test name
Test status
Simulation time 1502541942 ps
CPU time 10.18 seconds
Started Jul 11 06:22:24 PM PDT 24
Finished Jul 11 06:22:41 PM PDT 24
Peak memory 217204 kb
Host smart-7e7bdd89-64c0-48d6-abf3-fc0a8497100a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323794698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3323794698
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.3257489430
Short name T310
Test name
Test status
Simulation time 1396760737 ps
CPU time 27.75 seconds
Started Jul 11 06:22:28 PM PDT 24
Finished Jul 11 06:23:01 PM PDT 24
Peak memory 250712 kb
Host smart-ab1ce332-f685-4fe6-91eb-0671c327e3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257489430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3257489430
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.4249424111
Short name T203
Test name
Test status
Simulation time 62726338 ps
CPU time 12.88 seconds
Started Jul 11 06:22:27 PM PDT 24
Finished Jul 11 06:22:46 PM PDT 24
Peak memory 250720 kb
Host smart-6013f370-6566-4fa6-8d05-85ef58c8e98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249424111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.4249424111
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2367667881
Short name T856
Test name
Test status
Simulation time 1864603670 ps
CPU time 65.52 seconds
Started Jul 11 06:22:23 PM PDT 24
Finished Jul 11 06:23:37 PM PDT 24
Peak memory 250452 kb
Host smart-611572fe-2a11-48f0-83e2-5d9bc80f996f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367667881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2367667881
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2632940109
Short name T368
Test name
Test status
Simulation time 43895960 ps
CPU time 0.88 seconds
Started Jul 11 06:22:24 PM PDT 24
Finished Jul 11 06:22:32 PM PDT 24
Peak memory 211360 kb
Host smart-4e39d46f-252a-4b0f-980c-1235b4e518a3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632940109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.2632940109
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2403349236
Short name T574
Test name
Test status
Simulation time 50781645 ps
CPU time 1.74 seconds
Started Jul 11 06:22:26 PM PDT 24
Finished Jul 11 06:22:35 PM PDT 24
Peak memory 208628 kb
Host smart-96b57498-435e-4539-b290-ed68e7362942
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403349236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2403349236
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1764967759
Short name T294
Test name
Test status
Simulation time 5436088836 ps
CPU time 17.69 seconds
Started Jul 11 06:22:28 PM PDT 24
Finished Jul 11 06:22:51 PM PDT 24
Peak memory 217780 kb
Host smart-1b0da235-22b6-400a-8b6a-951ca15efca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764967759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1764967759
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1001888166
Short name T426
Test name
Test status
Simulation time 190445101 ps
CPU time 5.55 seconds
Started Jul 11 06:22:25 PM PDT 24
Finished Jul 11 06:22:37 PM PDT 24
Peak memory 217192 kb
Host smart-82fc2837-de80-4849-a846-f5aaf58b04cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001888166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1001888166
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3181355980
Short name T309
Test name
Test status
Simulation time 234168224 ps
CPU time 2.49 seconds
Started Jul 11 06:22:25 PM PDT 24
Finished Jul 11 06:22:34 PM PDT 24
Peak memory 217736 kb
Host smart-443326db-2cfe-4588-92b7-fe630ffb136f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181355980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3181355980
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1940827235
Short name T646
Test name
Test status
Simulation time 1482590494 ps
CPU time 11.51 seconds
Started Jul 11 06:22:25 PM PDT 24
Finished Jul 11 06:22:43 PM PDT 24
Peak memory 218128 kb
Host smart-17089f7c-49a9-4a29-bafa-44d4f9a7fe14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940827235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1940827235
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3430167783
Short name T642
Test name
Test status
Simulation time 1076166273 ps
CPU time 12.22 seconds
Started Jul 11 06:22:26 PM PDT 24
Finished Jul 11 06:22:45 PM PDT 24
Peak memory 225592 kb
Host smart-0cb2ee1f-6a24-45de-9813-d2ad6bac9cc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430167783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3430167783
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3732412792
Short name T49
Test name
Test status
Simulation time 4625635303 ps
CPU time 12.46 seconds
Started Jul 11 06:22:27 PM PDT 24
Finished Jul 11 06:22:46 PM PDT 24
Peak memory 217804 kb
Host smart-e5bd0359-039b-4312-a67b-a08704bb9cb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732412792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3732412792
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.4014097517
Short name T10
Test name
Test status
Simulation time 15265226 ps
CPU time 1.12 seconds
Started Jul 11 06:22:22 PM PDT 24
Finished Jul 11 06:22:31 PM PDT 24
Peak memory 217128 kb
Host smart-5fd9c09b-b929-49e7-a012-fd67f006c992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014097517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.4014097517
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2579876192
Short name T710
Test name
Test status
Simulation time 252013277 ps
CPU time 18.9 seconds
Started Jul 11 06:22:35 PM PDT 24
Finished Jul 11 06:23:01 PM PDT 24
Peak memory 250168 kb
Host smart-6b843f70-6183-4641-8c64-a588b430f8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579876192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2579876192
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2090760227
Short name T536
Test name
Test status
Simulation time 47641910 ps
CPU time 2.4 seconds
Started Jul 11 06:22:25 PM PDT 24
Finished Jul 11 06:22:34 PM PDT 24
Peak memory 221748 kb
Host smart-5e327166-29f1-4969-abf3-43afdf7b4cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090760227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2090760227
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3525401766
Short name T810
Test name
Test status
Simulation time 9573253578 ps
CPU time 89.41 seconds
Started Jul 11 06:22:29 PM PDT 24
Finished Jul 11 06:24:06 PM PDT 24
Peak memory 225556 kb
Host smart-9b59c1af-08dd-4676-b3ac-dfc25c3478b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525401766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3525401766
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3430436299
Short name T512
Test name
Test status
Simulation time 41573601 ps
CPU time 1.04 seconds
Started Jul 11 06:22:27 PM PDT 24
Finished Jul 11 06:22:34 PM PDT 24
Peak memory 211392 kb
Host smart-019f368f-330e-4497-b59f-1fe32b41ac76
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430436299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3430436299
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2948313492
Short name T217
Test name
Test status
Simulation time 17345267 ps
CPU time 1.17 seconds
Started Jul 11 06:22:29 PM PDT 24
Finished Jul 11 06:22:36 PM PDT 24
Peak memory 208544 kb
Host smart-60206d78-454a-4f5b-921b-906123e64421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948313492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2948313492
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3348519679
Short name T625
Test name
Test status
Simulation time 307522271 ps
CPU time 13.12 seconds
Started Jul 11 06:22:28 PM PDT 24
Finished Jul 11 06:22:48 PM PDT 24
Peak memory 217740 kb
Host smart-9f27934d-044f-4b1b-9a3d-25de177edee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348519679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3348519679
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.290377618
Short name T23
Test name
Test status
Simulation time 2125014500 ps
CPU time 7.06 seconds
Started Jul 11 06:22:37 PM PDT 24
Finished Jul 11 06:22:53 PM PDT 24
Peak memory 217172 kb
Host smart-292e2fda-c244-4404-a643-a32c6a6c1b6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290377618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.290377618
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1035660795
Short name T752
Test name
Test status
Simulation time 321606366 ps
CPU time 2.54 seconds
Started Jul 11 06:22:31 PM PDT 24
Finished Jul 11 06:22:40 PM PDT 24
Peak memory 217648 kb
Host smart-b191fd94-171b-4232-8536-daba8a36784b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035660795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1035660795
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.286679941
Short name T188
Test name
Test status
Simulation time 903539972 ps
CPU time 17.34 seconds
Started Jul 11 06:22:28 PM PDT 24
Finished Jul 11 06:22:52 PM PDT 24
Peak memory 218404 kb
Host smart-57cf047d-7d8c-4607-8bbe-8d99b157a3ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286679941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.286679941
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1083281177
Short name T243
Test name
Test status
Simulation time 2041764749 ps
CPU time 10.18 seconds
Started Jul 11 06:22:30 PM PDT 24
Finished Jul 11 06:22:47 PM PDT 24
Peak memory 225492 kb
Host smart-0d073bd0-c1a1-4fbf-881e-fdb395cf74a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083281177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1083281177
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.635420693
Short name T821
Test name
Test status
Simulation time 375462363 ps
CPU time 13.27 seconds
Started Jul 11 06:22:29 PM PDT 24
Finished Jul 11 06:22:49 PM PDT 24
Peak memory 225532 kb
Host smart-a614e5d3-2640-49e0-b490-bcacd33ff48f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635420693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.635420693
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.334390054
Short name T724
Test name
Test status
Simulation time 195447031 ps
CPU time 5.7 seconds
Started Jul 11 06:22:31 PM PDT 24
Finished Jul 11 06:22:44 PM PDT 24
Peak memory 224260 kb
Host smart-c4315e00-de88-4c06-809f-bd49bbd9f6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334390054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.334390054
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.545079333
Short name T427
Test name
Test status
Simulation time 449012647 ps
CPU time 9.99 seconds
Started Jul 11 06:22:27 PM PDT 24
Finished Jul 11 06:22:43 PM PDT 24
Peak memory 217216 kb
Host smart-ba3ff236-fe07-432e-8aa9-1c9a5b208d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545079333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.545079333
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3270266409
Short name T613
Test name
Test status
Simulation time 1195250299 ps
CPU time 22.89 seconds
Started Jul 11 06:22:29 PM PDT 24
Finished Jul 11 06:23:00 PM PDT 24
Peak memory 250540 kb
Host smart-93efa642-384b-4823-a746-b1d515b1ef00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270266409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3270266409
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1623401482
Short name T787
Test name
Test status
Simulation time 66318667 ps
CPU time 6.85 seconds
Started Jul 11 06:22:28 PM PDT 24
Finished Jul 11 06:22:41 PM PDT 24
Peak memory 246044 kb
Host smart-0affdae9-a14e-4788-9e8e-f53942cbfae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623401482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1623401482
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.447414757
Short name T104
Test name
Test status
Simulation time 14772811345 ps
CPU time 243.1 seconds
Started Jul 11 06:22:31 PM PDT 24
Finished Jul 11 06:26:41 PM PDT 24
Peak memory 271876 kb
Host smart-cb5b033f-91f9-44c2-93b0-b372735641b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447414757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.447414757
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.824450259
Short name T13
Test name
Test status
Simulation time 16992865958 ps
CPU time 517.66 seconds
Started Jul 11 06:22:30 PM PDT 24
Finished Jul 11 06:31:14 PM PDT 24
Peak memory 304756 kb
Host smart-e5d96b5a-75cf-40f3-93f4-9e93435b0a5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=824450259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.824450259
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1002335758
Short name T501
Test name
Test status
Simulation time 10937766 ps
CPU time 0.91 seconds
Started Jul 11 06:22:29 PM PDT 24
Finished Jul 11 06:22:36 PM PDT 24
Peak memory 208452 kb
Host smart-73fb7216-3283-4ee0-968e-cc662931f90b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002335758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1002335758
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2747228907
Short name T534
Test name
Test status
Simulation time 105526910 ps
CPU time 1.02 seconds
Started Jul 11 06:22:33 PM PDT 24
Finished Jul 11 06:22:41 PM PDT 24
Peak memory 208376 kb
Host smart-ef0b55c6-468f-4521-9249-e8a65c127444
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747228907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2747228907
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.586257156
Short name T584
Test name
Test status
Simulation time 247254976 ps
CPU time 12.8 seconds
Started Jul 11 06:22:28 PM PDT 24
Finished Jul 11 06:22:47 PM PDT 24
Peak memory 225600 kb
Host smart-bfcb8f09-baac-442b-a6ef-5e2b052bb598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586257156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.586257156
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3601404935
Short name T238
Test name
Test status
Simulation time 128395281 ps
CPU time 1.52 seconds
Started Jul 11 06:22:34 PM PDT 24
Finished Jul 11 06:22:43 PM PDT 24
Peak memory 217328 kb
Host smart-690e953f-865b-4307-a90f-4a2218b8bcaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601404935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.3601404935
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.157922798
Short name T600
Test name
Test status
Simulation time 93834659 ps
CPU time 3.07 seconds
Started Jul 11 06:22:31 PM PDT 24
Finished Jul 11 06:22:41 PM PDT 24
Peak memory 222152 kb
Host smart-68093e9e-1e97-4b24-941d-a6e50cd8a733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157922798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.157922798
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1325659452
Short name T36
Test name
Test status
Simulation time 2024705254 ps
CPU time 19.78 seconds
Started Jul 11 06:22:34 PM PDT 24
Finished Jul 11 06:23:01 PM PDT 24
Peak memory 217932 kb
Host smart-2bef2569-fdf4-4a96-951d-2216c3590109
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325659452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1325659452
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3435656378
Short name T822
Test name
Test status
Simulation time 1236646300 ps
CPU time 10.58 seconds
Started Jul 11 06:22:35 PM PDT 24
Finished Jul 11 06:22:53 PM PDT 24
Peak memory 225488 kb
Host smart-8159c8ae-8735-4dc9-b0b9-d3731f1ad03d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435656378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3435656378
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2367302691
Short name T465
Test name
Test status
Simulation time 1099879172 ps
CPU time 8.96 seconds
Started Jul 11 06:22:37 PM PDT 24
Finished Jul 11 06:22:55 PM PDT 24
Peak memory 217908 kb
Host smart-bd40fa7f-f4e6-4fe2-a54b-e2f842378049
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367302691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2367302691
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.920009933
Short name T44
Test name
Test status
Simulation time 2254864622 ps
CPU time 9.88 seconds
Started Jul 11 06:22:38 PM PDT 24
Finished Jul 11 06:22:57 PM PDT 24
Peak memory 225720 kb
Host smart-a273a994-9cc8-4b2c-8bac-c23b84274f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920009933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.920009933
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1934984801
Short name T615
Test name
Test status
Simulation time 140627897 ps
CPU time 3.56 seconds
Started Jul 11 06:22:29 PM PDT 24
Finished Jul 11 06:22:40 PM PDT 24
Peak memory 217208 kb
Host smart-bdc09dc9-0ee3-40c9-ada8-987626671458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934984801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1934984801
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1789461013
Short name T295
Test name
Test status
Simulation time 619259861 ps
CPU time 30.47 seconds
Started Jul 11 06:22:27 PM PDT 24
Finished Jul 11 06:23:03 PM PDT 24
Peak memory 250524 kb
Host smart-c92093ad-6a52-408b-bdd2-fd159685f8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789461013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1789461013
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1030920412
Short name T844
Test name
Test status
Simulation time 74679804 ps
CPU time 8.78 seconds
Started Jul 11 06:22:28 PM PDT 24
Finished Jul 11 06:22:42 PM PDT 24
Peak memory 250480 kb
Host smart-52268d8c-8b21-4768-acf5-807341d41979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030920412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1030920412
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2187780558
Short name T323
Test name
Test status
Simulation time 92859859510 ps
CPU time 107.71 seconds
Started Jul 11 06:22:34 PM PDT 24
Finished Jul 11 06:24:28 PM PDT 24
Peak memory 247372 kb
Host smart-ea8bef47-5fd8-402e-a0bb-acaf82dfbfaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187780558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2187780558
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2135590749
Short name T33
Test name
Test status
Simulation time 12509324 ps
CPU time 0.8 seconds
Started Jul 11 06:22:30 PM PDT 24
Finished Jul 11 06:22:37 PM PDT 24
Peak memory 208108 kb
Host smart-d069ba0e-fdb3-4a14-98c6-847a4978eb1d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135590749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2135590749
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3273114450
Short name T792
Test name
Test status
Simulation time 20338083 ps
CPU time 1.01 seconds
Started Jul 11 06:22:34 PM PDT 24
Finished Jul 11 06:22:42 PM PDT 24
Peak memory 208564 kb
Host smart-2f228168-7c72-4d75-abc9-c4a63f82e780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273114450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3273114450
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2026636600
Short name T50
Test name
Test status
Simulation time 1211616300 ps
CPU time 13.46 seconds
Started Jul 11 06:22:35 PM PDT 24
Finished Jul 11 06:22:56 PM PDT 24
Peak memory 217764 kb
Host smart-0aed805b-30ac-4e98-97ab-9dd7fd83b390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026636600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2026636600
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.999668269
Short name T556
Test name
Test status
Simulation time 623634694 ps
CPU time 7.76 seconds
Started Jul 11 06:22:35 PM PDT 24
Finished Jul 11 06:22:50 PM PDT 24
Peak memory 216928 kb
Host smart-39fb9552-5dda-4534-aa4b-f5088c4ea5a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999668269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.999668269
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1112835544
Short name T189
Test name
Test status
Simulation time 143936350 ps
CPU time 2.71 seconds
Started Jul 11 06:22:32 PM PDT 24
Finished Jul 11 06:22:42 PM PDT 24
Peak memory 217788 kb
Host smart-d2df7bfc-e1fe-47a8-b81e-319f4df8c27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112835544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1112835544
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.3935857224
Short name T326
Test name
Test status
Simulation time 619683195 ps
CPU time 15.29 seconds
Started Jul 11 06:22:32 PM PDT 24
Finished Jul 11 06:22:55 PM PDT 24
Peak memory 218436 kb
Host smart-c351a2fd-ca65-420f-96cb-93e3bd6acfdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935857224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3935857224
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.4071477608
Short name T695
Test name
Test status
Simulation time 256848370 ps
CPU time 9.04 seconds
Started Jul 11 06:22:35 PM PDT 24
Finished Jul 11 06:22:52 PM PDT 24
Peak memory 225392 kb
Host smart-ccfa9d06-508a-4218-8d9b-9012ea3732d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071477608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.4071477608
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1448449105
Short name T301
Test name
Test status
Simulation time 3432463994 ps
CPU time 7.45 seconds
Started Jul 11 06:22:35 PM PDT 24
Finished Jul 11 06:22:49 PM PDT 24
Peak memory 217720 kb
Host smart-17a9730f-21c1-4532-a167-67cec491640b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448449105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1448449105
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.4280474158
Short name T611
Test name
Test status
Simulation time 1303069523 ps
CPU time 7.64 seconds
Started Jul 11 06:22:38 PM PDT 24
Finished Jul 11 06:22:55 PM PDT 24
Peak memory 225652 kb
Host smart-a4040de4-98ff-499e-8084-e3f41a881500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280474158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.4280474158
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2810611554
Short name T263
Test name
Test status
Simulation time 244776321 ps
CPU time 5.78 seconds
Started Jul 11 06:22:36 PM PDT 24
Finished Jul 11 06:22:51 PM PDT 24
Peak memory 217240 kb
Host smart-fcf94a4e-c71f-4cfb-8068-c2e1452b0608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810611554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2810611554
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3132451712
Short name T827
Test name
Test status
Simulation time 230434324 ps
CPU time 28.17 seconds
Started Jul 11 06:22:36 PM PDT 24
Finished Jul 11 06:23:12 PM PDT 24
Peak memory 250556 kb
Host smart-0c822083-0331-4746-8573-36dceafce0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132451712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3132451712
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1012804409
Short name T236
Test name
Test status
Simulation time 990638685 ps
CPU time 7.37 seconds
Started Jul 11 06:22:35 PM PDT 24
Finished Jul 11 06:22:50 PM PDT 24
Peak memory 246452 kb
Host smart-817d06b4-3761-488e-bdc6-bbe4311e60f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012804409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1012804409
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2227515945
Short name T807
Test name
Test status
Simulation time 26156959678 ps
CPU time 114.66 seconds
Started Jul 11 06:22:33 PM PDT 24
Finished Jul 11 06:24:34 PM PDT 24
Peak memory 250524 kb
Host smart-829705ac-8c03-404d-b7dc-cb139ab6c629
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227515945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2227515945
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1825887060
Short name T599
Test name
Test status
Simulation time 14478145 ps
CPU time 0.98 seconds
Started Jul 11 06:22:32 PM PDT 24
Finished Jul 11 06:22:39 PM PDT 24
Peak memory 211412 kb
Host smart-9e8e0ce5-522d-4472-8ec7-8b4cc58d313a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825887060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1825887060
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1523693873
Short name T291
Test name
Test status
Simulation time 62160064 ps
CPU time 0.82 seconds
Started Jul 11 06:20:30 PM PDT 24
Finished Jul 11 06:20:32 PM PDT 24
Peak memory 208392 kb
Host smart-2c3ff8a3-b276-4807-9c0a-787821ee7d25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523693873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1523693873
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1603809295
Short name T530
Test name
Test status
Simulation time 1394179174 ps
CPU time 12.3 seconds
Started Jul 11 06:20:26 PM PDT 24
Finished Jul 11 06:20:40 PM PDT 24
Peak memory 217732 kb
Host smart-7e4b4399-af61-4fab-881c-d3c13b264d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603809295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1603809295
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.384065067
Short name T688
Test name
Test status
Simulation time 404527922 ps
CPU time 4.49 seconds
Started Jul 11 06:20:33 PM PDT 24
Finished Jul 11 06:20:38 PM PDT 24
Peak memory 216588 kb
Host smart-7653812c-a125-426b-b77b-fd4023fbc39e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384065067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.384065067
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.3783142803
Short name T16
Test name
Test status
Simulation time 2770049254 ps
CPU time 40.62 seconds
Started Jul 11 06:20:32 PM PDT 24
Finished Jul 11 06:21:14 PM PDT 24
Peak memory 218396 kb
Host smart-54108ba1-4beb-4688-bc1e-37eb3bfd76fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783142803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.3783142803
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.808029858
Short name T278
Test name
Test status
Simulation time 894082515 ps
CPU time 9.68 seconds
Started Jul 11 06:20:31 PM PDT 24
Finished Jul 11 06:20:42 PM PDT 24
Peak memory 217296 kb
Host smart-7f4c942b-fb1b-411e-9b85-abf1dad694da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808029858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.808029858
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.327006736
Short name T785
Test name
Test status
Simulation time 2034884845 ps
CPU time 8.34 seconds
Started Jul 11 06:20:35 PM PDT 24
Finished Jul 11 06:20:45 PM PDT 24
Peak memory 223804 kb
Host smart-82057fd6-92cc-4b8b-88d1-bbd2048bdb0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327006736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
prog_failure.327006736
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.462983775
Short name T612
Test name
Test status
Simulation time 1216469968 ps
CPU time 15.43 seconds
Started Jul 11 06:20:35 PM PDT 24
Finished Jul 11 06:20:52 PM PDT 24
Peak memory 217144 kb
Host smart-714f4856-b673-4421-bda3-8e795129a37f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462983775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.462983775
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.332764082
Short name T204
Test name
Test status
Simulation time 342772560 ps
CPU time 3.17 seconds
Started Jul 11 06:20:28 PM PDT 24
Finished Jul 11 06:20:32 PM PDT 24
Peak memory 217080 kb
Host smart-404e8fa0-8242-4bf3-8c0c-f99daada211b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332764082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.332764082
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3465575845
Short name T684
Test name
Test status
Simulation time 4979309327 ps
CPU time 87.96 seconds
Started Jul 11 06:20:24 PM PDT 24
Finished Jul 11 06:21:54 PM PDT 24
Peak memory 282944 kb
Host smart-d62b35c6-56df-417e-a0f1-cd8d575253ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465575845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3465575845
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.823701837
Short name T796
Test name
Test status
Simulation time 498746556 ps
CPU time 12.23 seconds
Started Jul 11 06:20:33 PM PDT 24
Finished Jul 11 06:20:46 PM PDT 24
Peak memory 250468 kb
Host smart-0ac00910-2e5e-4943-83bb-6e746091803a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823701837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.823701837
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1640538610
Short name T641
Test name
Test status
Simulation time 27421895 ps
CPU time 2.12 seconds
Started Jul 11 06:20:30 PM PDT 24
Finished Jul 11 06:20:34 PM PDT 24
Peak memory 217772 kb
Host smart-b8bb10a4-b375-4062-b9ec-54a264839b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640538610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1640538610
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.223949253
Short name T771
Test name
Test status
Simulation time 999768121 ps
CPU time 9.28 seconds
Started Jul 11 06:20:24 PM PDT 24
Finished Jul 11 06:20:35 PM PDT 24
Peak memory 217208 kb
Host smart-8d14618e-f387-46fa-a991-048ec4f38ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223949253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.223949253
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1563738987
Short name T344
Test name
Test status
Simulation time 1758793268 ps
CPU time 18.52 seconds
Started Jul 11 06:20:33 PM PDT 24
Finished Jul 11 06:20:53 PM PDT 24
Peak memory 225508 kb
Host smart-4f6bdb4c-6645-4ef0-8f6b-d92f6072aa5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563738987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.1563738987
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.272360989
Short name T354
Test name
Test status
Simulation time 332302108 ps
CPU time 6.7 seconds
Started Jul 11 06:20:30 PM PDT 24
Finished Jul 11 06:20:38 PM PDT 24
Peak memory 217912 kb
Host smart-0768fa08-4d18-4c78-9be6-ffc71bf46691
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272360989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.272360989
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.545351522
Short name T544
Test name
Test status
Simulation time 1141590494 ps
CPU time 12.27 seconds
Started Jul 11 06:20:25 PM PDT 24
Finished Jul 11 06:20:39 PM PDT 24
Peak memory 217812 kb
Host smart-b083ee0f-b7aa-4fea-a7cc-e10417dc5ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545351522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.545351522
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.528955336
Short name T373
Test name
Test status
Simulation time 54354092 ps
CPU time 2.93 seconds
Started Jul 11 06:20:22 PM PDT 24
Finished Jul 11 06:20:26 PM PDT 24
Peak memory 217220 kb
Host smart-6ec6708b-f40d-4520-b9b6-3917055f481f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528955336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.528955336
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1155680511
Short name T764
Test name
Test status
Simulation time 368591790 ps
CPU time 35.56 seconds
Started Jul 11 06:20:24 PM PDT 24
Finished Jul 11 06:21:01 PM PDT 24
Peak memory 250540 kb
Host smart-d0a158af-9f52-475a-9b9d-1ddeab130956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155680511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1155680511
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.683277062
Short name T241
Test name
Test status
Simulation time 327747611 ps
CPU time 5.75 seconds
Started Jul 11 06:20:27 PM PDT 24
Finished Jul 11 06:20:34 PM PDT 24
Peak memory 245988 kb
Host smart-f61cd77c-70b1-4e7e-8c6d-bd8215109bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683277062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.683277062
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2879939700
Short name T274
Test name
Test status
Simulation time 1661226669 ps
CPU time 49.49 seconds
Started Jul 11 06:20:33 PM PDT 24
Finished Jul 11 06:21:24 PM PDT 24
Peak memory 273776 kb
Host smart-7f114676-9643-4f8a-94b5-8035637c4f8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879939700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2879939700
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1715622048
Short name T603
Test name
Test status
Simulation time 13991359 ps
CPU time 0.81 seconds
Started Jul 11 06:20:28 PM PDT 24
Finished Jul 11 06:20:30 PM PDT 24
Peak memory 208316 kb
Host smart-d4a72ab7-adb3-457a-b26b-08cc3a5aff13
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715622048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1715622048
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.532184686
Short name T619
Test name
Test status
Simulation time 91007211 ps
CPU time 1.22 seconds
Started Jul 11 06:20:38 PM PDT 24
Finished Jul 11 06:20:41 PM PDT 24
Peak memory 208624 kb
Host smart-64e5424d-826a-4574-b443-8f8ac9835e8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532184686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.532184686
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.290087418
Short name T183
Test name
Test status
Simulation time 25427826 ps
CPU time 0.8 seconds
Started Jul 11 06:20:34 PM PDT 24
Finished Jul 11 06:20:37 PM PDT 24
Peak memory 208316 kb
Host smart-d29c519b-e888-4495-b158-6c86934813c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290087418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.290087418
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2262294022
Short name T661
Test name
Test status
Simulation time 638400954 ps
CPU time 12.53 seconds
Started Jul 11 06:20:38 PM PDT 24
Finished Jul 11 06:20:52 PM PDT 24
Peak memory 225616 kb
Host smart-c7ca637a-dfbb-442b-ac07-261192d58f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262294022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2262294022
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2468795709
Short name T649
Test name
Test status
Simulation time 483058483 ps
CPU time 2.28 seconds
Started Jul 11 06:20:37 PM PDT 24
Finished Jul 11 06:20:41 PM PDT 24
Peak memory 217208 kb
Host smart-17d459f2-e933-4c77-9a60-d9eb7315a948
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468795709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2468795709
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2291914933
Short name T708
Test name
Test status
Simulation time 2175645706 ps
CPU time 33.58 seconds
Started Jul 11 06:20:34 PM PDT 24
Finished Jul 11 06:21:09 PM PDT 24
Peak memory 217788 kb
Host smart-a9a7cba0-a049-4f56-9ff3-7d36616f54d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291914933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2291914933
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1348815918
Short name T677
Test name
Test status
Simulation time 1061905600 ps
CPU time 23.29 seconds
Started Jul 11 06:20:37 PM PDT 24
Finished Jul 11 06:21:01 PM PDT 24
Peak memory 217268 kb
Host smart-bba24081-84ea-40fc-af0f-49b3d31b4d3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348815918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
348815918
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1584190277
Short name T221
Test name
Test status
Simulation time 90155371 ps
CPU time 1.79 seconds
Started Jul 11 06:20:39 PM PDT 24
Finished Jul 11 06:20:42 PM PDT 24
Peak memory 217700 kb
Host smart-2fa7399c-88ee-4926-a1b1-f4a6b16730dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584190277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1584190277
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2185717023
Short name T592
Test name
Test status
Simulation time 1340952158 ps
CPU time 20.46 seconds
Started Jul 11 06:20:36 PM PDT 24
Finished Jul 11 06:20:58 PM PDT 24
Peak memory 217140 kb
Host smart-50eab1a2-9ba3-447e-ae06-9c54e99e5577
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185717023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2185717023
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.141309256
Short name T213
Test name
Test status
Simulation time 467500529 ps
CPU time 4.98 seconds
Started Jul 11 06:20:35 PM PDT 24
Finished Jul 11 06:20:41 PM PDT 24
Peak memory 217140 kb
Host smart-1978e46a-fa0a-4a5d-b14e-03ca552e0a3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141309256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.141309256
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.217884081
Short name T416
Test name
Test status
Simulation time 5452864027 ps
CPU time 33.26 seconds
Started Jul 11 06:20:38 PM PDT 24
Finished Jul 11 06:21:13 PM PDT 24
Peak memory 250496 kb
Host smart-0e8a15ee-6afa-448a-bffc-0eb2a80816bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217884081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.217884081
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3477447549
Short name T481
Test name
Test status
Simulation time 716412518 ps
CPU time 7.3 seconds
Started Jul 11 06:20:33 PM PDT 24
Finished Jul 11 06:20:42 PM PDT 24
Peak memory 217596 kb
Host smart-e99d0914-52e5-4a1d-9a1f-76ba0b0da533
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477447549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3477447549
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1187577832
Short name T657
Test name
Test status
Simulation time 84979646 ps
CPU time 3.61 seconds
Started Jul 11 06:20:38 PM PDT 24
Finished Jul 11 06:20:43 PM PDT 24
Peak memory 217780 kb
Host smart-87a66d7b-0179-4b74-bfde-3ad56d31fce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187577832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1187577832
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2816550529
Short name T58
Test name
Test status
Simulation time 1474916033 ps
CPU time 13.27 seconds
Started Jul 11 06:20:39 PM PDT 24
Finished Jul 11 06:20:53 PM PDT 24
Peak memory 217180 kb
Host smart-9c0626fa-b490-43aa-a94f-20d276d034f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816550529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2816550529
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.4208884620
Short name T627
Test name
Test status
Simulation time 324753940 ps
CPU time 11.08 seconds
Started Jul 11 06:20:36 PM PDT 24
Finished Jul 11 06:20:48 PM PDT 24
Peak memory 218012 kb
Host smart-8827e6ff-7902-4274-93f9-d0c4b0887857
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208884620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.4208884620
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.4073763473
Short name T25
Test name
Test status
Simulation time 404615816 ps
CPU time 12.14 seconds
Started Jul 11 06:20:40 PM PDT 24
Finished Jul 11 06:20:54 PM PDT 24
Peak memory 225508 kb
Host smart-d8637356-f357-476b-b880-fb6c5714d124
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073763473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.4073763473
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2351087644
Short name T325
Test name
Test status
Simulation time 1228086535 ps
CPU time 11.53 seconds
Started Jul 11 06:20:36 PM PDT 24
Finished Jul 11 06:20:49 PM PDT 24
Peak memory 217740 kb
Host smart-56e448e7-73ff-495c-91f9-119f6680ecfe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351087644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
351087644
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3936989586
Short name T43
Test name
Test status
Simulation time 409365132 ps
CPU time 10.56 seconds
Started Jul 11 06:20:33 PM PDT 24
Finished Jul 11 06:20:44 PM PDT 24
Peak memory 217868 kb
Host smart-f87de76c-af65-455a-b34d-e64a9843f523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936989586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3936989586
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.63409517
Short name T343
Test name
Test status
Simulation time 243737961 ps
CPU time 10.01 seconds
Started Jul 11 06:20:31 PM PDT 24
Finished Jul 11 06:20:42 PM PDT 24
Peak memory 217152 kb
Host smart-99645d98-af08-44b1-82e9-86d3b801762c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63409517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.63409517
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.590330806
Short name T467
Test name
Test status
Simulation time 840198054 ps
CPU time 19.78 seconds
Started Jul 11 06:20:37 PM PDT 24
Finished Jul 11 06:20:58 PM PDT 24
Peak memory 250420 kb
Host smart-2459e203-7502-4641-9d1d-e021a20acf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590330806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.590330806
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2293688743
Short name T234
Test name
Test status
Simulation time 43790348 ps
CPU time 7.07 seconds
Started Jul 11 06:20:38 PM PDT 24
Finished Jul 11 06:20:46 PM PDT 24
Peak memory 250520 kb
Host smart-5d9d8a4c-da09-4fd9-9862-92b763e1aa0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293688743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2293688743
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.4087381218
Short name T731
Test name
Test status
Simulation time 2074976095 ps
CPU time 54.94 seconds
Started Jul 11 06:20:35 PM PDT 24
Finished Jul 11 06:21:31 PM PDT 24
Peak memory 250528 kb
Host smart-1df5ca8a-5eff-4cde-b827-081ae7a04461
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087381218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.4087381218
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3200791289
Short name T620
Test name
Test status
Simulation time 242472797521 ps
CPU time 211.33 seconds
Started Jul 11 06:20:39 PM PDT 24
Finished Jul 11 06:24:11 PM PDT 24
Peak memory 273412 kb
Host smart-0f71af03-bce7-4110-8673-633e77864893
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3200791289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.3200791289
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.179891338
Short name T32
Test name
Test status
Simulation time 39249303 ps
CPU time 0.96 seconds
Started Jul 11 06:20:28 PM PDT 24
Finished Jul 11 06:20:30 PM PDT 24
Peak memory 211340 kb
Host smart-8ed1c96c-6dfa-49a4-a67e-403355819473
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179891338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr
l_volatile_unlock_smoke.179891338
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.604155036
Short name T758
Test name
Test status
Simulation time 237079229 ps
CPU time 1.01 seconds
Started Jul 11 06:20:54 PM PDT 24
Finished Jul 11 06:20:59 PM PDT 24
Peak memory 208468 kb
Host smart-298d08a9-32c3-4f22-95d4-de691c09af03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604155036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.604155036
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.4182582799
Short name T482
Test name
Test status
Simulation time 10924272 ps
CPU time 0.78 seconds
Started Jul 11 06:20:53 PM PDT 24
Finished Jul 11 06:20:58 PM PDT 24
Peak memory 208424 kb
Host smart-81209c99-6e5e-4804-a90d-73a701b49fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182582799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.4182582799
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1540221414
Short name T658
Test name
Test status
Simulation time 436753135 ps
CPU time 10.73 seconds
Started Jul 11 06:20:37 PM PDT 24
Finished Jul 11 06:20:49 PM PDT 24
Peak memory 225512 kb
Host smart-dc7bdee9-7020-4410-b26b-7fd9f4b1d76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540221414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1540221414
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2499173844
Short name T529
Test name
Test status
Simulation time 106564327 ps
CPU time 3.45 seconds
Started Jul 11 06:20:40 PM PDT 24
Finished Jul 11 06:20:46 PM PDT 24
Peak memory 217264 kb
Host smart-cd09cbc2-cb64-4ade-b881-01243742bc43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499173844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2499173844
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1577304618
Short name T439
Test name
Test status
Simulation time 16393299321 ps
CPU time 53.88 seconds
Started Jul 11 06:20:44 PM PDT 24
Finished Jul 11 06:21:41 PM PDT 24
Peak memory 219252 kb
Host smart-0006cd95-e66f-47f4-aa3d-4bdaa44602c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577304618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1577304618
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3334389707
Short name T809
Test name
Test status
Simulation time 218339626 ps
CPU time 1.54 seconds
Started Jul 11 06:20:41 PM PDT 24
Finished Jul 11 06:20:45 PM PDT 24
Peak memory 217492 kb
Host smart-7e53214c-d8ce-4d9f-9b1b-50143804551c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334389707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
334389707
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.338573217
Short name T790
Test name
Test status
Simulation time 473761594 ps
CPU time 9.51 seconds
Started Jul 11 06:20:45 PM PDT 24
Finished Jul 11 06:20:57 PM PDT 24
Peak memory 223696 kb
Host smart-e702391e-6585-4548-bde5-3ebde31723d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338573217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.338573217
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.172300026
Short name T75
Test name
Test status
Simulation time 4017060826 ps
CPU time 15.28 seconds
Started Jul 11 06:20:42 PM PDT 24
Finished Jul 11 06:21:00 PM PDT 24
Peak memory 217184 kb
Host smart-507449fe-8de5-469b-9a1f-d2da36c64ff0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172300026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.172300026
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3289311415
Short name T664
Test name
Test status
Simulation time 341172333 ps
CPU time 2.91 seconds
Started Jul 11 06:20:43 PM PDT 24
Finished Jul 11 06:20:48 PM PDT 24
Peak memory 217092 kb
Host smart-e7e2e1f2-d2d4-42d2-ba8c-a615015b4cd2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289311415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3289311415
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.816216563
Short name T382
Test name
Test status
Simulation time 2787268860 ps
CPU time 86.06 seconds
Started Jul 11 06:20:44 PM PDT 24
Finished Jul 11 06:22:13 PM PDT 24
Peak memory 283492 kb
Host smart-70013659-fd48-4972-b51e-eb8b1f03caa4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816216563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.816216563
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.635573835
Short name T383
Test name
Test status
Simulation time 3143015109 ps
CPU time 20.54 seconds
Started Jul 11 06:20:39 PM PDT 24
Finished Jul 11 06:21:01 PM PDT 24
Peak memory 225896 kb
Host smart-2e20d810-d484-4d6e-8306-aa1191123eb5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635573835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.635573835
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1134030394
Short name T522
Test name
Test status
Simulation time 162422263 ps
CPU time 2.93 seconds
Started Jul 11 06:20:37 PM PDT 24
Finished Jul 11 06:20:41 PM PDT 24
Peak memory 217644 kb
Host smart-89db8bf8-0be3-4080-9415-e1a46361cf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134030394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1134030394
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1346224304
Short name T618
Test name
Test status
Simulation time 1640605662 ps
CPU time 12.58 seconds
Started Jul 11 06:20:40 PM PDT 24
Finished Jul 11 06:20:54 PM PDT 24
Peak memory 214196 kb
Host smart-8014bb90-af6c-40b3-a236-237a66451bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346224304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1346224304
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.4021178814
Short name T572
Test name
Test status
Simulation time 744786531 ps
CPU time 12.31 seconds
Started Jul 11 06:20:46 PM PDT 24
Finished Jul 11 06:21:00 PM PDT 24
Peak memory 219500 kb
Host smart-140e734f-bb91-4024-9741-b85dfae01d77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021178814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.4021178814
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.487137497
Short name T2
Test name
Test status
Simulation time 1520756731 ps
CPU time 17.19 seconds
Started Jul 11 06:20:41 PM PDT 24
Finished Jul 11 06:21:01 PM PDT 24
Peak memory 225520 kb
Host smart-bddbab36-7224-4ec7-aed6-badacbe2906f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487137497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.487137497
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.516799295
Short name T390
Test name
Test status
Simulation time 1560352511 ps
CPU time 9.38 seconds
Started Jul 11 06:20:43 PM PDT 24
Finished Jul 11 06:20:56 PM PDT 24
Peak memory 217736 kb
Host smart-d70a2af7-42e0-47e7-b72d-2c6d86798794
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516799295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.516799295
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1145206468
Short name T814
Test name
Test status
Simulation time 194233463 ps
CPU time 9.76 seconds
Started Jul 11 06:20:44 PM PDT 24
Finished Jul 11 06:20:56 PM PDT 24
Peak memory 217856 kb
Host smart-7d2f1e5a-8137-4828-88ad-f406eeefb2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145206468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1145206468
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.123712264
Short name T855
Test name
Test status
Simulation time 34653060 ps
CPU time 2.44 seconds
Started Jul 11 06:20:36 PM PDT 24
Finished Jul 11 06:20:39 PM PDT 24
Peak memory 214144 kb
Host smart-8f74b16b-c621-4081-9458-e10e39eaac11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123712264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.123712264
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1058532972
Short name T370
Test name
Test status
Simulation time 317899321 ps
CPU time 23.93 seconds
Started Jul 11 06:20:36 PM PDT 24
Finished Jul 11 06:21:01 PM PDT 24
Peak memory 250532 kb
Host smart-d50289d4-4dbf-43a7-9794-64c3e5ec61d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058532972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1058532972
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3646514932
Short name T801
Test name
Test status
Simulation time 179252465 ps
CPU time 6.24 seconds
Started Jul 11 06:20:35 PM PDT 24
Finished Jul 11 06:20:43 PM PDT 24
Peak memory 246072 kb
Host smart-8c92b30b-1521-4223-9b8e-737e4d81d86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646514932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3646514932
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3145766666
Short name T689
Test name
Test status
Simulation time 3597752983 ps
CPU time 135.58 seconds
Started Jul 11 06:20:46 PM PDT 24
Finished Jul 11 06:23:04 PM PDT 24
Peak memory 250560 kb
Host smart-38a314b3-5cc4-447f-ae3e-e1cc35257a87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145766666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3145766666
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3273022653
Short name T261
Test name
Test status
Simulation time 41336313 ps
CPU time 0.89 seconds
Started Jul 11 06:20:39 PM PDT 24
Finished Jul 11 06:20:42 PM PDT 24
Peak memory 208452 kb
Host smart-f0e2d29f-db38-472c-9912-66289a07b765
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273022653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3273022653
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1520254105
Short name T466
Test name
Test status
Simulation time 136282958 ps
CPU time 2.06 seconds
Started Jul 11 06:20:45 PM PDT 24
Finished Jul 11 06:20:50 PM PDT 24
Peak memory 208616 kb
Host smart-25d91698-39bd-429d-bc8f-b665b25cabb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520254105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1520254105
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1249561659
Short name T516
Test name
Test status
Simulation time 26102427 ps
CPU time 0.85 seconds
Started Jul 11 06:20:43 PM PDT 24
Finished Jul 11 06:20:47 PM PDT 24
Peak memory 208528 kb
Host smart-fa3b8bd1-bdea-4d32-976f-cc62c108442b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249561659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1249561659
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1760168648
Short name T90
Test name
Test status
Simulation time 463067625 ps
CPU time 9.45 seconds
Started Jul 11 06:20:43 PM PDT 24
Finished Jul 11 06:20:55 PM PDT 24
Peak memory 225588 kb
Host smart-50f54452-3266-41c0-ab8b-90a8916494ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760168648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1760168648
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3918702068
Short name T474
Test name
Test status
Simulation time 429044087 ps
CPU time 1.89 seconds
Started Jul 11 06:20:54 PM PDT 24
Finished Jul 11 06:20:59 PM PDT 24
Peak memory 216916 kb
Host smart-20ff4a02-1b62-4b7c-91da-110fa868a8dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918702068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3918702068
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.4173508098
Short name T663
Test name
Test status
Simulation time 9368008996 ps
CPU time 37.42 seconds
Started Jul 11 06:20:42 PM PDT 24
Finished Jul 11 06:21:22 PM PDT 24
Peak memory 218432 kb
Host smart-abbc9dfc-11c6-4034-9654-4465cd38f6f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173508098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.4173508098
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.800891529
Short name T4
Test name
Test status
Simulation time 6546162454 ps
CPU time 16.8 seconds
Started Jul 11 06:20:43 PM PDT 24
Finished Jul 11 06:21:02 PM PDT 24
Peak memory 217324 kb
Host smart-6c352923-50a5-485e-b230-e7d6a7522fd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800891529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.800891529
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2484761913
Short name T800
Test name
Test status
Simulation time 453005964 ps
CPU time 4.13 seconds
Started Jul 11 06:20:44 PM PDT 24
Finished Jul 11 06:20:51 PM PDT 24
Peak memory 217732 kb
Host smart-a8293182-f917-4f2f-a45b-b048eb0ee441
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484761913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2484761913
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1926322861
Short name T206
Test name
Test status
Simulation time 13602192116 ps
CPU time 39.56 seconds
Started Jul 11 06:20:42 PM PDT 24
Finished Jul 11 06:21:25 PM PDT 24
Peak memory 217176 kb
Host smart-666b6f69-497e-4138-a8f8-daeb07701d10
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926322861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1926322861
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3442884751
Short name T68
Test name
Test status
Simulation time 474999763 ps
CPU time 12.1 seconds
Started Jul 11 06:20:54 PM PDT 24
Finished Jul 11 06:21:09 PM PDT 24
Peak memory 216992 kb
Host smart-48682e80-79e3-4a82-b88b-10e63b7f1edb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442884751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3442884751
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3212708355
Short name T676
Test name
Test status
Simulation time 1813911084 ps
CPU time 32.88 seconds
Started Jul 11 06:20:39 PM PDT 24
Finished Jul 11 06:21:13 PM PDT 24
Peak memory 250492 kb
Host smart-96384ed9-8327-4ab5-9dc4-89560ade4d28
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212708355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3212708355
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.4228526407
Short name T284
Test name
Test status
Simulation time 6577215960 ps
CPU time 8.77 seconds
Started Jul 11 06:20:42 PM PDT 24
Finished Jul 11 06:20:53 PM PDT 24
Peak memory 224264 kb
Host smart-aaf66850-4aff-49c6-bdd9-6d5c50714192
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228526407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.4228526407
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.708614617
Short name T858
Test name
Test status
Simulation time 36096580 ps
CPU time 1.59 seconds
Started Jul 11 06:20:41 PM PDT 24
Finished Jul 11 06:20:45 PM PDT 24
Peak memory 217792 kb
Host smart-9336eb85-b014-4ccd-b2cc-3b7bc41e12e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708614617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.708614617
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2110398305
Short name T74
Test name
Test status
Simulation time 397271383 ps
CPU time 9.65 seconds
Started Jul 11 06:20:44 PM PDT 24
Finished Jul 11 06:20:56 PM PDT 24
Peak memory 213680 kb
Host smart-90e46cfc-0ce0-4576-8d95-00e1b4b80701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110398305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2110398305
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.971570017
Short name T630
Test name
Test status
Simulation time 429006584 ps
CPU time 14.18 seconds
Started Jul 11 06:20:51 PM PDT 24
Finished Jul 11 06:21:08 PM PDT 24
Peak memory 225696 kb
Host smart-5a443cd4-270b-48f8-a978-49385ae9efcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971570017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.971570017
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1172221812
Short name T527
Test name
Test status
Simulation time 1009943711 ps
CPU time 8.7 seconds
Started Jul 11 06:20:47 PM PDT 24
Finished Jul 11 06:20:59 PM PDT 24
Peak memory 225484 kb
Host smart-c3c4eb9f-01c7-4736-ad94-9fbb2852165e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172221812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1172221812
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.4064848349
Short name T734
Test name
Test status
Simulation time 308381606 ps
CPU time 7.12 seconds
Started Jul 11 06:20:51 PM PDT 24
Finished Jul 11 06:21:01 PM PDT 24
Peak memory 217716 kb
Host smart-f934247e-f87a-4034-818e-2bb4f1eb49f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064848349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.4
064848349
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.821843665
Short name T510
Test name
Test status
Simulation time 947829080 ps
CPU time 10.43 seconds
Started Jul 11 06:20:40 PM PDT 24
Finished Jul 11 06:20:52 PM PDT 24
Peak memory 225720 kb
Host smart-a1712c9e-f7b3-4f0a-b959-62fc59cc3e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821843665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.821843665
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3978868355
Short name T65
Test name
Test status
Simulation time 142418530 ps
CPU time 2.37 seconds
Started Jul 11 06:20:42 PM PDT 24
Finished Jul 11 06:20:47 PM PDT 24
Peak memory 217212 kb
Host smart-70c4fa2c-612b-4357-8c6b-a4151201353a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978868355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3978868355
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.1677944466
Short name T377
Test name
Test status
Simulation time 170755380 ps
CPU time 20.39 seconds
Started Jul 11 06:20:44 PM PDT 24
Finished Jul 11 06:21:07 PM PDT 24
Peak memory 250560 kb
Host smart-4916b3ec-393d-491c-8c7b-9ce090f741a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677944466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1677944466
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3749308124
Short name T602
Test name
Test status
Simulation time 56341383 ps
CPU time 8.96 seconds
Started Jul 11 06:20:42 PM PDT 24
Finished Jul 11 06:20:53 PM PDT 24
Peak memory 250408 kb
Host smart-fa24e3a1-d461-415e-b5e2-7e3b76b63d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749308124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3749308124
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3766402509
Short name T155
Test name
Test status
Simulation time 3966756293 ps
CPU time 68.38 seconds
Started Jul 11 06:20:46 PM PDT 24
Finished Jul 11 06:21:56 PM PDT 24
Peak memory 250436 kb
Host smart-30edf6d3-04e4-4c24-a8cd-5749582ecbfa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766402509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3766402509
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.418725793
Short name T88
Test name
Test status
Simulation time 66723982075 ps
CPU time 851.37 seconds
Started Jul 11 06:20:49 PM PDT 24
Finished Jul 11 06:35:03 PM PDT 24
Peak memory 496484 kb
Host smart-8418ef5b-a31d-4fa7-8faa-d728f3a78581
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=418725793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.418725793
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3561786393
Short name T287
Test name
Test status
Simulation time 11936453 ps
CPU time 0.77 seconds
Started Jul 11 06:20:55 PM PDT 24
Finished Jul 11 06:20:59 PM PDT 24
Peak memory 208228 kb
Host smart-147f1f28-266e-4811-a315-811f1e4f5066
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561786393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3561786393
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2867261713
Short name T359
Test name
Test status
Simulation time 22141539 ps
CPU time 0.92 seconds
Started Jul 11 06:20:50 PM PDT 24
Finished Jul 11 06:20:54 PM PDT 24
Peak memory 208104 kb
Host smart-abebba3d-7729-4d1c-bde6-6ff4941caf2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867261713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2867261713
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.4174392503
Short name T431
Test name
Test status
Simulation time 42917750 ps
CPU time 0.93 seconds
Started Jul 11 06:20:46 PM PDT 24
Finished Jul 11 06:20:49 PM PDT 24
Peak memory 208684 kb
Host smart-a5f8e900-643b-4cd3-8985-846a3f59c331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174392503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.4174392503
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1637890560
Short name T499
Test name
Test status
Simulation time 361618969 ps
CPU time 17.13 seconds
Started Jul 11 06:20:47 PM PDT 24
Finished Jul 11 06:21:08 PM PDT 24
Peak memory 217804 kb
Host smart-912d1bfe-f04d-42da-ba47-e9e98a1b5d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637890560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1637890560
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.2149096946
Short name T470
Test name
Test status
Simulation time 12720104966 ps
CPU time 9.68 seconds
Started Jul 11 06:20:47 PM PDT 24
Finished Jul 11 06:21:00 PM PDT 24
Peak memory 217284 kb
Host smart-af44ca4c-f622-440a-ac3c-e056c97f04b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149096946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2149096946
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.524708191
Short name T838
Test name
Test status
Simulation time 7571933874 ps
CPU time 32.57 seconds
Started Jul 11 06:20:51 PM PDT 24
Finished Jul 11 06:21:27 PM PDT 24
Peak memory 218432 kb
Host smart-2add5986-ecd0-47f7-a1ae-bac59b35eb5b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524708191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.524708191
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1305730632
Short name T443
Test name
Test status
Simulation time 534323924 ps
CPU time 6.82 seconds
Started Jul 11 06:20:51 PM PDT 24
Finished Jul 11 06:21:01 PM PDT 24
Peak memory 217204 kb
Host smart-dab18c4a-7bdb-4de3-853f-d73c74ff4407
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305730632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
305730632
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3325029677
Short name T419
Test name
Test status
Simulation time 100626602 ps
CPU time 2.67 seconds
Started Jul 11 06:20:46 PM PDT 24
Finished Jul 11 06:20:52 PM PDT 24
Peak memory 217732 kb
Host smart-be5c2de0-09fa-460a-bf4f-95ccde7cc2c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325029677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.3325029677
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.4161472068
Short name T266
Test name
Test status
Simulation time 3157900003 ps
CPU time 33.39 seconds
Started Jul 11 06:20:45 PM PDT 24
Finished Jul 11 06:21:21 PM PDT 24
Peak memory 217196 kb
Host smart-7b83386c-c27b-455a-9cd6-d84718648630
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161472068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.4161472068
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2480245778
Short name T317
Test name
Test status
Simulation time 366732929 ps
CPU time 2.68 seconds
Started Jul 11 06:20:47 PM PDT 24
Finished Jul 11 06:20:52 PM PDT 24
Peak memory 217064 kb
Host smart-a6b57d50-865f-4ed9-8665-eff7ab4f391b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480245778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2480245778
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.4258375184
Short name T857
Test name
Test status
Simulation time 12155711161 ps
CPU time 48.53 seconds
Started Jul 11 06:20:47 PM PDT 24
Finished Jul 11 06:21:39 PM PDT 24
Peak memory 266920 kb
Host smart-2dc2a064-38b8-43bc-96b9-6465498430a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258375184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.4258375184
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1626205100
Short name T669
Test name
Test status
Simulation time 382744756 ps
CPU time 17.15 seconds
Started Jul 11 06:20:48 PM PDT 24
Finished Jul 11 06:21:08 PM PDT 24
Peak memory 250632 kb
Host smart-4ceda7f4-1fcd-4859-ac9e-98b7a2557905
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626205100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1626205100
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2546142089
Short name T154
Test name
Test status
Simulation time 46879755 ps
CPU time 2.45 seconds
Started Jul 11 06:20:53 PM PDT 24
Finished Jul 11 06:20:59 PM PDT 24
Peak memory 217776 kb
Host smart-c3dc65e0-00b6-4225-b8a8-305b15108134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546142089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2546142089
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1711671932
Short name T725
Test name
Test status
Simulation time 612338115 ps
CPU time 10.02 seconds
Started Jul 11 06:20:50 PM PDT 24
Finished Jul 11 06:21:03 PM PDT 24
Peak memory 213836 kb
Host smart-b14485bd-9bd3-4f8b-a17d-e71d195446c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711671932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1711671932
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1144123798
Short name T847
Test name
Test status
Simulation time 677121190 ps
CPU time 7.89 seconds
Started Jul 11 06:20:47 PM PDT 24
Finished Jul 11 06:20:58 PM PDT 24
Peak memory 225588 kb
Host smart-82d9e509-5a33-476f-8cea-8ecb01e15536
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144123798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1144123798
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2340517280
Short name T152
Test name
Test status
Simulation time 246418830 ps
CPU time 7.51 seconds
Started Jul 11 06:20:49 PM PDT 24
Finished Jul 11 06:21:00 PM PDT 24
Peak memory 217752 kb
Host smart-558bf005-bf51-4392-add2-7aaec1df3bcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340517280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
340517280
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3508124788
Short name T227
Test name
Test status
Simulation time 2545749465 ps
CPU time 12.64 seconds
Started Jul 11 06:20:48 PM PDT 24
Finished Jul 11 06:21:04 PM PDT 24
Peak memory 224944 kb
Host smart-ec8ddc9b-0dd2-4465-a92e-dff06512878e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508124788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3508124788
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2202196347
Short name T71
Test name
Test status
Simulation time 233009613 ps
CPU time 2.08 seconds
Started Jul 11 06:20:47 PM PDT 24
Finished Jul 11 06:20:53 PM PDT 24
Peak memory 217208 kb
Host smart-0386d93a-19dd-48ff-ad01-82e76a823cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202196347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2202196347
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2156753289
Short name T200
Test name
Test status
Simulation time 958917740 ps
CPU time 22.31 seconds
Started Jul 11 06:20:52 PM PDT 24
Finished Jul 11 06:21:18 PM PDT 24
Peak memory 250604 kb
Host smart-0b167a6e-df62-4503-ab71-885a0f4af5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156753289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2156753289
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.341027299
Short name T271
Test name
Test status
Simulation time 331223375 ps
CPU time 6.95 seconds
Started Jul 11 06:20:46 PM PDT 24
Finished Jul 11 06:20:56 PM PDT 24
Peak memory 250124 kb
Host smart-c7190cd2-e045-4c03-8961-2575cffb3cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341027299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.341027299
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3275394533
Short name T759
Test name
Test status
Simulation time 2755521609 ps
CPU time 64.64 seconds
Started Jul 11 06:20:48 PM PDT 24
Finished Jul 11 06:21:56 PM PDT 24
Peak memory 267212 kb
Host smart-172fe10b-2594-43b2-9efd-450cefe21ede
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275394533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3275394533
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2131528701
Short name T240
Test name
Test status
Simulation time 20272791 ps
CPU time 1.39 seconds
Started Jul 11 06:20:46 PM PDT 24
Finished Jul 11 06:20:49 PM PDT 24
Peak memory 217180 kb
Host smart-ab8075de-0b50-4f32-b911-d9e852d8576c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131528701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2131528701
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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