Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51239 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T3 |
99 |
auto[1] |
1964 |
1 |
|
|
T4 |
43 |
|
T5 |
36 |
|
T14 |
74 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52565 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T3 |
99 |
auto[1] |
638 |
1 |
|
|
T56 |
11 |
|
T30 |
17 |
|
T57 |
25 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51375 |
1 |
|
|
T1 |
60 |
|
T2 |
47 |
|
T3 |
85 |
auto[1] |
1828 |
1 |
|
|
T2 |
5 |
|
T3 |
14 |
|
T4 |
31 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51287 |
1 |
|
|
T1 |
60 |
|
T2 |
45 |
|
T3 |
85 |
auto[1] |
1916 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T4 |
26 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51352 |
1 |
|
|
T1 |
60 |
|
T2 |
46 |
|
T3 |
95 |
auto[1] |
1851 |
1 |
|
|
T2 |
6 |
|
T3 |
4 |
|
T4 |
30 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
48313 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T3 |
99 |
no_err_inj |
4890 |
1 |
|
|
T4 |
39 |
|
T5 |
48 |
|
T11 |
5 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51312 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T3 |
99 |
auto[1] |
1891 |
1 |
|
|
T4 |
52 |
|
T5 |
25 |
|
T14 |
66 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52659 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T3 |
99 |
auto[1] |
544 |
1 |
|
|
T56 |
10 |
|
T30 |
13 |
|
T57 |
14 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37721 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T9 |
86 |
auto[1] |
15482 |
1 |
|
|
T3 |
99 |
|
T4 |
211 |
|
T5 |
90 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51316 |
1 |
|
|
T1 |
60 |
|
T2 |
49 |
|
T3 |
88 |
auto[1] |
1887 |
1 |
|
|
T2 |
3 |
|
T3 |
11 |
|
T4 |
19 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51397 |
1 |
|
|
T1 |
60 |
|
T2 |
47 |
|
T3 |
86 |
auto[1] |
1806 |
1 |
|
|
T2 |
5 |
|
T3 |
13 |
|
T4 |
21 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51361 |
1 |
|
|
T1 |
60 |
|
T2 |
43 |
|
T3 |
88 |
auto[1] |
1842 |
1 |
|
|
T2 |
9 |
|
T3 |
11 |
|
T4 |
23 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51328 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T3 |
99 |
auto[1] |
1875 |
1 |
|
|
T4 |
43 |
|
T5 |
32 |
|
T14 |
62 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50869 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T3 |
99 |
auto[1] |
2334 |
1 |
|
|
T4 |
60 |
|
T12 |
1 |
|
T14 |
40 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52632 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T3 |
99 |
auto[1] |
571 |
1 |
|
|
T56 |
13 |
|
T30 |
20 |
|
T57 |
13 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52614 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T3 |
99 |
auto[1] |
589 |
1 |
|
|
T56 |
17 |
|
T30 |
12 |
|
T57 |
16 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52621 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T3 |
99 |
auto[1] |
582 |
1 |
|
|
T56 |
17 |
|
T30 |
18 |
|
T57 |
25 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50412 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T3 |
99 |
auto[1] |
2791 |
1 |
|
|
T4 |
12 |
|
T5 |
12 |
|
T11 |
10 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49516 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T3 |
99 |
auto[1] |
3687 |
1 |
|
|
T13 |
69 |
|
T51 |
54 |
|
T50 |
55 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51383 |
1 |
|
|
T1 |
60 |
|
T2 |
47 |
|
T3 |
90 |
auto[1] |
1820 |
1 |
|
|
T2 |
5 |
|
T3 |
9 |
|
T4 |
17 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51309 |
1 |
|
|
T1 |
60 |
|
T2 |
48 |
|
T3 |
88 |
auto[1] |
1894 |
1 |
|
|
T2 |
4 |
|
T3 |
11 |
|
T4 |
16 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51403 |
1 |
|
|
T1 |
60 |
|
T2 |
44 |
|
T3 |
87 |
auto[1] |
1800 |
1 |
|
|
T2 |
8 |
|
T3 |
12 |
|
T4 |
31 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51269 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T3 |
99 |
auto[1] |
1934 |
1 |
|
|
T4 |
43 |
|
T5 |
37 |
|
T14 |
69 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47495 |
1 |
|
|
T2 |
52 |
|
T3 |
99 |
|
T4 |
605 |
auto[1] |
5708 |
1 |
|
|
T1 |
60 |
|
T9 |
86 |
|
T4 |
47 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49537 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T3 |
99 |
auto[1] |
3666 |
1 |
|
|
T20 |
72 |
|
T47 |
73 |
|
T55 |
52 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53203 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T3 |
99 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51285 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T3 |
99 |
auto[1] |
1918 |
1 |
|
|
T4 |
43 |
|
T5 |
39 |
|
T14 |
63 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51301 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T3 |
99 |
auto[1] |
1902 |
1 |
|
|
T4 |
36 |
|
T5 |
27 |
|
T14 |
75 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51337 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T3 |
99 |
auto[1] |
1866 |
1 |
|
|
T4 |
32 |
|
T5 |
26 |
|
T14 |
77 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
46906 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T3 |
99 |
auto[0] |
no_err_inj |
3506 |
1 |
|
|
T4 |
34 |
|
T5 |
41 |
|
T14 |
75 |
auto[1] |
err_inj |
1407 |
1 |
|
|
T4 |
7 |
|
T5 |
5 |
|
T11 |
5 |
auto[1] |
no_err_inj |
1384 |
1 |
|
|
T4 |
5 |
|
T5 |
7 |
|
T11 |
5 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48678 |
1 |
|
|
T1 |
60 |
|
T2 |
48 |
|
T3 |
88 |
auto[0] |
auto[1] |
1734 |
1 |
|
|
T2 |
4 |
|
T3 |
11 |
|
T4 |
16 |
auto[1] |
auto[0] |
2631 |
1 |
|
|
T4 |
12 |
|
T5 |
12 |
|
T11 |
10 |
auto[1] |
auto[1] |
160 |
1 |
|
|
T14 |
3 |
|
T15 |
2 |
|
T17 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48767 |
1 |
|
|
T1 |
60 |
|
T2 |
47 |
|
T3 |
86 |
auto[0] |
auto[1] |
1645 |
1 |
|
|
T2 |
5 |
|
T3 |
13 |
|
T4 |
21 |
auto[1] |
auto[0] |
2630 |
1 |
|
|
T4 |
12 |
|
T5 |
12 |
|
T11 |
10 |
auto[1] |
auto[1] |
161 |
1 |
|
|
T14 |
3 |
|
T16 |
2 |
|
T17 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48745 |
1 |
|
|
T1 |
60 |
|
T2 |
44 |
|
T3 |
87 |
auto[0] |
auto[1] |
1667 |
1 |
|
|
T2 |
8 |
|
T3 |
12 |
|
T4 |
31 |
auto[1] |
auto[0] |
2658 |
1 |
|
|
T4 |
12 |
|
T5 |
12 |
|
T11 |
9 |
auto[1] |
auto[1] |
133 |
1 |
|
|
T11 |
1 |
|
T14 |
3 |
|
T15 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48656 |
1 |
|
|
T1 |
60 |
|
T2 |
45 |
|
T3 |
85 |
auto[0] |
auto[1] |
1756 |
1 |
|
|
T2 |
7 |
|
T3 |
14 |
|
T4 |
25 |
auto[1] |
auto[0] |
2631 |
1 |
|
|
T4 |
11 |
|
T5 |
11 |
|
T11 |
10 |
auto[1] |
auto[1] |
160 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T14 |
9 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48723 |
1 |
|
|
T1 |
60 |
|
T2 |
46 |
|
T3 |
95 |
auto[0] |
auto[1] |
1689 |
1 |
|
|
T2 |
6 |
|
T3 |
4 |
|
T4 |
28 |
auto[1] |
auto[0] |
2629 |
1 |
|
|
T4 |
10 |
|
T5 |
12 |
|
T11 |
10 |
auto[1] |
auto[1] |
162 |
1 |
|
|
T4 |
2 |
|
T14 |
1 |
|
T19 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48741 |
1 |
|
|
T1 |
60 |
|
T2 |
47 |
|
T3 |
85 |
auto[0] |
auto[1] |
1671 |
1 |
|
|
T2 |
5 |
|
T3 |
14 |
|
T4 |
30 |
auto[1] |
auto[0] |
2634 |
1 |
|
|
T4 |
11 |
|
T5 |
10 |
|
T11 |
8 |
auto[1] |
auto[1] |
157 |
1 |
|
|
T4 |
1 |
|
T5 |
2 |
|
T11 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36438 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T9 |
86 |
auto[0] |
auto[1] |
1283 |
1 |
|
|
T4 |
32 |
|
T5 |
32 |
|
T14 |
47 |
auto[1] |
auto[0] |
14801 |
1 |
|
|
T3 |
99 |
|
T4 |
200 |
|
T5 |
86 |
auto[1] |
auto[1] |
681 |
1 |
|
|
T4 |
11 |
|
T5 |
4 |
|
T14 |
27 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36538 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T9 |
86 |
auto[0] |
auto[1] |
1183 |
1 |
|
|
T4 |
40 |
|
T5 |
15 |
|
T14 |
38 |
auto[1] |
auto[0] |
14774 |
1 |
|
|
T3 |
99 |
|
T4 |
199 |
|
T5 |
80 |
auto[1] |
auto[1] |
708 |
1 |
|
|
T4 |
12 |
|
T5 |
10 |
|
T14 |
28 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36382 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T9 |
86 |
auto[0] |
auto[1] |
1339 |
1 |
|
|
T4 |
48 |
|
T12 |
1 |
|
T14 |
21 |
auto[1] |
auto[0] |
14487 |
1 |
|
|
T3 |
99 |
|
T4 |
199 |
|
T5 |
90 |
auto[1] |
auto[1] |
995 |
1 |
|
|
T4 |
12 |
|
T14 |
19 |
|
T17 |
20 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36467 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T9 |
86 |
auto[0] |
auto[1] |
1254 |
1 |
|
|
T4 |
33 |
|
T5 |
24 |
|
T14 |
52 |
auto[1] |
auto[0] |
14861 |
1 |
|
|
T3 |
99 |
|
T4 |
201 |
|
T5 |
82 |
auto[1] |
auto[1] |
621 |
1 |
|
|
T4 |
10 |
|
T5 |
8 |
|
T14 |
10 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32700 |
1 |
|
|
T2 |
52 |
|
T4 |
400 |
|
T10 |
83 |
auto[0] |
auto[1] |
5021 |
1 |
|
|
T1 |
60 |
|
T9 |
86 |
|
T4 |
41 |
auto[1] |
auto[0] |
14795 |
1 |
|
|
T3 |
99 |
|
T4 |
205 |
|
T5 |
83 |
auto[1] |
auto[1] |
687 |
1 |
|
|
T4 |
6 |
|
T5 |
7 |
|
T14 |
25 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36642 |
1 |
|
|
T1 |
60 |
|
T2 |
48 |
|
T9 |
86 |
auto[0] |
auto[1] |
1079 |
1 |
|
|
T2 |
4 |
|
T4 |
5 |
|
T10 |
16 |
auto[1] |
auto[0] |
14667 |
1 |
|
|
T3 |
88 |
|
T4 |
200 |
|
T5 |
90 |
auto[1] |
auto[1] |
815 |
1 |
|
|
T3 |
11 |
|
T4 |
11 |
|
T14 |
40 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36688 |
1 |
|
|
T1 |
60 |
|
T2 |
47 |
|
T9 |
86 |
auto[0] |
auto[1] |
1033 |
1 |
|
|
T2 |
5 |
|
T4 |
9 |
|
T10 |
8 |
auto[1] |
auto[0] |
14695 |
1 |
|
|
T3 |
90 |
|
T4 |
203 |
|
T5 |
90 |
auto[1] |
auto[1] |
787 |
1 |
|
|
T3 |
9 |
|
T4 |
8 |
|
T14 |
43 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36669 |
1 |
|
|
T1 |
60 |
|
T2 |
47 |
|
T9 |
86 |
auto[0] |
auto[1] |
1052 |
1 |
|
|
T2 |
5 |
|
T4 |
9 |
|
T10 |
4 |
auto[1] |
auto[0] |
14728 |
1 |
|
|
T3 |
86 |
|
T4 |
199 |
|
T5 |
90 |
auto[1] |
auto[1] |
754 |
1 |
|
|
T3 |
13 |
|
T4 |
12 |
|
T14 |
35 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36615 |
1 |
|
|
T1 |
60 |
|
T2 |
49 |
|
T9 |
86 |
auto[0] |
auto[1] |
1106 |
1 |
|
|
T2 |
3 |
|
T4 |
9 |
|
T10 |
8 |
auto[1] |
auto[0] |
14701 |
1 |
|
|
T3 |
88 |
|
T4 |
201 |
|
T5 |
88 |
auto[1] |
auto[1] |
781 |
1 |
|
|
T3 |
11 |
|
T4 |
10 |
|
T5 |
2 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36635 |
1 |
|
|
T1 |
60 |
|
T2 |
45 |
|
T9 |
86 |
auto[0] |
auto[1] |
1086 |
1 |
|
|
T2 |
7 |
|
T4 |
14 |
|
T10 |
11 |
auto[1] |
auto[0] |
14652 |
1 |
|
|
T3 |
85 |
|
T4 |
199 |
|
T5 |
89 |
auto[1] |
auto[1] |
830 |
1 |
|
|
T3 |
14 |
|
T4 |
12 |
|
T5 |
1 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36669 |
1 |
|
|
T1 |
60 |
|
T2 |
47 |
|
T9 |
86 |
auto[0] |
auto[1] |
1052 |
1 |
|
|
T2 |
5 |
|
T4 |
13 |
|
T10 |
13 |
auto[1] |
auto[0] |
14706 |
1 |
|
|
T3 |
85 |
|
T4 |
193 |
|
T5 |
88 |
auto[1] |
auto[1] |
776 |
1 |
|
|
T3 |
14 |
|
T4 |
18 |
|
T5 |
2 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36526 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T9 |
86 |
auto[0] |
auto[1] |
1195 |
1 |
|
|
T4 |
28 |
|
T5 |
21 |
|
T14 |
48 |
auto[1] |
auto[0] |
14811 |
1 |
|
|
T3 |
99 |
|
T4 |
207 |
|
T5 |
85 |
auto[1] |
auto[1] |
671 |
1 |
|
|
T4 |
4 |
|
T5 |
5 |
|
T14 |
29 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36475 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T9 |
86 |
auto[0] |
auto[1] |
1246 |
1 |
|
|
T4 |
31 |
|
T5 |
20 |
|
T14 |
46 |
auto[1] |
auto[0] |
14826 |
1 |
|
|
T3 |
99 |
|
T4 |
206 |
|
T5 |
83 |
auto[1] |
auto[1] |
656 |
1 |
|
|
T4 |
5 |
|
T5 |
7 |
|
T14 |
29 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36155 |
1 |
|
|
T1 |
60 |
|
T2 |
52 |
|
T9 |
86 |
auto[0] |
auto[1] |
1566 |
1 |
|
|
T4 |
12 |
|
T11 |
10 |
|
T14 |
15 |
auto[1] |
auto[0] |
14257 |
1 |
|
|
T3 |
99 |
|
T4 |
211 |
|
T5 |
78 |
auto[1] |
auto[1] |
1225 |
1 |
|
|
T5 |
12 |
|
T14 |
48 |
|
T15 |
12 |