Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107128110

1

T1

36692

T2

14589

T3

153790

auto[1]

1386808

1

T2

1881

T3

4018

T4

13095

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107136501

1

T1

36692

T2

14886

T3

154378

auto[1]

1378417

1

T2

1584

T3

3430

T4

13017

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7442026	1			T1	5251		T2	5276		T3	24329
auto[IdleSt]	21468222	1			T1	2043		T2	1326		T3	5470
auto[ClkMuxSt]	35627	1			T1	60		T9	86		T4	439
auto[CntIncrSt]	35266	1			T1	60		T9	86		T4	439
auto[CntProgSt]	1783008	1			T1	14385		T9	1503		T4	11076
auto[TransCheckSt]	27380	1			T1	60		T9	86		T4	300
auto[TokenHashSt]	46197544	1			T1	5741		T9	67359		T4	143563
auto[FlashRmaSt]	33124	1			T4	292		T5	185		T11	5
auto[TokenCheck0St]	12313	1			T4	133		T5	103		T11	5
auto[TokenCheck1St]	9213	1			T4	84		T5	82		T11	5
auto[TransProgSt]	418705	1			T4	2446		T5	1170		T11	70
auto[PostTransSt]	12576813	1			T1	9092		T9	13046		T4	111549
auto[ScrapSt]	188297	1			T4	280		T5	81		T13	3
auto[EscalateSt]	6791871	1			T2	4861		T3	30404		T4	62951
auto[InvalidSt]	11493620	1			T2	5002		T3	97592		T4	111535

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1889	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11493620	1			T2	5002		T3	97592		T4	111535
EscalateSt	6791871	1			T2	4861		T3	30404		T4	62951
ScrapSt	188297	1			T4	280		T5	81		T13	3
PostTransSt	12576813	1			T1	9092		T9	13046		T4	111549
TransProgSt	418705	1			T4	2446		T5	1170		T11	70
TokenCheck1St	9213	1			T4	84		T5	82		T11	5
TokenCheck0St	12313	1			T4	133		T5	103		T11	5
FlashRmaSt	33124	1			T4	292		T5	185		T11	5
TokenHashSt	46197544	1			T1	5741		T9	67359		T4	143563
TransCheckSt	27380	1			T1	60		T9	86		T4	300
CntProgSt	1783008	1			T1	14385		T9	1503		T4	11076
CntIncrSt	35266	1			T1	60		T9	86		T4	439
ClkMuxSt	35627	1			T1	60		T9	86		T4	439
IdleSt	21468222	1			T1	2043		T2	1326		T3	5470
ResetSt	7442026	1			T1	5251		T2	5276		T3	24329
arcs[ResetSt=>IdleSt]	53552	1			T1	61		T2	44		T3	89
arcs[IdleSt=>ScrapSt]	287	1			T4	1		T5	2		T13	1
arcs[IdleSt=>ClkMuxSt]	35332	1			T1	60		T9	86		T4	439
arcs[ClkMuxSt=>CntIncrSt]	35266	1			T1	60		T9	86		T4	439
arcs[CntIncrSt=>PostTransSt]	1902	1			T4	36		T5	27		T14	75
arcs[CntIncrSt=>CntProgSt]	33298	1			T1	60		T9	86		T4	403
arcs[CntProgSt=>PostTransSt]	4917	1			T4	103		T5	36		T12	1
arcs[CntProgSt=>TransCheckSt]	27380	1			T1	60		T9	86		T4	300
arcs[TransCheckSt=>PostTransSt]	3736	1			T4	33		T5	26		T14	77
arcs[TransCheckSt=>TokenHashSt]	23511	1			T1	60		T9	86		T4	267
arcs[TokenHashSt=>PostTransSt]	10430	1			T1	60		T9	86		T4	134
arcs[TokenHashSt=>FlashRmaSt]	12402	1			T4	133		T5	103		T11	5
arcs[FlashRmaSt=>TokenCheck0St]	12313	1			T4	133		T5	103		T11	5
arcs[TokenCheck0St=>PostTransSt]	3082	1			T4	49		T5	21		T14	63
arcs[TokenCheck0St=>TokenCheck1St]	9213	1			T4	84		T5	82		T11	5
arcs[TokenCheck1St=>PostTransSt]	656	1			T4	2		T5	4		T14	4
arcs[TransProgSt=>PostTransSt]	7699	1			T4	82		T5	78		T11	5
arcs[IdleSt=>EscalateSt]	200	1			T13	4		T51	6		T50	3
arcs[ClkMuxSt=>EscalateSt]	66	1			T13	2		T48	1		T49	1
arcs[CntIncrSt=>EscalateSt]	66	1			T13	1		T50	1		T49	1
arcs[CntProgSt=>EscalateSt]	1001	1			T13	9		T51	17		T50	21
arcs[TransCheckSt=>EscalateSt]	133	1			T13	5		T51	3		T50	1
arcs[TokenHashSt=>EscalateSt]	679	1			T13	21		T51	4		T50	7
arcs[FlashRmaSt=>EscalateSt]	89	1			T13	1		T51	2		T50	1
arcs[TokenCheck0St=>EscalateSt]	18	1			T50	1		T48	1		T53	2
arcs[TokenCheck1St=>EscalateSt]	119	1			T13	2		T51	2		T50	1
arcs[TransProgSt=>EscalateSt]	739	1			T13	12		T51	12		T50	15
arcs[PostTransSt=>EscalateSt]	5186	1			T4	103		T5	36		T12	1
arcs[InvalidSt=>EscalateSt]	13606	1			T2	35		T3	76		T4	162

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7441860	1			T1	5251		T2	5276		T3	24329
auto[0]	auto[IdleSt]	21468079	1			T1	2043		T2	1326		T3	5470
auto[0]	auto[ClkMuxSt]	35585	1			T1	60		T9	86		T4	439
auto[0]	auto[CntIncrSt]	35230	1			T1	60		T9	86		T4	439
auto[0]	auto[CntProgSt]	1782331	1			T1	14385		T9	1503		T4	11076
auto[0]	auto[TransCheckSt]	27284	1			T1	60		T9	86		T4	300
auto[0]	auto[TokenHashSt]	46197075	1			T1	5741		T9	67359		T4	143563
auto[0]	auto[FlashRmaSt]	33064	1			T4	292		T5	185		T11	5
auto[0]	auto[TokenCheck0St]	12300	1			T4	133		T5	103		T11	5
auto[0]	auto[TokenCheck1St]	9132	1			T4	84		T5	82		T11	5
auto[0]	auto[TransProgSt]	418240	1			T4	2446		T5	1170		T11	70
auto[0]	auto[PostTransSt]	12574139	1			T1	9092		T9	13046		T4	111496
auto[0]	auto[ScrapSt]	188249	1			T4	280		T5	81		T13	2
auto[0]	auto[EscalateSt]	5416876	1			T2	2999		T3	26427		T4	49989
auto[0]	auto[InvalidSt]	11486777	1			T2	4983		T3	97551		T4	111455
auto[1]	auto[ResetSt]	166	1			T13	4		T51	1		T50	2
auto[1]	auto[IdleSt]	143	1			T13	2		T51	4		T50	3
auto[1]	auto[ClkMuxSt]	42	1			T13	1		T49	1		T201	2
auto[1]	auto[CntIncrSt]	36	1			T50	1		T49	1		T202	1
auto[1]	auto[CntProgSt]	677	1			T13	5		T51	11		T50	13
auto[1]	auto[TransCheckSt]	96	1			T13	3		T51	2		T49	3
auto[1]	auto[TokenHashSt]	469	1			T13	14		T51	1		T50	4
auto[1]	auto[FlashRmaSt]	60	1			T13	1		T51	1		T50	1
auto[1]	auto[TokenCheck0St]	13	1			T48	1		T53	2		T203	1
auto[1]	auto[TokenCheck1St]	81	1			T13	1		T51	2		T50	1
auto[1]	auto[TransProgSt]	465	1			T13	7		T51	8		T50	8
auto[1]	auto[PostTransSt]	2674	1			T4	53		T5	28		T12	1
auto[1]	auto[ScrapSt]	48	1			T13	1		T51	1		T53	1
auto[1]	auto[EscalateSt]	1374995	1			T2	1862		T3	3977		T4	12962
auto[1]	auto[InvalidSt]	6843	1			T2	19		T3	41		T4	80

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7441831	1			T1	5251		T2	5276		T3	24329
auto[0]	auto[IdleSt]	21468094	1			T1	2043		T2	1326		T3	5470
auto[0]	auto[ClkMuxSt]	35583	1			T1	60		T9	86		T4	439
auto[0]	auto[CntIncrSt]	35218	1			T1	60		T9	86		T4	439
auto[0]	auto[CntProgSt]	1782330	1			T1	14385		T9	1503		T4	11076
auto[0]	auto[TransCheckSt]	27291	1			T1	60		T9	86		T4	300
auto[0]	auto[TokenHashSt]	46197108	1			T1	5741		T9	67359		T4	143563
auto[0]	auto[FlashRmaSt]	33062	1			T4	292		T5	185		T11	5
auto[0]	auto[TokenCheck0St]	12301	1			T4	133		T5	103		T11	5
auto[0]	auto[TokenCheck1St]	9140	1			T4	84		T5	82		T11	5
auto[0]	auto[TransProgSt]	418194	1			T4	2446		T5	1170		T11	70
auto[0]	auto[PostTransSt]	12574222	1			T1	9092		T9	13046		T4	111499
auto[0]	auto[ScrapSt]	188260	1			T4	280		T5	81		T13	3
auto[0]	auto[EscalateSt]	5425121	1			T2	3293		T3	27009		T4	50066
auto[0]	auto[InvalidSt]	11486857	1			T2	4986		T3	97557		T4	111453
auto[1]	auto[ResetSt]	195	1			T13	4		T51	4		T50	3
auto[1]	auto[IdleSt]	128	1			T13	3		T51	6		T50	2
auto[1]	auto[ClkMuxSt]	44	1			T13	2		T48	1		T49	1
auto[1]	auto[CntIncrSt]	48	1			T13	1		T50	1		T53	3
auto[1]	auto[CntProgSt]	678	1			T13	6		T51	11		T50	15
auto[1]	auto[TransCheckSt]	89	1			T13	3		T51	1		T50	1
auto[1]	auto[TokenHashSt]	436	1			T13	13		T51	4		T50	6
auto[1]	auto[FlashRmaSt]	62	1			T13	1		T51	2		T50	1
auto[1]	auto[TokenCheck0St]	12	1			T50	1		T48	1		T53	1
auto[1]	auto[TokenCheck1St]	73	1			T13	1		T51	1		T53	1
auto[1]	auto[TransProgSt]	511	1			T13	8		T51	9		T50	11
auto[1]	auto[PostTransSt]	2591	1			T4	50		T5	8		T13	4
auto[1]	auto[ScrapSt]	37	1			T48	1		T49	1		T204	1
auto[1]	auto[EscalateSt]	1366750	1			T2	1568		T3	3395		T4	12885
auto[1]	auto[InvalidSt]	6763	1			T2	16		T3	35		T4	82