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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.89 97.99 95.59 93.38 97.67 98.55 98.76 96.29


Total test records in report: 994
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T815 /workspace/coverage/default/11.lc_ctrl_stress_all.4002824285 Jul 12 04:43:22 PM PDT 24 Jul 12 04:44:58 PM PDT 24 15623340875 ps
T816 /workspace/coverage/default/28.lc_ctrl_security_escalation.2054253836 Jul 12 04:44:19 PM PDT 24 Jul 12 04:44:36 PM PDT 24 2045606314 ps
T817 /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2282003256 Jul 12 04:44:25 PM PDT 24 Jul 12 04:44:54 PM PDT 24 2928463234 ps
T818 /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.2984326195 Jul 12 04:44:32 PM PDT 24 Jul 12 04:51:00 PM PDT 24 146671975395 ps
T819 /workspace/coverage/default/13.lc_ctrl_errors.1854817647 Jul 12 04:43:26 PM PDT 24 Jul 12 04:43:39 PM PDT 24 266257082 ps
T820 /workspace/coverage/default/17.lc_ctrl_prog_failure.2000696625 Jul 12 04:43:44 PM PDT 24 Jul 12 04:43:49 PM PDT 24 348833519 ps
T821 /workspace/coverage/default/21.lc_ctrl_sec_token_digest.520485388 Jul 12 04:43:58 PM PDT 24 Jul 12 04:44:18 PM PDT 24 605141421 ps
T822 /workspace/coverage/default/38.lc_ctrl_prog_failure.3143013115 Jul 12 04:44:33 PM PDT 24 Jul 12 04:44:39 PM PDT 24 231184611 ps
T823 /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3734938674 Jul 12 04:42:58 PM PDT 24 Jul 12 04:43:10 PM PDT 24 204351254 ps
T824 /workspace/coverage/default/4.lc_ctrl_state_failure.1726749581 Jul 12 04:43:03 PM PDT 24 Jul 12 04:43:31 PM PDT 24 1106018307 ps
T825 /workspace/coverage/default/37.lc_ctrl_errors.1666048092 Jul 12 04:44:29 PM PDT 24 Jul 12 04:44:49 PM PDT 24 875978018 ps
T826 /workspace/coverage/default/9.lc_ctrl_state_post_trans.2364866419 Jul 12 04:43:14 PM PDT 24 Jul 12 04:43:20 PM PDT 24 71199691 ps
T827 /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2066653637 Jul 12 04:43:22 PM PDT 24 Jul 12 04:43:41 PM PDT 24 1530528849 ps
T828 /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2585359603 Jul 12 04:43:30 PM PDT 24 Jul 12 04:43:37 PM PDT 24 1649132582 ps
T829 /workspace/coverage/default/11.lc_ctrl_jtag_access.4171337885 Jul 12 04:43:21 PM PDT 24 Jul 12 04:43:32 PM PDT 24 1247919812 ps
T830 /workspace/coverage/default/30.lc_ctrl_errors.76255341 Jul 12 04:44:13 PM PDT 24 Jul 12 04:44:35 PM PDT 24 374330464 ps
T831 /workspace/coverage/default/42.lc_ctrl_sec_mubi.1331338295 Jul 12 04:44:47 PM PDT 24 Jul 12 04:45:10 PM PDT 24 610640922 ps
T832 /workspace/coverage/default/25.lc_ctrl_state_failure.1486092631 Jul 12 04:44:06 PM PDT 24 Jul 12 04:44:42 PM PDT 24 209085389 ps
T833 /workspace/coverage/default/23.lc_ctrl_smoke.496795908 Jul 12 04:44:01 PM PDT 24 Jul 12 04:44:11 PM PDT 24 27445677 ps
T198 /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1495979207 Jul 12 04:43:10 PM PDT 24 Jul 12 04:43:14 PM PDT 24 14121930 ps
T834 /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1421904073 Jul 12 04:44:26 PM PDT 24 Jul 12 04:44:36 PM PDT 24 239249152 ps
T835 /workspace/coverage/default/15.lc_ctrl_prog_failure.1831143406 Jul 12 04:43:36 PM PDT 24 Jul 12 04:43:40 PM PDT 24 77432878 ps
T836 /workspace/coverage/default/40.lc_ctrl_jtag_access.1373448600 Jul 12 04:44:39 PM PDT 24 Jul 12 04:44:43 PM PDT 24 1166354094 ps
T837 /workspace/coverage/default/17.lc_ctrl_smoke.2283182127 Jul 12 04:43:41 PM PDT 24 Jul 12 04:43:46 PM PDT 24 96878838 ps
T838 /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2252835917 Jul 12 04:43:19 PM PDT 24 Jul 12 04:43:22 PM PDT 24 23317854 ps
T105 /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.1117007323 Jul 12 04:42:54 PM PDT 24 Jul 12 04:57:19 PM PDT 24 23251193217 ps
T839 /workspace/coverage/default/23.lc_ctrl_security_escalation.1815702798 Jul 12 04:44:00 PM PDT 24 Jul 12 04:44:16 PM PDT 24 480204741 ps
T840 /workspace/coverage/default/16.lc_ctrl_security_escalation.2288359003 Jul 12 04:43:38 PM PDT 24 Jul 12 04:43:51 PM PDT 24 676584712 ps
T841 /workspace/coverage/default/24.lc_ctrl_state_post_trans.2366706098 Jul 12 04:44:13 PM PDT 24 Jul 12 04:44:30 PM PDT 24 327878918 ps
T842 /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1230392410 Jul 12 04:43:27 PM PDT 24 Jul 12 04:43:35 PM PDT 24 892780272 ps
T843 /workspace/coverage/default/47.lc_ctrl_smoke.1478268971 Jul 12 04:44:57 PM PDT 24 Jul 12 04:45:03 PM PDT 24 108443962 ps
T844 /workspace/coverage/default/7.lc_ctrl_jtag_priority.4214108503 Jul 12 04:43:10 PM PDT 24 Jul 12 04:43:16 PM PDT 24 829138077 ps
T845 /workspace/coverage/default/13.lc_ctrl_stress_all.192895862 Jul 12 04:43:25 PM PDT 24 Jul 12 04:48:11 PM PDT 24 8088039598 ps
T46 /workspace/coverage/default/18.lc_ctrl_jtag_errors.116667147 Jul 12 04:43:51 PM PDT 24 Jul 12 04:44:49 PM PDT 24 19266101627 ps
T846 /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1071754814 Jul 12 04:44:23 PM PDT 24 Jul 12 04:44:38 PM PDT 24 2018316404 ps
T847 /workspace/coverage/default/41.lc_ctrl_sec_token_mux.522795310 Jul 12 04:44:40 PM PDT 24 Jul 12 04:44:51 PM PDT 24 3083932712 ps
T848 /workspace/coverage/default/14.lc_ctrl_errors.2429460060 Jul 12 04:43:28 PM PDT 24 Jul 12 04:43:49 PM PDT 24 815670646 ps
T849 /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2655814944 Jul 12 04:42:45 PM PDT 24 Jul 12 04:42:48 PM PDT 24 103224524 ps
T850 /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1909031777 Jul 12 04:44:29 PM PDT 24 Jul 12 04:44:44 PM PDT 24 525182872 ps
T851 /workspace/coverage/default/16.lc_ctrl_prog_failure.1736895392 Jul 12 04:43:37 PM PDT 24 Jul 12 04:43:42 PM PDT 24 73101833 ps
T852 /workspace/coverage/default/41.lc_ctrl_stress_all.1735200236 Jul 12 04:44:41 PM PDT 24 Jul 12 04:48:58 PM PDT 24 6093762078 ps
T853 /workspace/coverage/default/12.lc_ctrl_errors.2341442957 Jul 12 04:43:19 PM PDT 24 Jul 12 04:43:33 PM PDT 24 579169269 ps
T854 /workspace/coverage/default/0.lc_ctrl_stress_all.1598765818 Jul 12 04:42:45 PM PDT 24 Jul 12 04:43:17 PM PDT 24 1623814671 ps
T855 /workspace/coverage/default/31.lc_ctrl_alert_test.3148116817 Jul 12 04:44:17 PM PDT 24 Jul 12 04:44:25 PM PDT 24 103708672 ps
T856 /workspace/coverage/default/8.lc_ctrl_state_failure.3548174293 Jul 12 04:43:08 PM PDT 24 Jul 12 04:43:38 PM PDT 24 251519622 ps
T857 /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3265041671 Jul 12 04:42:53 PM PDT 24 Jul 12 04:44:07 PM PDT 24 7336712422 ps
T858 /workspace/coverage/default/33.lc_ctrl_prog_failure.1163062589 Jul 12 04:44:22 PM PDT 24 Jul 12 04:44:31 PM PDT 24 61184079 ps
T859 /workspace/coverage/default/3.lc_ctrl_prog_failure.2420131101 Jul 12 04:42:48 PM PDT 24 Jul 12 04:42:52 PM PDT 24 76574033 ps
T860 /workspace/coverage/default/41.lc_ctrl_state_post_trans.3210010159 Jul 12 04:44:40 PM PDT 24 Jul 12 04:44:46 PM PDT 24 197127448 ps
T861 /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3960116144 Jul 12 04:43:04 PM PDT 24 Jul 12 04:43:31 PM PDT 24 783936470 ps
T153 /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.1322338454 Jul 12 04:44:13 PM PDT 24 Jul 12 05:00:05 PM PDT 24 217551786378 ps
T862 /workspace/coverage/default/16.lc_ctrl_state_failure.1013356113 Jul 12 04:43:37 PM PDT 24 Jul 12 04:44:03 PM PDT 24 406571376 ps
T863 /workspace/coverage/default/15.lc_ctrl_smoke.42526923 Jul 12 04:43:40 PM PDT 24 Jul 12 04:43:45 PM PDT 24 204906252 ps
T864 /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3107055733 Jul 12 04:43:23 PM PDT 24 Jul 12 04:43:38 PM PDT 24 377986084 ps
T865 /workspace/coverage/default/3.lc_ctrl_jtag_access.1367900127 Jul 12 04:43:03 PM PDT 24 Jul 12 04:43:28 PM PDT 24 17932364130 ps
T866 /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1034621404 Jul 12 04:44:24 PM PDT 24 Jul 12 04:44:37 PM PDT 24 578395440 ps
T867 /workspace/coverage/default/26.lc_ctrl_prog_failure.3459460355 Jul 12 04:44:04 PM PDT 24 Jul 12 04:44:14 PM PDT 24 175542091 ps
T868 /workspace/coverage/default/1.lc_ctrl_prog_failure.107950583 Jul 12 04:42:42 PM PDT 24 Jul 12 04:42:47 PM PDT 24 334330214 ps
T869 /workspace/coverage/default/2.lc_ctrl_stress_all.3980814914 Jul 12 04:42:50 PM PDT 24 Jul 12 04:43:41 PM PDT 24 692047291 ps
T120 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3764645461 Jul 12 04:42:11 PM PDT 24 Jul 12 04:42:14 PM PDT 24 17142230 ps
T108 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.334666719 Jul 12 04:42:37 PM PDT 24 Jul 12 04:42:41 PM PDT 24 352118750 ps
T121 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3751173047 Jul 12 04:42:31 PM PDT 24 Jul 12 04:42:34 PM PDT 24 43868314 ps
T111 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3610418724 Jul 12 04:42:20 PM PDT 24 Jul 12 04:42:22 PM PDT 24 22263923 ps
T109 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2606666275 Jul 12 04:42:36 PM PDT 24 Jul 12 04:42:39 PM PDT 24 67624114 ps
T172 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2541090983 Jul 12 04:42:11 PM PDT 24 Jul 12 04:42:13 PM PDT 24 31854896 ps
T148 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.226425826 Jul 12 04:42:38 PM PDT 24 Jul 12 04:42:41 PM PDT 24 27840401 ps
T116 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3733884677 Jul 12 04:41:58 PM PDT 24 Jul 12 04:42:01 PM PDT 24 135935256 ps
T173 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1241285541 Jul 12 04:42:11 PM PDT 24 Jul 12 04:42:14 PM PDT 24 12871773 ps
T140 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.291257518 Jul 12 04:42:19 PM PDT 24 Jul 12 04:42:23 PM PDT 24 71681551 ps
T149 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1525573218 Jul 12 04:41:58 PM PDT 24 Jul 12 04:42:01 PM PDT 24 32436272 ps
T150 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3848137834 Jul 12 04:42:00 PM PDT 24 Jul 12 04:42:03 PM PDT 24 32521136 ps
T141 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3053502215 Jul 12 04:42:11 PM PDT 24 Jul 12 04:42:15 PM PDT 24 131636124 ps
T186 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3747939197 Jul 12 04:42:35 PM PDT 24 Jul 12 04:42:38 PM PDT 24 46146179 ps
T110 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2182339581 Jul 12 04:42:29 PM PDT 24 Jul 12 04:42:34 PM PDT 24 54393926 ps
T117 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1482189972 Jul 12 04:42:25 PM PDT 24 Jul 12 04:42:28 PM PDT 24 127069008 ps
T870 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3097134031 Jul 12 04:42:12 PM PDT 24 Jul 12 04:42:19 PM PDT 24 998138954 ps
T194 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.856167555 Jul 12 04:41:59 PM PDT 24 Jul 12 04:42:12 PM PDT 24 425143782 ps
T195 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2379628476 Jul 12 04:41:58 PM PDT 24 Jul 12 04:42:01 PM PDT 24 202670511 ps
T118 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1167144860 Jul 12 04:42:19 PM PDT 24 Jul 12 04:42:22 PM PDT 24 26922181 ps
T112 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2759213648 Jul 12 04:42:27 PM PDT 24 Jul 12 04:42:32 PM PDT 24 556395076 ps
T137 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4007218645 Jul 12 04:42:29 PM PDT 24 Jul 12 04:42:31 PM PDT 24 42604547 ps
T113 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3345300374 Jul 12 04:42:33 PM PDT 24 Jul 12 04:42:40 PM PDT 24 152751636 ps
T871 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2352176917 Jul 12 04:42:35 PM PDT 24 Jul 12 04:42:37 PM PDT 24 57070041 ps
T138 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1262205971 Jul 12 04:41:59 PM PDT 24 Jul 12 04:42:03 PM PDT 24 896220457 ps
T872 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2682083379 Jul 12 04:41:58 PM PDT 24 Jul 12 04:42:02 PM PDT 24 82420090 ps
T174 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3158148293 Jul 12 04:42:21 PM PDT 24 Jul 12 04:42:23 PM PDT 24 18071773 ps
T873 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3266678285 Jul 12 04:42:19 PM PDT 24 Jul 12 04:42:26 PM PDT 24 1732639592 ps
T114 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.865651482 Jul 12 04:42:32 PM PDT 24 Jul 12 04:42:37 PM PDT 24 103835743 ps
T874 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.861724380 Jul 12 04:42:25 PM PDT 24 Jul 12 04:42:38 PM PDT 24 3746752458 ps
T875 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2353252787 Jul 12 04:42:12 PM PDT 24 Jul 12 04:42:16 PM PDT 24 338630711 ps
T187 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3199533858 Jul 12 04:42:23 PM PDT 24 Jul 12 04:42:25 PM PDT 24 118944786 ps
T876 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2528186194 Jul 12 04:42:04 PM PDT 24 Jul 12 04:42:06 PM PDT 24 48159926 ps
T188 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1543863569 Jul 12 04:42:30 PM PDT 24 Jul 12 04:42:33 PM PDT 24 41435543 ps
T175 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.353518047 Jul 12 04:42:38 PM PDT 24 Jul 12 04:42:40 PM PDT 24 51600481 ps
T189 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2959557847 Jul 12 04:41:59 PM PDT 24 Jul 12 04:42:02 PM PDT 24 80331407 ps
T877 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.558958538 Jul 12 04:42:26 PM PDT 24 Jul 12 04:42:45 PM PDT 24 2204477673 ps
T129 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1626278655 Jul 12 04:42:24 PM PDT 24 Jul 12 04:42:27 PM PDT 24 88406777 ps
T190 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.137521421 Jul 12 04:42:25 PM PDT 24 Jul 12 04:42:27 PM PDT 24 44824418 ps
T878 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.923523730 Jul 12 04:42:32 PM PDT 24 Jul 12 04:42:35 PM PDT 24 31125539 ps
T115 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1657257171 Jul 12 04:42:31 PM PDT 24 Jul 12 04:42:36 PM PDT 24 225351050 ps
T879 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2745073489 Jul 12 04:42:18 PM PDT 24 Jul 12 04:42:24 PM PDT 24 1798839276 ps
T880 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.551172269 Jul 12 04:42:06 PM PDT 24 Jul 12 04:42:09 PM PDT 24 206114892 ps
T119 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.335030546 Jul 12 04:42:37 PM PDT 24 Jul 12 04:42:41 PM PDT 24 30434672 ps
T881 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2804826729 Jul 12 04:42:11 PM PDT 24 Jul 12 04:42:16 PM PDT 24 103158629 ps
T882 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1016309912 Jul 12 04:42:25 PM PDT 24 Jul 12 04:42:36 PM PDT 24 1176559777 ps
T191 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1986261040 Jul 12 04:42:12 PM PDT 24 Jul 12 04:42:16 PM PDT 24 22042235 ps
T883 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1663077992 Jul 12 04:42:37 PM PDT 24 Jul 12 04:42:39 PM PDT 24 16073082 ps
T884 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1976903139 Jul 12 04:42:37 PM PDT 24 Jul 12 04:42:40 PM PDT 24 40793179 ps
T885 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.584932955 Jul 12 04:42:18 PM PDT 24 Jul 12 04:42:22 PM PDT 24 179344305 ps
T176 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.4174087477 Jul 12 04:42:34 PM PDT 24 Jul 12 04:42:36 PM PDT 24 46585882 ps
T886 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.768826407 Jul 12 04:42:14 PM PDT 24 Jul 12 04:42:17 PM PDT 24 17149494 ps
T887 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1505242316 Jul 12 04:43:42 PM PDT 24 Jul 12 04:43:44 PM PDT 24 38270316 ps
T136 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2137256054 Jul 12 04:42:28 PM PDT 24 Jul 12 04:42:34 PM PDT 24 593824658 ps
T888 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2538855621 Jul 12 04:49:07 PM PDT 24 Jul 12 04:49:21 PM PDT 24 3751962367 ps
T889 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1817907415 Jul 12 04:42:19 PM PDT 24 Jul 12 04:42:23 PM PDT 24 1232113488 ps
T890 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.362801953 Jul 12 04:42:39 PM PDT 24 Jul 12 04:42:42 PM PDT 24 18101661 ps
T891 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1133320850 Jul 12 04:42:24 PM PDT 24 Jul 12 04:42:27 PM PDT 24 58496627 ps
T892 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2879694321 Jul 12 04:42:06 PM PDT 24 Jul 12 04:42:15 PM PDT 24 1485943240 ps
T893 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3646367397 Jul 12 04:42:29 PM PDT 24 Jul 12 04:42:32 PM PDT 24 15055655 ps
T894 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.884030914 Jul 12 04:41:59 PM PDT 24 Jul 12 04:42:13 PM PDT 24 519030255 ps
T895 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3128642476 Jul 12 04:42:19 PM PDT 24 Jul 12 04:42:23 PM PDT 24 17627103 ps
T139 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.537323748 Jul 12 04:41:59 PM PDT 24 Jul 12 04:42:03 PM PDT 24 67101768 ps
T200 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.751039426 Jul 12 04:42:42 PM PDT 24 Jul 12 04:42:46 PM PDT 24 68020494 ps
T131 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3450345229 Jul 12 04:42:18 PM PDT 24 Jul 12 04:42:23 PM PDT 24 225875880 ps
T896 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2535487420 Jul 12 04:42:24 PM PDT 24 Jul 12 04:42:26 PM PDT 24 15248188 ps
T124 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2948092412 Jul 12 04:42:43 PM PDT 24 Jul 12 04:42:47 PM PDT 24 70780109 ps
T897 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3782776968 Jul 12 04:42:19 PM PDT 24 Jul 12 04:42:24 PM PDT 24 170628975 ps
T126 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.795423973 Jul 12 04:42:13 PM PDT 24 Jul 12 04:42:17 PM PDT 24 142150297 ps
T898 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3261277311 Jul 12 04:42:38 PM PDT 24 Jul 12 04:42:40 PM PDT 24 36590655 ps
T899 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2405173042 Jul 12 04:42:18 PM PDT 24 Jul 12 04:42:32 PM PDT 24 2234074449 ps
T900 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.21798081 Jul 12 04:42:19 PM PDT 24 Jul 12 04:42:23 PM PDT 24 32565523 ps
T901 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4091278383 Jul 12 04:42:29 PM PDT 24 Jul 12 04:42:32 PM PDT 24 429880192 ps
T902 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1589932094 Jul 12 04:42:19 PM PDT 24 Jul 12 04:42:23 PM PDT 24 223688470 ps
T903 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.413683979 Jul 12 04:42:08 PM PDT 24 Jul 12 04:42:10 PM PDT 24 22797210 ps
T133 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1403103999 Jul 12 04:41:59 PM PDT 24 Jul 12 04:42:05 PM PDT 24 293375153 ps
T904 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3851405379 Jul 12 04:42:40 PM PDT 24 Jul 12 04:42:42 PM PDT 24 51664506 ps
T905 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.332173200 Jul 12 04:42:06 PM PDT 24 Jul 12 04:42:08 PM PDT 24 44708577 ps
T906 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3198040006 Jul 12 04:42:19 PM PDT 24 Jul 12 04:42:23 PM PDT 24 54993418 ps
T177 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.255442370 Jul 12 04:42:30 PM PDT 24 Jul 12 04:42:33 PM PDT 24 20800116 ps
T907 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3378301224 Jul 12 04:42:28 PM PDT 24 Jul 12 04:42:30 PM PDT 24 59077408 ps
T908 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3190485365 Jul 12 04:41:58 PM PDT 24 Jul 12 04:42:02 PM PDT 24 176985892 ps
T178 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1105794380 Jul 12 04:42:12 PM PDT 24 Jul 12 04:42:16 PM PDT 24 285874749 ps
T909 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.253537290 Jul 12 04:42:31 PM PDT 24 Jul 12 04:42:34 PM PDT 24 28096685 ps
T910 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1663906388 Jul 12 04:42:16 PM PDT 24 Jul 12 04:42:19 PM PDT 24 50369191 ps
T911 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.796007935 Jul 12 04:42:43 PM PDT 24 Jul 12 04:42:46 PM PDT 24 36291985 ps
T912 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.616621404 Jul 12 04:42:12 PM PDT 24 Jul 12 04:42:16 PM PDT 24 85438875 ps
T913 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2231560479 Jul 12 04:42:43 PM PDT 24 Jul 12 04:42:46 PM PDT 24 31199376 ps
T914 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1691874181 Jul 12 04:42:05 PM PDT 24 Jul 12 04:42:32 PM PDT 24 1176646483 ps
T915 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2884304395 Jul 12 04:42:01 PM PDT 24 Jul 12 04:42:27 PM PDT 24 5139227963 ps
T916 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1095549889 Jul 12 04:41:59 PM PDT 24 Jul 12 04:42:04 PM PDT 24 67477604 ps
T917 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2824754363 Jul 12 04:42:36 PM PDT 24 Jul 12 04:42:40 PM PDT 24 169309175 ps
T918 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1933186250 Jul 12 04:42:33 PM PDT 24 Jul 12 04:42:37 PM PDT 24 96468075 ps
T128 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1705320111 Jul 12 04:42:32 PM PDT 24 Jul 12 04:42:36 PM PDT 24 179086357 ps
T122 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.722592275 Jul 12 04:42:26 PM PDT 24 Jul 12 04:42:32 PM PDT 24 413846102 ps
T919 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2377681422 Jul 12 04:42:13 PM PDT 24 Jul 12 04:42:16 PM PDT 24 21379875 ps
T182 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1408777589 Jul 12 04:41:59 PM PDT 24 Jul 12 04:42:04 PM PDT 24 210797830 ps
T920 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.329270838 Jul 12 04:42:29 PM PDT 24 Jul 12 04:42:32 PM PDT 24 29457741 ps
T921 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.4117478778 Jul 12 04:42:02 PM PDT 24 Jul 12 04:42:04 PM PDT 24 18509838 ps
T922 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3137629316 Jul 12 04:42:25 PM PDT 24 Jul 12 04:42:28 PM PDT 24 188312769 ps
T923 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3464276401 Jul 12 04:42:36 PM PDT 24 Jul 12 04:42:40 PM PDT 24 29672855 ps
T179 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1346570522 Jul 12 04:42:00 PM PDT 24 Jul 12 04:42:03 PM PDT 24 17216831 ps
T924 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2272445511 Jul 12 04:42:14 PM PDT 24 Jul 12 04:42:17 PM PDT 24 30330416 ps
T925 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1301749637 Jul 12 04:42:18 PM PDT 24 Jul 12 04:42:21 PM PDT 24 116896311 ps
T926 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2171290855 Jul 12 04:42:20 PM PDT 24 Jul 12 04:42:24 PM PDT 24 49215690 ps
T927 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3595398437 Jul 12 04:42:05 PM PDT 24 Jul 12 04:42:07 PM PDT 24 64660257 ps
T928 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1080974417 Jul 12 04:42:14 PM PDT 24 Jul 12 04:42:17 PM PDT 24 45613908 ps
T929 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3474733879 Jul 12 04:42:11 PM PDT 24 Jul 12 04:42:15 PM PDT 24 46850216 ps
T930 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2101427135 Jul 12 04:42:22 PM PDT 24 Jul 12 04:42:24 PM PDT 24 89515075 ps
T931 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2705230869 Jul 12 04:42:11 PM PDT 24 Jul 12 04:42:14 PM PDT 24 190835598 ps
T932 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.350319689 Jul 12 04:42:35 PM PDT 24 Jul 12 04:42:39 PM PDT 24 62975040 ps
T125 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1757856466 Jul 12 04:42:39 PM PDT 24 Jul 12 04:42:43 PM PDT 24 376692686 ps
T933 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2375997173 Jul 12 04:42:18 PM PDT 24 Jul 12 04:42:21 PM PDT 24 23985364 ps
T934 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.470544651 Jul 12 04:42:26 PM PDT 24 Jul 12 04:42:28 PM PDT 24 45982322 ps
T935 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3895382548 Jul 12 04:42:18 PM PDT 24 Jul 12 04:42:34 PM PDT 24 591064508 ps
T936 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4241610915 Jul 12 04:42:05 PM PDT 24 Jul 12 04:42:08 PM PDT 24 34566494 ps
T937 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1634485312 Jul 12 04:42:32 PM PDT 24 Jul 12 04:42:35 PM PDT 24 13192873 ps
T938 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3824855491 Jul 12 04:42:05 PM PDT 24 Jul 12 04:42:07 PM PDT 24 162206019 ps
T939 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.126435510 Jul 12 04:42:00 PM PDT 24 Jul 12 04:42:04 PM PDT 24 26727363 ps
T940 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4214190149 Jul 12 04:42:00 PM PDT 24 Jul 12 04:42:05 PM PDT 24 168045492 ps
T941 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1604331051 Jul 12 04:42:22 PM PDT 24 Jul 12 04:42:24 PM PDT 24 42811959 ps
T942 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.780869228 Jul 12 04:42:05 PM PDT 24 Jul 12 04:42:08 PM PDT 24 640016163 ps
T943 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.801991362 Jul 12 04:42:38 PM PDT 24 Jul 12 04:42:42 PM PDT 24 57838433 ps
T944 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.73460127 Jul 12 04:41:58 PM PDT 24 Jul 12 04:42:06 PM PDT 24 878270922 ps
T945 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2178497844 Jul 12 04:42:13 PM PDT 24 Jul 12 04:42:17 PM PDT 24 1514763941 ps
T946 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2113709778 Jul 12 04:42:12 PM PDT 24 Jul 12 04:42:22 PM PDT 24 697160365 ps
T947 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.871772745 Jul 12 04:42:00 PM PDT 24 Jul 12 04:42:03 PM PDT 24 81592797 ps
T948 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1610130064 Jul 12 04:42:33 PM PDT 24 Jul 12 04:42:51 PM PDT 24 2477015058 ps
T123 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.705031633 Jul 12 04:42:33 PM PDT 24 Jul 12 04:42:37 PM PDT 24 62023317 ps
T949 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3978865920 Jul 12 04:42:18 PM PDT 24 Jul 12 04:42:23 PM PDT 24 704134556 ps
T950 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.4048370901 Jul 12 04:42:32 PM PDT 24 Jul 12 04:42:35 PM PDT 24 294865062 ps
T951 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.4209468282 Jul 12 04:42:25 PM PDT 24 Jul 12 04:42:29 PM PDT 24 148561151 ps
T952 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2060902775 Jul 12 04:42:11 PM PDT 24 Jul 12 04:42:14 PM PDT 24 228354607 ps
T953 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2886055729 Jul 12 04:42:11 PM PDT 24 Jul 12 04:42:15 PM PDT 24 85702065 ps
T954 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4013551172 Jul 12 04:42:30 PM PDT 24 Jul 12 04:42:33 PM PDT 24 26648620 ps
T955 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3042536520 Jul 12 04:42:24 PM PDT 24 Jul 12 04:42:35 PM PDT 24 443721318 ps
T956 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.461981882 Jul 12 04:42:35 PM PDT 24 Jul 12 04:42:38 PM PDT 24 258058428 ps
T957 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1711450022 Jul 12 04:42:31 PM PDT 24 Jul 12 04:42:34 PM PDT 24 20933693 ps
T958 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2920219665 Jul 12 04:42:34 PM PDT 24 Jul 12 04:42:36 PM PDT 24 36230472 ps
T959 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2121789139 Jul 12 04:41:58 PM PDT 24 Jul 12 04:42:01 PM PDT 24 61435800 ps
T960 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4273380740 Jul 12 04:42:10 PM PDT 24 Jul 12 04:42:14 PM PDT 24 126165508 ps
T961 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1534250746 Jul 12 04:42:20 PM PDT 24 Jul 12 04:42:26 PM PDT 24 256032859 ps
T962 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.714183774 Jul 12 04:42:18 PM PDT 24 Jul 12 04:42:22 PM PDT 24 55528074 ps
T963 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3114083547 Jul 12 04:42:29 PM PDT 24 Jul 12 04:42:34 PM PDT 24 62611488 ps
T130 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2613836395 Jul 12 04:42:10 PM PDT 24 Jul 12 04:42:13 PM PDT 24 43555560 ps
T964 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4206381775 Jul 12 04:42:31 PM PDT 24 Jul 12 04:42:35 PM PDT 24 1208906307 ps
T965 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3568652366 Jul 12 04:42:36 PM PDT 24 Jul 12 04:42:39 PM PDT 24 24790810 ps
T135 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3818421670 Jul 12 04:42:05 PM PDT 24 Jul 12 04:42:09 PM PDT 24 68209978 ps
T966 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.4224641973 Jul 12 04:42:06 PM PDT 24 Jul 12 04:42:08 PM PDT 24 28183366 ps
T967 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1296628065 Jul 12 04:42:26 PM PDT 24 Jul 12 04:42:32 PM PDT 24 357894030 ps
T968 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2920719045 Jul 12 04:42:11 PM PDT 24 Jul 12 04:42:19 PM PDT 24 136803030 ps
T969 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3605017470 Jul 12 04:42:36 PM PDT 24 Jul 12 04:42:38 PM PDT 24 24065962 ps
T134 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3852208814 Jul 12 04:42:00 PM PDT 24 Jul 12 04:42:06 PM PDT 24 101889174 ps
T180 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2696182471 Jul 12 04:42:14 PM PDT 24 Jul 12 04:42:16 PM PDT 24 35321329 ps
T970 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3730977793 Jul 12 04:42:23 PM PDT 24 Jul 12 04:42:30 PM PDT 24 442511223 ps
T971 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.761669410 Jul 12 04:42:32 PM PDT 24 Jul 12 04:42:35 PM PDT 24 26822966 ps
T972 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3300824146 Jul 12 04:42:25 PM PDT 24 Jul 12 04:42:28 PM PDT 24 1486776989 ps
T181 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.137547177 Jul 12 04:41:59 PM PDT 24 Jul 12 04:42:02 PM PDT 24 24557366 ps
T132 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2721749755 Jul 12 04:42:29 PM PDT 24 Jul 12 04:42:33 PM PDT 24 56868027 ps
T183 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.4082958949 Jul 12 04:42:08 PM PDT 24 Jul 12 04:42:10 PM PDT 24 20964557 ps
T973 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4114778576 Jul 12 04:42:39 PM PDT 24 Jul 12 04:42:43 PM PDT 24 30512582 ps
T974 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.919143847 Jul 12 04:42:26 PM PDT 24 Jul 12 04:42:32 PM PDT 24 174443419 ps
T975 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.117701478 Jul 12 04:42:03 PM PDT 24 Jul 12 04:42:06 PM PDT 24 38745902 ps
T976 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.710396737 Jul 12 04:42:30 PM PDT 24 Jul 12 04:42:34 PM PDT 24 129890655 ps
T127 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.769033656 Jul 12 04:42:33 PM PDT 24 Jul 12 04:42:37 PM PDT 24 513889102 ps
T184 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3073106506 Jul 12 04:42:24 PM PDT 24 Jul 12 04:42:27 PM PDT 24 26725929 ps
T977 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1335315795 Jul 12 04:51:46 PM PDT 24 Jul 12 04:51:51 PM PDT 24 147772850 ps
T978 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1858953477 Jul 12 04:42:10 PM PDT 24 Jul 12 04:42:14 PM PDT 24 379896463 ps
T979 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1910390697 Jul 12 04:42:26 PM PDT 24 Jul 12 04:42:29 PM PDT 24 48736552 ps
T980 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2988381560 Jul 12 04:42:00 PM PDT 24 Jul 12 04:42:03 PM PDT 24 54856245 ps
T981 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2638239670 Jul 12 04:42:21 PM PDT 24 Jul 12 04:42:25 PM PDT 24 175833239 ps
T185 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.403245405 Jul 12 04:42:32 PM PDT 24 Jul 12 04:42:35 PM PDT 24 80481201 ps
T982 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3633142616 Jul 12 04:42:37 PM PDT 24 Jul 12 04:42:40 PM PDT 24 22478701 ps
T983 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2680076233 Jul 12 04:42:24 PM PDT 24 Jul 12 04:42:27 PM PDT 24 168751685 ps
T984 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3621875169 Jul 12 04:42:06 PM PDT 24 Jul 12 04:42:34 PM PDT 24 4393396595 ps
T985 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.230003086 Jul 12 04:42:05 PM PDT 24 Jul 12 04:42:08 PM PDT 24 149867748 ps
T986 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3208323804 Jul 12 04:42:35 PM PDT 24 Jul 12 04:42:37 PM PDT 24 155388106 ps
T987 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3555734289 Jul 12 04:42:28 PM PDT 24 Jul 12 04:42:31 PM PDT 24 74550092 ps
T988 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1749199095 Jul 12 04:42:05 PM PDT 24 Jul 12 04:42:08 PM PDT 24 52506695 ps
T989 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.319436076 Jul 12 04:42:05 PM PDT 24 Jul 12 04:42:07 PM PDT 24 123001896 ps
T990 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.546579908 Jul 12 04:42:37 PM PDT 24 Jul 12 04:42:40 PM PDT 24 23948235 ps
T991 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.261481168 Jul 12 04:42:12 PM PDT 24 Jul 12 04:42:19 PM PDT 24 180360392 ps
T992 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3506086535 Jul 12 04:42:11 PM PDT 24 Jul 12 04:42:14 PM PDT 24 198288231 ps
T993 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.4120383377 Jul 12 04:42:35 PM PDT 24 Jul 12 04:42:37 PM PDT 24 16628954 ps
T994 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3251545199 Jul 12 04:42:23 PM PDT 24 Jul 12 04:42:25 PM PDT 24 86352045 ps

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3037670728
Short name T4
Test name
Test status
Simulation time 115280076550 ps
CPU time 702.46 seconds
Started Jul 12 04:44:48 PM PDT 24
Finished Jul 12 04:56:32 PM PDT 24
Peak memory 283324 kb
Host smart-1f1fef82-5e9b-464c-a9f9-0a6da479a6e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3037670728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.3037670728
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1282637460
Short name T13
Test name
Test status
Simulation time 475212019 ps
CPU time 9.4 seconds
Started Jul 12 04:44:01 PM PDT 24
Finished Jul 12 04:44:18 PM PDT 24
Peak memory 217772 kb
Host smart-07b368ff-c755-4279-bbc4-adbed5596ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282637460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1282637460
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3841915649
Short name T56
Test name
Test status
Simulation time 224028999 ps
CPU time 10.93 seconds
Started Jul 12 04:45:16 PM PDT 24
Finished Jul 12 04:45:28 PM PDT 24
Peak memory 225408 kb
Host smart-c1be53e5-0435-4ed0-a7f2-a8f5f97ab376
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841915649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3841915649
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3901126283
Short name T14
Test name
Test status
Simulation time 56465359047 ps
CPU time 1436.14 seconds
Started Jul 12 04:42:47 PM PDT 24
Finished Jul 12 05:06:46 PM PDT 24
Peak memory 496252 kb
Host smart-c0656f1d-5313-4cd7-a4eb-289d45d50459
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3901126283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.3901126283
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3519579950
Short name T36
Test name
Test status
Simulation time 84104030 ps
CPU time 0.79 seconds
Started Jul 12 04:44:28 PM PDT 24
Finished Jul 12 04:44:32 PM PDT 24
Peak memory 208344 kb
Host smart-1d0c2d43-3716-4a81-b7d5-44baf96fc42b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519579950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3519579950
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.334666719
Short name T108
Test name
Test status
Simulation time 352118750 ps
CPU time 3.23 seconds
Started Jul 12 04:42:37 PM PDT 24
Finished Jul 12 04:42:41 PM PDT 24
Peak memory 217784 kb
Host smart-821add75-a8f5-4603-b1bc-c6f7bebd9c08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334666719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.334666719
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1292732018
Short name T52
Test name
Test status
Simulation time 1501577065 ps
CPU time 37.25 seconds
Started Jul 12 04:42:46 PM PDT 24
Finished Jul 12 04:43:26 PM PDT 24
Peak memory 269504 kb
Host smart-5ee8e362-a73c-4e86-b3e1-7a97605ba592
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292732018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1292732018
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3349387789
Short name T325
Test name
Test status
Simulation time 1388129874 ps
CPU time 9.47 seconds
Started Jul 12 04:42:47 PM PDT 24
Finished Jul 12 04:42:58 PM PDT 24
Peak memory 217728 kb
Host smart-c94f20f1-5945-4062-bc50-6f310aeca745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349387789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3349387789
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2952406064
Short name T208
Test name
Test status
Simulation time 293496411 ps
CPU time 6.87 seconds
Started Jul 12 04:45:02 PM PDT 24
Finished Jul 12 04:45:13 PM PDT 24
Peak memory 225412 kb
Host smart-8f1bff02-6430-41cc-b568-e1d9d1e99082
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952406064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2952406064
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.2410664819
Short name T103
Test name
Test status
Simulation time 16357654628 ps
CPU time 371.23 seconds
Started Jul 12 04:44:18 PM PDT 24
Finished Jul 12 04:50:35 PM PDT 24
Peak memory 299212 kb
Host smart-ccca560a-4f8c-44c6-949a-a9ba67390227
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2410664819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.2410664819
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1279100097
Short name T7
Test name
Test status
Simulation time 664822624 ps
CPU time 11.19 seconds
Started Jul 12 04:44:22 PM PDT 24
Finished Jul 12 04:44:39 PM PDT 24
Peak memory 216644 kb
Host smart-6ce8f43f-9e02-4e43-ae58-61f66b226654
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279100097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1279100097
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3345300374
Short name T113
Test name
Test status
Simulation time 152751636 ps
CPU time 5.15 seconds
Started Jul 12 04:42:33 PM PDT 24
Finished Jul 12 04:42:40 PM PDT 24
Peak memory 217456 kb
Host smart-3c9e1345-69c3-44b5-abf1-c05bf8a9f31e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345300374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3345300374
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3397808608
Short name T80
Test name
Test status
Simulation time 53338425 ps
CPU time 1.14 seconds
Started Jul 12 04:44:22 PM PDT 24
Finished Jul 12 04:44:29 PM PDT 24
Peak memory 208456 kb
Host smart-a769ba95-db97-4840-bdf3-05d868c3b129
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397808608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3397808608
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2541090983
Short name T172
Test name
Test status
Simulation time 31854896 ps
CPU time 0.81 seconds
Started Jul 12 04:42:11 PM PDT 24
Finished Jul 12 04:42:13 PM PDT 24
Peak memory 208364 kb
Host smart-6e98699f-199c-4d32-9900-2ec7e85693a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541090983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2541090983
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1262205971
Short name T138
Test name
Test status
Simulation time 896220457 ps
CPU time 1.89 seconds
Started Jul 12 04:41:59 PM PDT 24
Finished Jul 12 04:42:03 PM PDT 24
Peak memory 218608 kb
Host smart-d7e64e97-bbfe-43db-8d31-1c3cd071bb5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126220
5971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1262205971
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1546830066
Short name T10
Test name
Test status
Simulation time 286891235 ps
CPU time 29.81 seconds
Started Jul 12 04:43:01 PM PDT 24
Finished Jul 12 04:43:35 PM PDT 24
Peak memory 245452 kb
Host smart-b87fb052-b275-4708-8bb9-bf3f4783e39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546830066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1546830066
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3158148293
Short name T174
Test name
Test status
Simulation time 18071773 ps
CPU time 0.94 seconds
Started Jul 12 04:42:21 PM PDT 24
Finished Jul 12 04:42:23 PM PDT 24
Peak memory 209228 kb
Host smart-65a16d2e-17cb-43c1-ad11-18f090010e7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158148293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3158148293
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.769033656
Short name T127
Test name
Test status
Simulation time 513889102 ps
CPU time 2.93 seconds
Started Jul 12 04:42:33 PM PDT 24
Finished Jul 12 04:42:37 PM PDT 24
Peak memory 221820 kb
Host smart-59941ef8-23aa-4119-b5f7-c9f56e6182de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769033656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.769033656
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3434534109
Short name T29
Test name
Test status
Simulation time 26847063 ps
CPU time 0.92 seconds
Started Jul 12 04:44:40 PM PDT 24
Finished Jul 12 04:44:44 PM PDT 24
Peak memory 208352 kb
Host smart-75911801-f300-405c-84fa-71b959984fac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434534109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3434534109
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3818421670
Short name T135
Test name
Test status
Simulation time 68209978 ps
CPU time 2.71 seconds
Started Jul 12 04:42:05 PM PDT 24
Finished Jul 12 04:42:09 PM PDT 24
Peak memory 217392 kb
Host smart-90389249-f953-4401-86da-0753d247c812
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818421670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3818421670
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3450345229
Short name T131
Test name
Test status
Simulation time 225875880 ps
CPU time 2.81 seconds
Started Jul 12 04:42:18 PM PDT 24
Finished Jul 12 04:42:23 PM PDT 24
Peak memory 222268 kb
Host smart-c5661d52-0707-4b73-9dbd-80f1df4ac1f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450345229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3450345229
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2948092412
Short name T124
Test name
Test status
Simulation time 70780109 ps
CPU time 2.63 seconds
Started Jul 12 04:42:43 PM PDT 24
Finished Jul 12 04:42:47 PM PDT 24
Peak memory 222196 kb
Host smart-65c3f294-8fad-4d77-9759-2ca77c2fce87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948092412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2948092412
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2987295589
Short name T83
Test name
Test status
Simulation time 39767737577 ps
CPU time 698.72 seconds
Started Jul 12 04:43:26 PM PDT 24
Finished Jul 12 04:55:06 PM PDT 24
Peak memory 316132 kb
Host smart-e8ee948b-acf8-47eb-8d31-2b3310125158
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2987295589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.2987295589
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2402508955
Short name T1
Test name
Test status
Simulation time 4076979342 ps
CPU time 10.94 seconds
Started Jul 12 04:43:36 PM PDT 24
Finished Jul 12 04:43:48 PM PDT 24
Peak memory 225460 kb
Host smart-f21800da-b98c-4620-b725-27dbff869502
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402508955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2402508955
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1705320111
Short name T128
Test name
Test status
Simulation time 179086357 ps
CPU time 1.9 seconds
Started Jul 12 04:42:32 PM PDT 24
Finished Jul 12 04:42:36 PM PDT 24
Peak memory 221732 kb
Host smart-27985721-f227-4916-aa4d-b564d70e8bb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705320111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1705320111
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2223331786
Short name T196
Test name
Test status
Simulation time 38932176 ps
CPU time 0.92 seconds
Started Jul 12 04:42:44 PM PDT 24
Finished Jul 12 04:42:47 PM PDT 24
Peak memory 208344 kb
Host smart-2e0a0432-1ffd-4221-9d89-e2b23245bb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223331786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2223331786
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1864228225
Short name T199
Test name
Test status
Simulation time 39857785 ps
CPU time 0.81 seconds
Started Jul 12 04:42:50 PM PDT 24
Finished Jul 12 04:42:53 PM PDT 24
Peak memory 208492 kb
Host smart-7306c445-d492-4788-a87e-2ea791d7fd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864228225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1864228225
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2931081658
Short name T162
Test name
Test status
Simulation time 20061574 ps
CPU time 0.82 seconds
Started Jul 12 04:43:03 PM PDT 24
Finished Jul 12 04:43:07 PM PDT 24
Peak memory 208488 kb
Host smart-d79d2da0-6c13-47b3-95dd-f2b2163610d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931081658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2931081658
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1495979207
Short name T198
Test name
Test status
Simulation time 14121930 ps
CPU time 0.81 seconds
Started Jul 12 04:43:10 PM PDT 24
Finished Jul 12 04:43:14 PM PDT 24
Peak memory 208152 kb
Host smart-5b912370-bbd9-43da-b4ec-4e61930b6d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495979207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1495979207
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3852208814
Short name T134
Test name
Test status
Simulation time 101889174 ps
CPU time 4.12 seconds
Started Jul 12 04:42:00 PM PDT 24
Finished Jul 12 04:42:06 PM PDT 24
Peak memory 217344 kb
Host smart-ca9b9aa6-be19-4829-b5f2-9e55b70c239e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852208814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3852208814
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1657257171
Short name T115
Test name
Test status
Simulation time 225351050 ps
CPU time 2.89 seconds
Started Jul 12 04:42:31 PM PDT 24
Finished Jul 12 04:42:36 PM PDT 24
Peak memory 222496 kb
Host smart-b4d2efa8-50b3-4d38-9495-20530a827335
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657257171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1657257171
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2613836395
Short name T130
Test name
Test status
Simulation time 43555560 ps
CPU time 1.78 seconds
Started Jul 12 04:42:10 PM PDT 24
Finished Jul 12 04:42:13 PM PDT 24
Peak memory 217488 kb
Host smart-c158a0f0-3833-4fd5-b902-ac7829808988
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613836395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2613836395
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2721749755
Short name T132
Test name
Test status
Simulation time 56868027 ps
CPU time 2.03 seconds
Started Jul 12 04:42:29 PM PDT 24
Finished Jul 12 04:42:33 PM PDT 24
Peak memory 221540 kb
Host smart-351b482c-5ad5-4ae8-a739-61973e09764a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721749755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.2721749755
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.1350607182
Short name T45
Test name
Test status
Simulation time 28271258867 ps
CPU time 466.16 seconds
Started Jul 12 04:43:20 PM PDT 24
Finished Jul 12 04:51:10 PM PDT 24
Peak memory 411096 kb
Host smart-1e6beb22-d9f6-4183-b8ef-15d5dfb0cac1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1350607182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.1350607182
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3876744994
Short name T47
Test name
Test status
Simulation time 1141216648 ps
CPU time 17.77 seconds
Started Jul 12 04:44:37 PM PDT 24
Finished Jul 12 04:44:57 PM PDT 24
Peak memory 217612 kb
Host smart-7d3796dd-3a9c-4694-b849-de515d48b7ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876744994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3876744994
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1346570522
Short name T179
Test name
Test status
Simulation time 17216831 ps
CPU time 1.18 seconds
Started Jul 12 04:42:00 PM PDT 24
Finished Jul 12 04:42:03 PM PDT 24
Peak memory 217408 kb
Host smart-5f4460d6-364d-4f12-8695-444143906d12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346570522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1346570522
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1408777589
Short name T182
Test name
Test status
Simulation time 210797830 ps
CPU time 2.09 seconds
Started Jul 12 04:41:59 PM PDT 24
Finished Jul 12 04:42:04 PM PDT 24
Peak memory 209312 kb
Host smart-03f9e035-f09e-4514-b2ba-ee7ef19b0a75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408777589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1408777589
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.137547177
Short name T181
Test name
Test status
Simulation time 24557366 ps
CPU time 1.07 seconds
Started Jul 12 04:41:59 PM PDT 24
Finished Jul 12 04:42:02 PM PDT 24
Peak memory 210088 kb
Host smart-55180e89-5866-45ac-8643-569bb51122aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137547177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.137547177
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3848137834
Short name T150
Test name
Test status
Simulation time 32521136 ps
CPU time 1.17 seconds
Started Jul 12 04:42:00 PM PDT 24
Finished Jul 12 04:42:03 PM PDT 24
Peak memory 217500 kb
Host smart-7ad72deb-23c8-4593-97f2-0d3f82007513
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848137834 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3848137834
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.4117478778
Short name T921
Test name
Test status
Simulation time 18509838 ps
CPU time 0.96 seconds
Started Jul 12 04:42:02 PM PDT 24
Finished Jul 12 04:42:04 PM PDT 24
Peak memory 209156 kb
Host smart-01898b0b-dfd8-4235-87c0-df7d007c059b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117478778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.4117478778
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2988381560
Short name T980
Test name
Test status
Simulation time 54856245 ps
CPU time 0.96 seconds
Started Jul 12 04:42:00 PM PDT 24
Finished Jul 12 04:42:03 PM PDT 24
Peak memory 208524 kb
Host smart-6e36c4bf-1e78-462c-9c18-0754c6ad281e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988381560 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2988381560
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.73460127
Short name T944
Test name
Test status
Simulation time 878270922 ps
CPU time 5.57 seconds
Started Jul 12 04:41:58 PM PDT 24
Finished Jul 12 04:42:06 PM PDT 24
Peak memory 209000 kb
Host smart-baef631e-f1bc-40c9-a9b9-0ed98a1e7ad5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73460127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.lc_ctrl_jtag_csr_aliasing.73460127
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.856167555
Short name T194
Test name
Test status
Simulation time 425143782 ps
CPU time 11.08 seconds
Started Jul 12 04:41:59 PM PDT 24
Finished Jul 12 04:42:12 PM PDT 24
Peak memory 209044 kb
Host smart-15e9439f-66e3-4295-a12c-1994f1a16700
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856167555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.856167555
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2379628476
Short name T195
Test name
Test status
Simulation time 202670511 ps
CPU time 1.3 seconds
Started Jul 12 04:41:58 PM PDT 24
Finished Jul 12 04:42:01 PM PDT 24
Peak memory 217264 kb
Host smart-a58a0b61-3e50-4800-96bf-755957c35e9a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379628476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2379628476
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.537323748
Short name T139
Test name
Test status
Simulation time 67101768 ps
CPU time 1.73 seconds
Started Jul 12 04:41:59 PM PDT 24
Finished Jul 12 04:42:03 PM PDT 24
Peak memory 209124 kb
Host smart-e3a99984-d9e7-4db3-ae07-cf28ee49923a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537323748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.537323748
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1525573218
Short name T149
Test name
Test status
Simulation time 32436272 ps
CPU time 1.55 seconds
Started Jul 12 04:41:58 PM PDT 24
Finished Jul 12 04:42:01 PM PDT 24
Peak memory 209136 kb
Host smart-5e5ba1db-b24e-42f7-8a33-eea48be37af3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525573218 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1525573218
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2959557847
Short name T189
Test name
Test status
Simulation time 80331407 ps
CPU time 1.03 seconds
Started Jul 12 04:41:59 PM PDT 24
Finished Jul 12 04:42:02 PM PDT 24
Peak memory 209240 kb
Host smart-523a40d9-16b5-4210-9b2b-0af1c648f9f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959557847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2959557847
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.126435510
Short name T939
Test name
Test status
Simulation time 26727363 ps
CPU time 2.08 seconds
Started Jul 12 04:42:00 PM PDT 24
Finished Jul 12 04:42:04 PM PDT 24
Peak memory 217644 kb
Host smart-fbdac7bd-48ab-4af5-9f93-fc30998daad0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126435510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.126435510
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1403103999
Short name T133
Test name
Test status
Simulation time 293375153 ps
CPU time 3.34 seconds
Started Jul 12 04:41:59 PM PDT 24
Finished Jul 12 04:42:05 PM PDT 24
Peak memory 217344 kb
Host smart-19091d66-8dc4-443f-9c24-2ce32eec3a81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403103999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1403103999
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1505242316
Short name T887
Test name
Test status
Simulation time 38270316 ps
CPU time 1.03 seconds
Started Jul 12 04:43:42 PM PDT 24
Finished Jul 12 04:43:44 PM PDT 24
Peak memory 209216 kb
Host smart-19a771ce-9969-47b2-8fed-15b75a87176d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505242316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1505242316
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3824855491
Short name T938
Test name
Test status
Simulation time 162206019 ps
CPU time 1.71 seconds
Started Jul 12 04:42:05 PM PDT 24
Finished Jul 12 04:42:07 PM PDT 24
Peak memory 217180 kb
Host smart-84bea13d-b2a3-4745-a986-4bd7cfe186b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824855491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3824855491
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2121789139
Short name T959
Test name
Test status
Simulation time 61435800 ps
CPU time 0.94 seconds
Started Jul 12 04:41:58 PM PDT 24
Finished Jul 12 04:42:01 PM PDT 24
Peak memory 209496 kb
Host smart-d56f898d-1629-4568-b22b-fe894bad3802
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121789139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2121789139
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2528186194
Short name T876
Test name
Test status
Simulation time 48159926 ps
CPU time 1.25 seconds
Started Jul 12 04:42:04 PM PDT 24
Finished Jul 12 04:42:06 PM PDT 24
Peak memory 217512 kb
Host smart-c2d3ce61-3108-4614-99d9-61442efb048d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528186194 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2528186194
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3764645461
Short name T120
Test name
Test status
Simulation time 17142230 ps
CPU time 1.03 seconds
Started Jul 12 04:42:11 PM PDT 24
Finished Jul 12 04:42:14 PM PDT 24
Peak memory 209052 kb
Host smart-d65fa24c-d4ca-4dbb-a5cf-58a981a93fce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764645461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3764645461
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.871772745
Short name T947
Test name
Test status
Simulation time 81592797 ps
CPU time 1.12 seconds
Started Jul 12 04:42:00 PM PDT 24
Finished Jul 12 04:42:03 PM PDT 24
Peak memory 208936 kb
Host smart-4b5bc06a-5034-4f0f-bec4-7b75ad5a124a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871772745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.871772745
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.884030914
Short name T894
Test name
Test status
Simulation time 519030255 ps
CPU time 12.34 seconds
Started Jul 12 04:41:59 PM PDT 24
Finished Jul 12 04:42:13 PM PDT 24
Peak memory 216884 kb
Host smart-c9e4e3fc-0629-4abc-85a6-41dba83976dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884030914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.884030914
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2884304395
Short name T915
Test name
Test status
Simulation time 5139227963 ps
CPU time 24.82 seconds
Started Jul 12 04:42:01 PM PDT 24
Finished Jul 12 04:42:27 PM PDT 24
Peak memory 209236 kb
Host smart-d9b5c3bc-09b5-43f9-b355-6c24f4026e6c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884304395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2884304395
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2682083379
Short name T872
Test name
Test status
Simulation time 82420090 ps
CPU time 1.68 seconds
Started Jul 12 04:41:58 PM PDT 24
Finished Jul 12 04:42:02 PM PDT 24
Peak memory 210600 kb
Host smart-9a07295b-4305-411b-93c9-644f6a44426c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682083379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2682083379
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4214190149
Short name T940
Test name
Test status
Simulation time 168045492 ps
CPU time 2.93 seconds
Started Jul 12 04:42:00 PM PDT 24
Finished Jul 12 04:42:05 PM PDT 24
Peak memory 218896 kb
Host smart-5b6cb604-2afb-4f29-84a3-c09415b4a961
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421419
0149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4214190149
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1095549889
Short name T916
Test name
Test status
Simulation time 67477604 ps
CPU time 2.32 seconds
Started Jul 12 04:41:59 PM PDT 24
Finished Jul 12 04:42:04 PM PDT 24
Peak memory 209164 kb
Host smart-fce0ba37-bb2a-45e4-bda3-b606d4de94f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095549889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1095549889
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3733884677
Short name T116
Test name
Test status
Simulation time 135935256 ps
CPU time 1.33 seconds
Started Jul 12 04:41:58 PM PDT 24
Finished Jul 12 04:42:01 PM PDT 24
Peak memory 209192 kb
Host smart-61f6e9e9-a66b-4702-81e2-d63fe46ff0a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733884677 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3733884677
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.4224641973
Short name T966
Test name
Test status
Simulation time 28183366 ps
CPU time 1.05 seconds
Started Jul 12 04:42:06 PM PDT 24
Finished Jul 12 04:42:08 PM PDT 24
Peak memory 209188 kb
Host smart-838b5e79-8d1c-496e-8fd3-eeddf1a49064
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224641973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.4224641973
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3190485365
Short name T908
Test name
Test status
Simulation time 176985892 ps
CPU time 2.95 seconds
Started Jul 12 04:41:58 PM PDT 24
Finished Jul 12 04:42:02 PM PDT 24
Peak memory 217952 kb
Host smart-12f0ba34-c67e-47b9-b6fc-eabf6e0b782b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190485365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3190485365
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4013551172
Short name T954
Test name
Test status
Simulation time 26648620 ps
CPU time 2.05 seconds
Started Jul 12 04:42:30 PM PDT 24
Finished Jul 12 04:42:33 PM PDT 24
Peak memory 219704 kb
Host smart-ea8e1430-92b9-45c5-bd88-fd276a495d88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013551172 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.4013551172
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1634485312
Short name T937
Test name
Test status
Simulation time 13192873 ps
CPU time 1.03 seconds
Started Jul 12 04:42:32 PM PDT 24
Finished Jul 12 04:42:35 PM PDT 24
Peak memory 209120 kb
Host smart-c4e66b93-021a-4473-aae1-dd1608f2505b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634485312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1634485312
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.761669410
Short name T971
Test name
Test status
Simulation time 26822966 ps
CPU time 1.04 seconds
Started Jul 12 04:42:32 PM PDT 24
Finished Jul 12 04:42:35 PM PDT 24
Peak memory 209236 kb
Host smart-d3075724-2f00-4c1d-ab0a-89f4b77b89fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761669410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.761669410
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2182339581
Short name T110
Test name
Test status
Simulation time 54393926 ps
CPU time 2.55 seconds
Started Jul 12 04:42:29 PM PDT 24
Finished Jul 12 04:42:34 PM PDT 24
Peak memory 217392 kb
Host smart-ccdc7cb2-4bf5-4276-a6cc-52f07dcbadfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182339581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2182339581
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3208323804
Short name T986
Test name
Test status
Simulation time 155388106 ps
CPU time 1.14 seconds
Started Jul 12 04:42:35 PM PDT 24
Finished Jul 12 04:42:37 PM PDT 24
Peak memory 221752 kb
Host smart-289df2db-f951-4030-bc22-20a3c914609a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208323804 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3208323804
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1711450022
Short name T957
Test name
Test status
Simulation time 20933693 ps
CPU time 1.02 seconds
Started Jul 12 04:42:31 PM PDT 24
Finished Jul 12 04:42:34 PM PDT 24
Peak memory 209232 kb
Host smart-fc4c3fbb-43c6-4659-99a9-57962938b09e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711450022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1711450022
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1543863569
Short name T188
Test name
Test status
Simulation time 41435543 ps
CPU time 1.27 seconds
Started Jul 12 04:42:30 PM PDT 24
Finished Jul 12 04:42:33 PM PDT 24
Peak memory 209144 kb
Host smart-8fd9f03c-20f8-4518-9075-5999987bf4de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543863569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1543863569
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.710396737
Short name T976
Test name
Test status
Simulation time 129890655 ps
CPU time 2.01 seconds
Started Jul 12 04:42:30 PM PDT 24
Finished Jul 12 04:42:34 PM PDT 24
Peak memory 217368 kb
Host smart-e41c063a-dcbc-4ab1-bd2e-9483ca183105
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710396737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.710396737
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.865651482
Short name T114
Test name
Test status
Simulation time 103835743 ps
CPU time 2.96 seconds
Started Jul 12 04:42:32 PM PDT 24
Finished Jul 12 04:42:37 PM PDT 24
Peak memory 217268 kb
Host smart-0dc0790d-19fd-41c9-ba70-777aebdeb958
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865651482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.865651482
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3751173047
Short name T121
Test name
Test status
Simulation time 43868314 ps
CPU time 1.03 seconds
Started Jul 12 04:42:31 PM PDT 24
Finished Jul 12 04:42:34 PM PDT 24
Peak memory 217496 kb
Host smart-f83c0671-030c-4f7d-93ef-db41d75200e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751173047 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3751173047
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.255442370
Short name T177
Test name
Test status
Simulation time 20800116 ps
CPU time 0.97 seconds
Started Jul 12 04:42:30 PM PDT 24
Finished Jul 12 04:42:33 PM PDT 24
Peak memory 209224 kb
Host smart-8204e1d4-2cdd-4f4d-be0d-a4a0fd588c84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255442370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.255442370
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.329270838
Short name T920
Test name
Test status
Simulation time 29457741 ps
CPU time 1.1 seconds
Started Jul 12 04:42:29 PM PDT 24
Finished Jul 12 04:42:32 PM PDT 24
Peak memory 217376 kb
Host smart-5d12d796-5872-484d-a174-264dd5cec252
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329270838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.329270838
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3114083547
Short name T963
Test name
Test status
Simulation time 62611488 ps
CPU time 2.7 seconds
Started Jul 12 04:42:29 PM PDT 24
Finished Jul 12 04:42:34 PM PDT 24
Peak memory 217456 kb
Host smart-4690f203-5396-4384-8da1-572111f5c6b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114083547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3114083547
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3633142616
Short name T982
Test name
Test status
Simulation time 22478701 ps
CPU time 1.43 seconds
Started Jul 12 04:42:37 PM PDT 24
Finished Jul 12 04:42:40 PM PDT 24
Peak memory 217476 kb
Host smart-545a114b-d029-464e-ab43-c04daeeb52fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633142616 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3633142616
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3646367397
Short name T893
Test name
Test status
Simulation time 15055655 ps
CPU time 0.94 seconds
Started Jul 12 04:42:29 PM PDT 24
Finished Jul 12 04:42:32 PM PDT 24
Peak memory 208924 kb
Host smart-7822fa55-4653-4ae1-91cb-5d240bfda7d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646367397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3646367397
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3605017470
Short name T969
Test name
Test status
Simulation time 24065962 ps
CPU time 1.53 seconds
Started Jul 12 04:42:36 PM PDT 24
Finished Jul 12 04:42:38 PM PDT 24
Peak memory 211388 kb
Host smart-ec6b9aa8-84c6-4ab6-9700-2a6c39813e94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605017470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3605017470
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.253537290
Short name T909
Test name
Test status
Simulation time 28096685 ps
CPU time 1.74 seconds
Started Jul 12 04:42:31 PM PDT 24
Finished Jul 12 04:42:34 PM PDT 24
Peak memory 217428 kb
Host smart-bc784e1f-a45d-4398-9380-92b09686deac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253537290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.253537290
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.335030546
Short name T119
Test name
Test status
Simulation time 30434672 ps
CPU time 2.28 seconds
Started Jul 12 04:42:37 PM PDT 24
Finished Jul 12 04:42:41 PM PDT 24
Peak memory 219300 kb
Host smart-fbd5e29a-dcf1-4b17-b054-fffcb623baf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335030546 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.335030546
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.353518047
Short name T175
Test name
Test status
Simulation time 51600481 ps
CPU time 0.96 seconds
Started Jul 12 04:42:38 PM PDT 24
Finished Jul 12 04:42:40 PM PDT 24
Peak memory 209112 kb
Host smart-b6bf164b-b1ef-44ae-a414-535a42289b34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353518047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.353518047
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2920219665
Short name T958
Test name
Test status
Simulation time 36230472 ps
CPU time 1.17 seconds
Started Jul 12 04:42:34 PM PDT 24
Finished Jul 12 04:42:36 PM PDT 24
Peak memory 211408 kb
Host smart-493d34e1-f330-4dec-a190-4558e5f1dd47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920219665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2920219665
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2606666275
Short name T109
Test name
Test status
Simulation time 67624114 ps
CPU time 1.75 seconds
Started Jul 12 04:42:36 PM PDT 24
Finished Jul 12 04:42:39 PM PDT 24
Peak memory 218496 kb
Host smart-6279ba11-c2f7-453b-a959-c497680e9ee7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606666275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2606666275
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.350319689
Short name T932
Test name
Test status
Simulation time 62975040 ps
CPU time 1.95 seconds
Started Jul 12 04:42:35 PM PDT 24
Finished Jul 12 04:42:39 PM PDT 24
Peak memory 221616 kb
Host smart-2acebb67-8f20-4dd9-8744-7caa6eb33827
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350319689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.350319689
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3464276401
Short name T923
Test name
Test status
Simulation time 29672855 ps
CPU time 1.75 seconds
Started Jul 12 04:42:36 PM PDT 24
Finished Jul 12 04:42:40 PM PDT 24
Peak memory 217584 kb
Host smart-ec7fbbb4-ea20-4d83-971b-154f678d32b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464276401 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3464276401
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.796007935
Short name T911
Test name
Test status
Simulation time 36291985 ps
CPU time 1.02 seconds
Started Jul 12 04:42:43 PM PDT 24
Finished Jul 12 04:42:46 PM PDT 24
Peak memory 209272 kb
Host smart-fbacd3a3-3ea3-48d3-a5b6-55f4617dcfc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796007935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.796007935
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.546579908
Short name T990
Test name
Test status
Simulation time 23948235 ps
CPU time 1.31 seconds
Started Jul 12 04:42:37 PM PDT 24
Finished Jul 12 04:42:40 PM PDT 24
Peak memory 217324 kb
Host smart-a50b350a-ddff-4e3d-a8c4-d93e042495fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546579908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.546579908
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4114778576
Short name T973
Test name
Test status
Simulation time 30512582 ps
CPU time 2.16 seconds
Started Jul 12 04:42:39 PM PDT 24
Finished Jul 12 04:42:43 PM PDT 24
Peak memory 217320 kb
Host smart-37b22ea3-6a9a-445a-9af1-5847d7ed0bd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114778576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.4114778576
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.705031633
Short name T123
Test name
Test status
Simulation time 62023317 ps
CPU time 2.2 seconds
Started Jul 12 04:42:33 PM PDT 24
Finished Jul 12 04:42:37 PM PDT 24
Peak memory 217440 kb
Host smart-a40f2599-1697-4bd0-b811-142942d43425
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705031633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_
err.705031633
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2231560479
Short name T913
Test name
Test status
Simulation time 31199376 ps
CPU time 1.32 seconds
Started Jul 12 04:42:43 PM PDT 24
Finished Jul 12 04:42:46 PM PDT 24
Peak memory 221884 kb
Host smart-825f2a6a-1ed2-43d6-9c6e-1ffe2df02b62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231560479 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2231560479
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.4174087477
Short name T176
Test name
Test status
Simulation time 46585882 ps
CPU time 0.99 seconds
Started Jul 12 04:42:34 PM PDT 24
Finished Jul 12 04:42:36 PM PDT 24
Peak memory 209192 kb
Host smart-20ff6903-7315-4102-8ce1-a770fae15548
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174087477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.4174087477
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3261277311
Short name T898
Test name
Test status
Simulation time 36590655 ps
CPU time 1.13 seconds
Started Jul 12 04:42:38 PM PDT 24
Finished Jul 12 04:42:40 PM PDT 24
Peak memory 217344 kb
Host smart-b56f3eea-ef84-44e5-8b82-bf131ded25b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261277311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3261277311
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2824754363
Short name T917
Test name
Test status
Simulation time 169309175 ps
CPU time 1.8 seconds
Started Jul 12 04:42:36 PM PDT 24
Finished Jul 12 04:42:40 PM PDT 24
Peak memory 217552 kb
Host smart-92ddbed2-0367-432a-9064-d8bcb8e18c1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824754363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2824754363
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3568652366
Short name T965
Test name
Test status
Simulation time 24790810 ps
CPU time 1.64 seconds
Started Jul 12 04:42:36 PM PDT 24
Finished Jul 12 04:42:39 PM PDT 24
Peak memory 217480 kb
Host smart-d8550c9e-1475-4f0f-8a50-fa67ac59a2a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568652366 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3568652366
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1976903139
Short name T884
Test name
Test status
Simulation time 40793179 ps
CPU time 1.02 seconds
Started Jul 12 04:42:37 PM PDT 24
Finished Jul 12 04:42:40 PM PDT 24
Peak memory 209000 kb
Host smart-42842f6a-38a8-4c5a-a718-70d15599a709
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976903139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1976903139
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3851405379
Short name T904
Test name
Test status
Simulation time 51664506 ps
CPU time 1.17 seconds
Started Jul 12 04:42:40 PM PDT 24
Finished Jul 12 04:42:42 PM PDT 24
Peak memory 209148 kb
Host smart-07102b25-4dfc-4cec-80f9-f1a7dc257385
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851405379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3851405379
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.226425826
Short name T148
Test name
Test status
Simulation time 27840401 ps
CPU time 1.37 seconds
Started Jul 12 04:42:38 PM PDT 24
Finished Jul 12 04:42:41 PM PDT 24
Peak memory 218668 kb
Host smart-c40e890e-3f1a-4c1f-9701-b830bc2c4e71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226425826 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.226425826
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.362801953
Short name T890
Test name
Test status
Simulation time 18101661 ps
CPU time 0.95 seconds
Started Jul 12 04:42:39 PM PDT 24
Finished Jul 12 04:42:42 PM PDT 24
Peak memory 209144 kb
Host smart-ea173922-9b46-4b75-be9d-5492e77ecf76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362801953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.362801953
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3747939197
Short name T186
Test name
Test status
Simulation time 46146179 ps
CPU time 0.99 seconds
Started Jul 12 04:42:35 PM PDT 24
Finished Jul 12 04:42:38 PM PDT 24
Peak memory 209180 kb
Host smart-66936ecd-648d-4308-a764-335dfc1050df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747939197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3747939197
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.801991362
Short name T943
Test name
Test status
Simulation time 57838433 ps
CPU time 2.63 seconds
Started Jul 12 04:42:38 PM PDT 24
Finished Jul 12 04:42:42 PM PDT 24
Peak memory 217292 kb
Host smart-dbed6b3d-2220-4e0c-afa9-c9a3eed357c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801991362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.801991362
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1757856466
Short name T125
Test name
Test status
Simulation time 376692686 ps
CPU time 2.28 seconds
Started Jul 12 04:42:39 PM PDT 24
Finished Jul 12 04:42:43 PM PDT 24
Peak memory 222080 kb
Host smart-02ed16ce-dbec-4b4a-8d34-59ec2cd8a5fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757856466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1757856466
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2352176917
Short name T871
Test name
Test status
Simulation time 57070041 ps
CPU time 1.01 seconds
Started Jul 12 04:42:35 PM PDT 24
Finished Jul 12 04:42:37 PM PDT 24
Peak memory 217508 kb
Host smart-fffdd171-0e42-4cbb-b4a7-c63edd13404a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352176917 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2352176917
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1663077992
Short name T883
Test name
Test status
Simulation time 16073082 ps
CPU time 1.05 seconds
Started Jul 12 04:42:37 PM PDT 24
Finished Jul 12 04:42:39 PM PDT 24
Peak memory 208952 kb
Host smart-a9d5ae4e-cc83-465f-add8-23e34c2e4310
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663077992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1663077992
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.4120383377
Short name T993
Test name
Test status
Simulation time 16628954 ps
CPU time 1.01 seconds
Started Jul 12 04:42:35 PM PDT 24
Finished Jul 12 04:42:37 PM PDT 24
Peak memory 209136 kb
Host smart-51f6bc87-ea48-4d4b-81bd-39135a93d1f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120383377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.4120383377
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.461981882
Short name T956
Test name
Test status
Simulation time 258058428 ps
CPU time 2.11 seconds
Started Jul 12 04:42:35 PM PDT 24
Finished Jul 12 04:42:38 PM PDT 24
Peak memory 217872 kb
Host smart-3c9c5d47-b12e-4d12-93e5-92feaa70e391
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461981882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.461981882
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.751039426
Short name T200
Test name
Test status
Simulation time 68020494 ps
CPU time 2.07 seconds
Started Jul 12 04:42:42 PM PDT 24
Finished Jul 12 04:42:46 PM PDT 24
Peak memory 221796 kb
Host smart-1c136bc4-cb3a-4ec8-b0a0-f33b559b7a51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751039426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.751039426
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.332173200
Short name T905
Test name
Test status
Simulation time 44708577 ps
CPU time 0.97 seconds
Started Jul 12 04:42:06 PM PDT 24
Finished Jul 12 04:42:08 PM PDT 24
Peak memory 209420 kb
Host smart-87f50fb5-e51b-4642-ac94-505c4a5453b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332173200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.332173200
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.551172269
Short name T880
Test name
Test status
Simulation time 206114892 ps
CPU time 2.04 seconds
Started Jul 12 04:42:06 PM PDT 24
Finished Jul 12 04:42:09 PM PDT 24
Peak memory 209212 kb
Host smart-7b37fcfd-c2e5-4514-bb80-474c04f11bdb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551172269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash
.551172269
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.4082958949
Short name T183
Test name
Test status
Simulation time 20964557 ps
CPU time 1.28 seconds
Started Jul 12 04:42:08 PM PDT 24
Finished Jul 12 04:42:10 PM PDT 24
Peak memory 209976 kb
Host smart-a83c0845-491a-47fd-a740-248de491bbcd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082958949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.4082958949
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.413683979
Short name T903
Test name
Test status
Simulation time 22797210 ps
CPU time 1.09 seconds
Started Jul 12 04:42:08 PM PDT 24
Finished Jul 12 04:42:10 PM PDT 24
Peak memory 218576 kb
Host smart-c6aa520d-1cb2-4901-acfd-058ba6f6ff87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413683979 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.413683979
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1241285541
Short name T173
Test name
Test status
Simulation time 12871773 ps
CPU time 0.97 seconds
Started Jul 12 04:42:11 PM PDT 24
Finished Jul 12 04:42:14 PM PDT 24
Peak memory 209088 kb
Host smart-0e068715-2998-4919-980b-9b6be728f5f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241285541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1241285541
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2060902775
Short name T952
Test name
Test status
Simulation time 228354607 ps
CPU time 1.31 seconds
Started Jul 12 04:42:11 PM PDT 24
Finished Jul 12 04:42:14 PM PDT 24
Peak memory 208948 kb
Host smart-297dfe0d-a639-42ab-b258-500b0de67df8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060902775 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2060902775
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2879694321
Short name T892
Test name
Test status
Simulation time 1485943240 ps
CPU time 8.29 seconds
Started Jul 12 04:42:06 PM PDT 24
Finished Jul 12 04:42:15 PM PDT 24
Peak memory 209064 kb
Host smart-87da78b8-129b-4f3f-aee2-f610958f3b7e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879694321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2879694321
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2113709778
Short name T946
Test name
Test status
Simulation time 697160365 ps
CPU time 7.26 seconds
Started Jul 12 04:42:12 PM PDT 24
Finished Jul 12 04:42:22 PM PDT 24
Peak memory 208648 kb
Host smart-e0c5b031-fb04-4a6a-a94d-5ac8a16262d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113709778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2113709778
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.230003086
Short name T985
Test name
Test status
Simulation time 149867748 ps
CPU time 2.39 seconds
Started Jul 12 04:42:05 PM PDT 24
Finished Jul 12 04:42:08 PM PDT 24
Peak memory 210684 kb
Host smart-be6d13c6-1ed5-43fb-a19f-0ce448d55e97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230003086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.230003086
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1858953477
Short name T978
Test name
Test status
Simulation time 379896463 ps
CPU time 3.14 seconds
Started Jul 12 04:42:10 PM PDT 24
Finished Jul 12 04:42:14 PM PDT 24
Peak memory 219060 kb
Host smart-b1519752-38b4-4210-be08-92dc52876954
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185895
3477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1858953477
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.319436076
Short name T989
Test name
Test status
Simulation time 123001896 ps
CPU time 1.03 seconds
Started Jul 12 04:42:05 PM PDT 24
Finished Jul 12 04:42:07 PM PDT 24
Peak memory 209136 kb
Host smart-ad1620cb-386a-4fa8-8677-08e90713501f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319436076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.319436076
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4241610915
Short name T936
Test name
Test status
Simulation time 34566494 ps
CPU time 1.1 seconds
Started Jul 12 04:42:05 PM PDT 24
Finished Jul 12 04:42:08 PM PDT 24
Peak memory 209116 kb
Host smart-7c78ee45-89b3-4791-afa3-956c4198dd7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241610915 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.4241610915
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.117701478
Short name T975
Test name
Test status
Simulation time 38745902 ps
CPU time 1.3 seconds
Started Jul 12 04:42:03 PM PDT 24
Finished Jul 12 04:42:06 PM PDT 24
Peak memory 209104 kb
Host smart-211a9e2d-1c8b-4551-a59a-aaf2aaa82a28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117701478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.117701478
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1749199095
Short name T988
Test name
Test status
Simulation time 52506695 ps
CPU time 2.3 seconds
Started Jul 12 04:42:05 PM PDT 24
Finished Jul 12 04:42:08 PM PDT 24
Peak memory 217436 kb
Host smart-73819814-96b8-4c72-b509-e935a4710763
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749199095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1749199095
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1105794380
Short name T178
Test name
Test status
Simulation time 285874749 ps
CPU time 1.29 seconds
Started Jul 12 04:42:12 PM PDT 24
Finished Jul 12 04:42:16 PM PDT 24
Peak memory 217712 kb
Host smart-3ec2e76a-9be2-44f5-931f-4a621d6fb538
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105794380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1105794380
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2705230869
Short name T931
Test name
Test status
Simulation time 190835598 ps
CPU time 1.36 seconds
Started Jul 12 04:42:11 PM PDT 24
Finished Jul 12 04:42:14 PM PDT 24
Peak memory 209136 kb
Host smart-5c89d046-791e-4ad6-af49-ecd656de4d3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705230869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2705230869
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.768826407
Short name T886
Test name
Test status
Simulation time 17149494 ps
CPU time 0.94 seconds
Started Jul 12 04:42:14 PM PDT 24
Finished Jul 12 04:42:17 PM PDT 24
Peak memory 209812 kb
Host smart-b91254d0-cd25-4403-ac56-b79f1706adb3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768826407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_reset
.768826407
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.795423973
Short name T126
Test name
Test status
Simulation time 142150297 ps
CPU time 1.8 seconds
Started Jul 12 04:42:13 PM PDT 24
Finished Jul 12 04:42:17 PM PDT 24
Peak memory 219540 kb
Host smart-ed60be2a-68c3-49d2-b1c1-92f83204ba9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795423973 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.795423973
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1080974417
Short name T928
Test name
Test status
Simulation time 45613908 ps
CPU time 0.95 seconds
Started Jul 12 04:42:14 PM PDT 24
Finished Jul 12 04:42:17 PM PDT 24
Peak memory 208908 kb
Host smart-a6fe24a4-d13c-4325-9795-70acc9027e15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080974417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1080974417
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3474733879
Short name T929
Test name
Test status
Simulation time 46850216 ps
CPU time 1.39 seconds
Started Jul 12 04:42:11 PM PDT 24
Finished Jul 12 04:42:15 PM PDT 24
Peak memory 208948 kb
Host smart-9551c567-0e79-4c67-a19b-f5648fa62ea3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474733879 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3474733879
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1691874181
Short name T914
Test name
Test status
Simulation time 1176646483 ps
CPU time 25.81 seconds
Started Jul 12 04:42:05 PM PDT 24
Finished Jul 12 04:42:32 PM PDT 24
Peak memory 209188 kb
Host smart-cda329f6-6102-451a-bc96-818320037089
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691874181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1691874181
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3621875169
Short name T984
Test name
Test status
Simulation time 4393396595 ps
CPU time 27.28 seconds
Started Jul 12 04:42:06 PM PDT 24
Finished Jul 12 04:42:34 PM PDT 24
Peak memory 209172 kb
Host smart-02de5274-94d8-4b41-bb67-ad7a82d1ac15
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621875169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3621875169
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.780869228
Short name T942
Test name
Test status
Simulation time 640016163 ps
CPU time 1.83 seconds
Started Jul 12 04:42:05 PM PDT 24
Finished Jul 12 04:42:08 PM PDT 24
Peak memory 210700 kb
Host smart-917089a3-3e58-45ab-a447-a54233997b1e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780869228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.780869228
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2804826729
Short name T881
Test name
Test status
Simulation time 103158629 ps
CPU time 2.04 seconds
Started Jul 12 04:42:11 PM PDT 24
Finished Jul 12 04:42:16 PM PDT 24
Peak memory 218404 kb
Host smart-0db15286-5898-4d32-bf98-c55afd4af59b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280482
6729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2804826729
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3595398437
Short name T927
Test name
Test status
Simulation time 64660257 ps
CPU time 1.29 seconds
Started Jul 12 04:42:05 PM PDT 24
Finished Jul 12 04:42:07 PM PDT 24
Peak memory 209104 kb
Host smart-b68b3d5d-d8d9-4e87-b819-0fa5b9bc3e56
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595398437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3595398437
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1986261040
Short name T191
Test name
Test status
Simulation time 22042235 ps
CPU time 1.28 seconds
Started Jul 12 04:42:12 PM PDT 24
Finished Jul 12 04:42:16 PM PDT 24
Peak memory 209072 kb
Host smart-b45b0c1a-b73c-4e3e-8899-17608955f029
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986261040 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1986261040
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2272445511
Short name T924
Test name
Test status
Simulation time 30330416 ps
CPU time 1.45 seconds
Started Jul 12 04:42:14 PM PDT 24
Finished Jul 12 04:42:17 PM PDT 24
Peak memory 209200 kb
Host smart-34a72d66-1125-4df3-ae0d-884c1ab1b2a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272445511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.2272445511
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2920719045
Short name T968
Test name
Test status
Simulation time 136803030 ps
CPU time 5.22 seconds
Started Jul 12 04:42:11 PM PDT 24
Finished Jul 12 04:42:19 PM PDT 24
Peak memory 217360 kb
Host smart-fa14f315-3e31-4622-a384-4ddb8ca8a631
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920719045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2920719045
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2377681422
Short name T919
Test name
Test status
Simulation time 21379875 ps
CPU time 1.03 seconds
Started Jul 12 04:42:13 PM PDT 24
Finished Jul 12 04:42:16 PM PDT 24
Peak memory 209212 kb
Host smart-c31df5aa-6712-4552-8421-4c04cddd2a99
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377681422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2377681422
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.616621404
Short name T912
Test name
Test status
Simulation time 85438875 ps
CPU time 1.47 seconds
Started Jul 12 04:42:12 PM PDT 24
Finished Jul 12 04:42:16 PM PDT 24
Peak memory 209120 kb
Host smart-eef8fd4a-ff8d-45f4-94f6-96cd68685e19
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616621404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.616621404
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2696182471
Short name T180
Test name
Test status
Simulation time 35321329 ps
CPU time 0.94 seconds
Started Jul 12 04:42:14 PM PDT 24
Finished Jul 12 04:42:16 PM PDT 24
Peak memory 209828 kb
Host smart-8d1e9f87-3c3e-44b7-9fc6-2d9ee88f41c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696182471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2696182471
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3610418724
Short name T111
Test name
Test status
Simulation time 22263923 ps
CPU time 1.08 seconds
Started Jul 12 04:42:20 PM PDT 24
Finished Jul 12 04:42:22 PM PDT 24
Peak memory 218424 kb
Host smart-40573b22-566d-4085-9bde-14b08e7fc4e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610418724 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3610418724
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2178497844
Short name T945
Test name
Test status
Simulation time 1514763941 ps
CPU time 1.46 seconds
Started Jul 12 04:42:13 PM PDT 24
Finished Jul 12 04:42:17 PM PDT 24
Peak memory 208524 kb
Host smart-ab4700bc-c1a4-4c0e-976a-2114998de675
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178497844 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2178497844
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3097134031
Short name T870
Test name
Test status
Simulation time 998138954 ps
CPU time 4.45 seconds
Started Jul 12 04:42:12 PM PDT 24
Finished Jul 12 04:42:19 PM PDT 24
Peak memory 216888 kb
Host smart-4e99e366-27d9-418a-ac12-7689a248d113
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097134031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3097134031
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2538855621
Short name T888
Test name
Test status
Simulation time 3751962367 ps
CPU time 13.63 seconds
Started Jul 12 04:49:07 PM PDT 24
Finished Jul 12 04:49:21 PM PDT 24
Peak memory 209248 kb
Host smart-edc43fbf-cc6e-4b34-b358-7c9292eb8a9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538855621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2538855621
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2353252787
Short name T875
Test name
Test status
Simulation time 338630711 ps
CPU time 1.65 seconds
Started Jul 12 04:42:12 PM PDT 24
Finished Jul 12 04:42:16 PM PDT 24
Peak memory 210768 kb
Host smart-fc50db1b-3875-415d-b5ad-385287ff0d65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353252787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2353252787
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.261481168
Short name T991
Test name
Test status
Simulation time 180360392 ps
CPU time 4.75 seconds
Started Jul 12 04:42:12 PM PDT 24
Finished Jul 12 04:42:19 PM PDT 24
Peak memory 218044 kb
Host smart-a8a7996a-aadc-4aab-b3b4-380cbee24d8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261481
168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.261481168
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3053502215
Short name T141
Test name
Test status
Simulation time 131636124 ps
CPU time 1.16 seconds
Started Jul 12 04:42:11 PM PDT 24
Finished Jul 12 04:42:15 PM PDT 24
Peak memory 209080 kb
Host smart-817251d0-934c-4fe9-8d64-3a29d1fdf3a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053502215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3053502215
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3506086535
Short name T992
Test name
Test status
Simulation time 198288231 ps
CPU time 1.49 seconds
Started Jul 12 04:42:11 PM PDT 24
Finished Jul 12 04:42:14 PM PDT 24
Peak memory 211320 kb
Host smart-10cbc41e-f5f7-48fa-9bf4-8d5ae209f7d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506086535 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3506086535
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1663906388
Short name T910
Test name
Test status
Simulation time 50369191 ps
CPU time 1.29 seconds
Started Jul 12 04:42:16 PM PDT 24
Finished Jul 12 04:42:19 PM PDT 24
Peak memory 209196 kb
Host smart-33f16c87-d806-436d-9f57-ff93f6a36509
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663906388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1663906388
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2886055729
Short name T953
Test name
Test status
Simulation time 85702065 ps
CPU time 1.71 seconds
Started Jul 12 04:42:11 PM PDT 24
Finished Jul 12 04:42:15 PM PDT 24
Peak memory 217504 kb
Host smart-5107363c-b1c6-451b-ab6a-1639e699bbb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886055729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2886055729
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4273380740
Short name T960
Test name
Test status
Simulation time 126165508 ps
CPU time 2.02 seconds
Started Jul 12 04:42:10 PM PDT 24
Finished Jul 12 04:42:14 PM PDT 24
Peak memory 221904 kb
Host smart-1833d2b0-1a7b-4f7c-8d76-9bcf428fd5b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273380740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.4273380740
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1167144860
Short name T118
Test name
Test status
Simulation time 26922181 ps
CPU time 1.27 seconds
Started Jul 12 04:42:19 PM PDT 24
Finished Jul 12 04:42:22 PM PDT 24
Peak memory 218500 kb
Host smart-00e5fc10-76b3-4234-a9f2-78ed29f677b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167144860 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1167144860
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1301749637
Short name T925
Test name
Test status
Simulation time 116896311 ps
CPU time 0.87 seconds
Started Jul 12 04:42:18 PM PDT 24
Finished Jul 12 04:42:21 PM PDT 24
Peak memory 209024 kb
Host smart-47adf7a0-3f43-488c-9ec2-938f7f4aa729
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301749637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1301749637
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2101427135
Short name T930
Test name
Test status
Simulation time 89515075 ps
CPU time 0.97 seconds
Started Jul 12 04:42:22 PM PDT 24
Finished Jul 12 04:42:24 PM PDT 24
Peak memory 207792 kb
Host smart-f5cc5d91-8105-4782-ba2c-3c0a461fff43
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101427135 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2101427135
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2745073489
Short name T879
Test name
Test status
Simulation time 1798839276 ps
CPU time 4.05 seconds
Started Jul 12 04:42:18 PM PDT 24
Finished Jul 12 04:42:24 PM PDT 24
Peak memory 216844 kb
Host smart-807aad69-267a-4f6e-8de4-c59c742191e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745073489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2745073489
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3266678285
Short name T873
Test name
Test status
Simulation time 1732639592 ps
CPU time 5.6 seconds
Started Jul 12 04:42:19 PM PDT 24
Finished Jul 12 04:42:26 PM PDT 24
Peak memory 209036 kb
Host smart-015b7e76-cf84-487f-a7db-2769c80fbddc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266678285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3266678285
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3782776968
Short name T897
Test name
Test status
Simulation time 170628975 ps
CPU time 2.76 seconds
Started Jul 12 04:42:19 PM PDT 24
Finished Jul 12 04:42:24 PM PDT 24
Peak memory 210828 kb
Host smart-16f5e5e8-d28b-4fc5-a3a9-d9142ce69c2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782776968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3782776968
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2638239670
Short name T981
Test name
Test status
Simulation time 175833239 ps
CPU time 2.88 seconds
Started Jul 12 04:42:21 PM PDT 24
Finished Jul 12 04:42:25 PM PDT 24
Peak memory 218988 kb
Host smart-3cc195db-04e0-49fc-a3fc-4b07aad08afc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263823
9670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2638239670
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3198040006
Short name T906
Test name
Test status
Simulation time 54993418 ps
CPU time 2.07 seconds
Started Jul 12 04:42:19 PM PDT 24
Finished Jul 12 04:42:23 PM PDT 24
Peak memory 217376 kb
Host smart-8c60fb5f-c72f-44ef-87b0-2c5b82577490
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198040006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3198040006
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2171290855
Short name T926
Test name
Test status
Simulation time 49215690 ps
CPU time 1.58 seconds
Started Jul 12 04:42:20 PM PDT 24
Finished Jul 12 04:42:24 PM PDT 24
Peak memory 217400 kb
Host smart-65f19fa2-fc09-4096-853b-21f37a4b7262
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171290855 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2171290855
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.584932955
Short name T885
Test name
Test status
Simulation time 179344305 ps
CPU time 1.55 seconds
Started Jul 12 04:42:18 PM PDT 24
Finished Jul 12 04:42:22 PM PDT 24
Peak memory 217340 kb
Host smart-3f5dbc0c-f973-49f9-81ce-5b044827fbb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584932955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.584932955
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.21798081
Short name T900
Test name
Test status
Simulation time 32565523 ps
CPU time 2.44 seconds
Started Jul 12 04:42:19 PM PDT 24
Finished Jul 12 04:42:23 PM PDT 24
Peak memory 218828 kb
Host smart-a186e1fd-dfd3-4d2d-ad8c-614d71e2c9e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21798081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.21798081
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1604331051
Short name T941
Test name
Test status
Simulation time 42811959 ps
CPU time 1.19 seconds
Started Jul 12 04:42:22 PM PDT 24
Finished Jul 12 04:42:24 PM PDT 24
Peak memory 216744 kb
Host smart-6e4a3f6a-c9d0-4044-8a7a-c13a0d5ecfd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604331051 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1604331051
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1817907415
Short name T889
Test name
Test status
Simulation time 1232113488 ps
CPU time 2.16 seconds
Started Jul 12 04:42:19 PM PDT 24
Finished Jul 12 04:42:23 PM PDT 24
Peak memory 208996 kb
Host smart-eaad4f21-d431-4d71-843f-2b1acb8cfe12
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817907415 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1817907415
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3895382548
Short name T935
Test name
Test status
Simulation time 591064508 ps
CPU time 14.05 seconds
Started Jul 12 04:42:18 PM PDT 24
Finished Jul 12 04:42:34 PM PDT 24
Peak memory 209172 kb
Host smart-c1dfbd8c-c386-4613-9d81-9897e3c6c262
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895382548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3895382548
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2405173042
Short name T899
Test name
Test status
Simulation time 2234074449 ps
CPU time 13 seconds
Started Jul 12 04:42:18 PM PDT 24
Finished Jul 12 04:42:32 PM PDT 24
Peak memory 209072 kb
Host smart-2b1c21a1-76c3-4576-b043-368ec7d37661
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405173042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2405173042
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3978865920
Short name T949
Test name
Test status
Simulation time 704134556 ps
CPU time 2.85 seconds
Started Jul 12 04:42:18 PM PDT 24
Finished Jul 12 04:42:23 PM PDT 24
Peak memory 210604 kb
Host smart-38a78d2f-fe1a-4f42-bb6d-4a59fc837c40
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978865920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.3978865920
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.291257518
Short name T140
Test name
Test status
Simulation time 71681551 ps
CPU time 2.43 seconds
Started Jul 12 04:42:19 PM PDT 24
Finished Jul 12 04:42:23 PM PDT 24
Peak memory 217500 kb
Host smart-c289c65d-4a3c-4450-920c-e2ff5160a70e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291257
518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.291257518
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1534250746
Short name T961
Test name
Test status
Simulation time 256032859 ps
CPU time 3.68 seconds
Started Jul 12 04:42:20 PM PDT 24
Finished Jul 12 04:42:26 PM PDT 24
Peak memory 217536 kb
Host smart-cea62f36-29b6-4a85-94eb-6f356537d1b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534250746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1534250746
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2375997173
Short name T933
Test name
Test status
Simulation time 23985364 ps
CPU time 1.36 seconds
Started Jul 12 04:42:18 PM PDT 24
Finished Jul 12 04:42:21 PM PDT 24
Peak memory 209228 kb
Host smart-4b777149-e14d-4579-8621-632dd2ca9dfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375997173 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2375997173
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3128642476
Short name T895
Test name
Test status
Simulation time 17627103 ps
CPU time 1.26 seconds
Started Jul 12 04:42:19 PM PDT 24
Finished Jul 12 04:42:23 PM PDT 24
Peak memory 209316 kb
Host smart-70c1f514-8773-499e-a958-088fd5d81f85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128642476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3128642476
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.714183774
Short name T962
Test name
Test status
Simulation time 55528074 ps
CPU time 2.38 seconds
Started Jul 12 04:42:18 PM PDT 24
Finished Jul 12 04:42:22 PM PDT 24
Peak memory 217468 kb
Host smart-58f88ab9-9a2e-4478-a70f-96641a8d96db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714183774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.714183774
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1589932094
Short name T902
Test name
Test status
Simulation time 223688470 ps
CPU time 1.95 seconds
Started Jul 12 04:42:19 PM PDT 24
Finished Jul 12 04:42:23 PM PDT 24
Peak memory 221196 kb
Host smart-e586c03e-ba62-4e0a-ba88-11db9301fca2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589932094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1589932094
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3251545199
Short name T994
Test name
Test status
Simulation time 86352045 ps
CPU time 1.58 seconds
Started Jul 12 04:42:23 PM PDT 24
Finished Jul 12 04:42:25 PM PDT 24
Peak memory 222520 kb
Host smart-e6c35a96-aa27-44ed-bc7f-5a97b12e6f29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251545199 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3251545199
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.470544651
Short name T934
Test name
Test status
Simulation time 45982322 ps
CPU time 1.04 seconds
Started Jul 12 04:42:26 PM PDT 24
Finished Jul 12 04:42:28 PM PDT 24
Peak memory 209324 kb
Host smart-4afa8623-03e5-4932-97d6-0407efbabfc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470544651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.470544651
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2680076233
Short name T983
Test name
Test status
Simulation time 168751685 ps
CPU time 1.15 seconds
Started Jul 12 04:42:24 PM PDT 24
Finished Jul 12 04:42:27 PM PDT 24
Peak memory 208984 kb
Host smart-7cedd7f7-8c92-48ff-8cb8-38df331bdb41
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680076233 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2680076233
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3730977793
Short name T970
Test name
Test status
Simulation time 442511223 ps
CPU time 6.01 seconds
Started Jul 12 04:42:23 PM PDT 24
Finished Jul 12 04:42:30 PM PDT 24
Peak memory 216852 kb
Host smart-c9a209de-6598-4a41-bce9-5a65ef1a2248
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730977793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3730977793
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1016309912
Short name T882
Test name
Test status
Simulation time 1176559777 ps
CPU time 9.42 seconds
Started Jul 12 04:42:25 PM PDT 24
Finished Jul 12 04:42:36 PM PDT 24
Peak memory 209180 kb
Host smart-b8b9a528-d7d1-427d-8179-904f678e9ce9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016309912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1016309912
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1335315795
Short name T977
Test name
Test status
Simulation time 147772850 ps
CPU time 3.97 seconds
Started Jul 12 04:51:46 PM PDT 24
Finished Jul 12 04:51:51 PM PDT 24
Peak memory 210856 kb
Host smart-b8162aa3-417c-4c12-9e44-1badb6cd168e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335315795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1335315795
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3555734289
Short name T987
Test name
Test status
Simulation time 74550092 ps
CPU time 2.64 seconds
Started Jul 12 04:42:28 PM PDT 24
Finished Jul 12 04:42:31 PM PDT 24
Peak memory 223456 kb
Host smart-41c1d3c1-641f-46f3-9dfe-b082f7b1f4c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355573
4289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3555734289
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1482189972
Short name T117
Test name
Test status
Simulation time 127069008 ps
CPU time 2.26 seconds
Started Jul 12 04:42:25 PM PDT 24
Finished Jul 12 04:42:28 PM PDT 24
Peak memory 209192 kb
Host smart-07bdd5ba-1c11-4a8d-a451-bd7f27c168d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482189972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1482189972
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4091278383
Short name T901
Test name
Test status
Simulation time 429880192 ps
CPU time 1.75 seconds
Started Jul 12 04:42:29 PM PDT 24
Finished Jul 12 04:42:32 PM PDT 24
Peak memory 211408 kb
Host smart-ca920b2e-24d9-490d-beed-82e2cf77d026
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091278383 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.4091278383
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3137629316
Short name T922
Test name
Test status
Simulation time 188312769 ps
CPU time 1.64 seconds
Started Jul 12 04:42:25 PM PDT 24
Finished Jul 12 04:42:28 PM PDT 24
Peak memory 211280 kb
Host smart-7e122786-27d1-4298-8a21-5d157e6fdc28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137629316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3137629316
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2759213648
Short name T112
Test name
Test status
Simulation time 556395076 ps
CPU time 3.56 seconds
Started Jul 12 04:42:27 PM PDT 24
Finished Jul 12 04:42:32 PM PDT 24
Peak memory 218260 kb
Host smart-04243c5e-9e59-4da3-b910-dd55e40285cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759213648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2759213648
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2137256054
Short name T136
Test name
Test status
Simulation time 593824658 ps
CPU time 4.96 seconds
Started Jul 12 04:42:28 PM PDT 24
Finished Jul 12 04:42:34 PM PDT 24
Peak memory 217412 kb
Host smart-5dbc893b-6cc1-4a7f-bba5-4fb4d3272658
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137256054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2137256054
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3378301224
Short name T907
Test name
Test status
Simulation time 59077408 ps
CPU time 0.96 seconds
Started Jul 12 04:42:28 PM PDT 24
Finished Jul 12 04:42:30 PM PDT 24
Peak memory 217460 kb
Host smart-09fe259d-5db2-4d0b-995e-c9433586c439
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378301224 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3378301224
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3073106506
Short name T184
Test name
Test status
Simulation time 26725929 ps
CPU time 1.06 seconds
Started Jul 12 04:42:24 PM PDT 24
Finished Jul 12 04:42:27 PM PDT 24
Peak memory 209224 kb
Host smart-71586f47-99af-4ef2-a9cb-31bf38e9da72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073106506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3073106506
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2535487420
Short name T896
Test name
Test status
Simulation time 15248188 ps
CPU time 0.89 seconds
Started Jul 12 04:42:24 PM PDT 24
Finished Jul 12 04:42:26 PM PDT 24
Peak memory 209068 kb
Host smart-67914960-e2ee-43ea-b38c-e54d06a10327
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535487420 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2535487420
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1610130064
Short name T948
Test name
Test status
Simulation time 2477015058 ps
CPU time 15.75 seconds
Started Jul 12 04:42:33 PM PDT 24
Finished Jul 12 04:42:51 PM PDT 24
Peak memory 209124 kb
Host smart-c6a2bc22-63af-4e97-8b4d-000a55864f71
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610130064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1610130064
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.861724380
Short name T874
Test name
Test status
Simulation time 3746752458 ps
CPU time 11.66 seconds
Started Jul 12 04:42:25 PM PDT 24
Finished Jul 12 04:42:38 PM PDT 24
Peak memory 209224 kb
Host smart-32c26ae5-f2b7-4068-ad67-9a939bf76449
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861724380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.861724380
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.4209468282
Short name T951
Test name
Test status
Simulation time 148561151 ps
CPU time 2 seconds
Started Jul 12 04:42:25 PM PDT 24
Finished Jul 12 04:42:29 PM PDT 24
Peak memory 210468 kb
Host smart-424d7f29-c117-4d50-a766-d4c3a254f73a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209468282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.4209468282
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1133320850
Short name T891
Test name
Test status
Simulation time 58496627 ps
CPU time 2.13 seconds
Started Jul 12 04:42:24 PM PDT 24
Finished Jul 12 04:42:27 PM PDT 24
Peak memory 217592 kb
Host smart-89a97966-834e-459e-a7bf-046bb917a11f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113332
0850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1133320850
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3300824146
Short name T972
Test name
Test status
Simulation time 1486776989 ps
CPU time 1.38 seconds
Started Jul 12 04:42:25 PM PDT 24
Finished Jul 12 04:42:28 PM PDT 24
Peak memory 217108 kb
Host smart-36634bd3-5a4b-4e06-9814-3b58bc27b367
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300824146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3300824146
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1910390697
Short name T979
Test name
Test status
Simulation time 48736552 ps
CPU time 1.5 seconds
Started Jul 12 04:42:26 PM PDT 24
Finished Jul 12 04:42:29 PM PDT 24
Peak memory 209220 kb
Host smart-328c670c-9d31-4505-af65-9ceab24f81ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910390697 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1910390697
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.137521421
Short name T190
Test name
Test status
Simulation time 44824418 ps
CPU time 1.09 seconds
Started Jul 12 04:42:25 PM PDT 24
Finished Jul 12 04:42:27 PM PDT 24
Peak memory 217436 kb
Host smart-ced3fd15-5f0a-42f6-85af-d7a2675f5a1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137521421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.137521421
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1626278655
Short name T129
Test name
Test status
Simulation time 88406777 ps
CPU time 1.88 seconds
Started Jul 12 04:42:24 PM PDT 24
Finished Jul 12 04:42:27 PM PDT 24
Peak memory 217472 kb
Host smart-6078de75-da7c-44b3-8688-49de0f19f8f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626278655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1626278655
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.722592275
Short name T122
Test name
Test status
Simulation time 413846102 ps
CPU time 4.12 seconds
Started Jul 12 04:42:26 PM PDT 24
Finished Jul 12 04:42:32 PM PDT 24
Peak memory 217368 kb
Host smart-aea69152-07b2-4daf-807d-c2b1b7b5f2f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722592275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_e
rr.722592275
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.923523730
Short name T878
Test name
Test status
Simulation time 31125539 ps
CPU time 1.06 seconds
Started Jul 12 04:42:32 PM PDT 24
Finished Jul 12 04:42:35 PM PDT 24
Peak memory 217408 kb
Host smart-0fb4163d-9474-42c6-93ff-ec8907a818ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923523730 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.923523730
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.403245405
Short name T185
Test name
Test status
Simulation time 80481201 ps
CPU time 0.93 seconds
Started Jul 12 04:42:32 PM PDT 24
Finished Jul 12 04:42:35 PM PDT 24
Peak memory 209072 kb
Host smart-105c97d7-245b-44ce-9e15-d566fea3f153
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403245405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.403245405
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.4048370901
Short name T950
Test name
Test status
Simulation time 294865062 ps
CPU time 1.38 seconds
Started Jul 12 04:42:32 PM PDT 24
Finished Jul 12 04:42:35 PM PDT 24
Peak memory 208372 kb
Host smart-a9a92c98-7eb8-4d7e-99bd-6113872204e5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048370901 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.4048370901
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3042536520
Short name T955
Test name
Test status
Simulation time 443721318 ps
CPU time 9.84 seconds
Started Jul 12 04:42:24 PM PDT 24
Finished Jul 12 04:42:35 PM PDT 24
Peak memory 209028 kb
Host smart-bfdadcc3-d988-44ac-a34e-e2986f367aaa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042536520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3042536520
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.558958538
Short name T877
Test name
Test status
Simulation time 2204477673 ps
CPU time 17.58 seconds
Started Jul 12 04:42:26 PM PDT 24
Finished Jul 12 04:42:45 PM PDT 24
Peak memory 209324 kb
Host smart-4e4c7b6c-a078-4d96-83d8-5dddbd72f040
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558958538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.558958538
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.919143847
Short name T974
Test name
Test status
Simulation time 174443419 ps
CPU time 4.52 seconds
Started Jul 12 04:42:26 PM PDT 24
Finished Jul 12 04:42:32 PM PDT 24
Peak memory 217376 kb
Host smart-ddac94bd-30a7-403d-b877-86f2570dd916
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919143847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.919143847
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4206381775
Short name T964
Test name
Test status
Simulation time 1208906307 ps
CPU time 2.12 seconds
Started Jul 12 04:42:31 PM PDT 24
Finished Jul 12 04:42:35 PM PDT 24
Peak memory 218480 kb
Host smart-255f9385-7cbe-42e8-8017-ae7e422522cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420638
1775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4206381775
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1296628065
Short name T967
Test name
Test status
Simulation time 357894030 ps
CPU time 4.49 seconds
Started Jul 12 04:42:26 PM PDT 24
Finished Jul 12 04:42:32 PM PDT 24
Peak memory 209064 kb
Host smart-39b067dc-a9fb-4635-8b33-904b92beb0d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296628065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1296628065
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3199533858
Short name T187
Test name
Test status
Simulation time 118944786 ps
CPU time 1.37 seconds
Started Jul 12 04:42:23 PM PDT 24
Finished Jul 12 04:42:25 PM PDT 24
Peak memory 209252 kb
Host smart-12a76f3c-402d-4475-90d3-5dfb44f0a2c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199533858 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3199533858
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4007218645
Short name T137
Test name
Test status
Simulation time 42604547 ps
CPU time 1.46 seconds
Started Jul 12 04:42:29 PM PDT 24
Finished Jul 12 04:42:31 PM PDT 24
Peak memory 209220 kb
Host smart-03ad9932-da70-4b60-9cb5-5a312cfffe82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007218645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.4007218645
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1933186250
Short name T918
Test name
Test status
Simulation time 96468075 ps
CPU time 2.72 seconds
Started Jul 12 04:42:33 PM PDT 24
Finished Jul 12 04:42:37 PM PDT 24
Peak memory 217468 kb
Host smart-38aaac8b-7dfa-489a-aeaf-96b271144042
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933186250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1933186250
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1555266164
Short name T281
Test name
Test status
Simulation time 134217686 ps
CPU time 0.85 seconds
Started Jul 12 04:42:47 PM PDT 24
Finished Jul 12 04:42:51 PM PDT 24
Peak memory 208320 kb
Host smart-537d3f59-f397-41e9-8a72-7c51e3dd20c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555266164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1555266164
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1220751293
Short name T260
Test name
Test status
Simulation time 42521677 ps
CPU time 0.81 seconds
Started Jul 12 04:42:45 PM PDT 24
Finished Jul 12 04:42:48 PM PDT 24
Peak memory 208428 kb
Host smart-46b2a6ca-cf9b-4f27-964e-e1cb89c44dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220751293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1220751293
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3920976732
Short name T272
Test name
Test status
Simulation time 528035041 ps
CPU time 13.8 seconds
Started Jul 12 04:42:44 PM PDT 24
Finished Jul 12 04:43:00 PM PDT 24
Peak memory 217536 kb
Host smart-b0e04ad2-cf8b-495b-a25c-79077ffde6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920976732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3920976732
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2326535814
Short name T26
Test name
Test status
Simulation time 800145328 ps
CPU time 4.39 seconds
Started Jul 12 04:42:42 PM PDT 24
Finished Jul 12 04:42:47 PM PDT 24
Peak memory 217112 kb
Host smart-1eb3626c-3715-48fa-b7aa-f8ef55f42531
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326535814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2326535814
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2498744398
Short name T348
Test name
Test status
Simulation time 14248753419 ps
CPU time 52.26 seconds
Started Jul 12 04:42:48 PM PDT 24
Finished Jul 12 04:43:44 PM PDT 24
Peak memory 218304 kb
Host smart-c591ebd1-1a8f-4852-aa33-e7c82abecbb4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498744398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2498744398
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.12668507
Short name T268
Test name
Test status
Simulation time 1061279572 ps
CPU time 12.16 seconds
Started Jul 12 04:42:44 PM PDT 24
Finished Jul 12 04:42:58 PM PDT 24
Peak memory 217152 kb
Host smart-0b03d86c-13ca-42b2-ad74-d33a7c03b8b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12668507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.12668507
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3966044994
Short name T499
Test name
Test status
Simulation time 1991134389 ps
CPU time 3.85 seconds
Started Jul 12 04:42:44 PM PDT 24
Finished Jul 12 04:42:50 PM PDT 24
Peak memory 217536 kb
Host smart-37eee534-806b-4d9f-b8d7-1e421c3b38ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966044994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3966044994
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.568833907
Short name T701
Test name
Test status
Simulation time 1401379470 ps
CPU time 16.94 seconds
Started Jul 12 04:42:44 PM PDT 24
Finished Jul 12 04:43:03 PM PDT 24
Peak memory 217068 kb
Host smart-923756aa-dde7-4a38-b395-7ab80eb17d37
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568833907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.568833907
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.307878512
Short name T545
Test name
Test status
Simulation time 809319709 ps
CPU time 3.11 seconds
Started Jul 12 04:45:00 PM PDT 24
Finished Jul 12 04:45:06 PM PDT 24
Peak memory 216976 kb
Host smart-393e5fb7-be03-4b8b-b109-c6cdf27ec686
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307878512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.307878512
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2282288265
Short name T243
Test name
Test status
Simulation time 6003465128 ps
CPU time 39.99 seconds
Started Jul 12 04:42:42 PM PDT 24
Finished Jul 12 04:43:24 PM PDT 24
Peak memory 253960 kb
Host smart-d1214d8f-9e5e-499a-bc92-14eb29d0c38b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282288265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.2282288265
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.932843322
Short name T296
Test name
Test status
Simulation time 1696902679 ps
CPU time 12.25 seconds
Started Jul 12 04:42:41 PM PDT 24
Finished Jul 12 04:42:55 PM PDT 24
Peak memory 245560 kb
Host smart-9ee560e7-2525-4801-bbab-3a14f21d47c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932843322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.932843322
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3777116868
Short name T321
Test name
Test status
Simulation time 337575875 ps
CPU time 3.07 seconds
Started Jul 12 04:42:41 PM PDT 24
Finished Jul 12 04:42:45 PM PDT 24
Peak memory 217632 kb
Host smart-b4fec10c-2677-4a95-9c73-7ef85f5e70d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777116868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3777116868
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1318227665
Short name T58
Test name
Test status
Simulation time 416669776 ps
CPU time 13.71 seconds
Started Jul 12 04:42:43 PM PDT 24
Finished Jul 12 04:42:59 PM PDT 24
Peak memory 217168 kb
Host smart-e38305bd-b53e-4790-b9e5-73e2090c8907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318227665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1318227665
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.156943321
Short name T79
Test name
Test status
Simulation time 561979778 ps
CPU time 25.48 seconds
Started Jul 12 04:42:42 PM PDT 24
Finished Jul 12 04:43:09 PM PDT 24
Peak memory 281620 kb
Host smart-000080dc-7cb0-4b73-8cdf-5fb4b59b6d10
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156943321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.156943321
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3016368125
Short name T235
Test name
Test status
Simulation time 969134722 ps
CPU time 24.54 seconds
Started Jul 12 04:42:45 PM PDT 24
Finished Jul 12 04:43:11 PM PDT 24
Peak memory 225416 kb
Host smart-216e4793-5bdd-4109-b116-c59207a48dd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016368125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3016368125
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.4201457731
Short name T578
Test name
Test status
Simulation time 4710870342 ps
CPU time 20.66 seconds
Started Jul 12 04:42:49 PM PDT 24
Finished Jul 12 04:43:12 PM PDT 24
Peak memory 217676 kb
Host smart-fee4f43e-c5cc-4fff-b6a0-623fc6c0a55c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201457731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.4
201457731
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.544908320
Short name T733
Test name
Test status
Simulation time 191318274 ps
CPU time 5.83 seconds
Started Jul 12 04:42:41 PM PDT 24
Finished Jul 12 04:42:48 PM PDT 24
Peak memory 225428 kb
Host smart-4fee97ba-af0b-4959-9b3b-6165a3fbbbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544908320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.544908320
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1859014123
Short name T263
Test name
Test status
Simulation time 45662927 ps
CPU time 2.25 seconds
Started Jul 12 04:42:39 PM PDT 24
Finished Jul 12 04:42:43 PM PDT 24
Peak memory 213648 kb
Host smart-b03f3808-312b-47fe-a50e-a2ce65f0e5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859014123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1859014123
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3793413814
Short name T692
Test name
Test status
Simulation time 181454596 ps
CPU time 22.25 seconds
Started Jul 12 04:42:45 PM PDT 24
Finished Jul 12 04:43:09 PM PDT 24
Peak memory 250148 kb
Host smart-ea5c03d5-1daa-4a5f-9f3f-488f141e1fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793413814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3793413814
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3290759586
Short name T255
Test name
Test status
Simulation time 471739833 ps
CPU time 6.58 seconds
Started Jul 12 04:42:41 PM PDT 24
Finished Jul 12 04:42:49 PM PDT 24
Peak memory 246268 kb
Host smart-1bb3340b-7874-4fb7-92c8-da82a9426d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290759586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3290759586
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1598765818
Short name T854
Test name
Test status
Simulation time 1623814671 ps
CPU time 30.29 seconds
Started Jul 12 04:42:45 PM PDT 24
Finished Jul 12 04:43:17 PM PDT 24
Peak memory 225232 kb
Host smart-6a8c44a2-6cac-4816-846c-7603740002a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598765818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1598765818
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1995846280
Short name T327
Test name
Test status
Simulation time 13861547 ps
CPU time 0.88 seconds
Started Jul 12 04:42:45 PM PDT 24
Finished Jul 12 04:42:47 PM PDT 24
Peak memory 208280 kb
Host smart-fd3f3517-b4c7-4a74-afff-eedd135fb4ad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995846280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1995846280
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3028878674
Short name T663
Test name
Test status
Simulation time 48640335 ps
CPU time 1.02 seconds
Started Jul 12 04:42:43 PM PDT 24
Finished Jul 12 04:42:47 PM PDT 24
Peak memory 208340 kb
Host smart-23291d27-40b0-4db3-a34f-c543679cee5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028878674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3028878674
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3826764110
Short name T43
Test name
Test status
Simulation time 378235638 ps
CPU time 10.82 seconds
Started Jul 12 04:42:46 PM PDT 24
Finished Jul 12 04:42:59 PM PDT 24
Peak memory 217780 kb
Host smart-735cb451-10dc-4d88-b73a-d60072637299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826764110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3826764110
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.4282418390
Short name T344
Test name
Test status
Simulation time 7290767811 ps
CPU time 5.96 seconds
Started Jul 12 04:42:43 PM PDT 24
Finished Jul 12 04:42:51 PM PDT 24
Peak memory 217160 kb
Host smart-394bfe17-e905-4985-9d55-6a731323ed43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282418390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.4282418390
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.4071145424
Short name T594
Test name
Test status
Simulation time 9687895758 ps
CPU time 34.85 seconds
Started Jul 12 04:42:44 PM PDT 24
Finished Jul 12 04:43:21 PM PDT 24
Peak memory 217628 kb
Host smart-f443d4fd-e65b-4d62-a73a-400613a4e0bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071145424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.4071145424
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3325779407
Short name T192
Test name
Test status
Simulation time 2748044540 ps
CPU time 8.58 seconds
Started Jul 12 04:42:45 PM PDT 24
Finished Jul 12 04:42:55 PM PDT 24
Peak memory 217220 kb
Host smart-c2b4cac4-a2ba-4a2e-a42b-fb7afca08080
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325779407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3
325779407
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1683498871
Short name T356
Test name
Test status
Simulation time 484476284 ps
CPU time 3.11 seconds
Started Jul 12 04:42:41 PM PDT 24
Finished Jul 12 04:42:46 PM PDT 24
Peak memory 217672 kb
Host smart-076fae06-b0a7-479b-8b4a-a2012aaf1afb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683498871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1683498871
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.541642820
Short name T488
Test name
Test status
Simulation time 2613182388 ps
CPU time 10.81 seconds
Started Jul 12 04:42:48 PM PDT 24
Finished Jul 12 04:43:02 PM PDT 24
Peak memory 217076 kb
Host smart-d64d0c7c-eb4b-44ed-a82c-0ed8ee4c9206
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541642820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_regwen_during_op.541642820
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.604774800
Short name T400
Test name
Test status
Simulation time 88204224 ps
CPU time 3.22 seconds
Started Jul 12 04:42:45 PM PDT 24
Finished Jul 12 04:42:50 PM PDT 24
Peak memory 217176 kb
Host smart-e5d43eac-bce7-41d3-9271-bc1dcad2e381
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604774800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.604774800
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2098207178
Short name T315
Test name
Test status
Simulation time 1332156457 ps
CPU time 35.21 seconds
Started Jul 12 04:42:46 PM PDT 24
Finished Jul 12 04:43:23 PM PDT 24
Peak memory 283296 kb
Host smart-90e0a5a5-8344-4f30-b4c0-00a5a6d41e4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098207178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2098207178
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1973325983
Short name T19
Test name
Test status
Simulation time 297850767 ps
CPU time 14.6 seconds
Started Jul 12 04:42:43 PM PDT 24
Finished Jul 12 04:42:59 PM PDT 24
Peak memory 250388 kb
Host smart-48c5424c-0772-4eb4-bc59-e1d6edc947e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973325983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1973325983
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.107950583
Short name T868
Test name
Test status
Simulation time 334330214 ps
CPU time 3.05 seconds
Started Jul 12 04:42:42 PM PDT 24
Finished Jul 12 04:42:47 PM PDT 24
Peak memory 217696 kb
Host smart-f16db507-f869-417a-9884-6c6c5d01cc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107950583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.107950583
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.499047703
Short name T309
Test name
Test status
Simulation time 744818632 ps
CPU time 11.28 seconds
Started Jul 12 04:42:47 PM PDT 24
Finished Jul 12 04:43:01 PM PDT 24
Peak memory 217108 kb
Host smart-9c6a4d21-784a-4ca3-9b57-d36d6d4b5b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499047703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.499047703
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2824802613
Short name T93
Test name
Test status
Simulation time 105321601 ps
CPU time 22.93 seconds
Started Jul 12 04:42:46 PM PDT 24
Finished Jul 12 04:43:11 PM PDT 24
Peak memory 284144 kb
Host smart-f0c1546d-cfee-428b-98c6-840d098e296c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824802613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2824802613
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1110356599
Short name T286
Test name
Test status
Simulation time 185539922 ps
CPU time 10.33 seconds
Started Jul 12 04:42:43 PM PDT 24
Finished Jul 12 04:42:55 PM PDT 24
Peak memory 225432 kb
Host smart-f24714c7-4c50-4b7b-bdcc-7ed015631bbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110356599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1110356599
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1772084555
Short name T786
Test name
Test status
Simulation time 389580949 ps
CPU time 10.4 seconds
Started Jul 12 04:42:42 PM PDT 24
Finished Jul 12 04:42:54 PM PDT 24
Peak memory 225400 kb
Host smart-bc32e8be-5253-4f62-a3db-e5fdc2b76a27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772084555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1772084555
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.823064181
Short name T221
Test name
Test status
Simulation time 591870931 ps
CPU time 7.98 seconds
Started Jul 12 04:42:42 PM PDT 24
Finished Jul 12 04:42:51 PM PDT 24
Peak memory 217676 kb
Host smart-12ec4ab0-fc73-4cea-937c-eebccfb0abe7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823064181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.823064181
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3017492644
Short name T608
Test name
Test status
Simulation time 319895509 ps
CPU time 12.16 seconds
Started Jul 12 04:42:46 PM PDT 24
Finished Jul 12 04:43:00 PM PDT 24
Peak memory 225484 kb
Host smart-d3291565-6e7f-45b9-84f6-da1e3d33fd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017492644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3017492644
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2768972185
Short name T409
Test name
Test status
Simulation time 54632810 ps
CPU time 3.45 seconds
Started Jul 12 04:42:44 PM PDT 24
Finished Jul 12 04:42:49 PM PDT 24
Peak memory 222108 kb
Host smart-d667f45c-ec70-4d86-9134-4abef194107f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768972185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2768972185
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3400774481
Short name T689
Test name
Test status
Simulation time 194914608 ps
CPU time 23.77 seconds
Started Jul 12 04:42:42 PM PDT 24
Finished Jul 12 04:43:07 PM PDT 24
Peak memory 250448 kb
Host smart-26c109f2-e7a6-4d69-859c-74e795d57841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400774481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3400774481
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1627035376
Short name T369
Test name
Test status
Simulation time 125704203 ps
CPU time 7.72 seconds
Started Jul 12 04:42:43 PM PDT 24
Finished Jul 12 04:42:53 PM PDT 24
Peak memory 250384 kb
Host smart-262a0e81-50ec-47be-93e9-15625f5a8c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627035376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1627035376
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3879126719
Short name T483
Test name
Test status
Simulation time 13455401356 ps
CPU time 45.55 seconds
Started Jul 12 04:42:42 PM PDT 24
Finished Jul 12 04:43:29 PM PDT 24
Peak memory 266904 kb
Host smart-a1ae548f-2ac2-4dd7-90c6-51613b349d30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879126719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3879126719
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2655814944
Short name T849
Test name
Test status
Simulation time 103224524 ps
CPU time 1.56 seconds
Started Jul 12 04:42:45 PM PDT 24
Finished Jul 12 04:42:48 PM PDT 24
Peak memory 217296 kb
Host smart-971c1a77-8c14-4eca-9e2d-1030057dab8c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655814944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2655814944
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2677552069
Short name T354
Test name
Test status
Simulation time 19046771 ps
CPU time 1.11 seconds
Started Jul 12 04:43:21 PM PDT 24
Finished Jul 12 04:43:26 PM PDT 24
Peak memory 208440 kb
Host smart-94e6180e-b778-4375-a953-b69740d3cd55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677552069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2677552069
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3864446563
Short name T363
Test name
Test status
Simulation time 432464938 ps
CPU time 12 seconds
Started Jul 12 04:43:16 PM PDT 24
Finished Jul 12 04:43:31 PM PDT 24
Peak memory 217624 kb
Host smart-9deab3a9-ca7e-4402-a5c9-53d52f807f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864446563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3864446563
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.4288714481
Short name T416
Test name
Test status
Simulation time 1481861700 ps
CPU time 9.15 seconds
Started Jul 12 04:43:18 PM PDT 24
Finished Jul 12 04:43:30 PM PDT 24
Peak memory 217128 kb
Host smart-9bbd976a-b56d-4d08-8c00-f8cc08ac212c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288714481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.4288714481
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2061599274
Short name T687
Test name
Test status
Simulation time 8150584646 ps
CPU time 57.08 seconds
Started Jul 12 04:43:17 PM PDT 24
Finished Jul 12 04:44:16 PM PDT 24
Peak memory 218356 kb
Host smart-12b434c7-58f3-4c34-94cd-da3894cf8653
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061599274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2061599274
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1445047944
Short name T755
Test name
Test status
Simulation time 700082409 ps
CPU time 3.21 seconds
Started Jul 12 04:43:21 PM PDT 24
Finished Jul 12 04:43:27 PM PDT 24
Peak memory 217596 kb
Host smart-a501ecd4-ddb1-46a2-8ed6-c1d14ab76471
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445047944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1445047944
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.938555014
Short name T584
Test name
Test status
Simulation time 1932449019 ps
CPU time 4.59 seconds
Started Jul 12 04:43:22 PM PDT 24
Finished Jul 12 04:43:30 PM PDT 24
Peak memory 217004 kb
Host smart-3d1b1c2a-4827-4cc9-9756-1eac243a5964
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938555014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.
938555014
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.895919531
Short name T100
Test name
Test status
Simulation time 2904884615 ps
CPU time 64.77 seconds
Started Jul 12 04:43:14 PM PDT 24
Finished Jul 12 04:44:21 PM PDT 24
Peak memory 277308 kb
Host smart-2fb86421-39a1-454e-a95e-4bdf13620fd0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895919531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_state_failure.895919531
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2066653637
Short name T827
Test name
Test status
Simulation time 1530528849 ps
CPU time 15.78 seconds
Started Jul 12 04:43:22 PM PDT 24
Finished Jul 12 04:43:41 PM PDT 24
Peak memory 249828 kb
Host smart-671e5d76-df7c-452c-80d3-6fc0f8d0929c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066653637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2066653637
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2630815888
Short name T454
Test name
Test status
Simulation time 72512934 ps
CPU time 2.79 seconds
Started Jul 12 04:43:19 PM PDT 24
Finished Jul 12 04:43:25 PM PDT 24
Peak memory 221848 kb
Host smart-908751e5-01dd-4413-b985-a729b0252fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630815888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2630815888
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3459500835
Short name T337
Test name
Test status
Simulation time 1156951639 ps
CPU time 15.29 seconds
Started Jul 12 04:43:22 PM PDT 24
Finished Jul 12 04:43:41 PM PDT 24
Peak memory 218324 kb
Host smart-aa88d73f-3733-428a-be55-487eaac1de77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459500835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3459500835
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1809746512
Short name T668
Test name
Test status
Simulation time 723105581 ps
CPU time 7.68 seconds
Started Jul 12 04:43:19 PM PDT 24
Finished Jul 12 04:43:30 PM PDT 24
Peak memory 225432 kb
Host smart-51b1f750-904c-459d-bacc-02ba7dbf11a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809746512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1809746512
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.846178213
Short name T677
Test name
Test status
Simulation time 462249111 ps
CPU time 9.28 seconds
Started Jul 12 04:43:20 PM PDT 24
Finished Jul 12 04:43:33 PM PDT 24
Peak memory 217508 kb
Host smart-4f0e5c06-b49e-4aef-a147-2f49a7a08c6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846178213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.846178213
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3860493341
Short name T524
Test name
Test status
Simulation time 1367986163 ps
CPU time 11.2 seconds
Started Jul 12 04:43:12 PM PDT 24
Finished Jul 12 04:43:25 PM PDT 24
Peak memory 217760 kb
Host smart-511eee18-5e3c-4003-857f-dcc1730c9fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860493341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3860493341
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.647517232
Short name T544
Test name
Test status
Simulation time 67415044 ps
CPU time 1.21 seconds
Started Jul 12 04:43:12 PM PDT 24
Finished Jul 12 04:43:16 PM PDT 24
Peak memory 213084 kb
Host smart-dc78d087-feca-4c5d-8238-c75304563add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647517232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.647517232
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2466619635
Short name T340
Test name
Test status
Simulation time 961630851 ps
CPU time 22.83 seconds
Started Jul 12 04:43:12 PM PDT 24
Finished Jul 12 04:43:38 PM PDT 24
Peak memory 250416 kb
Host smart-80a8b6e3-710b-4d3b-81f5-874cd0c725e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466619635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2466619635
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.78795417
Short name T493
Test name
Test status
Simulation time 371491596 ps
CPU time 3.42 seconds
Started Jul 12 04:43:22 PM PDT 24
Finished Jul 12 04:43:29 PM PDT 24
Peak memory 217596 kb
Host smart-d320b313-405c-46c0-a205-967eda675773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78795417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.78795417
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1305479112
Short name T780
Test name
Test status
Simulation time 3312397214 ps
CPU time 130.41 seconds
Started Jul 12 04:43:19 PM PDT 24
Finished Jul 12 04:45:33 PM PDT 24
Peak memory 266912 kb
Host smart-2985290a-d6fe-46d3-9cb0-037bec65a75a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305479112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1305479112
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3443999146
Short name T34
Test name
Test status
Simulation time 11804780 ps
CPU time 1.06 seconds
Started Jul 12 04:43:18 PM PDT 24
Finished Jul 12 04:43:22 PM PDT 24
Peak memory 211304 kb
Host smart-92e4ebcc-8b09-41d7-9c02-3d6949b47bdf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443999146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3443999146
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.929240502
Short name T769
Test name
Test status
Simulation time 67504651 ps
CPU time 0.93 seconds
Started Jul 12 04:43:19 PM PDT 24
Finished Jul 12 04:43:23 PM PDT 24
Peak memory 208320 kb
Host smart-744aba95-53a0-4532-9fb3-5f3c67665a8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929240502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.929240502
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3036191310
Short name T59
Test name
Test status
Simulation time 438764576 ps
CPU time 14.12 seconds
Started Jul 12 04:43:20 PM PDT 24
Finished Jul 12 04:43:38 PM PDT 24
Peak memory 217636 kb
Host smart-135bb03e-3d12-4abe-9f9e-18fe25e3a935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036191310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3036191310
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.4171337885
Short name T829
Test name
Test status
Simulation time 1247919812 ps
CPU time 7.84 seconds
Started Jul 12 04:43:21 PM PDT 24
Finished Jul 12 04:43:32 PM PDT 24
Peak memory 216680 kb
Host smart-3a948d8b-0b2d-4d5e-9863-69e4b98df169
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171337885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.4171337885
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1300445736
Short name T209
Test name
Test status
Simulation time 4932803328 ps
CPU time 130.34 seconds
Started Jul 12 04:43:20 PM PDT 24
Finished Jul 12 04:45:34 PM PDT 24
Peak memory 219620 kb
Host smart-79769bf4-8af6-488e-a315-78a7a188c1c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300445736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1300445736
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.4280839587
Short name T485
Test name
Test status
Simulation time 794733424 ps
CPU time 22.2 seconds
Started Jul 12 04:43:20 PM PDT 24
Finished Jul 12 04:43:46 PM PDT 24
Peak memory 217880 kb
Host smart-c4fe39f6-4ba3-48ca-925e-847281994b56
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280839587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.4280839587
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.1264812797
Short name T158
Test name
Test status
Simulation time 218620711 ps
CPU time 6.66 seconds
Started Jul 12 04:43:23 PM PDT 24
Finished Jul 12 04:43:33 PM PDT 24
Peak memory 216964 kb
Host smart-c98bc42f-5526-4396-82f1-e094cd4ba7c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264812797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.1264812797
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1474313686
Short name T393
Test name
Test status
Simulation time 8922326267 ps
CPU time 93.62 seconds
Started Jul 12 04:43:19 PM PDT 24
Finished Jul 12 04:44:56 PM PDT 24
Peak memory 283084 kb
Host smart-6c50e9d9-65fa-40ce-9be3-d029114b95a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474313686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.1474313686
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3107055733
Short name T864
Test name
Test status
Simulation time 377986084 ps
CPU time 12.4 seconds
Started Jul 12 04:43:23 PM PDT 24
Finished Jul 12 04:43:38 PM PDT 24
Peak memory 250316 kb
Host smart-ca472da9-24cf-4215-ad97-60c918da9f28
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107055733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3107055733
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1375267963
Short name T86
Test name
Test status
Simulation time 90713925 ps
CPU time 1.96 seconds
Started Jul 12 04:43:23 PM PDT 24
Finished Jul 12 04:43:28 PM PDT 24
Peak memory 217632 kb
Host smart-4901abb4-849f-401f-a2c0-213009c4de6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375267963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1375267963
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.674001967
Short name T789
Test name
Test status
Simulation time 186487738 ps
CPU time 7.58 seconds
Started Jul 12 04:43:20 PM PDT 24
Finished Jul 12 04:43:30 PM PDT 24
Peak memory 225492 kb
Host smart-087bf84e-00c3-4fde-b15a-28dc7348d033
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674001967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.674001967
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2133669786
Short name T320
Test name
Test status
Simulation time 1746181707 ps
CPU time 10.06 seconds
Started Jul 12 04:43:23 PM PDT 24
Finished Jul 12 04:43:36 PM PDT 24
Peak memory 225384 kb
Host smart-8c6a6a6d-3049-44af-90bb-8a8b48d6d4d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133669786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2133669786
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3374254268
Short name T334
Test name
Test status
Simulation time 243162603 ps
CPU time 9.02 seconds
Started Jul 12 04:43:19 PM PDT 24
Finished Jul 12 04:43:31 PM PDT 24
Peak memory 217588 kb
Host smart-34665e33-2927-476f-98b4-b9e51c8d3042
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374254268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3374254268
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1031369492
Short name T265
Test name
Test status
Simulation time 297863425 ps
CPU time 10.67 seconds
Started Jul 12 04:43:22 PM PDT 24
Finished Jul 12 04:43:36 PM PDT 24
Peak memory 225452 kb
Host smart-e8098a09-f2b2-44ef-b847-9c1cad6b2bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031369492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1031369492
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3628277519
Short name T244
Test name
Test status
Simulation time 58121066 ps
CPU time 1.42 seconds
Started Jul 12 04:43:24 PM PDT 24
Finished Jul 12 04:43:28 PM PDT 24
Peak memory 213216 kb
Host smart-56fbbdbf-1da1-4448-b66b-34ce490fd36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628277519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3628277519
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.4059086298
Short name T707
Test name
Test status
Simulation time 367108219 ps
CPU time 21.31 seconds
Started Jul 12 04:43:22 PM PDT 24
Finished Jul 12 04:43:47 PM PDT 24
Peak memory 250412 kb
Host smart-c7d27341-c26d-49c9-aef9-2a576a28030b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059086298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.4059086298
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.314669786
Short name T719
Test name
Test status
Simulation time 95741025 ps
CPU time 7.32 seconds
Started Jul 12 04:43:19 PM PDT 24
Finished Jul 12 04:43:30 PM PDT 24
Peak memory 250464 kb
Host smart-642ad936-6d71-44f8-a979-05296f4d46f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314669786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.314669786
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.4002824285
Short name T815
Test name
Test status
Simulation time 15623340875 ps
CPU time 92.51 seconds
Started Jul 12 04:43:22 PM PDT 24
Finished Jul 12 04:44:58 PM PDT 24
Peak memory 267028 kb
Host smart-10243f05-ef95-43df-b11b-3e0129115ec9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002824285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.4002824285
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2252835917
Short name T838
Test name
Test status
Simulation time 23317854 ps
CPU time 0.83 seconds
Started Jul 12 04:43:19 PM PDT 24
Finished Jul 12 04:43:22 PM PDT 24
Peak memory 208284 kb
Host smart-88be748d-a243-4456-84a2-9e0635918ee3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252835917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2252835917
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3464541402
Short name T709
Test name
Test status
Simulation time 20180892 ps
CPU time 0.91 seconds
Started Jul 12 04:43:23 PM PDT 24
Finished Jul 12 04:43:27 PM PDT 24
Peak memory 208428 kb
Host smart-3bbbc1b1-2bd7-43ea-8d45-ce99265634ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464541402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3464541402
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2341442957
Short name T853
Test name
Test status
Simulation time 579169269 ps
CPU time 10.52 seconds
Started Jul 12 04:43:19 PM PDT 24
Finished Jul 12 04:43:33 PM PDT 24
Peak memory 225444 kb
Host smart-72a3f5d5-fde2-4782-987f-f10c0112c957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341442957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2341442957
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3400040704
Short name T775
Test name
Test status
Simulation time 2710557836 ps
CPU time 7.83 seconds
Started Jul 12 04:43:19 PM PDT 24
Finished Jul 12 04:43:29 PM PDT 24
Peak memory 217044 kb
Host smart-c4f89899-8600-4dd1-af3c-c5edb77eaa2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400040704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3400040704
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3431521579
Short name T762
Test name
Test status
Simulation time 74917670471 ps
CPU time 49.67 seconds
Started Jul 12 04:43:24 PM PDT 24
Finished Jul 12 04:44:17 PM PDT 24
Peak memory 218436 kb
Host smart-66a7e99f-8aeb-4b5a-9d1b-d3776f3f8c37
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431521579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3431521579
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3837071278
Short name T406
Test name
Test status
Simulation time 222584310 ps
CPU time 7.36 seconds
Started Jul 12 04:43:21 PM PDT 24
Finished Jul 12 04:43:32 PM PDT 24
Peak memory 217656 kb
Host smart-3ba31590-879b-4cba-98eb-79691fdcb3f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837071278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3837071278
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1735562313
Short name T270
Test name
Test status
Simulation time 1198872737 ps
CPU time 3.8 seconds
Started Jul 12 04:43:21 PM PDT 24
Finished Jul 12 04:43:28 PM PDT 24
Peak memory 216948 kb
Host smart-f1465058-7d11-451c-ab63-46881eb58c58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735562313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1735562313
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1144920441
Short name T653
Test name
Test status
Simulation time 808436335 ps
CPU time 33.47 seconds
Started Jul 12 04:43:20 PM PDT 24
Finished Jul 12 04:43:57 PM PDT 24
Peak memory 250460 kb
Host smart-0b8fade2-d1ca-4c33-941d-7c187b071e5e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144920441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1144920441
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1880131900
Short name T306
Test name
Test status
Simulation time 523894372 ps
CPU time 12.49 seconds
Started Jul 12 04:43:19 PM PDT 24
Finished Jul 12 04:43:35 PM PDT 24
Peak memory 246028 kb
Host smart-cc621f2b-a770-4e16-83e8-db8e7ef2dbfd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880131900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1880131900
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3441613211
Short name T610
Test name
Test status
Simulation time 608179530 ps
CPU time 3.42 seconds
Started Jul 12 04:43:20 PM PDT 24
Finished Jul 12 04:43:27 PM PDT 24
Peak memory 217600 kb
Host smart-8cfd309b-372a-4e65-9fdd-b5e5fe8b0ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441613211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3441613211
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.4224154789
Short name T84
Test name
Test status
Simulation time 1541632666 ps
CPU time 11.76 seconds
Started Jul 12 04:43:28 PM PDT 24
Finished Jul 12 04:43:42 PM PDT 24
Peak memory 217704 kb
Host smart-fdc3e0d4-531c-4645-b5cd-a497a7a0e2b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224154789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.4224154789
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1337469073
Short name T679
Test name
Test status
Simulation time 894991113 ps
CPU time 16.24 seconds
Started Jul 12 04:43:24 PM PDT 24
Finished Jul 12 04:43:43 PM PDT 24
Peak memory 225416 kb
Host smart-1c783fc3-1b85-4aeb-addb-ffe8fcba3db4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337469073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1337469073
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.4102671706
Short name T253
Test name
Test status
Simulation time 1609988120 ps
CPU time 13.61 seconds
Started Jul 12 04:43:30 PM PDT 24
Finished Jul 12 04:43:45 PM PDT 24
Peak memory 217596 kb
Host smart-bf50eead-fe45-4a76-87fc-8bddff74b637
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102671706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
4102671706
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1252075379
Short name T541
Test name
Test status
Simulation time 1033073796 ps
CPU time 8.55 seconds
Started Jul 12 04:43:21 PM PDT 24
Finished Jul 12 04:43:33 PM PDT 24
Peak memory 225512 kb
Host smart-2f6fea68-989b-4ff4-91c6-561d934605a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252075379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1252075379
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.546296882
Short name T676
Test name
Test status
Simulation time 49742302 ps
CPU time 2.61 seconds
Started Jul 12 04:43:20 PM PDT 24
Finished Jul 12 04:43:26 PM PDT 24
Peak memory 217096 kb
Host smart-006fea07-f7b1-4950-b357-7a5d9d90952e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546296882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.546296882
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.439755702
Short name T227
Test name
Test status
Simulation time 191276891 ps
CPU time 23.5 seconds
Started Jul 12 04:43:22 PM PDT 24
Finished Jul 12 04:43:49 PM PDT 24
Peak memory 250344 kb
Host smart-75aa46a2-5b3a-4de1-87fa-14b8d0834edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439755702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.439755702
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1656875713
Short name T645
Test name
Test status
Simulation time 74642129 ps
CPU time 7.52 seconds
Started Jul 12 04:43:21 PM PDT 24
Finished Jul 12 04:43:32 PM PDT 24
Peak memory 250436 kb
Host smart-0666edbc-d56a-4a6c-a1f5-a404f84d2ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656875713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1656875713
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2970656953
Short name T682
Test name
Test status
Simulation time 8162021869 ps
CPU time 155.79 seconds
Started Jul 12 04:43:26 PM PDT 24
Finished Jul 12 04:46:04 PM PDT 24
Peak memory 250040 kb
Host smart-6c971c0a-77c3-4e30-ac9a-0d4a018b4e54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970656953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2970656953
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2569534366
Short name T375
Test name
Test status
Simulation time 27202610 ps
CPU time 0.81 seconds
Started Jul 12 04:43:22 PM PDT 24
Finished Jul 12 04:43:26 PM PDT 24
Peak memory 208212 kb
Host smart-c48335d2-9446-4f38-a009-df086a13cde9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569534366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.2569534366
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.525748118
Short name T547
Test name
Test status
Simulation time 33658563 ps
CPU time 0.92 seconds
Started Jul 12 04:43:24 PM PDT 24
Finished Jul 12 04:43:28 PM PDT 24
Peak memory 208356 kb
Host smart-66dea9ec-f6a2-4141-a893-6e66b3e32199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525748118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.525748118
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1854817647
Short name T819
Test name
Test status
Simulation time 266257082 ps
CPU time 12.04 seconds
Started Jul 12 04:43:26 PM PDT 24
Finished Jul 12 04:43:39 PM PDT 24
Peak memory 217716 kb
Host smart-e433fe19-44e5-48f0-a9b7-edd792f2e886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854817647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1854817647
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2860037985
Short name T422
Test name
Test status
Simulation time 1557423905 ps
CPU time 9.95 seconds
Started Jul 12 04:43:24 PM PDT 24
Finished Jul 12 04:43:37 PM PDT 24
Peak memory 217056 kb
Host smart-adfba2fb-1a17-4b1a-9c73-a279aee16d52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860037985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2860037985
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3903816459
Short name T85
Test name
Test status
Simulation time 4030614118 ps
CPU time 30.95 seconds
Started Jul 12 04:43:26 PM PDT 24
Finished Jul 12 04:43:59 PM PDT 24
Peak memory 218360 kb
Host smart-04b38ec9-5398-4a27-8f0f-2c57e3c09fb9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903816459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3903816459
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2612048775
Short name T329
Test name
Test status
Simulation time 286658049 ps
CPU time 3.28 seconds
Started Jul 12 04:43:27 PM PDT 24
Finished Jul 12 04:43:33 PM PDT 24
Peak memory 217508 kb
Host smart-4a2f7742-21bc-4640-b12f-33cf899d455b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612048775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2612048775
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.631139227
Short name T666
Test name
Test status
Simulation time 1455809610 ps
CPU time 9.71 seconds
Started Jul 12 04:43:25 PM PDT 24
Finished Jul 12 04:43:37 PM PDT 24
Peak memory 216996 kb
Host smart-dacde76b-e3cf-4e20-8f37-e0629435fcfc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631139227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
631139227
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1108083310
Short name T734
Test name
Test status
Simulation time 1341396204 ps
CPU time 34.74 seconds
Started Jul 12 04:43:23 PM PDT 24
Finished Jul 12 04:44:01 PM PDT 24
Peak memory 266772 kb
Host smart-b885d912-116b-4bfd-b312-4720a53efb3a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108083310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1108083310
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3996704038
Short name T16
Test name
Test status
Simulation time 436101778 ps
CPU time 12.88 seconds
Started Jul 12 04:43:26 PM PDT 24
Finished Jul 12 04:43:41 PM PDT 24
Peak memory 250436 kb
Host smart-13a7118e-383a-49a9-9c27-09142f3f6fd3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996704038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3996704038
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3053966228
Short name T349
Test name
Test status
Simulation time 296604104 ps
CPU time 1.96 seconds
Started Jul 12 04:43:29 PM PDT 24
Finished Jul 12 04:43:33 PM PDT 24
Peak memory 217704 kb
Host smart-abb1d666-4cc6-4856-aefd-ea3de5f2bf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053966228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3053966228
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3438192007
Short name T427
Test name
Test status
Simulation time 1538917227 ps
CPU time 14.19 seconds
Started Jul 12 04:43:29 PM PDT 24
Finished Jul 12 04:43:45 PM PDT 24
Peak memory 218280 kb
Host smart-daf1d7cb-bdc4-4bec-8385-67ce8e8e1c80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438192007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3438192007
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1810492606
Short name T617
Test name
Test status
Simulation time 500363672 ps
CPU time 11.43 seconds
Started Jul 12 04:43:28 PM PDT 24
Finished Jul 12 04:43:42 PM PDT 24
Peak memory 225332 kb
Host smart-ec8092f8-9578-4632-87e9-3f7d3efb26c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810492606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1810492606
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.4199130428
Short name T156
Test name
Test status
Simulation time 587251941 ps
CPU time 6.98 seconds
Started Jul 12 04:43:30 PM PDT 24
Finished Jul 12 04:43:39 PM PDT 24
Peak memory 217596 kb
Host smart-081d14fd-3a97-459c-b4ec-f77f125e9329
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199130428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
4199130428
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2287191960
Short name T48
Test name
Test status
Simulation time 311723141 ps
CPU time 8.48 seconds
Started Jul 12 04:43:29 PM PDT 24
Finished Jul 12 04:43:39 PM PDT 24
Peak memory 223932 kb
Host smart-091f0b79-2686-4610-94db-ddb6b8eb6c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287191960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2287191960
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1960805071
Short name T697
Test name
Test status
Simulation time 71374532 ps
CPU time 1.09 seconds
Started Jul 12 04:43:28 PM PDT 24
Finished Jul 12 04:43:31 PM PDT 24
Peak memory 213148 kb
Host smart-b6f2f8df-4ed7-4118-a15a-6015bdba4f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960805071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1960805071
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2144579836
Short name T772
Test name
Test status
Simulation time 304871333 ps
CPU time 34.76 seconds
Started Jul 12 04:43:29 PM PDT 24
Finished Jul 12 04:44:05 PM PDT 24
Peak memory 250472 kb
Host smart-7474a59c-4373-4c2b-b0eb-e8e514fd86d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144579836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2144579836
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2077876068
Short name T316
Test name
Test status
Simulation time 200500570 ps
CPU time 6.07 seconds
Started Jul 12 04:43:29 PM PDT 24
Finished Jul 12 04:43:37 PM PDT 24
Peak memory 250032 kb
Host smart-bf1beec3-1098-4a04-986d-684341c0fd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077876068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2077876068
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.192895862
Short name T845
Test name
Test status
Simulation time 8088039598 ps
CPU time 284.16 seconds
Started Jul 12 04:43:25 PM PDT 24
Finished Jul 12 04:48:11 PM PDT 24
Peak memory 250524 kb
Host smart-ead4f2b1-a903-4fba-9045-2d2c120b6bb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192895862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.192895862
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3250721891
Short name T496
Test name
Test status
Simulation time 31054095 ps
CPU time 0.75 seconds
Started Jul 12 04:43:26 PM PDT 24
Finished Jul 12 04:43:29 PM PDT 24
Peak memory 208092 kb
Host smart-a1d37d6a-bb5d-491b-bfd8-22290a895958
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250721891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3250721891
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1293958180
Short name T82
Test name
Test status
Simulation time 43775668 ps
CPU time 0.89 seconds
Started Jul 12 04:43:32 PM PDT 24
Finished Jul 12 04:43:34 PM PDT 24
Peak memory 208248 kb
Host smart-e3239160-4994-4c47-9dc3-14a894f5910d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293958180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1293958180
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2429460060
Short name T848
Test name
Test status
Simulation time 815670646 ps
CPU time 18.3 seconds
Started Jul 12 04:43:28 PM PDT 24
Finished Jul 12 04:43:49 PM PDT 24
Peak memory 217632 kb
Host smart-33d303b7-37ec-492e-8160-841fd0662015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429460060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2429460060
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.665262135
Short name T97
Test name
Test status
Simulation time 196631003 ps
CPU time 1.2 seconds
Started Jul 12 04:43:31 PM PDT 24
Finished Jul 12 04:43:34 PM PDT 24
Peak memory 217128 kb
Host smart-ca63b5ef-10b0-4948-aace-cd63a0e96432
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665262135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.665262135
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1154862905
Short name T621
Test name
Test status
Simulation time 3447651605 ps
CPU time 28.46 seconds
Started Jul 12 04:43:33 PM PDT 24
Finished Jul 12 04:44:03 PM PDT 24
Peak memory 218336 kb
Host smart-53e1d835-4d1f-459c-bd95-a5c94b111e4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154862905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1154862905
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2585359603
Short name T828
Test name
Test status
Simulation time 1649132582 ps
CPU time 5.27 seconds
Started Jul 12 04:43:30 PM PDT 24
Finished Jul 12 04:43:37 PM PDT 24
Peak memory 221112 kb
Host smart-37a1cdca-b80c-44bb-93a7-1f44117a9caf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585359603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2585359603
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1230392410
Short name T842
Test name
Test status
Simulation time 892780272 ps
CPU time 6.46 seconds
Started Jul 12 04:43:27 PM PDT 24
Finished Jul 12 04:43:35 PM PDT 24
Peak memory 217052 kb
Host smart-8af234c8-07b4-40fc-a936-29fb3cd6b141
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230392410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1230392410
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.294658582
Short name T233
Test name
Test status
Simulation time 7376707496 ps
CPU time 38.45 seconds
Started Jul 12 04:43:33 PM PDT 24
Finished Jul 12 04:44:13 PM PDT 24
Peak memory 266868 kb
Host smart-175f5194-db83-4a6a-8700-9b9b54d135a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294658582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.294658582
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.3112229496
Short name T399
Test name
Test status
Simulation time 2420826087 ps
CPU time 15.28 seconds
Started Jul 12 04:43:33 PM PDT 24
Finished Jul 12 04:43:50 PM PDT 24
Peak memory 225700 kb
Host smart-4839cd7d-89b6-43cf-bef7-9123562c861d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112229496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.3112229496
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3997833009
Short name T449
Test name
Test status
Simulation time 269390400 ps
CPU time 3.16 seconds
Started Jul 12 04:43:24 PM PDT 24
Finished Jul 12 04:43:30 PM PDT 24
Peak memory 222024 kb
Host smart-2fc0229a-4ccc-4c2b-a4d7-32ca630257ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997833009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3997833009
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.655735132
Short name T626
Test name
Test status
Simulation time 794168002 ps
CPU time 7.82 seconds
Started Jul 12 04:43:31 PM PDT 24
Finished Jul 12 04:43:40 PM PDT 24
Peak memory 225512 kb
Host smart-c2b6d717-6167-4d8d-a2cd-6254fdee9cf6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655735132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.655735132
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2025808202
Short name T392
Test name
Test status
Simulation time 255215016 ps
CPU time 11.36 seconds
Started Jul 12 04:43:32 PM PDT 24
Finished Jul 12 04:43:45 PM PDT 24
Peak memory 225452 kb
Host smart-1691a538-0f7b-4e23-bfcc-65b7f265a017
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025808202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2025808202
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1454829000
Short name T794
Test name
Test status
Simulation time 707437472 ps
CPU time 14.97 seconds
Started Jul 12 04:43:34 PM PDT 24
Finished Jul 12 04:43:50 PM PDT 24
Peak memory 217596 kb
Host smart-14b700b5-923a-4ea3-a993-41f0b9eba235
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454829000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1454829000
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2677568986
Short name T736
Test name
Test status
Simulation time 809329030 ps
CPU time 10.22 seconds
Started Jul 12 04:43:27 PM PDT 24
Finished Jul 12 04:43:39 PM PDT 24
Peak memory 225512 kb
Host smart-163cb790-0481-4b73-b74a-2da15d3a56bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677568986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2677568986
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2261569572
Short name T783
Test name
Test status
Simulation time 192044960 ps
CPU time 2.83 seconds
Started Jul 12 04:43:31 PM PDT 24
Finished Jul 12 04:43:35 PM PDT 24
Peak memory 217068 kb
Host smart-eae99949-b19c-4f66-b8ee-02f3d5cde8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261569572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2261569572
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3444762325
Short name T464
Test name
Test status
Simulation time 186348221 ps
CPU time 24.95 seconds
Started Jul 12 04:43:29 PM PDT 24
Finished Jul 12 04:43:55 PM PDT 24
Peak memory 250388 kb
Host smart-0c40d523-e4e5-4975-93a7-ac0ca51bccea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444762325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3444762325
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2076902251
Short name T256
Test name
Test status
Simulation time 90101253 ps
CPU time 4.51 seconds
Started Jul 12 04:43:29 PM PDT 24
Finished Jul 12 04:43:35 PM PDT 24
Peak memory 221868 kb
Host smart-4f79684e-ea34-499f-af17-dc1b1ea99337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076902251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2076902251
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3175368442
Short name T38
Test name
Test status
Simulation time 61481894010 ps
CPU time 74.12 seconds
Started Jul 12 04:43:35 PM PDT 24
Finished Jul 12 04:44:50 PM PDT 24
Peak memory 250500 kb
Host smart-60aad70b-fe20-4d9f-a8c3-2c3e4e2936b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175368442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3175368442
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3556777843
Short name T431
Test name
Test status
Simulation time 14554099 ps
CPU time 0.98 seconds
Started Jul 12 04:43:26 PM PDT 24
Finished Jul 12 04:43:29 PM PDT 24
Peak memory 208380 kb
Host smart-8b9a06be-2cc8-495d-97e3-ab54befc5d1c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556777843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3556777843
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.617140276
Short name T654
Test name
Test status
Simulation time 46897316 ps
CPU time 1.04 seconds
Started Jul 12 04:43:41 PM PDT 24
Finished Jul 12 04:43:43 PM PDT 24
Peak memory 208384 kb
Host smart-e734b05a-2fcd-4dcd-9cbd-429c8051a8e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617140276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.617140276
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2249618852
Short name T68
Test name
Test status
Simulation time 384281040 ps
CPU time 14.14 seconds
Started Jul 12 04:43:35 PM PDT 24
Finished Jul 12 04:43:50 PM PDT 24
Peak memory 225464 kb
Host smart-f2e47120-984a-40c4-9bfd-1339625986a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249618852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2249618852
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3580277296
Short name T598
Test name
Test status
Simulation time 820096082 ps
CPU time 2.82 seconds
Started Jul 12 04:43:30 PM PDT 24
Finished Jul 12 04:43:34 PM PDT 24
Peak memory 217048 kb
Host smart-c7ccbb3a-cc49-4f93-bd56-9a3e34810996
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580277296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3580277296
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2873080516
Short name T223
Test name
Test status
Simulation time 3173680222 ps
CPU time 46.94 seconds
Started Jul 12 04:43:32 PM PDT 24
Finished Jul 12 04:44:20 PM PDT 24
Peak memory 218504 kb
Host smart-18e5cf12-0fc7-41f2-bc57-5bc93f8032ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873080516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2873080516
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2363996008
Short name T455
Test name
Test status
Simulation time 302004802 ps
CPU time 8.77 seconds
Started Jul 12 04:43:31 PM PDT 24
Finished Jul 12 04:43:41 PM PDT 24
Peak memory 217656 kb
Host smart-5fd70623-7e10-4ba7-9c72-0c580b7daa75
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363996008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2363996008
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.4114800771
Short name T278
Test name
Test status
Simulation time 792218441 ps
CPU time 2.81 seconds
Started Jul 12 04:47:38 PM PDT 24
Finished Jul 12 04:47:42 PM PDT 24
Peak memory 217112 kb
Host smart-4c7ead5e-9c22-4720-8b22-a524545b5450
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114800771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.4114800771
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.711248931
Short name T661
Test name
Test status
Simulation time 25745393037 ps
CPU time 36.32 seconds
Started Jul 12 04:43:35 PM PDT 24
Finished Jul 12 04:44:12 PM PDT 24
Peak memory 275036 kb
Host smart-f0507106-f69c-48a0-81c8-88f7c8005af2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711248931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.711248931
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.484822851
Short name T675
Test name
Test status
Simulation time 3007604814 ps
CPU time 18.52 seconds
Started Jul 12 04:43:34 PM PDT 24
Finished Jul 12 04:43:53 PM PDT 24
Peak memory 250388 kb
Host smart-2299c919-1281-42b8-8781-924f40c9ae73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484822851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.484822851
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1831143406
Short name T835
Test name
Test status
Simulation time 77432878 ps
CPU time 3.3 seconds
Started Jul 12 04:43:36 PM PDT 24
Finished Jul 12 04:43:40 PM PDT 24
Peak memory 217724 kb
Host smart-4b99531f-112b-46a8-861a-a05693becf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831143406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1831143406
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.4136238708
Short name T165
Test name
Test status
Simulation time 366019023 ps
CPU time 8.46 seconds
Started Jul 12 04:43:39 PM PDT 24
Finished Jul 12 04:43:49 PM PDT 24
Peak memory 225672 kb
Host smart-719a7e92-1a60-4acb-9fee-de715b8551ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136238708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.4136238708
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.789045831
Short name T430
Test name
Test status
Simulation time 874266675 ps
CPU time 12.77 seconds
Started Jul 12 04:43:39 PM PDT 24
Finished Jul 12 04:43:53 PM PDT 24
Peak memory 217632 kb
Host smart-566ed606-7963-440d-87f2-64f9a82c49d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789045831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.789045831
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.797440333
Short name T370
Test name
Test status
Simulation time 290518550 ps
CPU time 10.98 seconds
Started Jul 12 04:43:35 PM PDT 24
Finished Jul 12 04:43:47 PM PDT 24
Peak memory 217676 kb
Host smart-593e9781-c422-4af3-90ca-a13286dc5863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797440333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.797440333
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.42526923
Short name T863
Test name
Test status
Simulation time 204906252 ps
CPU time 3.49 seconds
Started Jul 12 04:43:40 PM PDT 24
Finished Jul 12 04:43:45 PM PDT 24
Peak memory 217116 kb
Host smart-4319ded8-8f8c-4576-941d-082d61141b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42526923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.42526923
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1288817184
Short name T295
Test name
Test status
Simulation time 146164105 ps
CPU time 18.67 seconds
Started Jul 12 04:43:32 PM PDT 24
Finished Jul 12 04:43:52 PM PDT 24
Peak memory 250464 kb
Host smart-9d6c6df1-1b68-4774-b51c-d4d101e62ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288817184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1288817184
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.921905498
Short name T350
Test name
Test status
Simulation time 209510284 ps
CPU time 6.33 seconds
Started Jul 12 04:43:31 PM PDT 24
Finished Jul 12 04:43:39 PM PDT 24
Peak memory 246884 kb
Host smart-b871406a-1c76-4922-8411-bdb6b6a06782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921905498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.921905498
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1566830802
Short name T241
Test name
Test status
Simulation time 2463228777 ps
CPU time 39.97 seconds
Started Jul 12 04:43:38 PM PDT 24
Finished Jul 12 04:44:20 PM PDT 24
Peak memory 250640 kb
Host smart-06f2e49c-10a5-4c90-a7cd-6cfdc855aced
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566830802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1566830802
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1891071443
Short name T41
Test name
Test status
Simulation time 17069312 ps
CPU time 1.05 seconds
Started Jul 12 04:43:32 PM PDT 24
Finished Jul 12 04:43:35 PM PDT 24
Peak memory 217216 kb
Host smart-fcf344b6-cb15-4978-bd95-a0581b7e76ef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891071443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1891071443
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.674416956
Short name T776
Test name
Test status
Simulation time 46611691 ps
CPU time 1 seconds
Started Jul 12 04:43:40 PM PDT 24
Finished Jul 12 04:43:42 PM PDT 24
Peak memory 208480 kb
Host smart-cb8dba43-e525-4b7f-bb8f-303f677466b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674416956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.674416956
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2823829729
Short name T536
Test name
Test status
Simulation time 306477626 ps
CPU time 9.93 seconds
Started Jul 12 04:43:39 PM PDT 24
Finished Jul 12 04:43:50 PM PDT 24
Peak memory 217716 kb
Host smart-4f254eb7-81fc-4f74-a054-9f9d7f92675a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823829729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2823829729
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1532594926
Short name T376
Test name
Test status
Simulation time 1136770119 ps
CPU time 14.46 seconds
Started Jul 12 04:43:40 PM PDT 24
Finished Jul 12 04:43:56 PM PDT 24
Peak memory 216832 kb
Host smart-b1cfb2d8-4bdb-4d97-8b0d-5fe49fe83fb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532594926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1532594926
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.263001984
Short name T435
Test name
Test status
Simulation time 2550996361 ps
CPU time 72.18 seconds
Started Jul 12 04:43:38 PM PDT 24
Finished Jul 12 04:44:51 PM PDT 24
Peak memory 218844 kb
Host smart-16518b2d-9dd0-4726-97e2-52403cdf86ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263001984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.263001984
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.2043566650
Short name T711
Test name
Test status
Simulation time 1839548963 ps
CPU time 6.87 seconds
Started Jul 12 04:43:37 PM PDT 24
Finished Jul 12 04:43:46 PM PDT 24
Peak memory 223540 kb
Host smart-ee688df7-19e9-416e-bde6-9b5f11ec4c17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043566650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.2043566650
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2318028565
Short name T421
Test name
Test status
Simulation time 340329172 ps
CPU time 3.81 seconds
Started Jul 12 04:43:39 PM PDT 24
Finished Jul 12 04:43:44 PM PDT 24
Peak memory 216992 kb
Host smart-8b34d0c2-3b93-49c7-8c2a-81afee03c93e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318028565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2318028565
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2940138759
Short name T251
Test name
Test status
Simulation time 2863524606 ps
CPU time 52.68 seconds
Started Jul 12 04:43:41 PM PDT 24
Finished Jul 12 04:44:35 PM PDT 24
Peak memory 275056 kb
Host smart-d9e101f1-5788-4c57-812d-6a44a138fda6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940138759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2940138759
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.207062753
Short name T491
Test name
Test status
Simulation time 1282746684 ps
CPU time 13.52 seconds
Started Jul 12 04:43:40 PM PDT 24
Finished Jul 12 04:43:55 PM PDT 24
Peak memory 246040 kb
Host smart-fad8b2ab-90c4-41f4-a1c0-0420609c92a2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207062753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.207062753
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1736895392
Short name T851
Test name
Test status
Simulation time 73101833 ps
CPU time 3.11 seconds
Started Jul 12 04:43:37 PM PDT 24
Finished Jul 12 04:43:42 PM PDT 24
Peak memory 217684 kb
Host smart-35a4656e-3172-4044-8531-7a0ded9c60d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736895392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1736895392
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.2797986460
Short name T335
Test name
Test status
Simulation time 294138106 ps
CPU time 15.16 seconds
Started Jul 12 04:43:38 PM PDT 24
Finished Jul 12 04:43:54 PM PDT 24
Peak memory 218292 kb
Host smart-3a967ec9-614f-4258-83d6-1f791543785e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797986460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2797986460
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2134430824
Short name T305
Test name
Test status
Simulation time 3214769846 ps
CPU time 6.38 seconds
Started Jul 12 04:43:35 PM PDT 24
Finished Jul 12 04:43:42 PM PDT 24
Peak memory 225440 kb
Host smart-7dc3e33e-7fc2-4543-8bbd-0f3ae956448c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134430824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2134430824
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2288359003
Short name T840
Test name
Test status
Simulation time 676584712 ps
CPU time 11.87 seconds
Started Jul 12 04:43:38 PM PDT 24
Finished Jul 12 04:43:51 PM PDT 24
Peak memory 225500 kb
Host smart-eadb324a-62e8-4f0a-9ad3-980cfa6e96b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288359003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2288359003
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.87754745
Short name T257
Test name
Test status
Simulation time 135124606 ps
CPU time 2.48 seconds
Started Jul 12 04:43:39 PM PDT 24
Finished Jul 12 04:43:42 PM PDT 24
Peak memory 213892 kb
Host smart-f79fd458-50cb-47c2-ad70-13f15fd84e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87754745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.87754745
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1013356113
Short name T862
Test name
Test status
Simulation time 406571376 ps
CPU time 25.56 seconds
Started Jul 12 04:43:37 PM PDT 24
Finished Jul 12 04:44:03 PM PDT 24
Peak memory 250372 kb
Host smart-25821828-5846-4c2b-ab08-710bf88cc284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013356113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1013356113
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.1068656101
Short name T215
Test name
Test status
Simulation time 109052109 ps
CPU time 7.11 seconds
Started Jul 12 04:43:41 PM PDT 24
Finished Jul 12 04:43:50 PM PDT 24
Peak memory 249896 kb
Host smart-f1bc4194-8e58-4239-a956-13b9c87bc904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068656101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1068656101
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.283896814
Short name T582
Test name
Test status
Simulation time 11127612664 ps
CPU time 120.14 seconds
Started Jul 12 04:43:38 PM PDT 24
Finished Jul 12 04:45:39 PM PDT 24
Peak memory 267624 kb
Host smart-b787470d-9853-4c2e-989c-79f615cb2874
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283896814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.283896814
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.1921472025
Short name T747
Test name
Test status
Simulation time 20066865362 ps
CPU time 493.79 seconds
Started Jul 12 04:43:36 PM PDT 24
Finished Jul 12 04:51:51 PM PDT 24
Peak memory 310224 kb
Host smart-5ae8b84b-d873-4624-ae83-c1a6ab5917e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1921472025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.1921472025
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2896748374
Short name T735
Test name
Test status
Simulation time 21712874 ps
CPU time 0.8 seconds
Started Jul 12 04:43:41 PM PDT 24
Finished Jul 12 04:43:43 PM PDT 24
Peak memory 208296 kb
Host smart-72d40b37-12e0-4559-8b32-4d445db7af38
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896748374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.2896748374
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2257331624
Short name T688
Test name
Test status
Simulation time 205193025 ps
CPU time 1.28 seconds
Started Jul 12 04:43:48 PM PDT 24
Finished Jul 12 04:43:52 PM PDT 24
Peak memory 208380 kb
Host smart-4431b34e-c113-4a86-8097-4422cd45839f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257331624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2257331624
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2272451584
Short name T791
Test name
Test status
Simulation time 314754875 ps
CPU time 10.27 seconds
Started Jul 12 04:43:47 PM PDT 24
Finished Jul 12 04:43:59 PM PDT 24
Peak memory 225448 kb
Host smart-64ba7fd4-3122-4291-8a12-12232ceb6a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272451584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2272451584
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1616968531
Short name T6
Test name
Test status
Simulation time 580123150 ps
CPU time 2.34 seconds
Started Jul 12 04:43:46 PM PDT 24
Finished Jul 12 04:43:50 PM PDT 24
Peak memory 216516 kb
Host smart-3430fe78-7163-473e-9f48-31779e174123
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616968531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1616968531
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3821496410
Short name T222
Test name
Test status
Simulation time 12908069951 ps
CPU time 42.76 seconds
Started Jul 12 04:43:44 PM PDT 24
Finished Jul 12 04:44:27 PM PDT 24
Peak memory 217948 kb
Host smart-d09eeea9-1c2f-4379-8713-d6ea4668c4ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821496410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3821496410
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.4262261598
Short name T283
Test name
Test status
Simulation time 957919935 ps
CPU time 5.59 seconds
Started Jul 12 04:43:47 PM PDT 24
Finished Jul 12 04:43:55 PM PDT 24
Peak memory 222320 kb
Host smart-0638997e-8d7d-42b4-9eaa-2173539cb826
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262261598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.4262261598
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1058562955
Short name T618
Test name
Test status
Simulation time 403383824 ps
CPU time 1.84 seconds
Started Jul 12 04:43:48 PM PDT 24
Finished Jul 12 04:43:52 PM PDT 24
Peak memory 217036 kb
Host smart-1dee0e9d-0097-40e0-9e45-875f40df9ad8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058562955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1058562955
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3051828557
Short name T291
Test name
Test status
Simulation time 956539428 ps
CPU time 42.24 seconds
Started Jul 12 04:43:47 PM PDT 24
Finished Jul 12 04:44:31 PM PDT 24
Peak memory 250384 kb
Host smart-f5f6b6d2-7532-4c13-b797-796ff57414b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051828557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3051828557
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2424507961
Short name T718
Test name
Test status
Simulation time 840792577 ps
CPU time 13.77 seconds
Started Jul 12 04:43:49 PM PDT 24
Finished Jul 12 04:44:06 PM PDT 24
Peak memory 222708 kb
Host smart-d8877429-4482-4536-8785-486f199aac15
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424507961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2424507961
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2000696625
Short name T820
Test name
Test status
Simulation time 348833519 ps
CPU time 4.67 seconds
Started Jul 12 04:43:44 PM PDT 24
Finished Jul 12 04:43:49 PM PDT 24
Peak memory 217640 kb
Host smart-4fb038f4-ff22-415b-92df-021e2ade1de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000696625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2000696625
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1698242492
Short name T364
Test name
Test status
Simulation time 283793129 ps
CPU time 10.01 seconds
Started Jul 12 04:44:02 PM PDT 24
Finished Jul 12 04:44:19 PM PDT 24
Peak memory 218360 kb
Host smart-74785fab-ee3f-4a7f-8772-e129ecb7a724
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698242492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1698242492
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.497558992
Short name T411
Test name
Test status
Simulation time 316768863 ps
CPU time 12.29 seconds
Started Jul 12 04:43:47 PM PDT 24
Finished Jul 12 04:44:02 PM PDT 24
Peak memory 225400 kb
Host smart-75b23b64-b374-4448-9188-f31cf5515a44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497558992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_di
gest.497558992
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.36287685
Short name T298
Test name
Test status
Simulation time 777827427 ps
CPU time 6.94 seconds
Started Jul 12 04:43:52 PM PDT 24
Finished Jul 12 04:44:03 PM PDT 24
Peak memory 223988 kb
Host smart-5808fc12-85b6-411f-88d3-5c9e5f6a08a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36287685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.36287685
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3881871625
Short name T721
Test name
Test status
Simulation time 560514450 ps
CPU time 8.72 seconds
Started Jul 12 04:43:47 PM PDT 24
Finished Jul 12 04:43:58 PM PDT 24
Peak memory 225444 kb
Host smart-d6145f3d-8004-4137-b71e-518c5f242de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881871625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3881871625
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2283182127
Short name T837
Test name
Test status
Simulation time 96878838 ps
CPU time 3.18 seconds
Started Jul 12 04:43:41 PM PDT 24
Finished Jul 12 04:43:46 PM PDT 24
Peak memory 217140 kb
Host smart-c0d137f7-2814-4d59-b0f7-c34d2ef63eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283182127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2283182127
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2222643452
Short name T658
Test name
Test status
Simulation time 302956004 ps
CPU time 35.39 seconds
Started Jul 12 04:43:37 PM PDT 24
Finished Jul 12 04:44:13 PM PDT 24
Peak memory 250352 kb
Host smart-0c8ab0e2-f1dc-4be5-a466-b36051356766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222643452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2222643452
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2596452434
Short name T351
Test name
Test status
Simulation time 350416835 ps
CPU time 8.4 seconds
Started Jul 12 04:43:48 PM PDT 24
Finished Jul 12 04:44:00 PM PDT 24
Peak memory 250484 kb
Host smart-9f91a4e6-a06e-4313-9ca1-460e16f9593b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596452434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2596452434
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.1928725871
Short name T434
Test name
Test status
Simulation time 10932933150 ps
CPU time 87.31 seconds
Started Jul 12 04:43:45 PM PDT 24
Finished Jul 12 04:45:13 PM PDT 24
Peak memory 250396 kb
Host smart-fb4ab8ea-0437-4435-ae11-1738ba130cd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928725871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.1928725871
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.4262383127
Short name T147
Test name
Test status
Simulation time 12103386715 ps
CPU time 402.93 seconds
Started Jul 12 04:43:45 PM PDT 24
Finished Jul 12 04:50:29 PM PDT 24
Peak memory 267020 kb
Host smart-02fe089d-32ab-4fde-b01d-c9577beb9c0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4262383127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.4262383127
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.778456976
Short name T501
Test name
Test status
Simulation time 23663770 ps
CPU time 0.75 seconds
Started Jul 12 04:43:40 PM PDT 24
Finished Jul 12 04:43:42 PM PDT 24
Peak memory 206572 kb
Host smart-356776e7-153a-4f44-92ef-b0cda5deb107
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778456976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.778456976
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3415839072
Short name T441
Test name
Test status
Simulation time 23630502 ps
CPU time 0.79 seconds
Started Jul 12 04:43:50 PM PDT 24
Finished Jul 12 04:43:54 PM PDT 24
Peak memory 208340 kb
Host smart-960a8cac-e16e-43b5-af48-46e330664e9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415839072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3415839072
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2093732082
Short name T530
Test name
Test status
Simulation time 300112487 ps
CPU time 15.61 seconds
Started Jul 12 04:43:45 PM PDT 24
Finished Jul 12 04:44:02 PM PDT 24
Peak memory 217600 kb
Host smart-8b47c199-2c14-48b6-9f7b-ea0f55323029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093732082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2093732082
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3207980312
Short name T728
Test name
Test status
Simulation time 513652165 ps
CPU time 5.76 seconds
Started Jul 12 04:43:54 PM PDT 24
Finished Jul 12 04:44:04 PM PDT 24
Peak memory 216868 kb
Host smart-b475076c-7900-4ac6-be35-fe43378e5f57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207980312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3207980312
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.116667147
Short name T46
Test name
Test status
Simulation time 19266101627 ps
CPU time 54.86 seconds
Started Jul 12 04:43:51 PM PDT 24
Finished Jul 12 04:44:49 PM PDT 24
Peak memory 218660 kb
Host smart-7115fbf3-90c4-4004-b62f-1c019b0fdd11
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116667147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.116667147
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.640836172
Short name T450
Test name
Test status
Simulation time 1580753762 ps
CPU time 7.04 seconds
Started Jul 12 04:43:46 PM PDT 24
Finished Jul 12 04:43:54 PM PDT 24
Peak memory 217640 kb
Host smart-642837ab-2967-4118-9eb0-f8327b0effb1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640836172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.640836172
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2450718889
Short name T252
Test name
Test status
Simulation time 287496896 ps
CPU time 5.54 seconds
Started Jul 12 04:43:47 PM PDT 24
Finished Jul 12 04:43:53 PM PDT 24
Peak memory 216980 kb
Host smart-d61cce6b-6611-45bf-bd4d-5dd2887be2a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450718889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2450718889
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1047300523
Short name T652
Test name
Test status
Simulation time 6166917475 ps
CPU time 61.54 seconds
Started Jul 12 04:43:48 PM PDT 24
Finished Jul 12 04:44:52 PM PDT 24
Peak memory 275008 kb
Host smart-f1522c09-c5e1-44ee-a14a-d913502d02da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047300523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1047300523
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.131815908
Short name T445
Test name
Test status
Simulation time 3914866877 ps
CPU time 29.57 seconds
Started Jul 12 04:43:48 PM PDT 24
Finished Jul 12 04:44:20 PM PDT 24
Peak memory 245600 kb
Host smart-f29a51cf-5f91-47ed-af5e-3e145a39625f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131815908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
jtag_state_post_trans.131815908
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.39765522
Short name T583
Test name
Test status
Simulation time 97314181 ps
CPU time 3.39 seconds
Started Jul 12 04:43:45 PM PDT 24
Finished Jul 12 04:43:50 PM PDT 24
Peak memory 217620 kb
Host smart-1d85358e-ff79-49cc-bcf0-7410be40c248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39765522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.39765522
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.601846297
Short name T560
Test name
Test status
Simulation time 1146110096 ps
CPU time 16.24 seconds
Started Jul 12 04:43:52 PM PDT 24
Finished Jul 12 04:44:12 PM PDT 24
Peak memory 218296 kb
Host smart-007a9795-9cb7-427f-9d1c-39da9467f972
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601846297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.601846297
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.981905921
Short name T336
Test name
Test status
Simulation time 881725060 ps
CPU time 11.01 seconds
Started Jul 12 04:43:50 PM PDT 24
Finished Jul 12 04:44:04 PM PDT 24
Peak memory 225416 kb
Host smart-a74b525b-b75d-4ad0-83c5-20e5112f9943
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981905921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.981905921
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1296956697
Short name T476
Test name
Test status
Simulation time 2577640776 ps
CPU time 11.86 seconds
Started Jul 12 04:43:50 PM PDT 24
Finished Jul 12 04:44:05 PM PDT 24
Peak memory 217676 kb
Host smart-1b8b18ba-2a38-4315-ae70-60eb9c2d102c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296956697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1296956697
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.17294900
Short name T605
Test name
Test status
Simulation time 2280390753 ps
CPU time 13.52 seconds
Started Jul 12 04:43:45 PM PDT 24
Finished Jul 12 04:44:00 PM PDT 24
Peak memory 217892 kb
Host smart-8c05763c-3019-4582-9574-00741221f81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17294900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.17294900
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1867079514
Short name T319
Test name
Test status
Simulation time 31921621 ps
CPU time 1.66 seconds
Started Jul 12 04:43:44 PM PDT 24
Finished Jul 12 04:43:47 PM PDT 24
Peak memory 213612 kb
Host smart-c5121edc-7f2e-4088-978e-2c25fac81302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867079514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1867079514
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3004826357
Short name T384
Test name
Test status
Simulation time 879417170 ps
CPU time 24.09 seconds
Started Jul 12 04:43:48 PM PDT 24
Finished Jul 12 04:44:14 PM PDT 24
Peak memory 250440 kb
Host smart-6cc5448b-d81e-4c67-a442-c9f163de4c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004826357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3004826357
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2961297495
Short name T642
Test name
Test status
Simulation time 766559109 ps
CPU time 6.25 seconds
Started Jul 12 04:43:47 PM PDT 24
Finished Jul 12 04:43:54 PM PDT 24
Peak memory 246024 kb
Host smart-e1491e12-c098-4154-b86e-ebad9b613b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961297495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2961297495
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2497935597
Short name T170
Test name
Test status
Simulation time 7841688330 ps
CPU time 39.62 seconds
Started Jul 12 04:44:00 PM PDT 24
Finished Jul 12 04:44:48 PM PDT 24
Peak memory 250496 kb
Host smart-2a8aaf9c-3a06-4154-8840-bbc0a52295f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497935597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2497935597
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2456277473
Short name T378
Test name
Test status
Simulation time 145313807 ps
CPU time 0.86 seconds
Started Jul 12 04:43:47 PM PDT 24
Finished Jul 12 04:43:50 PM PDT 24
Peak memory 211216 kb
Host smart-2bc45451-9aa2-47e6-a809-d1ee70ce9ad1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456277473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2456277473
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2347059516
Short name T159
Test name
Test status
Simulation time 50330260 ps
CPU time 0.88 seconds
Started Jul 12 04:43:53 PM PDT 24
Finished Jul 12 04:43:58 PM PDT 24
Peak memory 208440 kb
Host smart-7f1e1488-5ecc-42e1-b1fb-dc3144d976e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347059516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2347059516
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3852242093
Short name T727
Test name
Test status
Simulation time 1693579366 ps
CPU time 18.18 seconds
Started Jul 12 04:43:54 PM PDT 24
Finished Jul 12 04:44:17 PM PDT 24
Peak memory 225468 kb
Host smart-97f97173-bb74-44f9-b6da-064c7bb93209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852242093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3852242093
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.4140489273
Short name T394
Test name
Test status
Simulation time 1032438051 ps
CPU time 5.77 seconds
Started Jul 12 04:43:54 PM PDT 24
Finished Jul 12 04:44:05 PM PDT 24
Peak memory 216764 kb
Host smart-4d7ba361-17e2-4cc9-849f-b056aa91df1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140489273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.4140489273
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1806026116
Short name T292
Test name
Test status
Simulation time 13225895278 ps
CPU time 81.7 seconds
Started Jul 12 04:43:51 PM PDT 24
Finished Jul 12 04:45:16 PM PDT 24
Peak memory 218504 kb
Host smart-36ebf53f-ae21-480d-b33b-252c53b04eb2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806026116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1806026116
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3376046232
Short name T489
Test name
Test status
Simulation time 994111390 ps
CPU time 5.11 seconds
Started Jul 12 04:43:51 PM PDT 24
Finished Jul 12 04:43:59 PM PDT 24
Peak memory 217560 kb
Host smart-60adc287-8230-4e65-9583-827fbb8a59dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376046232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.3376046232
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3865112639
Short name T533
Test name
Test status
Simulation time 115293459 ps
CPU time 1.57 seconds
Started Jul 12 04:43:51 PM PDT 24
Finished Jul 12 04:43:56 PM PDT 24
Peak memory 217052 kb
Host smart-22a425b3-9dae-4e6d-a8ec-21ebc418471c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865112639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3865112639
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1329213001
Short name T519
Test name
Test status
Simulation time 2349800264 ps
CPU time 54.15 seconds
Started Jul 12 04:43:55 PM PDT 24
Finished Jul 12 04:44:54 PM PDT 24
Peak memory 275136 kb
Host smart-5b5018e1-81ac-4beb-be32-da464772d053
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329213001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1329213001
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2794483437
Short name T15
Test name
Test status
Simulation time 388258421 ps
CPU time 15.48 seconds
Started Jul 12 04:43:52 PM PDT 24
Finished Jul 12 04:44:11 PM PDT 24
Peak memory 250296 kb
Host smart-ba97f6fb-26be-4d35-aa14-1c4e227fb8aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794483437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2794483437
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.517645269
Short name T726
Test name
Test status
Simulation time 62826708 ps
CPU time 1.93 seconds
Started Jul 12 04:43:56 PM PDT 24
Finished Jul 12 04:44:05 PM PDT 24
Peak memory 217620 kb
Host smart-f692d7ce-acb8-4d4d-94a4-2ed93ef323d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517645269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.517645269
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3706545856
Short name T289
Test name
Test status
Simulation time 353270719 ps
CPU time 15.09 seconds
Started Jul 12 04:43:51 PM PDT 24
Finished Jul 12 04:44:09 PM PDT 24
Peak memory 218316 kb
Host smart-ef632f13-2b99-4045-a6b7-8ca776cdb492
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706545856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3706545856
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2525490176
Short name T163
Test name
Test status
Simulation time 1629632783 ps
CPU time 8.79 seconds
Started Jul 12 04:43:52 PM PDT 24
Finished Jul 12 04:44:04 PM PDT 24
Peak memory 225468 kb
Host smart-ff27e2b7-b477-4867-8387-87a5cd693897
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525490176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2525490176
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3854474016
Short name T55
Test name
Test status
Simulation time 698514298 ps
CPU time 7.34 seconds
Started Jul 12 04:43:56 PM PDT 24
Finished Jul 12 04:44:11 PM PDT 24
Peak memory 217264 kb
Host smart-d6fd1b65-fe1b-448f-9da8-c8790794ec59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854474016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
3854474016
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2432064530
Short name T612
Test name
Test status
Simulation time 492771010 ps
CPU time 16.62 seconds
Started Jul 12 04:43:51 PM PDT 24
Finished Jul 12 04:44:11 PM PDT 24
Peak memory 225520 kb
Host smart-6ff6f9b1-181d-4f26-a13b-b673cd5bc11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432064530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2432064530
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.12121303
Short name T732
Test name
Test status
Simulation time 83178452 ps
CPU time 3.07 seconds
Started Jul 12 04:43:50 PM PDT 24
Finished Jul 12 04:43:56 PM PDT 24
Peak memory 214292 kb
Host smart-3a65a34e-bb2e-4845-825f-ef85916d87cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12121303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.12121303
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2530672375
Short name T366
Test name
Test status
Simulation time 3483028589 ps
CPU time 29.03 seconds
Started Jul 12 04:43:50 PM PDT 24
Finished Jul 12 04:44:22 PM PDT 24
Peak memory 250512 kb
Host smart-9c4e1044-7859-4f66-9075-8ed8b452e2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530672375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2530672375
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1929681803
Short name T254
Test name
Test status
Simulation time 185205488 ps
CPU time 5.03 seconds
Started Jul 12 04:43:53 PM PDT 24
Finished Jul 12 04:44:03 PM PDT 24
Peak memory 222108 kb
Host smart-e7299d0b-7d96-4f18-847c-69b9ce9c5bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929681803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1929681803
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.4249848641
Short name T70
Test name
Test status
Simulation time 7314464740 ps
CPU time 64.89 seconds
Started Jul 12 04:44:00 PM PDT 24
Finished Jul 12 04:45:12 PM PDT 24
Peak memory 250504 kb
Host smart-a8d5f7ab-6101-470b-bc17-93d94bcfdbbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249848641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.4249848641
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2138138767
Short name T146
Test name
Test status
Simulation time 10755915334 ps
CPU time 374.24 seconds
Started Jul 12 04:43:55 PM PDT 24
Finished Jul 12 04:50:15 PM PDT 24
Peak memory 280372 kb
Host smart-a6b907b1-d5a2-432a-b922-32d388066cea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2138138767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.2138138767
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3446390763
Short name T763
Test name
Test status
Simulation time 15165811 ps
CPU time 1.16 seconds
Started Jul 12 04:43:52 PM PDT 24
Finished Jul 12 04:43:57 PM PDT 24
Peak memory 211388 kb
Host smart-b0cf8aae-c875-4d04-89ec-e9172072bce4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446390763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3446390763
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1654184998
Short name T452
Test name
Test status
Simulation time 38527986 ps
CPU time 1.16 seconds
Started Jul 12 04:42:49 PM PDT 24
Finished Jul 12 04:42:53 PM PDT 24
Peak memory 208468 kb
Host smart-8b8e0af3-ef9f-4452-a8c2-43426f7e04fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654184998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1654184998
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1294282553
Short name T487
Test name
Test status
Simulation time 1473383318 ps
CPU time 12.48 seconds
Started Jul 12 04:42:50 PM PDT 24
Finished Jul 12 04:43:05 PM PDT 24
Peak memory 225468 kb
Host smart-227f3d0f-c3eb-482a-b65b-1e48d89f4a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294282553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1294282553
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.194006447
Short name T23
Test name
Test status
Simulation time 2495873599 ps
CPU time 15.48 seconds
Started Jul 12 04:42:50 PM PDT 24
Finished Jul 12 04:43:08 PM PDT 24
Peak memory 217192 kb
Host smart-5c2e3460-99c8-4ff1-a4ee-55b8ac31a9ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194006447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.194006447
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1103566564
Short name T660
Test name
Test status
Simulation time 18070510861 ps
CPU time 63.16 seconds
Started Jul 12 04:42:49 PM PDT 24
Finished Jul 12 04:43:55 PM PDT 24
Peak memory 218308 kb
Host smart-1702ca8a-cada-4b8e-8168-b2598b36171e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103566564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1103566564
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1139062048
Short name T380
Test name
Test status
Simulation time 616378931 ps
CPU time 6.19 seconds
Started Jul 12 04:42:46 PM PDT 24
Finished Jul 12 04:42:54 PM PDT 24
Peak memory 217152 kb
Host smart-0a414afb-64b5-4478-8e59-1e3bdb3a4549
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139062048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
139062048
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1174637114
Short name T514
Test name
Test status
Simulation time 1544466915 ps
CPU time 6.36 seconds
Started Jul 12 04:42:47 PM PDT 24
Finished Jul 12 04:42:56 PM PDT 24
Peak memory 222580 kb
Host smart-01a56533-5bce-491c-98f1-4915872c71b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174637114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.1174637114
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1391380742
Short name T631
Test name
Test status
Simulation time 748875496 ps
CPU time 20.28 seconds
Started Jul 12 04:42:49 PM PDT 24
Finished Jul 12 04:43:12 PM PDT 24
Peak memory 217068 kb
Host smart-4a9342aa-cb7f-4917-953b-170898aea12b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391380742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1391380742
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.318121385
Short name T419
Test name
Test status
Simulation time 169152217 ps
CPU time 5.68 seconds
Started Jul 12 04:42:49 PM PDT 24
Finished Jul 12 04:42:58 PM PDT 24
Peak memory 217088 kb
Host smart-220d06ad-c403-482e-b1b9-8046693adac2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318121385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.318121385
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2582807831
Short name T673
Test name
Test status
Simulation time 1253584708 ps
CPU time 42.4 seconds
Started Jul 12 04:42:48 PM PDT 24
Finished Jul 12 04:43:33 PM PDT 24
Peak memory 266784 kb
Host smart-617a8029-20ea-4fec-be4c-e98b9d22e2dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582807831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2582807831
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2847884906
Short name T557
Test name
Test status
Simulation time 634527822 ps
CPU time 10.36 seconds
Started Jul 12 04:42:47 PM PDT 24
Finished Jul 12 04:43:00 PM PDT 24
Peak memory 217656 kb
Host smart-e86a5282-3c6a-4bc2-be4b-5371795e28aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847884906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2847884906
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.818378649
Short name T622
Test name
Test status
Simulation time 32316924 ps
CPU time 1.7 seconds
Started Jul 12 04:42:44 PM PDT 24
Finished Jul 12 04:42:48 PM PDT 24
Peak memory 217684 kb
Host smart-5bc4293c-3508-4a23-aa32-5f99914e8e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818378649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.818378649
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.730288015
Short name T467
Test name
Test status
Simulation time 276738206 ps
CPU time 8.19 seconds
Started Jul 12 04:42:52 PM PDT 24
Finished Jul 12 04:43:01 PM PDT 24
Peak memory 213984 kb
Host smart-70a17ca4-c209-4d81-a20e-0330548f2559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730288015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.730288015
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.8143351
Short name T607
Test name
Test status
Simulation time 926703561 ps
CPU time 10.8 seconds
Started Jul 12 04:42:50 PM PDT 24
Finished Jul 12 04:43:03 PM PDT 24
Peak memory 225520 kb
Host smart-0faae974-2cf5-497d-b466-f822a447df6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8143351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.8143351
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2170644999
Short name T635
Test name
Test status
Simulation time 308428115 ps
CPU time 9.34 seconds
Started Jul 12 04:42:52 PM PDT 24
Finished Jul 12 04:43:02 PM PDT 24
Peak memory 225420 kb
Host smart-ae5f1698-e21e-48ca-b0ee-445bf67397ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170644999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2170644999
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.790677617
Short name T224
Test name
Test status
Simulation time 248183186 ps
CPU time 9.24 seconds
Started Jul 12 04:42:50 PM PDT 24
Finished Jul 12 04:43:02 PM PDT 24
Peak memory 217552 kb
Host smart-e31ccc58-95e5-49a2-b2df-c3d91dde1baa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790677617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.790677617
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.300314999
Short name T805
Test name
Test status
Simulation time 436518028 ps
CPU time 3.29 seconds
Started Jul 12 04:42:43 PM PDT 24
Finished Jul 12 04:42:49 PM PDT 24
Peak memory 217052 kb
Host smart-e6f657f7-7700-4c1d-8d16-bb3c910e1e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300314999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.300314999
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.90578027
Short name T451
Test name
Test status
Simulation time 1326122288 ps
CPU time 29.58 seconds
Started Jul 12 04:42:41 PM PDT 24
Finished Jul 12 04:43:12 PM PDT 24
Peak memory 250476 kb
Host smart-2ff785af-df95-4142-b86f-28f3a6e4291c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90578027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.90578027
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1765910093
Short name T749
Test name
Test status
Simulation time 298124979 ps
CPU time 4.09 seconds
Started Jul 12 04:42:43 PM PDT 24
Finished Jul 12 04:42:49 PM PDT 24
Peak memory 223752 kb
Host smart-093e418c-66d1-4a55-8bea-ba1597e7ce7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765910093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1765910093
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.3980814914
Short name T869
Test name
Test status
Simulation time 692047291 ps
CPU time 48.39 seconds
Started Jul 12 04:42:50 PM PDT 24
Finished Jul 12 04:43:41 PM PDT 24
Peak memory 250228 kb
Host smart-d8f70fb7-0036-4e07-b612-00209c414ac6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980814914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.3980814914
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3439437959
Short name T700
Test name
Test status
Simulation time 15758998 ps
CPU time 1.2 seconds
Started Jul 12 04:42:43 PM PDT 24
Finished Jul 12 04:42:46 PM PDT 24
Peak memory 211380 kb
Host smart-9a9c1b78-6c5b-43e7-b3dc-c15181182762
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439437959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3439437959
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1859005126
Short name T563
Test name
Test status
Simulation time 185401728 ps
CPU time 1.13 seconds
Started Jul 12 04:43:56 PM PDT 24
Finished Jul 12 04:44:04 PM PDT 24
Peak memory 208436 kb
Host smart-8b95b48b-479b-493d-a0cf-8cae9e37d48c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859005126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1859005126
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2190573756
Short name T44
Test name
Test status
Simulation time 1842027171 ps
CPU time 10.3 seconds
Started Jul 12 04:43:52 PM PDT 24
Finished Jul 12 04:44:07 PM PDT 24
Peak memory 217704 kb
Host smart-5fe5a5fb-8f9f-4deb-a2ec-56c4f5a0315f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190573756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2190573756
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.5846322
Short name T98
Test name
Test status
Simulation time 292841334 ps
CPU time 4.15 seconds
Started Jul 12 04:43:52 PM PDT 24
Finished Jul 12 04:43:59 PM PDT 24
Peak memory 217100 kb
Host smart-fbc1eef7-1b7e-4317-a5e5-c8f1d8a53a22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5846322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.5846322
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.860564322
Short name T102
Test name
Test status
Simulation time 67785948 ps
CPU time 2.65 seconds
Started Jul 12 04:43:54 PM PDT 24
Finished Jul 12 04:44:02 PM PDT 24
Peak memory 217628 kb
Host smart-11e4ca3b-9bb0-445a-a73c-0c0dd5b3fc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860564322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.860564322
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.3187580725
Short name T798
Test name
Test status
Simulation time 1645832918 ps
CPU time 16.25 seconds
Started Jul 12 04:43:56 PM PDT 24
Finished Jul 12 04:44:19 PM PDT 24
Peak memory 219308 kb
Host smart-9018b461-d1c7-4d33-954e-e434694aa76c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187580725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3187580725
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.589548960
Short name T708
Test name
Test status
Simulation time 655576776 ps
CPU time 26.25 seconds
Started Jul 12 04:43:54 PM PDT 24
Finished Jul 12 04:44:26 PM PDT 24
Peak memory 225368 kb
Host smart-b92f8e5d-5c4e-48b0-a779-0681a4fa2f8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589548960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.589548960
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2444470126
Short name T504
Test name
Test status
Simulation time 584350411 ps
CPU time 11.99 seconds
Started Jul 12 04:43:55 PM PDT 24
Finished Jul 12 04:44:13 PM PDT 24
Peak memory 217636 kb
Host smart-239b72ca-a972-4095-bd15-9e109693bf11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444470126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2444470126
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3897724824
Short name T204
Test name
Test status
Simulation time 796576292 ps
CPU time 7.89 seconds
Started Jul 12 04:44:00 PM PDT 24
Finished Jul 12 04:44:16 PM PDT 24
Peak memory 225492 kb
Host smart-c608f038-fba2-45e8-92e7-d060843d53fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897724824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3897724824
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.977396070
Short name T64
Test name
Test status
Simulation time 214921864 ps
CPU time 3.41 seconds
Started Jul 12 04:43:59 PM PDT 24
Finished Jul 12 04:44:10 PM PDT 24
Peak memory 217104 kb
Host smart-42798edf-8192-4dd9-a795-992d0b7397fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977396070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.977396070
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.4011538483
Short name T680
Test name
Test status
Simulation time 584566267 ps
CPU time 20.79 seconds
Started Jul 12 04:43:51 PM PDT 24
Finished Jul 12 04:44:15 PM PDT 24
Peak memory 245360 kb
Host smart-dfb7f3aa-20c8-4128-bb28-27f4fc94d7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011538483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.4011538483
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.4142763794
Short name T495
Test name
Test status
Simulation time 577905159 ps
CPU time 6.72 seconds
Started Jul 12 04:43:55 PM PDT 24
Finished Jul 12 04:44:07 PM PDT 24
Peak memory 246056 kb
Host smart-98e53b35-c302-4c45-bbf2-6564339a93e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142763794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.4142763794
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1936939561
Short name T596
Test name
Test status
Simulation time 2795219558 ps
CPU time 72.9 seconds
Started Jul 12 04:43:56 PM PDT 24
Finished Jul 12 04:45:16 PM PDT 24
Peak memory 266588 kb
Host smart-773f1af7-76a5-4d4f-8627-034a777677b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936939561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1936939561
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.666771587
Short name T426
Test name
Test status
Simulation time 13271090 ps
CPU time 0.95 seconds
Started Jul 12 04:43:56 PM PDT 24
Finished Jul 12 04:44:04 PM PDT 24
Peak memory 210816 kb
Host smart-fd1b6097-0270-4b2e-8697-3fd91bf40c4e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666771587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.666771587
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.4072879650
Short name T381
Test name
Test status
Simulation time 59418502 ps
CPU time 1.02 seconds
Started Jul 12 04:43:57 PM PDT 24
Finished Jul 12 04:44:06 PM PDT 24
Peak memory 208544 kb
Host smart-977f22b2-90ed-42a9-b1db-d4e35295ba13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072879650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.4072879650
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3424470718
Short name T95
Test name
Test status
Simulation time 4359958951 ps
CPU time 15.4 seconds
Started Jul 12 04:43:59 PM PDT 24
Finished Jul 12 04:44:22 PM PDT 24
Peak memory 225520 kb
Host smart-53892ff8-fceb-4212-b4dc-fda111581155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424470718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3424470718
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2213405162
Short name T698
Test name
Test status
Simulation time 3407995646 ps
CPU time 8.17 seconds
Started Jul 12 04:44:01 PM PDT 24
Finished Jul 12 04:44:17 PM PDT 24
Peak memory 217128 kb
Host smart-9dcbe0f1-2790-40af-affe-733821f918d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213405162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2213405162
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.710621380
Short name T206
Test name
Test status
Simulation time 228610859 ps
CPU time 2.26 seconds
Started Jul 12 04:44:01 PM PDT 24
Finished Jul 12 04:44:11 PM PDT 24
Peak memory 217648 kb
Host smart-f076df6c-e34e-4990-a9ca-83d5ac432c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710621380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.710621380
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1492709463
Short name T696
Test name
Test status
Simulation time 413265614 ps
CPU time 9.62 seconds
Started Jul 12 04:44:02 PM PDT 24
Finished Jul 12 04:44:20 PM PDT 24
Peak memory 217860 kb
Host smart-3a01621c-5845-498f-8d88-d035b02c38ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492709463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1492709463
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.520485388
Short name T821
Test name
Test status
Simulation time 605141421 ps
CPU time 13.24 seconds
Started Jul 12 04:43:58 PM PDT 24
Finished Jul 12 04:44:18 PM PDT 24
Peak memory 225448 kb
Host smart-1afcf547-f1a1-4ffc-9b85-eb983e41bfea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520485388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_di
gest.520485388
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2027847530
Short name T277
Test name
Test status
Simulation time 248085755 ps
CPU time 9.55 seconds
Started Jul 12 04:44:00 PM PDT 24
Finished Jul 12 04:44:18 PM PDT 24
Peak memory 217656 kb
Host smart-4d45f25a-a933-402a-b85a-ca4231f3c1ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027847530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2027847530
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3288617621
Short name T339
Test name
Test status
Simulation time 44966217 ps
CPU time 2.03 seconds
Started Jul 12 04:43:59 PM PDT 24
Finished Jul 12 04:44:09 PM PDT 24
Peak memory 213676 kb
Host smart-97510e77-928d-4ae8-b098-0cbfb3b2ebe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288617621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3288617621
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3791108162
Short name T574
Test name
Test status
Simulation time 261239799 ps
CPU time 22.29 seconds
Started Jul 12 04:44:01 PM PDT 24
Finished Jul 12 04:44:31 PM PDT 24
Peak memory 246772 kb
Host smart-2fd687a1-aee9-4dd0-8f5b-65c3619ec63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791108162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3791108162
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2428405404
Short name T361
Test name
Test status
Simulation time 71951398 ps
CPU time 7.59 seconds
Started Jul 12 04:44:00 PM PDT 24
Finished Jul 12 04:44:16 PM PDT 24
Peak memory 250436 kb
Host smart-5f752c1d-d640-4ecc-b486-bfd638c13060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428405404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2428405404
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1936128564
Short name T396
Test name
Test status
Simulation time 5890475712 ps
CPU time 123.72 seconds
Started Jul 12 04:44:00 PM PDT 24
Finished Jul 12 04:46:12 PM PDT 24
Peak memory 250676 kb
Host smart-4a283455-69c9-4d0e-b615-d7d943f4f68a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936128564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1936128564
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.4238945601
Short name T377
Test name
Test status
Simulation time 14206242 ps
CPU time 0.81 seconds
Started Jul 12 04:44:00 PM PDT 24
Finished Jul 12 04:44:08 PM PDT 24
Peak memory 208512 kb
Host smart-b79ce70f-7e3b-441b-8e6f-f8942b81801c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238945601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.4238945601
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.3098981791
Short name T570
Test name
Test status
Simulation time 93030315 ps
CPU time 0.95 seconds
Started Jul 12 04:44:01 PM PDT 24
Finished Jul 12 04:44:10 PM PDT 24
Peak memory 208480 kb
Host smart-be623d03-604f-4695-bd9b-ed451359006a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098981791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3098981791
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.293065757
Short name T264
Test name
Test status
Simulation time 463562979 ps
CPU time 11.49 seconds
Started Jul 12 04:44:00 PM PDT 24
Finished Jul 12 04:44:20 PM PDT 24
Peak memory 217640 kb
Host smart-db99228b-972f-4cf5-9931-146f470e8ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293065757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.293065757
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1527476286
Short name T423
Test name
Test status
Simulation time 162224656 ps
CPU time 1.52 seconds
Started Jul 12 04:44:00 PM PDT 24
Finished Jul 12 04:44:10 PM PDT 24
Peak memory 217060 kb
Host smart-b6ccd070-ff25-4d02-8b69-ee8cb670e24f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527476286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1527476286
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1028742928
Short name T424
Test name
Test status
Simulation time 39140187 ps
CPU time 2.4 seconds
Started Jul 12 04:44:00 PM PDT 24
Finished Jul 12 04:44:10 PM PDT 24
Peak memory 217712 kb
Host smart-70282646-32c2-4c49-862c-e1c21a7f8a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028742928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1028742928
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2676857928
Short name T723
Test name
Test status
Simulation time 874079401 ps
CPU time 9.24 seconds
Started Jul 12 04:44:00 PM PDT 24
Finished Jul 12 04:44:18 PM PDT 24
Peak memory 217704 kb
Host smart-67a51c60-8922-43e3-8522-d5a7a5b93590
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676857928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2676857928
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2963142678
Short name T597
Test name
Test status
Simulation time 369302145 ps
CPU time 11.88 seconds
Started Jul 12 04:44:01 PM PDT 24
Finished Jul 12 04:44:21 PM PDT 24
Peak memory 225396 kb
Host smart-aa42ac96-7433-49b6-9c07-7194d8521670
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963142678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2963142678
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2181696906
Short name T795
Test name
Test status
Simulation time 1080693237 ps
CPU time 13.92 seconds
Started Jul 12 04:43:57 PM PDT 24
Finished Jul 12 04:44:19 PM PDT 24
Peak memory 225464 kb
Host smart-8a70eea8-5eb6-45d7-9d9c-d8e4d61333c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181696906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2181696906
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.2778278434
Short name T461
Test name
Test status
Simulation time 1211001836 ps
CPU time 12.13 seconds
Started Jul 12 04:43:57 PM PDT 24
Finished Jul 12 04:44:17 PM PDT 24
Peak memory 217704 kb
Host smart-5c2d3a37-c713-4bec-a1d5-7ece1b885506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778278434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2778278434
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.4238339205
Short name T717
Test name
Test status
Simulation time 28344329 ps
CPU time 2.04 seconds
Started Jul 12 04:43:57 PM PDT 24
Finished Jul 12 04:44:06 PM PDT 24
Peak memory 221776 kb
Host smart-dbff9608-da9b-4860-afc0-0ced20034372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238339205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.4238339205
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.598024398
Short name T288
Test name
Test status
Simulation time 1433759225 ps
CPU time 37.52 seconds
Started Jul 12 04:44:02 PM PDT 24
Finished Jul 12 04:44:48 PM PDT 24
Peak memory 247492 kb
Host smart-1639d77c-0304-4b7c-be96-d8486374dc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598024398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.598024398
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1778898960
Short name T279
Test name
Test status
Simulation time 58765631 ps
CPU time 7.58 seconds
Started Jul 12 04:44:00 PM PDT 24
Finished Jul 12 04:44:15 PM PDT 24
Peak memory 250680 kb
Host smart-bcc063ce-1938-4f47-b02f-990deaf03c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778898960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1778898960
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2608607319
Short name T365
Test name
Test status
Simulation time 1122589837 ps
CPU time 21.84 seconds
Started Jul 12 04:43:57 PM PDT 24
Finished Jul 12 04:44:27 PM PDT 24
Peak memory 218568 kb
Host smart-39cb0e25-0960-4826-b1ac-97091da3d82a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608607319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2608607319
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2211733529
Short name T297
Test name
Test status
Simulation time 11551985 ps
CPU time 0.95 seconds
Started Jul 12 04:44:00 PM PDT 24
Finished Jul 12 04:44:08 PM PDT 24
Peak memory 208572 kb
Host smart-4fb833c5-8352-497a-9087-897363371c2e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211733529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2211733529
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3536272799
Short name T766
Test name
Test status
Simulation time 75483743 ps
CPU time 1.2 seconds
Started Jul 12 04:44:00 PM PDT 24
Finished Jul 12 04:44:09 PM PDT 24
Peak memory 208372 kb
Host smart-386b7f9b-723b-4f49-8a29-24c2bbb62227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536272799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3536272799
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2733694661
Short name T492
Test name
Test status
Simulation time 1617519604 ps
CPU time 17.13 seconds
Started Jul 12 04:44:00 PM PDT 24
Finished Jul 12 04:44:24 PM PDT 24
Peak memory 217596 kb
Host smart-1e4c8454-7488-4517-8961-70489de3fb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733694661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2733694661
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3031342128
Short name T27
Test name
Test status
Simulation time 274606736 ps
CPU time 3.55 seconds
Started Jul 12 04:44:00 PM PDT 24
Finished Jul 12 04:44:12 PM PDT 24
Peak memory 216584 kb
Host smart-ed581b2b-e963-47d5-8e63-658f00a78697
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031342128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3031342128
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.61703797
Short name T778
Test name
Test status
Simulation time 131709311 ps
CPU time 2.71 seconds
Started Jul 12 04:43:57 PM PDT 24
Finished Jul 12 04:44:07 PM PDT 24
Peak memory 217700 kb
Host smart-b6a7c9bd-2969-4f24-9b01-c0b35ccf3fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61703797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.61703797
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.724437498
Short name T521
Test name
Test status
Simulation time 1936752317 ps
CPU time 12.95 seconds
Started Jul 12 04:43:57 PM PDT 24
Finished Jul 12 04:44:17 PM PDT 24
Peak memory 217956 kb
Host smart-1be80cc1-0514-4f11-8fa9-ced649c87975
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724437498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.724437498
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2685397810
Short name T706
Test name
Test status
Simulation time 504478218 ps
CPU time 13.76 seconds
Started Jul 12 04:43:59 PM PDT 24
Finished Jul 12 04:44:20 PM PDT 24
Peak memory 225388 kb
Host smart-951f77fc-dc9d-4847-b463-4b7625c6440d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685397810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2685397810
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.119925871
Short name T458
Test name
Test status
Simulation time 1548465393 ps
CPU time 10.07 seconds
Started Jul 12 04:44:03 PM PDT 24
Finished Jul 12 04:44:21 PM PDT 24
Peak memory 225444 kb
Host smart-6772fc2a-0a79-486c-a076-2d5688d7b677
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119925871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.119925871
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1815702798
Short name T839
Test name
Test status
Simulation time 480204741 ps
CPU time 7.38 seconds
Started Jul 12 04:44:00 PM PDT 24
Finished Jul 12 04:44:16 PM PDT 24
Peak memory 224148 kb
Host smart-8f3389b4-abc5-4b9b-86c3-dc2d75430a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815702798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1815702798
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.496795908
Short name T833
Test name
Test status
Simulation time 27445677 ps
CPU time 1.98 seconds
Started Jul 12 04:44:01 PM PDT 24
Finished Jul 12 04:44:11 PM PDT 24
Peak memory 213792 kb
Host smart-10139501-33a5-457f-8d14-16aa7087e729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496795908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.496795908
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.973571091
Short name T465
Test name
Test status
Simulation time 209466236 ps
CPU time 16.48 seconds
Started Jul 12 04:44:00 PM PDT 24
Finished Jul 12 04:44:25 PM PDT 24
Peak memory 250380 kb
Host smart-45ceb8e9-6807-43dd-bc14-1502c243f996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973571091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.973571091
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2005431996
Short name T282
Test name
Test status
Simulation time 57311867 ps
CPU time 3.68 seconds
Started Jul 12 04:43:59 PM PDT 24
Finished Jul 12 04:44:10 PM PDT 24
Peak memory 225892 kb
Host smart-98435f9e-4ef4-48e7-b191-623055395c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005431996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2005431996
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2572729547
Short name T704
Test name
Test status
Simulation time 11600130135 ps
CPU time 324.6 seconds
Started Jul 12 04:44:00 PM PDT 24
Finished Jul 12 04:49:32 PM PDT 24
Peak memory 283212 kb
Host smart-9abef7a8-470a-46e6-b621-0f88877494a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572729547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2572729547
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3298022146
Short name T756
Test name
Test status
Simulation time 12904217 ps
CPU time 0.85 seconds
Started Jul 12 04:43:59 PM PDT 24
Finished Jul 12 04:44:07 PM PDT 24
Peak memory 208476 kb
Host smart-03e93ae0-f600-4128-b0e2-2b0f3aa66452
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298022146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3298022146
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.916824626
Short name T89
Test name
Test status
Simulation time 26890161 ps
CPU time 0.95 seconds
Started Jul 12 04:44:14 PM PDT 24
Finished Jul 12 04:44:22 PM PDT 24
Peak memory 208400 kb
Host smart-50006be1-0354-4ce7-a233-916a2b640f09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916824626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.916824626
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3235618869
Short name T473
Test name
Test status
Simulation time 367239153 ps
CPU time 15.6 seconds
Started Jul 12 04:44:06 PM PDT 24
Finished Jul 12 04:44:29 PM PDT 24
Peak memory 225432 kb
Host smart-b0bdff04-5f6c-4843-98d7-f7032f804746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235618869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3235618869
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3394676849
Short name T575
Test name
Test status
Simulation time 157029721 ps
CPU time 1.25 seconds
Started Jul 12 04:44:09 PM PDT 24
Finished Jul 12 04:44:17 PM PDT 24
Peak memory 216556 kb
Host smart-b17f682b-de28-449a-bf90-a0343da447dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394676849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3394676849
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.244745366
Short name T228
Test name
Test status
Simulation time 67282324 ps
CPU time 3.35 seconds
Started Jul 12 04:44:03 PM PDT 24
Finished Jul 12 04:44:14 PM PDT 24
Peak memory 217716 kb
Host smart-be5b5f43-e9ea-4820-8729-45f8b0e4ba95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244745366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.244745366
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2664164512
Short name T462
Test name
Test status
Simulation time 262412762 ps
CPU time 13.02 seconds
Started Jul 12 04:44:08 PM PDT 24
Finished Jul 12 04:44:28 PM PDT 24
Peak memory 225516 kb
Host smart-a9db836e-01f1-4f99-9af6-a74ce032152b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664164512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2664164512
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.3536738529
Short name T324
Test name
Test status
Simulation time 371491627 ps
CPU time 11.44 seconds
Started Jul 12 04:44:02 PM PDT 24
Finished Jul 12 04:44:21 PM PDT 24
Peak memory 225404 kb
Host smart-4caa9239-d7d5-4285-913a-28619faf35a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536738529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.3536738529
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3346270002
Short name T505
Test name
Test status
Simulation time 285121953 ps
CPU time 10.19 seconds
Started Jul 12 04:44:07 PM PDT 24
Finished Jul 12 04:44:24 PM PDT 24
Peak memory 217588 kb
Host smart-8a765882-4981-4ab7-a0bc-756d0d72d6af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346270002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3346270002
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.749099337
Short name T659
Test name
Test status
Simulation time 1633311670 ps
CPU time 9.3 seconds
Started Jul 12 04:44:06 PM PDT 24
Finished Jul 12 04:44:22 PM PDT 24
Peak memory 217696 kb
Host smart-f20f8da0-d862-4761-a5b2-031fc763c941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749099337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.749099337
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3551351405
Short name T338
Test name
Test status
Simulation time 143084882 ps
CPU time 1.87 seconds
Started Jul 12 04:44:01 PM PDT 24
Finished Jul 12 04:44:11 PM PDT 24
Peak memory 213400 kb
Host smart-745030b1-8b0a-47cf-967d-3970d1042a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551351405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3551351405
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1034929925
Short name T528
Test name
Test status
Simulation time 364622284 ps
CPU time 19.67 seconds
Started Jul 12 04:44:05 PM PDT 24
Finished Jul 12 04:44:32 PM PDT 24
Peak memory 250448 kb
Host smart-b691a5f3-c91c-4f30-92cd-f68612492321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034929925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1034929925
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2366706098
Short name T841
Test name
Test status
Simulation time 327878918 ps
CPU time 9.81 seconds
Started Jul 12 04:44:13 PM PDT 24
Finished Jul 12 04:44:30 PM PDT 24
Peak memory 250352 kb
Host smart-8c10f833-96b2-4392-a6e8-60f29e4c9bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366706098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2366706098
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2056878071
Short name T703
Test name
Test status
Simulation time 38055548947 ps
CPU time 73.72 seconds
Started Jul 12 04:44:04 PM PDT 24
Finished Jul 12 04:45:25 PM PDT 24
Peak memory 250448 kb
Host smart-ef55edd8-8ee9-4dcc-b0ff-63919e9f11c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056878071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2056878071
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3372960698
Short name T151
Test name
Test status
Simulation time 108242554553 ps
CPU time 478 seconds
Started Jul 12 04:44:05 PM PDT 24
Finished Jul 12 04:52:10 PM PDT 24
Peak memory 283364 kb
Host smart-7458c969-14e1-4ce8-a34c-4bb3dd475640
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3372960698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3372960698
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.251781445
Short name T555
Test name
Test status
Simulation time 14943708 ps
CPU time 1.27 seconds
Started Jul 12 04:44:01 PM PDT 24
Finished Jul 12 04:44:10 PM PDT 24
Peak memory 211320 kb
Host smart-65c80a4b-cba7-47b4-b2b3-53967aca57cd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251781445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct
rl_volatile_unlock_smoke.251781445
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1319861150
Short name T463
Test name
Test status
Simulation time 36382210 ps
CPU time 0.94 seconds
Started Jul 12 04:44:03 PM PDT 24
Finished Jul 12 04:44:12 PM PDT 24
Peak memory 208696 kb
Host smart-6ed70e98-1214-4330-b281-45ab639bc82e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319861150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1319861150
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.902753595
Short name T271
Test name
Test status
Simulation time 1033006364 ps
CPU time 20.91 seconds
Started Jul 12 04:44:03 PM PDT 24
Finished Jul 12 04:44:32 PM PDT 24
Peak memory 217652 kb
Host smart-201f07ea-215a-4551-bc7f-ecae27de6565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902753595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.902753595
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.402145116
Short name T518
Test name
Test status
Simulation time 2041392168 ps
CPU time 8.35 seconds
Started Jul 12 04:44:05 PM PDT 24
Finished Jul 12 04:44:20 PM PDT 24
Peak memory 216720 kb
Host smart-8937b4e4-03d6-4088-bed4-8b27b8cb5b8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402145116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.402145116
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1675293738
Short name T12
Test name
Test status
Simulation time 56133747 ps
CPU time 1.48 seconds
Started Jul 12 04:44:09 PM PDT 24
Finished Jul 12 04:44:17 PM PDT 24
Peak memory 217684 kb
Host smart-8cc743c0-d2c1-49f8-b618-fdb681a1ece6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675293738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1675293738
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.553840066
Short name T690
Test name
Test status
Simulation time 433984236 ps
CPU time 12.47 seconds
Started Jul 12 04:44:13 PM PDT 24
Finished Jul 12 04:44:33 PM PDT 24
Peak memory 225340 kb
Host smart-ad51696a-436e-41d1-ba74-bb5740fc4228
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553840066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.553840066
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1514310389
Short name T765
Test name
Test status
Simulation time 673450556 ps
CPU time 6.93 seconds
Started Jul 12 04:44:04 PM PDT 24
Finished Jul 12 04:44:18 PM PDT 24
Peak memory 217672 kb
Host smart-5d118199-279d-49f9-8ea0-74707642a652
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514310389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1514310389
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.635390273
Short name T352
Test name
Test status
Simulation time 1052803497 ps
CPU time 8.49 seconds
Started Jul 12 04:44:13 PM PDT 24
Finished Jul 12 04:44:29 PM PDT 24
Peak memory 225356 kb
Host smart-5d5049b0-259d-4887-b0e0-46d82364185f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635390273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.635390273
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1437529070
Short name T740
Test name
Test status
Simulation time 198985541 ps
CPU time 3.6 seconds
Started Jul 12 04:44:04 PM PDT 24
Finished Jul 12 04:44:15 PM PDT 24
Peak memory 213964 kb
Host smart-c286e64d-517b-46e6-ac7a-077f115ae789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437529070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1437529070
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1486092631
Short name T832
Test name
Test status
Simulation time 209085389 ps
CPU time 28.29 seconds
Started Jul 12 04:44:06 PM PDT 24
Finished Jul 12 04:44:42 PM PDT 24
Peak memory 250436 kb
Host smart-9e2d00f8-9629-412c-a8fe-25b6d3067ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486092631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1486092631
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.266242992
Short name T217
Test name
Test status
Simulation time 78493203 ps
CPU time 2.79 seconds
Started Jul 12 04:44:05 PM PDT 24
Finished Jul 12 04:44:15 PM PDT 24
Peak memory 221896 kb
Host smart-c2cfd8d4-05ce-4dd0-84e9-a968de1c3e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266242992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.266242992
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1937729239
Short name T193
Test name
Test status
Simulation time 13159877670 ps
CPU time 256.29 seconds
Started Jul 12 04:44:13 PM PDT 24
Finished Jul 12 04:48:37 PM PDT 24
Peak memory 266588 kb
Host smart-6512a46c-f3fe-4f7b-bcc9-133b11622e2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937729239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1937729239
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.1848659617
Short name T142
Test name
Test status
Simulation time 10014077650 ps
CPU time 343.77 seconds
Started Jul 12 04:44:11 PM PDT 24
Finished Jul 12 04:50:02 PM PDT 24
Peak memory 283384 kb
Host smart-aa97ac32-596f-4a8b-9845-3a67ee44c284
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1848659617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.1848659617
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1101528219
Short name T601
Test name
Test status
Simulation time 27569077 ps
CPU time 0.95 seconds
Started Jul 12 04:44:04 PM PDT 24
Finished Jul 12 04:44:13 PM PDT 24
Peak memory 208540 kb
Host smart-a8e424e1-8b0d-49eb-9e27-e9dd24b6d000
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101528219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1101528219
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2385176234
Short name T761
Test name
Test status
Simulation time 18413768 ps
CPU time 1.15 seconds
Started Jul 12 04:44:05 PM PDT 24
Finished Jul 12 04:44:14 PM PDT 24
Peak memory 208552 kb
Host smart-7b60c3a2-e02f-49fa-aa12-3159d1c64983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385176234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2385176234
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.510471611
Short name T261
Test name
Test status
Simulation time 1738254855 ps
CPU time 11.06 seconds
Started Jul 12 04:44:07 PM PDT 24
Finished Jul 12 04:44:26 PM PDT 24
Peak memory 217640 kb
Host smart-8f1cd6ec-42df-420d-84d5-704bab3bda19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510471611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.510471611
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3899434859
Short name T367
Test name
Test status
Simulation time 2108404432 ps
CPU time 10.17 seconds
Started Jul 12 04:44:07 PM PDT 24
Finished Jul 12 04:44:25 PM PDT 24
Peak memory 217104 kb
Host smart-b4c3009c-4035-4e03-8253-df84a9092ca9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899434859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3899434859
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3459460355
Short name T867
Test name
Test status
Simulation time 175542091 ps
CPU time 2.01 seconds
Started Jul 12 04:44:04 PM PDT 24
Finished Jul 12 04:44:14 PM PDT 24
Peak memory 221496 kb
Host smart-494d3cfb-5b6d-403c-ba8c-2356dde1317c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459460355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3459460355
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.1508548369
Short name T572
Test name
Test status
Simulation time 2264159689 ps
CPU time 9.54 seconds
Started Jul 12 04:44:05 PM PDT 24
Finished Jul 12 04:44:21 PM PDT 24
Peak memory 225584 kb
Host smart-ac4244fa-10a4-455e-86f1-646c5aec97f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508548369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1508548369
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3237584120
Short name T580
Test name
Test status
Simulation time 1282862790 ps
CPU time 10.67 seconds
Started Jul 12 04:44:11 PM PDT 24
Finished Jul 12 04:44:28 PM PDT 24
Peak memory 225408 kb
Host smart-0fcfcd56-6c06-4e6f-aba8-66b648adb1e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237584120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3237584120
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2133348879
Short name T716
Test name
Test status
Simulation time 1308626672 ps
CPU time 11.98 seconds
Started Jul 12 04:44:06 PM PDT 24
Finished Jul 12 04:44:25 PM PDT 24
Peak memory 217564 kb
Host smart-910bfe7d-83ac-4b03-9a46-853ef4644337
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133348879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2133348879
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.554514094
Short name T554
Test name
Test status
Simulation time 1793337687 ps
CPU time 10.86 seconds
Started Jul 12 04:44:07 PM PDT 24
Finished Jul 12 04:44:25 PM PDT 24
Peak memory 217708 kb
Host smart-8417cff0-5936-4c6d-9a82-fc05bb59d97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554514094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.554514094
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1158479240
Short name T345
Test name
Test status
Simulation time 105118226 ps
CPU time 2.13 seconds
Started Jul 12 04:44:07 PM PDT 24
Finished Jul 12 04:44:17 PM PDT 24
Peak memory 213800 kb
Host smart-5def3992-e650-4921-be68-b37d718b2220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158479240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1158479240
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1245504492
Short name T647
Test name
Test status
Simulation time 448334807 ps
CPU time 17.59 seconds
Started Jul 12 04:44:04 PM PDT 24
Finished Jul 12 04:44:29 PM PDT 24
Peak memory 250460 kb
Host smart-767731d9-663a-493d-9575-85e5b7580adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245504492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1245504492
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3416071012
Short name T705
Test name
Test status
Simulation time 56883409 ps
CPU time 10.39 seconds
Started Jul 12 04:44:07 PM PDT 24
Finished Jul 12 04:44:25 PM PDT 24
Peak memory 250392 kb
Host smart-9a85a76e-2789-4c8a-bece-4ba6f5635bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416071012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3416071012
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.3429857703
Short name T670
Test name
Test status
Simulation time 2968465366 ps
CPU time 101.53 seconds
Started Jul 12 04:44:07 PM PDT 24
Finished Jul 12 04:45:56 PM PDT 24
Peak memory 250520 kb
Host smart-84b63080-18be-4d7f-b15c-dea5c031c0fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429857703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.3429857703
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.3510052298
Short name T42
Test name
Test status
Simulation time 42786797447 ps
CPU time 494.23 seconds
Started Jul 12 04:44:10 PM PDT 24
Finished Jul 12 04:52:31 PM PDT 24
Peak memory 496228 kb
Host smart-9b6f481d-193d-4118-90f7-89d135f738dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3510052298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.3510052298
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2921223036
Short name T538
Test name
Test status
Simulation time 42040655 ps
CPU time 0.75 seconds
Started Jul 12 04:44:11 PM PDT 24
Finished Jul 12 04:44:18 PM PDT 24
Peak memory 208212 kb
Host smart-1ea3c6cd-34f0-482a-9507-224c8a51e4f3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921223036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2921223036
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3414898762
Short name T432
Test name
Test status
Simulation time 50335778 ps
CPU time 0.83 seconds
Started Jul 12 04:44:19 PM PDT 24
Finished Jul 12 04:44:26 PM PDT 24
Peak memory 208228 kb
Host smart-d9703bd0-c185-4e99-9e4c-e44eceb3618d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414898762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3414898762
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2562079255
Short name T509
Test name
Test status
Simulation time 776368210 ps
CPU time 7.78 seconds
Started Jul 12 04:44:19 PM PDT 24
Finished Jul 12 04:44:33 PM PDT 24
Peak memory 217540 kb
Host smart-cb0cab8d-0e6c-4a05-a491-911f07014e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562079255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2562079255
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.4047289645
Short name T625
Test name
Test status
Simulation time 2292992309 ps
CPU time 7.34 seconds
Started Jul 12 04:44:10 PM PDT 24
Finished Jul 12 04:44:24 PM PDT 24
Peak memory 216884 kb
Host smart-c216bcfe-f61e-4b83-8615-cad814c581d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047289645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.4047289645
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3907061805
Short name T592
Test name
Test status
Simulation time 54311118 ps
CPU time 3.08 seconds
Started Jul 12 04:44:13 PM PDT 24
Finished Jul 12 04:44:23 PM PDT 24
Peak memory 217620 kb
Host smart-bd552de4-94bb-43bd-92c2-d7547f45ff06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907061805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3907061805
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.382474579
Short name T678
Test name
Test status
Simulation time 1085737846 ps
CPU time 10.57 seconds
Started Jul 12 04:44:10 PM PDT 24
Finished Jul 12 04:44:27 PM PDT 24
Peak memory 218360 kb
Host smart-781679f5-4115-47b7-bedd-84355b687eb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382474579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.382474579
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1122950549
Short name T385
Test name
Test status
Simulation time 217258690 ps
CPU time 7.39 seconds
Started Jul 12 04:44:08 PM PDT 24
Finished Jul 12 04:44:23 PM PDT 24
Peak memory 225332 kb
Host smart-dfcbbc6d-c9f2-4153-b4bd-8aaed03f8f36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122950549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1122950549
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2100233021
Short name T447
Test name
Test status
Simulation time 898280886 ps
CPU time 8.95 seconds
Started Jul 12 04:44:09 PM PDT 24
Finished Jul 12 04:44:24 PM PDT 24
Peak memory 217656 kb
Host smart-78a387c7-a086-4748-a638-a856d4d50684
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100233021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2100233021
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2954731311
Short name T397
Test name
Test status
Simulation time 436615603 ps
CPU time 9.97 seconds
Started Jul 12 04:44:11 PM PDT 24
Finished Jul 12 04:44:27 PM PDT 24
Peak memory 225424 kb
Host smart-089b6600-cf4a-470e-9efa-1771447f70c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954731311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2954731311
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2231000563
Short name T328
Test name
Test status
Simulation time 137147357 ps
CPU time 0.99 seconds
Started Jul 12 04:44:08 PM PDT 24
Finished Jul 12 04:44:16 PM PDT 24
Peak memory 211704 kb
Host smart-a077f9fe-afd9-4044-955d-fe12842cd867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231000563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2231000563
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.835968700
Short name T413
Test name
Test status
Simulation time 368407836 ps
CPU time 16.56 seconds
Started Jul 12 04:44:09 PM PDT 24
Finished Jul 12 04:44:32 PM PDT 24
Peak memory 250404 kb
Host smart-4fc41440-dd12-4ba2-a70a-df544835888a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835968700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.835968700
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.2659217342
Short name T226
Test name
Test status
Simulation time 327862951 ps
CPU time 3.89 seconds
Started Jul 12 04:44:09 PM PDT 24
Finished Jul 12 04:44:19 PM PDT 24
Peak memory 222172 kb
Host smart-589a9800-8c33-426a-bb8b-b3e2a6c06ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659217342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2659217342
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3485990227
Short name T107
Test name
Test status
Simulation time 13357328590 ps
CPU time 125.3 seconds
Started Jul 12 04:44:13 PM PDT 24
Finished Jul 12 04:46:25 PM PDT 24
Peak memory 272952 kb
Host smart-1cd4d59f-43b4-4bd3-b61a-5809d270cbcd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485990227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3485990227
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1918117869
Short name T40
Test name
Test status
Simulation time 20075010 ps
CPU time 1.14 seconds
Started Jul 12 04:44:06 PM PDT 24
Finished Jul 12 04:44:15 PM PDT 24
Peak memory 217236 kb
Host smart-6bcf7fdb-6113-4f1e-9dc9-09cd3d657117
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918117869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1918117869
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.372518779
Short name T649
Test name
Test status
Simulation time 19025701 ps
CPU time 1.17 seconds
Started Jul 12 04:44:10 PM PDT 24
Finished Jul 12 04:44:18 PM PDT 24
Peak memory 208360 kb
Host smart-7e9b03fa-9c5a-4f45-8601-328d68734950
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372518779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.372518779
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.4268055223
Short name T218
Test name
Test status
Simulation time 830327118 ps
CPU time 14.16 seconds
Started Jul 12 04:44:11 PM PDT 24
Finished Jul 12 04:44:32 PM PDT 24
Peak memory 225488 kb
Host smart-708c1f80-ed9a-427f-9498-a548091b8c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268055223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.4268055223
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2443552860
Short name T777
Test name
Test status
Simulation time 561646376 ps
CPU time 14.31 seconds
Started Jul 12 04:44:09 PM PDT 24
Finished Jul 12 04:44:30 PM PDT 24
Peak memory 217020 kb
Host smart-1842c7bc-27c3-46e8-b0f3-f8f0b265a41c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443552860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2443552860
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.296897811
Short name T357
Test name
Test status
Simulation time 250415593 ps
CPU time 3.51 seconds
Started Jul 12 04:44:13 PM PDT 24
Finished Jul 12 04:44:24 PM PDT 24
Peak memory 222116 kb
Host smart-900dfc88-8baf-49bd-8103-cd34826e44f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296897811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.296897811
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.661972528
Short name T304
Test name
Test status
Simulation time 414019858 ps
CPU time 14.94 seconds
Started Jul 12 04:44:12 PM PDT 24
Finished Jul 12 04:44:34 PM PDT 24
Peak memory 225404 kb
Host smart-9a7c9243-5ffe-41ac-8e69-4d97b9f06c00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661972528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.661972528
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2637768271
Short name T787
Test name
Test status
Simulation time 713145078 ps
CPU time 12.79 seconds
Started Jul 12 04:44:13 PM PDT 24
Finished Jul 12 04:44:33 PM PDT 24
Peak memory 225396 kb
Host smart-8dafb071-2350-4699-b814-5344a9ee19b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637768271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2637768271
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3316615625
Short name T342
Test name
Test status
Simulation time 1221289631 ps
CPU time 10.73 seconds
Started Jul 12 04:44:11 PM PDT 24
Finished Jul 12 04:44:28 PM PDT 24
Peak memory 217656 kb
Host smart-51e872f8-b51f-4f45-9f3e-97949cc6c985
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316615625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3316615625
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2054253836
Short name T816
Test name
Test status
Simulation time 2045606314 ps
CPU time 10.86 seconds
Started Jul 12 04:44:19 PM PDT 24
Finished Jul 12 04:44:36 PM PDT 24
Peak memory 217668 kb
Host smart-59584bb2-9be1-46bd-a9f8-3c7249e550ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054253836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2054253836
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1573674700
Short name T667
Test name
Test status
Simulation time 185641134 ps
CPU time 3.39 seconds
Started Jul 12 04:44:10 PM PDT 24
Finished Jul 12 04:44:20 PM PDT 24
Peak memory 214320 kb
Host smart-dbdeab11-42a9-4797-94f9-70619695fba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573674700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1573674700
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3301336906
Short name T471
Test name
Test status
Simulation time 1912668098 ps
CPU time 22.42 seconds
Started Jul 12 04:44:15 PM PDT 24
Finished Jul 12 04:44:44 PM PDT 24
Peak memory 250460 kb
Host smart-d06ac900-4887-49ff-a458-131e0b3061ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301336906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3301336906
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1674441215
Short name T389
Test name
Test status
Simulation time 48257803 ps
CPU time 6.82 seconds
Started Jul 12 04:44:12 PM PDT 24
Finished Jul 12 04:44:26 PM PDT 24
Peak memory 250008 kb
Host smart-c5a4bf3e-b11d-4b17-843f-4468d39b24c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674441215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1674441215
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.94182099
Short name T472
Test name
Test status
Simulation time 8451402808 ps
CPU time 93.59 seconds
Started Jul 12 04:44:12 PM PDT 24
Finished Jul 12 04:45:52 PM PDT 24
Peak memory 280180 kb
Host smart-120f5726-bd13-449b-a8aa-3475f3c2837c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94182099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.lc_ctrl_stress_all.94182099
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.4088934444
Short name T784
Test name
Test status
Simulation time 19171337 ps
CPU time 1.18 seconds
Started Jul 12 04:44:12 PM PDT 24
Finished Jul 12 04:44:19 PM PDT 24
Peak memory 217204 kb
Host smart-e795442e-165a-4ae3-8490-b6c5d5662935
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088934444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.4088934444
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3830019286
Short name T250
Test name
Test status
Simulation time 48110087 ps
CPU time 0.99 seconds
Started Jul 12 04:44:12 PM PDT 24
Finished Jul 12 04:44:19 PM PDT 24
Peak memory 208408 kb
Host smart-cf72ef61-8ac2-478c-bdf8-a8a5b2580b54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830019286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3830019286
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3812389050
Short name T285
Test name
Test status
Simulation time 968549148 ps
CPU time 11.28 seconds
Started Jul 12 04:44:19 PM PDT 24
Finished Jul 12 04:44:38 PM PDT 24
Peak memory 217712 kb
Host smart-aae8951b-d0ff-450b-9c2d-b28528f1b920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812389050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3812389050
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2084987647
Short name T22
Test name
Test status
Simulation time 4441004469 ps
CPU time 14.24 seconds
Started Jul 12 04:44:15 PM PDT 24
Finished Jul 12 04:44:36 PM PDT 24
Peak memory 217292 kb
Host smart-c858e174-7ff7-4dac-a3e2-deaeb30eeb9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084987647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2084987647
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3373943307
Short name T739
Test name
Test status
Simulation time 73999813 ps
CPU time 2.91 seconds
Started Jul 12 04:44:09 PM PDT 24
Finished Jul 12 04:44:18 PM PDT 24
Peak memory 221776 kb
Host smart-140dfdfc-80d0-423b-86f6-fce65027c935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373943307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3373943307
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1788377275
Short name T741
Test name
Test status
Simulation time 402315592 ps
CPU time 16.89 seconds
Started Jul 12 04:51:41 PM PDT 24
Finished Jul 12 04:51:59 PM PDT 24
Peak memory 225480 kb
Host smart-5959f983-5933-43e0-acff-192122ed0b46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788377275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1788377275
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2617288163
Short name T751
Test name
Test status
Simulation time 2742450855 ps
CPU time 18.64 seconds
Started Jul 12 04:44:14 PM PDT 24
Finished Jul 12 04:44:40 PM PDT 24
Peak memory 225464 kb
Host smart-e852a359-ab52-44c2-a79e-e33c7ad60049
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617288163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2617288163
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1329719251
Short name T269
Test name
Test status
Simulation time 258970764 ps
CPU time 7.29 seconds
Started Jul 12 04:44:11 PM PDT 24
Finished Jul 12 04:44:24 PM PDT 24
Peak memory 225448 kb
Host smart-54c4d842-adf1-477a-be12-af90fddf5e8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329719251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1329719251
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.614777513
Short name T523
Test name
Test status
Simulation time 351644128 ps
CPU time 8.06 seconds
Started Jul 12 04:44:20 PM PDT 24
Finished Jul 12 04:44:34 PM PDT 24
Peak memory 224688 kb
Host smart-c06149a0-9d53-4f4e-be5a-11d8ab1d6596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614777513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.614777513
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.967566138
Short name T448
Test name
Test status
Simulation time 61261651 ps
CPU time 2.13 seconds
Started Jul 12 04:44:19 PM PDT 24
Finished Jul 12 04:44:28 PM PDT 24
Peak memory 213444 kb
Host smart-ed7e7d90-7751-427e-b2c5-9345968505b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967566138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.967566138
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.976794671
Short name T516
Test name
Test status
Simulation time 758429567 ps
CPU time 36.16 seconds
Started Jul 12 04:44:11 PM PDT 24
Finished Jul 12 04:44:54 PM PDT 24
Peak memory 250380 kb
Host smart-d77e403b-1660-43a1-a18d-c3a104ecf90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976794671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.976794671
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2520193803
Short name T623
Test name
Test status
Simulation time 61527822 ps
CPU time 7.57 seconds
Started Jul 12 04:44:12 PM PDT 24
Finished Jul 12 04:44:27 PM PDT 24
Peak memory 250436 kb
Host smart-9faf5f77-8027-4df1-bae0-e7dfb09aa637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520193803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2520193803
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3523559654
Short name T171
Test name
Test status
Simulation time 39777846870 ps
CPU time 152.85 seconds
Started Jul 12 04:44:12 PM PDT 24
Finished Jul 12 04:46:52 PM PDT 24
Peak memory 226880 kb
Host smart-e7db3326-c5b5-4a97-a36f-1ebe4f90487c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523559654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3523559654
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.1322338454
Short name T153
Test name
Test status
Simulation time 217551786378 ps
CPU time 944.66 seconds
Started Jul 12 04:44:13 PM PDT 24
Finished Jul 12 05:00:05 PM PDT 24
Peak memory 496296 kb
Host smart-5ea49828-ed70-44fb-9492-b4d5dc5dc44a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1322338454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.1322338454
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1186957157
Short name T535
Test name
Test status
Simulation time 13963633 ps
CPU time 0.89 seconds
Started Jul 12 04:44:09 PM PDT 24
Finished Jul 12 04:44:16 PM PDT 24
Peak memory 211308 kb
Host smart-4a7a9d43-831f-40ed-b5dd-160996c2cfc8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186957157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1186957157
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1938450816
Short name T65
Test name
Test status
Simulation time 45217370 ps
CPU time 0.86 seconds
Started Jul 12 04:43:03 PM PDT 24
Finished Jul 12 04:43:08 PM PDT 24
Peak memory 208388 kb
Host smart-e67159f9-9934-4cb5-965d-b2d4b3524228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938450816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1938450816
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3448480220
Short name T237
Test name
Test status
Simulation time 12826001 ps
CPU time 0.89 seconds
Started Jul 12 04:42:48 PM PDT 24
Finished Jul 12 04:42:51 PM PDT 24
Peak memory 208468 kb
Host smart-a1f0850f-808c-432e-bf94-d7cc236461fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448480220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3448480220
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3292798945
Short name T88
Test name
Test status
Simulation time 316516329 ps
CPU time 12.94 seconds
Started Jul 12 04:42:49 PM PDT 24
Finished Jul 12 04:43:05 PM PDT 24
Peak memory 225520 kb
Host smart-136fd695-6814-417d-bd46-ab2ae9fa203a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292798945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3292798945
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1367900127
Short name T865
Test name
Test status
Simulation time 17932364130 ps
CPU time 20.81 seconds
Started Jul 12 04:43:03 PM PDT 24
Finished Jul 12 04:43:28 PM PDT 24
Peak memory 217120 kb
Host smart-f6127d92-8c9e-4ca5-a950-4eeb6fa92903
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367900127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1367900127
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.834904288
Short name T636
Test name
Test status
Simulation time 1633797873 ps
CPU time 29.99 seconds
Started Jul 12 04:42:56 PM PDT 24
Finished Jul 12 04:43:27 PM PDT 24
Peak memory 217624 kb
Host smart-00beb167-f6fc-42fd-959d-e3595c7703f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834904288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.834904288
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2005965957
Short name T258
Test name
Test status
Simulation time 218034114 ps
CPU time 3.83 seconds
Started Jul 12 04:42:56 PM PDT 24
Finished Jul 12 04:43:01 PM PDT 24
Peak memory 217160 kb
Host smart-32d6016b-8cbf-4f47-891c-20e62e727ce6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005965957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
005965957
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.375715325
Short name T627
Test name
Test status
Simulation time 1077864013 ps
CPU time 8.66 seconds
Started Jul 12 04:42:54 PM PDT 24
Finished Jul 12 04:43:04 PM PDT 24
Peak memory 222612 kb
Host smart-3ffb2cc5-263d-4d72-a023-a960e5ad3e4b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375715325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
prog_failure.375715325
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1925794050
Short name T69
Test name
Test status
Simulation time 1887738885 ps
CPU time 14.78 seconds
Started Jul 12 04:42:53 PM PDT 24
Finished Jul 12 04:43:09 PM PDT 24
Peak memory 216984 kb
Host smart-865948dd-7f55-4b98-8ba4-0fb951373d97
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925794050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1925794050
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.4280676530
Short name T552
Test name
Test status
Simulation time 1845765392 ps
CPU time 5.87 seconds
Started Jul 12 04:42:49 PM PDT 24
Finished Jul 12 04:42:58 PM PDT 24
Peak memory 216948 kb
Host smart-b97e2573-c461-444e-8edf-b60336f0b16e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280676530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
4280676530
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3265041671
Short name T857
Test name
Test status
Simulation time 7336712422 ps
CPU time 72.16 seconds
Started Jul 12 04:42:53 PM PDT 24
Finished Jul 12 04:44:07 PM PDT 24
Peak memory 275052 kb
Host smart-0c8bab55-151d-413e-91a4-36339061e3ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265041671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3265041671
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.95140644
Short name T674
Test name
Test status
Simulation time 866477768 ps
CPU time 26.9 seconds
Started Jul 12 04:42:54 PM PDT 24
Finished Jul 12 04:43:22 PM PDT 24
Peak memory 249808 kb
Host smart-914cd76a-c240-4e45-b494-8e410bf948cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95140644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jt
ag_state_post_trans.95140644
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2420131101
Short name T859
Test name
Test status
Simulation time 76574033 ps
CPU time 1.91 seconds
Started Jul 12 04:42:48 PM PDT 24
Finished Jul 12 04:42:52 PM PDT 24
Peak memory 217628 kb
Host smart-ed08638b-708b-426e-8dfa-3b7c76220335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420131101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2420131101
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.429572923
Short name T73
Test name
Test status
Simulation time 398098967 ps
CPU time 20.83 seconds
Started Jul 12 04:42:48 PM PDT 24
Finished Jul 12 04:43:12 PM PDT 24
Peak memory 217124 kb
Host smart-f6571620-38ee-40ce-8747-cd9c91c2625a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429572923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.429572923
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1644629014
Short name T77
Test name
Test status
Simulation time 827517997 ps
CPU time 40.31 seconds
Started Jul 12 04:42:53 PM PDT 24
Finished Jul 12 04:43:35 PM PDT 24
Peak memory 269784 kb
Host smart-8bb0b660-fc1f-4fb0-8268-218b8bffa4ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644629014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1644629014
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1492235486
Short name T561
Test name
Test status
Simulation time 3772996042 ps
CPU time 19.52 seconds
Started Jul 12 04:42:57 PM PDT 24
Finished Jul 12 04:43:18 PM PDT 24
Peak memory 225504 kb
Host smart-c6c0066d-73f9-477e-b832-ab648b27df15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492235486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1492235486
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.913886200
Short name T323
Test name
Test status
Simulation time 1608230076 ps
CPU time 11.15 seconds
Started Jul 12 04:42:55 PM PDT 24
Finished Jul 12 04:43:07 PM PDT 24
Peak memory 225376 kb
Host smart-b91c8e86-fe47-4135-9a50-d4a7c081ecdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913886200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig
est.913886200
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.456045035
Short name T358
Test name
Test status
Simulation time 355098321 ps
CPU time 9.3 seconds
Started Jul 12 04:42:56 PM PDT 24
Finished Jul 12 04:43:06 PM PDT 24
Peak memory 217660 kb
Host smart-a61019be-7483-4638-816e-a380b3e998e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456045035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.456045035
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2164142649
Short name T49
Test name
Test status
Simulation time 238045743 ps
CPU time 6.5 seconds
Started Jul 12 04:42:48 PM PDT 24
Finished Jul 12 04:42:58 PM PDT 24
Peak memory 224496 kb
Host smart-7923f1bb-a674-4095-9e1f-57eb8d3c9bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164142649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2164142649
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1627266565
Short name T63
Test name
Test status
Simulation time 15124571 ps
CPU time 0.89 seconds
Started Jul 12 04:42:49 PM PDT 24
Finished Jul 12 04:42:53 PM PDT 24
Peak memory 208352 kb
Host smart-6eeba51e-c9c6-48cf-a3d4-0c80a5cc39ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627266565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1627266565
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2238338184
Short name T468
Test name
Test status
Simulation time 288331582 ps
CPU time 23.98 seconds
Started Jul 12 04:42:49 PM PDT 24
Finished Jul 12 04:43:16 PM PDT 24
Peak memory 250360 kb
Host smart-b748ef83-6f06-4615-9f5c-c812fcdd2651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238338184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2238338184
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2232904145
Short name T614
Test name
Test status
Simulation time 697083195 ps
CPU time 9.51 seconds
Started Jul 12 04:42:49 PM PDT 24
Finished Jul 12 04:43:02 PM PDT 24
Peak memory 250372 kb
Host smart-2b57def7-a829-41f7-9231-349d2910a9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232904145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2232904145
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.846220863
Short name T415
Test name
Test status
Simulation time 4496601858 ps
CPU time 107.51 seconds
Started Jul 12 04:43:03 PM PDT 24
Finished Jul 12 04:44:54 PM PDT 24
Peak memory 275664 kb
Host smart-e082d535-6d68-449b-9e05-7ce85683234a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846220863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.846220863
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3747566319
Short name T17
Test name
Test status
Simulation time 5674211220 ps
CPU time 202.29 seconds
Started Jul 12 04:42:55 PM PDT 24
Finished Jul 12 04:46:19 PM PDT 24
Peak memory 271000 kb
Host smart-f564f7ff-20ee-403b-82af-b98a27f7b235
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3747566319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.3747566319
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.456052617
Short name T742
Test name
Test status
Simulation time 13929558 ps
CPU time 1.01 seconds
Started Jul 12 04:42:47 PM PDT 24
Finished Jul 12 04:42:50 PM PDT 24
Peak memory 208636 kb
Host smart-f30ee0b0-6c79-4d5c-aafd-098b0d6383e7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456052617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr
l_volatile_unlock_smoke.456052617
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2594756206
Short name T525
Test name
Test status
Simulation time 24850447 ps
CPU time 1.04 seconds
Started Jul 12 04:44:19 PM PDT 24
Finished Jul 12 04:44:26 PM PDT 24
Peak memory 208384 kb
Host smart-cae376d0-3f2d-486e-bebf-3265dc571a7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594756206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2594756206
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.76255341
Short name T830
Test name
Test status
Simulation time 374330464 ps
CPU time 14.99 seconds
Started Jul 12 04:44:13 PM PDT 24
Finished Jul 12 04:44:35 PM PDT 24
Peak memory 217716 kb
Host smart-009d7e2c-8e8d-4fb4-8aa2-92c8520eff31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76255341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.76255341
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1167283695
Short name T529
Test name
Test status
Simulation time 980334515 ps
CPU time 12.71 seconds
Started Jul 12 04:44:11 PM PDT 24
Finished Jul 12 04:44:30 PM PDT 24
Peak memory 217164 kb
Host smart-06a7dbc8-80ab-4cff-8d18-4262241db669
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167283695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1167283695
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3081730331
Short name T408
Test name
Test status
Simulation time 112900063 ps
CPU time 1.68 seconds
Started Jul 12 04:44:10 PM PDT 24
Finished Jul 12 04:44:18 PM PDT 24
Peak memory 217760 kb
Host smart-3799e866-7722-455d-8be5-1c8d45131a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081730331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3081730331
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.2827220115
Short name T801
Test name
Test status
Simulation time 1495761200 ps
CPU time 12.17 seconds
Started Jul 12 04:44:18 PM PDT 24
Finished Jul 12 04:44:37 PM PDT 24
Peak memory 217616 kb
Host smart-267c756d-68df-4931-a1c4-344cd1b8f8ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827220115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.2827220115
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2933771317
Short name T810
Test name
Test status
Simulation time 4699621822 ps
CPU time 9.67 seconds
Started Jul 12 04:44:18 PM PDT 24
Finished Jul 12 04:44:34 PM PDT 24
Peak memory 225516 kb
Host smart-f5d5ecf2-5a8d-4de6-ac7b-100801599bad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933771317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2933771317
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1942262514
Short name T230
Test name
Test status
Simulation time 2275836965 ps
CPU time 10.97 seconds
Started Jul 12 04:44:16 PM PDT 24
Finished Jul 12 04:44:34 PM PDT 24
Peak memory 217736 kb
Host smart-69ee8f7a-6078-47ba-b010-b7d242712bc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942262514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1942262514
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3098080739
Short name T405
Test name
Test status
Simulation time 1105544766 ps
CPU time 8.29 seconds
Started Jul 12 04:44:11 PM PDT 24
Finished Jul 12 04:44:25 PM PDT 24
Peak memory 225420 kb
Host smart-24ec97f0-7fb3-4e77-a347-bec2e2e072c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098080739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3098080739
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3195805042
Short name T353
Test name
Test status
Simulation time 89395002 ps
CPU time 2.81 seconds
Started Jul 12 04:44:12 PM PDT 24
Finished Jul 12 04:44:22 PM PDT 24
Peak memory 217108 kb
Host smart-049c8ec3-5dcd-4505-8a20-0c1da03e0657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195805042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3195805042
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1050724484
Short name T515
Test name
Test status
Simulation time 1403596840 ps
CPU time 32.23 seconds
Started Jul 12 04:44:13 PM PDT 24
Finished Jul 12 04:44:53 PM PDT 24
Peak memory 250444 kb
Host smart-2f357002-7fc0-465f-9808-394b4cf3ced5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050724484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1050724484
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3332342777
Short name T513
Test name
Test status
Simulation time 120627371 ps
CPU time 9.93 seconds
Started Jul 12 04:44:14 PM PDT 24
Finished Jul 12 04:44:31 PM PDT 24
Peak memory 250420 kb
Host smart-b74d5386-d9a2-4d85-9bee-80e2577d9c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332342777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3332342777
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3716745478
Short name T683
Test name
Test status
Simulation time 14119872689 ps
CPU time 196.15 seconds
Started Jul 12 04:44:17 PM PDT 24
Finished Jul 12 04:47:40 PM PDT 24
Peak memory 220440 kb
Host smart-1908b08c-3a86-400d-b8c4-3161528ce4f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716745478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3716745478
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1425110526
Short name T589
Test name
Test status
Simulation time 34927819 ps
CPU time 0.94 seconds
Started Jul 12 04:44:12 PM PDT 24
Finished Jul 12 04:44:20 PM PDT 24
Peak memory 211236 kb
Host smart-c9a2608b-11bc-4f5f-9457-5ae0e1bb02ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425110526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1425110526
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3148116817
Short name T855
Test name
Test status
Simulation time 103708672 ps
CPU time 1.06 seconds
Started Jul 12 04:44:17 PM PDT 24
Finished Jul 12 04:44:25 PM PDT 24
Peak memory 208556 kb
Host smart-21b1ae76-b787-464d-ba72-aba134ad8ce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148116817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3148116817
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.4133419590
Short name T752
Test name
Test status
Simulation time 202529102 ps
CPU time 10.96 seconds
Started Jul 12 04:44:16 PM PDT 24
Finished Jul 12 04:44:34 PM PDT 24
Peak memory 217760 kb
Host smart-1a1045d1-d89e-441c-962b-e657c421bfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133419590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.4133419590
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3424440250
Short name T417
Test name
Test status
Simulation time 69253179 ps
CPU time 1.41 seconds
Started Jul 12 04:44:16 PM PDT 24
Finished Jul 12 04:44:25 PM PDT 24
Peak memory 216544 kb
Host smart-1d2b680f-550c-4815-a511-cd692fddfbc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424440250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3424440250
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3228791716
Short name T362
Test name
Test status
Simulation time 36533704 ps
CPU time 1.68 seconds
Started Jul 12 04:44:19 PM PDT 24
Finished Jul 12 04:44:28 PM PDT 24
Peak memory 217616 kb
Host smart-d6ebe496-4cbf-4189-8eec-f12233c7f14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228791716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3228791716
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3786912500
Short name T164
Test name
Test status
Simulation time 848926019 ps
CPU time 15.03 seconds
Started Jul 12 04:44:16 PM PDT 24
Finished Jul 12 04:44:38 PM PDT 24
Peak memory 225348 kb
Host smart-170a509c-93a7-4a9e-bad3-f93a96d9df64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786912500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3786912500
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3077256773
Short name T91
Test name
Test status
Simulation time 248068930 ps
CPU time 6.63 seconds
Started Jul 12 04:44:17 PM PDT 24
Finished Jul 12 04:44:30 PM PDT 24
Peak memory 217664 kb
Host smart-0c5d56ca-44c8-49be-80df-ea9e896e704c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077256773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3077256773
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.956879455
Short name T96
Test name
Test status
Simulation time 742797551 ps
CPU time 10.12 seconds
Started Jul 12 04:44:19 PM PDT 24
Finished Jul 12 04:44:35 PM PDT 24
Peak memory 224824 kb
Host smart-9d7e14cb-735f-48d4-bd7f-898314025d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956879455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.956879455
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.452620697
Short name T54
Test name
Test status
Simulation time 75063700 ps
CPU time 2.6 seconds
Started Jul 12 04:44:17 PM PDT 24
Finished Jul 12 04:44:27 PM PDT 24
Peak memory 213996 kb
Host smart-84444cb0-36ce-48f6-812e-c3ccb291409a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452620697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.452620697
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.780233119
Short name T796
Test name
Test status
Simulation time 323507583 ps
CPU time 24.51 seconds
Started Jul 12 04:44:18 PM PDT 24
Finished Jul 12 04:44:49 PM PDT 24
Peak memory 250416 kb
Host smart-38f23db5-474c-42f1-a316-aa91525772da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780233119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.780233119
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2833627447
Short name T770
Test name
Test status
Simulation time 94604125 ps
CPU time 7.56 seconds
Started Jul 12 04:44:17 PM PDT 24
Finished Jul 12 04:44:32 PM PDT 24
Peak memory 250340 kb
Host smart-c90f18b8-3f5f-4144-a04a-3d6c7b87f3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833627447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2833627447
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2357126247
Short name T587
Test name
Test status
Simulation time 16316597314 ps
CPU time 273.11 seconds
Started Jul 12 04:44:19 PM PDT 24
Finished Jul 12 04:48:59 PM PDT 24
Peak memory 222060 kb
Host smart-0440f0fa-d454-49ad-9e1f-0c00fae00672
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357126247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2357126247
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3683059309
Short name T503
Test name
Test status
Simulation time 26592802 ps
CPU time 0.77 seconds
Started Jul 12 04:44:17 PM PDT 24
Finished Jul 12 04:44:25 PM PDT 24
Peak memory 208464 kb
Host smart-c7735ba7-a8b0-4a88-9eb0-2a832fbb18a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683059309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3683059309
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.257629022
Short name T804
Test name
Test status
Simulation time 14429169 ps
CPU time 0.86 seconds
Started Jul 12 04:44:18 PM PDT 24
Finished Jul 12 04:44:25 PM PDT 24
Peak memory 208308 kb
Host smart-f14cf879-3452-4dc3-adfc-8e886e4e802d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257629022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.257629022
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.377304476
Short name T249
Test name
Test status
Simulation time 174402479 ps
CPU time 9.28 seconds
Started Jul 12 04:44:16 PM PDT 24
Finished Jul 12 04:44:32 PM PDT 24
Peak memory 225492 kb
Host smart-e55fbeb6-a797-4e13-837f-f4525e75e520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377304476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.377304476
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1851043738
Short name T167
Test name
Test status
Simulation time 447901207 ps
CPU time 3.41 seconds
Started Jul 12 04:44:15 PM PDT 24
Finished Jul 12 04:44:26 PM PDT 24
Peak memory 217048 kb
Host smart-a96aee6a-51d4-4fe6-88d6-072b18276989
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851043738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1851043738
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1188306095
Short name T484
Test name
Test status
Simulation time 40670803 ps
CPU time 1.42 seconds
Started Jul 12 04:44:19 PM PDT 24
Finished Jul 12 04:44:28 PM PDT 24
Peak memory 217620 kb
Host smart-3c43b5b3-f070-41ed-89d1-20251c7b65f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188306095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1188306095
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.648634715
Short name T720
Test name
Test status
Simulation time 1626461750 ps
CPU time 13.02 seconds
Started Jul 12 04:44:18 PM PDT 24
Finished Jul 12 04:44:38 PM PDT 24
Peak memory 224124 kb
Host smart-d52e4a09-8607-461f-9507-2d5bc1c87b7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648634715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.648634715
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.476397637
Short name T613
Test name
Test status
Simulation time 4666724202 ps
CPU time 9.76 seconds
Started Jul 12 04:44:18 PM PDT 24
Finished Jul 12 04:44:35 PM PDT 24
Peak memory 224148 kb
Host smart-0d7ee67c-90e9-4c9b-bc21-01fd2cf2a657
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476397637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.476397637
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1245532770
Short name T438
Test name
Test status
Simulation time 2172985568 ps
CPU time 12.85 seconds
Started Jul 12 04:44:16 PM PDT 24
Finished Jul 12 04:44:36 PM PDT 24
Peak memory 217676 kb
Host smart-294a26ce-f0c2-486a-8ec5-8b8bedf92d9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245532770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1245532770
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.28763562
Short name T699
Test name
Test status
Simulation time 252000612 ps
CPU time 7.17 seconds
Started Jul 12 04:44:18 PM PDT 24
Finished Jul 12 04:44:32 PM PDT 24
Peak memory 224408 kb
Host smart-8f2aa0d6-ee8f-4166-b1ae-26786f80a1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28763562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.28763562
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.345809070
Short name T585
Test name
Test status
Simulation time 115512463 ps
CPU time 2.15 seconds
Started Jul 12 04:44:16 PM PDT 24
Finished Jul 12 04:44:25 PM PDT 24
Peak memory 213880 kb
Host smart-fe5feff7-0f24-47b6-827c-2236d976d5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345809070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.345809070
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.418452391
Short name T604
Test name
Test status
Simulation time 296997087 ps
CPU time 19.95 seconds
Started Jul 12 04:44:18 PM PDT 24
Finished Jul 12 04:44:44 PM PDT 24
Peak memory 250332 kb
Host smart-5ccb1a8a-1b56-433f-9fc7-ee11c45e4ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418452391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.418452391
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1561575206
Short name T715
Test name
Test status
Simulation time 126870284 ps
CPU time 7.39 seconds
Started Jul 12 04:44:14 PM PDT 24
Finished Jul 12 04:44:29 PM PDT 24
Peak memory 250452 kb
Host smart-e8088034-748f-4160-8e5c-c6515e79d77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561575206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1561575206
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1726138684
Short name T522
Test name
Test status
Simulation time 7636794442 ps
CPU time 246.2 seconds
Started Jul 12 04:44:20 PM PDT 24
Finished Jul 12 04:48:32 PM PDT 24
Peak memory 273356 kb
Host smart-396ea5ba-c82a-4ad2-8e5f-9f921a043de1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726138684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1726138684
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.4003831077
Short name T76
Test name
Test status
Simulation time 9252450009 ps
CPU time 335.29 seconds
Started Jul 12 04:44:16 PM PDT 24
Finished Jul 12 04:49:59 PM PDT 24
Peak memory 272828 kb
Host smart-1df7e1fd-c834-4646-8276-19a7d35342aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4003831077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.4003831077
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.444201022
Short name T318
Test name
Test status
Simulation time 12143275 ps
CPU time 0.8 seconds
Started Jul 12 04:44:16 PM PDT 24
Finished Jul 12 04:44:24 PM PDT 24
Peak memory 208240 kb
Host smart-ffb243d7-716f-4029-9e22-38236c7a376a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444201022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.444201022
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.4205018708
Short name T710
Test name
Test status
Simulation time 3416078998 ps
CPU time 11.05 seconds
Started Jul 12 04:44:26 PM PDT 24
Finished Jul 12 04:44:41 PM PDT 24
Peak memory 218396 kb
Host smart-60e7e260-a074-42a8-92ca-935e9cac03cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205018708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.4205018708
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1163062589
Short name T858
Test name
Test status
Simulation time 61184079 ps
CPU time 3.58 seconds
Started Jul 12 04:44:22 PM PDT 24
Finished Jul 12 04:44:31 PM PDT 24
Peak memory 217580 kb
Host smart-164f8121-a99d-4501-803a-4d394526262c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163062589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1163062589
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1806344052
Short name T737
Test name
Test status
Simulation time 294249546 ps
CPU time 8.45 seconds
Started Jul 12 04:44:21 PM PDT 24
Finished Jul 12 04:44:35 PM PDT 24
Peak memory 225440 kb
Host smart-3562e57b-8511-4692-afcc-04ccf4138dab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806344052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1806344052
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1071754814
Short name T846
Test name
Test status
Simulation time 2018316404 ps
CPU time 8.94 seconds
Started Jul 12 04:44:23 PM PDT 24
Finished Jul 12 04:44:38 PM PDT 24
Peak memory 217596 kb
Host smart-cf76a9b2-358d-48be-b618-33570cdbe158
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071754814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1071754814
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.21274168
Short name T402
Test name
Test status
Simulation time 1370546376 ps
CPU time 11.86 seconds
Started Jul 12 04:44:39 PM PDT 24
Finished Jul 12 04:44:54 PM PDT 24
Peak memory 225508 kb
Host smart-63b326ab-108a-4194-831c-8f229d446895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21274168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.21274168
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3902126764
Short name T802
Test name
Test status
Simulation time 111210665 ps
CPU time 4.83 seconds
Started Jul 12 04:44:19 PM PDT 24
Finished Jul 12 04:44:30 PM PDT 24
Peak memory 217124 kb
Host smart-429d7345-1c9d-4f8f-97bb-179fb3fa677c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902126764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3902126764
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2611898916
Short name T2
Test name
Test status
Simulation time 166383245 ps
CPU time 17.81 seconds
Started Jul 12 04:44:22 PM PDT 24
Finished Jul 12 04:44:45 PM PDT 24
Peak memory 250428 kb
Host smart-dd048954-f966-4669-991f-33290a412228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611898916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2611898916
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.681837192
Short name T300
Test name
Test status
Simulation time 77358035 ps
CPU time 6.87 seconds
Started Jul 12 04:44:22 PM PDT 24
Finished Jul 12 04:44:34 PM PDT 24
Peak memory 250480 kb
Host smart-d36411f1-71c3-450c-b733-ede3ae28074f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681837192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.681837192
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1948793309
Short name T459
Test name
Test status
Simulation time 4728062983 ps
CPU time 74.3 seconds
Started Jul 12 04:44:27 PM PDT 24
Finished Jul 12 04:45:45 PM PDT 24
Peak memory 250080 kb
Host smart-ff71d339-7157-4777-97ca-3fb82b2e3da9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948793309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1948793309
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1579722171
Short name T490
Test name
Test status
Simulation time 28325163 ps
CPU time 0.93 seconds
Started Jul 12 04:44:20 PM PDT 24
Finished Jul 12 04:44:27 PM PDT 24
Peak memory 212212 kb
Host smart-9e7f9f72-e514-4b69-9b07-87d5d179e7a6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579722171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1579722171
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1983733260
Short name T648
Test name
Test status
Simulation time 59252357 ps
CPU time 1.1 seconds
Started Jul 12 04:44:39 PM PDT 24
Finished Jul 12 04:44:42 PM PDT 24
Peak memory 208488 kb
Host smart-6257fb24-0822-4889-b31c-1afe24b5d5b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983733260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1983733260
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1464315340
Short name T568
Test name
Test status
Simulation time 4990943577 ps
CPU time 13.98 seconds
Started Jul 12 04:44:38 PM PDT 24
Finished Jul 12 04:44:55 PM PDT 24
Peak memory 218040 kb
Host smart-bf890e08-a96a-49f9-9d33-d3716287c22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464315340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1464315340
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.2961388111
Short name T502
Test name
Test status
Simulation time 187588503 ps
CPU time 2.07 seconds
Started Jul 12 04:44:39 PM PDT 24
Finished Jul 12 04:44:44 PM PDT 24
Peak memory 217128 kb
Host smart-9c8c3f3f-ece1-48b6-9a15-bb6be5b97385
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961388111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.2961388111
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2565596921
Short name T599
Test name
Test status
Simulation time 27252970 ps
CPU time 2.35 seconds
Started Jul 12 04:44:27 PM PDT 24
Finished Jul 12 04:44:33 PM PDT 24
Peak memory 221188 kb
Host smart-377bc875-2890-426f-9042-fcf28d8f8bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565596921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2565596921
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2282003256
Short name T817
Test name
Test status
Simulation time 2928463234 ps
CPU time 24.82 seconds
Started Jul 12 04:44:25 PM PDT 24
Finished Jul 12 04:44:54 PM PDT 24
Peak memory 217652 kb
Host smart-42a3a179-3164-49e9-9306-7246c9207fbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282003256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2282003256
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1034621404
Short name T866
Test name
Test status
Simulation time 578395440 ps
CPU time 8.8 seconds
Started Jul 12 04:44:24 PM PDT 24
Finished Jul 12 04:44:37 PM PDT 24
Peak memory 217620 kb
Host smart-1cbb6d63-e2b9-4e57-a9eb-2ff4fd3e815b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034621404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
1034621404
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.2026545993
Short name T632
Test name
Test status
Simulation time 1332584543 ps
CPU time 9.56 seconds
Started Jul 12 04:44:22 PM PDT 24
Finished Jul 12 04:44:37 PM PDT 24
Peak memory 225600 kb
Host smart-c46d55cf-eb6c-47e8-9e8c-766a7e4981d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026545993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.2026545993
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2877333049
Short name T638
Test name
Test status
Simulation time 81756820 ps
CPU time 1.11 seconds
Started Jul 12 04:44:38 PM PDT 24
Finished Jul 12 04:44:41 PM PDT 24
Peak memory 213048 kb
Host smart-aa6f2c0e-fe51-45ec-9292-000ce2ff8727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877333049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2877333049
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2408787205
Short name T662
Test name
Test status
Simulation time 1006434760 ps
CPU time 32.07 seconds
Started Jul 12 04:44:25 PM PDT 24
Finished Jul 12 04:45:01 PM PDT 24
Peak memory 250416 kb
Host smart-6af1b845-3aac-434d-9888-404e9dbc058d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408787205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2408787205
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3340747565
Short name T603
Test name
Test status
Simulation time 125361987 ps
CPU time 6.64 seconds
Started Jul 12 04:44:24 PM PDT 24
Finished Jul 12 04:44:36 PM PDT 24
Peak memory 250440 kb
Host smart-e8a4e2ac-b6be-4062-bf61-a7adcb49b1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340747565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3340747565
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2924746477
Short name T287
Test name
Test status
Simulation time 447444161 ps
CPU time 19.1 seconds
Started Jul 12 04:44:24 PM PDT 24
Finished Jul 12 04:44:48 PM PDT 24
Peak memory 250340 kb
Host smart-ba979338-aaed-49c3-8cb6-80c1a7e64654
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924746477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2924746477
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2419871181
Short name T302
Test name
Test status
Simulation time 40874376 ps
CPU time 0.84 seconds
Started Jul 12 04:44:38 PM PDT 24
Finished Jul 12 04:44:41 PM PDT 24
Peak memory 211364 kb
Host smart-e7bb5f3c-7350-4579-ac86-28527ed69104
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419871181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2419871181
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2035660235
Short name T92
Test name
Test status
Simulation time 17783687 ps
CPU time 1.13 seconds
Started Jul 12 04:44:27 PM PDT 24
Finished Jul 12 04:44:32 PM PDT 24
Peak memory 208420 kb
Host smart-6eeaca8f-a4c0-4190-aa97-239fa9e3aad6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035660235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2035660235
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.340032645
Short name T537
Test name
Test status
Simulation time 721137755 ps
CPU time 8.07 seconds
Started Jul 12 04:44:23 PM PDT 24
Finished Jul 12 04:44:37 PM PDT 24
Peak memory 217676 kb
Host smart-86753577-bf5e-4743-bcc6-25ad01463921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340032645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.340032645
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.4274334181
Short name T8
Test name
Test status
Simulation time 229306262 ps
CPU time 6.51 seconds
Started Jul 12 04:44:27 PM PDT 24
Finished Jul 12 04:44:37 PM PDT 24
Peak memory 217056 kb
Host smart-a1a8c3c9-6680-46c5-8385-2172be98df78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274334181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.4274334181
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.788187575
Short name T293
Test name
Test status
Simulation time 83416531 ps
CPU time 4.21 seconds
Started Jul 12 04:44:22 PM PDT 24
Finished Jul 12 04:44:32 PM PDT 24
Peak memory 222236 kb
Host smart-4b4c958f-2836-4a2a-bd78-6642673865bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788187575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.788187575
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.3233221160
Short name T571
Test name
Test status
Simulation time 315652955 ps
CPU time 10.15 seconds
Started Jul 12 04:44:26 PM PDT 24
Finished Jul 12 04:44:40 PM PDT 24
Peak memory 218428 kb
Host smart-b6dbdf31-d760-4562-99af-cc79f6bc08df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233221160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.3233221160
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1143383130
Short name T790
Test name
Test status
Simulation time 1341573857 ps
CPU time 17.11 seconds
Started Jul 12 04:44:26 PM PDT 24
Finished Jul 12 04:44:47 PM PDT 24
Peak memory 225668 kb
Host smart-8407ad7f-dcaa-43dd-a7a5-91a26a386303
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143383130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.1143383130
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1421904073
Short name T834
Test name
Test status
Simulation time 239249152 ps
CPU time 6.77 seconds
Started Jul 12 04:44:26 PM PDT 24
Finished Jul 12 04:44:36 PM PDT 24
Peak memory 217652 kb
Host smart-c13c251d-7175-4a3a-a3ae-1fb738c05c8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421904073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1421904073
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3251358541
Short name T478
Test name
Test status
Simulation time 1227590612 ps
CPU time 9.05 seconds
Started Jul 12 04:44:23 PM PDT 24
Finished Jul 12 04:44:37 PM PDT 24
Peak memory 217784 kb
Host smart-6fadc5ff-533d-4042-b881-ff580eeda384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251358541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3251358541
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3853672689
Short name T534
Test name
Test status
Simulation time 817436808 ps
CPU time 2.07 seconds
Started Jul 12 04:44:23 PM PDT 24
Finished Jul 12 04:44:30 PM PDT 24
Peak memory 217108 kb
Host smart-3728e343-ea9e-4335-807e-1df3333b1da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853672689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3853672689
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3238349570
Short name T567
Test name
Test status
Simulation time 225585736 ps
CPU time 18.8 seconds
Started Jul 12 04:44:27 PM PDT 24
Finished Jul 12 04:44:50 PM PDT 24
Peak memory 249988 kb
Host smart-35cd0f29-3645-43bb-afd8-4f76e53897a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238349570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3238349570
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1362163892
Short name T657
Test name
Test status
Simulation time 1134145372 ps
CPU time 8.45 seconds
Started Jul 12 04:44:22 PM PDT 24
Finished Jul 12 04:44:36 PM PDT 24
Peak memory 250400 kb
Host smart-fd101b33-046e-4c43-9043-f94096105b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362163892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1362163892
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1016262564
Short name T774
Test name
Test status
Simulation time 5535680082 ps
CPU time 93.75 seconds
Started Jul 12 04:44:29 PM PDT 24
Finished Jul 12 04:46:06 PM PDT 24
Peak memory 271488 kb
Host smart-6c74c00a-745a-4a25-8ac1-2f13a813a8db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016262564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1016262564
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3835483609
Short name T811
Test name
Test status
Simulation time 14973781 ps
CPU time 0.97 seconds
Started Jul 12 04:44:27 PM PDT 24
Finished Jul 12 04:44:32 PM PDT 24
Peak memory 210840 kb
Host smart-177d7de0-3b2c-4594-9a67-028a2cc67429
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835483609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3835483609
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3030782466
Short name T540
Test name
Test status
Simulation time 21548697 ps
CPU time 1.2 seconds
Started Jul 12 05:49:46 PM PDT 24
Finished Jul 12 05:49:48 PM PDT 24
Peak memory 208468 kb
Host smart-fb5e8fd9-0947-4d77-af10-b0aea5c26eea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030782466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3030782466
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3975917633
Short name T239
Test name
Test status
Simulation time 353229720 ps
CPU time 9.09 seconds
Started Jul 12 04:44:34 PM PDT 24
Finished Jul 12 04:44:46 PM PDT 24
Peak memory 225488 kb
Host smart-208decdc-1a45-40ac-8032-da7558d8614d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975917633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3975917633
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3454763618
Short name T90
Test name
Test status
Simulation time 636862705 ps
CPU time 6.83 seconds
Started Jul 12 04:44:31 PM PDT 24
Finished Jul 12 04:44:40 PM PDT 24
Peak memory 217020 kb
Host smart-af28429d-8f1b-4ea5-9c4c-716e3112bf30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454763618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3454763618
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2302876026
Short name T371
Test name
Test status
Simulation time 96316336 ps
CPU time 3.2 seconds
Started Jul 12 04:44:32 PM PDT 24
Finished Jul 12 04:44:37 PM PDT 24
Peak memory 217648 kb
Host smart-26010f74-d068-46be-b408-1567ea0a25e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302876026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2302876026
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.193773755
Short name T656
Test name
Test status
Simulation time 399116180 ps
CPU time 12.27 seconds
Started Jul 12 04:44:30 PM PDT 24
Finished Jul 12 04:44:46 PM PDT 24
Peak memory 225424 kb
Host smart-8084eaa9-44bb-42ba-ab22-eb6577b262bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193773755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.193773755
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1411718017
Short name T753
Test name
Test status
Simulation time 647370924 ps
CPU time 13.89 seconds
Started Jul 12 04:44:32 PM PDT 24
Finished Jul 12 04:44:48 PM PDT 24
Peak memory 225380 kb
Host smart-07765049-babd-4cb9-8f77-60085948d2bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411718017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1411718017
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1909031777
Short name T850
Test name
Test status
Simulation time 525182872 ps
CPU time 11.99 seconds
Started Jul 12 04:44:29 PM PDT 24
Finished Jul 12 04:44:44 PM PDT 24
Peak memory 217656 kb
Host smart-a0dc1e9f-672d-4e79-b5e4-4f46c18d191d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909031777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1909031777
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1151652399
Short name T508
Test name
Test status
Simulation time 423311658 ps
CPU time 7.32 seconds
Started Jul 12 04:44:30 PM PDT 24
Finished Jul 12 04:44:40 PM PDT 24
Peak memory 224216 kb
Host smart-dc2b6bc6-2555-4dd2-976e-c8e142df1a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151652399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1151652399
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.643746239
Short name T744
Test name
Test status
Simulation time 574677692 ps
CPU time 6.83 seconds
Started Jul 12 04:44:27 PM PDT 24
Finished Jul 12 04:44:38 PM PDT 24
Peak memory 217220 kb
Host smart-aad260ab-f668-4017-a0e9-ac826f2de116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643746239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.643746239
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.18756992
Short name T553
Test name
Test status
Simulation time 286797400 ps
CPU time 21.8 seconds
Started Jul 12 04:44:28 PM PDT 24
Finished Jul 12 04:44:53 PM PDT 24
Peak memory 250464 kb
Host smart-493a0c67-fb97-48b6-aa38-a6096aea31dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18756992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.18756992
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.4145033412
Short name T322
Test name
Test status
Simulation time 65165475 ps
CPU time 6.68 seconds
Started Jul 12 04:44:26 PM PDT 24
Finished Jul 12 04:44:36 PM PDT 24
Peak memory 246236 kb
Host smart-ae5c08f7-edb7-44d1-81b9-0161826616a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145033412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.4145033412
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.3988313770
Short name T262
Test name
Test status
Simulation time 8583303986 ps
CPU time 289.28 seconds
Started Jul 12 05:14:10 PM PDT 24
Finished Jul 12 05:19:00 PM PDT 24
Peak memory 332328 kb
Host smart-d2f89d1a-eebf-4e69-8f33-01a3f82eeafa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988313770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.3988313770
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1605793138
Short name T590
Test name
Test status
Simulation time 33623126 ps
CPU time 0.76 seconds
Started Jul 12 04:44:29 PM PDT 24
Finished Jul 12 04:44:33 PM PDT 24
Peak memory 208160 kb
Host smart-457d0381-cd59-4925-877f-3633376ae28e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605793138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1605793138
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.728571965
Short name T494
Test name
Test status
Simulation time 15221159 ps
CPU time 0.92 seconds
Started Jul 12 04:44:33 PM PDT 24
Finished Jul 12 04:44:36 PM PDT 24
Peak memory 208436 kb
Host smart-6d7c2e6f-6dd3-435c-95da-87fef3c0a98f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728571965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.728571965
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1666048092
Short name T825
Test name
Test status
Simulation time 875978018 ps
CPU time 16.83 seconds
Started Jul 12 04:44:29 PM PDT 24
Finished Jul 12 04:44:49 PM PDT 24
Peak memory 217700 kb
Host smart-73fa3834-9169-42af-89e1-12abf2043ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666048092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1666048092
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3769766426
Short name T442
Test name
Test status
Simulation time 267290040 ps
CPU time 8.16 seconds
Started Jul 12 04:44:29 PM PDT 24
Finished Jul 12 04:44:40 PM PDT 24
Peak memory 217360 kb
Host smart-c1308872-1161-4f49-a28f-a7608215af7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769766426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3769766426
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2553451942
Short name T379
Test name
Test status
Simulation time 133789884 ps
CPU time 3.64 seconds
Started Jul 12 04:44:31 PM PDT 24
Finished Jul 12 04:44:38 PM PDT 24
Peak memory 217580 kb
Host smart-5c712e54-cfc1-4700-86d0-1787745f2c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553451942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2553451942
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2049121801
Short name T30
Test name
Test status
Simulation time 366029447 ps
CPU time 16.52 seconds
Started Jul 12 04:44:27 PM PDT 24
Finished Jul 12 04:44:47 PM PDT 24
Peak memory 218364 kb
Host smart-d1bd5344-3a70-489b-9056-aa508af505c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049121801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2049121801
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.37942961
Short name T212
Test name
Test status
Simulation time 2344631976 ps
CPU time 20.7 seconds
Started Jul 12 04:44:27 PM PDT 24
Finished Jul 12 04:44:51 PM PDT 24
Peak memory 225500 kb
Host smart-b39a7598-f65f-41ce-9d92-28268c0c8a95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37942961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_dig
est.37942961
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2017108248
Short name T757
Test name
Test status
Simulation time 2100836275 ps
CPU time 7.19 seconds
Started Jul 12 04:44:28 PM PDT 24
Finished Jul 12 04:44:39 PM PDT 24
Peak memory 217584 kb
Host smart-65b61522-c905-46d1-8421-d23b7fa805eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017108248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2017108248
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2193255244
Short name T202
Test name
Test status
Simulation time 5501686759 ps
CPU time 10.39 seconds
Started Jul 12 04:44:27 PM PDT 24
Finished Jul 12 04:44:41 PM PDT 24
Peak memory 217852 kb
Host smart-cbe17384-b0a2-4892-b6cb-3f0677b28257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193255244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2193255244
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1601376088
Short name T760
Test name
Test status
Simulation time 135055819 ps
CPU time 2.16 seconds
Started Jul 12 06:10:02 PM PDT 24
Finished Jul 12 06:11:47 PM PDT 24
Peak memory 217116 kb
Host smart-a4f5b68c-ebcb-4292-a29e-1c868b7f01e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601376088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1601376088
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2899348115
Short name T220
Test name
Test status
Simulation time 663329597 ps
CPU time 17.22 seconds
Started Jul 12 04:44:29 PM PDT 24
Finished Jul 12 04:44:49 PM PDT 24
Peak memory 250360 kb
Host smart-8fcfaba1-99e1-4ca4-8e1a-affc952b3b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899348115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2899348115
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1304404896
Short name T549
Test name
Test status
Simulation time 249151261 ps
CPU time 9.64 seconds
Started Jul 12 04:44:28 PM PDT 24
Finished Jul 12 04:44:41 PM PDT 24
Peak memory 250680 kb
Host smart-ab60e860-bbe7-4110-aefc-66ec3f823cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304404896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1304404896
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.928320759
Short name T474
Test name
Test status
Simulation time 7638866226 ps
CPU time 151.72 seconds
Started Jul 12 04:44:27 PM PDT 24
Finished Jul 12 04:47:02 PM PDT 24
Peak memory 276120 kb
Host smart-560e7a19-52b2-431e-a288-9ac3a928db51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928320759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.928320759
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.3482194344
Short name T143
Test name
Test status
Simulation time 21962769431 ps
CPU time 897.36 seconds
Started Jul 12 04:44:28 PM PDT 24
Finished Jul 12 04:59:28 PM PDT 24
Peak memory 283408 kb
Host smart-8b6dac39-424f-4fd0-b314-10b78243ecdf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3482194344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.3482194344
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3282688877
Short name T512
Test name
Test status
Simulation time 223157457 ps
CPU time 1.12 seconds
Started Jul 12 04:44:33 PM PDT 24
Finished Jul 12 04:44:36 PM PDT 24
Peak memory 208488 kb
Host smart-4641a164-3181-4862-bc38-f66907dab649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282688877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3282688877
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.664223993
Short name T724
Test name
Test status
Simulation time 1139678402 ps
CPU time 11.76 seconds
Started Jul 12 04:44:32 PM PDT 24
Finished Jul 12 04:44:46 PM PDT 24
Peak memory 217696 kb
Host smart-f1e5b55c-6d70-452f-a494-f477e682b92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664223993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.664223993
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1474376660
Short name T785
Test name
Test status
Simulation time 360060679 ps
CPU time 9.75 seconds
Started Jul 12 04:44:36 PM PDT 24
Finished Jul 12 04:44:48 PM PDT 24
Peak memory 217124 kb
Host smart-d2d3bed4-83d0-4266-8153-bb505da16f2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474376660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1474376660
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3143013115
Short name T822
Test name
Test status
Simulation time 231184611 ps
CPU time 2.95 seconds
Started Jul 12 04:44:33 PM PDT 24
Finished Jul 12 04:44:39 PM PDT 24
Peak memory 217652 kb
Host smart-46eb84ae-9510-4c00-aaf9-503b614ef85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143013115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3143013115
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.161797330
Short name T57
Test name
Test status
Simulation time 472137390 ps
CPU time 16.11 seconds
Started Jul 12 04:44:32 PM PDT 24
Finished Jul 12 04:44:51 PM PDT 24
Peak memory 218364 kb
Host smart-ec952441-1173-47b5-a7ed-f42ab78dbd33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161797330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.161797330
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.270600101
Short name T313
Test name
Test status
Simulation time 1877657243 ps
CPU time 11.19 seconds
Started Jul 12 04:44:35 PM PDT 24
Finished Jul 12 04:44:49 PM PDT 24
Peak memory 225388 kb
Host smart-00da9fbf-87c4-45c1-b37d-f94ed0bd2076
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270600101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_di
gest.270600101
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.52217575
Short name T161
Test name
Test status
Simulation time 474955334 ps
CPU time 13.17 seconds
Started Jul 12 04:44:35 PM PDT 24
Finished Jul 12 04:44:51 PM PDT 24
Peak memory 217604 kb
Host smart-b3ef8b1a-84f4-49cf-a0ef-a7a0dc95df0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52217575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.52217575
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1801063775
Short name T51
Test name
Test status
Simulation time 566359593 ps
CPU time 9.3 seconds
Started Jul 12 04:44:36 PM PDT 24
Finished Jul 12 04:44:47 PM PDT 24
Peak memory 217776 kb
Host smart-6cf6fd72-5119-42f5-b374-0c06bddc088d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801063775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1801063775
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3280092326
Short name T60
Test name
Test status
Simulation time 27568959 ps
CPU time 1.99 seconds
Started Jul 12 04:44:35 PM PDT 24
Finished Jul 12 04:44:40 PM PDT 24
Peak memory 213752 kb
Host smart-e3b01c84-d996-47cb-9198-92f0a9da23a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280092326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3280092326
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.26848629
Short name T359
Test name
Test status
Simulation time 1483375417 ps
CPU time 19.79 seconds
Started Jul 12 04:44:33 PM PDT 24
Finished Jul 12 04:44:55 PM PDT 24
Peak memory 250400 kb
Host smart-fb9616c3-8298-461e-9810-3da896493a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26848629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.26848629
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2282213216
Short name T266
Test name
Test status
Simulation time 272062894 ps
CPU time 7.36 seconds
Started Jul 12 04:44:35 PM PDT 24
Finished Jul 12 04:44:45 PM PDT 24
Peak memory 249964 kb
Host smart-3e4ed04d-ce92-4019-a54f-89e138a8022f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282213216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2282213216
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.212036549
Short name T600
Test name
Test status
Simulation time 18102484982 ps
CPU time 111.2 seconds
Started Jul 12 04:44:37 PM PDT 24
Finished Jul 12 04:46:31 PM PDT 24
Peak memory 282228 kb
Host smart-cf7edfd8-fa26-49bd-87b2-c9a0811cde11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212036549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.212036549
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.2984326195
Short name T818
Test name
Test status
Simulation time 146671975395 ps
CPU time 385.57 seconds
Started Jul 12 04:44:32 PM PDT 24
Finished Jul 12 04:51:00 PM PDT 24
Peak memory 372488 kb
Host smart-8ac341e6-570f-4001-b5b1-58aeba088efc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2984326195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.2984326195
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.982312153
Short name T788
Test name
Test status
Simulation time 32640988 ps
CPU time 0.9 seconds
Started Jul 12 04:44:32 PM PDT 24
Finished Jul 12 04:44:35 PM PDT 24
Peak memory 208412 kb
Host smart-03b3ffc5-a2fb-40ec-b6cd-7a83d30a5657
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982312153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.982312153
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.641089565
Short name T240
Test name
Test status
Simulation time 695285013 ps
CPU time 13.19 seconds
Started Jul 12 04:44:36 PM PDT 24
Finished Jul 12 04:44:51 PM PDT 24
Peak memory 217592 kb
Host smart-a01b9c5d-e512-4d62-8571-5e984405adeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641089565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.641089565
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3465443583
Short name T497
Test name
Test status
Simulation time 333880779 ps
CPU time 4.21 seconds
Started Jul 12 04:44:33 PM PDT 24
Finished Jul 12 04:44:40 PM PDT 24
Peak memory 217128 kb
Host smart-c174fc3a-9128-4a8a-a976-ed245adf00fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465443583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3465443583
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2668697975
Short name T457
Test name
Test status
Simulation time 27478709 ps
CPU time 1.96 seconds
Started Jul 12 04:44:37 PM PDT 24
Finished Jul 12 04:44:41 PM PDT 24
Peak memory 221320 kb
Host smart-82ed02a4-f7ae-4801-ac51-d62a05647052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668697975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2668697975
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.4247854666
Short name T332
Test name
Test status
Simulation time 330128495 ps
CPU time 13.98 seconds
Started Jul 12 04:44:33 PM PDT 24
Finished Jul 12 04:44:50 PM PDT 24
Peak memory 217528 kb
Host smart-e98bbe84-51a9-4816-a383-b5b0a4e09b21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247854666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.4247854666
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2493631271
Short name T577
Test name
Test status
Simulation time 216210215 ps
CPU time 9.03 seconds
Started Jul 12 04:44:34 PM PDT 24
Finished Jul 12 04:44:45 PM PDT 24
Peak memory 225440 kb
Host smart-f465d356-edde-4fbb-bd5e-2a90d127feba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493631271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2493631271
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1777499766
Short name T695
Test name
Test status
Simulation time 128116531 ps
CPU time 1.6 seconds
Started Jul 12 04:44:37 PM PDT 24
Finished Jul 12 04:44:41 PM PDT 24
Peak memory 213072 kb
Host smart-3997f67e-bebe-4130-b5e3-b8111be822d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777499766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1777499766
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3842085334
Short name T290
Test name
Test status
Simulation time 316821686 ps
CPU time 19.61 seconds
Started Jul 12 04:44:34 PM PDT 24
Finished Jul 12 04:44:56 PM PDT 24
Peak memory 250440 kb
Host smart-e7e7062c-e6a1-4920-9f71-cb85f188a7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842085334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3842085334
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2658568510
Short name T510
Test name
Test status
Simulation time 152745023 ps
CPU time 3.88 seconds
Started Jul 12 04:44:33 PM PDT 24
Finished Jul 12 04:44:39 PM PDT 24
Peak memory 222208 kb
Host smart-08c0aefe-abde-4325-8cf0-39ae8e4b88de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658568510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2658568510
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2379633783
Short name T764
Test name
Test status
Simulation time 3438341584 ps
CPU time 137.68 seconds
Started Jul 12 04:44:36 PM PDT 24
Finished Jul 12 04:46:56 PM PDT 24
Peak memory 274744 kb
Host smart-efdfccae-7e1c-40c0-9a64-4d26b8b7e4bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379633783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2379633783
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2444589507
Short name T310
Test name
Test status
Simulation time 15088939 ps
CPU time 1.29 seconds
Started Jul 12 04:44:36 PM PDT 24
Finished Jul 12 04:44:40 PM PDT 24
Peak memory 211300 kb
Host smart-2021fb3f-4aaf-4476-8bb2-02e9fb0a9d6e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444589507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2444589507
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3191925736
Short name T232
Test name
Test status
Simulation time 21700613 ps
CPU time 0.93 seconds
Started Jul 12 04:42:53 PM PDT 24
Finished Jul 12 04:42:55 PM PDT 24
Peak memory 208424 kb
Host smart-77d6e1e3-7697-4387-a13a-d9a2b0e263ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191925736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3191925736
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1040553846
Short name T446
Test name
Test status
Simulation time 13730623 ps
CPU time 0.98 seconds
Started Jul 12 04:42:58 PM PDT 24
Finished Jul 12 04:43:02 PM PDT 24
Peak memory 208664 kb
Host smart-47036f6e-43da-40e5-92b8-cee9219a7eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040553846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1040553846
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3598625169
Short name T456
Test name
Test status
Simulation time 1338248284 ps
CPU time 10.86 seconds
Started Jul 12 04:42:55 PM PDT 24
Finished Jul 12 04:43:07 PM PDT 24
Peak memory 217628 kb
Host smart-5f61c3b8-a180-40b8-9401-d33306533498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598625169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3598625169
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.2527413993
Short name T634
Test name
Test status
Simulation time 1109031912 ps
CPU time 26.14 seconds
Started Jul 12 04:42:55 PM PDT 24
Finished Jul 12 04:43:22 PM PDT 24
Peak memory 217048 kb
Host smart-88f5f08c-e75d-443b-ac4d-95ee1565f598
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527413993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.2527413993
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.4055989992
Short name T646
Test name
Test status
Simulation time 5358656445 ps
CPU time 58.82 seconds
Started Jul 12 04:43:05 PM PDT 24
Finished Jul 12 04:44:07 PM PDT 24
Peak memory 218304 kb
Host smart-62729f0b-cf10-4ea2-b1e7-4ddf804b9ad2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055989992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.4055989992
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.312769685
Short name T615
Test name
Test status
Simulation time 360620945 ps
CPU time 2.47 seconds
Started Jul 12 04:42:57 PM PDT 24
Finished Jul 12 04:43:00 PM PDT 24
Peak memory 217124 kb
Host smart-68c0f1a1-5418-4695-948e-b2723395e31a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312769685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.312769685
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.2579351544
Short name T793
Test name
Test status
Simulation time 246115356 ps
CPU time 7.17 seconds
Started Jul 12 04:43:05 PM PDT 24
Finished Jul 12 04:43:16 PM PDT 24
Peak memory 222300 kb
Host smart-7fb1b02a-5421-4076-8826-04b3af1b03af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579351544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.2579351544
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3960116144
Short name T861
Test name
Test status
Simulation time 783936470 ps
CPU time 23.25 seconds
Started Jul 12 04:43:04 PM PDT 24
Finished Jul 12 04:43:31 PM PDT 24
Peak memory 217080 kb
Host smart-2d4fba5e-32f1-4973-bd31-8e240ecbd3f6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960116144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3960116144
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1602377312
Short name T633
Test name
Test status
Simulation time 188152791 ps
CPU time 2.7 seconds
Started Jul 12 04:42:54 PM PDT 24
Finished Jul 12 04:42:58 PM PDT 24
Peak memory 217028 kb
Host smart-17aa795b-031e-4234-a5c5-f375adc1448d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602377312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
1602377312
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.17227292
Short name T686
Test name
Test status
Simulation time 2868756841 ps
CPU time 72.74 seconds
Started Jul 12 04:42:56 PM PDT 24
Finished Jul 12 04:44:10 PM PDT 24
Peak memory 276680 kb
Host smart-ac48cebf-746f-43a3-960e-03bfeb2c8c78
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17227292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
state_failure.17227292
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2765761957
Short name T743
Test name
Test status
Simulation time 1382996001 ps
CPU time 15.46 seconds
Started Jul 12 04:42:56 PM PDT 24
Finished Jul 12 04:43:13 PM PDT 24
Peak memory 245384 kb
Host smart-cc69bdd9-2643-40a8-9741-eb06a334255c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765761957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2765761957
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2224551621
Short name T326
Test name
Test status
Simulation time 44624231 ps
CPU time 2.33 seconds
Started Jul 12 04:42:54 PM PDT 24
Finished Jul 12 04:42:58 PM PDT 24
Peak memory 217692 kb
Host smart-2ee9f71e-95c1-403f-a74f-f1fc98d3f44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224551621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2224551621
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1032128854
Short name T74
Test name
Test status
Simulation time 251748300 ps
CPU time 16.69 seconds
Started Jul 12 04:42:55 PM PDT 24
Finished Jul 12 04:43:13 PM PDT 24
Peak memory 217068 kb
Host smart-807570b5-5b51-4772-9a16-5a51abf79ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032128854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1032128854
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3280063636
Short name T78
Test name
Test status
Simulation time 3214168799 ps
CPU time 37.55 seconds
Started Jul 12 04:43:03 PM PDT 24
Finished Jul 12 04:43:44 PM PDT 24
Peak memory 282120 kb
Host smart-3925c7bc-6743-4c1b-8346-a51ea9a14d26
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280063636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3280063636
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.201815107
Short name T460
Test name
Test status
Simulation time 618113131 ps
CPU time 21.51 seconds
Started Jul 12 04:42:54 PM PDT 24
Finished Jul 12 04:43:17 PM PDT 24
Peak memory 225516 kb
Host smart-cc9e868a-21a6-4a84-a567-580fae46c427
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201815107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.201815107
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3734938674
Short name T823
Test name
Test status
Simulation time 204351254 ps
CPU time 8.84 seconds
Started Jul 12 04:42:58 PM PDT 24
Finished Jul 12 04:43:10 PM PDT 24
Peak memory 225420 kb
Host smart-03796041-e5f5-442d-b3f6-c913a7facc6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734938674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3734938674
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2506751058
Short name T500
Test name
Test status
Simulation time 914977220 ps
CPU time 7.47 seconds
Started Jul 12 04:51:14 PM PDT 24
Finished Jul 12 04:51:22 PM PDT 24
Peak memory 217628 kb
Host smart-2fdd648d-c138-422f-b52d-c97177d948f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506751058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
506751058
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1604120614
Short name T616
Test name
Test status
Simulation time 924229778 ps
CPU time 7.53 seconds
Started Jul 12 04:42:53 PM PDT 24
Finished Jul 12 04:43:02 PM PDT 24
Peak memory 225508 kb
Host smart-789af7c3-66e7-4e39-9a03-4df9163e7123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604120614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1604120614
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3271785141
Short name T595
Test name
Test status
Simulation time 105380329 ps
CPU time 3.39 seconds
Started Jul 12 04:42:53 PM PDT 24
Finished Jul 12 04:42:58 PM PDT 24
Peak memory 217144 kb
Host smart-7827fda1-1f23-4adf-a925-c9bf005251bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271785141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3271785141
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1726749581
Short name T824
Test name
Test status
Simulation time 1106018307 ps
CPU time 24.17 seconds
Started Jul 12 04:43:03 PM PDT 24
Finished Jul 12 04:43:31 PM PDT 24
Peak memory 250396 kb
Host smart-eeb344ad-2623-4c21-b478-8e4fb4478baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726749581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1726749581
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.828203846
Short name T551
Test name
Test status
Simulation time 86477946 ps
CPU time 6.07 seconds
Started Jul 12 04:42:53 PM PDT 24
Finished Jul 12 04:43:00 PM PDT 24
Peak memory 245872 kb
Host smart-af1c96f6-9b30-493e-9cdc-7c3d32131faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828203846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.828203846
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1822270039
Short name T745
Test name
Test status
Simulation time 10733751072 ps
CPU time 375.76 seconds
Started Jul 12 04:42:55 PM PDT 24
Finished Jul 12 04:49:12 PM PDT 24
Peak memory 250408 kb
Host smart-2af350d6-3969-453d-be45-59fec6433c6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822270039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1822270039
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.1117007323
Short name T105
Test name
Test status
Simulation time 23251193217 ps
CPU time 862.84 seconds
Started Jul 12 04:42:54 PM PDT 24
Finished Jul 12 04:57:19 PM PDT 24
Peak memory 479888 kb
Host smart-8befa996-f771-459c-9b3a-5196f9bc2939
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1117007323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.1117007323
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.283524051
Short name T368
Test name
Test status
Simulation time 26151289 ps
CPU time 1.05 seconds
Started Jul 12 04:43:03 PM PDT 24
Finished Jul 12 04:43:07 PM PDT 24
Peak memory 211228 kb
Host smart-655b759c-3d9c-49bf-8021-71a4052d1ee5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283524051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.283524051
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3779412232
Short name T395
Test name
Test status
Simulation time 33870997 ps
CPU time 0.97 seconds
Started Jul 12 04:44:38 PM PDT 24
Finished Jul 12 04:44:42 PM PDT 24
Peak memory 208528 kb
Host smart-ff527e75-6e5d-43e9-867c-e4dbf0e30c5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779412232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3779412232
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.3886755100
Short name T591
Test name
Test status
Simulation time 654146712 ps
CPU time 9.71 seconds
Started Jul 12 04:44:41 PM PDT 24
Finished Jul 12 04:44:53 PM PDT 24
Peak memory 217700 kb
Host smart-cc284f4b-ef97-4408-ae7d-3e23a9dc3c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886755100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3886755100
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1373448600
Short name T836
Test name
Test status
Simulation time 1166354094 ps
CPU time 1.76 seconds
Started Jul 12 04:44:39 PM PDT 24
Finished Jul 12 04:44:43 PM PDT 24
Peak memory 217260 kb
Host smart-5e3aaa16-5ef0-41dd-93ff-1e3978c18cf9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373448600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1373448600
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2793920762
Short name T331
Test name
Test status
Simulation time 775923128 ps
CPU time 2.82 seconds
Started Jul 12 04:44:39 PM PDT 24
Finished Jul 12 04:44:45 PM PDT 24
Peak memory 221964 kb
Host smart-db6d2625-d034-40dc-8a39-2d04fe317419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793920762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2793920762
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.483730
Short name T651
Test name
Test status
Simulation time 679171301 ps
CPU time 15.72 seconds
Started Jul 12 04:44:38 PM PDT 24
Finished Jul 12 04:44:56 PM PDT 24
Peak memory 217912 kb
Host smart-b0d7e8e2-043e-48e1-8593-3165654cf9d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.483730
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.296867223
Short name T588
Test name
Test status
Simulation time 1400979035 ps
CPU time 10.22 seconds
Started Jul 12 04:44:37 PM PDT 24
Finished Jul 12 04:44:49 PM PDT 24
Peak memory 225432 kb
Host smart-105263db-e6e9-489b-980a-e7131aeb5b76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296867223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_di
gest.296867223
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.428352230
Short name T341
Test name
Test status
Simulation time 315757537 ps
CPU time 9.24 seconds
Started Jul 12 04:44:39 PM PDT 24
Finished Jul 12 04:44:52 PM PDT 24
Peak memory 225440 kb
Host smart-8b96882f-e003-4ad4-9ae5-c4181b6a4f99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428352230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.428352230
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2104658602
Short name T498
Test name
Test status
Simulation time 254673177 ps
CPU time 6.76 seconds
Started Jul 12 04:44:38 PM PDT 24
Finished Jul 12 04:44:47 PM PDT 24
Peak memory 225468 kb
Host smart-2795fbfa-0523-41b9-9460-f654816fdb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104658602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2104658602
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.4118004443
Short name T738
Test name
Test status
Simulation time 163053512 ps
CPU time 3.37 seconds
Started Jul 12 04:44:35 PM PDT 24
Finished Jul 12 04:44:41 PM PDT 24
Peak memory 214328 kb
Host smart-2292e16e-d316-4986-a2f5-01dfc16cce13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118004443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.4118004443
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3843330487
Short name T274
Test name
Test status
Simulation time 425992201 ps
CPU time 22.07 seconds
Started Jul 12 04:44:40 PM PDT 24
Finished Jul 12 04:45:05 PM PDT 24
Peak memory 246024 kb
Host smart-8f8e91ea-8426-4e35-9ff6-cd87ba5ba1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843330487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3843330487
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2970121854
Short name T398
Test name
Test status
Simulation time 246565213 ps
CPU time 6.46 seconds
Started Jul 12 04:44:40 PM PDT 24
Finished Jul 12 04:44:49 PM PDT 24
Peak memory 246508 kb
Host smart-35c7d4bd-de68-4eb4-aa0e-ec8b16a586f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970121854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2970121854
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.578107647
Short name T803
Test name
Test status
Simulation time 16527619438 ps
CPU time 93.09 seconds
Started Jul 12 04:44:38 PM PDT 24
Finished Jul 12 04:46:13 PM PDT 24
Peak memory 275124 kb
Host smart-92bbcdd2-9b7d-4cba-9a5f-a5c41f1a784a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578107647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.578107647
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3761460880
Short name T725
Test name
Test status
Simulation time 76938181 ps
CPU time 1.12 seconds
Started Jul 12 04:44:41 PM PDT 24
Finished Jul 12 04:44:44 PM PDT 24
Peak memory 217220 kb
Host smart-4e255a67-9f12-4b27-9536-313d4567af26
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761460880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3761460880
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2527890121
Short name T66
Test name
Test status
Simulation time 12755603 ps
CPU time 0.99 seconds
Started Jul 12 04:44:47 PM PDT 24
Finished Jul 12 04:44:49 PM PDT 24
Peak memory 208440 kb
Host smart-c5675bca-7105-4335-be08-462428c58b99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527890121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2527890121
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3446407136
Short name T229
Test name
Test status
Simulation time 232266639 ps
CPU time 8.8 seconds
Started Jul 12 04:44:41 PM PDT 24
Finished Jul 12 04:44:52 PM PDT 24
Peak memory 217732 kb
Host smart-7ed75a78-16c2-49f2-9605-960c74db6954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446407136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3446407136
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1589683588
Short name T401
Test name
Test status
Simulation time 122928299 ps
CPU time 1.97 seconds
Started Jul 12 04:44:42 PM PDT 24
Finished Jul 12 04:44:46 PM PDT 24
Peak memory 217100 kb
Host smart-504b79a0-baa2-4bc8-b364-0571f7141e9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589683588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1589683588
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2570557510
Short name T418
Test name
Test status
Simulation time 28212997 ps
CPU time 1.83 seconds
Started Jul 12 04:44:41 PM PDT 24
Finished Jul 12 04:44:45 PM PDT 24
Peak memory 221456 kb
Host smart-cf3d4acc-4ebf-45de-a58f-55f5673003b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570557510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2570557510
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.316856459
Short name T750
Test name
Test status
Simulation time 375356391 ps
CPU time 9.91 seconds
Started Jul 12 04:44:42 PM PDT 24
Finished Jul 12 04:44:54 PM PDT 24
Peak memory 217700 kb
Host smart-cf760571-cc4f-468e-9c15-ecb25cb313aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316856459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.316856459
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.719462534
Short name T360
Test name
Test status
Simulation time 715061639 ps
CPU time 6.86 seconds
Started Jul 12 04:44:40 PM PDT 24
Finished Jul 12 04:44:50 PM PDT 24
Peak memory 217636 kb
Host smart-d59760f6-f879-4c69-bbc1-06ef4161915a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719462534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.719462534
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.522795310
Short name T847
Test name
Test status
Simulation time 3083932712 ps
CPU time 8.38 seconds
Started Jul 12 04:44:40 PM PDT 24
Finished Jul 12 04:44:51 PM PDT 24
Peak memory 217692 kb
Host smart-a90b0846-17c0-47f1-9380-01e52538d6bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522795310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.522795310
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.4164361962
Short name T203
Test name
Test status
Simulation time 269178317 ps
CPU time 7.47 seconds
Started Jul 12 04:44:39 PM PDT 24
Finished Jul 12 04:44:49 PM PDT 24
Peak memory 225444 kb
Host smart-878ce924-e01b-4119-8687-e154bdd3da94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164361962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.4164361962
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.946711480
Short name T640
Test name
Test status
Simulation time 38106962 ps
CPU time 2.52 seconds
Started Jul 12 04:44:41 PM PDT 24
Finished Jul 12 04:44:46 PM PDT 24
Peak memory 213816 kb
Host smart-43fba859-412e-4459-8e98-ecf5e4422b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946711480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.946711480
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2391129307
Short name T213
Test name
Test status
Simulation time 185941360 ps
CPU time 20.75 seconds
Started Jul 12 04:44:41 PM PDT 24
Finished Jul 12 04:45:04 PM PDT 24
Peak memory 250480 kb
Host smart-c966a383-97ac-4908-abd9-bbfe0f834a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391129307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2391129307
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3210010159
Short name T860
Test name
Test status
Simulation time 197127448 ps
CPU time 3.66 seconds
Started Jul 12 04:44:40 PM PDT 24
Finished Jul 12 04:44:46 PM PDT 24
Peak memory 225828 kb
Host smart-394288eb-9eac-4f52-a4e2-f17672407241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210010159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3210010159
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1735200236
Short name T852
Test name
Test status
Simulation time 6093762078 ps
CPU time 254.63 seconds
Started Jul 12 04:44:41 PM PDT 24
Finished Jul 12 04:48:58 PM PDT 24
Peak memory 496176 kb
Host smart-dd8133cd-6bb6-4ae5-8fca-c43b6b37d6bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735200236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1735200236
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.441580625
Short name T104
Test name
Test status
Simulation time 194337998488 ps
CPU time 1490.01 seconds
Started Jul 12 04:44:46 PM PDT 24
Finished Jul 12 05:09:37 PM PDT 24
Peak memory 283360 kb
Host smart-5716c8fb-f238-49f0-8cec-9b9ee468b11f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=441580625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.441580625
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.492348861
Short name T814
Test name
Test status
Simulation time 11588959 ps
CPU time 0.77 seconds
Started Jul 12 04:44:36 PM PDT 24
Finished Jul 12 04:44:39 PM PDT 24
Peak memory 208164 kb
Host smart-88773809-f5f9-42eb-86ff-69370ae1eb17
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492348861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct
rl_volatile_unlock_smoke.492348861
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2190067190
Short name T99
Test name
Test status
Simulation time 132742808 ps
CPU time 0.85 seconds
Started Jul 12 04:44:46 PM PDT 24
Finished Jul 12 04:44:49 PM PDT 24
Peak memory 208324 kb
Host smart-f72d8971-fc10-4f02-8457-a3e76f38097f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190067190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2190067190
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.138011621
Short name T294
Test name
Test status
Simulation time 571879967 ps
CPU time 18.4 seconds
Started Jul 12 04:44:47 PM PDT 24
Finished Jul 12 04:45:07 PM PDT 24
Peak memory 225456 kb
Host smart-acbbe4bd-0f3b-4299-ac82-d4f8505c0bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138011621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.138011621
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.891313025
Short name T168
Test name
Test status
Simulation time 3705907391 ps
CPU time 10.98 seconds
Started Jul 12 04:44:56 PM PDT 24
Finished Jul 12 04:45:10 PM PDT 24
Peak memory 217172 kb
Host smart-410e0b1a-374a-4f8a-88cf-533ef62a5216
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891313025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.891313025
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2651247322
Short name T691
Test name
Test status
Simulation time 69390782 ps
CPU time 3.35 seconds
Started Jul 12 04:44:56 PM PDT 24
Finished Jul 12 04:45:01 PM PDT 24
Peak memory 217692 kb
Host smart-cefe91d7-7c2c-4140-8105-0cd20d1a0246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651247322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2651247322
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1331338295
Short name T831
Test name
Test status
Simulation time 610640922 ps
CPU time 21.99 seconds
Started Jul 12 04:44:47 PM PDT 24
Finished Jul 12 04:45:10 PM PDT 24
Peak memory 218416 kb
Host smart-e08d62e2-6d7b-48f7-bd0a-03bc85b7f10d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331338295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1331338295
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.908324957
Short name T236
Test name
Test status
Simulation time 412956297 ps
CPU time 9.42 seconds
Started Jul 12 04:44:47 PM PDT 24
Finished Jul 12 04:44:58 PM PDT 24
Peak memory 225396 kb
Host smart-56cc36e5-9df2-4c7e-9343-57dee1752165
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908324957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.908324957
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.292809537
Short name T238
Test name
Test status
Simulation time 723473421 ps
CPU time 13.17 seconds
Started Jul 12 04:44:46 PM PDT 24
Finished Jul 12 04:45:01 PM PDT 24
Peak memory 217480 kb
Host smart-28740b97-da76-4bce-8a38-8cb6a195ab64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292809537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.292809537
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.852127923
Short name T480
Test name
Test status
Simulation time 869057603 ps
CPU time 10.01 seconds
Started Jul 12 04:44:48 PM PDT 24
Finished Jul 12 04:45:00 PM PDT 24
Peak memory 225464 kb
Host smart-177187fb-be54-4772-90b4-477a51cb470a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852127923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.852127923
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2917217282
Short name T72
Test name
Test status
Simulation time 171296013 ps
CPU time 1.79 seconds
Started Jul 12 04:44:46 PM PDT 24
Finished Jul 12 04:44:50 PM PDT 24
Peak memory 216956 kb
Host smart-c8112d6c-ee99-4ab4-b06c-6a60e9ab1f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917217282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2917217282
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.847236490
Short name T650
Test name
Test status
Simulation time 864344643 ps
CPU time 24.47 seconds
Started Jul 12 04:44:47 PM PDT 24
Finished Jul 12 04:45:13 PM PDT 24
Peak memory 250440 kb
Host smart-c742bde4-8788-49e1-8402-b1b09f7fa644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847236490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.847236490
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2510077625
Short name T211
Test name
Test status
Simulation time 44936444 ps
CPU time 6.61 seconds
Started Jul 12 04:44:45 PM PDT 24
Finished Jul 12 04:44:53 PM PDT 24
Peak memory 249780 kb
Host smart-569f5305-eae1-4281-94a5-f0405f288634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510077625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2510077625
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1244065997
Short name T31
Test name
Test status
Simulation time 15131928779 ps
CPU time 159.3 seconds
Started Jul 12 04:44:45 PM PDT 24
Finished Jul 12 04:47:26 PM PDT 24
Peak memory 283204 kb
Host smart-509a52c1-0e67-4674-8c52-d58a895acc23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244065997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1244065997
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3610011410
Short name T771
Test name
Test status
Simulation time 41548816 ps
CPU time 0.93 seconds
Started Jul 12 04:44:45 PM PDT 24
Finished Jul 12 04:44:47 PM PDT 24
Peak memory 211372 kb
Host smart-a2869dcf-54b1-4b7d-b4bb-26663a5ca5e5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610011410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.3610011410
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1644767958
Short name T383
Test name
Test status
Simulation time 19899728 ps
CPU time 1.16 seconds
Started Jul 12 04:44:50 PM PDT 24
Finished Jul 12 04:44:52 PM PDT 24
Peak memory 208536 kb
Host smart-2a994d79-3abb-4fb8-bb88-ec8bf79fe9f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644767958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1644767958
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3455898203
Short name T466
Test name
Test status
Simulation time 1571235912 ps
CPU time 11.69 seconds
Started Jul 12 04:44:45 PM PDT 24
Finished Jul 12 04:44:58 PM PDT 24
Peak memory 217664 kb
Host smart-2d8b036b-5ed5-4fac-9af1-684e197f32d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455898203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3455898203
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2054809287
Short name T532
Test name
Test status
Simulation time 369251167 ps
CPU time 1.85 seconds
Started Jul 12 04:44:48 PM PDT 24
Finished Jul 12 04:44:51 PM PDT 24
Peak memory 217100 kb
Host smart-6e2569cf-8944-4837-9c67-4fa78157fe2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054809287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2054809287
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1717716933
Short name T355
Test name
Test status
Simulation time 492903366 ps
CPU time 4.47 seconds
Started Jul 12 04:44:51 PM PDT 24
Finished Jul 12 04:44:57 PM PDT 24
Peak memory 217700 kb
Host smart-36f2072a-e739-42aa-92e8-b9aa7e635878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717716933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1717716933
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2681274093
Short name T606
Test name
Test status
Simulation time 1289240607 ps
CPU time 24.29 seconds
Started Jul 12 04:44:56 PM PDT 24
Finished Jul 12 04:45:22 PM PDT 24
Peak memory 225484 kb
Host smart-55d03199-3344-496c-a0ca-24ff0a43be13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681274093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2681274093
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2895211122
Short name T404
Test name
Test status
Simulation time 638496546 ps
CPU time 12.8 seconds
Started Jul 12 04:44:53 PM PDT 24
Finished Jul 12 04:45:08 PM PDT 24
Peak memory 225356 kb
Host smart-3626bd8d-5a56-4c1b-a12d-4564bbb99bf9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895211122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2895211122
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2279833732
Short name T314
Test name
Test status
Simulation time 321174510 ps
CPU time 11.21 seconds
Started Jul 12 04:44:50 PM PDT 24
Finished Jul 12 04:45:02 PM PDT 24
Peak memory 217564 kb
Host smart-498d9ee1-2b06-4b0e-8d92-ccf0a2a57edd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279833732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2279833732
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3770840613
Short name T333
Test name
Test status
Simulation time 2284786648 ps
CPU time 14.21 seconds
Started Jul 12 04:44:46 PM PDT 24
Finished Jul 12 04:45:02 PM PDT 24
Peak memory 225548 kb
Host smart-f65709fe-a246-4b9a-a31b-3c05033d48b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770840613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3770840613
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1934030306
Short name T586
Test name
Test status
Simulation time 138453872 ps
CPU time 2.62 seconds
Started Jul 12 04:44:46 PM PDT 24
Finished Jul 12 04:44:50 PM PDT 24
Peak memory 214260 kb
Host smart-8b7580d7-b68e-4495-83a6-3ccf2d62f376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934030306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1934030306
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3712465149
Short name T374
Test name
Test status
Simulation time 343654815 ps
CPU time 26.47 seconds
Started Jul 12 04:44:45 PM PDT 24
Finished Jul 12 04:45:13 PM PDT 24
Peak memory 250452 kb
Host smart-b8aff724-29e0-4055-97da-621dee6b14e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712465149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3712465149
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.4043539930
Short name T556
Test name
Test status
Simulation time 295452070 ps
CPU time 7.51 seconds
Started Jul 12 04:44:47 PM PDT 24
Finished Jul 12 04:44:57 PM PDT 24
Peak memory 249964 kb
Host smart-5235bb5b-f545-48e0-b1a6-3b43a6e20ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043539930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.4043539930
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.3552360998
Short name T611
Test name
Test status
Simulation time 836129369 ps
CPU time 30.43 seconds
Started Jul 12 04:44:52 PM PDT 24
Finished Jul 12 04:45:24 PM PDT 24
Peak memory 250460 kb
Host smart-45b0229b-6e3f-485d-bd36-53264aab7a07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552360998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.3552360998
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.1992848710
Short name T144
Test name
Test status
Simulation time 60350515396 ps
CPU time 512.4 seconds
Started Jul 12 04:44:51 PM PDT 24
Finished Jul 12 04:53:24 PM PDT 24
Peak memory 332580 kb
Host smart-987cd8d4-a5f0-4fd9-b4ed-7f80fffe612f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1992848710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.1992848710
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.970159085
Short name T581
Test name
Test status
Simulation time 16254867 ps
CPU time 0.8 seconds
Started Jul 12 04:44:46 PM PDT 24
Finished Jul 12 04:44:49 PM PDT 24
Peak memory 208188 kb
Host smart-15fd9fdf-4e19-4c41-98e8-240a47e7e1d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970159085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.970159085
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.4189369534
Short name T81
Test name
Test status
Simulation time 33927611 ps
CPU time 1.13 seconds
Started Jul 12 04:44:55 PM PDT 24
Finished Jul 12 04:44:59 PM PDT 24
Peak memory 208416 kb
Host smart-b117e71c-4311-4c5e-86ea-394bda26e9f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189369534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.4189369534
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2977494648
Short name T210
Test name
Test status
Simulation time 679642253 ps
CPU time 9.25 seconds
Started Jul 12 04:44:53 PM PDT 24
Finished Jul 12 04:45:05 PM PDT 24
Peak memory 217636 kb
Host smart-f42a950a-3343-44a8-85b1-954912a4ac90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977494648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2977494648
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2267048046
Short name T317
Test name
Test status
Simulation time 414018147 ps
CPU time 4.8 seconds
Started Jul 12 04:44:54 PM PDT 24
Finished Jul 12 04:45:01 PM PDT 24
Peak memory 216508 kb
Host smart-953edc02-5240-45d5-9a3a-1fa0272e0466
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267048046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2267048046
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3481485929
Short name T307
Test name
Test status
Simulation time 32927570 ps
CPU time 1.85 seconds
Started Jul 12 04:44:53 PM PDT 24
Finished Jul 12 04:44:57 PM PDT 24
Peak memory 217604 kb
Host smart-103b046d-f38c-4af8-97f1-502afadbf90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481485929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3481485929
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3639435998
Short name T284
Test name
Test status
Simulation time 207881358 ps
CPU time 9.48 seconds
Started Jul 12 04:44:50 PM PDT 24
Finished Jul 12 04:45:00 PM PDT 24
Peak memory 225636 kb
Host smart-7b53c8bb-fd71-4644-b3b9-7cbdb448f2e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639435998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3639435998
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3783203719
Short name T812
Test name
Test status
Simulation time 1882895038 ps
CPU time 9.51 seconds
Started Jul 12 04:44:53 PM PDT 24
Finished Jul 12 04:45:05 PM PDT 24
Peak memory 225444 kb
Host smart-f0a492b0-7b57-4881-9707-ef011f1e4923
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783203719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3783203719
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2083251566
Short name T712
Test name
Test status
Simulation time 1112454698 ps
CPU time 10.12 seconds
Started Jul 12 04:44:53 PM PDT 24
Finished Jul 12 04:45:05 PM PDT 24
Peak memory 225400 kb
Host smart-e812560d-66ef-463a-869c-b97405f67795
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083251566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2083251566
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2338970190
Short name T542
Test name
Test status
Simulation time 319377447 ps
CPU time 8.75 seconds
Started Jul 12 04:44:52 PM PDT 24
Finished Jul 12 04:45:02 PM PDT 24
Peak memory 224424 kb
Host smart-3573033f-e2d5-42c6-96c7-db2e46ce3f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338970190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2338970190
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.423750018
Short name T373
Test name
Test status
Simulation time 148980028 ps
CPU time 2.67 seconds
Started Jul 12 04:44:57 PM PDT 24
Finished Jul 12 04:45:02 PM PDT 24
Peak memory 217132 kb
Host smart-978c59bd-d1a6-42ed-85e5-3a50dec8fe58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423750018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.423750018
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2795677513
Short name T797
Test name
Test status
Simulation time 2184750088 ps
CPU time 18.12 seconds
Started Jul 12 04:44:52 PM PDT 24
Finished Jul 12 04:45:12 PM PDT 24
Peak memory 250508 kb
Host smart-5f43c72e-7b63-4630-9bd7-6f28390a682c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795677513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2795677513
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.79986525
Short name T245
Test name
Test status
Simulation time 545764577 ps
CPU time 4.22 seconds
Started Jul 12 04:44:51 PM PDT 24
Finished Jul 12 04:44:57 PM PDT 24
Peak memory 222352 kb
Host smart-c674ffc9-de70-4866-98c4-d7d3d01e1a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79986525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.79986525
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.853385299
Short name T558
Test name
Test status
Simulation time 9285750646 ps
CPU time 316.82 seconds
Started Jul 12 04:44:51 PM PDT 24
Finished Jul 12 04:50:09 PM PDT 24
Peak memory 250444 kb
Host smart-6e715ae2-8afe-40d3-aeb1-ae1adaa21757
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853385299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.853385299
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.314736047
Short name T559
Test name
Test status
Simulation time 70177644121 ps
CPU time 1380.12 seconds
Started Jul 12 04:44:53 PM PDT 24
Finished Jul 12 05:07:55 PM PDT 24
Peak memory 348968 kb
Host smart-15c269c6-4dd4-48f3-bdd6-4f345dedd185
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=314736047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.314736047
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1385593223
Short name T312
Test name
Test status
Simulation time 14691489 ps
CPU time 0.91 seconds
Started Jul 12 04:44:52 PM PDT 24
Finished Jul 12 04:44:55 PM PDT 24
Peak memory 208404 kb
Host smart-ae808c9f-d632-4d71-8e75-e3becea272bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385593223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1385593223
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.435640875
Short name T731
Test name
Test status
Simulation time 1398622811 ps
CPU time 15.85 seconds
Started Jul 12 04:44:52 PM PDT 24
Finished Jul 12 04:45:10 PM PDT 24
Peak memory 217724 kb
Host smart-408684d5-bea0-486a-88cf-a7ae33f422ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435640875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.435640875
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.580015338
Short name T782
Test name
Test status
Simulation time 154410044 ps
CPU time 4.67 seconds
Started Jul 12 04:44:49 PM PDT 24
Finished Jul 12 04:44:55 PM PDT 24
Peak memory 217008 kb
Host smart-7afbd13a-4490-4c10-a4fd-19c3e636b86b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580015338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.580015338
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.4234023853
Short name T420
Test name
Test status
Simulation time 45382539 ps
CPU time 2.68 seconds
Started Jul 12 04:44:52 PM PDT 24
Finished Jul 12 04:44:56 PM PDT 24
Peak memory 217728 kb
Host smart-bec93b62-ff1e-46ff-9a0b-6905ea75e65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234023853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.4234023853
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1634176520
Short name T602
Test name
Test status
Simulation time 560692875 ps
CPU time 11.81 seconds
Started Jul 12 04:44:57 PM PDT 24
Finished Jul 12 04:45:11 PM PDT 24
Peak memory 217696 kb
Host smart-f749826c-a58d-48f4-aa96-5209227fdec9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634176520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1634176520
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3549040878
Short name T520
Test name
Test status
Simulation time 1083548218 ps
CPU time 12.15 seconds
Started Jul 12 04:44:55 PM PDT 24
Finished Jul 12 04:45:10 PM PDT 24
Peak memory 225392 kb
Host smart-cebf2d91-4e22-40d9-9ba2-e0a366a96d2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549040878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3549040878
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3176150897
Short name T50
Test name
Test status
Simulation time 849502954 ps
CPU time 6.88 seconds
Started Jul 12 04:44:53 PM PDT 24
Finished Jul 12 04:45:02 PM PDT 24
Peak memory 224736 kb
Host smart-55a2b3d8-2c2b-4ec2-8564-ae447d2e40fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176150897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3176150897
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.4170679583
Short name T330
Test name
Test status
Simulation time 112813959 ps
CPU time 3.13 seconds
Started Jul 12 04:44:57 PM PDT 24
Finished Jul 12 04:45:03 PM PDT 24
Peak memory 217064 kb
Host smart-b21005a1-8d2a-4f5a-851f-596865589f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170679583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.4170679583
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1936913241
Short name T207
Test name
Test status
Simulation time 311440226 ps
CPU time 32.85 seconds
Started Jul 12 04:44:54 PM PDT 24
Finished Jul 12 04:45:29 PM PDT 24
Peak memory 250424 kb
Host smart-e7aa5e97-ba68-41c2-836f-4088e6525ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936913241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1936913241
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2138969134
Short name T807
Test name
Test status
Simulation time 115555520 ps
CPU time 9.95 seconds
Started Jul 12 04:44:54 PM PDT 24
Finished Jul 12 04:45:06 PM PDT 24
Peak memory 250280 kb
Host smart-2f9fd899-aa2b-4ae3-ada3-c1a3f5bba004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138969134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2138969134
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1573480274
Short name T5
Test name
Test status
Simulation time 58709158657 ps
CPU time 245.92 seconds
Started Jul 12 04:44:52 PM PDT 24
Finished Jul 12 04:49:00 PM PDT 24
Peak memory 250612 kb
Host smart-5577c7f0-cb5c-48e5-873a-f982bbd97ae9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573480274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1573480274
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.86853789
Short name T101
Test name
Test status
Simulation time 91228749962 ps
CPU time 461.94 seconds
Started Jul 12 04:45:02 PM PDT 24
Finished Jul 12 04:52:47 PM PDT 24
Peak memory 292188 kb
Host smart-b0791760-f44b-4637-b2b7-1d79333486a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=86853789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.86853789
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2298290440
Short name T391
Test name
Test status
Simulation time 54122454 ps
CPU time 1.05 seconds
Started Jul 12 04:45:02 PM PDT 24
Finished Jul 12 04:45:07 PM PDT 24
Peak memory 217144 kb
Host smart-6768306f-ee60-4076-a049-d88c29277233
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298290440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.2298290440
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.947184679
Short name T562
Test name
Test status
Simulation time 20006535 ps
CPU time 1.18 seconds
Started Jul 12 04:44:58 PM PDT 24
Finished Jul 12 04:45:02 PM PDT 24
Peak memory 208528 kb
Host smart-864099d5-4383-4bb7-9337-c9f8c78d5a81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947184679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.947184679
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3293716627
Short name T231
Test name
Test status
Simulation time 1214551829 ps
CPU time 19.85 seconds
Started Jul 12 04:44:53 PM PDT 24
Finished Jul 12 04:45:15 PM PDT 24
Peak memory 217624 kb
Host smart-7ba8c718-80ea-4279-b1d1-a0ea9efccedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293716627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3293716627
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1387140727
Short name T166
Test name
Test status
Simulation time 1898890256 ps
CPU time 12.86 seconds
Started Jul 12 04:44:53 PM PDT 24
Finished Jul 12 04:45:08 PM PDT 24
Peak memory 217036 kb
Host smart-576156ca-21b5-427c-958f-7defc1a78d81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387140727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1387140727
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1588274141
Short name T259
Test name
Test status
Simulation time 24665100 ps
CPU time 1.71 seconds
Started Jul 12 04:44:57 PM PDT 24
Finished Jul 12 04:45:01 PM PDT 24
Peak memory 217644 kb
Host smart-c7d1ce83-78e5-48f6-9214-2a8252766821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588274141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1588274141
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1999207094
Short name T444
Test name
Test status
Simulation time 1523310350 ps
CPU time 14.7 seconds
Started Jul 12 04:44:59 PM PDT 24
Finished Jul 12 04:45:16 PM PDT 24
Peak memory 218336 kb
Host smart-45c99c52-d8c0-4bf9-9725-f525d1a97a3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999207094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1999207094
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1905018900
Short name T630
Test name
Test status
Simulation time 842327501 ps
CPU time 10.45 seconds
Started Jul 12 04:44:57 PM PDT 24
Finished Jul 12 04:45:10 PM PDT 24
Peak memory 225000 kb
Host smart-20fb0d7c-48c8-428d-beb5-0c99d19fd000
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905018900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1905018900
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1487849616
Short name T550
Test name
Test status
Simulation time 787322867 ps
CPU time 9.78 seconds
Started Jul 12 04:45:01 PM PDT 24
Finished Jul 12 04:45:14 PM PDT 24
Peak memory 217588 kb
Host smart-a2a4acff-dfcb-460c-bc97-20987ff54648
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487849616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1487849616
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.4216490264
Short name T813
Test name
Test status
Simulation time 1326662670 ps
CPU time 12.47 seconds
Started Jul 12 04:44:51 PM PDT 24
Finished Jul 12 04:45:05 PM PDT 24
Peak memory 217772 kb
Host smart-036f697e-5e82-4361-bdc0-f8ca0393fedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216490264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.4216490264
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.4033065251
Short name T773
Test name
Test status
Simulation time 51803358 ps
CPU time 2.17 seconds
Started Jul 12 04:44:53 PM PDT 24
Finished Jul 12 04:44:57 PM PDT 24
Peak memory 213824 kb
Host smart-e78881d4-5e22-4aa0-b882-43ce2f5c1759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033065251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.4033065251
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.357402233
Short name T576
Test name
Test status
Simulation time 508157722 ps
CPU time 19.59 seconds
Started Jul 12 04:44:57 PM PDT 24
Finished Jul 12 04:45:19 PM PDT 24
Peak memory 250440 kb
Host smart-fce2aa42-92b7-4bf6-90c0-a35931f9fd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357402233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.357402233
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1954389485
Short name T267
Test name
Test status
Simulation time 141078609 ps
CPU time 3.09 seconds
Started Jul 12 04:44:53 PM PDT 24
Finished Jul 12 04:44:59 PM PDT 24
Peak memory 225864 kb
Host smart-1ba062a8-fbaa-4a5d-8ee6-14fd2b2861cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954389485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1954389485
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3792998119
Short name T39
Test name
Test status
Simulation time 43236002970 ps
CPU time 217.23 seconds
Started Jul 12 04:44:56 PM PDT 24
Finished Jul 12 04:48:35 PM PDT 24
Peak memory 283184 kb
Host smart-7c17b88b-df5a-4ed2-897e-d93844c09dfc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792998119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3792998119
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3045528189
Short name T152
Test name
Test status
Simulation time 16449918672 ps
CPU time 708.52 seconds
Started Jul 12 04:45:02 PM PDT 24
Finished Jul 12 04:56:54 PM PDT 24
Peak memory 408148 kb
Host smart-16c943ec-ebe3-4ba6-b0bf-fc9448725100
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3045528189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.3045528189
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2180456626
Short name T301
Test name
Test status
Simulation time 15338310 ps
CPU time 1 seconds
Started Jul 12 04:44:51 PM PDT 24
Finished Jul 12 04:44:54 PM PDT 24
Peak memory 208552 kb
Host smart-47587cb9-6338-4838-9c29-b5fe9ec21cf3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180456626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2180456626
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.386887587
Short name T730
Test name
Test status
Simulation time 16588610 ps
CPU time 0.9 seconds
Started Jul 12 04:44:58 PM PDT 24
Finished Jul 12 04:45:02 PM PDT 24
Peak memory 208368 kb
Host smart-8569f008-360e-4b2e-a4b5-c6a9113f68c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386887587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.386887587
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3325639848
Short name T564
Test name
Test status
Simulation time 904923196 ps
CPU time 9.56 seconds
Started Jul 12 04:44:57 PM PDT 24
Finished Jul 12 04:45:09 PM PDT 24
Peak memory 225492 kb
Host smart-0d3cf823-1287-4ac4-aaf8-48d4d2429fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325639848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3325639848
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.4090814791
Short name T24
Test name
Test status
Simulation time 1826553332 ps
CPU time 11.77 seconds
Started Jul 12 04:44:56 PM PDT 24
Finished Jul 12 04:45:09 PM PDT 24
Peak memory 216948 kb
Host smart-1ddbd0fe-e62e-4e29-9ad7-3c4031dbfbdb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090814791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.4090814791
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.170087503
Short name T477
Test name
Test status
Simulation time 194022632 ps
CPU time 2.41 seconds
Started Jul 12 04:44:58 PM PDT 24
Finished Jul 12 04:45:03 PM PDT 24
Peak memory 217700 kb
Host smart-2ef4c2ec-4e6e-423b-8705-6b1fb81d7a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170087503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.170087503
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.441467664
Short name T9
Test name
Test status
Simulation time 4046859397 ps
CPU time 23.63 seconds
Started Jul 12 04:45:12 PM PDT 24
Finished Jul 12 04:45:37 PM PDT 24
Peak memory 225372 kb
Host smart-2f5c1d30-cdc8-4dbb-b18a-df6c084a426b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441467664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.441467664
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3817736698
Short name T573
Test name
Test status
Simulation time 190559576 ps
CPU time 7.99 seconds
Started Jul 12 04:44:59 PM PDT 24
Finished Jul 12 04:45:10 PM PDT 24
Peak memory 217620 kb
Host smart-d155a13f-9e93-4012-ad9c-d118e0acd7a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817736698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3817736698
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1354138761
Short name T479
Test name
Test status
Simulation time 2518774874 ps
CPU time 10.82 seconds
Started Jul 12 04:45:00 PM PDT 24
Finished Jul 12 04:45:13 PM PDT 24
Peak memory 225172 kb
Host smart-d75868b8-772e-4c01-9881-e011ca081a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354138761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1354138761
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1478268971
Short name T843
Test name
Test status
Simulation time 108443962 ps
CPU time 3.75 seconds
Started Jul 12 04:44:57 PM PDT 24
Finished Jul 12 04:45:03 PM PDT 24
Peak memory 217060 kb
Host smart-a5dd5bf8-5c9c-431d-adf1-2601367a4e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478268971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1478268971
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3675052612
Short name T781
Test name
Test status
Simulation time 869369326 ps
CPU time 19.29 seconds
Started Jul 12 04:44:58 PM PDT 24
Finished Jul 12 04:45:20 PM PDT 24
Peak memory 250460 kb
Host smart-94fe45f1-1d19-4d79-b0b9-9ca80aeae215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675052612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3675052612
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2975001182
Short name T799
Test name
Test status
Simulation time 297627754 ps
CPU time 6.33 seconds
Started Jul 12 04:45:00 PM PDT 24
Finished Jul 12 04:45:08 PM PDT 24
Peak memory 246516 kb
Host smart-cba58cb6-9ce4-4d08-bb67-1648c426eb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975001182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2975001182
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2519502015
Short name T439
Test name
Test status
Simulation time 1817004995 ps
CPU time 33.97 seconds
Started Jul 12 04:44:57 PM PDT 24
Finished Jul 12 04:45:34 PM PDT 24
Peak memory 250248 kb
Host smart-6b49b9bf-4f0e-4d44-85ae-98d2b5fc1ddc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519502015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2519502015
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.346635855
Short name T308
Test name
Test status
Simulation time 14450558 ps
CPU time 0.94 seconds
Started Jul 12 04:45:00 PM PDT 24
Finished Jul 12 04:45:04 PM PDT 24
Peak memory 208336 kb
Host smart-29ff2e6e-03ec-41b7-b8b5-0096b5a3784e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346635855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.346635855
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2211451630
Short name T517
Test name
Test status
Simulation time 15607844 ps
CPU time 0.97 seconds
Started Jul 12 04:44:57 PM PDT 24
Finished Jul 12 04:45:01 PM PDT 24
Peak memory 208436 kb
Host smart-cc063aae-71ad-4bad-bd46-a9a8acbc7fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211451630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2211451630
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.48838052
Short name T593
Test name
Test status
Simulation time 1750524386 ps
CPU time 9.81 seconds
Started Jul 12 04:44:58 PM PDT 24
Finished Jul 12 04:45:10 PM PDT 24
Peak memory 217700 kb
Host smart-14deec7c-458a-4035-ab89-0f2698386c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48838052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.48838052
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3729281302
Short name T685
Test name
Test status
Simulation time 482902377 ps
CPU time 5.1 seconds
Started Jul 12 04:45:01 PM PDT 24
Finished Jul 12 04:45:09 PM PDT 24
Peak memory 216668 kb
Host smart-5cd42993-284a-49be-8bf5-e00bbdfdede7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729281302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.3729281302
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2635862196
Short name T225
Test name
Test status
Simulation time 155310164 ps
CPU time 1.83 seconds
Started Jul 12 04:44:56 PM PDT 24
Finished Jul 12 04:44:59 PM PDT 24
Peak memory 217928 kb
Host smart-e0bd0027-a0ac-42e1-85b1-49531534f8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635862196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2635862196
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.470879190
Short name T429
Test name
Test status
Simulation time 1148341254 ps
CPU time 11.19 seconds
Started Jul 12 04:44:58 PM PDT 24
Finished Jul 12 04:45:12 PM PDT 24
Peak memory 225412 kb
Host smart-19f5dfe7-2407-43bd-93b0-2a218b7963bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470879190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.470879190
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1976043503
Short name T407
Test name
Test status
Simulation time 325822071 ps
CPU time 9.2 seconds
Started Jul 12 04:44:59 PM PDT 24
Finished Jul 12 04:45:11 PM PDT 24
Peak memory 217660 kb
Host smart-cbefd8a5-7d78-4297-9d92-6a00daefbf36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976043503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1976043503
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1491159474
Short name T748
Test name
Test status
Simulation time 263149524 ps
CPU time 10.59 seconds
Started Jul 12 04:45:03 PM PDT 24
Finished Jul 12 04:45:18 PM PDT 24
Peak memory 225484 kb
Host smart-559051e1-cb5d-404e-9464-a756483a87ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491159474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1491159474
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1158509474
Short name T779
Test name
Test status
Simulation time 25583516 ps
CPU time 1.43 seconds
Started Jul 12 04:45:12 PM PDT 24
Finished Jul 12 04:45:15 PM PDT 24
Peak memory 213180 kb
Host smart-40559d9b-c19a-48b0-88d0-48476da5b0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158509474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1158509474
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3042469515
Short name T273
Test name
Test status
Simulation time 425655664 ps
CPU time 31.7 seconds
Started Jul 12 04:45:00 PM PDT 24
Finished Jul 12 04:45:34 PM PDT 24
Peak memory 250536 kb
Host smart-68162102-322f-4293-9c34-018f9b799ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042469515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3042469515
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2481826217
Short name T303
Test name
Test status
Simulation time 178789570 ps
CPU time 6.32 seconds
Started Jul 12 04:45:17 PM PDT 24
Finished Jul 12 04:45:24 PM PDT 24
Peak memory 246332 kb
Host smart-3ad537be-70a7-4f59-847d-ba9e0ae8b177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481826217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2481826217
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1275718577
Short name T527
Test name
Test status
Simulation time 17298801233 ps
CPU time 151.69 seconds
Started Jul 12 04:44:57 PM PDT 24
Finished Jul 12 04:47:32 PM PDT 24
Peak memory 283228 kb
Host smart-29f478fc-0654-4530-aa7e-b61311b3d212
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275718577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1275718577
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.673339425
Short name T531
Test name
Test status
Simulation time 45510659 ps
CPU time 0.89 seconds
Started Jul 12 04:44:56 PM PDT 24
Finished Jul 12 04:44:59 PM PDT 24
Peak memory 208380 kb
Host smart-aa87001b-a603-48a8-8900-747d78e8b4e6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673339425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct
rl_volatile_unlock_smoke.673339425
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2737266169
Short name T511
Test name
Test status
Simulation time 20685618 ps
CPU time 0.93 seconds
Started Jul 12 04:44:57 PM PDT 24
Finished Jul 12 04:45:01 PM PDT 24
Peak memory 208388 kb
Host smart-ce748b95-a680-43c4-a2cb-85d7788f49c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737266169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2737266169
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1212561043
Short name T543
Test name
Test status
Simulation time 2870326028 ps
CPU time 15.16 seconds
Started Jul 12 04:44:58 PM PDT 24
Finished Jul 12 04:45:16 PM PDT 24
Peak memory 217748 kb
Host smart-07858d5a-a199-4770-a448-ca2a57b2b626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212561043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1212561043
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2664292503
Short name T21
Test name
Test status
Simulation time 723568935 ps
CPU time 2.75 seconds
Started Jul 12 04:45:00 PM PDT 24
Finished Jul 12 04:45:07 PM PDT 24
Peak memory 217020 kb
Host smart-9a508a75-7fc5-432c-99cd-670e0229526c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664292503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2664292503
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.4211706632
Short name T506
Test name
Test status
Simulation time 232205538 ps
CPU time 2.16 seconds
Started Jul 12 04:45:12 PM PDT 24
Finished Jul 12 04:45:16 PM PDT 24
Peak memory 217592 kb
Host smart-8e27fe2b-507a-4369-b98e-7736dafe5ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211706632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.4211706632
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.412289277
Short name T565
Test name
Test status
Simulation time 986256758 ps
CPU time 10.52 seconds
Started Jul 12 04:45:01 PM PDT 24
Finished Jul 12 04:45:15 PM PDT 24
Peak memory 225392 kb
Host smart-d01ad557-af1d-4a60-9650-1cbb7a282e7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412289277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.412289277
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1046707479
Short name T481
Test name
Test status
Simulation time 1831567705 ps
CPU time 9.94 seconds
Started Jul 12 04:44:58 PM PDT 24
Finished Jul 12 04:45:11 PM PDT 24
Peak memory 225444 kb
Host smart-34583dce-da7a-4ab7-8c15-cd37a70fe12d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046707479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1046707479
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.4132632278
Short name T619
Test name
Test status
Simulation time 221647003 ps
CPU time 10.18 seconds
Started Jul 12 04:45:04 PM PDT 24
Finished Jul 12 04:45:18 PM PDT 24
Peak memory 217752 kb
Host smart-9766aa7d-7feb-4f44-a5ba-d9dd3a4328f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132632278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.4132632278
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.768633435
Short name T299
Test name
Test status
Simulation time 213058028 ps
CPU time 2.82 seconds
Started Jul 12 04:44:56 PM PDT 24
Finished Jul 12 04:45:02 PM PDT 24
Peak memory 217116 kb
Host smart-d00e7f07-cfc8-47b6-8725-2f76fc23a652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768633435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.768633435
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1930573884
Short name T387
Test name
Test status
Simulation time 311179560 ps
CPU time 30.86 seconds
Started Jul 12 04:44:59 PM PDT 24
Finished Jul 12 04:45:33 PM PDT 24
Peak memory 250380 kb
Host smart-002e1f32-b326-419d-9226-d89365c00388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930573884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1930573884
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1368491837
Short name T219
Test name
Test status
Simulation time 214229017 ps
CPU time 3.27 seconds
Started Jul 12 04:45:03 PM PDT 24
Finished Jul 12 04:45:10 PM PDT 24
Peak memory 223500 kb
Host smart-c7827cf1-6d74-47e3-ab42-ce641a633f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368491837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1368491837
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3207486712
Short name T275
Test name
Test status
Simulation time 65398916545 ps
CPU time 279.77 seconds
Started Jul 12 04:45:01 PM PDT 24
Finished Jul 12 04:49:44 PM PDT 24
Peak memory 250492 kb
Host smart-58db720f-4d99-4026-a781-3bd90314a801
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207486712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3207486712
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.333166644
Short name T37
Test name
Test status
Simulation time 28553225 ps
CPU time 0.78 seconds
Started Jul 12 04:45:01 PM PDT 24
Finished Jul 12 04:45:06 PM PDT 24
Peak memory 208136 kb
Host smart-ddadd579-339e-44c5-ae1f-32621f5defa6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333166644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.333166644
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2442556625
Short name T579
Test name
Test status
Simulation time 93212076 ps
CPU time 0.84 seconds
Started Jul 12 04:42:59 PM PDT 24
Finished Jul 12 04:43:02 PM PDT 24
Peak memory 208244 kb
Host smart-4c6581de-1d28-419f-95e5-8429b870ef07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442556625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2442556625
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.4035057342
Short name T637
Test name
Test status
Simulation time 923393455 ps
CPU time 9.05 seconds
Started Jul 12 04:43:00 PM PDT 24
Finished Jul 12 04:43:12 PM PDT 24
Peak memory 225436 kb
Host smart-c259a2b7-af45-4c00-ac48-906f18095c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035057342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.4035057342
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2349135505
Short name T25
Test name
Test status
Simulation time 475443339 ps
CPU time 12.55 seconds
Started Jul 12 04:43:02 PM PDT 24
Finished Jul 12 04:43:18 PM PDT 24
Peak memory 217104 kb
Host smart-b0b807cf-7eae-4989-9e62-a7a186f183cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349135505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2349135505
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2475918493
Short name T809
Test name
Test status
Simulation time 4042149579 ps
CPU time 32.51 seconds
Started Jul 12 04:43:01 PM PDT 24
Finished Jul 12 04:43:36 PM PDT 24
Peak memory 217792 kb
Host smart-9ee81ae5-20b5-4517-8b8a-064ad55d5f3b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475918493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2475918493
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2278510178
Short name T155
Test name
Test status
Simulation time 9107945819 ps
CPU time 5.49 seconds
Started Jul 12 04:43:02 PM PDT 24
Finished Jul 12 04:43:11 PM PDT 24
Peak memory 217268 kb
Host smart-3481b628-5138-409d-b8cf-bb25d47d30b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278510178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
278510178
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1138725501
Short name T684
Test name
Test status
Simulation time 186852164 ps
CPU time 3.75 seconds
Started Jul 12 04:43:01 PM PDT 24
Finished Jul 12 04:43:08 PM PDT 24
Peak memory 221140 kb
Host smart-1719b840-8f7a-4d70-b372-8b05eb389928
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138725501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1138725501
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.272652179
Short name T154
Test name
Test status
Simulation time 1061907286 ps
CPU time 17.8 seconds
Started Jul 12 04:43:01 PM PDT 24
Finished Jul 12 04:43:22 PM PDT 24
Peak memory 217040 kb
Host smart-e6f6bcad-7a81-4693-83fa-52e4b8a5cd52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272652179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.272652179
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1047313827
Short name T569
Test name
Test status
Simulation time 177514832 ps
CPU time 2.91 seconds
Started Jul 12 04:43:02 PM PDT 24
Finished Jul 12 04:43:09 PM PDT 24
Peak memory 217028 kb
Host smart-9e10c298-4f49-4c7b-8d32-e73a9258376d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047313827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1047313827
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3382207869
Short name T214
Test name
Test status
Simulation time 7214771684 ps
CPU time 115.83 seconds
Started Jul 12 04:43:04 PM PDT 24
Finished Jul 12 04:45:03 PM PDT 24
Peak memory 283200 kb
Host smart-9f7a5e65-8327-40ec-af0c-9c7fd92b3779
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382207869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3382207869
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2592501367
Short name T18
Test name
Test status
Simulation time 1624750433 ps
CPU time 17.42 seconds
Started Jul 12 04:43:00 PM PDT 24
Finished Jul 12 04:43:20 PM PDT 24
Peak memory 250364 kb
Host smart-afb65bca-43dd-4fd5-971f-80fc08f2e59e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592501367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2592501367
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3887880380
Short name T746
Test name
Test status
Simulation time 96590719 ps
CPU time 4.63 seconds
Started Jul 12 04:43:03 PM PDT 24
Finished Jul 12 04:43:11 PM PDT 24
Peak memory 217592 kb
Host smart-6fe16159-77e0-4468-8ea0-1474b54edc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887880380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3887880380
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.4077069576
Short name T61
Test name
Test status
Simulation time 1119682383 ps
CPU time 12.43 seconds
Started Jul 12 04:43:04 PM PDT 24
Finished Jul 12 04:43:20 PM PDT 24
Peak memory 214152 kb
Host smart-855557aa-3761-44fb-9b34-02cf903b4934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077069576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.4077069576
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2020759838
Short name T205
Test name
Test status
Simulation time 399237454 ps
CPU time 13.46 seconds
Started Jul 12 04:43:04 PM PDT 24
Finished Jul 12 04:43:21 PM PDT 24
Peak memory 218432 kb
Host smart-45538a52-2ed1-4ecc-a275-f1f9b7b1085f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020759838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2020759838
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1569775261
Short name T248
Test name
Test status
Simulation time 1103169059 ps
CPU time 27.61 seconds
Started Jul 12 04:43:02 PM PDT 24
Finished Jul 12 04:43:33 PM PDT 24
Peak memory 225416 kb
Host smart-54e79695-4052-4099-bf66-fb6b022a8c2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569775261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.1569775261
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2568520124
Short name T624
Test name
Test status
Simulation time 3992383671 ps
CPU time 10.17 seconds
Started Jul 12 04:43:04 PM PDT 24
Finished Jul 12 04:43:18 PM PDT 24
Peak memory 217652 kb
Host smart-a5b7a8bc-4fab-4406-a725-736bde3d84c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568520124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
568520124
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3201606206
Short name T201
Test name
Test status
Simulation time 4246874752 ps
CPU time 12.71 seconds
Started Jul 12 04:43:00 PM PDT 24
Finished Jul 12 04:43:15 PM PDT 24
Peak memory 225240 kb
Host smart-bc284be0-c2a0-4c01-8617-a366c73b2f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201606206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3201606206
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2440575190
Short name T526
Test name
Test status
Simulation time 635706164 ps
CPU time 4.99 seconds
Started Jul 12 04:43:02 PM PDT 24
Finished Jul 12 04:43:11 PM PDT 24
Peak memory 217104 kb
Host smart-77ed1822-68e4-49fc-b5a4-c7ebcc045ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440575190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2440575190
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.63184004
Short name T546
Test name
Test status
Simulation time 237780712 ps
CPU time 27.46 seconds
Started Jul 12 04:42:59 PM PDT 24
Finished Jul 12 04:43:29 PM PDT 24
Peak memory 250464 kb
Host smart-98d772aa-b74d-4e86-900b-ae4d5e4cd269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63184004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.63184004
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1509915181
Short name T433
Test name
Test status
Simulation time 365450320 ps
CPU time 7.26 seconds
Started Jul 12 04:43:00 PM PDT 24
Finished Jul 12 04:43:10 PM PDT 24
Peak memory 250456 kb
Host smart-5196b253-a8fc-42d4-91e6-b983705013fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509915181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1509915181
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.717332916
Short name T32
Test name
Test status
Simulation time 5187615164 ps
CPU time 82.51 seconds
Started Jul 12 04:43:00 PM PDT 24
Finished Jul 12 04:44:26 PM PDT 24
Peak memory 277796 kb
Host smart-f0a8144b-dcad-47a2-8b9b-cf2ed9de1439
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717332916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.717332916
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1381532140
Short name T35
Test name
Test status
Simulation time 21205736 ps
CPU time 1.03 seconds
Started Jul 12 04:43:01 PM PDT 24
Finished Jul 12 04:43:05 PM PDT 24
Peak memory 211308 kb
Host smart-da302441-42a0-4c2f-a665-1e2be2e397b8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381532140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1381532140
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1946376234
Short name T242
Test name
Test status
Simulation time 82580494 ps
CPU time 1 seconds
Started Jul 12 04:43:10 PM PDT 24
Finished Jul 12 04:43:14 PM PDT 24
Peak memory 208484 kb
Host smart-758110f7-02d4-4f5a-a3ca-96ec205a065c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946376234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1946376234
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2823046638
Short name T412
Test name
Test status
Simulation time 36193200 ps
CPU time 0.9 seconds
Started Jul 12 04:43:01 PM PDT 24
Finished Jul 12 04:43:06 PM PDT 24
Peak memory 208376 kb
Host smart-01b9475f-6701-424d-ad73-5cf851007f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823046638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2823046638
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3533493958
Short name T768
Test name
Test status
Simulation time 211573089 ps
CPU time 10.89 seconds
Started Jul 12 04:43:02 PM PDT 24
Finished Jul 12 04:43:17 PM PDT 24
Peak memory 217844 kb
Host smart-04002c35-e4e0-4807-b8c0-8dc2bf0cb75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533493958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3533493958
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2445552857
Short name T507
Test name
Test status
Simulation time 362310322 ps
CPU time 1.56 seconds
Started Jul 12 04:43:05 PM PDT 24
Finished Jul 12 04:43:10 PM PDT 24
Peak memory 217052 kb
Host smart-09121258-b76f-474e-84dc-d0fae1dfa3c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445552857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2445552857
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1519976962
Short name T628
Test name
Test status
Simulation time 3534633402 ps
CPU time 50.99 seconds
Started Jul 12 04:43:02 PM PDT 24
Finished Jul 12 04:43:57 PM PDT 24
Peak memory 218744 kb
Host smart-9d90a708-f555-434d-a75a-d6427ce30846
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519976962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1519976962
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.410908680
Short name T482
Test name
Test status
Simulation time 514639746 ps
CPU time 5.06 seconds
Started Jul 12 04:43:06 PM PDT 24
Finished Jul 12 04:43:14 PM PDT 24
Peak memory 217096 kb
Host smart-96f18207-2c3a-4efc-8593-5e1e968db1d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410908680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.410908680
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2277567199
Short name T641
Test name
Test status
Simulation time 713109795 ps
CPU time 7.91 seconds
Started Jul 12 04:43:01 PM PDT 24
Finished Jul 12 04:43:12 PM PDT 24
Peak memory 217644 kb
Host smart-70a97f31-a606-4758-be62-e332cb4c5f4a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277567199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2277567199
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.4118247528
Short name T311
Test name
Test status
Simulation time 9669501851 ps
CPU time 12.74 seconds
Started Jul 12 04:43:04 PM PDT 24
Finished Jul 12 04:43:20 PM PDT 24
Peak memory 217116 kb
Host smart-5f5a9a98-dbdf-4fd0-984c-f9254ee34855
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118247528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.4118247528
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1315270181
Short name T71
Test name
Test status
Simulation time 258237029 ps
CPU time 8.39 seconds
Started Jul 12 04:43:02 PM PDT 24
Finished Jul 12 04:43:14 PM PDT 24
Peak memory 217164 kb
Host smart-0348cee0-0038-4dab-b775-7c84466b1b1f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315270181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1315270181
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.307543638
Short name T388
Test name
Test status
Simulation time 4486302327 ps
CPU time 44.24 seconds
Started Jul 12 04:43:04 PM PDT 24
Finished Jul 12 04:43:52 PM PDT 24
Peak memory 266776 kb
Host smart-f3bcd672-e861-4e67-ab60-49dc57b78182
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307543638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.307543638
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1633671691
Short name T808
Test name
Test status
Simulation time 1908231968 ps
CPU time 11.32 seconds
Started Jul 12 04:43:05 PM PDT 24
Finished Jul 12 04:43:20 PM PDT 24
Peak memory 249820 kb
Host smart-4ed72164-00e4-4f53-90da-07c7be872ab1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633671691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1633671691
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1878220541
Short name T469
Test name
Test status
Simulation time 35012603 ps
CPU time 2 seconds
Started Jul 12 04:43:06 PM PDT 24
Finished Jul 12 04:43:11 PM PDT 24
Peak memory 217628 kb
Host smart-b820249a-a069-4a5e-907a-0c528f9dbc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878220541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1878220541
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2090720140
Short name T160
Test name
Test status
Simulation time 833038159 ps
CPU time 15.25 seconds
Started Jul 12 04:43:02 PM PDT 24
Finished Jul 12 04:43:21 PM PDT 24
Peak memory 217064 kb
Host smart-6a25d848-220f-4cf1-9f22-572eddd1c1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090720140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2090720140
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1155517694
Short name T414
Test name
Test status
Simulation time 781989459 ps
CPU time 17.33 seconds
Started Jul 12 04:43:08 PM PDT 24
Finished Jul 12 04:43:28 PM PDT 24
Peak memory 225432 kb
Host smart-e96c9910-bd53-421d-82c8-d682fc9e3b29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155517694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1155517694
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1946187555
Short name T276
Test name
Test status
Simulation time 902539677 ps
CPU time 17.83 seconds
Started Jul 12 04:43:08 PM PDT 24
Finished Jul 12 04:43:29 PM PDT 24
Peak memory 225408 kb
Host smart-4f011124-95e8-479b-91c1-345cd6b3cf0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946187555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1946187555
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3657726505
Short name T714
Test name
Test status
Simulation time 2757427056 ps
CPU time 6.79 seconds
Started Jul 12 04:43:07 PM PDT 24
Finished Jul 12 04:43:17 PM PDT 24
Peak memory 217736 kb
Host smart-42e7d752-9f41-4fbe-8dc9-22228bbe01e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657726505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
657726505
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.99423316
Short name T53
Test name
Test status
Simulation time 330819930 ps
CPU time 9.15 seconds
Started Jul 12 04:43:02 PM PDT 24
Finished Jul 12 04:43:15 PM PDT 24
Peak memory 217740 kb
Host smart-1496ea79-a751-4d81-82c7-ef4d0efe4b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99423316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.99423316
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.497591560
Short name T75
Test name
Test status
Simulation time 154502442 ps
CPU time 2.38 seconds
Started Jul 12 04:42:59 PM PDT 24
Finished Jul 12 04:43:04 PM PDT 24
Peak memory 217052 kb
Host smart-92139ab9-4bd2-4667-8cec-6782818ae3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497591560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.497591560
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.481630084
Short name T410
Test name
Test status
Simulation time 186764161 ps
CPU time 6.09 seconds
Started Jul 12 04:43:00 PM PDT 24
Finished Jul 12 04:43:08 PM PDT 24
Peak memory 245636 kb
Host smart-5233daf6-51b7-4c2d-8ea9-1f036095ef56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481630084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.481630084
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.3306246766
Short name T566
Test name
Test status
Simulation time 20187923939 ps
CPU time 105.65 seconds
Started Jul 12 04:43:08 PM PDT 24
Finished Jul 12 04:44:58 PM PDT 24
Peak memory 250516 kb
Host smart-a2ca2c31-72b8-49d3-ad54-56ced03f1300
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306246766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.3306246766
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.63895614
Short name T722
Test name
Test status
Simulation time 163468245158 ps
CPU time 245.52 seconds
Started Jul 12 04:43:11 PM PDT 24
Finished Jul 12 04:47:19 PM PDT 24
Peak memory 271912 kb
Host smart-ce43884a-71d6-4cba-b1d5-48a399a9e158
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=63895614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.63895614
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2123703401
Short name T672
Test name
Test status
Simulation time 14216363 ps
CPU time 1.12 seconds
Started Jul 12 04:43:01 PM PDT 24
Finished Jul 12 04:43:06 PM PDT 24
Peak memory 211284 kb
Host smart-9b63a8cc-0a48-4cdf-836f-d3c23172ac02
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123703401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2123703401
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2809492754
Short name T62
Test name
Test status
Simulation time 207093637 ps
CPU time 0.95 seconds
Started Jul 12 04:43:10 PM PDT 24
Finished Jul 12 04:43:14 PM PDT 24
Peak memory 208456 kb
Host smart-b6fee994-6863-4534-bb11-13df97aa5ba4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809492754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2809492754
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1966266588
Short name T759
Test name
Test status
Simulation time 436259725 ps
CPU time 8.98 seconds
Started Jul 12 04:43:07 PM PDT 24
Finished Jul 12 04:43:20 PM PDT 24
Peak memory 217792 kb
Host smart-26e98b3d-14da-4cdd-b059-b1d0d36f3009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966266588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1966266588
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3507331570
Short name T403
Test name
Test status
Simulation time 9586149368 ps
CPU time 8.6 seconds
Started Jul 12 04:43:09 PM PDT 24
Finished Jul 12 04:43:20 PM PDT 24
Peak memory 217208 kb
Host smart-cee8d068-b910-46fd-bf8d-9100ff9a7b8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507331570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3507331570
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2620300441
Short name T436
Test name
Test status
Simulation time 2184796676 ps
CPU time 65.47 seconds
Started Jul 12 04:43:08 PM PDT 24
Finished Jul 12 04:44:17 PM PDT 24
Peak memory 218312 kb
Host smart-83afd909-982a-42a5-a6a8-53a227bf9916
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620300441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2620300441
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.4214108503
Short name T844
Test name
Test status
Simulation time 829138077 ps
CPU time 3.37 seconds
Started Jul 12 04:43:10 PM PDT 24
Finished Jul 12 04:43:16 PM PDT 24
Peak memory 217028 kb
Host smart-03ce02d1-0c2d-4db8-9763-ff861f29dc0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214108503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.4
214108503
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2053300815
Short name T425
Test name
Test status
Simulation time 2609848066 ps
CPU time 18.53 seconds
Started Jul 12 04:43:10 PM PDT 24
Finished Jul 12 04:43:31 PM PDT 24
Peak memory 217620 kb
Host smart-c7b1cf9a-c502-4c64-83c3-ed91d32626ff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053300815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2053300815
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1725674910
Short name T234
Test name
Test status
Simulation time 4142266237 ps
CPU time 15.43 seconds
Started Jul 12 04:43:08 PM PDT 24
Finished Jul 12 04:43:27 PM PDT 24
Peak memory 217116 kb
Host smart-d2a44920-c004-42ea-ad74-ae7eed5da463
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725674910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1725674910
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1315244096
Short name T67
Test name
Test status
Simulation time 891626428 ps
CPU time 7.81 seconds
Started Jul 12 04:43:07 PM PDT 24
Finished Jul 12 04:43:18 PM PDT 24
Peak memory 217032 kb
Host smart-4859b410-5d5e-4420-8d26-2ba51b040772
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315244096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1315244096
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2975455027
Short name T729
Test name
Test status
Simulation time 8942200679 ps
CPU time 74.69 seconds
Started Jul 12 04:43:06 PM PDT 24
Finished Jul 12 04:44:25 PM PDT 24
Peak memory 279120 kb
Host smart-d8732497-e7d9-4918-8ef5-a54d15dd02d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975455027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2975455027
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1449001146
Short name T669
Test name
Test status
Simulation time 1920445797 ps
CPU time 30.48 seconds
Started Jul 12 04:43:07 PM PDT 24
Finished Jul 12 04:43:41 PM PDT 24
Peak memory 249672 kb
Host smart-2cc97a77-8976-48a1-87cb-b96c36c8db0a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449001146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.1449001146
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3429425751
Short name T655
Test name
Test status
Simulation time 34372416 ps
CPU time 1.55 seconds
Started Jul 12 04:43:10 PM PDT 24
Finished Jul 12 04:43:14 PM PDT 24
Peak memory 217732 kb
Host smart-e782f0d3-1463-40cf-af1b-64a085f0fa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429425751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3429425751
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.4238781854
Short name T386
Test name
Test status
Simulation time 846130577 ps
CPU time 6.78 seconds
Started Jul 12 04:43:07 PM PDT 24
Finished Jul 12 04:43:17 PM PDT 24
Peak memory 217060 kb
Host smart-4a73989f-dba2-46f0-9848-5f41ecb624b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238781854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.4238781854
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1157542166
Short name T548
Test name
Test status
Simulation time 336078848 ps
CPU time 14.49 seconds
Started Jul 12 04:43:08 PM PDT 24
Finished Jul 12 04:43:26 PM PDT 24
Peak memory 218360 kb
Host smart-0e1c58f6-ec9c-4813-9268-dd0f45f57645
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157542166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1157542166
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3660855112
Short name T216
Test name
Test status
Simulation time 1125957112 ps
CPU time 8.99 seconds
Started Jul 12 04:43:09 PM PDT 24
Finished Jul 12 04:43:21 PM PDT 24
Peak memory 225384 kb
Host smart-6fa4070e-d162-4451-a0bc-b16cc51c6832
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660855112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3660855112
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2981912181
Short name T475
Test name
Test status
Simulation time 266642868 ps
CPU time 7.13 seconds
Started Jul 12 04:43:08 PM PDT 24
Finished Jul 12 04:43:19 PM PDT 24
Peak memory 225400 kb
Host smart-e3c77652-90c2-46ab-a56e-f24bb4c9b6c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981912181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
981912181
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2847015131
Short name T347
Test name
Test status
Simulation time 331363839 ps
CPU time 11.66 seconds
Started Jul 12 04:43:06 PM PDT 24
Finished Jul 12 04:43:21 PM PDT 24
Peak memory 217752 kb
Host smart-b40153c6-62be-4ce8-b058-f882090590d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847015131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2847015131
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2069736604
Short name T609
Test name
Test status
Simulation time 73454877 ps
CPU time 1.63 seconds
Started Jul 12 04:43:10 PM PDT 24
Finished Jul 12 04:43:15 PM PDT 24
Peak memory 217036 kb
Host smart-577e03fe-d47f-4c87-88b1-f5b3940ada0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069736604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2069736604
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3317844699
Short name T806
Test name
Test status
Simulation time 147070934 ps
CPU time 17.38 seconds
Started Jul 12 04:43:07 PM PDT 24
Finished Jul 12 04:43:28 PM PDT 24
Peak memory 250408 kb
Host smart-3908ff3d-bdb7-4f03-bfa4-778e9b007278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317844699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3317844699
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2135773429
Short name T157
Test name
Test status
Simulation time 424271878 ps
CPU time 6.16 seconds
Started Jul 12 04:43:07 PM PDT 24
Finished Jul 12 04:43:17 PM PDT 24
Peak memory 247240 kb
Host smart-43517a68-5626-46f1-afdc-4a7fd48f7176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135773429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2135773429
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3808594988
Short name T280
Test name
Test status
Simulation time 17615340967 ps
CPU time 124.07 seconds
Started Jul 12 04:43:06 PM PDT 24
Finished Jul 12 04:45:14 PM PDT 24
Peak memory 282364 kb
Host smart-6e8c7409-0be5-4d94-8659-1b91e720bd84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808594988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3808594988
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.3769778577
Short name T145
Test name
Test status
Simulation time 43228065781 ps
CPU time 674.05 seconds
Started Jul 12 04:43:07 PM PDT 24
Finished Jul 12 04:54:24 PM PDT 24
Peak memory 296760 kb
Host smart-3a5813cc-77f4-4842-9b25-89b9319c7daa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3769778577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.3769778577
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1091081244
Short name T792
Test name
Test status
Simulation time 15982386 ps
CPU time 0.96 seconds
Started Jul 12 04:43:12 PM PDT 24
Finished Jul 12 04:43:15 PM PDT 24
Peak memory 212244 kb
Host smart-81c569f3-fa31-4f24-8001-96d088640a6e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091081244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1091081244
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2641373706
Short name T767
Test name
Test status
Simulation time 301916992 ps
CPU time 0.93 seconds
Started Jul 12 04:43:12 PM PDT 24
Finished Jul 12 04:43:15 PM PDT 24
Peak memory 208520 kb
Host smart-8cd4053d-ae78-44dc-89d3-637bb098ca4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641373706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2641373706
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.772822486
Short name T428
Test name
Test status
Simulation time 11994675 ps
CPU time 0.94 seconds
Started Jul 12 04:43:15 PM PDT 24
Finished Jul 12 04:43:19 PM PDT 24
Peak memory 208360 kb
Host smart-68805ab5-f339-4218-b6c1-3bf1fe03f439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772822486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.772822486
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.467074395
Short name T33
Test name
Test status
Simulation time 218655863 ps
CPU time 8.02 seconds
Started Jul 12 04:43:14 PM PDT 24
Finished Jul 12 04:43:25 PM PDT 24
Peak memory 217640 kb
Host smart-45b577cd-5c23-4df8-ba9b-ff0c2ca55b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467074395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.467074395
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3973871555
Short name T702
Test name
Test status
Simulation time 2859655825 ps
CPU time 4.47 seconds
Started Jul 12 04:43:14 PM PDT 24
Finished Jul 12 04:43:21 PM PDT 24
Peak memory 216964 kb
Host smart-03aa51c2-6585-4c8a-9b5c-770767e1b041
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973871555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3973871555
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1126591148
Short name T664
Test name
Test status
Simulation time 2412978624 ps
CPU time 38.7 seconds
Started Jul 12 04:43:17 PM PDT 24
Finished Jul 12 04:43:58 PM PDT 24
Peak memory 217700 kb
Host smart-ceca0882-4293-416a-925b-2546c7775910
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126591148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1126591148
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1086627173
Short name T87
Test name
Test status
Simulation time 1284995486 ps
CPU time 12.06 seconds
Started Jul 12 04:43:17 PM PDT 24
Finished Jul 12 04:43:31 PM PDT 24
Peak memory 217100 kb
Host smart-175b6180-de60-4c5b-b5d6-dd0eab16ee25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086627173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
086627173
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.650952512
Short name T453
Test name
Test status
Simulation time 683802074 ps
CPU time 18.46 seconds
Started Jul 12 04:43:15 PM PDT 24
Finished Jul 12 04:43:37 PM PDT 24
Peak memory 217660 kb
Host smart-72f77b91-bac2-42d4-9d4b-7681923d36bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650952512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.650952512
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2589449582
Short name T693
Test name
Test status
Simulation time 1347419057 ps
CPU time 18.7 seconds
Started Jul 12 04:43:11 PM PDT 24
Finished Jul 12 04:43:33 PM PDT 24
Peak memory 217040 kb
Host smart-22d4022b-b06c-4076-9e5e-94ca5b4c482d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589449582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2589449582
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3888833184
Short name T713
Test name
Test status
Simulation time 103192423 ps
CPU time 2.07 seconds
Started Jul 12 04:43:12 PM PDT 24
Finished Jul 12 04:43:17 PM PDT 24
Peak memory 217052 kb
Host smart-686cbd63-f46d-495b-a858-9bd2b3c4b3ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888833184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3888833184
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.361753708
Short name T3
Test name
Test status
Simulation time 1643919261 ps
CPU time 73.71 seconds
Started Jul 12 04:43:12 PM PDT 24
Finished Jul 12 04:44:28 PM PDT 24
Peak memory 266616 kb
Host smart-055792ea-548c-4f58-b17c-36ebd9ab2c0d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361753708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.361753708
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.117643803
Short name T643
Test name
Test status
Simulation time 303363530 ps
CPU time 8.6 seconds
Started Jul 12 04:43:12 PM PDT 24
Finished Jul 12 04:43:23 PM PDT 24
Peak memory 242200 kb
Host smart-163724e5-0e24-4a2b-ab7c-0f2075c640e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117643803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.117643803
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.409576133
Short name T800
Test name
Test status
Simulation time 120224856 ps
CPU time 3.19 seconds
Started Jul 12 04:43:13 PM PDT 24
Finished Jul 12 04:43:19 PM PDT 24
Peak memory 217656 kb
Host smart-d5469605-fc49-4372-8da5-01ab574ffd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409576133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.409576133
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2808594091
Short name T694
Test name
Test status
Simulation time 803663616 ps
CPU time 8.9 seconds
Started Jul 12 04:43:13 PM PDT 24
Finished Jul 12 04:43:25 PM PDT 24
Peak memory 217136 kb
Host smart-9de03b3a-26e0-47ba-aacd-741cf77571c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808594091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2808594091
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3878701212
Short name T443
Test name
Test status
Simulation time 211836776 ps
CPU time 10.06 seconds
Started Jul 12 04:43:12 PM PDT 24
Finished Jul 12 04:43:25 PM PDT 24
Peak memory 217928 kb
Host smart-cfc30828-dd83-4d25-9343-b6002b2dc0eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878701212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3878701212
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3669238076
Short name T758
Test name
Test status
Simulation time 8117293023 ps
CPU time 12.62 seconds
Started Jul 12 04:43:16 PM PDT 24
Finished Jul 12 04:43:31 PM PDT 24
Peak memory 225420 kb
Host smart-711c67ce-fddd-456a-9b1c-f8717fe64c7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669238076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3669238076
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1677711699
Short name T20
Test name
Test status
Simulation time 383483085 ps
CPU time 9.71 seconds
Started Jul 12 04:43:13 PM PDT 24
Finished Jul 12 04:43:26 PM PDT 24
Peak memory 217632 kb
Host smart-02f85fce-19fe-467f-b444-464e5cbe6a79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677711699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
677711699
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.310445745
Short name T665
Test name
Test status
Simulation time 212435848 ps
CPU time 5.67 seconds
Started Jul 12 04:43:12 PM PDT 24
Finished Jul 12 04:43:20 PM PDT 24
Peak memory 223972 kb
Host smart-03c6c6af-111d-44b0-a696-ed62788bf097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310445745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.310445745
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2122850177
Short name T343
Test name
Test status
Simulation time 41481888 ps
CPU time 2.32 seconds
Started Jul 12 04:43:09 PM PDT 24
Finished Jul 12 04:43:14 PM PDT 24
Peak memory 222276 kb
Host smart-3ee20dd1-f5ac-4120-8a95-589cae695470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122850177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2122850177
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3548174293
Short name T856
Test name
Test status
Simulation time 251519622 ps
CPU time 26.64 seconds
Started Jul 12 04:43:08 PM PDT 24
Finished Jul 12 04:43:38 PM PDT 24
Peak memory 250444 kb
Host smart-469663d4-dffb-4736-a607-2125456c175e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548174293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3548174293
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3167082713
Short name T11
Test name
Test status
Simulation time 150283596 ps
CPU time 7.42 seconds
Started Jul 12 04:43:08 PM PDT 24
Finished Jul 12 04:43:19 PM PDT 24
Peak memory 250336 kb
Host smart-2af82eac-f37e-4ade-a3c6-eda6d02aeb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167082713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3167082713
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1733106349
Short name T169
Test name
Test status
Simulation time 36594931647 ps
CPU time 197.27 seconds
Started Jul 12 04:43:15 PM PDT 24
Finished Jul 12 04:46:36 PM PDT 24
Peak memory 283220 kb
Host smart-0d3f758b-3178-4029-a677-7758d2dc286c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733106349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1733106349
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.351492106
Short name T106
Test name
Test status
Simulation time 18087920243 ps
CPU time 389.63 seconds
Started Jul 12 04:43:13 PM PDT 24
Finished Jul 12 04:49:45 PM PDT 24
Peak memory 262692 kb
Host smart-c8c76f09-1aab-432f-8bf5-c23bbf772ee5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=351492106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.351492106
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3778999194
Short name T372
Test name
Test status
Simulation time 40246837 ps
CPU time 0.87 seconds
Started Jul 12 04:43:08 PM PDT 24
Finished Jul 12 04:43:13 PM PDT 24
Peak memory 208388 kb
Host smart-f1b8679c-3476-48d2-9b0e-0871d9d79dc5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778999194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3778999194
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.468529667
Short name T486
Test name
Test status
Simulation time 20875222 ps
CPU time 1.09 seconds
Started Jul 12 04:43:15 PM PDT 24
Finished Jul 12 04:43:19 PM PDT 24
Peak memory 208312 kb
Host smart-6a5f0fdb-9db4-4e33-9ba2-b300169b6f2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468529667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.468529667
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.964182068
Short name T197
Test name
Test status
Simulation time 11237217 ps
CPU time 1 seconds
Started Jul 12 04:43:12 PM PDT 24
Finished Jul 12 04:43:15 PM PDT 24
Peak memory 208364 kb
Host smart-41735849-13ce-4318-aed2-aefcd1f5463f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964182068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.964182068
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.2810547551
Short name T437
Test name
Test status
Simulation time 754748968 ps
CPU time 27.99 seconds
Started Jul 12 04:43:11 PM PDT 24
Finished Jul 12 04:43:42 PM PDT 24
Peak memory 217604 kb
Host smart-fa16844c-d8e1-4e33-8399-b993ae1afb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810547551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2810547551
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3089943968
Short name T94
Test name
Test status
Simulation time 2415227787 ps
CPU time 14.78 seconds
Started Jul 12 04:43:13 PM PDT 24
Finished Jul 12 04:43:31 PM PDT 24
Peak memory 217116 kb
Host smart-64ad074a-0615-401d-aa8f-c932a362ac46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089943968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3089943968
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1070690373
Short name T470
Test name
Test status
Simulation time 1618250355 ps
CPU time 48.23 seconds
Started Jul 12 04:43:17 PM PDT 24
Finished Jul 12 04:44:07 PM PDT 24
Peak memory 218284 kb
Host smart-02bb2763-51be-4d24-bb06-6a2ab449c115
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070690373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1070690373
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.4171517186
Short name T346
Test name
Test status
Simulation time 189400299 ps
CPU time 5.13 seconds
Started Jul 12 04:43:15 PM PDT 24
Finished Jul 12 04:43:23 PM PDT 24
Peak memory 217164 kb
Host smart-d1819501-2f8d-402c-af34-130b2f0d5c4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171517186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.4
171517186
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2034895275
Short name T390
Test name
Test status
Simulation time 732255779 ps
CPU time 6.9 seconds
Started Jul 12 04:43:16 PM PDT 24
Finished Jul 12 04:43:25 PM PDT 24
Peak memory 217652 kb
Host smart-f3781060-8acf-4f7e-af3f-ea312a3d801b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034895275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2034895275
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1331784330
Short name T440
Test name
Test status
Simulation time 1145665724 ps
CPU time 19.54 seconds
Started Jul 12 04:43:15 PM PDT 24
Finished Jul 12 04:43:38 PM PDT 24
Peak memory 217048 kb
Host smart-f5651750-c235-487d-a0fd-31265174b81e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331784330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1331784330
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3301370278
Short name T539
Test name
Test status
Simulation time 641891005 ps
CPU time 3.42 seconds
Started Jul 12 04:43:15 PM PDT 24
Finished Jul 12 04:43:22 PM PDT 24
Peak memory 217036 kb
Host smart-a53c7ea4-c3d8-4897-b3ff-f3d187d67938
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301370278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3301370278
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3609614836
Short name T644
Test name
Test status
Simulation time 1312998962 ps
CPU time 50.99 seconds
Started Jul 12 04:43:11 PM PDT 24
Finished Jul 12 04:44:05 PM PDT 24
Peak memory 266724 kb
Host smart-2306930a-de3b-4637-b16d-595f248230b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609614836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3609614836
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1590706305
Short name T754
Test name
Test status
Simulation time 1306448336 ps
CPU time 26.92 seconds
Started Jul 12 04:43:17 PM PDT 24
Finished Jul 12 04:43:47 PM PDT 24
Peak memory 250368 kb
Host smart-4f2d5ff6-80d9-4de1-adc3-bd19a9381491
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590706305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1590706305
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3851738093
Short name T246
Test name
Test status
Simulation time 235193798 ps
CPU time 1.96 seconds
Started Jul 12 04:43:13 PM PDT 24
Finished Jul 12 04:43:17 PM PDT 24
Peak memory 217636 kb
Host smart-86f84ca5-f912-41e0-8a80-20efa53aa223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851738093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3851738093
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3526115634
Short name T620
Test name
Test status
Simulation time 475244827 ps
CPU time 13.37 seconds
Started Jul 12 04:43:14 PM PDT 24
Finished Jul 12 04:43:30 PM PDT 24
Peak memory 217156 kb
Host smart-ecc66496-4260-4074-acff-1a13facacc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526115634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3526115634
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3648760705
Short name T247
Test name
Test status
Simulation time 1881142977 ps
CPU time 13.12 seconds
Started Jul 12 04:43:17 PM PDT 24
Finished Jul 12 04:43:33 PM PDT 24
Peak memory 225348 kb
Host smart-7caae701-7fd6-489f-aa0c-f6678fe55473
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648760705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3648760705
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2523050741
Short name T681
Test name
Test status
Simulation time 510387245 ps
CPU time 6.82 seconds
Started Jul 12 04:43:14 PM PDT 24
Finished Jul 12 04:43:24 PM PDT 24
Peak memory 217584 kb
Host smart-10df2bcd-8e08-48b4-bb21-a06000592dc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523050741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
523050741
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3417097367
Short name T671
Test name
Test status
Simulation time 1332454950 ps
CPU time 6.84 seconds
Started Jul 12 04:43:13 PM PDT 24
Finished Jul 12 04:43:23 PM PDT 24
Peak memory 217700 kb
Host smart-6e70835a-ef8f-4cb0-b6b8-523d11711af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417097367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3417097367
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3500729866
Short name T629
Test name
Test status
Simulation time 31070087 ps
CPU time 1.37 seconds
Started Jul 12 04:43:16 PM PDT 24
Finished Jul 12 04:43:20 PM PDT 24
Peak memory 213152 kb
Host smart-d42c1e20-24c2-448c-b447-be71468e8baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500729866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3500729866
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2768186351
Short name T382
Test name
Test status
Simulation time 272530057 ps
CPU time 27.7 seconds
Started Jul 12 04:43:15 PM PDT 24
Finished Jul 12 04:43:46 PM PDT 24
Peak memory 250536 kb
Host smart-3df7e25c-9f01-45db-ada1-a375776ecf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768186351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2768186351
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2364866419
Short name T826
Test name
Test status
Simulation time 71199691 ps
CPU time 2.93 seconds
Started Jul 12 04:43:14 PM PDT 24
Finished Jul 12 04:43:20 PM PDT 24
Peak memory 222136 kb
Host smart-5348ff39-1378-463e-9fb9-4fe50937047b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364866419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2364866419
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3117406991
Short name T28
Test name
Test status
Simulation time 11281818036 ps
CPU time 88.34 seconds
Started Jul 12 04:43:20 PM PDT 24
Finished Jul 12 04:44:52 PM PDT 24
Peak memory 250452 kb
Host smart-9b56c609-4bf4-4994-8aa9-27c3cff6987c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117406991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3117406991
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2501710736
Short name T639
Test name
Test status
Simulation time 13011213 ps
CPU time 0.77 seconds
Started Jul 12 04:43:13 PM PDT 24
Finished Jul 12 04:43:16 PM PDT 24
Peak memory 208232 kb
Host smart-67c07f9d-f45c-4a93-a6c5-85e5aeebb60f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501710736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2501710736
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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