Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99692026

1

T1

107689

T2

4552

T3

26459

auto[1]

1382238

1

T2

396

T8

198

T11

6406

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99671409

1

T1

107689

T2

4156

T3

26459

auto[1]

1402855

1

T2

792

T8

297

T11

7333

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7368284	1			T1	101		T2	1099		T3	6968
auto[IdleSt]	23115134	1			T1	107588		T2	1533		T3	2573
auto[ClkMuxSt]	34076	1			T2	12		T3	74		T4	6
auto[CntIncrSt]	33919	1			T2	12		T3	74		T4	6
auto[CntProgSt]	1425100	1			T2	24		T3	2215		T4	12
auto[TransCheckSt]	26394	1			T3	74		T4	6		T8	5
auto[TokenHashSt]	34997333	1			T3	2999		T4	64		T8	376
auto[FlashRmaSt]	32983	1			T3	72		T4	6		T8	23
auto[TokenCheck0St]	12121	1			T3	23		T4	6		T8	5
auto[TokenCheck1St]	9051	1			T3	7		T4	6		T8	5
auto[TransProgSt]	380228	1			T4	12		T8	10		T11	31
auto[PostTransSt]	13863536	1			T2	737		T3	11380		T4	1185
auto[ScrapSt]	296671	1			T4	1961		T10	1047		T11	9
auto[EscalateSt]	7059496	1			T2	1531		T8	1334		T11	10002
auto[InvalidSt]	12417910	1			T8	963		T5	307655		T34	246

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2028	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12417910	1			T8	963		T5	307655		T34	246
EscalateSt	7059496	1			T2	1531		T8	1334		T11	10002
ScrapSt	296671	1			T4	1961		T10	1047		T11	9
PostTransSt	13863536	1			T2	737		T3	11380		T4	1185
TransProgSt	380228	1			T4	12		T8	10		T11	31
TokenCheck1St	9051	1			T3	7		T4	6		T8	5
TokenCheck0St	12121	1			T3	23		T4	6		T8	5
FlashRmaSt	32983	1			T3	72		T4	6		T8	23
TokenHashSt	34997333	1			T3	2999		T4	64		T8	376
TransCheckSt	26394	1			T3	74		T4	6		T8	5
CntProgSt	1425100	1			T2	24		T3	2215		T4	12
CntIncrSt	33919	1			T2	12		T3	74		T4	6
ClkMuxSt	34076	1			T2	12		T3	74		T4	6
IdleSt	23115134	1			T1	107588		T2	1533		T3	2573
ResetSt	7368284	1			T1	101		T2	1099		T3	6968
arcs[ResetSt=>IdleSt]	52675	1			T1	1		T2	13		T3	75
arcs[IdleSt=>ScrapSt]	310	1			T4	2		T10	1		T11	3
arcs[IdleSt=>ClkMuxSt]	33976	1			T2	12		T3	74		T4	6
arcs[ClkMuxSt=>CntIncrSt]	33919	1			T2	12		T3	74		T4	6
arcs[CntIncrSt=>PostTransSt]	1722	1			T5	22		T17	34		T31	19
arcs[CntIncrSt=>CntProgSt]	32135	1			T2	12		T3	74		T4	6
arcs[CntProgSt=>PostTransSt]	4678	1			T2	12		T5	44		T14	9
arcs[CntProgSt=>TransCheckSt]	26394	1			T3	74		T4	6		T8	5
arcs[TransCheckSt=>PostTransSt]	3586	1			T3	39		T5	15		T36	39
arcs[TransCheckSt=>TokenHashSt]	22658	1			T3	35		T4	6		T8	5
arcs[TokenHashSt=>PostTransSt]	9784	1			T3	12		T9	92		T5	60
arcs[TokenHashSt=>FlashRmaSt]	12199	1			T3	23		T4	6		T8	5
arcs[FlashRmaSt=>TokenCheck0St]	12121	1			T3	23		T4	6		T8	5
arcs[TokenCheck0St=>PostTransSt]	3044	1			T3	16		T5	18		T36	24
arcs[TokenCheck0St=>TokenCheck1St]	9051	1			T3	7		T4	6		T8	5
arcs[TokenCheck1St=>PostTransSt]	599	1			T3	7		T5	4		T36	12
arcs[TransProgSt=>PostTransSt]	7642	1			T4	6		T8	5		T11	10
arcs[IdleSt=>EscalateSt]	197	1			T12	3		T55	6		T54	4
arcs[ClkMuxSt=>EscalateSt]	57	1			T12	1		T53	2		T54	3
arcs[CntIncrSt=>EscalateSt]	62	1			T11	2		T12	2		T53	1
arcs[CntProgSt=>EscalateSt]	1063	1			T11	6		T12	27		T55	9
arcs[TransCheckSt=>EscalateSt]	150	1			T11	4		T55	9		T53	1
arcs[TokenHashSt=>EscalateSt]	674	1			T11	24		T12	7		T5	1
arcs[FlashRmaSt=>EscalateSt]	78	1			T11	1		T12	2		T55	4
arcs[TokenCheck0St=>EscalateSt]	26	1			T11	1		T55	1		T59	2
arcs[TokenCheck1St=>EscalateSt]	148	1			T11	1		T12	1		T55	2
arcs[TransProgSt=>EscalateSt]	662	1			T11	7		T12	15		T55	11
arcs[PostTransSt=>EscalateSt]	4935	1			T2	12		T11	10		T12	2
arcs[InvalidSt=>EscalateSt]	14106	1			T8	5		T5	195		T34	2

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7368104	1			T1	101		T2	1099		T3	6968
auto[0]	auto[IdleSt]	23114992	1			T1	107588		T2	1533		T3	2573
auto[0]	auto[ClkMuxSt]	34046	1			T2	12		T3	74		T4	6
auto[0]	auto[CntIncrSt]	33870	1			T2	12		T3	74		T4	6
auto[0]	auto[CntProgSt]	1424367	1			T2	24		T3	2215		T4	12
auto[0]	auto[TransCheckSt]	26293	1			T3	74		T4	6		T8	5
auto[0]	auto[TokenHashSt]	34996860	1			T3	2999		T4	64		T8	376
auto[0]	auto[FlashRmaSt]	32932	1			T3	72		T4	6		T8	23
auto[0]	auto[TokenCheck0St]	12101	1			T3	23		T4	6		T8	5
auto[0]	auto[TokenCheck1St]	8952	1			T3	7		T4	6		T8	5
auto[0]	auto[TransProgSt]	379792	1			T4	12		T8	10		T11	26
auto[0]	auto[PostTransSt]	13861070	1			T2	733		T3	11380		T4	1185
auto[0]	auto[ScrapSt]	296636	1			T4	1961		T10	1047		T11	7
auto[0]	auto[EscalateSt]	5689023	1			T2	1139		T8	1138		T11	3636
auto[0]	auto[InvalidSt]	12410960	1			T8	961		T5	307568		T34	245
auto[1]	auto[ResetSt]	180	1			T11	3		T12	6		T55	3
auto[1]	auto[IdleSt]	142	1			T12	3		T55	3		T54	4
auto[1]	auto[ClkMuxSt]	30	1			T12	1		T54	2		T181	1
auto[1]	auto[CntIncrSt]	49	1			T11	2		T12	2		T53	1
auto[1]	auto[CntProgSt]	733	1			T11	4		T12	18		T55	7
auto[1]	auto[TransCheckSt]	101	1			T11	2		T55	6		T182	1
auto[1]	auto[TokenHashSt]	473	1			T11	16		T12	4		T17	1
auto[1]	auto[FlashRmaSt]	51	1			T11	1		T12	2		T55	4
auto[1]	auto[TokenCheck0St]	20	1			T11	1		T55	1		T59	2
auto[1]	auto[TokenCheck1St]	99	1			T11	1		T12	1		T55	1
auto[1]	auto[TransProgSt]	436	1			T11	5		T12	5		T55	9
auto[1]	auto[PostTransSt]	2466	1			T2	4		T11	3		T5	23
auto[1]	auto[ScrapSt]	35	1			T11	2		T53	1		T59	1
auto[1]	auto[EscalateSt]	1370473	1			T2	392		T8	196		T11	6366
auto[1]	auto[InvalidSt]	6950	1			T8	2		T5	87		T34	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7368095	1			T1	101		T2	1099		T3	6968
auto[0]	auto[IdleSt]	23114998	1			T1	107588		T2	1533		T3	2573
auto[0]	auto[ClkMuxSt]	34033	1			T2	12		T3	74		T4	6
auto[0]	auto[CntIncrSt]	33881	1			T2	12		T3	74		T4	6
auto[0]	auto[CntProgSt]	1424402	1			T2	24		T3	2215		T4	12
auto[0]	auto[TransCheckSt]	26298	1			T3	74		T4	6		T8	5
auto[0]	auto[TokenHashSt]	34996903	1			T3	2999		T4	64		T8	376
auto[0]	auto[FlashRmaSt]	32928	1			T3	72		T4	6		T8	23
auto[0]	auto[TokenCheck0St]	12100	1			T3	23		T4	6		T8	5
auto[0]	auto[TokenCheck1St]	8945	1			T3	7		T4	6		T8	5
auto[0]	auto[TransProgSt]	379769	1			T4	12		T8	10		T11	26
auto[0]	auto[PostTransSt]	13860996	1			T2	729		T3	11380		T4	1185
auto[0]	auto[ScrapSt]	296636	1			T4	1961		T10	1047		T11	8
auto[0]	auto[EscalateSt]	5668643	1			T2	747		T8	1040		T11	2714
auto[0]	auto[InvalidSt]	12410754	1			T8	960		T5	307547		T34	245
auto[1]	auto[ResetSt]	189	1			T11	3		T12	6		T55	3
auto[1]	auto[IdleSt]	136	1			T12	2		T55	5		T54	1
auto[1]	auto[ClkMuxSt]	43	1			T12	1		T53	2		T54	3
auto[1]	auto[CntIncrSt]	38	1			T11	1		T53	1		T59	3
auto[1]	auto[CntProgSt]	698	1			T11	4		T12	17		T55	5
auto[1]	auto[TransCheckSt]	96	1			T11	4		T55	4		T53	1
auto[1]	auto[TokenHashSt]	430	1			T11	16		T12	5		T5	1
auto[1]	auto[FlashRmaSt]	55	1			T12	1		T55	2		T53	1
auto[1]	auto[TokenCheck0St]	21	1			T11	1		T55	1		T59	2
auto[1]	auto[TokenCheck1St]	106	1			T11	1		T12	1		T55	2
auto[1]	auto[TransProgSt]	459	1			T11	5		T12	11		T55	8
auto[1]	auto[PostTransSt]	2540	1			T2	8		T11	9		T12	2
auto[1]	auto[ScrapSt]	35	1			T11	1		T55	2		T181	1
auto[1]	auto[EscalateSt]	1390853	1			T2	784		T8	294		T11	7288
auto[1]	auto[InvalidSt]	7156	1			T8	3		T5	108		T34	1