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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.23 97.99 96.04 93.38 100.00 98.55 98.51 96.11


Total test records in report: 996
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T811 /workspace/coverage/default/38.lc_ctrl_errors.468552316 Jul 13 04:47:52 PM PDT 24 Jul 13 04:48:10 PM PDT 24 2007893097 ps
T812 /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1270523672 Jul 13 04:46:11 PM PDT 24 Jul 13 04:46:12 PM PDT 24 46218352 ps
T813 /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3953922212 Jul 13 04:46:21 PM PDT 24 Jul 13 04:46:37 PM PDT 24 1657161504 ps
T814 /workspace/coverage/default/16.lc_ctrl_stress_all.749870746 Jul 13 04:46:57 PM PDT 24 Jul 13 04:47:25 PM PDT 24 4360930450 ps
T815 /workspace/coverage/default/34.lc_ctrl_jtag_access.1647222979 Jul 13 04:47:44 PM PDT 24 Jul 13 04:47:50 PM PDT 24 890170304 ps
T816 /workspace/coverage/default/27.lc_ctrl_sec_mubi.1388953030 Jul 13 04:47:24 PM PDT 24 Jul 13 04:47:37 PM PDT 24 269769070 ps
T817 /workspace/coverage/default/21.lc_ctrl_prog_failure.3481060528 Jul 13 04:47:08 PM PDT 24 Jul 13 04:47:10 PM PDT 24 65548883 ps
T818 /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1397348992 Jul 13 04:46:39 PM PDT 24 Jul 13 04:46:53 PM PDT 24 604445669 ps
T819 /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.3417974227 Jul 13 04:46:46 PM PDT 24 Jul 13 04:53:04 PM PDT 24 23071020538 ps
T820 /workspace/coverage/default/17.lc_ctrl_sec_mubi.855907701 Jul 13 04:46:57 PM PDT 24 Jul 13 04:47:17 PM PDT 24 4103519151 ps
T821 /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3713260661 Jul 13 04:46:36 PM PDT 24 Jul 13 04:46:49 PM PDT 24 2142356408 ps
T822 /workspace/coverage/default/3.lc_ctrl_jtag_priority.260596526 Jul 13 04:46:01 PM PDT 24 Jul 13 04:46:05 PM PDT 24 813444354 ps
T823 /workspace/coverage/default/16.lc_ctrl_jtag_access.1955341835 Jul 13 04:46:47 PM PDT 24 Jul 13 04:46:53 PM PDT 24 367295341 ps
T824 /workspace/coverage/default/27.lc_ctrl_errors.1723213568 Jul 13 04:47:31 PM PDT 24 Jul 13 04:47:42 PM PDT 24 514681821 ps
T825 /workspace/coverage/default/31.lc_ctrl_prog_failure.1221177928 Jul 13 04:47:40 PM PDT 24 Jul 13 04:47:43 PM PDT 24 210805284 ps
T826 /workspace/coverage/default/34.lc_ctrl_errors.1181109918 Jul 13 04:47:46 PM PDT 24 Jul 13 04:48:04 PM PDT 24 424243781 ps
T827 /workspace/coverage/default/46.lc_ctrl_state_post_trans.28672310 Jul 13 04:48:09 PM PDT 24 Jul 13 04:48:14 PM PDT 24 140929424 ps
T828 /workspace/coverage/default/25.lc_ctrl_state_failure.4161173163 Jul 13 04:47:25 PM PDT 24 Jul 13 04:48:04 PM PDT 24 1537186895 ps
T829 /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3805121357 Jul 13 04:46:47 PM PDT 24 Jul 13 04:47:06 PM PDT 24 1081677906 ps
T830 /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3950137680 Jul 13 04:46:38 PM PDT 24 Jul 13 04:46:54 PM PDT 24 356543381 ps
T831 /workspace/coverage/default/12.lc_ctrl_alert_test.4000622923 Jul 13 04:46:38 PM PDT 24 Jul 13 04:46:40 PM PDT 24 20622308 ps
T832 /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2643692639 Jul 13 04:46:53 PM PDT 24 Jul 13 04:46:59 PM PDT 24 893345565 ps
T833 /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1655952854 Jul 13 04:46:20 PM PDT 24 Jul 13 04:46:38 PM PDT 24 885348659 ps
T834 /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3509923837 Jul 13 04:48:06 PM PDT 24 Jul 13 04:52:32 PM PDT 24 29827723163 ps
T835 /workspace/coverage/default/30.lc_ctrl_jtag_access.3101401644 Jul 13 04:47:34 PM PDT 24 Jul 13 04:47:46 PM PDT 24 2046033409 ps
T836 /workspace/coverage/default/18.lc_ctrl_stress_all.2997950405 Jul 13 04:47:14 PM PDT 24 Jul 13 04:49:58 PM PDT 24 14538542989 ps
T837 /workspace/coverage/default/46.lc_ctrl_sec_token_mux.249384215 Jul 13 04:48:20 PM PDT 24 Jul 13 04:48:29 PM PDT 24 1082515014 ps
T838 /workspace/coverage/default/11.lc_ctrl_smoke.3516131357 Jul 13 04:46:32 PM PDT 24 Jul 13 04:46:36 PM PDT 24 39701485 ps
T839 /workspace/coverage/default/3.lc_ctrl_alert_test.4070528898 Jul 13 04:46:00 PM PDT 24 Jul 13 04:46:02 PM PDT 24 44951437 ps
T840 /workspace/coverage/default/17.lc_ctrl_smoke.3953935420 Jul 13 04:47:01 PM PDT 24 Jul 13 04:47:07 PM PDT 24 123515219 ps
T841 /workspace/coverage/default/1.lc_ctrl_jtag_priority.2157064049 Jul 13 04:45:53 PM PDT 24 Jul 13 04:46:00 PM PDT 24 2750666870 ps
T842 /workspace/coverage/default/40.lc_ctrl_security_escalation.2148489793 Jul 13 04:48:00 PM PDT 24 Jul 13 04:48:13 PM PDT 24 933473821 ps
T843 /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2991131330 Jul 13 04:45:45 PM PDT 24 Jul 13 04:46:00 PM PDT 24 854021110 ps
T844 /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2581609307 Jul 13 04:46:35 PM PDT 24 Jul 13 04:46:41 PM PDT 24 246393258 ps
T845 /workspace/coverage/default/12.lc_ctrl_sec_token_digest.156859313 Jul 13 04:46:47 PM PDT 24 Jul 13 04:46:58 PM PDT 24 302121218 ps
T846 /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1430411758 Jul 13 04:46:19 PM PDT 24 Jul 13 04:46:34 PM PDT 24 2279044141 ps
T847 /workspace/coverage/default/4.lc_ctrl_jtag_priority.549844488 Jul 13 04:46:02 PM PDT 24 Jul 13 04:46:09 PM PDT 24 445454553 ps
T848 /workspace/coverage/default/40.lc_ctrl_smoke.2410174333 Jul 13 04:47:59 PM PDT 24 Jul 13 04:48:04 PM PDT 24 99130112 ps
T849 /workspace/coverage/default/47.lc_ctrl_security_escalation.1450479207 Jul 13 04:48:16 PM PDT 24 Jul 13 04:48:27 PM PDT 24 398440389 ps
T850 /workspace/coverage/default/43.lc_ctrl_sec_token_mux.4176379775 Jul 13 04:48:10 PM PDT 24 Jul 13 04:48:20 PM PDT 24 442845930 ps
T851 /workspace/coverage/default/9.lc_ctrl_smoke.310091968 Jul 13 04:46:31 PM PDT 24 Jul 13 04:46:33 PM PDT 24 42835486 ps
T852 /workspace/coverage/default/20.lc_ctrl_sec_mubi.627825580 Jul 13 04:47:11 PM PDT 24 Jul 13 04:47:30 PM PDT 24 382237104 ps
T853 /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.683057680 Jul 13 04:46:47 PM PDT 24 Jul 13 04:46:51 PM PDT 24 32767236 ps
T854 /workspace/coverage/default/8.lc_ctrl_state_failure.2792989962 Jul 13 04:46:20 PM PDT 24 Jul 13 04:46:39 PM PDT 24 1556868840 ps
T855 /workspace/coverage/default/49.lc_ctrl_errors.1861233928 Jul 13 04:48:17 PM PDT 24 Jul 13 04:48:35 PM PDT 24 1000650981 ps
T856 /workspace/coverage/default/1.lc_ctrl_security_escalation.71962123 Jul 13 04:45:53 PM PDT 24 Jul 13 04:46:09 PM PDT 24 348435864 ps
T857 /workspace/coverage/default/24.lc_ctrl_jtag_access.2231930099 Jul 13 04:47:24 PM PDT 24 Jul 13 04:47:32 PM PDT 24 272493175 ps
T858 /workspace/coverage/default/28.lc_ctrl_state_post_trans.2633094905 Jul 13 04:47:31 PM PDT 24 Jul 13 04:47:40 PM PDT 24 93338366 ps
T859 /workspace/coverage/default/35.lc_ctrl_smoke.1045515484 Jul 13 04:47:44 PM PDT 24 Jul 13 04:47:46 PM PDT 24 18456202 ps
T860 /workspace/coverage/default/42.lc_ctrl_errors.3683718086 Jul 13 04:47:59 PM PDT 24 Jul 13 04:48:16 PM PDT 24 3049780285 ps
T861 /workspace/coverage/default/41.lc_ctrl_stress_all.4279614120 Jul 13 04:47:58 PM PDT 24 Jul 13 04:52:22 PM PDT 24 7449115319 ps
T862 /workspace/coverage/default/11.lc_ctrl_security_escalation.2990770998 Jul 13 04:46:32 PM PDT 24 Jul 13 04:46:42 PM PDT 24 277368152 ps
T863 /workspace/coverage/default/3.lc_ctrl_stress_all.1503378905 Jul 13 04:46:01 PM PDT 24 Jul 13 04:49:00 PM PDT 24 11267167669 ps
T864 /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2754047985 Jul 13 04:46:11 PM PDT 24 Jul 13 04:46:21 PM PDT 24 1209976282 ps
T865 /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2465434744 Jul 13 04:47:22 PM PDT 24 Jul 13 04:47:35 PM PDT 24 510130582 ps
T866 /workspace/coverage/default/34.lc_ctrl_smoke.3597528128 Jul 13 04:47:48 PM PDT 24 Jul 13 04:47:52 PM PDT 24 85062773 ps
T867 /workspace/coverage/default/10.lc_ctrl_prog_failure.2112767662 Jul 13 04:46:31 PM PDT 24 Jul 13 04:46:36 PM PDT 24 396865590 ps
T868 /workspace/coverage/default/46.lc_ctrl_sec_mubi.1826136808 Jul 13 04:48:17 PM PDT 24 Jul 13 04:48:38 PM PDT 24 393432327 ps
T869 /workspace/coverage/default/30.lc_ctrl_errors.2086647506 Jul 13 04:47:35 PM PDT 24 Jul 13 04:47:50 PM PDT 24 4197860856 ps
T870 /workspace/coverage/default/18.lc_ctrl_jtag_access.2219713242 Jul 13 04:47:11 PM PDT 24 Jul 13 04:47:17 PM PDT 24 1064289228 ps
T137 /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.3376930452 Jul 13 04:48:09 PM PDT 24 Jul 13 04:52:42 PM PDT 24 31157316882 ps
T96 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2408970967 Jul 13 06:23:51 PM PDT 24 Jul 13 06:23:54 PM PDT 24 117840435 ps
T102 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.323722632 Jul 13 06:24:13 PM PDT 24 Jul 13 06:24:15 PM PDT 24 44752589 ps
T97 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1031052402 Jul 13 06:23:38 PM PDT 24 Jul 13 06:23:41 PM PDT 24 43650657 ps
T103 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.305610298 Jul 13 06:23:59 PM PDT 24 Jul 13 06:24:03 PM PDT 24 96042363 ps
T106 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1869744174 Jul 13 06:23:43 PM PDT 24 Jul 13 06:23:45 PM PDT 24 46492630 ps
T104 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.332311917 Jul 13 06:23:49 PM PDT 24 Jul 13 06:23:58 PM PDT 24 118120928 ps
T99 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.970658559 Jul 13 06:23:54 PM PDT 24 Jul 13 06:23:56 PM PDT 24 19939154 ps
T127 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1643857917 Jul 13 06:23:39 PM PDT 24 Jul 13 06:23:41 PM PDT 24 49657383 ps
T98 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1132258394 Jul 13 06:24:19 PM PDT 24 Jul 13 06:24:25 PM PDT 24 561034692 ps
T169 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2967071635 Jul 13 06:24:00 PM PDT 24 Jul 13 06:24:02 PM PDT 24 57174850 ps
T138 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.746760529 Jul 13 06:24:05 PM PDT 24 Jul 13 06:24:06 PM PDT 24 13756174 ps
T148 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.319667957 Jul 13 06:23:39 PM PDT 24 Jul 13 06:23:40 PM PDT 24 28832755 ps
T170 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3659553623 Jul 13 06:24:20 PM PDT 24 Jul 13 06:24:25 PM PDT 24 326026494 ps
T129 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3497425540 Jul 13 06:23:46 PM PDT 24 Jul 13 06:23:51 PM PDT 24 299943229 ps
T871 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3007394060 Jul 13 06:24:02 PM PDT 24 Jul 13 06:24:04 PM PDT 24 681635878 ps
T155 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3897915161 Jul 13 06:23:50 PM PDT 24 Jul 13 06:23:52 PM PDT 24 81185500 ps
T100 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1029556782 Jul 13 06:23:55 PM PDT 24 Jul 13 06:24:00 PM PDT 24 477056332 ps
T128 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1187185749 Jul 13 06:23:42 PM PDT 24 Jul 13 06:23:45 PM PDT 24 164569341 ps
T101 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2924206375 Jul 13 06:24:06 PM PDT 24 Jul 13 06:24:10 PM PDT 24 369556529 ps
T126 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2656109583 Jul 13 06:24:17 PM PDT 24 Jul 13 06:24:22 PM PDT 24 46466440 ps
T118 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.53545802 Jul 13 06:24:03 PM PDT 24 Jul 13 06:24:05 PM PDT 24 148433853 ps
T121 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.888742361 Jul 13 06:23:47 PM PDT 24 Jul 13 06:23:52 PM PDT 24 53085580 ps
T120 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1690071377 Jul 13 06:23:26 PM PDT 24 Jul 13 06:23:29 PM PDT 24 87550773 ps
T872 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1562766135 Jul 13 06:23:46 PM PDT 24 Jul 13 06:23:49 PM PDT 24 18412045 ps
T873 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2165800399 Jul 13 06:23:53 PM PDT 24 Jul 13 06:24:00 PM PDT 24 978371073 ps
T874 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3611101009 Jul 13 06:23:39 PM PDT 24 Jul 13 06:24:14 PM PDT 24 1519782135 ps
T149 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2815343155 Jul 13 06:24:06 PM PDT 24 Jul 13 06:24:07 PM PDT 24 17023855 ps
T105 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1976401177 Jul 13 06:23:47 PM PDT 24 Jul 13 06:23:52 PM PDT 24 1089881469 ps
T150 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3206815749 Jul 13 06:24:07 PM PDT 24 Jul 13 06:24:09 PM PDT 24 29731371 ps
T171 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1100645959 Jul 13 06:23:36 PM PDT 24 Jul 13 06:23:38 PM PDT 24 36038029 ps
T110 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2144037691 Jul 13 06:23:59 PM PDT 24 Jul 13 06:24:01 PM PDT 24 44318285 ps
T111 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2970474423 Jul 13 06:23:47 PM PDT 24 Jul 13 06:23:51 PM PDT 24 30049762 ps
T156 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3725728712 Jul 13 06:23:46 PM PDT 24 Jul 13 06:23:50 PM PDT 24 46390574 ps
T875 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3601079577 Jul 13 06:24:19 PM PDT 24 Jul 13 06:24:23 PM PDT 24 26800810 ps
T876 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2145124633 Jul 13 06:24:17 PM PDT 24 Jul 13 06:24:21 PM PDT 24 301547894 ps
T877 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3338356039 Jul 13 06:23:39 PM PDT 24 Jul 13 06:23:41 PM PDT 24 200210934 ps
T878 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2307077601 Jul 13 06:24:16 PM PDT 24 Jul 13 06:24:21 PM PDT 24 45980273 ps
T112 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.959821642 Jul 13 06:23:48 PM PDT 24 Jul 13 06:23:56 PM PDT 24 143585965 ps
T157 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1492842802 Jul 13 06:23:49 PM PDT 24 Jul 13 06:23:52 PM PDT 24 40458913 ps
T879 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1295714498 Jul 13 06:24:05 PM PDT 24 Jul 13 06:24:16 PM PDT 24 2299214287 ps
T880 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.847633518 Jul 13 06:23:42 PM PDT 24 Jul 13 06:23:44 PM PDT 24 78239880 ps
T881 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.603106548 Jul 13 06:23:50 PM PDT 24 Jul 13 06:23:53 PM PDT 24 147098980 ps
T882 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2175760721 Jul 13 06:23:55 PM PDT 24 Jul 13 06:24:00 PM PDT 24 316876407 ps
T883 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3548128202 Jul 13 06:23:46 PM PDT 24 Jul 13 06:23:49 PM PDT 24 102306998 ps
T884 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1232750630 Jul 13 06:24:17 PM PDT 24 Jul 13 06:24:20 PM PDT 24 24596808 ps
T119 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.859466648 Jul 13 06:24:00 PM PDT 24 Jul 13 06:24:04 PM PDT 24 323495104 ps
T172 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3373767400 Jul 13 06:24:11 PM PDT 24 Jul 13 06:24:14 PM PDT 24 56679660 ps
T885 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3226858276 Jul 13 06:23:57 PM PDT 24 Jul 13 06:23:58 PM PDT 24 19609256 ps
T113 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.89200547 Jul 13 06:23:54 PM PDT 24 Jul 13 06:23:58 PM PDT 24 452775975 ps
T886 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.451248594 Jul 13 06:23:52 PM PDT 24 Jul 13 06:23:55 PM PDT 24 87433714 ps
T887 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3664805509 Jul 13 06:24:09 PM PDT 24 Jul 13 06:24:12 PM PDT 24 132388524 ps
T888 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2830688220 Jul 13 06:23:52 PM PDT 24 Jul 13 06:23:55 PM PDT 24 439629339 ps
T173 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.403927058 Jul 13 06:23:46 PM PDT 24 Jul 13 06:23:49 PM PDT 24 108725404 ps
T114 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.470541354 Jul 13 06:23:57 PM PDT 24 Jul 13 06:24:05 PM PDT 24 105912449 ps
T108 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1658505118 Jul 13 06:23:41 PM PDT 24 Jul 13 06:23:44 PM PDT 24 339235144 ps
T174 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3211256227 Jul 13 06:23:52 PM PDT 24 Jul 13 06:23:54 PM PDT 24 55199024 ps
T889 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.973347274 Jul 13 06:23:45 PM PDT 24 Jul 13 06:23:47 PM PDT 24 32278219 ps
T158 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3895039393 Jul 13 06:23:58 PM PDT 24 Jul 13 06:24:00 PM PDT 24 30728706 ps
T890 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.876004621 Jul 13 06:23:53 PM PDT 24 Jul 13 06:23:56 PM PDT 24 93263327 ps
T175 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3023962293 Jul 13 06:23:53 PM PDT 24 Jul 13 06:23:55 PM PDT 24 15047407 ps
T891 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1371269089 Jul 13 06:23:47 PM PDT 24 Jul 13 06:24:07 PM PDT 24 1453831602 ps
T892 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1032448716 Jul 13 06:24:06 PM PDT 24 Jul 13 06:24:08 PM PDT 24 87816582 ps
T893 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2424590954 Jul 13 06:23:45 PM PDT 24 Jul 13 06:23:58 PM PDT 24 2342181260 ps
T894 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.204695853 Jul 13 06:23:46 PM PDT 24 Jul 13 06:23:51 PM PDT 24 171184359 ps
T895 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1836277585 Jul 13 06:23:40 PM PDT 24 Jul 13 06:23:42 PM PDT 24 81053272 ps
T159 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3785031981 Jul 13 06:25:59 PM PDT 24 Jul 13 06:26:00 PM PDT 24 33902561 ps
T160 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.407898085 Jul 13 06:24:17 PM PDT 24 Jul 13 06:24:22 PM PDT 24 159207965 ps
T115 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.182036999 Jul 13 06:24:16 PM PDT 24 Jul 13 06:24:22 PM PDT 24 841435343 ps
T896 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2918656326 Jul 13 06:23:50 PM PDT 24 Jul 13 06:23:54 PM PDT 24 119004232 ps
T897 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2170122603 Jul 13 06:24:05 PM PDT 24 Jul 13 06:24:10 PM PDT 24 538288618 ps
T898 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2781906110 Jul 13 06:23:46 PM PDT 24 Jul 13 06:23:53 PM PDT 24 107965440 ps
T161 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1442046560 Jul 13 06:23:47 PM PDT 24 Jul 13 06:23:50 PM PDT 24 24582536 ps
T899 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.336400758 Jul 13 06:23:42 PM PDT 24 Jul 13 06:23:44 PM PDT 24 51440535 ps
T162 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.164464965 Jul 13 06:23:41 PM PDT 24 Jul 13 06:23:43 PM PDT 24 38544881 ps
T900 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2044751725 Jul 13 06:24:00 PM PDT 24 Jul 13 06:24:02 PM PDT 24 50309133 ps
T901 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3856310719 Jul 13 06:23:52 PM PDT 24 Jul 13 06:23:56 PM PDT 24 786374818 ps
T902 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2795889054 Jul 13 06:23:47 PM PDT 24 Jul 13 06:23:51 PM PDT 24 50722819 ps
T903 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1592971964 Jul 13 06:23:34 PM PDT 24 Jul 13 06:23:36 PM PDT 24 379159481 ps
T163 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1226151587 Jul 13 06:23:47 PM PDT 24 Jul 13 06:23:50 PM PDT 24 33319251 ps
T904 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1291910524 Jul 13 06:23:56 PM PDT 24 Jul 13 06:23:58 PM PDT 24 189501765 ps
T905 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3613687135 Jul 13 06:23:39 PM PDT 24 Jul 13 06:23:47 PM PDT 24 662828089 ps
T906 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2648082311 Jul 13 06:23:44 PM PDT 24 Jul 13 06:23:46 PM PDT 24 238414448 ps
T907 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.803596867 Jul 13 06:23:48 PM PDT 24 Jul 13 06:23:53 PM PDT 24 703375937 ps
T908 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2960713565 Jul 13 06:24:17 PM PDT 24 Jul 13 06:24:20 PM PDT 24 380129076 ps
T909 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.40925617 Jul 13 06:24:05 PM PDT 24 Jul 13 06:24:08 PM PDT 24 49409202 ps
T910 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3530224051 Jul 13 06:24:17 PM PDT 24 Jul 13 06:24:27 PM PDT 24 516604776 ps
T911 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2879232799 Jul 13 06:24:29 PM PDT 24 Jul 13 06:24:38 PM PDT 24 698367230 ps
T912 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2693697939 Jul 13 06:23:39 PM PDT 24 Jul 13 06:23:46 PM PDT 24 228495630 ps
T164 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4264269680 Jul 13 06:23:44 PM PDT 24 Jul 13 06:23:46 PM PDT 24 60718083 ps
T913 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3500019182 Jul 13 06:23:46 PM PDT 24 Jul 13 06:23:53 PM PDT 24 458198899 ps
T914 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3548052032 Jul 13 06:24:21 PM PDT 24 Jul 13 06:24:34 PM PDT 24 745868888 ps
T124 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2592166226 Jul 13 06:23:46 PM PDT 24 Jul 13 06:23:51 PM PDT 24 243685935 ps
T915 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1634702304 Jul 13 06:23:39 PM PDT 24 Jul 13 06:23:40 PM PDT 24 45008518 ps
T916 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.368604356 Jul 13 06:23:41 PM PDT 24 Jul 13 06:23:45 PM PDT 24 1608964614 ps
T165 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2771188198 Jul 13 06:23:55 PM PDT 24 Jul 13 06:23:57 PM PDT 24 15048961 ps
T917 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.801971890 Jul 13 06:23:47 PM PDT 24 Jul 13 06:23:50 PM PDT 24 33579510 ps
T918 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.578146712 Jul 13 06:24:07 PM PDT 24 Jul 13 06:24:09 PM PDT 24 75442194 ps
T116 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.805874043 Jul 13 06:24:25 PM PDT 24 Jul 13 06:24:30 PM PDT 24 102934363 ps
T919 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.4074700366 Jul 13 06:23:46 PM PDT 24 Jul 13 06:23:50 PM PDT 24 19868206 ps
T920 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1062091300 Jul 13 06:23:57 PM PDT 24 Jul 13 06:23:59 PM PDT 24 133949930 ps
T921 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4089786372 Jul 13 06:24:02 PM PDT 24 Jul 13 06:24:04 PM PDT 24 89938023 ps
T922 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.623490140 Jul 13 06:23:45 PM PDT 24 Jul 13 06:23:48 PM PDT 24 57768006 ps
T923 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3667167474 Jul 13 06:23:47 PM PDT 24 Jul 13 06:23:51 PM PDT 24 29083726 ps
T924 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1865424657 Jul 13 06:23:45 PM PDT 24 Jul 13 06:23:47 PM PDT 24 324180219 ps
T925 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1637225991 Jul 13 06:24:07 PM PDT 24 Jul 13 06:24:08 PM PDT 24 25334748 ps
T166 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3603590255 Jul 13 06:23:52 PM PDT 24 Jul 13 06:23:54 PM PDT 24 43150389 ps
T168 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2273657704 Jul 13 06:24:14 PM PDT 24 Jul 13 06:24:16 PM PDT 24 19613186 ps
T926 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1692621213 Jul 13 06:23:34 PM PDT 24 Jul 13 06:23:36 PM PDT 24 407292542 ps
T927 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3793048958 Jul 13 06:24:12 PM PDT 24 Jul 13 06:24:14 PM PDT 24 47723452 ps
T928 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1622548109 Jul 13 06:23:47 PM PDT 24 Jul 13 06:23:52 PM PDT 24 333744081 ps
T929 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2071225335 Jul 13 06:23:48 PM PDT 24 Jul 13 06:23:56 PM PDT 24 465301104 ps
T930 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1179226355 Jul 13 06:24:00 PM PDT 24 Jul 13 06:24:02 PM PDT 24 31981600 ps
T931 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.625797834 Jul 13 06:23:47 PM PDT 24 Jul 13 06:23:50 PM PDT 24 16412959 ps
T117 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.752963278 Jul 13 06:23:36 PM PDT 24 Jul 13 06:23:38 PM PDT 24 57811069 ps
T932 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4246925907 Jul 13 06:23:59 PM PDT 24 Jul 13 06:24:01 PM PDT 24 149593045 ps
T933 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.960872265 Jul 13 06:23:45 PM PDT 24 Jul 13 06:23:47 PM PDT 24 32647183 ps
T934 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3834459109 Jul 13 06:23:46 PM PDT 24 Jul 13 06:23:49 PM PDT 24 73161933 ps
T935 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2265853129 Jul 13 06:23:50 PM PDT 24 Jul 13 06:23:52 PM PDT 24 212874897 ps
T936 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.352798248 Jul 13 06:23:45 PM PDT 24 Jul 13 06:23:47 PM PDT 24 44085200 ps
T107 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.587043252 Jul 13 06:23:55 PM PDT 24 Jul 13 06:24:01 PM PDT 24 108404941 ps
T937 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2758390215 Jul 13 06:24:10 PM PDT 24 Jul 13 06:24:12 PM PDT 24 24012843 ps
T938 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2352686248 Jul 13 06:23:46 PM PDT 24 Jul 13 06:23:49 PM PDT 24 12598288 ps
T939 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1795870825 Jul 13 06:23:33 PM PDT 24 Jul 13 06:23:34 PM PDT 24 21271485 ps
T940 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3635009789 Jul 13 06:23:55 PM PDT 24 Jul 13 06:23:57 PM PDT 24 64202808 ps
T941 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1748229468 Jul 13 06:23:47 PM PDT 24 Jul 13 06:23:53 PM PDT 24 88789884 ps
T942 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.323784051 Jul 13 06:23:46 PM PDT 24 Jul 13 06:23:49 PM PDT 24 147724008 ps
T943 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3901902117 Jul 13 06:23:45 PM PDT 24 Jul 13 06:23:47 PM PDT 24 53222546 ps
T944 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2311536243 Jul 13 06:23:47 PM PDT 24 Jul 13 06:23:51 PM PDT 24 21825329 ps
T122 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4034569659 Jul 13 06:23:41 PM PDT 24 Jul 13 06:23:44 PM PDT 24 442635016 ps
T945 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1302586907 Jul 13 06:23:41 PM PDT 24 Jul 13 06:23:43 PM PDT 24 75260639 ps
T946 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2398799349 Jul 13 06:23:49 PM PDT 24 Jul 13 06:23:52 PM PDT 24 140867118 ps
T947 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.4106749973 Jul 13 06:23:46 PM PDT 24 Jul 13 06:23:54 PM PDT 24 126908822 ps
T948 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1373949422 Jul 13 06:24:12 PM PDT 24 Jul 13 06:24:27 PM PDT 24 1356508219 ps
T949 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4097234407 Jul 13 06:23:45 PM PDT 24 Jul 13 06:23:47 PM PDT 24 620828789 ps
T950 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3178987997 Jul 13 06:23:35 PM PDT 24 Jul 13 06:23:37 PM PDT 24 26069361 ps
T951 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1772954641 Jul 13 06:23:52 PM PDT 24 Jul 13 06:23:54 PM PDT 24 22169798 ps
T952 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3755684004 Jul 13 06:23:37 PM PDT 24 Jul 13 06:23:38 PM PDT 24 67476341 ps
T953 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.242191511 Jul 13 06:23:45 PM PDT 24 Jul 13 06:23:57 PM PDT 24 1106867951 ps
T954 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2616420288 Jul 13 06:23:58 PM PDT 24 Jul 13 06:24:00 PM PDT 24 38004892 ps
T955 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1453919989 Jul 13 06:23:45 PM PDT 24 Jul 13 06:23:48 PM PDT 24 29792068 ps
T956 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3022597937 Jul 13 06:23:42 PM PDT 24 Jul 13 06:24:03 PM PDT 24 3719080648 ps
T957 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1204315677 Jul 13 06:23:49 PM PDT 24 Jul 13 06:23:54 PM PDT 24 190476799 ps
T958 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3909605099 Jul 13 06:24:10 PM PDT 24 Jul 13 06:24:33 PM PDT 24 4016800936 ps
T959 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.237048602 Jul 13 06:23:47 PM PDT 24 Jul 13 06:23:59 PM PDT 24 976666445 ps
T960 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.4178790925 Jul 13 06:24:16 PM PDT 24 Jul 13 06:24:21 PM PDT 24 113356449 ps
T167 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2664382033 Jul 13 06:23:32 PM PDT 24 Jul 13 06:23:34 PM PDT 24 16944843 ps
T123 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.263627547 Jul 13 06:24:20 PM PDT 24 Jul 13 06:24:26 PM PDT 24 465567413 ps
T961 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2229802769 Jul 13 06:24:09 PM PDT 24 Jul 13 06:24:12 PM PDT 24 23085938 ps
T962 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4178257434 Jul 13 06:23:58 PM PDT 24 Jul 13 06:24:00 PM PDT 24 53521943 ps
T109 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2076620919 Jul 13 06:23:50 PM PDT 24 Jul 13 06:23:54 PM PDT 24 784868607 ps
T963 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.336815293 Jul 13 06:24:12 PM PDT 24 Jul 13 06:24:15 PM PDT 24 47868253 ps
T964 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.672211052 Jul 13 06:23:46 PM PDT 24 Jul 13 06:23:49 PM PDT 24 67461631 ps
T125 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1468605590 Jul 13 06:24:03 PM PDT 24 Jul 13 06:24:06 PM PDT 24 446232662 ps
T965 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.94437176 Jul 13 06:24:13 PM PDT 24 Jul 13 06:24:15 PM PDT 24 25095059 ps
T966 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2338428551 Jul 13 06:23:56 PM PDT 24 Jul 13 06:23:58 PM PDT 24 18215040 ps
T967 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1912230341 Jul 13 06:23:42 PM PDT 24 Jul 13 06:23:43 PM PDT 24 26574204 ps
T968 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2511983618 Jul 13 06:24:17 PM PDT 24 Jul 13 06:24:21 PM PDT 24 48075647 ps
T969 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.352807611 Jul 13 06:23:45 PM PDT 24 Jul 13 06:23:57 PM PDT 24 2649143467 ps
T970 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.149434687 Jul 13 06:24:06 PM PDT 24 Jul 13 06:24:09 PM PDT 24 322761981 ps
T971 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.909877808 Jul 13 06:23:54 PM PDT 24 Jul 13 06:23:56 PM PDT 24 23887809 ps
T972 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1970312361 Jul 13 06:24:19 PM PDT 24 Jul 13 06:24:24 PM PDT 24 43599889 ps
T973 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1491744450 Jul 13 06:24:09 PM PDT 24 Jul 13 06:24:11 PM PDT 24 18809048 ps
T974 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3156451325 Jul 13 06:24:15 PM PDT 24 Jul 13 06:24:18 PM PDT 24 37333971 ps
T975 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1446795077 Jul 13 06:23:44 PM PDT 24 Jul 13 06:23:56 PM PDT 24 8965143596 ps
T976 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.631131692 Jul 13 06:23:39 PM PDT 24 Jul 13 06:23:42 PM PDT 24 130107465 ps
T977 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2027201246 Jul 13 06:23:47 PM PDT 24 Jul 13 06:23:51 PM PDT 24 38360158 ps
T978 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1763234366 Jul 13 06:24:09 PM PDT 24 Jul 13 06:24:14 PM PDT 24 46886586 ps
T979 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1132500993 Jul 13 06:24:01 PM PDT 24 Jul 13 06:24:03 PM PDT 24 34138052 ps
T980 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1607851719 Jul 13 06:23:50 PM PDT 24 Jul 13 06:23:52 PM PDT 24 43444702 ps
T981 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1677329076 Jul 13 06:23:52 PM PDT 24 Jul 13 06:23:53 PM PDT 24 50128385 ps
T982 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2218597105 Jul 13 06:24:15 PM PDT 24 Jul 13 06:24:20 PM PDT 24 108049859 ps
T983 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1112949147 Jul 13 06:23:42 PM PDT 24 Jul 13 06:23:47 PM PDT 24 121795573 ps
T984 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2963338625 Jul 13 06:24:11 PM PDT 24 Jul 13 06:24:14 PM PDT 24 143917295 ps
T985 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.94805792 Jul 13 06:24:16 PM PDT 24 Jul 13 06:24:20 PM PDT 24 73936171 ps
T986 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3644195691 Jul 13 06:23:59 PM PDT 24 Jul 13 06:24:01 PM PDT 24 35936307 ps
T987 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2465339177 Jul 13 06:23:52 PM PDT 24 Jul 13 06:23:56 PM PDT 24 122362118 ps
T988 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3229256048 Jul 13 06:24:03 PM PDT 24 Jul 13 06:24:05 PM PDT 24 18322979 ps
T989 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3645604877 Jul 13 06:24:10 PM PDT 24 Jul 13 06:24:12 PM PDT 24 22548415 ps
T990 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2929812191 Jul 13 06:23:48 PM PDT 24 Jul 13 06:23:51 PM PDT 24 74628635 ps
T991 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3903627637 Jul 13 06:23:56 PM PDT 24 Jul 13 06:23:58 PM PDT 24 30526608 ps
T992 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3047067744 Jul 13 06:23:44 PM PDT 24 Jul 13 06:23:46 PM PDT 24 40467787 ps
T993 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3131628950 Jul 13 06:24:06 PM PDT 24 Jul 13 06:24:10 PM PDT 24 167491026 ps
T994 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.512487095 Jul 13 06:23:45 PM PDT 24 Jul 13 06:24:00 PM PDT 24 1109687476 ps
T995 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.524132125 Jul 13 06:23:49 PM PDT 24 Jul 13 06:23:59 PM PDT 24 93105970 ps
T996 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4234390462 Jul 13 06:24:23 PM PDT 24 Jul 13 06:24:29 PM PDT 24 157124121 ps

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3945633292
Short name T12
Test name
Test status
Simulation time 6001921184 ps
CPU time 11.09 seconds
Started Jul 13 04:47:59 PM PDT 24
Finished Jul 13 04:48:11 PM PDT 24
Peak memory 225600 kb
Host smart-c5d4b8c3-7b0a-4243-8ea6-8d555c70b864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945633292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3945633292
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.2820751749
Short name T5
Test name
Test status
Simulation time 118368541731 ps
CPU time 461.34 seconds
Started Jul 13 04:47:36 PM PDT 24
Finished Jul 13 04:55:20 PM PDT 24
Peak memory 446952 kb
Host smart-206fab98-11a9-4ccb-b66d-2c3a16f53f45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2820751749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.2820751749
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3711025079
Short name T39
Test name
Test status
Simulation time 574766397 ps
CPU time 11.34 seconds
Started Jul 13 04:46:35 PM PDT 24
Finished Jul 13 04:46:48 PM PDT 24
Peak memory 225456 kb
Host smart-e5d15f4c-4a6e-4784-b833-ca77bc7459ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711025079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3711025079
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1016920503
Short name T11
Test name
Test status
Simulation time 195446348 ps
CPU time 9.41 seconds
Started Jul 13 04:46:47 PM PDT 24
Finished Jul 13 04:46:59 PM PDT 24
Peak memory 225124 kb
Host smart-13f4cf9d-dfc8-4d18-a743-f4b272a2a3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016920503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1016920503
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.970658559
Short name T99
Test name
Test status
Simulation time 19939154 ps
CPU time 1.52 seconds
Started Jul 13 06:23:54 PM PDT 24
Finished Jul 13 06:23:56 PM PDT 24
Peak memory 222396 kb
Host smart-659c7be9-1680-4525-bdf2-59fa7114285c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970658559 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.970658559
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3863049809
Short name T30
Test name
Test status
Simulation time 52202133 ps
CPU time 0.79 seconds
Started Jul 13 04:47:26 PM PDT 24
Finished Jul 13 04:47:29 PM PDT 24
Peak memory 208176 kb
Host smart-36281542-2463-4865-bb3c-c29bf28de373
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863049809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3863049809
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.4188386077
Short name T56
Test name
Test status
Simulation time 466088850 ps
CPU time 37.25 seconds
Started Jul 13 04:46:09 PM PDT 24
Finished Jul 13 04:46:46 PM PDT 24
Peak memory 281772 kb
Host smart-04b30577-1dc2-4e0e-b70f-8bb33452a312
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188386077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.4188386077
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.215619827
Short name T17
Test name
Test status
Simulation time 11719423573 ps
CPU time 180.78 seconds
Started Jul 13 04:47:24 PM PDT 24
Finished Jul 13 04:50:27 PM PDT 24
Peak memory 255632 kb
Host smart-66655751-e57f-4c3d-a809-9092f8a7bb00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215619827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.215619827
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.3460071857
Short name T211
Test name
Test status
Simulation time 40187766229 ps
CPU time 353.06 seconds
Started Jul 13 04:47:23 PM PDT 24
Finished Jul 13 04:53:18 PM PDT 24
Peak memory 371896 kb
Host smart-ebf50430-8e23-409b-aa4d-b1c92d1fc46e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3460071857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.3460071857
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1029556782
Short name T100
Test name
Test status
Simulation time 477056332 ps
CPU time 4.38 seconds
Started Jul 13 06:23:55 PM PDT 24
Finished Jul 13 06:24:00 PM PDT 24
Peak memory 217472 kb
Host smart-4612a222-30c4-4ec0-8659-cb3fb27d3ba8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029556782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1029556782
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3905439503
Short name T1
Test name
Test status
Simulation time 1121830920 ps
CPU time 25.67 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:48:28 PM PDT 24
Peak memory 217064 kb
Host smart-6d5ad0ae-e0ec-43e2-921c-7abe904835d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905439503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3905439503
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1700898705
Short name T36
Test name
Test status
Simulation time 1134831481 ps
CPU time 8.84 seconds
Started Jul 13 04:48:08 PM PDT 24
Finished Jul 13 04:48:17 PM PDT 24
Peak memory 225444 kb
Host smart-6a20c59b-cfa0-47d5-85b9-92080dc8fe00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700898705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1700898705
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.164464965
Short name T162
Test name
Test status
Simulation time 38544881 ps
CPU time 1.26 seconds
Started Jul 13 06:23:41 PM PDT 24
Finished Jul 13 06:23:43 PM PDT 24
Peak memory 217324 kb
Host smart-eed08abe-438c-4eff-a6fc-fa819d0772b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164464965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.164464965
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1690071377
Short name T120
Test name
Test status
Simulation time 87550773 ps
CPU time 3.11 seconds
Started Jul 13 06:23:26 PM PDT 24
Finished Jul 13 06:23:29 PM PDT 24
Peak memory 217952 kb
Host smart-db756dfa-9469-4d0e-a998-5a2dfc4729a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169007
1377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1690071377
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2363214185
Short name T86
Test name
Test status
Simulation time 18750828 ps
CPU time 1.2 seconds
Started Jul 13 04:47:34 PM PDT 24
Finished Jul 13 04:47:37 PM PDT 24
Peak memory 207536 kb
Host smart-d02683bb-65ae-4ccd-8d2b-e8114c902eb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363214185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2363214185
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.587043252
Short name T107
Test name
Test status
Simulation time 108404941 ps
CPU time 4.08 seconds
Started Jul 13 06:23:55 PM PDT 24
Finished Jul 13 06:24:01 PM PDT 24
Peak memory 217552 kb
Host smart-57a3a836-b8c7-4b08-ac1e-c6827f79db18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587043252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_
err.587043252
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.2962607488
Short name T48
Test name
Test status
Simulation time 198008873462 ps
CPU time 1530.42 seconds
Started Jul 13 04:45:49 PM PDT 24
Finished Jul 13 05:11:21 PM PDT 24
Peak memory 331704 kb
Host smart-c7638876-f52d-4d3d-813d-be09aa385a6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2962607488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.2962607488
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1976401177
Short name T105
Test name
Test status
Simulation time 1089881469 ps
CPU time 3.59 seconds
Started Jul 13 06:23:47 PM PDT 24
Finished Jul 13 06:23:52 PM PDT 24
Peak memory 217444 kb
Host smart-2a4a08cd-e501-4025-b378-d1a517f932aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976401177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1976401177
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.4069939314
Short name T61
Test name
Test status
Simulation time 31741337543 ps
CPU time 1150.58 seconds
Started Jul 13 04:47:12 PM PDT 24
Finished Jul 13 05:06:24 PM PDT 24
Peak memory 283336 kb
Host smart-05145298-605f-4a71-bb69-704f3f0cd6ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4069939314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.4069939314
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1658505118
Short name T108
Test name
Test status
Simulation time 339235144 ps
CPU time 3.06 seconds
Started Jul 13 06:23:41 PM PDT 24
Finished Jul 13 06:23:44 PM PDT 24
Peak memory 217432 kb
Host smart-06fd1f70-2708-48f7-90e8-47e1f76ff56c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658505118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1658505118
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2924206375
Short name T101
Test name
Test status
Simulation time 369556529 ps
CPU time 3.61 seconds
Started Jul 13 06:24:06 PM PDT 24
Finished Jul 13 06:24:10 PM PDT 24
Peak memory 222428 kb
Host smart-e74a06dd-f827-47e2-9c4c-4db6e04014a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924206375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2924206375
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.3732702165
Short name T69
Test name
Test status
Simulation time 3596052623 ps
CPU time 48.56 seconds
Started Jul 13 04:47:09 PM PDT 24
Finished Jul 13 04:47:58 PM PDT 24
Peak memory 250456 kb
Host smart-a1420fca-7958-4bad-a914-a20837ef5ba7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732702165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.3732702165
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1100645959
Short name T171
Test name
Test status
Simulation time 36038029 ps
CPU time 1.1 seconds
Started Jul 13 06:23:36 PM PDT 24
Finished Jul 13 06:23:38 PM PDT 24
Peak memory 209240 kb
Host smart-f7358d76-5799-40fd-97b8-604b9e3b6c54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100645959 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1100645959
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.103342307
Short name T13
Test name
Test status
Simulation time 11630066 ps
CPU time 0.83 seconds
Started Jul 13 04:46:23 PM PDT 24
Finished Jul 13 04:46:25 PM PDT 24
Peak memory 208176 kb
Host smart-95bb13c3-3e7e-404e-9c60-35bcf48f9e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103342307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.103342307
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3039575745
Short name T32
Test name
Test status
Simulation time 2495864314 ps
CPU time 13.3 seconds
Started Jul 13 04:45:44 PM PDT 24
Finished Jul 13 04:45:59 PM PDT 24
Peak memory 225564 kb
Host smart-eab6019c-b7af-4d40-9060-59df98639186
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039575745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3039575745
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.888742361
Short name T121
Test name
Test status
Simulation time 53085580 ps
CPU time 1.93 seconds
Started Jul 13 06:23:47 PM PDT 24
Finished Jul 13 06:23:52 PM PDT 24
Peak memory 221572 kb
Host smart-227dd55a-7e99-4acc-b178-f1f60c136ff0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888742361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.888742361
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.4241976066
Short name T177
Test name
Test status
Simulation time 22059920 ps
CPU time 0.95 seconds
Started Jul 13 04:45:48 PM PDT 24
Finished Jul 13 04:45:50 PM PDT 24
Peak memory 208248 kb
Host smart-8b840186-06b7-4e3a-971c-f6a419a4f82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241976066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.4241976066
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2900194108
Short name T180
Test name
Test status
Simulation time 173597058 ps
CPU time 0.92 seconds
Started Jul 13 04:46:10 PM PDT 24
Finished Jul 13 04:46:12 PM PDT 24
Peak memory 208584 kb
Host smart-ee516529-bbcd-4e8a-bfea-9438ec37d43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900194108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2900194108
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1220006526
Short name T15
Test name
Test status
Simulation time 1088347319 ps
CPU time 12.41 seconds
Started Jul 13 04:47:10 PM PDT 24
Finished Jul 13 04:47:23 PM PDT 24
Peak memory 225432 kb
Host smart-9f6936a7-192b-45a0-8d68-d801c593956a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220006526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1220006526
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.876004621
Short name T890
Test name
Test status
Simulation time 93263327 ps
CPU time 1.67 seconds
Started Jul 13 06:23:53 PM PDT 24
Finished Jul 13 06:23:56 PM PDT 24
Peak memory 210612 kb
Host smart-672715b1-20ae-457a-a06f-aa68d266e0ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876004621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.876004621
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.752963278
Short name T117
Test name
Test status
Simulation time 57811069 ps
CPU time 1.97 seconds
Started Jul 13 06:23:36 PM PDT 24
Finished Jul 13 06:23:38 PM PDT 24
Peak memory 212972 kb
Host smart-a6c0c046-71e9-4b53-9568-649efb5bed26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752963278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.752963278
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.182036999
Short name T115
Test name
Test status
Simulation time 841435343 ps
CPU time 3.54 seconds
Started Jul 13 06:24:16 PM PDT 24
Finished Jul 13 06:24:22 PM PDT 24
Peak memory 222208 kb
Host smart-ac78f4e7-dc9f-4d37-85ef-6991be3bd215
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182036999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.182036999
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2076620919
Short name T109
Test name
Test status
Simulation time 784868607 ps
CPU time 2.24 seconds
Started Jul 13 06:23:50 PM PDT 24
Finished Jul 13 06:23:54 PM PDT 24
Peak memory 217448 kb
Host smart-48b21d01-6ee5-4bab-bec8-02fae519ddbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076620919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2076620919
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.53545802
Short name T118
Test name
Test status
Simulation time 148433853 ps
CPU time 1.86 seconds
Started Jul 13 06:24:03 PM PDT 24
Finished Jul 13 06:24:05 PM PDT 24
Peak memory 221512 kb
Host smart-714a1dde-ebad-4ad4-82dd-736493d9a4c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53545802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_e
rr.53545802
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4034569659
Short name T122
Test name
Test status
Simulation time 442635016 ps
CPU time 2.4 seconds
Started Jul 13 06:23:41 PM PDT 24
Finished Jul 13 06:23:44 PM PDT 24
Peak memory 217468 kb
Host smart-32985fc0-078c-464c-8ae8-9ec5828fcac1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034569659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.4034569659
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1511714353
Short name T51
Test name
Test status
Simulation time 2463690333 ps
CPU time 11.74 seconds
Started Jul 13 04:45:49 PM PDT 24
Finished Jul 13 04:46:02 PM PDT 24
Peak memory 225464 kb
Host smart-327a4c86-f65c-4d1d-919c-11fc40ad241f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511714353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1511714353
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2531529164
Short name T207
Test name
Test status
Simulation time 4850342095 ps
CPU time 158.48 seconds
Started Jul 13 04:45:51 PM PDT 24
Finished Jul 13 04:48:31 PM PDT 24
Peak memory 278652 kb
Host smart-da244408-7aaa-4a56-8811-c9330da070d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531529164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2531529164
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2033676472
Short name T9
Test name
Test status
Simulation time 1926623945 ps
CPU time 12.29 seconds
Started Jul 13 04:45:48 PM PDT 24
Finished Jul 13 04:46:01 PM PDT 24
Peak memory 225412 kb
Host smart-f037e4b0-c4f8-410a-94a6-2403747d2af2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033676472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2033676472
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1592971964
Short name T903
Test name
Test status
Simulation time 379159481 ps
CPU time 2.1 seconds
Started Jul 13 06:23:34 PM PDT 24
Finished Jul 13 06:23:36 PM PDT 24
Peak memory 209180 kb
Host smart-7065b792-21a2-4677-adb0-03097e2f720d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592971964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1592971964
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4178257434
Short name T962
Test name
Test status
Simulation time 53521943 ps
CPU time 0.92 seconds
Started Jul 13 06:23:58 PM PDT 24
Finished Jul 13 06:24:00 PM PDT 24
Peak memory 209848 kb
Host smart-f5c0c375-bc68-4122-9dd8-1ad2ca66985f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178257434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.4178257434
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3635009789
Short name T940
Test name
Test status
Simulation time 64202808 ps
CPU time 1.48 seconds
Started Jul 13 06:23:55 PM PDT 24
Finished Jul 13 06:23:57 PM PDT 24
Peak memory 224740 kb
Host smart-38e5a829-582b-4a68-8acb-d2f162102834
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635009789 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3635009789
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2664382033
Short name T167
Test name
Test status
Simulation time 16944843 ps
CPU time 0.95 seconds
Started Jul 13 06:23:32 PM PDT 24
Finished Jul 13 06:23:34 PM PDT 24
Peak memory 208900 kb
Host smart-874912e1-cc92-4d2b-8555-cd4cb4ba9845
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664382033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2664382033
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.625797834
Short name T931
Test name
Test status
Simulation time 16412959 ps
CPU time 1.1 seconds
Started Jul 13 06:23:47 PM PDT 24
Finished Jul 13 06:23:50 PM PDT 24
Peak memory 209092 kb
Host smart-ae087c22-c544-4baf-9c2c-b22316f160b0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625797834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.625797834
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3497425540
Short name T129
Test name
Test status
Simulation time 299943229 ps
CPU time 3.6 seconds
Started Jul 13 06:23:46 PM PDT 24
Finished Jul 13 06:23:51 PM PDT 24
Peak memory 209128 kb
Host smart-38f6b98c-882f-4032-bd38-9b3f13de4563
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497425540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3497425540
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3022597937
Short name T956
Test name
Test status
Simulation time 3719080648 ps
CPU time 19.94 seconds
Started Jul 13 06:23:42 PM PDT 24
Finished Jul 13 06:24:03 PM PDT 24
Peak memory 208956 kb
Host smart-693b7548-71af-4616-a55d-bb1a02985516
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022597937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.3022597937
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.323784051
Short name T942
Test name
Test status
Simulation time 147724008 ps
CPU time 1.1 seconds
Started Jul 13 06:23:46 PM PDT 24
Finished Jul 13 06:23:49 PM PDT 24
Peak memory 217240 kb
Host smart-762302ae-6f02-4d6d-80a0-3f1abb0b85cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323784051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.323784051
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3178987997
Short name T950
Test name
Test status
Simulation time 26069361 ps
CPU time 1.39 seconds
Started Jul 13 06:23:35 PM PDT 24
Finished Jul 13 06:23:37 PM PDT 24
Peak memory 209256 kb
Host smart-a19e6109-c61c-4644-a8c6-2751b9ce3afe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178987997 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3178987997
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1795870825
Short name T939
Test name
Test status
Simulation time 21271485 ps
CPU time 1.32 seconds
Started Jul 13 06:23:33 PM PDT 24
Finished Jul 13 06:23:34 PM PDT 24
Peak memory 209608 kb
Host smart-bc77ea31-85a0-4647-b3e8-40fafca5cd8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795870825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1795870825
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1031052402
Short name T97
Test name
Test status
Simulation time 43650657 ps
CPU time 2.69 seconds
Started Jul 13 06:23:38 PM PDT 24
Finished Jul 13 06:23:41 PM PDT 24
Peak memory 217432 kb
Host smart-98895d41-c050-4257-850c-8d097061f6e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031052402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1031052402
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4264269680
Short name T164
Test name
Test status
Simulation time 60718083 ps
CPU time 1.08 seconds
Started Jul 13 06:23:44 PM PDT 24
Finished Jul 13 06:23:46 PM PDT 24
Peak memory 209252 kb
Host smart-6e43c868-1edd-4aad-bd00-5adb0e82e4d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264269680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.4264269680
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1062091300
Short name T920
Test name
Test status
Simulation time 133949930 ps
CPU time 1.1 seconds
Started Jul 13 06:23:57 PM PDT 24
Finished Jul 13 06:23:59 PM PDT 24
Peak memory 209004 kb
Host smart-fde2f71d-15c4-44b8-a21f-68d2844eb838
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062091300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1062091300
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1226151587
Short name T163
Test name
Test status
Simulation time 33319251 ps
CPU time 1.28 seconds
Started Jul 13 06:23:47 PM PDT 24
Finished Jul 13 06:23:50 PM PDT 24
Peak memory 211656 kb
Host smart-61f6ab34-27f9-449e-b204-4eec843e4b94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226151587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1226151587
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.973347274
Short name T889
Test name
Test status
Simulation time 32278219 ps
CPU time 1.37 seconds
Started Jul 13 06:23:45 PM PDT 24
Finished Jul 13 06:23:47 PM PDT 24
Peak memory 221560 kb
Host smart-61e96492-f16e-4781-9388-c77cffd68945
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973347274 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.973347274
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.746760529
Short name T138
Test name
Test status
Simulation time 13756174 ps
CPU time 0.83 seconds
Started Jul 13 06:24:05 PM PDT 24
Finished Jul 13 06:24:06 PM PDT 24
Peak memory 209080 kb
Host smart-e8bbc2bf-abc4-4ceb-9902-5aa3278ac6c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746760529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.746760529
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2465339177
Short name T987
Test name
Test status
Simulation time 122362118 ps
CPU time 3.13 seconds
Started Jul 13 06:23:52 PM PDT 24
Finished Jul 13 06:23:56 PM PDT 24
Peak memory 208656 kb
Host smart-0258d7df-968d-42ba-8fbb-97ff5f7424c0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465339177 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2465339177
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3530224051
Short name T910
Test name
Test status
Simulation time 516604776 ps
CPU time 6.04 seconds
Started Jul 13 06:24:17 PM PDT 24
Finished Jul 13 06:24:27 PM PDT 24
Peak memory 208980 kb
Host smart-c7a1d096-add9-467e-a834-76af3cb03e02
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530224051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3530224051
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3611101009
Short name T874
Test name
Test status
Simulation time 1519782135 ps
CPU time 34.48 seconds
Started Jul 13 06:23:39 PM PDT 24
Finished Jul 13 06:24:14 PM PDT 24
Peak memory 209140 kb
Host smart-5944161e-d556-4729-8930-384c85caf52e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611101009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3611101009
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.451248594
Short name T886
Test name
Test status
Simulation time 87433714 ps
CPU time 1.8 seconds
Started Jul 13 06:23:52 PM PDT 24
Finished Jul 13 06:23:55 PM PDT 24
Peak memory 217300 kb
Host smart-7d44d9d5-8a7a-4f70-a03a-0bf80faed2c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451248594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.451248594
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4097234407
Short name T949
Test name
Test status
Simulation time 620828789 ps
CPU time 2.24 seconds
Started Jul 13 06:23:45 PM PDT 24
Finished Jul 13 06:23:47 PM PDT 24
Peak memory 217628 kb
Host smart-5381370e-a575-4deb-b5fb-b055b429522c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409723
4407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4097234407
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1291910524
Short name T904
Test name
Test status
Simulation time 189501765 ps
CPU time 1.21 seconds
Started Jul 13 06:23:56 PM PDT 24
Finished Jul 13 06:23:58 PM PDT 24
Peak memory 209068 kb
Host smart-ebd75a6f-6ec6-4394-b867-cdbe96ccc95f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291910524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1291910524
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1912230341
Short name T967
Test name
Test status
Simulation time 26574204 ps
CPU time 1.11 seconds
Started Jul 13 06:23:42 PM PDT 24
Finished Jul 13 06:23:43 PM PDT 24
Peak memory 209220 kb
Host smart-9f191182-7fd3-4b45-b050-34cc33cf953c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912230341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1912230341
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.4106749973
Short name T947
Test name
Test status
Simulation time 126908822 ps
CPU time 2.33 seconds
Started Jul 13 06:23:46 PM PDT 24
Finished Jul 13 06:23:54 PM PDT 24
Peak memory 217444 kb
Host smart-90509459-e90b-4e50-95cb-ab70bfe7975b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106749973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.4106749973
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2592166226
Short name T124
Test name
Test status
Simulation time 243685935 ps
CPU time 2.15 seconds
Started Jul 13 06:23:46 PM PDT 24
Finished Jul 13 06:23:51 PM PDT 24
Peak memory 222036 kb
Host smart-2e044f8e-668c-46bf-b605-43396bb6dee7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592166226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2592166226
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2145124633
Short name T876
Test name
Test status
Simulation time 301547894 ps
CPU time 1.17 seconds
Started Jul 13 06:24:17 PM PDT 24
Finished Jul 13 06:24:21 PM PDT 24
Peak memory 219436 kb
Host smart-d9be0356-8ee3-4994-b013-52a62ddcce0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145124633 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2145124633
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2511983618
Short name T968
Test name
Test status
Simulation time 48075647 ps
CPU time 0.88 seconds
Started Jul 13 06:24:17 PM PDT 24
Finished Jul 13 06:24:21 PM PDT 24
Peak memory 209156 kb
Host smart-6009043a-e2fe-477f-8ce6-67d3168b8ac5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511983618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2511983618
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1637225991
Short name T925
Test name
Test status
Simulation time 25334748 ps
CPU time 1.4 seconds
Started Jul 13 06:24:07 PM PDT 24
Finished Jul 13 06:24:08 PM PDT 24
Peak memory 209244 kb
Host smart-e292fb78-186f-47b4-bb62-b9f8b8f47a1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637225991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.1637225991
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.40925617
Short name T909
Test name
Test status
Simulation time 49409202 ps
CPU time 3.31 seconds
Started Jul 13 06:24:05 PM PDT 24
Finished Jul 13 06:24:08 PM PDT 24
Peak memory 217476 kb
Host smart-0cd20ffe-1689-4d18-9512-9d11f4f8d8fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40925617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.40925617
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.263627547
Short name T123
Test name
Test status
Simulation time 465567413 ps
CPU time 3 seconds
Started Jul 13 06:24:20 PM PDT 24
Finished Jul 13 06:24:26 PM PDT 24
Peak memory 217396 kb
Host smart-5bd79988-e6f0-4aba-8975-d6e517396882
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263627547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.263627547
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3793048958
Short name T927
Test name
Test status
Simulation time 47723452 ps
CPU time 1.78 seconds
Started Jul 13 06:24:12 PM PDT 24
Finished Jul 13 06:24:14 PM PDT 24
Peak memory 219012 kb
Host smart-1bf4f73e-bbea-4281-a678-54cb23f780c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793048958 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3793048958
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3229256048
Short name T988
Test name
Test status
Simulation time 18322979 ps
CPU time 0.89 seconds
Started Jul 13 06:24:03 PM PDT 24
Finished Jul 13 06:24:05 PM PDT 24
Peak memory 209192 kb
Host smart-77ffa212-69ba-473d-b7b3-140157d0ec13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229256048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3229256048
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1491744450
Short name T973
Test name
Test status
Simulation time 18809048 ps
CPU time 1.41 seconds
Started Jul 13 06:24:09 PM PDT 24
Finished Jul 13 06:24:11 PM PDT 24
Peak memory 217572 kb
Host smart-90fcedda-7467-4ab2-9160-5bfaeb41e510
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491744450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1491744450
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4234390462
Short name T996
Test name
Test status
Simulation time 157124121 ps
CPU time 3.62 seconds
Started Jul 13 06:24:23 PM PDT 24
Finished Jul 13 06:24:29 PM PDT 24
Peak memory 217396 kb
Host smart-a6f610ac-20fb-4935-864a-5e9474d88fcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234390462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.4234390462
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3206815749
Short name T150
Test name
Test status
Simulation time 29731371 ps
CPU time 1.7 seconds
Started Jul 13 06:24:07 PM PDT 24
Finished Jul 13 06:24:09 PM PDT 24
Peak memory 219608 kb
Host smart-91f2019b-9d82-47ac-832c-8a6639fecdd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206815749 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3206815749
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.801971890
Short name T917
Test name
Test status
Simulation time 33579510 ps
CPU time 1.11 seconds
Started Jul 13 06:23:47 PM PDT 24
Finished Jul 13 06:23:50 PM PDT 24
Peak memory 208996 kb
Host smart-465985e1-1f60-4e59-9512-035a00bb08dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801971890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.801971890
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1869744174
Short name T106
Test name
Test status
Simulation time 46492630 ps
CPU time 1.32 seconds
Started Jul 13 06:23:43 PM PDT 24
Finished Jul 13 06:23:45 PM PDT 24
Peak memory 209244 kb
Host smart-fffdbb68-fb72-47c3-8722-347e1ca7b4a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869744174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1869744174
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2781906110
Short name T898
Test name
Test status
Simulation time 107965440 ps
CPU time 4.55 seconds
Started Jul 13 06:23:46 PM PDT 24
Finished Jul 13 06:23:53 PM PDT 24
Peak memory 217520 kb
Host smart-50da642a-5590-4503-a88a-7a054fa512be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781906110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2781906110
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2398799349
Short name T946
Test name
Test status
Simulation time 140867118 ps
CPU time 1.55 seconds
Started Jul 13 06:23:49 PM PDT 24
Finished Jul 13 06:23:52 PM PDT 24
Peak memory 217604 kb
Host smart-c518f96f-a71b-45b4-b9ec-94c334b0aa0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398799349 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2398799349
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2273657704
Short name T168
Test name
Test status
Simulation time 19613186 ps
CPU time 0.93 seconds
Started Jul 13 06:24:14 PM PDT 24
Finished Jul 13 06:24:16 PM PDT 24
Peak memory 209176 kb
Host smart-0d5cc7d0-17ca-4395-b48a-d851a841d04b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273657704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2273657704
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4089786372
Short name T921
Test name
Test status
Simulation time 89938023 ps
CPU time 1.5 seconds
Started Jul 13 06:24:02 PM PDT 24
Finished Jul 13 06:24:04 PM PDT 24
Peak memory 217520 kb
Host smart-ef17e7de-efbe-459a-8c44-d85a3dce4874
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089786372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.4089786372
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3131628950
Short name T993
Test name
Test status
Simulation time 167491026 ps
CPU time 2.93 seconds
Started Jul 13 06:24:06 PM PDT 24
Finished Jul 13 06:24:10 PM PDT 24
Peak memory 217452 kb
Host smart-5950aca4-9ac7-4abf-8538-c72cb7c9f945
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131628950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3131628950
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.4178790925
Short name T960
Test name
Test status
Simulation time 113356449 ps
CPU time 2.54 seconds
Started Jul 13 06:24:16 PM PDT 24
Finished Jul 13 06:24:21 PM PDT 24
Peak memory 217476 kb
Host smart-b5c5eb73-0f5f-4ed0-b494-36e6e5d87db7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178790925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.4178790925
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1453919989
Short name T955
Test name
Test status
Simulation time 29792068 ps
CPU time 1.04 seconds
Started Jul 13 06:23:45 PM PDT 24
Finished Jul 13 06:23:48 PM PDT 24
Peak memory 219812 kb
Host smart-df307d54-91c7-4926-81dc-0fd7f10028e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453919989 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1453919989
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.352798248
Short name T936
Test name
Test status
Simulation time 44085200 ps
CPU time 0.83 seconds
Started Jul 13 06:23:45 PM PDT 24
Finished Jul 13 06:23:47 PM PDT 24
Peak memory 209172 kb
Host smart-c0597a33-0352-4b64-9a4e-91502e0b987e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352798248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.352798248
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2044751725
Short name T900
Test name
Test status
Simulation time 50309133 ps
CPU time 1.14 seconds
Started Jul 13 06:24:00 PM PDT 24
Finished Jul 13 06:24:02 PM PDT 24
Peak memory 209244 kb
Host smart-66a586b2-6458-491c-a180-f02d1619cd5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044751725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2044751725
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2408970967
Short name T96
Test name
Test status
Simulation time 117840435 ps
CPU time 2.11 seconds
Started Jul 13 06:23:51 PM PDT 24
Finished Jul 13 06:23:54 PM PDT 24
Peak memory 218504 kb
Host smart-540e5cc3-feda-4cfa-bb48-542f923c47c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408970967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2408970967
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2970474423
Short name T111
Test name
Test status
Simulation time 30049762 ps
CPU time 1.71 seconds
Started Jul 13 06:23:47 PM PDT 24
Finished Jul 13 06:23:51 PM PDT 24
Peak memory 217516 kb
Host smart-563cac7f-a374-4a84-aeec-5198e0f3ef55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970474423 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2970474423
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3603590255
Short name T166
Test name
Test status
Simulation time 43150389 ps
CPU time 0.96 seconds
Started Jul 13 06:23:52 PM PDT 24
Finished Jul 13 06:23:54 PM PDT 24
Peak memory 209168 kb
Host smart-e6239d5c-cb95-468c-8298-a2d49f0aca08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603590255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3603590255
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.94437176
Short name T965
Test name
Test status
Simulation time 25095059 ps
CPU time 1.09 seconds
Started Jul 13 06:24:13 PM PDT 24
Finished Jul 13 06:24:15 PM PDT 24
Peak memory 217476 kb
Host smart-d3b8c4ad-099f-4416-9c6e-bbbc13b180ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94437176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
same_csr_outstanding.94437176
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1132500993
Short name T979
Test name
Test status
Simulation time 34138052 ps
CPU time 1.62 seconds
Started Jul 13 06:24:01 PM PDT 24
Finished Jul 13 06:24:03 PM PDT 24
Peak memory 218484 kb
Host smart-eab5c34d-e239-44b5-a43e-f64f3bc03928
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132500993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1132500993
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2758390215
Short name T937
Test name
Test status
Simulation time 24012843 ps
CPU time 1.77 seconds
Started Jul 13 06:24:10 PM PDT 24
Finished Jul 13 06:24:12 PM PDT 24
Peak memory 217628 kb
Host smart-1b99fb22-1608-4e25-b2d5-61350266e696
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758390215 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2758390215
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.407898085
Short name T160
Test name
Test status
Simulation time 159207965 ps
CPU time 0.88 seconds
Started Jul 13 06:24:17 PM PDT 24
Finished Jul 13 06:24:22 PM PDT 24
Peak memory 209172 kb
Host smart-c243565c-22dc-4d25-9641-623e6153ae0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407898085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.407898085
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.336815293
Short name T963
Test name
Test status
Simulation time 47868253 ps
CPU time 2.08 seconds
Started Jul 13 06:24:12 PM PDT 24
Finished Jul 13 06:24:15 PM PDT 24
Peak memory 217348 kb
Host smart-144563fb-5430-4aab-a58d-e495e0e8bc14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336815293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_same_csr_outstanding.336815293
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2229802769
Short name T961
Test name
Test status
Simulation time 23085938 ps
CPU time 1.89 seconds
Started Jul 13 06:24:09 PM PDT 24
Finished Jul 13 06:24:12 PM PDT 24
Peak memory 217456 kb
Host smart-7cf8c896-e642-4b15-a9dd-5c810d776c1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229802769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2229802769
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1132258394
Short name T98
Test name
Test status
Simulation time 561034692 ps
CPU time 2.06 seconds
Started Jul 13 06:24:19 PM PDT 24
Finished Jul 13 06:24:25 PM PDT 24
Peak memory 217448 kb
Host smart-700174ab-e474-4564-8ef4-20e01c9f903a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132258394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1132258394
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2815343155
Short name T149
Test name
Test status
Simulation time 17023855 ps
CPU time 1.23 seconds
Started Jul 13 06:24:06 PM PDT 24
Finished Jul 13 06:24:07 PM PDT 24
Peak memory 217444 kb
Host smart-f453ff7b-5c3e-4ebd-b094-ec5629a5f076
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815343155 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2815343155
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3785031981
Short name T159
Test name
Test status
Simulation time 33902561 ps
CPU time 0.85 seconds
Started Jul 13 06:25:59 PM PDT 24
Finished Jul 13 06:26:00 PM PDT 24
Peak memory 209436 kb
Host smart-b7312b90-5b99-48db-abe0-1b58cb74a5c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785031981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3785031981
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3023962293
Short name T175
Test name
Test status
Simulation time 15047407 ps
CPU time 1.11 seconds
Started Jul 13 06:23:53 PM PDT 24
Finished Jul 13 06:23:55 PM PDT 24
Peak memory 209088 kb
Host smart-5895abe7-73c2-4f33-9129-267bc1cce0f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023962293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3023962293
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2963338625
Short name T984
Test name
Test status
Simulation time 143917295 ps
CPU time 1.89 seconds
Started Jul 13 06:24:11 PM PDT 24
Finished Jul 13 06:24:14 PM PDT 24
Peak memory 217312 kb
Host smart-26876266-8df0-4666-8c08-822dd1d307e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963338625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2963338625
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3644195691
Short name T986
Test name
Test status
Simulation time 35936307 ps
CPU time 1.46 seconds
Started Jul 13 06:23:59 PM PDT 24
Finished Jul 13 06:24:01 PM PDT 24
Peak memory 219660 kb
Host smart-e660fc40-fb8f-45f1-b028-c8215ef14624
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644195691 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3644195691
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1492842802
Short name T157
Test name
Test status
Simulation time 40458913 ps
CPU time 0.91 seconds
Started Jul 13 06:23:49 PM PDT 24
Finished Jul 13 06:23:52 PM PDT 24
Peak memory 209184 kb
Host smart-681dc837-b784-4359-8f9d-3cefeb441c61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492842802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1492842802
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.909877808
Short name T971
Test name
Test status
Simulation time 23887809 ps
CPU time 1.58 seconds
Started Jul 13 06:23:54 PM PDT 24
Finished Jul 13 06:23:56 PM PDT 24
Peak memory 217476 kb
Host smart-4661b064-fac3-4fcd-83dc-30b021112d1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909877808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.909877808
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.89200547
Short name T113
Test name
Test status
Simulation time 452775975 ps
CPU time 3.32 seconds
Started Jul 13 06:23:54 PM PDT 24
Finished Jul 13 06:23:58 PM PDT 24
Peak memory 217356 kb
Host smart-831fc2af-2fc0-418f-992e-337b29599540
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89200547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.89200547
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3156451325
Short name T974
Test name
Test status
Simulation time 37333971 ps
CPU time 1.16 seconds
Started Jul 13 06:24:15 PM PDT 24
Finished Jul 13 06:24:18 PM PDT 24
Peak memory 217492 kb
Host smart-9bb415ea-9beb-4d38-8292-a6c6f7baaff4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156451325 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3156451325
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2338428551
Short name T966
Test name
Test status
Simulation time 18215040 ps
CPU time 0.95 seconds
Started Jul 13 06:23:56 PM PDT 24
Finished Jul 13 06:23:58 PM PDT 24
Peak memory 217184 kb
Host smart-4ef30407-ef52-40ff-96ad-68cc9137517d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338428551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2338428551
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2616420288
Short name T954
Test name
Test status
Simulation time 38004892 ps
CPU time 1.25 seconds
Started Jul 13 06:23:58 PM PDT 24
Finished Jul 13 06:24:00 PM PDT 24
Peak memory 209228 kb
Host smart-81ace729-7217-4be5-9f49-5d83abc9cd9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616420288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2616420288
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.204695853
Short name T894
Test name
Test status
Simulation time 171184359 ps
CPU time 2.75 seconds
Started Jul 13 06:23:46 PM PDT 24
Finished Jul 13 06:23:51 PM PDT 24
Peak memory 217400 kb
Host smart-1b3992fe-628b-45b1-b15a-5953a744f936
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204695853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.204695853
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.470541354
Short name T114
Test name
Test status
Simulation time 105912449 ps
CPU time 1.92 seconds
Started Jul 13 06:23:57 PM PDT 24
Finished Jul 13 06:24:05 PM PDT 24
Peak memory 221916 kb
Host smart-c51cbdbf-b8ec-4fa1-8d6a-97b0dc185ad5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470541354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.470541354
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1232750630
Short name T884
Test name
Test status
Simulation time 24596808 ps
CPU time 1.08 seconds
Started Jul 13 06:24:17 PM PDT 24
Finished Jul 13 06:24:20 PM PDT 24
Peak memory 209228 kb
Host smart-d3bb67d0-758f-4ab1-99c5-54f4d405f4e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232750630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1232750630
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3901902117
Short name T943
Test name
Test status
Simulation time 53222546 ps
CPU time 1.44 seconds
Started Jul 13 06:23:45 PM PDT 24
Finished Jul 13 06:23:47 PM PDT 24
Peak memory 208980 kb
Host smart-0d5acf23-f713-49b5-8ad1-3fdb3e8fa6f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901902117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3901902117
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3645604877
Short name T989
Test name
Test status
Simulation time 22548415 ps
CPU time 1.09 seconds
Started Jul 13 06:24:10 PM PDT 24
Finished Jul 13 06:24:12 PM PDT 24
Peak memory 210800 kb
Host smart-8724ff6c-8cc4-40e7-bb45-6ed161d9d812
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645604877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3645604877
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.319667957
Short name T148
Test name
Test status
Simulation time 28832755 ps
CPU time 1.29 seconds
Started Jul 13 06:23:39 PM PDT 24
Finished Jul 13 06:23:40 PM PDT 24
Peak memory 221584 kb
Host smart-ebaa3f2c-cfbd-441a-90ee-bde46ce42eba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319667957 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.319667957
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1634702304
Short name T915
Test name
Test status
Simulation time 45008518 ps
CPU time 0.96 seconds
Started Jul 13 06:23:39 PM PDT 24
Finished Jul 13 06:23:40 PM PDT 24
Peak memory 209244 kb
Host smart-24a60b07-b0a4-4191-b6ba-b93339ea70fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634702304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1634702304
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1692621213
Short name T926
Test name
Test status
Simulation time 407292542 ps
CPU time 1.89 seconds
Started Jul 13 06:23:34 PM PDT 24
Finished Jul 13 06:23:36 PM PDT 24
Peak memory 208560 kb
Host smart-0525831a-4ec9-420c-b923-ac7f68462c15
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692621213 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1692621213
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3548052032
Short name T914
Test name
Test status
Simulation time 745868888 ps
CPU time 9.7 seconds
Started Jul 13 06:24:21 PM PDT 24
Finished Jul 13 06:24:34 PM PDT 24
Peak memory 209084 kb
Host smart-95648199-295b-48a6-9d54-8b610dcaa98b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548052032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3548052032
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.352807611
Short name T969
Test name
Test status
Simulation time 2649143467 ps
CPU time 10.33 seconds
Started Jul 13 06:23:45 PM PDT 24
Finished Jul 13 06:23:57 PM PDT 24
Peak memory 209000 kb
Host smart-f5c9f295-44fb-4f10-9f2b-d5207f091436
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352807611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.352807611
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.631131692
Short name T976
Test name
Test status
Simulation time 130107465 ps
CPU time 1.9 seconds
Started Jul 13 06:23:39 PM PDT 24
Finished Jul 13 06:23:42 PM PDT 24
Peak memory 210580 kb
Host smart-fc0f1e44-bae4-442d-b857-e940b1d68dac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631131692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.631131692
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2175760721
Short name T882
Test name
Test status
Simulation time 316876407 ps
CPU time 3.76 seconds
Started Jul 13 06:23:55 PM PDT 24
Finished Jul 13 06:24:00 PM PDT 24
Peak memory 217484 kb
Host smart-debedfaf-b3d3-413a-8170-77901a9485fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217576
0721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2175760721
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1302586907
Short name T945
Test name
Test status
Simulation time 75260639 ps
CPU time 1.5 seconds
Started Jul 13 06:23:41 PM PDT 24
Finished Jul 13 06:23:43 PM PDT 24
Peak memory 209108 kb
Host smart-bfbf3960-4322-470c-9c0c-3f32c5088070
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302586907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1302586907
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4246925907
Short name T932
Test name
Test status
Simulation time 149593045 ps
CPU time 1.68 seconds
Started Jul 13 06:23:59 PM PDT 24
Finished Jul 13 06:24:01 PM PDT 24
Peak memory 209152 kb
Host smart-c747a746-699c-4f30-a8bb-cb030bbb88e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246925907 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.4246925907
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2311536243
Short name T944
Test name
Test status
Simulation time 21825329 ps
CPU time 1.25 seconds
Started Jul 13 06:23:47 PM PDT 24
Finished Jul 13 06:23:51 PM PDT 24
Peak memory 217424 kb
Host smart-166d1345-8fc4-456b-a498-4a73046b034b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311536243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2311536243
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.859466648
Short name T119
Test name
Test status
Simulation time 323495104 ps
CPU time 3.22 seconds
Started Jul 13 06:24:00 PM PDT 24
Finished Jul 13 06:24:04 PM PDT 24
Peak memory 217444 kb
Host smart-ab7bb369-928c-4859-8202-9957aa42ea14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859466648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.859466648
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3725728712
Short name T156
Test name
Test status
Simulation time 46390574 ps
CPU time 1.03 seconds
Started Jul 13 06:23:46 PM PDT 24
Finished Jul 13 06:23:50 PM PDT 24
Peak memory 208892 kb
Host smart-3492e077-a07e-4530-95bd-8c8acc7a7ef5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725728712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3725728712
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3834459109
Short name T934
Test name
Test status
Simulation time 73161933 ps
CPU time 1.12 seconds
Started Jul 13 06:23:46 PM PDT 24
Finished Jul 13 06:23:49 PM PDT 24
Peak memory 209180 kb
Host smart-209b8a40-66ed-4f72-911f-d0b83a5f3d30
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834459109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3834459109
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3895039393
Short name T158
Test name
Test status
Simulation time 30728706 ps
CPU time 1.1 seconds
Started Jul 13 06:23:58 PM PDT 24
Finished Jul 13 06:24:00 PM PDT 24
Peak memory 209660 kb
Host smart-18e13f38-6cc6-4c07-b116-cd5f6d9b7fbb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895039393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3895039393
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2648082311
Short name T906
Test name
Test status
Simulation time 238414448 ps
CPU time 1.24 seconds
Started Jul 13 06:23:44 PM PDT 24
Finished Jul 13 06:23:46 PM PDT 24
Peak memory 217660 kb
Host smart-bf35b87f-6a3a-44f0-b0fa-d9dd4c5b7498
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648082311 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2648082311
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2352686248
Short name T938
Test name
Test status
Simulation time 12598288 ps
CPU time 0.81 seconds
Started Jul 13 06:23:46 PM PDT 24
Finished Jul 13 06:23:49 PM PDT 24
Peak memory 209116 kb
Host smart-a27726d5-7c22-41bb-974e-7f521ae7ef96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352686248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2352686248
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3601079577
Short name T875
Test name
Test status
Simulation time 26800810 ps
CPU time 0.96 seconds
Started Jul 13 06:24:19 PM PDT 24
Finished Jul 13 06:24:23 PM PDT 24
Peak memory 208952 kb
Host smart-f6b04227-e69c-4b75-bc12-34052151e255
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601079577 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3601079577
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.512487095
Short name T994
Test name
Test status
Simulation time 1109687476 ps
CPU time 13.54 seconds
Started Jul 13 06:23:45 PM PDT 24
Finished Jul 13 06:24:00 PM PDT 24
Peak memory 217060 kb
Host smart-c6d95082-795d-4cdc-a781-ca473b8f7ffa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512487095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.512487095
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2424590954
Short name T893
Test name
Test status
Simulation time 2342181260 ps
CPU time 11.59 seconds
Started Jul 13 06:23:45 PM PDT 24
Finished Jul 13 06:23:58 PM PDT 24
Peak memory 209324 kb
Host smart-c7aa2aa3-c95f-4d88-b9bd-56c52393e6d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424590954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2424590954
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.847633518
Short name T880
Test name
Test status
Simulation time 78239880 ps
CPU time 1.53 seconds
Started Jul 13 06:23:42 PM PDT 24
Finished Jul 13 06:23:44 PM PDT 24
Peak memory 210600 kb
Host smart-c3411bb5-4314-4e7e-80fc-7547f9182ca2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847633518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.847633518
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1112949147
Short name T983
Test name
Test status
Simulation time 121795573 ps
CPU time 3.91 seconds
Started Jul 13 06:23:42 PM PDT 24
Finished Jul 13 06:23:47 PM PDT 24
Peak memory 217648 kb
Host smart-ae7d8c2a-2eb2-4876-8515-276f99a65bfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111294
9147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1112949147
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2960713565
Short name T908
Test name
Test status
Simulation time 380129076 ps
CPU time 1.19 seconds
Started Jul 13 06:24:17 PM PDT 24
Finished Jul 13 06:24:20 PM PDT 24
Peak memory 209184 kb
Host smart-ef95ff6b-dab0-41a6-bde9-ea5562dcee6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960713565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2960713565
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3211256227
Short name T174
Test name
Test status
Simulation time 55199024 ps
CPU time 1.18 seconds
Started Jul 13 06:23:52 PM PDT 24
Finished Jul 13 06:23:54 PM PDT 24
Peak memory 209360 kb
Host smart-9a8406a3-049a-454e-b372-2d5fe0c31cd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211256227 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3211256227
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1836277585
Short name T895
Test name
Test status
Simulation time 81053272 ps
CPU time 1.72 seconds
Started Jul 13 06:23:40 PM PDT 24
Finished Jul 13 06:23:42 PM PDT 24
Peak memory 209236 kb
Host smart-04a7a0a8-b7c6-4d0b-bdc4-037a3c49a1bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836277585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1836277585
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1763234366
Short name T978
Test name
Test status
Simulation time 46886586 ps
CPU time 3.46 seconds
Started Jul 13 06:24:09 PM PDT 24
Finished Jul 13 06:24:14 PM PDT 24
Peak memory 217808 kb
Host smart-3d9ad6f6-b341-4fdb-bffc-2c74cb771559
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763234366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1763234366
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2918656326
Short name T896
Test name
Test status
Simulation time 119004232 ps
CPU time 2.69 seconds
Started Jul 13 06:23:50 PM PDT 24
Finished Jul 13 06:23:54 PM PDT 24
Peak memory 217468 kb
Host smart-21ac207b-0458-4dae-9a93-2408d80e396f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918656326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2918656326
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3338356039
Short name T877
Test name
Test status
Simulation time 200210934 ps
CPU time 1.33 seconds
Started Jul 13 06:23:39 PM PDT 24
Finished Jul 13 06:23:41 PM PDT 24
Peak memory 209328 kb
Host smart-dc39dc9a-1cb6-42c0-8b86-c22e46a41db8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338356039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.3338356039
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.960872265
Short name T933
Test name
Test status
Simulation time 32647183 ps
CPU time 1.17 seconds
Started Jul 13 06:23:45 PM PDT 24
Finished Jul 13 06:23:47 PM PDT 24
Peak memory 217056 kb
Host smart-126356cf-7cd4-494a-b4a9-b8f158a10932
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960872265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.960872265
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1643857917
Short name T127
Test name
Test status
Simulation time 49657383 ps
CPU time 1.06 seconds
Started Jul 13 06:23:39 PM PDT 24
Finished Jul 13 06:23:41 PM PDT 24
Peak memory 209788 kb
Host smart-7b50afe6-5c32-4b52-9184-ed8e25d712e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643857917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1643857917
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1607851719
Short name T980
Test name
Test status
Simulation time 43444702 ps
CPU time 1.17 seconds
Started Jul 13 06:23:50 PM PDT 24
Finished Jul 13 06:23:52 PM PDT 24
Peak memory 217448 kb
Host smart-34a0b174-07bf-4172-a4d0-4faa50aa5a51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607851719 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1607851719
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1677329076
Short name T981
Test name
Test status
Simulation time 50128385 ps
CPU time 0.85 seconds
Started Jul 13 06:23:52 PM PDT 24
Finished Jul 13 06:23:53 PM PDT 24
Peak memory 209180 kb
Host smart-ad722134-aa63-4184-ad62-a3a12c6a5f8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677329076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1677329076
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3548128202
Short name T883
Test name
Test status
Simulation time 102306998 ps
CPU time 1.73 seconds
Started Jul 13 06:23:46 PM PDT 24
Finished Jul 13 06:23:49 PM PDT 24
Peak memory 208624 kb
Host smart-4bb9f5dc-6213-49c6-9597-87ccee4b88e8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548128202 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3548128202
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3613687135
Short name T905
Test name
Test status
Simulation time 662828089 ps
CPU time 7.78 seconds
Started Jul 13 06:23:39 PM PDT 24
Finished Jul 13 06:23:47 PM PDT 24
Peak memory 209180 kb
Host smart-ba775f33-31ac-495f-8b6d-f991ecf65b48
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613687135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3613687135
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1371269089
Short name T891
Test name
Test status
Simulation time 1453831602 ps
CPU time 16.64 seconds
Started Jul 13 06:23:47 PM PDT 24
Finished Jul 13 06:24:07 PM PDT 24
Peak memory 217044 kb
Host smart-cd643f38-68cc-4d06-ac55-aabab7c3f9bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371269089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1371269089
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2830688220
Short name T888
Test name
Test status
Simulation time 439629339 ps
CPU time 2.03 seconds
Started Jul 13 06:23:52 PM PDT 24
Finished Jul 13 06:23:55 PM PDT 24
Peak memory 210836 kb
Host smart-611c3db9-228c-4b75-9547-d31832e790ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830688220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2830688220
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2218597105
Short name T982
Test name
Test status
Simulation time 108049859 ps
CPU time 2.03 seconds
Started Jul 13 06:24:15 PM PDT 24
Finished Jul 13 06:24:20 PM PDT 24
Peak memory 217460 kb
Host smart-3ab38b37-9f5e-4c98-8f8e-68508710dc2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221859
7105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2218597105
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2265853129
Short name T935
Test name
Test status
Simulation time 212874897 ps
CPU time 1.23 seconds
Started Jul 13 06:23:50 PM PDT 24
Finished Jul 13 06:23:52 PM PDT 24
Peak memory 209100 kb
Host smart-ee13a668-2fc5-4c98-9134-f1f495bbbb2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265853129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2265853129
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1772954641
Short name T951
Test name
Test status
Simulation time 22169798 ps
CPU time 1.25 seconds
Started Jul 13 06:23:52 PM PDT 24
Finished Jul 13 06:23:54 PM PDT 24
Peak memory 211376 kb
Host smart-d4a0aec3-3f66-4b5f-aa9c-8cd8be9bc4fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772954641 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1772954641
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.578146712
Short name T918
Test name
Test status
Simulation time 75442194 ps
CPU time 1.29 seconds
Started Jul 13 06:24:07 PM PDT 24
Finished Jul 13 06:24:09 PM PDT 24
Peak memory 209272 kb
Host smart-190b1eb7-d4d9-4ab5-8cc5-eb085a4f8a74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578146712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.578146712
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2170122603
Short name T897
Test name
Test status
Simulation time 538288618 ps
CPU time 5.06 seconds
Started Jul 13 06:24:05 PM PDT 24
Finished Jul 13 06:24:10 PM PDT 24
Peak memory 217360 kb
Host smart-7a03d1ff-0b05-4fb2-99da-ebd8be91a667
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170122603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2170122603
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.336400758
Short name T899
Test name
Test status
Simulation time 51440535 ps
CPU time 1.05 seconds
Started Jul 13 06:23:42 PM PDT 24
Finished Jul 13 06:23:44 PM PDT 24
Peak memory 209244 kb
Host smart-9840fed2-4d35-4a2e-ae05-e4bd69d5c5af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336400758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.336400758
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1562766135
Short name T872
Test name
Test status
Simulation time 18412045 ps
CPU time 0.93 seconds
Started Jul 13 06:23:46 PM PDT 24
Finished Jul 13 06:23:49 PM PDT 24
Peak memory 208424 kb
Host smart-3484865f-9df7-4a7b-8e01-b7f750274309
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562766135 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1562766135
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3909605099
Short name T958
Test name
Test status
Simulation time 4016800936 ps
CPU time 22.65 seconds
Started Jul 13 06:24:10 PM PDT 24
Finished Jul 13 06:24:33 PM PDT 24
Peak memory 217300 kb
Host smart-42d75379-c2f9-416c-a930-bbb15130e485
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909605099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3909605099
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2879232799
Short name T911
Test name
Test status
Simulation time 698367230 ps
CPU time 7.85 seconds
Started Jul 13 06:24:29 PM PDT 24
Finished Jul 13 06:24:38 PM PDT 24
Peak memory 209160 kb
Host smart-a0673e07-4a9a-43f0-8d21-dced386e556d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879232799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2879232799
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3007394060
Short name T871
Test name
Test status
Simulation time 681635878 ps
CPU time 1.86 seconds
Started Jul 13 06:24:02 PM PDT 24
Finished Jul 13 06:24:04 PM PDT 24
Peak memory 210740 kb
Host smart-70143bca-5376-4c61-b049-dc2783a349c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007394060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3007394060
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.959821642
Short name T112
Test name
Test status
Simulation time 143585965 ps
CPU time 1.8 seconds
Started Jul 13 06:23:48 PM PDT 24
Finished Jul 13 06:23:56 PM PDT 24
Peak memory 217412 kb
Host smart-6a636e7d-6375-4a42-8bd6-d21b8a909a74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959821
642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.959821642
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.524132125
Short name T995
Test name
Test status
Simulation time 93105970 ps
CPU time 2.73 seconds
Started Jul 13 06:23:49 PM PDT 24
Finished Jul 13 06:23:59 PM PDT 24
Peak memory 217348 kb
Host smart-41db2b98-74be-4d7f-b37d-f6064cc54bc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524132125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.524132125
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.94805792
Short name T985
Test name
Test status
Simulation time 73936171 ps
CPU time 1.2 seconds
Started Jul 13 06:24:16 PM PDT 24
Finished Jul 13 06:24:20 PM PDT 24
Peak memory 217176 kb
Host smart-f9726ce6-1dce-436d-9f4c-4b63e1f35c9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94805792 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.94805792
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3903627637
Short name T991
Test name
Test status
Simulation time 30526608 ps
CPU time 1.06 seconds
Started Jul 13 06:23:56 PM PDT 24
Finished Jul 13 06:23:58 PM PDT 24
Peak memory 209196 kb
Host smart-3f8698b9-1934-44ba-8c2e-4f146f7dd962
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903627637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3903627637
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3500019182
Short name T913
Test name
Test status
Simulation time 458198899 ps
CPU time 5.54 seconds
Started Jul 13 06:23:46 PM PDT 24
Finished Jul 13 06:23:53 PM PDT 24
Peak memory 217444 kb
Host smart-0b2f828b-de00-4c6e-8062-231618586d94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500019182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3500019182
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3047067744
Short name T992
Test name
Test status
Simulation time 40467787 ps
CPU time 1.78 seconds
Started Jul 13 06:23:44 PM PDT 24
Finished Jul 13 06:23:46 PM PDT 24
Peak memory 219352 kb
Host smart-5bef6da1-ec2f-4bf2-9455-0a0a74a8d19a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047067744 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3047067744
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3897915161
Short name T155
Test name
Test status
Simulation time 81185500 ps
CPU time 0.83 seconds
Started Jul 13 06:23:50 PM PDT 24
Finished Jul 13 06:23:52 PM PDT 24
Peak memory 209180 kb
Host smart-15b02730-364c-4064-9a41-f3bd7af8a43d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897915161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3897915161
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3755684004
Short name T952
Test name
Test status
Simulation time 67476341 ps
CPU time 1.11 seconds
Started Jul 13 06:23:37 PM PDT 24
Finished Jul 13 06:23:38 PM PDT 24
Peak memory 208456 kb
Host smart-a9db56d1-90e5-4ef1-aa06-f32ed671502f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755684004 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3755684004
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3856310719
Short name T901
Test name
Test status
Simulation time 786374818 ps
CPU time 3.01 seconds
Started Jul 13 06:23:52 PM PDT 24
Finished Jul 13 06:23:56 PM PDT 24
Peak memory 209076 kb
Host smart-5ac86a80-5fae-41ca-92a4-b5f0c42837c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856310719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3856310719
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1446795077
Short name T975
Test name
Test status
Simulation time 8965143596 ps
CPU time 11.12 seconds
Started Jul 13 06:23:44 PM PDT 24
Finished Jul 13 06:23:56 PM PDT 24
Peak memory 217260 kb
Host smart-334bf946-e52e-4782-98b3-23bedd95f35c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446795077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1446795077
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2307077601
Short name T878
Test name
Test status
Simulation time 45980273 ps
CPU time 1.86 seconds
Started Jul 13 06:24:16 PM PDT 24
Finished Jul 13 06:24:21 PM PDT 24
Peak memory 217320 kb
Host smart-a7226c4f-04b6-4981-a670-fa7d34ee846c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307077601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2307077601
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1204315677
Short name T957
Test name
Test status
Simulation time 190476799 ps
CPU time 3.27 seconds
Started Jul 13 06:23:49 PM PDT 24
Finished Jul 13 06:23:54 PM PDT 24
Peak memory 217560 kb
Host smart-8b3318c9-2d87-4feb-8d71-84cef29bb07c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120431
5677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1204315677
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1865424657
Short name T924
Test name
Test status
Simulation time 324180219 ps
CPU time 1.52 seconds
Started Jul 13 06:23:45 PM PDT 24
Finished Jul 13 06:23:47 PM PDT 24
Peak memory 209168 kb
Host smart-435f77ce-0b8c-44c7-a4d4-313ae64d6d78
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865424657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1865424657
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2967071635
Short name T169
Test name
Test status
Simulation time 57174850 ps
CPU time 1.34 seconds
Started Jul 13 06:24:00 PM PDT 24
Finished Jul 13 06:24:02 PM PDT 24
Peak memory 209168 kb
Host smart-70bcf572-b64d-43d7-ba5a-a49875ca2239
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967071635 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2967071635
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1179226355
Short name T930
Test name
Test status
Simulation time 31981600 ps
CPU time 1.17 seconds
Started Jul 13 06:24:00 PM PDT 24
Finished Jul 13 06:24:02 PM PDT 24
Peak memory 209188 kb
Host smart-c5885a90-9a3c-477e-bfc7-445dd8b2a679
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179226355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1179226355
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.149434687
Short name T970
Test name
Test status
Simulation time 322761981 ps
CPU time 2.78 seconds
Started Jul 13 06:24:06 PM PDT 24
Finished Jul 13 06:24:09 PM PDT 24
Peak memory 218736 kb
Host smart-9738f122-644d-4f7c-b79c-2eb7c57c986e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149434687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.149434687
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.805874043
Short name T116
Test name
Test status
Simulation time 102934363 ps
CPU time 1.98 seconds
Started Jul 13 06:24:25 PM PDT 24
Finished Jul 13 06:24:30 PM PDT 24
Peak memory 221512 kb
Host smart-c3a794dd-e870-4446-9171-3e23d3151e55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805874043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.805874043
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.4074700366
Short name T919
Test name
Test status
Simulation time 19868206 ps
CPU time 1.43 seconds
Started Jul 13 06:23:46 PM PDT 24
Finished Jul 13 06:23:50 PM PDT 24
Peak memory 219296 kb
Host smart-4676477f-640a-444b-afc3-34c7fb9fb5dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074700366 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.4074700366
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2771188198
Short name T165
Test name
Test status
Simulation time 15048961 ps
CPU time 0.94 seconds
Started Jul 13 06:23:55 PM PDT 24
Finished Jul 13 06:23:57 PM PDT 24
Peak memory 209508 kb
Host smart-c861a477-8384-4e1d-90be-b3503f8cf3ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771188198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2771188198
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3667167474
Short name T923
Test name
Test status
Simulation time 29083726 ps
CPU time 1.08 seconds
Started Jul 13 06:23:47 PM PDT 24
Finished Jul 13 06:23:51 PM PDT 24
Peak memory 209328 kb
Host smart-f166f5ed-a6a4-4ef8-8778-560c391185dd
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667167474 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3667167474
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1295714498
Short name T879
Test name
Test status
Simulation time 2299214287 ps
CPU time 10.1 seconds
Started Jul 13 06:24:05 PM PDT 24
Finished Jul 13 06:24:16 PM PDT 24
Peak memory 208948 kb
Host smart-9ecbc53b-719a-4112-8b65-b1fc59b903a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295714498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1295714498
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.237048602
Short name T959
Test name
Test status
Simulation time 976666445 ps
CPU time 10.28 seconds
Started Jul 13 06:23:47 PM PDT 24
Finished Jul 13 06:23:59 PM PDT 24
Peak memory 209168 kb
Host smart-e450e570-f96f-45b2-8ed9-24b483505314
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237048602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.237048602
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.368604356
Short name T916
Test name
Test status
Simulation time 1608964614 ps
CPU time 3.09 seconds
Started Jul 13 06:23:41 PM PDT 24
Finished Jul 13 06:23:45 PM PDT 24
Peak memory 210808 kb
Host smart-43785ab6-2dca-4ee4-9216-70a535c13ff6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368604356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.368604356
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2795889054
Short name T902
Test name
Test status
Simulation time 50722819 ps
CPU time 1.31 seconds
Started Jul 13 06:23:47 PM PDT 24
Finished Jul 13 06:23:51 PM PDT 24
Peak memory 218560 kb
Host smart-bd264e21-a88c-4523-81a3-eb4e1ce5eb42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279588
9054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2795889054
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1187185749
Short name T128
Test name
Test status
Simulation time 164569341 ps
CPU time 2.09 seconds
Started Jul 13 06:23:42 PM PDT 24
Finished Jul 13 06:23:45 PM PDT 24
Peak memory 209112 kb
Host smart-bebb7d5f-da45-483a-85c7-39a00fb80803
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187185749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1187185749
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.403927058
Short name T173
Test name
Test status
Simulation time 108725404 ps
CPU time 1.41 seconds
Started Jul 13 06:23:46 PM PDT 24
Finished Jul 13 06:23:49 PM PDT 24
Peak memory 217440 kb
Host smart-01471ac3-8260-4a71-9816-bd4462900f8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403927058 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.403927058
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.323722632
Short name T102
Test name
Test status
Simulation time 44752589 ps
CPU time 1.13 seconds
Started Jul 13 06:24:13 PM PDT 24
Finished Jul 13 06:24:15 PM PDT 24
Peak memory 209252 kb
Host smart-2e7faf4b-bef8-404d-8318-74cbbd99b946
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323722632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.323722632
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1468605590
Short name T125
Test name
Test status
Simulation time 446232662 ps
CPU time 2.73 seconds
Started Jul 13 06:24:03 PM PDT 24
Finished Jul 13 06:24:06 PM PDT 24
Peak memory 217328 kb
Host smart-ec7a9262-12d1-4c7e-a812-8cc7d1fcbefb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468605590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1468605590
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2929812191
Short name T990
Test name
Test status
Simulation time 74628635 ps
CPU time 1.2 seconds
Started Jul 13 06:23:48 PM PDT 24
Finished Jul 13 06:23:51 PM PDT 24
Peak memory 218432 kb
Host smart-59c2699a-dc14-46b4-860d-f4e8f901b9f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929812191 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.2929812191
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3226858276
Short name T885
Test name
Test status
Simulation time 19609256 ps
CPU time 0.9 seconds
Started Jul 13 06:23:57 PM PDT 24
Finished Jul 13 06:23:58 PM PDT 24
Peak memory 209188 kb
Host smart-c2d41758-5659-44ea-a5fa-db8d3c39e989
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226858276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3226858276
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.672211052
Short name T964
Test name
Test status
Simulation time 67461631 ps
CPU time 1.29 seconds
Started Jul 13 06:23:46 PM PDT 24
Finished Jul 13 06:23:49 PM PDT 24
Peak memory 208524 kb
Host smart-ac4d43a9-c7a7-4281-b68c-77cf7d9f354b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672211052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.672211052
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2693697939
Short name T912
Test name
Test status
Simulation time 228495630 ps
CPU time 6.06 seconds
Started Jul 13 06:23:39 PM PDT 24
Finished Jul 13 06:23:46 PM PDT 24
Peak memory 209168 kb
Host smart-590ceb1e-b739-42a4-b64b-992233eb634c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693697939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2693697939
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2165800399
Short name T873
Test name
Test status
Simulation time 978371073 ps
CPU time 6.04 seconds
Started Jul 13 06:23:53 PM PDT 24
Finished Jul 13 06:24:00 PM PDT 24
Peak memory 208592 kb
Host smart-3dcbbce2-db43-4b27-b1fe-0382a9371d32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165800399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2165800399
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.305610298
Short name T103
Test name
Test status
Simulation time 96042363 ps
CPU time 3.26 seconds
Started Jul 13 06:23:59 PM PDT 24
Finished Jul 13 06:24:03 PM PDT 24
Peak memory 217328 kb
Host smart-e829fe31-0fc3-4207-98db-bf56424ae860
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305610298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.305610298
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2071225335
Short name T929
Test name
Test status
Simulation time 465301104 ps
CPU time 6.05 seconds
Started Jul 13 06:23:48 PM PDT 24
Finished Jul 13 06:23:56 PM PDT 24
Peak memory 217896 kb
Host smart-2f41e95c-f6cb-4282-9ee8-103833163bab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207122
5335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2071225335
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.332311917
Short name T104
Test name
Test status
Simulation time 118120928 ps
CPU time 2.26 seconds
Started Jul 13 06:23:49 PM PDT 24
Finished Jul 13 06:23:58 PM PDT 24
Peak memory 209172 kb
Host smart-9cb1afa4-a748-455a-8fab-046de32ca24d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332311917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.332311917
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1032448716
Short name T892
Test name
Test status
Simulation time 87816582 ps
CPU time 1.26 seconds
Started Jul 13 06:24:06 PM PDT 24
Finished Jul 13 06:24:08 PM PDT 24
Peak memory 217420 kb
Host smart-1f7275c7-8bc7-4837-831b-eabb589b6b70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032448716 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1032448716
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2027201246
Short name T977
Test name
Test status
Simulation time 38360158 ps
CPU time 1.4 seconds
Started Jul 13 06:23:47 PM PDT 24
Finished Jul 13 06:23:51 PM PDT 24
Peak memory 209256 kb
Host smart-0c6f0f46-1db7-4888-843e-ddf3e41feb49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027201246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2027201246
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1622548109
Short name T928
Test name
Test status
Simulation time 333744081 ps
CPU time 2.79 seconds
Started Jul 13 06:23:47 PM PDT 24
Finished Jul 13 06:23:52 PM PDT 24
Peak memory 217440 kb
Host smart-d8f58b9d-00d1-48e8-9097-9608ef056407
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622548109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1622548109
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2144037691
Short name T110
Test name
Test status
Simulation time 44318285 ps
CPU time 1.85 seconds
Started Jul 13 06:23:59 PM PDT 24
Finished Jul 13 06:24:01 PM PDT 24
Peak memory 221928 kb
Host smart-d45b4fca-bd18-46ef-91e4-60c1b37ae1f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144037691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2144037691
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1970312361
Short name T972
Test name
Test status
Simulation time 43599889 ps
CPU time 1.2 seconds
Started Jul 13 06:24:19 PM PDT 24
Finished Jul 13 06:24:24 PM PDT 24
Peak memory 218752 kb
Host smart-8e9e63db-7ff5-44f6-a639-1f585ac5a89a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970312361 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1970312361
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1442046560
Short name T161
Test name
Test status
Simulation time 24582536 ps
CPU time 0.88 seconds
Started Jul 13 06:23:47 PM PDT 24
Finished Jul 13 06:23:50 PM PDT 24
Peak memory 209184 kb
Host smart-0772f5eb-d64c-4f49-969d-335ada344093
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442046560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1442046560
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.623490140
Short name T922
Test name
Test status
Simulation time 57768006 ps
CPU time 1.34 seconds
Started Jul 13 06:23:45 PM PDT 24
Finished Jul 13 06:23:48 PM PDT 24
Peak memory 208520 kb
Host smart-8448599c-33f4-44eb-adc9-d8e81726f629
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623490140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.623490140
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1373949422
Short name T948
Test name
Test status
Simulation time 1356508219 ps
CPU time 14.52 seconds
Started Jul 13 06:24:12 PM PDT 24
Finished Jul 13 06:24:27 PM PDT 24
Peak memory 217316 kb
Host smart-6ddc835b-6e63-4d03-950b-a04001538ca3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373949422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1373949422
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.242191511
Short name T953
Test name
Test status
Simulation time 1106867951 ps
CPU time 10.45 seconds
Started Jul 13 06:23:45 PM PDT 24
Finished Jul 13 06:23:57 PM PDT 24
Peak memory 209120 kb
Host smart-b1627668-ca39-401a-bd03-53730628b23c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242191511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.242191511
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.803596867
Short name T907
Test name
Test status
Simulation time 703375937 ps
CPU time 2.31 seconds
Started Jul 13 06:23:48 PM PDT 24
Finished Jul 13 06:23:53 PM PDT 24
Peak memory 217368 kb
Host smart-ed80b15c-7eae-4909-8021-6041ce3852a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803596867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.803596867
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3664805509
Short name T887
Test name
Test status
Simulation time 132388524 ps
CPU time 2.02 seconds
Started Jul 13 06:24:09 PM PDT 24
Finished Jul 13 06:24:12 PM PDT 24
Peak memory 218916 kb
Host smart-7b906a8a-07a7-42b3-beb1-69ebfb581c1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366480
5509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3664805509
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.603106548
Short name T881
Test name
Test status
Simulation time 147098980 ps
CPU time 1.99 seconds
Started Jul 13 06:23:50 PM PDT 24
Finished Jul 13 06:23:53 PM PDT 24
Peak memory 209096 kb
Host smart-8009c8d8-33f2-4a84-b5b4-8d41a9ca4e66
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603106548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.603106548
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3659553623
Short name T170
Test name
Test status
Simulation time 326026494 ps
CPU time 1.42 seconds
Started Jul 13 06:24:20 PM PDT 24
Finished Jul 13 06:24:25 PM PDT 24
Peak memory 217280 kb
Host smart-708e12af-e046-47a3-bc09-b18b24809b35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659553623 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3659553623
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3373767400
Short name T172
Test name
Test status
Simulation time 56679660 ps
CPU time 1.88 seconds
Started Jul 13 06:24:11 PM PDT 24
Finished Jul 13 06:24:14 PM PDT 24
Peak memory 209268 kb
Host smart-7da04a6e-4686-4682-bfd1-69770e914812
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373767400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3373767400
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1748229468
Short name T941
Test name
Test status
Simulation time 88789884 ps
CPU time 2.8 seconds
Started Jul 13 06:23:47 PM PDT 24
Finished Jul 13 06:23:53 PM PDT 24
Peak memory 217444 kb
Host smart-d6bd5d37-e3bb-471f-ab5c-3fd3b53aec63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748229468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1748229468
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2656109583
Short name T126
Test name
Test status
Simulation time 46466440 ps
CPU time 2 seconds
Started Jul 13 06:24:17 PM PDT 24
Finished Jul 13 06:24:22 PM PDT 24
Peak memory 221824 kb
Host smart-626fc093-16de-481c-abe3-69a4783e6f87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656109583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.2656109583
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2165284710
Short name T406
Test name
Test status
Simulation time 38042990 ps
CPU time 0.95 seconds
Started Jul 13 04:45:51 PM PDT 24
Finished Jul 13 04:45:54 PM PDT 24
Peak memory 208368 kb
Host smart-55d3d19b-f45f-401e-8fa5-c18d71778834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165284710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2165284710
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2359213036
Short name T418
Test name
Test status
Simulation time 226140113 ps
CPU time 3.66 seconds
Started Jul 13 04:45:47 PM PDT 24
Finished Jul 13 04:45:52 PM PDT 24
Peak memory 217068 kb
Host smart-d0d0b370-f7e0-447c-92e3-c516aa2b214d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359213036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2359213036
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3105904113
Short name T595
Test name
Test status
Simulation time 4192549699 ps
CPU time 49.77 seconds
Started Jul 13 04:45:48 PM PDT 24
Finished Jul 13 04:46:38 PM PDT 24
Peak memory 217680 kb
Host smart-7dab68ee-041b-4a55-91f3-3784745f1fa8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105904113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3105904113
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1230199231
Short name T384
Test name
Test status
Simulation time 431718947 ps
CPU time 4.39 seconds
Started Jul 13 04:45:48 PM PDT 24
Finished Jul 13 04:45:53 PM PDT 24
Peak memory 217132 kb
Host smart-2ca4fb4b-8075-43aa-897c-66b5fb1435ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230199231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
230199231
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3878365559
Short name T705
Test name
Test status
Simulation time 456767320 ps
CPU time 7.54 seconds
Started Jul 13 04:45:46 PM PDT 24
Finished Jul 13 04:45:55 PM PDT 24
Peak memory 217664 kb
Host smart-819d1170-63cd-4a49-a8ae-3d0dfaaf3293
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878365559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3878365559
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2991131330
Short name T843
Test name
Test status
Simulation time 854021110 ps
CPU time 13.79 seconds
Started Jul 13 04:45:45 PM PDT 24
Finished Jul 13 04:46:00 PM PDT 24
Peak memory 217060 kb
Host smart-fb9c6c8d-e916-45cd-b1a5-7cb850ddd20e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991131330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2991131330
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.441008472
Short name T563
Test name
Test status
Simulation time 1226414773 ps
CPU time 9.46 seconds
Started Jul 13 04:45:47 PM PDT 24
Finished Jul 13 04:45:57 PM PDT 24
Peak memory 217020 kb
Host smart-c6b76cd3-1182-4a59-82e5-45c56edc99c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441008472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.441008472
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3480526533
Short name T593
Test name
Test status
Simulation time 4648395082 ps
CPU time 78.32 seconds
Started Jul 13 04:45:48 PM PDT 24
Finished Jul 13 04:47:07 PM PDT 24
Peak memory 283020 kb
Host smart-c846af8e-523a-4445-8b64-7ade675fb0cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480526533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3480526533
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.3171627315
Short name T600
Test name
Test status
Simulation time 880777232 ps
CPU time 29.45 seconds
Started Jul 13 04:45:46 PM PDT 24
Finished Jul 13 04:46:17 PM PDT 24
Peak memory 249816 kb
Host smart-b964cba5-82ac-4284-8eb4-262d97641edb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171627315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.3171627315
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3075168554
Short name T286
Test name
Test status
Simulation time 41292869 ps
CPU time 1.47 seconds
Started Jul 13 04:45:48 PM PDT 24
Finished Jul 13 04:45:50 PM PDT 24
Peak memory 217684 kb
Host smart-98fda589-03f6-4c9c-b8e7-a1e1a689762a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075168554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3075168554
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2102548897
Short name T807
Test name
Test status
Simulation time 2805938394 ps
CPU time 10.24 seconds
Started Jul 13 04:45:46 PM PDT 24
Finished Jul 13 04:45:58 PM PDT 24
Peak memory 213992 kb
Host smart-e2a2a571-e485-4f76-89ac-f26c53efee00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102548897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2102548897
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3782320968
Short name T89
Test name
Test status
Simulation time 109774797 ps
CPU time 23.83 seconds
Started Jul 13 04:45:43 PM PDT 24
Finished Jul 13 04:46:09 PM PDT 24
Peak memory 269280 kb
Host smart-42007423-c56f-44fd-99fa-be1a879903b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782320968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3782320968
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3717886518
Short name T478
Test name
Test status
Simulation time 409347234 ps
CPU time 9.19 seconds
Started Jul 13 04:45:49 PM PDT 24
Finished Jul 13 04:45:59 PM PDT 24
Peak memory 217724 kb
Host smart-8fa80b2b-165e-4554-aa7f-5df2a41fe281
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717886518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
717886518
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.1212165869
Short name T386
Test name
Test status
Simulation time 371167705 ps
CPU time 13.69 seconds
Started Jul 13 04:45:42 PM PDT 24
Finished Jul 13 04:45:57 PM PDT 24
Peak memory 224884 kb
Host smart-8e39a43c-13c4-4cd3-b8ba-451fdfb81db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212165869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1212165869
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1900034043
Short name T461
Test name
Test status
Simulation time 64035063 ps
CPU time 2.59 seconds
Started Jul 13 04:45:48 PM PDT 24
Finished Jul 13 04:45:51 PM PDT 24
Peak memory 214016 kb
Host smart-14ad106b-7b0e-4c79-bd2e-5a9d6d6b0803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900034043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1900034043
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1965946744
Short name T619
Test name
Test status
Simulation time 686986810 ps
CPU time 20.53 seconds
Started Jul 13 04:45:49 PM PDT 24
Finished Jul 13 04:46:11 PM PDT 24
Peak memory 250472 kb
Host smart-c4c48c65-3883-4340-9347-1732e6228a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965946744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1965946744
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3666345006
Short name T646
Test name
Test status
Simulation time 713402047 ps
CPU time 8.75 seconds
Started Jul 13 04:45:48 PM PDT 24
Finished Jul 13 04:45:57 PM PDT 24
Peak memory 250436 kb
Host smart-f1d930de-0f5c-48a1-84ed-ddd57998baf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666345006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3666345006
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1417824881
Short name T334
Test name
Test status
Simulation time 1907890151 ps
CPU time 39.71 seconds
Started Jul 13 04:45:47 PM PDT 24
Finished Jul 13 04:46:28 PM PDT 24
Peak memory 250396 kb
Host smart-73f08fb4-277b-4d5d-bc52-6efc49d158f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417824881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1417824881
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1043460405
Short name T27
Test name
Test status
Simulation time 13975103 ps
CPU time 1.13 seconds
Started Jul 13 04:45:49 PM PDT 24
Finished Jul 13 04:45:51 PM PDT 24
Peak memory 211232 kb
Host smart-4b9004e4-d91b-4d92-8994-4280e351a0db
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043460405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1043460405
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1375884436
Short name T419
Test name
Test status
Simulation time 20702313 ps
CPU time 0.98 seconds
Started Jul 13 04:45:52 PM PDT 24
Finished Jul 13 04:45:55 PM PDT 24
Peak memory 208420 kb
Host smart-15bfa6de-fa6e-4b59-b171-303fc8185cbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375884436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1375884436
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1659905859
Short name T188
Test name
Test status
Simulation time 12088465 ps
CPU time 0.85 seconds
Started Jul 13 04:45:54 PM PDT 24
Finished Jul 13 04:45:56 PM PDT 24
Peak memory 208420 kb
Host smart-2649369d-801f-4c31-8951-3c2f62889897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659905859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1659905859
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1175219689
Short name T265
Test name
Test status
Simulation time 1049109508 ps
CPU time 12.98 seconds
Started Jul 13 04:45:51 PM PDT 24
Finished Jul 13 04:46:06 PM PDT 24
Peak memory 225448 kb
Host smart-449f3b8b-84cd-4441-9225-88bce36de524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175219689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1175219689
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.742241861
Short name T550
Test name
Test status
Simulation time 216909313 ps
CPU time 2.14 seconds
Started Jul 13 04:45:52 PM PDT 24
Finished Jul 13 04:45:55 PM PDT 24
Peak memory 217076 kb
Host smart-27c1d0d0-424d-4da6-8c9a-152f0061325e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742241861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.742241861
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2287081078
Short name T385
Test name
Test status
Simulation time 8356706118 ps
CPU time 68.69 seconds
Started Jul 13 04:45:53 PM PDT 24
Finished Jul 13 04:47:03 PM PDT 24
Peak memory 218636 kb
Host smart-e352dfc7-e31b-4535-ac1f-b18d5b31f48c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287081078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2287081078
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2157064049
Short name T841
Test name
Test status
Simulation time 2750666870 ps
CPU time 5.4 seconds
Started Jul 13 04:45:53 PM PDT 24
Finished Jul 13 04:46:00 PM PDT 24
Peak memory 217136 kb
Host smart-b0d84bc3-3e0b-43e3-bb98-6790a9963f19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157064049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
157064049
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.904694315
Short name T19
Test name
Test status
Simulation time 5845502281 ps
CPU time 15.84 seconds
Started Jul 13 04:45:51 PM PDT 24
Finished Jul 13 04:46:07 PM PDT 24
Peak memory 219388 kb
Host smart-d7da2856-7615-4f46-a534-2fc18511bc7b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904694315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.904694315
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1095180876
Short name T639
Test name
Test status
Simulation time 2663939382 ps
CPU time 28.62 seconds
Started Jul 13 04:45:53 PM PDT 24
Finished Jul 13 04:46:23 PM PDT 24
Peak memory 217048 kb
Host smart-2932dd13-54bf-4a38-9b3a-82378fbcfadb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095180876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1095180876
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.489504453
Short name T519
Test name
Test status
Simulation time 816248196 ps
CPU time 4.4 seconds
Started Jul 13 04:45:51 PM PDT 24
Finished Jul 13 04:45:57 PM PDT 24
Peak memory 217000 kb
Host smart-460040b6-2e44-495b-a30b-92a9048b2f89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489504453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.489504453
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3276740568
Short name T431
Test name
Test status
Simulation time 5509944405 ps
CPU time 59.44 seconds
Started Jul 13 04:45:51 PM PDT 24
Finished Jul 13 04:46:52 PM PDT 24
Peak memory 283144 kb
Host smart-238c48f2-5eb1-49b6-b46b-9c6f482fecd7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276740568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3276740568
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2958109128
Short name T336
Test name
Test status
Simulation time 621088835 ps
CPU time 10.92 seconds
Started Jul 13 04:45:52 PM PDT 24
Finished Jul 13 04:46:05 PM PDT 24
Peak memory 250384 kb
Host smart-90bd395e-d62b-4680-a991-42cd6b009bc2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958109128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2958109128
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.414098942
Short name T583
Test name
Test status
Simulation time 34328109 ps
CPU time 2.24 seconds
Started Jul 13 04:45:53 PM PDT 24
Finished Jul 13 04:45:57 PM PDT 24
Peak memory 221688 kb
Host smart-a0d4023e-9991-4405-9710-e0a1062fa37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414098942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.414098942
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2728221397
Short name T151
Test name
Test status
Simulation time 796042024 ps
CPU time 11.06 seconds
Started Jul 13 04:45:54 PM PDT 24
Finished Jul 13 04:46:06 PM PDT 24
Peak memory 217084 kb
Host smart-5c6e8763-4520-4b8e-ba25-6447e50f8d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728221397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2728221397
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.4061879153
Short name T58
Test name
Test status
Simulation time 1258086794 ps
CPU time 22.86 seconds
Started Jul 13 04:46:04 PM PDT 24
Finished Jul 13 04:46:27 PM PDT 24
Peak memory 283976 kb
Host smart-6458acee-9237-49a0-bd80-bc0546551ae5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061879153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.4061879153
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.857020024
Short name T337
Test name
Test status
Simulation time 776438124 ps
CPU time 10.03 seconds
Started Jul 13 04:45:58 PM PDT 24
Finished Jul 13 04:46:09 PM PDT 24
Peak memory 225384 kb
Host smart-cbd2326a-2f70-43b0-a6ca-b32e532031eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857020024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.857020024
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3988297183
Short name T233
Test name
Test status
Simulation time 240464585 ps
CPU time 9.99 seconds
Started Jul 13 04:45:52 PM PDT 24
Finished Jul 13 04:46:03 PM PDT 24
Peak memory 225384 kb
Host smart-e4c8d4c2-e2d3-409d-ab00-d2bd7eb072bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988297183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
988297183
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.71962123
Short name T856
Test name
Test status
Simulation time 348435864 ps
CPU time 15 seconds
Started Jul 13 04:45:53 PM PDT 24
Finished Jul 13 04:46:09 PM PDT 24
Peak memory 225492 kb
Host smart-c9481952-c589-4b1c-84ca-1c555b6b9ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71962123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.71962123
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.4173972830
Short name T74
Test name
Test status
Simulation time 83600392 ps
CPU time 1.31 seconds
Started Jul 13 04:45:59 PM PDT 24
Finished Jul 13 04:46:00 PM PDT 24
Peak memory 217076 kb
Host smart-2d5a6a23-b629-4d79-973b-fa56b947f61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173972830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.4173972830
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.20166591
Short name T313
Test name
Test status
Simulation time 514875193 ps
CPU time 31.89 seconds
Started Jul 13 04:45:53 PM PDT 24
Finished Jul 13 04:46:26 PM PDT 24
Peak memory 250404 kb
Host smart-5e9fa3f0-bc3a-481b-a9a7-e2fae3af50f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20166591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.20166591
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.453371296
Short name T224
Test name
Test status
Simulation time 171451733 ps
CPU time 7.68 seconds
Started Jul 13 04:45:52 PM PDT 24
Finished Jul 13 04:46:01 PM PDT 24
Peak memory 250456 kb
Host smart-21c9a557-5ef4-4913-b5f4-e30098b4cf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453371296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.453371296
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3270167640
Short name T352
Test name
Test status
Simulation time 27299035 ps
CPU time 1.19 seconds
Started Jul 13 04:45:51 PM PDT 24
Finished Jul 13 04:45:54 PM PDT 24
Peak memory 211296 kb
Host smart-f8c65654-f5e0-4466-95ea-9979cb33c1d7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270167640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3270167640
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3871861000
Short name T247
Test name
Test status
Simulation time 31136063 ps
CPU time 0.97 seconds
Started Jul 13 04:46:35 PM PDT 24
Finished Jul 13 04:46:37 PM PDT 24
Peak memory 208528 kb
Host smart-ca720b73-aca9-4a38-b47e-022684d4f68a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871861000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3871861000
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1250633676
Short name T60
Test name
Test status
Simulation time 354553137 ps
CPU time 13.65 seconds
Started Jul 13 04:46:31 PM PDT 24
Finished Jul 13 04:46:46 PM PDT 24
Peak memory 217676 kb
Host smart-d5ac92f9-1865-4017-95d6-3a98a1929a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250633676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1250633676
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.4149308990
Short name T66
Test name
Test status
Simulation time 148434928 ps
CPU time 1.76 seconds
Started Jul 13 04:46:31 PM PDT 24
Finished Jul 13 04:46:34 PM PDT 24
Peak memory 216536 kb
Host smart-4f56b423-6dc4-4f30-ab12-915c12526561
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149308990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.4149308990
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.812857573
Short name T571
Test name
Test status
Simulation time 9148181285 ps
CPU time 37.34 seconds
Started Jul 13 04:46:38 PM PDT 24
Finished Jul 13 04:47:16 PM PDT 24
Peak memory 218300 kb
Host smart-c6f2c6e4-5ea0-4502-bfe0-3d60e6141fab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812857573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_er
rors.812857573
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2102757122
Short name T285
Test name
Test status
Simulation time 1246428583 ps
CPU time 5.32 seconds
Started Jul 13 04:46:33 PM PDT 24
Finished Jul 13 04:46:40 PM PDT 24
Peak memory 222316 kb
Host smart-f54b2828-df64-46b2-9b09-cb0e6e204ed6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102757122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2102757122
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.74844280
Short name T259
Test name
Test status
Simulation time 195323053 ps
CPU time 4.52 seconds
Started Jul 13 04:46:34 PM PDT 24
Finished Jul 13 04:46:40 PM PDT 24
Peak memory 217004 kb
Host smart-5e12359e-8a63-4359-8f2c-3b811251c9cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74844280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.74844280
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2052832455
Short name T800
Test name
Test status
Simulation time 930237507 ps
CPU time 29.19 seconds
Started Jul 13 04:46:33 PM PDT 24
Finished Jul 13 04:47:04 PM PDT 24
Peak memory 266840 kb
Host smart-a9fd4d6b-063d-47e2-a243-06d193bc6f4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052832455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2052832455
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.467058083
Short name T757
Test name
Test status
Simulation time 1159867559 ps
CPU time 9.96 seconds
Started Jul 13 04:46:34 PM PDT 24
Finished Jul 13 04:46:45 PM PDT 24
Peak memory 249868 kb
Host smart-901970a9-d6aa-4698-a5aa-c6bb071882ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467058083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.467058083
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2112767662
Short name T867
Test name
Test status
Simulation time 396865590 ps
CPU time 3.31 seconds
Started Jul 13 04:46:31 PM PDT 24
Finished Jul 13 04:46:36 PM PDT 24
Peak memory 221980 kb
Host smart-8bf5525f-56ae-43f1-909c-15f031b63a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112767662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2112767662
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.4020280411
Short name T733
Test name
Test status
Simulation time 2604684632 ps
CPU time 13.51 seconds
Started Jul 13 04:46:36 PM PDT 24
Finished Jul 13 04:46:50 PM PDT 24
Peak memory 225536 kb
Host smart-0a1adee1-a7b8-4cb9-a893-d85d2544cc73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020280411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.4020280411
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3681242696
Short name T450
Test name
Test status
Simulation time 587276119 ps
CPU time 13.96 seconds
Started Jul 13 04:46:31 PM PDT 24
Finished Jul 13 04:46:47 PM PDT 24
Peak memory 225396 kb
Host smart-26b93ade-db01-4908-a83b-7782b316e284
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681242696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3681242696
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3713260661
Short name T821
Test name
Test status
Simulation time 2142356408 ps
CPU time 11.75 seconds
Started Jul 13 04:46:36 PM PDT 24
Finished Jul 13 04:46:49 PM PDT 24
Peak memory 217616 kb
Host smart-6c0e6914-11d3-479d-8b05-dc89605925fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713260661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
3713260661
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.441933409
Short name T534
Test name
Test status
Simulation time 1593575698 ps
CPU time 14.61 seconds
Started Jul 13 04:46:31 PM PDT 24
Finished Jul 13 04:46:48 PM PDT 24
Peak memory 225508 kb
Host smart-1dce68d7-1bb9-471f-8ba3-d7b73e86f3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441933409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.441933409
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3797297644
Short name T403
Test name
Test status
Simulation time 35280360 ps
CPU time 1.19 seconds
Started Jul 13 04:46:32 PM PDT 24
Finished Jul 13 04:46:35 PM PDT 24
Peak memory 212952 kb
Host smart-8c5c5426-ee97-4e1c-ad1e-ddfc85b90964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797297644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3797297644
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2321496907
Short name T271
Test name
Test status
Simulation time 202676820 ps
CPU time 23.35 seconds
Started Jul 13 04:46:31 PM PDT 24
Finished Jul 13 04:46:56 PM PDT 24
Peak memory 250420 kb
Host smart-3b360a5d-f25e-4ba2-b15d-a2577f7bec13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321496907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2321496907
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1909507167
Short name T401
Test name
Test status
Simulation time 138815534 ps
CPU time 9.4 seconds
Started Jul 13 04:46:30 PM PDT 24
Finished Jul 13 04:46:41 PM PDT 24
Peak memory 249892 kb
Host smart-fb56de14-1ec9-4c7b-b275-cd12162e551c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909507167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1909507167
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.73305465
Short name T605
Test name
Test status
Simulation time 11019804965 ps
CPU time 158.11 seconds
Started Jul 13 04:46:30 PM PDT 24
Finished Jul 13 04:49:09 PM PDT 24
Peak memory 268000 kb
Host smart-536a105c-46bd-40fa-ae16-543361b754e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73305465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.lc_ctrl_stress_all.73305465
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1626009964
Short name T624
Test name
Test status
Simulation time 10774755 ps
CPU time 0.78 seconds
Started Jul 13 04:46:34 PM PDT 24
Finished Jul 13 04:46:36 PM PDT 24
Peak memory 208228 kb
Host smart-c660fbf5-3aab-4007-b6b2-8bd82bc0b928
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626009964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1626009964
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3309614939
Short name T773
Test name
Test status
Simulation time 61114224 ps
CPU time 1.3 seconds
Started Jul 13 04:46:37 PM PDT 24
Finished Jul 13 04:46:39 PM PDT 24
Peak memory 208396 kb
Host smart-36b8d379-6193-40b3-b0d6-e307b2375837
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309614939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3309614939
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.633250865
Short name T142
Test name
Test status
Simulation time 1562096991 ps
CPU time 16.77 seconds
Started Jul 13 04:46:30 PM PDT 24
Finished Jul 13 04:46:48 PM PDT 24
Peak memory 217720 kb
Host smart-aae1b649-001c-4fab-b58b-83f17f478fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633250865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.633250865
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1525785487
Short name T152
Test name
Test status
Simulation time 444537978 ps
CPU time 5.12 seconds
Started Jul 13 04:46:43 PM PDT 24
Finished Jul 13 04:46:49 PM PDT 24
Peak memory 216648 kb
Host smart-8cecc267-4fe5-4663-b901-8be85c4ee025
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525785487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1525785487
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1924713445
Short name T465
Test name
Test status
Simulation time 2333779036 ps
CPU time 71.52 seconds
Started Jul 13 04:46:38 PM PDT 24
Finished Jul 13 04:47:51 PM PDT 24
Peak memory 218360 kb
Host smart-d6a8dc5a-e6b5-419d-9e55-b910c2ca8a4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924713445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1924713445
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2050731484
Short name T382
Test name
Test status
Simulation time 394439160 ps
CPU time 11.63 seconds
Started Jul 13 04:46:43 PM PDT 24
Finished Jul 13 04:46:55 PM PDT 24
Peak memory 222060 kb
Host smart-24416a6d-06cf-41a5-9810-85ec2c137736
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050731484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2050731484
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2581609307
Short name T844
Test name
Test status
Simulation time 246393258 ps
CPU time 4.29 seconds
Started Jul 13 04:46:35 PM PDT 24
Finished Jul 13 04:46:41 PM PDT 24
Peak memory 216956 kb
Host smart-fc58280a-9683-4724-9b55-b2ef5280d0fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581609307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2581609307
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1987847204
Short name T327
Test name
Test status
Simulation time 8426551933 ps
CPU time 45.25 seconds
Started Jul 13 04:46:32 PM PDT 24
Finished Jul 13 04:47:19 PM PDT 24
Peak memory 266796 kb
Host smart-a975f3c7-ce32-499c-970b-5ec71e034543
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987847204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.1987847204
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3950137680
Short name T830
Test name
Test status
Simulation time 356543381 ps
CPU time 15.79 seconds
Started Jul 13 04:46:38 PM PDT 24
Finished Jul 13 04:46:54 PM PDT 24
Peak memory 245716 kb
Host smart-7baa7fd4-6807-4284-9fb9-2f44f5bdd445
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950137680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3950137680
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.393427090
Short name T558
Test name
Test status
Simulation time 116749193 ps
CPU time 5.45 seconds
Started Jul 13 04:46:30 PM PDT 24
Finished Jul 13 04:46:36 PM PDT 24
Peak memory 217676 kb
Host smart-5b965375-9d0b-4345-a843-f8daad38c991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393427090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.393427090
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2239173047
Short name T472
Test name
Test status
Simulation time 514185821 ps
CPU time 11.41 seconds
Started Jul 13 04:46:39 PM PDT 24
Finished Jul 13 04:46:51 PM PDT 24
Peak memory 225508 kb
Host smart-7aab8934-fc0a-47a0-bb78-3107270a993a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239173047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2239173047
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2784291728
Short name T249
Test name
Test status
Simulation time 2777618440 ps
CPU time 17.71 seconds
Started Jul 13 04:46:38 PM PDT 24
Finished Jul 13 04:46:56 PM PDT 24
Peak memory 225504 kb
Host smart-debb694b-245e-4808-90ad-1aced2aa620f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784291728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2784291728
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1397348992
Short name T818
Test name
Test status
Simulation time 604445669 ps
CPU time 13.14 seconds
Started Jul 13 04:46:39 PM PDT 24
Finished Jul 13 04:46:53 PM PDT 24
Peak memory 225444 kb
Host smart-61569b92-d412-43d6-8f21-eb9c09133773
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397348992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1397348992
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2990770998
Short name T862
Test name
Test status
Simulation time 277368152 ps
CPU time 7.66 seconds
Started Jul 13 04:46:32 PM PDT 24
Finished Jul 13 04:46:42 PM PDT 24
Peak memory 225636 kb
Host smart-a95216f3-3221-4a7b-9561-51c392216688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990770998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2990770998
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3516131357
Short name T838
Test name
Test status
Simulation time 39701485 ps
CPU time 2.64 seconds
Started Jul 13 04:46:32 PM PDT 24
Finished Jul 13 04:46:36 PM PDT 24
Peak memory 213788 kb
Host smart-dded2e73-28f9-4b71-afa1-bc3ea124a58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516131357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3516131357
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1580485672
Short name T295
Test name
Test status
Simulation time 364730162 ps
CPU time 31.6 seconds
Started Jul 13 04:46:37 PM PDT 24
Finished Jul 13 04:47:10 PM PDT 24
Peak memory 250236 kb
Host smart-c77b2eac-77ab-4b74-8197-f97dbac08adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580485672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1580485672
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2653275862
Short name T560
Test name
Test status
Simulation time 260068725 ps
CPU time 7.16 seconds
Started Jul 13 04:46:33 PM PDT 24
Finished Jul 13 04:46:42 PM PDT 24
Peak memory 250456 kb
Host smart-1fec863a-7491-4476-b649-86870f0749b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653275862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2653275862
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3568448819
Short name T415
Test name
Test status
Simulation time 8006263381 ps
CPU time 141.42 seconds
Started Jul 13 04:46:40 PM PDT 24
Finished Jul 13 04:49:03 PM PDT 24
Peak memory 272584 kb
Host smart-1380ce2f-8250-4152-8c15-f1f59498d0a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568448819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3568448819
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.3963702635
Short name T545
Test name
Test status
Simulation time 47091562895 ps
CPU time 348.94 seconds
Started Jul 13 04:46:43 PM PDT 24
Finished Jul 13 04:52:32 PM PDT 24
Peak memory 258632 kb
Host smart-847c1b6d-4fdf-4292-b303-b40e12204f9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3963702635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.3963702635
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2975758721
Short name T790
Test name
Test status
Simulation time 15732930 ps
CPU time 0.98 seconds
Started Jul 13 04:46:35 PM PDT 24
Finished Jul 13 04:46:38 PM PDT 24
Peak memory 211272 kb
Host smart-b233e88f-2b26-44c6-908d-c1686a6d594d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975758721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2975758721
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.4000622923
Short name T831
Test name
Test status
Simulation time 20622308 ps
CPU time 1.18 seconds
Started Jul 13 04:46:38 PM PDT 24
Finished Jul 13 04:46:40 PM PDT 24
Peak memory 208404 kb
Host smart-1380104f-7d09-4966-b06f-8c67280f6c4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000622923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.4000622923
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3949879653
Short name T402
Test name
Test status
Simulation time 1325477008 ps
CPU time 10.91 seconds
Started Jul 13 04:46:39 PM PDT 24
Finished Jul 13 04:46:51 PM PDT 24
Peak memory 217680 kb
Host smart-757eebbf-dc0e-410c-8bf5-f2ec84d5d45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949879653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3949879653
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2839209943
Short name T24
Test name
Test status
Simulation time 819613496 ps
CPU time 5.49 seconds
Started Jul 13 04:46:38 PM PDT 24
Finished Jul 13 04:46:44 PM PDT 24
Peak memory 216712 kb
Host smart-8583eb31-9969-46df-b5e0-78c168e9d396
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839209943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2839209943
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.906908035
Short name T587
Test name
Test status
Simulation time 1245178188 ps
CPU time 21.51 seconds
Started Jul 13 04:46:46 PM PDT 24
Finished Jul 13 04:47:09 PM PDT 24
Peak memory 217544 kb
Host smart-a982b60a-3156-4a58-bc5a-a5421b85a14a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906908035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er
rors.906908035
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2557971064
Short name T232
Test name
Test status
Simulation time 1034160250 ps
CPU time 15.17 seconds
Started Jul 13 04:46:38 PM PDT 24
Finished Jul 13 04:46:54 PM PDT 24
Peak memory 217640 kb
Host smart-741376e6-e245-432e-8d27-ec7e3b6013d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557971064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2557971064
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1768268143
Short name T670
Test name
Test status
Simulation time 190241239 ps
CPU time 2.41 seconds
Started Jul 13 04:46:41 PM PDT 24
Finished Jul 13 04:46:44 PM PDT 24
Peak memory 217020 kb
Host smart-676c855b-56e6-472a-9145-5b12d5c31dd5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768268143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1768268143
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.4071922382
Short name T398
Test name
Test status
Simulation time 2674164786 ps
CPU time 85.8 seconds
Started Jul 13 04:46:40 PM PDT 24
Finished Jul 13 04:48:06 PM PDT 24
Peak memory 277304 kb
Host smart-f86a0e47-6999-42bd-a201-af148454d92f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071922382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.4071922382
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.4095291655
Short name T454
Test name
Test status
Simulation time 491354807 ps
CPU time 15.86 seconds
Started Jul 13 04:46:39 PM PDT 24
Finished Jul 13 04:46:56 PM PDT 24
Peak memory 250296 kb
Host smart-0f317fee-9e9b-4bfa-a4e2-579c8a24ad63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095291655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.4095291655
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3745881491
Short name T698
Test name
Test status
Simulation time 56928617 ps
CPU time 1.82 seconds
Started Jul 13 04:46:38 PM PDT 24
Finished Jul 13 04:46:41 PM PDT 24
Peak memory 217724 kb
Host smart-147734ad-c8cf-4703-a755-6d56c3a2efea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745881491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3745881491
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2727112789
Short name T627
Test name
Test status
Simulation time 434266849 ps
CPU time 13.7 seconds
Started Jul 13 04:46:46 PM PDT 24
Finished Jul 13 04:47:03 PM PDT 24
Peak memory 219372 kb
Host smart-22340a27-d9a7-475d-97fa-95785504dcf9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727112789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2727112789
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.156859313
Short name T845
Test name
Test status
Simulation time 302121218 ps
CPU time 8.61 seconds
Started Jul 13 04:46:47 PM PDT 24
Finished Jul 13 04:46:58 PM PDT 24
Peak memory 225288 kb
Host smart-baa54d13-8e8a-4aa3-88f4-5166bbd6cd4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156859313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.156859313
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2657776105
Short name T518
Test name
Test status
Simulation time 2022157862 ps
CPU time 9.65 seconds
Started Jul 13 04:46:38 PM PDT 24
Finished Jul 13 04:46:49 PM PDT 24
Peak memory 225444 kb
Host smart-409e60ef-f694-459e-a39b-cfa2e203306c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657776105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2657776105
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3764746251
Short name T703
Test name
Test status
Simulation time 94076480 ps
CPU time 1.64 seconds
Started Jul 13 04:46:46 PM PDT 24
Finished Jul 13 04:46:51 PM PDT 24
Peak memory 217104 kb
Host smart-c688a049-4fe5-4706-8fb8-7f7ef268613d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764746251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3764746251
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1182441887
Short name T230
Test name
Test status
Simulation time 388505872 ps
CPU time 32.36 seconds
Started Jul 13 04:46:40 PM PDT 24
Finished Jul 13 04:47:14 PM PDT 24
Peak memory 250468 kb
Host smart-85cdaa0a-8c7a-4921-a553-7fee9d2802fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182441887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1182441887
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3884931341
Short name T688
Test name
Test status
Simulation time 259646361 ps
CPU time 7.73 seconds
Started Jul 13 04:46:40 PM PDT 24
Finished Jul 13 04:46:48 PM PDT 24
Peak memory 250336 kb
Host smart-b09803c0-dcbb-4834-861e-e0a24f67ef78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884931341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3884931341
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2466555541
Short name T410
Test name
Test status
Simulation time 5191591159 ps
CPU time 66.99 seconds
Started Jul 13 04:46:37 PM PDT 24
Finished Jul 13 04:47:45 PM PDT 24
Peak memory 273996 kb
Host smart-51b6f1c1-686d-455d-80e1-ccd421af58b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466555541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2466555541
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.880759934
Short name T493
Test name
Test status
Simulation time 14286616 ps
CPU time 1 seconds
Started Jul 13 04:46:42 PM PDT 24
Finished Jul 13 04:46:44 PM PDT 24
Peak memory 211304 kb
Host smart-cd5693d6-754c-4a5f-b82a-f175bf204b78
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880759934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct
rl_volatile_unlock_smoke.880759934
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3114335620
Short name T475
Test name
Test status
Simulation time 24252246 ps
CPU time 1.17 seconds
Started Jul 13 04:46:47 PM PDT 24
Finished Jul 13 04:46:51 PM PDT 24
Peak memory 208052 kb
Host smart-fbd9e042-cb5e-499e-858f-25ce3c7480c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114335620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3114335620
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1575522954
Short name T145
Test name
Test status
Simulation time 1512730047 ps
CPU time 12.29 seconds
Started Jul 13 04:46:41 PM PDT 24
Finished Jul 13 04:46:54 PM PDT 24
Peak memory 217628 kb
Host smart-64fd4aa7-d31c-4e37-9154-9d7940810e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575522954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1575522954
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3206834701
Short name T768
Test name
Test status
Simulation time 416496515 ps
CPU time 1.39 seconds
Started Jul 13 04:46:43 PM PDT 24
Finished Jul 13 04:46:45 PM PDT 24
Peak memory 216136 kb
Host smart-7d10a510-1097-4493-b64b-f5c7f6534912
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206834701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3206834701
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1150218634
Short name T387
Test name
Test status
Simulation time 1315228012 ps
CPU time 20.29 seconds
Started Jul 13 04:46:43 PM PDT 24
Finished Jul 13 04:47:04 PM PDT 24
Peak memory 217608 kb
Host smart-cb7e69d8-589a-467d-b97a-3246d9553610
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150218634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1150218634
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1430954863
Short name T523
Test name
Test status
Simulation time 395935337 ps
CPU time 3.88 seconds
Started Jul 13 04:46:43 PM PDT 24
Finished Jul 13 04:46:47 PM PDT 24
Peak memory 217612 kb
Host smart-43357e21-2e8f-4f45-9872-6ee0ecbe6575
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430954863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1430954863
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.1992988896
Short name T77
Test name
Test status
Simulation time 423622646 ps
CPU time 2.43 seconds
Started Jul 13 04:46:47 PM PDT 24
Finished Jul 13 04:46:52 PM PDT 24
Peak memory 217384 kb
Host smart-14ce1ac1-2ce4-45e4-b45a-8b422857e198
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992988896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.1992988896
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1095145694
Short name T731
Test name
Test status
Simulation time 4908195601 ps
CPU time 58.04 seconds
Started Jul 13 04:46:40 PM PDT 24
Finished Jul 13 04:47:38 PM PDT 24
Peak memory 279344 kb
Host smart-73029465-4334-43b3-8a54-d9772bf52e42
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095145694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1095145694
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2839251675
Short name T684
Test name
Test status
Simulation time 1211342615 ps
CPU time 20.49 seconds
Started Jul 13 04:46:47 PM PDT 24
Finished Jul 13 04:47:11 PM PDT 24
Peak memory 250640 kb
Host smart-13990729-8e34-48f7-93ba-f2384c6e6a0f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839251675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2839251675
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2802352803
Short name T197
Test name
Test status
Simulation time 124563382 ps
CPU time 2.47 seconds
Started Jul 13 04:46:41 PM PDT 24
Finished Jul 13 04:46:44 PM PDT 24
Peak memory 217744 kb
Host smart-58defc04-1797-4614-ac37-e8b7a121dd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802352803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2802352803
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3899036187
Short name T289
Test name
Test status
Simulation time 4842470075 ps
CPU time 13.92 seconds
Started Jul 13 04:46:43 PM PDT 24
Finished Jul 13 04:46:58 PM PDT 24
Peak memory 225468 kb
Host smart-45f9c570-a1d9-4c65-a436-ffc42efa2f41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899036187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3899036187
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2729717250
Short name T192
Test name
Test status
Simulation time 926327829 ps
CPU time 6.49 seconds
Started Jul 13 04:46:41 PM PDT 24
Finished Jul 13 04:46:48 PM PDT 24
Peak memory 225316 kb
Host smart-d7379f91-eae6-4a18-b8ad-22d6cbf732ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729717250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2729717250
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2789155842
Short name T307
Test name
Test status
Simulation time 189611321 ps
CPU time 8.62 seconds
Started Jul 13 04:46:43 PM PDT 24
Finished Jul 13 04:46:52 PM PDT 24
Peak memory 225084 kb
Host smart-5935e095-43db-41d4-a604-2730d0c21068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789155842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2789155842
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.997551327
Short name T805
Test name
Test status
Simulation time 98282413 ps
CPU time 1.24 seconds
Started Jul 13 04:46:41 PM PDT 24
Finished Jul 13 04:46:43 PM PDT 24
Peak memory 213040 kb
Host smart-03bfda04-78ed-4321-b920-348367596d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997551327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.997551327
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.4279428156
Short name T532
Test name
Test status
Simulation time 322748878 ps
CPU time 32.98 seconds
Started Jul 13 04:46:38 PM PDT 24
Finished Jul 13 04:47:11 PM PDT 24
Peak memory 250420 kb
Host smart-6264ef88-63bb-4546-b45d-beab2067a42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279428156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.4279428156
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2274970232
Short name T682
Test name
Test status
Simulation time 372071488 ps
CPU time 7.79 seconds
Started Jul 13 04:46:46 PM PDT 24
Finished Jul 13 04:46:56 PM PDT 24
Peak memory 250416 kb
Host smart-b744a817-0fdf-41b4-9752-67a623de348f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274970232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2274970232
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.947991112
Short name T781
Test name
Test status
Simulation time 7933707401 ps
CPU time 177.74 seconds
Started Jul 13 04:46:41 PM PDT 24
Finished Jul 13 04:49:39 PM PDT 24
Peak memory 279092 kb
Host smart-c1f0bdc4-6cfd-4c6f-801e-bf86516653a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947991112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.947991112
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.3731665043
Short name T565
Test name
Test status
Simulation time 28146940839 ps
CPU time 548.07 seconds
Started Jul 13 04:46:46 PM PDT 24
Finished Jul 13 04:55:57 PM PDT 24
Peak memory 529120 kb
Host smart-55bd3cd5-e62f-4750-97e0-b419a6c17add
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3731665043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.3731665043
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2256804185
Short name T37
Test name
Test status
Simulation time 14469818 ps
CPU time 0.98 seconds
Started Jul 13 04:46:39 PM PDT 24
Finished Jul 13 04:46:41 PM PDT 24
Peak memory 208404 kb
Host smart-37b56c38-61eb-4c1e-ae8f-97315e9af70f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256804185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2256804185
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2340225264
Short name T88
Test name
Test status
Simulation time 52868287 ps
CPU time 1.03 seconds
Started Jul 13 04:46:59 PM PDT 24
Finished Jul 13 04:47:01 PM PDT 24
Peak memory 208444 kb
Host smart-344801ad-9058-479d-98bf-8d992cf89c45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340225264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2340225264
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.385067659
Short name T283
Test name
Test status
Simulation time 1168854346 ps
CPU time 11.94 seconds
Started Jul 13 04:46:59 PM PDT 24
Finished Jul 13 04:47:12 PM PDT 24
Peak memory 217644 kb
Host smart-e621221a-d4cc-4d6e-8d47-7912c25f72f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385067659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.385067659
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.1361222418
Short name T574
Test name
Test status
Simulation time 3670972641 ps
CPU time 6.53 seconds
Started Jul 13 04:46:45 PM PDT 24
Finished Jul 13 04:46:52 PM PDT 24
Peak memory 217132 kb
Host smart-de7fa9f8-7236-4ece-bbe4-6b54e03f7136
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361222418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1361222418
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2719341830
Short name T210
Test name
Test status
Simulation time 8383772573 ps
CPU time 50.35 seconds
Started Jul 13 04:46:45 PM PDT 24
Finished Jul 13 04:47:36 PM PDT 24
Peak memory 218412 kb
Host smart-b4106021-5da3-4cf7-992f-d7a7560466fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719341830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2719341830
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3199007132
Short name T801
Test name
Test status
Simulation time 686575972 ps
CPU time 9.71 seconds
Started Jul 13 04:46:45 PM PDT 24
Finished Jul 13 04:46:55 PM PDT 24
Peak memory 217612 kb
Host smart-dbef6ece-ef1f-4c2e-a29c-bc47358b842a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199007132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3199007132
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3636607479
Short name T566
Test name
Test status
Simulation time 687140877 ps
CPU time 5.83 seconds
Started Jul 13 04:46:59 PM PDT 24
Finished Jul 13 04:47:06 PM PDT 24
Peak memory 217060 kb
Host smart-299577e1-f05b-499c-b23c-eaf658f11e10
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636607479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.3636607479
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1245383525
Short name T447
Test name
Test status
Simulation time 3291982510 ps
CPU time 44.07 seconds
Started Jul 13 04:46:48 PM PDT 24
Finished Jul 13 04:47:34 PM PDT 24
Peak memory 283188 kb
Host smart-a04a1283-ee60-4206-bf13-6bd035d979e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245383525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1245383525
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1054195646
Short name T209
Test name
Test status
Simulation time 401270185 ps
CPU time 18.87 seconds
Started Jul 13 04:46:46 PM PDT 24
Finished Jul 13 04:47:07 PM PDT 24
Peak memory 250416 kb
Host smart-845b68c7-e8aa-4fcb-bd16-2d44187ee0ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054195646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1054195646
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.1227304789
Short name T2
Test name
Test status
Simulation time 49995343 ps
CPU time 3.06 seconds
Started Jul 13 04:46:48 PM PDT 24
Finished Jul 13 04:46:53 PM PDT 24
Peak memory 217720 kb
Host smart-645585d4-066c-46da-b18a-107d7633aa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227304789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1227304789
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.3520543384
Short name T681
Test name
Test status
Simulation time 2685300692 ps
CPU time 11.73 seconds
Started Jul 13 04:46:46 PM PDT 24
Finished Jul 13 04:47:00 PM PDT 24
Peak memory 225584 kb
Host smart-6f13ea4d-1d75-4f06-acac-7e889af5cc1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520543384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3520543384
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.4109543079
Short name T722
Test name
Test status
Simulation time 278234021 ps
CPU time 11.94 seconds
Started Jul 13 04:46:45 PM PDT 24
Finished Jul 13 04:46:57 PM PDT 24
Peak memory 225440 kb
Host smart-9b2a6c5a-170c-4654-a74d-3c6a973cbe76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109543079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.4109543079
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1498114780
Short name T664
Test name
Test status
Simulation time 247624115 ps
CPU time 10.54 seconds
Started Jul 13 04:46:49 PM PDT 24
Finished Jul 13 04:47:01 PM PDT 24
Peak memory 225524 kb
Host smart-835f7778-da7a-4528-be29-1625a2fea4fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498114780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1498114780
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.639793340
Short name T396
Test name
Test status
Simulation time 465584654 ps
CPU time 9.37 seconds
Started Jul 13 04:46:47 PM PDT 24
Finished Jul 13 04:46:59 PM PDT 24
Peak memory 217636 kb
Host smart-3484eb43-cde7-41e5-83ac-ac016c0f3481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639793340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.639793340
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3406722164
Short name T766
Test name
Test status
Simulation time 31933583 ps
CPU time 1.39 seconds
Started Jul 13 04:46:46 PM PDT 24
Finished Jul 13 04:46:50 PM PDT 24
Peak memory 213492 kb
Host smart-67922335-a0a8-4c5d-a71d-13efc8a893d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406722164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3406722164
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.1467033278
Short name T368
Test name
Test status
Simulation time 1045374425 ps
CPU time 22.99 seconds
Started Jul 13 04:46:38 PM PDT 24
Finished Jul 13 04:47:02 PM PDT 24
Peak memory 250476 kb
Host smart-b8558c9f-dd3c-4a26-893c-ac9e97f6ed3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467033278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1467033278
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.485758432
Short name T362
Test name
Test status
Simulation time 291387720 ps
CPU time 3.37 seconds
Started Jul 13 04:46:41 PM PDT 24
Finished Jul 13 04:46:45 PM PDT 24
Peak memory 225808 kb
Host smart-32b917c1-52ac-4bf8-9f9c-7c32923568a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485758432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.485758432
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1944262169
Short name T41
Test name
Test status
Simulation time 5000982376 ps
CPU time 75.03 seconds
Started Jul 13 04:46:45 PM PDT 24
Finished Jul 13 04:48:00 PM PDT 24
Peak memory 234172 kb
Host smart-a87c1621-e5b3-4522-a1b3-1ecc38f4a7e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944262169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1944262169
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.3417974227
Short name T819
Test name
Test status
Simulation time 23071020538 ps
CPU time 375.6 seconds
Started Jul 13 04:46:46 PM PDT 24
Finished Jul 13 04:53:04 PM PDT 24
Peak memory 283420 kb
Host smart-efdc7219-215f-480c-a42f-ee3f0f930a1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3417974227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.3417974227
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1677037845
Short name T471
Test name
Test status
Simulation time 24100850 ps
CPU time 1 seconds
Started Jul 13 04:46:42 PM PDT 24
Finished Jul 13 04:46:44 PM PDT 24
Peak memory 208504 kb
Host smart-e14969d5-9a44-40a0-999d-41194343d505
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677037845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1677037845
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.515420257
Short name T388
Test name
Test status
Simulation time 66331721 ps
CPU time 0.95 seconds
Started Jul 13 04:46:49 PM PDT 24
Finished Jul 13 04:46:52 PM PDT 24
Peak memory 208572 kb
Host smart-bb1c237d-4d3d-4e9e-82ee-8ce7eb6a189c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515420257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.515420257
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2364561750
Short name T507
Test name
Test status
Simulation time 1418873107 ps
CPU time 17.96 seconds
Started Jul 13 04:46:48 PM PDT 24
Finished Jul 13 04:47:08 PM PDT 24
Peak memory 217664 kb
Host smart-b4d456e9-0522-43bd-98dd-c015d8749784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364561750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2364561750
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1293492431
Short name T647
Test name
Test status
Simulation time 266036586 ps
CPU time 4.4 seconds
Started Jul 13 04:46:46 PM PDT 24
Finished Jul 13 04:46:52 PM PDT 24
Peak memory 217192 kb
Host smart-0f8717d1-7a6e-41da-a4bf-b458d705f58d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293492431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1293492431
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.5082886
Short name T535
Test name
Test status
Simulation time 32159616678 ps
CPU time 93.88 seconds
Started Jul 13 04:46:45 PM PDT 24
Finished Jul 13 04:48:21 PM PDT 24
Peak memory 219128 kb
Host smart-a7b53d93-05ad-47f2-b664-7b2dd8a97b66
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5082886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc
_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_erro
rs.5082886
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.261957627
Short name T287
Test name
Test status
Simulation time 1473813799 ps
CPU time 10.5 seconds
Started Jul 13 04:46:44 PM PDT 24
Finished Jul 13 04:46:55 PM PDT 24
Peak memory 222368 kb
Host smart-f9f1bc00-5a3d-4cea-84ac-9fd8245bd5ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261957627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.261957627
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3267189022
Short name T18
Test name
Test status
Simulation time 973458258 ps
CPU time 7.73 seconds
Started Jul 13 04:46:46 PM PDT 24
Finished Jul 13 04:46:55 PM PDT 24
Peak memory 217004 kb
Host smart-edc4c7dc-89d4-4248-9a20-9967c7cf842d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267189022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3267189022
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2675343342
Short name T234
Test name
Test status
Simulation time 49745392090 ps
CPU time 63.27 seconds
Started Jul 13 04:46:46 PM PDT 24
Finished Jul 13 04:47:52 PM PDT 24
Peak memory 279580 kb
Host smart-031ce3d6-2440-4d17-aba5-7f6e7d335565
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675343342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2675343342
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2669350192
Short name T143
Test name
Test status
Simulation time 2030261454 ps
CPU time 22.69 seconds
Started Jul 13 04:46:59 PM PDT 24
Finished Jul 13 04:47:23 PM PDT 24
Peak memory 250276 kb
Host smart-03be7774-c371-416e-b807-e5e961511fc1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669350192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2669350192
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1315537534
Short name T380
Test name
Test status
Simulation time 65023540 ps
CPU time 2.3 seconds
Started Jul 13 04:46:46 PM PDT 24
Finished Jul 13 04:46:50 PM PDT 24
Peak memory 217828 kb
Host smart-47fa7f96-e763-4ab1-a154-55c8c471f1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315537534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1315537534
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2436877446
Short name T706
Test name
Test status
Simulation time 221196840 ps
CPU time 9.66 seconds
Started Jul 13 04:46:44 PM PDT 24
Finished Jul 13 04:46:54 PM PDT 24
Peak memory 217652 kb
Host smart-17cd6c9b-69f6-45ef-b3b0-05e2782255f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436877446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2436877446
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2567714990
Short name T260
Test name
Test status
Simulation time 323071931 ps
CPU time 10.69 seconds
Started Jul 13 04:46:47 PM PDT 24
Finished Jul 13 04:47:00 PM PDT 24
Peak memory 225332 kb
Host smart-cdc7fb08-9021-423d-b805-5649fc955d9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567714990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2567714990
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.369361832
Short name T354
Test name
Test status
Simulation time 1574598947 ps
CPU time 13.67 seconds
Started Jul 13 04:46:47 PM PDT 24
Finished Jul 13 04:47:03 PM PDT 24
Peak memory 217608 kb
Host smart-3ba4b157-2252-4d96-86d9-eefc29feae5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369361832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.369361832
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3062907942
Short name T606
Test name
Test status
Simulation time 622081667 ps
CPU time 8.45 seconds
Started Jul 13 04:46:46 PM PDT 24
Finished Jul 13 04:46:57 PM PDT 24
Peak memory 225204 kb
Host smart-b59e4e5e-71c1-43ef-9779-553842b7353a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062907942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3062907942
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2126436382
Short name T435
Test name
Test status
Simulation time 49542053 ps
CPU time 2.62 seconds
Started Jul 13 04:46:59 PM PDT 24
Finished Jul 13 04:47:03 PM PDT 24
Peak memory 214164 kb
Host smart-80419bf1-0cc7-4bf3-8aa2-49c0d0cea6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126436382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2126436382
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2382350175
Short name T505
Test name
Test status
Simulation time 1196101828 ps
CPU time 27.32 seconds
Started Jul 13 04:46:47 PM PDT 24
Finished Jul 13 04:47:17 PM PDT 24
Peak memory 250412 kb
Host smart-56b16faf-1c70-4034-abd6-8d231f974dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382350175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2382350175
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1237003320
Short name T716
Test name
Test status
Simulation time 351402987 ps
CPU time 7.96 seconds
Started Jul 13 04:46:47 PM PDT 24
Finished Jul 13 04:46:57 PM PDT 24
Peak memory 250452 kb
Host smart-1b317c61-e1e7-4b04-bd26-63b61f7c26d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237003320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1237003320
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.2150629049
Short name T724
Test name
Test status
Simulation time 2854690496 ps
CPU time 105.83 seconds
Started Jul 13 04:46:46 PM PDT 24
Finished Jul 13 04:48:35 PM PDT 24
Peak memory 250532 kb
Host smart-37519c3e-6d1a-4088-a2cc-61d73cfb838a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150629049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.2150629049
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.683057680
Short name T853
Test name
Test status
Simulation time 32767236 ps
CPU time 0.94 seconds
Started Jul 13 04:46:47 PM PDT 24
Finished Jul 13 04:46:51 PM PDT 24
Peak memory 211264 kb
Host smart-8110b1b4-b77b-466a-b9bd-52fd15c71a42
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683057680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.683057680
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2151955807
Short name T763
Test name
Test status
Simulation time 46388014 ps
CPU time 1.31 seconds
Started Jul 13 04:46:57 PM PDT 24
Finished Jul 13 04:46:59 PM PDT 24
Peak memory 208548 kb
Host smart-4d663447-4fd5-4a95-ac5a-0c17f9108858
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151955807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2151955807
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2449671971
Short name T486
Test name
Test status
Simulation time 259444668 ps
CPU time 9.65 seconds
Started Jul 13 04:46:46 PM PDT 24
Finished Jul 13 04:46:59 PM PDT 24
Peak memory 225480 kb
Host smart-12118de7-8dba-4a9d-a780-e1ca9aae28c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449671971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2449671971
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1955341835
Short name T823
Test name
Test status
Simulation time 367295341 ps
CPU time 2.75 seconds
Started Jul 13 04:46:47 PM PDT 24
Finished Jul 13 04:46:53 PM PDT 24
Peak memory 216704 kb
Host smart-20780a48-7b46-4725-b899-a9800c9fd8cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955341835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1955341835
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1652543158
Short name T796
Test name
Test status
Simulation time 60375860945 ps
CPU time 39.67 seconds
Started Jul 13 04:46:59 PM PDT 24
Finished Jul 13 04:47:39 PM PDT 24
Peak memory 218140 kb
Host smart-3a2fc174-ed42-4ab2-a688-5d03bca305e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652543158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1652543158
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3805121357
Short name T829
Test name
Test status
Simulation time 1081677906 ps
CPU time 16.19 seconds
Started Jul 13 04:46:47 PM PDT 24
Finished Jul 13 04:47:06 PM PDT 24
Peak memory 217756 kb
Host smart-bafea4c7-d381-48e4-a544-4e1b788a09b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805121357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3805121357
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3854479601
Short name T521
Test name
Test status
Simulation time 1316720857 ps
CPU time 8.38 seconds
Started Jul 13 04:46:46 PM PDT 24
Finished Jul 13 04:46:58 PM PDT 24
Peak memory 217024 kb
Host smart-dc14185b-92b8-4301-9787-7e9cf8796cd3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854479601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3854479601
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1400121270
Short name T92
Test name
Test status
Simulation time 2794770514 ps
CPU time 48.71 seconds
Started Jul 13 04:46:46 PM PDT 24
Finished Jul 13 04:47:38 PM PDT 24
Peak memory 275460 kb
Host smart-cb0c28ae-544f-434e-9754-10e05f4c97c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400121270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1400121270
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.222025901
Short name T596
Test name
Test status
Simulation time 860650306 ps
CPU time 24.52 seconds
Started Jul 13 04:46:48 PM PDT 24
Finished Jul 13 04:47:15 PM PDT 24
Peak memory 221616 kb
Host smart-b3130c5e-8e27-4c49-b0e7-b4395b860563
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222025901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.222025901
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3128767094
Short name T754
Test name
Test status
Simulation time 194815704 ps
CPU time 4.61 seconds
Started Jul 13 04:46:45 PM PDT 24
Finished Jul 13 04:46:51 PM PDT 24
Peak memory 217508 kb
Host smart-e07b9492-f665-4bda-a470-0fb46f8e19bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128767094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3128767094
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.216164633
Short name T602
Test name
Test status
Simulation time 1320820981 ps
CPU time 24.45 seconds
Started Jul 13 04:46:48 PM PDT 24
Finished Jul 13 04:47:15 PM PDT 24
Peak memory 225464 kb
Host smart-dbb6d05a-c2bd-494f-b53e-0ffe13f02ea0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216164633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.216164633
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.4119271897
Short name T765
Test name
Test status
Simulation time 1085061552 ps
CPU time 12.3 seconds
Started Jul 13 04:46:59 PM PDT 24
Finished Jul 13 04:47:12 PM PDT 24
Peak memory 217632 kb
Host smart-01988f42-51bc-4243-8490-1584fa7eba49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119271897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.4119271897
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.177048785
Short name T494
Test name
Test status
Simulation time 670664409 ps
CPU time 5.89 seconds
Started Jul 13 04:46:58 PM PDT 24
Finished Jul 13 04:47:04 PM PDT 24
Peak memory 224248 kb
Host smart-0ad71e4e-6707-41ca-9776-4aa4b96e684e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177048785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.177048785
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3421552772
Short name T54
Test name
Test status
Simulation time 511431697 ps
CPU time 10.05 seconds
Started Jul 13 04:46:48 PM PDT 24
Finished Jul 13 04:47:00 PM PDT 24
Peak memory 225456 kb
Host smart-38013c4b-231c-4614-8e40-af885abb6ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421552772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3421552772
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3666760397
Short name T65
Test name
Test status
Simulation time 36504802 ps
CPU time 2.22 seconds
Started Jul 13 04:46:48 PM PDT 24
Finished Jul 13 04:46:52 PM PDT 24
Peak memory 217112 kb
Host smart-86bd45b5-2444-4218-bec6-69b98087cb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666760397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3666760397
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.116518299
Short name T187
Test name
Test status
Simulation time 1602199017 ps
CPU time 28.57 seconds
Started Jul 13 04:46:47 PM PDT 24
Finished Jul 13 04:47:19 PM PDT 24
Peak memory 250420 kb
Host smart-fc594d2e-1e52-4fa3-8de5-eddaef9c15c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116518299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.116518299
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2107862579
Short name T422
Test name
Test status
Simulation time 164159561 ps
CPU time 7.17 seconds
Started Jul 13 04:46:47 PM PDT 24
Finished Jul 13 04:46:57 PM PDT 24
Peak memory 250404 kb
Host smart-665be3d9-9e76-43ca-a1b5-547fa225597e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107862579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2107862579
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.749870746
Short name T814
Test name
Test status
Simulation time 4360930450 ps
CPU time 26.45 seconds
Started Jul 13 04:46:57 PM PDT 24
Finished Jul 13 04:47:25 PM PDT 24
Peak memory 225596 kb
Host smart-f913322a-6427-4b89-8efe-a12246fe41e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749870746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.749870746
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2044841699
Short name T499
Test name
Test status
Simulation time 13831170 ps
CPU time 1.14 seconds
Started Jul 13 04:46:47 PM PDT 24
Finished Jul 13 04:46:51 PM PDT 24
Peak memory 211304 kb
Host smart-f476d95b-0e30-462c-a7b8-7018c89e7d28
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044841699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.2044841699
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1270316309
Short name T397
Test name
Test status
Simulation time 31206195 ps
CPU time 0.92 seconds
Started Jul 13 04:46:56 PM PDT 24
Finished Jul 13 04:46:57 PM PDT 24
Peak memory 208428 kb
Host smart-7497a248-e808-49fa-9df1-c54cfb3a1531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270316309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1270316309
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1875957014
Short name T776
Test name
Test status
Simulation time 2657636085 ps
CPU time 15.45 seconds
Started Jul 13 04:46:58 PM PDT 24
Finished Jul 13 04:47:14 PM PDT 24
Peak memory 225540 kb
Host smart-4725ddb7-d0c1-4485-8aa3-2f70b4fb9428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875957014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1875957014
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1836494821
Short name T6
Test name
Test status
Simulation time 1117670337 ps
CPU time 4.63 seconds
Started Jul 13 04:46:57 PM PDT 24
Finished Jul 13 04:47:03 PM PDT 24
Peak memory 217080 kb
Host smart-86947eae-786a-432a-aa2a-e752b2812d72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836494821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1836494821
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3583111486
Short name T408
Test name
Test status
Simulation time 1633803537 ps
CPU time 29.27 seconds
Started Jul 13 04:46:57 PM PDT 24
Finished Jul 13 04:47:27 PM PDT 24
Peak memory 217652 kb
Host smart-fdbb9cc8-bbfb-4e27-b921-eba9cb4c7a10
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583111486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3583111486
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.71371933
Short name T371
Test name
Test status
Simulation time 2449159918 ps
CPU time 17.29 seconds
Started Jul 13 04:46:56 PM PDT 24
Finished Jul 13 04:47:14 PM PDT 24
Peak memory 217672 kb
Host smart-6291718f-6a93-4de7-8c1e-b06b5939d63b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71371933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_
prog_failure.71371933
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.4088190283
Short name T618
Test name
Test status
Simulation time 350392859 ps
CPU time 9.8 seconds
Started Jul 13 04:47:01 PM PDT 24
Finished Jul 13 04:47:11 PM PDT 24
Peak memory 217024 kb
Host smart-eff4aa96-6571-493a-baa0-f175fb1746ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088190283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.4088190283
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.26936512
Short name T636
Test name
Test status
Simulation time 1793629279 ps
CPU time 54.61 seconds
Started Jul 13 04:46:58 PM PDT 24
Finished Jul 13 04:47:53 PM PDT 24
Peak memory 267632 kb
Host smart-3968a2f6-356c-48ff-b2b4-00db00037167
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26936512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_state_failure.26936512
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3419549779
Short name T502
Test name
Test status
Simulation time 482974483 ps
CPU time 23.21 seconds
Started Jul 13 04:46:57 PM PDT 24
Finished Jul 13 04:47:20 PM PDT 24
Peak memory 250392 kb
Host smart-2e1dfddc-cf5e-442e-90a4-6e54715619a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419549779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3419549779
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2415906092
Short name T762
Test name
Test status
Simulation time 294329095 ps
CPU time 4.05 seconds
Started Jul 13 04:46:58 PM PDT 24
Finished Jul 13 04:47:03 PM PDT 24
Peak memory 217660 kb
Host smart-e240f80f-6561-482d-bf07-4e19067de487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415906092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2415906092
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.855907701
Short name T820
Test name
Test status
Simulation time 4103519151 ps
CPU time 19.21 seconds
Started Jul 13 04:46:57 PM PDT 24
Finished Jul 13 04:47:17 PM PDT 24
Peak memory 225548 kb
Host smart-3b0e5cb0-e9b6-471b-9875-410d0b8db394
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855907701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.855907701
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3903803175
Short name T586
Test name
Test status
Simulation time 1166911009 ps
CPU time 12.97 seconds
Started Jul 13 04:46:55 PM PDT 24
Finished Jul 13 04:47:09 PM PDT 24
Peak memory 225440 kb
Host smart-e648d663-9aef-4647-b3a8-b5b60759179c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903803175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3903803175
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2186744846
Short name T236
Test name
Test status
Simulation time 984387268 ps
CPU time 15.05 seconds
Started Jul 13 04:46:56 PM PDT 24
Finished Jul 13 04:47:11 PM PDT 24
Peak memory 217616 kb
Host smart-7e638b9a-9e1e-474e-9c6e-085065259f2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186744846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2186744846
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1052936810
Short name T728
Test name
Test status
Simulation time 1680098288 ps
CPU time 8.01 seconds
Started Jul 13 04:46:57 PM PDT 24
Finished Jul 13 04:47:06 PM PDT 24
Peak memory 225500 kb
Host smart-264bd200-1f07-4939-8401-33e70da80406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052936810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1052936810
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3953935420
Short name T840
Test name
Test status
Simulation time 123515219 ps
CPU time 5.33 seconds
Started Jul 13 04:47:01 PM PDT 24
Finished Jul 13 04:47:07 PM PDT 24
Peak memory 217084 kb
Host smart-35c16cd1-9c37-4a77-9270-2d40644ca2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953935420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3953935420
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3605202572
Short name T335
Test name
Test status
Simulation time 233896065 ps
CPU time 21.69 seconds
Started Jul 13 04:47:00 PM PDT 24
Finished Jul 13 04:47:23 PM PDT 24
Peak memory 250424 kb
Host smart-04b56798-bc08-49b5-bed5-ba2c582b986f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605202572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3605202572
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3960947294
Short name T277
Test name
Test status
Simulation time 139172177 ps
CPU time 7.48 seconds
Started Jul 13 04:46:58 PM PDT 24
Finished Jul 13 04:47:06 PM PDT 24
Peak memory 250668 kb
Host smart-672af567-8eb1-4ccf-bb89-f1e0ac8b517a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960947294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3960947294
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3338413701
Short name T229
Test name
Test status
Simulation time 31149232179 ps
CPU time 259.45 seconds
Started Jul 13 04:47:00 PM PDT 24
Finished Jul 13 04:51:20 PM PDT 24
Peak memory 277588 kb
Host smart-6686ad0a-6340-4da1-b2cc-e7ce6a65becf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338413701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3338413701
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.659340922
Short name T131
Test name
Test status
Simulation time 6572305320 ps
CPU time 309.59 seconds
Started Jul 13 04:46:57 PM PDT 24
Finished Jul 13 04:52:08 PM PDT 24
Peak memory 479968 kb
Host smart-0fe8ceed-d5d5-4c69-a1bd-6a1427c0ef66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=659340922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.659340922
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.464793687
Short name T68
Test name
Test status
Simulation time 18277891 ps
CPU time 1.05 seconds
Started Jul 13 04:46:59 PM PDT 24
Finished Jul 13 04:47:01 PM PDT 24
Peak memory 212240 kb
Host smart-cb322030-fa53-4773-9aa5-43b6c174e8ef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464793687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.464793687
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1946506970
Short name T633
Test name
Test status
Simulation time 16214905 ps
CPU time 0.91 seconds
Started Jul 13 04:47:12 PM PDT 24
Finished Jul 13 04:47:14 PM PDT 24
Peak memory 208416 kb
Host smart-44c69451-ca47-4947-802f-fa9b254e2e05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946506970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1946506970
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3016940385
Short name T40
Test name
Test status
Simulation time 404976113 ps
CPU time 13.55 seconds
Started Jul 13 04:46:55 PM PDT 24
Finished Jul 13 04:47:09 PM PDT 24
Peak memory 217656 kb
Host smart-a7c9c2e8-edad-4467-9488-5bd1d762b6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016940385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3016940385
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.2219713242
Short name T870
Test name
Test status
Simulation time 1064289228 ps
CPU time 4.45 seconds
Started Jul 13 04:47:11 PM PDT 24
Finished Jul 13 04:47:17 PM PDT 24
Peak memory 217164 kb
Host smart-7d17b91a-5c1d-4af1-b88e-3604bae21b4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219713242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2219713242
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2215322245
Short name T594
Test name
Test status
Simulation time 4331502239 ps
CPU time 115.65 seconds
Started Jul 13 04:47:09 PM PDT 24
Finished Jul 13 04:49:05 PM PDT 24
Peak memory 218280 kb
Host smart-23158539-47d3-4aaa-afb9-1273014158a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215322245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2215322245
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3801002180
Short name T341
Test name
Test status
Simulation time 69506512 ps
CPU time 3.06 seconds
Started Jul 13 04:47:09 PM PDT 24
Finished Jul 13 04:47:13 PM PDT 24
Peak memory 217612 kb
Host smart-a70b30e8-921f-477a-8d8b-849e45d55bdd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801002180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3801002180
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2643692639
Short name T832
Test name
Test status
Simulation time 893345565 ps
CPU time 5.66 seconds
Started Jul 13 04:46:53 PM PDT 24
Finished Jul 13 04:46:59 PM PDT 24
Peak memory 217000 kb
Host smart-fbe5b0b5-4a60-44d9-84c9-3915baeeec84
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643692639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2643692639
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1958740874
Short name T185
Test name
Test status
Simulation time 41706373363 ps
CPU time 50.08 seconds
Started Jul 13 04:46:56 PM PDT 24
Finished Jul 13 04:47:47 PM PDT 24
Peak memory 271224 kb
Host smart-31c1a794-6877-469d-83a7-11797266241c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958740874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1958740874
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2858701466
Short name T278
Test name
Test status
Simulation time 324041308 ps
CPU time 16.11 seconds
Started Jul 13 04:47:16 PM PDT 24
Finished Jul 13 04:47:34 PM PDT 24
Peak memory 250384 kb
Host smart-5c62297c-30a3-4296-b97e-476a9edb1835
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858701466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2858701466
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3510455887
Short name T797
Test name
Test status
Simulation time 65474088 ps
CPU time 1.75 seconds
Started Jul 13 04:46:56 PM PDT 24
Finished Jul 13 04:46:58 PM PDT 24
Peak memory 221540 kb
Host smart-d75944a7-9a86-4c92-8ee5-d4f59ac0daee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510455887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3510455887
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.3948747413
Short name T444
Test name
Test status
Simulation time 836097689 ps
CPU time 19.54 seconds
Started Jul 13 04:47:08 PM PDT 24
Finished Jul 13 04:47:29 PM PDT 24
Peak memory 219240 kb
Host smart-a5cb8cbe-8848-4d2c-aee9-0b394f5fb655
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948747413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3948747413
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3650030347
Short name T298
Test name
Test status
Simulation time 267193020 ps
CPU time 13.74 seconds
Started Jul 13 04:47:11 PM PDT 24
Finished Jul 13 04:47:26 PM PDT 24
Peak memory 225420 kb
Host smart-b2482200-e9de-423f-94ed-1bb2fa053907
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650030347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3650030347
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3881292104
Short name T221
Test name
Test status
Simulation time 561751647 ps
CPU time 11.62 seconds
Started Jul 13 04:47:10 PM PDT 24
Finished Jul 13 04:47:23 PM PDT 24
Peak memory 225436 kb
Host smart-0e6e0704-bc55-48d9-83b1-827d00fb6413
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881292104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3881292104
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1441442846
Short name T551
Test name
Test status
Simulation time 350499613 ps
CPU time 12.46 seconds
Started Jul 13 04:46:57 PM PDT 24
Finished Jul 13 04:47:10 PM PDT 24
Peak memory 225516 kb
Host smart-ae0e6d54-4e63-4075-9d3e-45c67c0bd587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441442846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1441442846
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2132758863
Short name T544
Test name
Test status
Simulation time 377855566 ps
CPU time 2.99 seconds
Started Jul 13 04:46:56 PM PDT 24
Finished Jul 13 04:46:59 PM PDT 24
Peak memory 222220 kb
Host smart-3ce8949d-8bc7-4eed-8e29-e6fbbf9f526b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132758863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2132758863
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2654988604
Short name T717
Test name
Test status
Simulation time 274514269 ps
CPU time 24.68 seconds
Started Jul 13 04:46:55 PM PDT 24
Finished Jul 13 04:47:21 PM PDT 24
Peak memory 250472 kb
Host smart-5efb0a84-e005-4654-9e5e-9a3c88db918e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654988604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2654988604
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.686735751
Short name T635
Test name
Test status
Simulation time 46577645 ps
CPU time 6.32 seconds
Started Jul 13 04:46:59 PM PDT 24
Finished Jul 13 04:47:06 PM PDT 24
Peak memory 246432 kb
Host smart-960dfdc1-20fc-411d-bd34-5b54337784dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686735751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.686735751
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2997950405
Short name T836
Test name
Test status
Simulation time 14538542989 ps
CPU time 163.59 seconds
Started Jul 13 04:47:14 PM PDT 24
Finished Jul 13 04:49:58 PM PDT 24
Peak memory 266876 kb
Host smart-08a3db59-842e-4acf-bad3-2e2a94cf10f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997950405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2997950405
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2402810074
Short name T250
Test name
Test status
Simulation time 15881508 ps
CPU time 0.91 seconds
Started Jul 13 04:46:55 PM PDT 24
Finished Jul 13 04:46:57 PM PDT 24
Peak memory 208556 kb
Host smart-d85acd7f-b057-4cc1-8aa3-edd94bee4db9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402810074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2402810074
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3212531526
Short name T603
Test name
Test status
Simulation time 84480791 ps
CPU time 1.09 seconds
Started Jul 13 04:47:10 PM PDT 24
Finished Jul 13 04:47:12 PM PDT 24
Peak memory 208384 kb
Host smart-42e77a40-6d6e-4278-a43c-21b146680a1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212531526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3212531526
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1296265900
Short name T557
Test name
Test status
Simulation time 1396418109 ps
CPU time 10.65 seconds
Started Jul 13 04:47:08 PM PDT 24
Finished Jul 13 04:47:19 PM PDT 24
Peak memory 217716 kb
Host smart-45aace45-fc42-4fff-a9a0-50bbced6a1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296265900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1296265900
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.693377181
Short name T154
Test name
Test status
Simulation time 2769757586 ps
CPU time 10.39 seconds
Started Jul 13 04:47:08 PM PDT 24
Finished Jul 13 04:47:19 PM PDT 24
Peak memory 217176 kb
Host smart-318c4651-9f7a-47ee-a2fa-be887d826212
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693377181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.693377181
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2641568220
Short name T320
Test name
Test status
Simulation time 4359169571 ps
CPU time 44.23 seconds
Started Jul 13 04:47:12 PM PDT 24
Finished Jul 13 04:47:57 PM PDT 24
Peak memory 217724 kb
Host smart-8ad88eba-0c23-4635-99d4-c43f385feb92
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641568220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2641568220
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2326102619
Short name T755
Test name
Test status
Simulation time 2369503958 ps
CPU time 9.3 seconds
Started Jul 13 04:47:11 PM PDT 24
Finished Jul 13 04:47:22 PM PDT 24
Peak memory 224960 kb
Host smart-1f8f3e14-c4f7-4e3a-9469-83ff047f1f83
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326102619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2326102619
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3018459001
Short name T4
Test name
Test status
Simulation time 143410290 ps
CPU time 4.63 seconds
Started Jul 13 04:47:11 PM PDT 24
Finished Jul 13 04:47:17 PM PDT 24
Peak memory 217076 kb
Host smart-423278df-47c8-4c36-9fcb-0ffe054ece6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018459001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3018459001
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3773537259
Short name T372
Test name
Test status
Simulation time 1699931904 ps
CPU time 70.18 seconds
Started Jul 13 04:47:06 PM PDT 24
Finished Jul 13 04:48:17 PM PDT 24
Peak memory 274984 kb
Host smart-6a49806d-6fab-423f-ad9c-5fea912f5902
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773537259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3773537259
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.518674987
Short name T481
Test name
Test status
Simulation time 4399299755 ps
CPU time 10.57 seconds
Started Jul 13 04:47:12 PM PDT 24
Finished Jul 13 04:47:24 PM PDT 24
Peak memory 223072 kb
Host smart-d12d75cd-989a-4c67-b9f5-89f3911be4d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518674987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.518674987
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.4130930058
Short name T666
Test name
Test status
Simulation time 1004651156 ps
CPU time 3.41 seconds
Started Jul 13 04:47:09 PM PDT 24
Finished Jul 13 04:47:13 PM PDT 24
Peak memory 222132 kb
Host smart-7d609e3d-ccd4-4622-8f4f-7f589d04fc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130930058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.4130930058
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1108902703
Short name T770
Test name
Test status
Simulation time 691566251 ps
CPU time 13.33 seconds
Started Jul 13 04:47:15 PM PDT 24
Finished Jul 13 04:47:29 PM PDT 24
Peak memory 225472 kb
Host smart-e960a3c4-dee4-4803-944c-84b30417dc3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108902703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1108902703
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1045839165
Short name T654
Test name
Test status
Simulation time 1242456112 ps
CPU time 10.24 seconds
Started Jul 13 04:47:08 PM PDT 24
Finished Jul 13 04:47:19 PM PDT 24
Peak memory 225288 kb
Host smart-a7b2e217-9507-4ad4-96ba-aca711ea99de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045839165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1045839165
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2400818627
Short name T53
Test name
Test status
Simulation time 901015857 ps
CPU time 6.79 seconds
Started Jul 13 04:47:12 PM PDT 24
Finished Jul 13 04:47:20 PM PDT 24
Peak memory 224480 kb
Host smart-c5d9b677-e35f-470e-86ca-d71892bfd37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400818627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2400818627
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3402833893
Short name T311
Test name
Test status
Simulation time 175574493 ps
CPU time 2.47 seconds
Started Jul 13 04:47:10 PM PDT 24
Finished Jul 13 04:47:13 PM PDT 24
Peak memory 213592 kb
Host smart-79441c7c-d5c3-4e84-98d2-d63a35cd75c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402833893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3402833893
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.940150274
Short name T476
Test name
Test status
Simulation time 445429088 ps
CPU time 22.05 seconds
Started Jul 13 04:47:09 PM PDT 24
Finished Jul 13 04:47:32 PM PDT 24
Peak memory 250240 kb
Host smart-7a9292dc-b97e-452b-a463-eb3014dc097e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940150274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.940150274
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.884247614
Short name T64
Test name
Test status
Simulation time 154900012 ps
CPU time 7.74 seconds
Started Jul 13 04:47:12 PM PDT 24
Finished Jul 13 04:47:21 PM PDT 24
Peak memory 249916 kb
Host smart-5babae46-d51e-4387-a3f1-ce6889e19ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884247614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.884247614
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.28516942
Short name T300
Test name
Test status
Simulation time 43551064 ps
CPU time 0.87 seconds
Started Jul 13 04:47:10 PM PDT 24
Finished Jul 13 04:47:12 PM PDT 24
Peak memory 208300 kb
Host smart-103bdf40-00e5-4bbe-9df5-30289e164f22
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28516942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_volatile_unlock_smoke.28516942
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.776043799
Short name T483
Test name
Test status
Simulation time 22555005 ps
CPU time 1.03 seconds
Started Jul 13 04:46:00 PM PDT 24
Finished Jul 13 04:46:01 PM PDT 24
Peak memory 208456 kb
Host smart-49033d45-06e1-4e09-bca1-f5811486fcc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776043799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.776043799
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1802433673
Short name T432
Test name
Test status
Simulation time 27781369 ps
CPU time 0.91 seconds
Started Jul 13 04:46:00 PM PDT 24
Finished Jul 13 04:46:01 PM PDT 24
Peak memory 208340 kb
Host smart-82d034a6-c5d4-4b1a-90b9-92a09e03133e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802433673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1802433673
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2077985805
Short name T474
Test name
Test status
Simulation time 1395380446 ps
CPU time 13.93 seconds
Started Jul 13 04:45:51 PM PDT 24
Finished Jul 13 04:46:06 PM PDT 24
Peak memory 217656 kb
Host smart-159d22f7-219e-4952-b4bd-376724b98342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077985805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2077985805
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.3162616766
Short name T564
Test name
Test status
Simulation time 319285015 ps
CPU time 8.27 seconds
Started Jul 13 04:45:54 PM PDT 24
Finished Jul 13 04:46:03 PM PDT 24
Peak memory 216584 kb
Host smart-5629a833-10e9-47ee-adeb-cf8a9c78613c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162616766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.3162616766
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2053216936
Short name T479
Test name
Test status
Simulation time 15849370795 ps
CPU time 25.22 seconds
Started Jul 13 04:45:55 PM PDT 24
Finished Jul 13 04:46:21 PM PDT 24
Peak memory 218304 kb
Host smart-e83c1bd1-bd77-4cf1-a35b-79e63de20b33
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053216936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2053216936
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.203766783
Short name T274
Test name
Test status
Simulation time 375838063 ps
CPU time 5.41 seconds
Started Jul 13 04:45:53 PM PDT 24
Finished Jul 13 04:45:59 PM PDT 24
Peak memory 217112 kb
Host smart-9e1b3811-1dd9-4ee5-b106-2ae340ab624c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203766783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.203766783
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2711767887
Short name T771
Test name
Test status
Simulation time 502003767 ps
CPU time 3.63 seconds
Started Jul 13 04:45:51 PM PDT 24
Finished Jul 13 04:45:56 PM PDT 24
Peak memory 217544 kb
Host smart-e4d5a5e2-c6c5-4a15-9201-60cfe30a9ebc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711767887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2711767887
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2520448697
Short name T282
Test name
Test status
Simulation time 903950344 ps
CPU time 27.87 seconds
Started Jul 13 04:45:53 PM PDT 24
Finished Jul 13 04:46:22 PM PDT 24
Peak memory 217000 kb
Host smart-3e112850-5cae-4778-aa66-4028bede0dd8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520448697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2520448697
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.596950590
Short name T351
Test name
Test status
Simulation time 348966776 ps
CPU time 9.56 seconds
Started Jul 13 04:45:52 PM PDT 24
Finished Jul 13 04:46:03 PM PDT 24
Peak memory 217068 kb
Host smart-ea399b12-b133-4c13-8a39-384d7978d88a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596950590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.596950590
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.771868163
Short name T525
Test name
Test status
Simulation time 9775501733 ps
CPU time 94.09 seconds
Started Jul 13 04:45:50 PM PDT 24
Finished Jul 13 04:47:25 PM PDT 24
Peak memory 266900 kb
Host smart-c4249f61-2b94-4da8-936b-6e32fe6f9432
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771868163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.771868163
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.825581044
Short name T799
Test name
Test status
Simulation time 369406214 ps
CPU time 12.65 seconds
Started Jul 13 04:45:51 PM PDT 24
Finished Jul 13 04:46:05 PM PDT 24
Peak memory 250236 kb
Host smart-fbf49989-73a7-4638-b07f-4b0a4e1fd4ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825581044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.825581044
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2321381958
Short name T679
Test name
Test status
Simulation time 42644083 ps
CPU time 2.06 seconds
Started Jul 13 04:45:51 PM PDT 24
Finished Jul 13 04:45:54 PM PDT 24
Peak memory 217732 kb
Host smart-a04d63ef-0d06-4ae6-8671-d6d59cc4cdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321381958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2321381958
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3940356752
Short name T76
Test name
Test status
Simulation time 577771985 ps
CPU time 16.53 seconds
Started Jul 13 04:45:56 PM PDT 24
Finished Jul 13 04:46:13 PM PDT 24
Peak memory 214104 kb
Host smart-8258c218-972b-427f-b388-7fce79e8423c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940356752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3940356752
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1249793451
Short name T85
Test name
Test status
Simulation time 234156761 ps
CPU time 37.82 seconds
Started Jul 13 04:46:00 PM PDT 24
Finished Jul 13 04:46:39 PM PDT 24
Peak memory 284008 kb
Host smart-2176db27-05af-4bba-a8b4-ef4114d4df72
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249793451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1249793451
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.4112036510
Short name T43
Test name
Test status
Simulation time 1938846932 ps
CPU time 11.8 seconds
Started Jul 13 04:45:54 PM PDT 24
Finished Jul 13 04:46:07 PM PDT 24
Peak memory 225492 kb
Host smart-4be8a19c-a4b7-40fb-bc01-df3749b17d1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112036510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.4112036510
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2058425392
Short name T214
Test name
Test status
Simulation time 4296234544 ps
CPU time 23.01 seconds
Started Jul 13 04:45:53 PM PDT 24
Finished Jul 13 04:46:17 PM PDT 24
Peak memory 225452 kb
Host smart-572066a5-c143-4d81-b271-b5f85df41238
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058425392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2058425392
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.30703519
Short name T685
Test name
Test status
Simulation time 1004954523 ps
CPU time 8.61 seconds
Started Jul 13 04:45:58 PM PDT 24
Finished Jul 13 04:46:07 PM PDT 24
Peak memory 225380 kb
Host smart-ed43a589-b679-456d-838f-f9aa796d1796
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30703519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.30703519
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1587512205
Short name T485
Test name
Test status
Simulation time 231080534 ps
CPU time 6.45 seconds
Started Jul 13 04:45:50 PM PDT 24
Finished Jul 13 04:45:58 PM PDT 24
Peak memory 224308 kb
Host smart-cab4d52c-6688-4438-a4e3-ded7094cace3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587512205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1587512205
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3923561815
Short name T251
Test name
Test status
Simulation time 795153727 ps
CPU time 5.62 seconds
Started Jul 13 04:45:51 PM PDT 24
Finished Jul 13 04:45:59 PM PDT 24
Peak memory 217088 kb
Host smart-f78d589d-772a-4cdc-86d5-974bb0c5242f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923561815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3923561815
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.4014327000
Short name T349
Test name
Test status
Simulation time 366063636 ps
CPU time 30.05 seconds
Started Jul 13 04:45:51 PM PDT 24
Finished Jul 13 04:46:22 PM PDT 24
Peak memory 250528 kb
Host smart-ce6cb2f9-a2c5-41aa-84be-d0e098403c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014327000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.4014327000
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2812879226
Short name T578
Test name
Test status
Simulation time 61235155 ps
CPU time 6.45 seconds
Started Jul 13 04:45:54 PM PDT 24
Finished Jul 13 04:46:01 PM PDT 24
Peak memory 248216 kb
Host smart-1a470e4b-a064-4ca9-bb98-ca9a92f76caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812879226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2812879226
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1947242501
Short name T556
Test name
Test status
Simulation time 32937640939 ps
CPU time 166.08 seconds
Started Jul 13 04:45:51 PM PDT 24
Finished Jul 13 04:48:39 PM PDT 24
Peak memory 315968 kb
Host smart-e6d63c04-4349-40be-9388-14afbb213806
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947242501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1947242501
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.890428216
Short name T758
Test name
Test status
Simulation time 25074659 ps
CPU time 1.08 seconds
Started Jul 13 04:45:50 PM PDT 24
Finished Jul 13 04:45:52 PM PDT 24
Peak memory 211200 kb
Host smart-b47f5b74-8bf8-4c95-a455-99afb99d09c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890428216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.890428216
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.978833170
Short name T611
Test name
Test status
Simulation time 22868876 ps
CPU time 0.98 seconds
Started Jul 13 04:47:08 PM PDT 24
Finished Jul 13 04:47:10 PM PDT 24
Peak memory 208424 kb
Host smart-c0a57f27-20e2-412c-b8c0-22e88540a243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978833170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.978833170
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1740363832
Short name T660
Test name
Test status
Simulation time 4224327629 ps
CPU time 12.27 seconds
Started Jul 13 04:47:11 PM PDT 24
Finished Jul 13 04:47:24 PM PDT 24
Peak memory 217720 kb
Host smart-a1ccb223-e1c2-48eb-aeb4-fd2cf84b3135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740363832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1740363832
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.67151981
Short name T638
Test name
Test status
Simulation time 425091660 ps
CPU time 3.62 seconds
Started Jul 13 04:47:10 PM PDT 24
Finished Jul 13 04:47:14 PM PDT 24
Peak memory 216592 kb
Host smart-9a129962-048a-4c84-b108-90b031b0fe14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67151981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.67151981
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1661846507
Short name T743
Test name
Test status
Simulation time 75249870 ps
CPU time 3.19 seconds
Started Jul 13 04:47:10 PM PDT 24
Finished Jul 13 04:47:13 PM PDT 24
Peak memory 221980 kb
Host smart-00395207-63b6-47b8-bcb6-0909049ba7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661846507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1661846507
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.627825580
Short name T852
Test name
Test status
Simulation time 382237104 ps
CPU time 18.18 seconds
Started Jul 13 04:47:11 PM PDT 24
Finished Jul 13 04:47:30 PM PDT 24
Peak memory 218436 kb
Host smart-18303a92-820d-49f5-9040-2ccdddef7c6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627825580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.627825580
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3815936585
Short name T322
Test name
Test status
Simulation time 1863275261 ps
CPU time 12.34 seconds
Started Jul 13 04:47:08 PM PDT 24
Finished Jul 13 04:47:21 PM PDT 24
Peak memory 225384 kb
Host smart-21d13c9b-5745-4386-b099-e8be645c3b77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815936585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3815936585
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1512951777
Short name T687
Test name
Test status
Simulation time 2916454883 ps
CPU time 8.45 seconds
Started Jul 13 04:47:09 PM PDT 24
Finished Jul 13 04:47:18 PM PDT 24
Peak memory 225448 kb
Host smart-ac47edba-c9f3-4a80-b14a-42361e8d4b88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512951777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1512951777
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1740925272
Short name T480
Test name
Test status
Simulation time 785810950 ps
CPU time 8.59 seconds
Started Jul 13 04:47:12 PM PDT 24
Finished Jul 13 04:47:22 PM PDT 24
Peak memory 225424 kb
Host smart-e8c44fa9-0d07-4743-b5a4-01764f02e719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740925272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1740925272
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3335099190
Short name T350
Test name
Test status
Simulation time 581997538 ps
CPU time 4.06 seconds
Started Jul 13 04:47:09 PM PDT 24
Finished Jul 13 04:47:14 PM PDT 24
Peak memory 217156 kb
Host smart-dcc3eaf3-bf0e-46e1-bb16-66bbd4163466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335099190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3335099190
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.558172226
Short name T186
Test name
Test status
Simulation time 225647015 ps
CPU time 20.73 seconds
Started Jul 13 04:47:10 PM PDT 24
Finished Jul 13 04:47:32 PM PDT 24
Peak memory 250408 kb
Host smart-2efaeee7-139b-46e2-a7f1-cbc6e6422610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558172226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.558172226
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.3424532051
Short name T482
Test name
Test status
Simulation time 115111273 ps
CPU time 7.27 seconds
Started Jul 13 04:47:07 PM PDT 24
Finished Jul 13 04:47:14 PM PDT 24
Peak memory 242292 kb
Host smart-4e8e0438-44c4-4d70-9feb-eb18870f33cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424532051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3424532051
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1960645041
Short name T427
Test name
Test status
Simulation time 1164166008 ps
CPU time 78.93 seconds
Started Jul 13 04:47:12 PM PDT 24
Finished Jul 13 04:48:32 PM PDT 24
Peak memory 248552 kb
Host smart-fee0c037-6bb5-4f68-bd3b-054293f7daa6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960645041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1960645041
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.4049628808
Short name T692
Test name
Test status
Simulation time 150192104918 ps
CPU time 580.8 seconds
Started Jul 13 04:47:12 PM PDT 24
Finished Jul 13 04:56:54 PM PDT 24
Peak memory 316136 kb
Host smart-7da7221b-039b-4ac8-8c37-5e43e46b3c4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4049628808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.4049628808
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.533364159
Short name T589
Test name
Test status
Simulation time 20375013 ps
CPU time 0.82 seconds
Started Jul 13 04:47:10 PM PDT 24
Finished Jul 13 04:47:13 PM PDT 24
Peak memory 208524 kb
Host smart-bf688829-4ba5-4be3-b030-674fd28a53cd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533364159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.533364159
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3043521045
Short name T729
Test name
Test status
Simulation time 26002800 ps
CPU time 1.27 seconds
Started Jul 13 04:47:22 PM PDT 24
Finished Jul 13 04:47:23 PM PDT 24
Peak memory 208488 kb
Host smart-293d4d4d-257c-4c18-b6e0-e94ae8e74fec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043521045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3043521045
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.4141404681
Short name T767
Test name
Test status
Simulation time 3470757210 ps
CPU time 12.74 seconds
Started Jul 13 04:47:12 PM PDT 24
Finished Jul 13 04:47:26 PM PDT 24
Peak memory 218432 kb
Host smart-5ac0fb56-de0b-44e5-8103-eaa985e52cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141404681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.4141404681
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2824991549
Short name T713
Test name
Test status
Simulation time 321058561 ps
CPU time 2.74 seconds
Started Jul 13 04:47:06 PM PDT 24
Finished Jul 13 04:47:10 PM PDT 24
Peak memory 217124 kb
Host smart-7a989b3d-e7f8-40b3-b37f-4a151da03848
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824991549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2824991549
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3481060528
Short name T817
Test name
Test status
Simulation time 65548883 ps
CPU time 2.58 seconds
Started Jul 13 04:47:08 PM PDT 24
Finished Jul 13 04:47:10 PM PDT 24
Peak memory 217660 kb
Host smart-b4cf7e9f-f02f-4995-a4dc-0f4724c37fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481060528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3481060528
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2338104588
Short name T794
Test name
Test status
Simulation time 369106628 ps
CPU time 9.73 seconds
Started Jul 13 04:47:10 PM PDT 24
Finished Jul 13 04:47:21 PM PDT 24
Peak memory 217940 kb
Host smart-0da8aedb-85bd-4517-b86c-2ef6bb83727f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338104588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2338104588
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1577608718
Short name T464
Test name
Test status
Simulation time 865771146 ps
CPU time 17.11 seconds
Started Jul 13 04:47:17 PM PDT 24
Finished Jul 13 04:47:36 PM PDT 24
Peak memory 225384 kb
Host smart-a69f9892-785d-4e4e-bfa4-59303d973527
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577608718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1577608718
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1845841294
Short name T425
Test name
Test status
Simulation time 644038037 ps
CPU time 12.33 seconds
Started Jul 13 04:47:16 PM PDT 24
Finished Jul 13 04:47:29 PM PDT 24
Peak memory 225408 kb
Host smart-62b0681d-4412-4fe0-bdc9-145a7bf31629
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845841294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1845841294
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3957470584
Short name T346
Test name
Test status
Simulation time 1307726091 ps
CPU time 10.42 seconds
Started Jul 13 04:47:11 PM PDT 24
Finished Jul 13 04:47:22 PM PDT 24
Peak memory 217776 kb
Host smart-e47d31e7-c088-4427-98ad-9bea98fcc273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957470584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3957470584
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.2571208675
Short name T787
Test name
Test status
Simulation time 977542480 ps
CPU time 3.14 seconds
Started Jul 13 04:47:09 PM PDT 24
Finished Jul 13 04:47:13 PM PDT 24
Peak memory 214228 kb
Host smart-82fb6636-18f4-4913-be9e-7634d1710a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571208675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2571208675
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.438904508
Short name T661
Test name
Test status
Simulation time 1063669717 ps
CPU time 19.45 seconds
Started Jul 13 04:47:10 PM PDT 24
Finished Jul 13 04:47:31 PM PDT 24
Peak memory 250472 kb
Host smart-4f1acd82-689c-4289-b112-23b328dfe0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438904508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.438904508
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2473461886
Short name T93
Test name
Test status
Simulation time 66746605 ps
CPU time 8.63 seconds
Started Jul 13 04:47:09 PM PDT 24
Finished Jul 13 04:47:19 PM PDT 24
Peak memory 250408 kb
Host smart-0fdcf0bf-ed6d-488f-a782-5d68aa531ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473461886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2473461886
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.974546959
Short name T281
Test name
Test status
Simulation time 12241381940 ps
CPU time 333.73 seconds
Started Jul 13 04:47:15 PM PDT 24
Finished Jul 13 04:52:50 PM PDT 24
Peak memory 272244 kb
Host smart-acb9c907-590f-47d1-b93f-6475dfb6e042
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974546959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.974546959
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2613871828
Short name T735
Test name
Test status
Simulation time 38802127 ps
CPU time 0.98 seconds
Started Jul 13 04:47:16 PM PDT 24
Finished Jul 13 04:47:19 PM PDT 24
Peak memory 211388 kb
Host smart-ded43a6b-8bbe-4751-820d-a4c4fb9f6767
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613871828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2613871828
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.3122529363
Short name T808
Test name
Test status
Simulation time 42069040 ps
CPU time 0.9 seconds
Started Jul 13 04:47:15 PM PDT 24
Finished Jul 13 04:47:17 PM PDT 24
Peak memory 208512 kb
Host smart-88c32ea9-9ea0-42eb-98cd-5359be7fbb6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122529363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3122529363
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3954810942
Short name T701
Test name
Test status
Simulation time 274882309 ps
CPU time 12.79 seconds
Started Jul 13 04:47:18 PM PDT 24
Finished Jul 13 04:47:32 PM PDT 24
Peak memory 225412 kb
Host smart-b4c1bbcb-e74a-4f5c-8ab3-5137b66677fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954810942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3954810942
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3860204490
Short name T536
Test name
Test status
Simulation time 421865864 ps
CPU time 5.28 seconds
Started Jul 13 04:47:22 PM PDT 24
Finished Jul 13 04:47:27 PM PDT 24
Peak memory 217136 kb
Host smart-a7766125-7438-414e-b4f5-86152c09b205
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860204490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3860204490
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2169363734
Short name T738
Test name
Test status
Simulation time 54070963 ps
CPU time 3.12 seconds
Started Jul 13 04:47:16 PM PDT 24
Finished Jul 13 04:47:21 PM PDT 24
Peak memory 221860 kb
Host smart-c440e2cf-d208-45c5-a95b-6ba65f7dd7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169363734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2169363734
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3333625701
Short name T774
Test name
Test status
Simulation time 248823048 ps
CPU time 8.63 seconds
Started Jul 13 04:47:18 PM PDT 24
Finished Jul 13 04:47:28 PM PDT 24
Peak memory 225384 kb
Host smart-05c8ec68-f245-4ac2-82fd-63eb62ee47f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333625701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3333625701
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1798549030
Short name T321
Test name
Test status
Simulation time 527143626 ps
CPU time 10.37 seconds
Started Jul 13 04:47:16 PM PDT 24
Finished Jul 13 04:47:27 PM PDT 24
Peak memory 217616 kb
Host smart-8833f659-5e1a-49ab-b7ef-5e9de59e3a34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798549030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
1798549030
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1901915079
Short name T559
Test name
Test status
Simulation time 735278032 ps
CPU time 6.77 seconds
Started Jul 13 04:47:24 PM PDT 24
Finished Jul 13 04:47:32 PM PDT 24
Peak memory 224412 kb
Host smart-f3a1b74b-8c4a-4181-8078-08f1daa79a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901915079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1901915079
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3937561465
Short name T391
Test name
Test status
Simulation time 149336137 ps
CPU time 3.28 seconds
Started Jul 13 04:47:14 PM PDT 24
Finished Jul 13 04:47:18 PM PDT 24
Peak memory 216928 kb
Host smart-6b7e7354-0a88-4fda-b6c0-ea4bb64a7e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937561465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3937561465
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.377074997
Short name T748
Test name
Test status
Simulation time 316769722 ps
CPU time 33.19 seconds
Started Jul 13 04:47:18 PM PDT 24
Finished Jul 13 04:47:53 PM PDT 24
Peak memory 250412 kb
Host smart-f22c71fc-8172-49a2-996b-a5a68605e16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377074997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.377074997
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1426465729
Short name T272
Test name
Test status
Simulation time 52387062 ps
CPU time 6.42 seconds
Started Jul 13 04:47:32 PM PDT 24
Finished Jul 13 04:47:39 PM PDT 24
Peak memory 249796 kb
Host smart-1a059d04-df2d-4998-8f19-e2ba76a58861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426465729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1426465729
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3982170673
Short name T786
Test name
Test status
Simulation time 24786735146 ps
CPU time 216.32 seconds
Started Jul 13 04:47:16 PM PDT 24
Finished Jul 13 04:50:53 PM PDT 24
Peak memory 271976 kb
Host smart-2a69b237-d0df-4074-a2e0-d596961f7afd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982170673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3982170673
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3096364711
Short name T710
Test name
Test status
Simulation time 28615507 ps
CPU time 0.77 seconds
Started Jul 13 04:47:15 PM PDT 24
Finished Jul 13 04:47:16 PM PDT 24
Peak memory 208120 kb
Host smart-4ef53870-f96a-4f08-86f8-4c1000d0a36e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096364711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3096364711
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1771255459
Short name T273
Test name
Test status
Simulation time 127456969 ps
CPU time 1.22 seconds
Started Jul 13 04:47:15 PM PDT 24
Finished Jul 13 04:47:17 PM PDT 24
Peak memory 208360 kb
Host smart-88e85cad-fd37-44f5-95a2-88bd64594ae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771255459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1771255459
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3159238178
Short name T50
Test name
Test status
Simulation time 1084688696 ps
CPU time 13.96 seconds
Started Jul 13 04:47:16 PM PDT 24
Finished Jul 13 04:47:31 PM PDT 24
Peak memory 217596 kb
Host smart-d0087362-11d6-4817-955f-b89eb10b9930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159238178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3159238178
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2888742421
Short name T542
Test name
Test status
Simulation time 540622362 ps
CPU time 6.51 seconds
Started Jul 13 04:47:18 PM PDT 24
Finished Jul 13 04:47:26 PM PDT 24
Peak memory 217136 kb
Host smart-67797cb7-7876-4b26-98ea-cd5782aabc53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888742421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2888742421
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3708801535
Short name T489
Test name
Test status
Simulation time 304975240 ps
CPU time 3.1 seconds
Started Jul 13 04:47:19 PM PDT 24
Finished Jul 13 04:47:23 PM PDT 24
Peak memory 217656 kb
Host smart-f19e502f-7e77-4af4-8478-88aff9168508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708801535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3708801535
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.999634252
Short name T301
Test name
Test status
Simulation time 877405886 ps
CPU time 11.07 seconds
Started Jul 13 04:47:15 PM PDT 24
Finished Jul 13 04:47:27 PM PDT 24
Peak memory 225468 kb
Host smart-a274cf70-1df0-4600-a5e5-373261b8c8d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999634252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.999634252
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3066040617
Short name T365
Test name
Test status
Simulation time 673952401 ps
CPU time 8.17 seconds
Started Jul 13 04:47:20 PM PDT 24
Finished Jul 13 04:47:28 PM PDT 24
Peak memory 225396 kb
Host smart-6603c242-4aee-4696-b84a-9b1ab697f347
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066040617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3066040617
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2675620279
Short name T339
Test name
Test status
Simulation time 436648077 ps
CPU time 15.75 seconds
Started Jul 13 04:47:17 PM PDT 24
Finished Jul 13 04:47:35 PM PDT 24
Peak memory 225472 kb
Host smart-32a0394b-199b-451d-acd4-93241e58941e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675620279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2675620279
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.789308523
Short name T404
Test name
Test status
Simulation time 214863606 ps
CPU time 2.36 seconds
Started Jul 13 04:47:17 PM PDT 24
Finished Jul 13 04:47:21 PM PDT 24
Peak memory 213980 kb
Host smart-f31ab2e5-225a-4a8f-ac75-19bab25243b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789308523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.789308523
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3755017269
Short name T439
Test name
Test status
Simulation time 628858780 ps
CPU time 19.83 seconds
Started Jul 13 04:47:16 PM PDT 24
Finished Jul 13 04:47:37 PM PDT 24
Peak memory 244848 kb
Host smart-ecafeff3-d4b0-462c-8135-2fa2766c8d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755017269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3755017269
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3713646099
Short name T227
Test name
Test status
Simulation time 1278619202 ps
CPU time 6.49 seconds
Started Jul 13 04:47:19 PM PDT 24
Finished Jul 13 04:47:26 PM PDT 24
Peak memory 249964 kb
Host smart-1b3130a2-3036-4b6e-a308-d81df5dd8c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713646099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3713646099
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3419892065
Short name T284
Test name
Test status
Simulation time 1156885029 ps
CPU time 45.7 seconds
Started Jul 13 04:47:18 PM PDT 24
Finished Jul 13 04:48:05 PM PDT 24
Peak memory 250452 kb
Host smart-71445b45-a9fc-40b9-b015-e2d45d762096
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419892065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3419892065
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.596824545
Short name T201
Test name
Test status
Simulation time 12662229 ps
CPU time 0.78 seconds
Started Jul 13 04:47:16 PM PDT 24
Finished Jul 13 04:47:19 PM PDT 24
Peak memory 207904 kb
Host smart-074459ef-0955-4681-b7fd-989dec338eab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596824545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ct
rl_volatile_unlock_smoke.596824545
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.734818451
Short name T704
Test name
Test status
Simulation time 39442164 ps
CPU time 0.85 seconds
Started Jul 13 04:47:20 PM PDT 24
Finished Jul 13 04:47:21 PM PDT 24
Peak memory 208252 kb
Host smart-e394bb26-1bf8-4d06-8c6d-34254143234c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734818451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.734818451
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.105747074
Short name T756
Test name
Test status
Simulation time 1371972766 ps
CPU time 14.88 seconds
Started Jul 13 04:47:15 PM PDT 24
Finished Jul 13 04:47:31 PM PDT 24
Peak memory 217660 kb
Host smart-92a01a00-0e09-43ba-a043-3b2d20072009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105747074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.105747074
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2231930099
Short name T857
Test name
Test status
Simulation time 272493175 ps
CPU time 5.07 seconds
Started Jul 13 04:47:24 PM PDT 24
Finished Jul 13 04:47:32 PM PDT 24
Peak memory 217100 kb
Host smart-2d8ebd5a-ae30-4977-805b-8265a653c7da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231930099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2231930099
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1472784108
Short name T299
Test name
Test status
Simulation time 90123762 ps
CPU time 3.42 seconds
Started Jul 13 04:47:18 PM PDT 24
Finished Jul 13 04:47:23 PM PDT 24
Peak memory 217640 kb
Host smart-29d7e536-8284-4f30-9a32-45f6f110933e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472784108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1472784108
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2257501419
Short name T751
Test name
Test status
Simulation time 1179329688 ps
CPU time 15.58 seconds
Started Jul 13 04:47:18 PM PDT 24
Finished Jul 13 04:47:35 PM PDT 24
Peak memory 218492 kb
Host smart-2d3c21fa-286b-4a3b-806d-dc2e9a608c03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257501419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2257501419
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2120992772
Short name T328
Test name
Test status
Simulation time 655766859 ps
CPU time 12.51 seconds
Started Jul 13 04:47:19 PM PDT 24
Finished Jul 13 04:47:32 PM PDT 24
Peak memory 225440 kb
Host smart-3332b368-5cae-4ab2-ad62-fe393b61088d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120992772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2120992772
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1461456570
Short name T263
Test name
Test status
Simulation time 367680192 ps
CPU time 12.65 seconds
Started Jul 13 04:47:17 PM PDT 24
Finished Jul 13 04:47:31 PM PDT 24
Peak memory 217600 kb
Host smart-ffbde5b4-6548-40bf-b3ad-d6500647dc61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461456570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1461456570
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3345349125
Short name T760
Test name
Test status
Simulation time 232431800 ps
CPU time 10.3 seconds
Started Jul 13 04:47:22 PM PDT 24
Finished Jul 13 04:47:33 PM PDT 24
Peak memory 225528 kb
Host smart-fe7bddfb-3967-4bc1-b7b5-a341c65103b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345349125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3345349125
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3794599505
Short name T584
Test name
Test status
Simulation time 111481951 ps
CPU time 2.13 seconds
Started Jul 13 04:47:19 PM PDT 24
Finished Jul 13 04:47:22 PM PDT 24
Peak memory 213788 kb
Host smart-3797155d-cc47-4457-acda-b01ee208e41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794599505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3794599505
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.4094630662
Short name T802
Test name
Test status
Simulation time 2406602100 ps
CPU time 30.44 seconds
Started Jul 13 04:47:16 PM PDT 24
Finished Jul 13 04:47:47 PM PDT 24
Peak memory 245132 kb
Host smart-a47c31b2-8745-4b26-8c85-c5bf387bb9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094630662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.4094630662
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1381748556
Short name T304
Test name
Test status
Simulation time 307500837 ps
CPU time 8.07 seconds
Started Jul 13 04:47:26 PM PDT 24
Finished Jul 13 04:47:36 PM PDT 24
Peak memory 250440 kb
Host smart-c6b415d4-c616-4489-820a-692bb0cac2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381748556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1381748556
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.830570107
Short name T667
Test name
Test status
Simulation time 1509144778 ps
CPU time 22.69 seconds
Started Jul 13 04:47:22 PM PDT 24
Finished Jul 13 04:47:46 PM PDT 24
Peak memory 242528 kb
Host smart-47cc4d12-062f-47e6-b09a-5bc9f6753091
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830570107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.830570107
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3120385812
Short name T326
Test name
Test status
Simulation time 32620682 ps
CPU time 0.96 seconds
Started Jul 13 04:47:16 PM PDT 24
Finished Jul 13 04:47:18 PM PDT 24
Peak memory 217216 kb
Host smart-8793f162-18bc-454a-9e73-2d8885b63f20
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120385812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3120385812
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.855200558
Short name T49
Test name
Test status
Simulation time 270956421 ps
CPU time 9.44 seconds
Started Jul 13 04:47:26 PM PDT 24
Finished Jul 13 04:47:37 PM PDT 24
Peak memory 217664 kb
Host smart-7a443a66-8b79-478f-9bfa-57508c38e5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855200558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.855200558
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3286258735
Short name T533
Test name
Test status
Simulation time 194483985 ps
CPU time 1.39 seconds
Started Jul 13 04:47:26 PM PDT 24
Finished Jul 13 04:47:29 PM PDT 24
Peak memory 216544 kb
Host smart-61345592-a499-4934-89e8-1a1adc9cea4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286258735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3286258735
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.484067869
Short name T139
Test name
Test status
Simulation time 183401291 ps
CPU time 3.32 seconds
Started Jul 13 04:47:24 PM PDT 24
Finished Jul 13 04:47:30 PM PDT 24
Peak memory 217660 kb
Host smart-756ea97f-62fa-478b-8bd4-13e193961a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484067869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.484067869
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1271324821
Short name T316
Test name
Test status
Simulation time 310289068 ps
CPU time 13.58 seconds
Started Jul 13 04:47:24 PM PDT 24
Finished Jul 13 04:47:39 PM PDT 24
Peak memory 225444 kb
Host smart-3c133376-8f89-412b-b9b5-d24825bd1933
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271324821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1271324821
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1011033381
Short name T753
Test name
Test status
Simulation time 394110037 ps
CPU time 7.99 seconds
Started Jul 13 04:47:27 PM PDT 24
Finished Jul 13 04:47:36 PM PDT 24
Peak memory 225392 kb
Host smart-4f135564-a292-4204-a283-d26ec2a35fca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011033381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1011033381
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2210456067
Short name T506
Test name
Test status
Simulation time 282096669 ps
CPU time 7.81 seconds
Started Jul 13 04:47:24 PM PDT 24
Finished Jul 13 04:47:34 PM PDT 24
Peak memory 224156 kb
Host smart-cd49a292-7015-45ca-822e-bfab9ec4216a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210456067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2210456067
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3242922081
Short name T91
Test name
Test status
Simulation time 111597181 ps
CPU time 1.4 seconds
Started Jul 13 04:47:17 PM PDT 24
Finished Jul 13 04:47:21 PM PDT 24
Peak memory 217084 kb
Host smart-8753fc1f-23d0-4133-91ba-4a1aa3dd21be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242922081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3242922081
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.4161173163
Short name T828
Test name
Test status
Simulation time 1537186895 ps
CPU time 37.4 seconds
Started Jul 13 04:47:25 PM PDT 24
Finished Jul 13 04:48:04 PM PDT 24
Peak memory 250468 kb
Host smart-a074bb2d-83ef-47cd-882d-d68aec1e734c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161173163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.4161173163
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.683936141
Short name T592
Test name
Test status
Simulation time 91777803 ps
CPU time 10.24 seconds
Started Jul 13 04:47:24 PM PDT 24
Finished Jul 13 04:47:36 PM PDT 24
Peak memory 250416 kb
Host smart-080c4060-2b53-4679-ace2-3d6e97cc5b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683936141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.683936141
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2262295584
Short name T42
Test name
Test status
Simulation time 4877163101 ps
CPU time 181.5 seconds
Started Jul 13 04:47:24 PM PDT 24
Finished Jul 13 04:50:28 PM PDT 24
Peak memory 281032 kb
Host smart-ab90ad99-5052-4425-b067-caa6b9d514ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262295584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2262295584
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1136569066
Short name T226
Test name
Test status
Simulation time 14410493 ps
CPU time 0.91 seconds
Started Jul 13 04:47:24 PM PDT 24
Finished Jul 13 04:47:27 PM PDT 24
Peak memory 208544 kb
Host smart-a3509a09-4ea6-45fd-9044-4701e78d2324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136569066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1136569066
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.595091911
Short name T553
Test name
Test status
Simulation time 282792880 ps
CPU time 12.33 seconds
Started Jul 13 04:47:23 PM PDT 24
Finished Jul 13 04:47:37 PM PDT 24
Peak memory 217792 kb
Host smart-c0b032c1-0de5-4f20-a26b-68653df96ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595091911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.595091911
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1376360929
Short name T7
Test name
Test status
Simulation time 441881543 ps
CPU time 4.67 seconds
Started Jul 13 04:47:22 PM PDT 24
Finished Jul 13 04:47:28 PM PDT 24
Peak memory 217132 kb
Host smart-b3062b60-efda-4c96-aabe-b74de3f3925a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376360929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1376360929
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.2354936461
Short name T413
Test name
Test status
Simulation time 24590091 ps
CPU time 1.44 seconds
Started Jul 13 04:47:23 PM PDT 24
Finished Jul 13 04:47:26 PM PDT 24
Peak memory 221176 kb
Host smart-16d46327-ee8d-40f7-913f-c2eb743bf0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354936461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2354936461
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.2584249169
Short name T303
Test name
Test status
Simulation time 471134539 ps
CPU time 12.69 seconds
Started Jul 13 04:47:23 PM PDT 24
Finished Jul 13 04:47:38 PM PDT 24
Peak memory 225480 kb
Host smart-34ddf5e0-437e-4c4c-9da3-3fed53071a14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584249169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2584249169
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3667289057
Short name T492
Test name
Test status
Simulation time 450464042 ps
CPU time 11.86 seconds
Started Jul 13 04:47:34 PM PDT 24
Finished Jul 13 04:47:48 PM PDT 24
Peak memory 225412 kb
Host smart-1c5c7d4f-145e-4988-82a5-6752a702520c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667289057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3667289057
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1251731788
Short name T772
Test name
Test status
Simulation time 3181281871 ps
CPU time 10.43 seconds
Started Jul 13 04:47:25 PM PDT 24
Finished Jul 13 04:47:38 PM PDT 24
Peak memory 218364 kb
Host smart-b336a9e3-f22b-468f-b9e7-dc06337305e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251731788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1251731788
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3044114666
Short name T691
Test name
Test status
Simulation time 514998093 ps
CPU time 6.77 seconds
Started Jul 13 04:47:26 PM PDT 24
Finished Jul 13 04:47:35 PM PDT 24
Peak memory 217724 kb
Host smart-313fde56-bfa3-419a-8d05-04caff18fe36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044114666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3044114666
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3443933785
Short name T612
Test name
Test status
Simulation time 190886145 ps
CPU time 2.16 seconds
Started Jul 13 04:47:26 PM PDT 24
Finished Jul 13 04:47:30 PM PDT 24
Peak memory 217092 kb
Host smart-b05c400d-0bad-4110-ac08-a16d04975925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443933785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3443933785
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3794791135
Short name T659
Test name
Test status
Simulation time 1043063592 ps
CPU time 26.94 seconds
Started Jul 13 04:47:25 PM PDT 24
Finished Jul 13 04:47:54 PM PDT 24
Peak memory 245084 kb
Host smart-72fd7053-6c1b-4e0c-97f2-dacbd7cf9bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794791135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3794791135
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2397122156
Short name T433
Test name
Test status
Simulation time 129471767 ps
CPU time 5.79 seconds
Started Jul 13 04:47:22 PM PDT 24
Finished Jul 13 04:47:29 PM PDT 24
Peak memory 245920 kb
Host smart-7d3014b0-f692-4005-a0f0-535d2da1722a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397122156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2397122156
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.3990899682
Short name T70
Test name
Test status
Simulation time 3684679332 ps
CPU time 32.19 seconds
Started Jul 13 04:47:25 PM PDT 24
Finished Jul 13 04:47:59 PM PDT 24
Peak memory 248460 kb
Host smart-8af4f5dd-513b-489b-aed3-9fa4dcc3f26a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990899682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.3990899682
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.1105052060
Short name T443
Test name
Test status
Simulation time 38599851083 ps
CPU time 313.36 seconds
Started Jul 13 04:47:23 PM PDT 24
Finished Jul 13 04:52:37 PM PDT 24
Peak memory 272236 kb
Host smart-bc5f630c-e59b-4b5f-b99e-ec4f25fe7f64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1105052060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.1105052060
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1038483217
Short name T517
Test name
Test status
Simulation time 22035828 ps
CPU time 1.01 seconds
Started Jul 13 04:47:25 PM PDT 24
Finished Jul 13 04:47:28 PM PDT 24
Peak memory 211336 kb
Host smart-771e0d93-376a-45db-9782-131b92723b07
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038483217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1038483217
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.4162936096
Short name T524
Test name
Test status
Simulation time 30488045 ps
CPU time 1.03 seconds
Started Jul 13 04:47:24 PM PDT 24
Finished Jul 13 04:47:27 PM PDT 24
Peak memory 208464 kb
Host smart-8d75f1a0-0974-4b54-96e3-0b73de53dbdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162936096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.4162936096
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1723213568
Short name T824
Test name
Test status
Simulation time 514681821 ps
CPU time 10.68 seconds
Started Jul 13 04:47:31 PM PDT 24
Finished Jul 13 04:47:42 PM PDT 24
Peak memory 225460 kb
Host smart-be976e2a-066d-41e2-964e-067954015bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723213568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1723213568
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.3097498268
Short name T356
Test name
Test status
Simulation time 7013039842 ps
CPU time 4.84 seconds
Started Jul 13 04:47:23 PM PDT 24
Finished Jul 13 04:47:29 PM PDT 24
Peak memory 217144 kb
Host smart-e40b99d6-6bed-4f38-b0f1-6f7270242973
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097498268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.3097498268
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1337922977
Short name T538
Test name
Test status
Simulation time 214449810 ps
CPU time 3.53 seconds
Started Jul 13 04:47:30 PM PDT 24
Finished Jul 13 04:47:34 PM PDT 24
Peak memory 217656 kb
Host smart-12307f71-bbd5-48d0-8fb6-b31c7c2336c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337922977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1337922977
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.1388953030
Short name T816
Test name
Test status
Simulation time 269769070 ps
CPU time 11.74 seconds
Started Jul 13 04:47:24 PM PDT 24
Finished Jul 13 04:47:37 PM PDT 24
Peak memory 225508 kb
Host smart-02baf863-3446-4d67-b6c4-59fadb9e6293
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388953030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.1388953030
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2465434744
Short name T865
Test name
Test status
Simulation time 510130582 ps
CPU time 11.25 seconds
Started Jul 13 04:47:22 PM PDT 24
Finished Jul 13 04:47:35 PM PDT 24
Peak memory 225400 kb
Host smart-a425ff4e-b0e1-4d6b-91a0-196d032f5048
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465434744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2465434744
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.116676119
Short name T675
Test name
Test status
Simulation time 798245277 ps
CPU time 9.02 seconds
Started Jul 13 04:47:25 PM PDT 24
Finished Jul 13 04:47:36 PM PDT 24
Peak memory 217548 kb
Host smart-c4f447cb-f519-4997-b844-77660053d038
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116676119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.116676119
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2599231655
Short name T798
Test name
Test status
Simulation time 1402637073 ps
CPU time 5.52 seconds
Started Jul 13 04:47:27 PM PDT 24
Finished Jul 13 04:47:34 PM PDT 24
Peak memory 217624 kb
Host smart-c9713a01-628d-48a4-94f5-4777e6303b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599231655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2599231655
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1541221076
Short name T714
Test name
Test status
Simulation time 72506268 ps
CPU time 1.51 seconds
Started Jul 13 04:47:23 PM PDT 24
Finished Jul 13 04:47:26 PM PDT 24
Peak memory 213208 kb
Host smart-b2846221-3914-4952-9cad-dc87759763c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541221076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1541221076
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2513865513
Short name T663
Test name
Test status
Simulation time 1933196873 ps
CPU time 34.79 seconds
Started Jul 13 04:47:22 PM PDT 24
Finished Jul 13 04:47:57 PM PDT 24
Peak memory 250472 kb
Host smart-6c3e4656-2ec4-43c0-8e3c-fca1274d27a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513865513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2513865513
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1080728780
Short name T376
Test name
Test status
Simulation time 60586374 ps
CPU time 8.71 seconds
Started Jul 13 04:47:27 PM PDT 24
Finished Jul 13 04:47:37 PM PDT 24
Peak memory 250408 kb
Host smart-3e22b4a4-a5be-4f47-9fc6-005cdb4aa302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080728780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1080728780
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.809379597
Short name T78
Test name
Test status
Simulation time 68199100 ps
CPU time 1.1 seconds
Started Jul 13 04:47:25 PM PDT 24
Finished Jul 13 04:47:28 PM PDT 24
Peak memory 211348 kb
Host smart-a8aca4ff-147c-4705-abcb-815116699c39
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809379597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ct
rl_volatile_unlock_smoke.809379597
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3273103438
Short name T668
Test name
Test status
Simulation time 56320161 ps
CPU time 1.04 seconds
Started Jul 13 04:47:27 PM PDT 24
Finished Jul 13 04:47:30 PM PDT 24
Peak memory 208340 kb
Host smart-c24810c2-9c12-49d3-9290-80596e372592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273103438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3273103438
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3866126079
Short name T699
Test name
Test status
Simulation time 3551932273 ps
CPU time 12.64 seconds
Started Jul 13 04:47:24 PM PDT 24
Finished Jul 13 04:47:38 PM PDT 24
Peak memory 218696 kb
Host smart-7e279f38-ae47-4263-b266-aee271bf3aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866126079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3866126079
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3084314882
Short name T22
Test name
Test status
Simulation time 612222620 ps
CPU time 6.83 seconds
Started Jul 13 04:47:26 PM PDT 24
Finished Jul 13 04:47:34 PM PDT 24
Peak memory 216632 kb
Host smart-9804e8c7-092f-4286-8ec1-ee55192a2f7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084314882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3084314882
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2766060112
Short name T256
Test name
Test status
Simulation time 349271230 ps
CPU time 4.09 seconds
Started Jul 13 04:47:22 PM PDT 24
Finished Jul 13 04:47:27 PM PDT 24
Peak memory 217660 kb
Host smart-937bccdd-3d67-40f4-8ab8-7ef4cd15ef8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766060112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2766060112
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.28766807
Short name T591
Test name
Test status
Simulation time 450836536 ps
CPU time 11.86 seconds
Started Jul 13 04:47:32 PM PDT 24
Finished Jul 13 04:47:45 PM PDT 24
Peak memory 217672 kb
Host smart-bbe0fe6f-fb8d-4ab4-8f76-fd513682e52b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28766807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.28766807
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1611762544
Short name T621
Test name
Test status
Simulation time 433368543 ps
CPU time 16.63 seconds
Started Jul 13 04:47:31 PM PDT 24
Finished Jul 13 04:47:48 PM PDT 24
Peak memory 225392 kb
Host smart-387ebce8-e29d-4e29-9a87-b97fd49de2ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611762544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1611762544
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.4138007491
Short name T217
Test name
Test status
Simulation time 2571838220 ps
CPU time 13.05 seconds
Started Jul 13 04:47:22 PM PDT 24
Finished Jul 13 04:47:37 PM PDT 24
Peak memory 225512 kb
Host smart-749c0ce3-d04d-4ec8-8777-a3ca9c5db607
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138007491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
4138007491
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3791522215
Short name T237
Test name
Test status
Simulation time 379366294 ps
CPU time 7.07 seconds
Started Jul 13 04:47:32 PM PDT 24
Finished Jul 13 04:47:40 PM PDT 24
Peak memory 224328 kb
Host smart-923e384b-56ad-469c-b8cc-474dde0d52d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791522215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3791522215
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1183561833
Short name T458
Test name
Test status
Simulation time 73442273 ps
CPU time 2.8 seconds
Started Jul 13 04:47:31 PM PDT 24
Finished Jul 13 04:47:35 PM PDT 24
Peak memory 213644 kb
Host smart-ffc8fcca-515d-44c4-8509-862c7b30dd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183561833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1183561833
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2718802046
Short name T598
Test name
Test status
Simulation time 636760303 ps
CPU time 28.03 seconds
Started Jul 13 04:47:23 PM PDT 24
Finished Jul 13 04:47:52 PM PDT 24
Peak memory 250588 kb
Host smart-c35881e5-3758-4d44-9c37-8624a0edbd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718802046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2718802046
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2633094905
Short name T858
Test name
Test status
Simulation time 93338366 ps
CPU time 6.81 seconds
Started Jul 13 04:47:31 PM PDT 24
Finished Jul 13 04:47:40 PM PDT 24
Peak memory 249956 kb
Host smart-ed8d24a4-ad81-4548-897a-6151462e116f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633094905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2633094905
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2360028388
Short name T46
Test name
Test status
Simulation time 5901382465 ps
CPU time 130.75 seconds
Started Jul 13 04:47:32 PM PDT 24
Finished Jul 13 04:49:44 PM PDT 24
Peak memory 258668 kb
Host smart-e1ea393f-d51b-4fa5-817b-73d31088bb56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360028388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2360028388
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2183067387
Short name T81
Test name
Test status
Simulation time 28463398 ps
CPU time 1.11 seconds
Started Jul 13 04:47:32 PM PDT 24
Finished Jul 13 04:47:34 PM PDT 24
Peak memory 211220 kb
Host smart-6ba428c0-d30d-4dee-b19c-ab17d4454cdb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183067387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2183067387
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.602549226
Short name T575
Test name
Test status
Simulation time 150504290 ps
CPU time 1.21 seconds
Started Jul 13 04:47:34 PM PDT 24
Finished Jul 13 04:47:37 PM PDT 24
Peak memory 208480 kb
Host smart-f3ebc4fd-03f7-485d-85a9-a9d5e2d2529a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602549226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.602549226
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1434717585
Short name T645
Test name
Test status
Simulation time 271169316 ps
CPU time 10.47 seconds
Started Jul 13 04:47:40 PM PDT 24
Finished Jul 13 04:47:51 PM PDT 24
Peak memory 217692 kb
Host smart-1ffbc248-6cee-4c84-b674-0dea170c1e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434717585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1434717585
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1998897346
Short name T736
Test name
Test status
Simulation time 198712542 ps
CPU time 5.65 seconds
Started Jul 13 04:47:34 PM PDT 24
Finished Jul 13 04:47:42 PM PDT 24
Peak memory 217080 kb
Host smart-d5499fa4-132e-4b0b-b38b-761ef38969d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998897346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1998897346
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.578215717
Short name T183
Test name
Test status
Simulation time 166483200 ps
CPU time 2.4 seconds
Started Jul 13 04:47:40 PM PDT 24
Finished Jul 13 04:47:43 PM PDT 24
Peak memory 217696 kb
Host smart-228d28d1-7719-410d-8d71-1bdc1c90ec43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578215717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.578215717
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1570946887
Short name T293
Test name
Test status
Simulation time 591957429 ps
CPU time 15.97 seconds
Started Jul 13 04:47:35 PM PDT 24
Finished Jul 13 04:47:53 PM PDT 24
Peak memory 219396 kb
Host smart-b1486aa1-e61c-4bd5-a7c5-2f148e3dc48e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570946887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1570946887
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3233122749
Short name T331
Test name
Test status
Simulation time 642198537 ps
CPU time 15.42 seconds
Started Jul 13 04:47:35 PM PDT 24
Finished Jul 13 04:47:53 PM PDT 24
Peak memory 225464 kb
Host smart-1de6f516-51a6-498c-869a-f6e484de09de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233122749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3233122749
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.704645375
Short name T393
Test name
Test status
Simulation time 1167507057 ps
CPU time 10.26 seconds
Started Jul 13 04:47:34 PM PDT 24
Finished Jul 13 04:47:46 PM PDT 24
Peak memory 217660 kb
Host smart-38640902-2e90-43a5-83a8-979c6eaebc2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704645375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.704645375
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.248556636
Short name T441
Test name
Test status
Simulation time 1489305817 ps
CPU time 8.61 seconds
Started Jul 13 04:47:35 PM PDT 24
Finished Jul 13 04:47:46 PM PDT 24
Peak memory 224752 kb
Host smart-10b59b2a-e17f-4ec5-9783-c8489ca721c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248556636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.248556636
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2058294423
Short name T310
Test name
Test status
Simulation time 54393763 ps
CPU time 3.14 seconds
Started Jul 13 04:47:25 PM PDT 24
Finished Jul 13 04:47:30 PM PDT 24
Peak memory 214372 kb
Host smart-d6e049c7-8a46-4c13-bbd1-2a50ee28b6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058294423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2058294423
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3803314131
Short name T473
Test name
Test status
Simulation time 1093230629 ps
CPU time 26.9 seconds
Started Jul 13 04:47:26 PM PDT 24
Finished Jul 13 04:47:55 PM PDT 24
Peak memory 250408 kb
Host smart-09279586-449a-4fd4-982b-a68fdcb76ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803314131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3803314131
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.1918600220
Short name T52
Test name
Test status
Simulation time 165590289 ps
CPU time 7.86 seconds
Started Jul 13 04:47:35 PM PDT 24
Finished Jul 13 04:47:45 PM PDT 24
Peak memory 250256 kb
Host smart-5861a2cd-51e7-447c-a8b6-f0c2bd67fd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918600220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1918600220
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1230877170
Short name T228
Test name
Test status
Simulation time 15054072002 ps
CPU time 60.41 seconds
Started Jul 13 04:47:34 PM PDT 24
Finished Jul 13 04:48:37 PM PDT 24
Peak memory 283272 kb
Host smart-c3b8c5ba-03bb-4c5f-9866-be13a135f7cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230877170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1230877170
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.4029175280
Short name T291
Test name
Test status
Simulation time 48856070 ps
CPU time 0.97 seconds
Started Jul 13 04:47:34 PM PDT 24
Finished Jul 13 04:47:37 PM PDT 24
Peak memory 211268 kb
Host smart-bc7ad54f-7a79-45b8-988f-e1faa3fe3fbc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029175280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.4029175280
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.4070528898
Short name T839
Test name
Test status
Simulation time 44951437 ps
CPU time 0.86 seconds
Started Jul 13 04:46:00 PM PDT 24
Finished Jul 13 04:46:02 PM PDT 24
Peak memory 208272 kb
Host smart-a56692a9-3e4b-4785-b6bf-2e372ce2d403
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070528898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.4070528898
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2350847089
Short name T178
Test name
Test status
Simulation time 81464011 ps
CPU time 0.88 seconds
Started Jul 13 04:46:01 PM PDT 24
Finished Jul 13 04:46:02 PM PDT 24
Peak memory 208340 kb
Host smart-a4952973-3a32-4109-b6b2-115fc0158779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350847089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2350847089
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1441373658
Short name T355
Test name
Test status
Simulation time 261383148 ps
CPU time 9.96 seconds
Started Jul 13 04:46:00 PM PDT 24
Finished Jul 13 04:46:10 PM PDT 24
Peak memory 217572 kb
Host smart-8687edf5-ae16-46e3-a949-c06fd8b95532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441373658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1441373658
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.953435112
Short name T677
Test name
Test status
Simulation time 167170356 ps
CPU time 1.25 seconds
Started Jul 13 04:46:05 PM PDT 24
Finished Jul 13 04:46:06 PM PDT 24
Peak memory 217120 kb
Host smart-e8cfb01b-c45c-423a-8215-882dc31c10a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953435112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.953435112
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.739850574
Short name T44
Test name
Test status
Simulation time 1516570319 ps
CPU time 26.2 seconds
Started Jul 13 04:46:03 PM PDT 24
Finished Jul 13 04:46:30 PM PDT 24
Peak memory 217668 kb
Host smart-f0d6e1f2-dae8-46ea-9c6d-3418dc72a4d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739850574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.739850574
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.260596526
Short name T822
Test name
Test status
Simulation time 813444354 ps
CPU time 2.38 seconds
Started Jul 13 04:46:01 PM PDT 24
Finished Jul 13 04:46:05 PM PDT 24
Peak memory 217220 kb
Host smart-3719d4c9-ca12-47f9-b77d-e3a0a7f0a56c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260596526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.260596526
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2742671833
Short name T16
Test name
Test status
Simulation time 691401636 ps
CPU time 3.9 seconds
Started Jul 13 04:46:02 PM PDT 24
Finished Jul 13 04:46:07 PM PDT 24
Peak memory 217640 kb
Host smart-05b2c56a-8a8e-4d71-b12a-aaa623632883
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742671833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2742671833
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1680547406
Short name T693
Test name
Test status
Simulation time 10281358936 ps
CPU time 35.04 seconds
Started Jul 13 04:46:03 PM PDT 24
Finished Jul 13 04:46:39 PM PDT 24
Peak memory 217064 kb
Host smart-f9c729de-76cc-4eec-9b14-249cebeb3d25
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680547406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1680547406
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2515943186
Short name T343
Test name
Test status
Simulation time 599379460 ps
CPU time 14.96 seconds
Started Jul 13 04:46:01 PM PDT 24
Finished Jul 13 04:46:17 PM PDT 24
Peak memory 217028 kb
Host smart-4174d935-0b77-41b3-b3a7-9ff739fd2da1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515943186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2515943186
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2580341460
Short name T421
Test name
Test status
Simulation time 5271936472 ps
CPU time 48.24 seconds
Started Jul 13 04:46:01 PM PDT 24
Finished Jul 13 04:46:51 PM PDT 24
Peak memory 267012 kb
Host smart-96b44985-38b3-4a7a-9580-b04fadf9f1e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580341460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2580341460
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.338801592
Short name T599
Test name
Test status
Simulation time 6224488447 ps
CPU time 18.87 seconds
Started Jul 13 04:46:02 PM PDT 24
Finished Jul 13 04:46:23 PM PDT 24
Peak memory 250432 kb
Host smart-c3c13b08-0e0a-4673-8f2c-30c2568f243f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338801592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.338801592
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1468735170
Short name T708
Test name
Test status
Simulation time 34963153 ps
CPU time 1.55 seconds
Started Jul 13 04:46:02 PM PDT 24
Finished Jul 13 04:46:05 PM PDT 24
Peak memory 217640 kb
Host smart-47d180ae-eea2-4089-ba5a-3d167b5f5b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468735170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1468735170
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.4287199839
Short name T73
Test name
Test status
Simulation time 326173087 ps
CPU time 8.6 seconds
Started Jul 13 04:46:01 PM PDT 24
Finished Jul 13 04:46:11 PM PDT 24
Peak memory 217144 kb
Host smart-5a426634-9984-4f83-8c07-3abc48f590f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287199839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.4287199839
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1035082729
Short name T57
Test name
Test status
Simulation time 237883654 ps
CPU time 34.84 seconds
Started Jul 13 04:46:01 PM PDT 24
Finished Jul 13 04:46:37 PM PDT 24
Peak memory 268928 kb
Host smart-ba1397f0-6da6-440c-a402-56daf0b3134a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035082729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1035082729
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.562064300
Short name T568
Test name
Test status
Simulation time 758571536 ps
CPU time 15.39 seconds
Started Jul 13 04:46:00 PM PDT 24
Finished Jul 13 04:46:15 PM PDT 24
Peak memory 217784 kb
Host smart-638cd36e-1984-44e3-91a5-f593823c5672
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562064300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.562064300
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1698260086
Short name T573
Test name
Test status
Simulation time 830900469 ps
CPU time 10.63 seconds
Started Jul 13 04:46:01 PM PDT 24
Finished Jul 13 04:46:13 PM PDT 24
Peak memory 225384 kb
Host smart-92b51e16-087d-4ea4-9fd9-19ba063b37d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698260086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1698260086
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1305659620
Short name T378
Test name
Test status
Simulation time 1028706465 ps
CPU time 7.79 seconds
Started Jul 13 04:46:00 PM PDT 24
Finished Jul 13 04:46:09 PM PDT 24
Peak memory 225396 kb
Host smart-d52200c5-9756-4ec5-863e-6d1bd223d7b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305659620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
305659620
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3206778439
Short name T379
Test name
Test status
Simulation time 1523964246 ps
CPU time 13.17 seconds
Started Jul 13 04:46:02 PM PDT 24
Finished Jul 13 04:46:16 PM PDT 24
Peak memory 217872 kb
Host smart-41bb83dc-2f20-4743-82cb-8ad5f49cff57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206778439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3206778439
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1895199002
Short name T62
Test name
Test status
Simulation time 41449374 ps
CPU time 2.77 seconds
Started Jul 13 04:46:00 PM PDT 24
Finished Jul 13 04:46:04 PM PDT 24
Peak memory 217068 kb
Host smart-58a71d32-8934-4f0c-84f5-3a9b74f5cf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895199002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1895199002
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2742104497
Short name T793
Test name
Test status
Simulation time 2438627729 ps
CPU time 22.62 seconds
Started Jul 13 04:46:01 PM PDT 24
Finished Jul 13 04:46:25 PM PDT 24
Peak memory 250524 kb
Host smart-40747e85-17ba-40a0-a5d7-6c8eeb51203f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742104497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2742104497
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3895343856
Short name T579
Test name
Test status
Simulation time 140211655 ps
CPU time 6.94 seconds
Started Jul 13 04:46:00 PM PDT 24
Finished Jul 13 04:46:08 PM PDT 24
Peak memory 246468 kb
Host smart-12e313da-c13b-41e8-8e7b-aad95b516f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895343856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3895343856
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1503378905
Short name T863
Test name
Test status
Simulation time 11267167669 ps
CPU time 178.48 seconds
Started Jul 13 04:46:01 PM PDT 24
Finished Jul 13 04:49:00 PM PDT 24
Peak memory 283116 kb
Host smart-7f251ebe-c587-4b75-8fb0-161f3901d512
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503378905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1503378905
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2452502080
Short name T270
Test name
Test status
Simulation time 22535777 ps
CPU time 1.1 seconds
Started Jul 13 04:46:01 PM PDT 24
Finished Jul 13 04:46:03 PM PDT 24
Peak memory 211308 kb
Host smart-d19553c6-1098-4183-8adf-f3323c4e7979
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452502080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2452502080
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.4003788396
Short name T451
Test name
Test status
Simulation time 97612151 ps
CPU time 0.84 seconds
Started Jul 13 04:47:36 PM PDT 24
Finished Jul 13 04:47:39 PM PDT 24
Peak memory 208340 kb
Host smart-3cf67e92-0e5c-45d7-8f0c-eb0ea9b687f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003788396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.4003788396
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2086647506
Short name T869
Test name
Test status
Simulation time 4197860856 ps
CPU time 12.33 seconds
Started Jul 13 04:47:35 PM PDT 24
Finished Jul 13 04:47:50 PM PDT 24
Peak memory 217864 kb
Host smart-1ff2dd05-04c4-4d93-abd6-ff372d726717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086647506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2086647506
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.3101401644
Short name T835
Test name
Test status
Simulation time 2046033409 ps
CPU time 11.59 seconds
Started Jul 13 04:47:34 PM PDT 24
Finished Jul 13 04:47:46 PM PDT 24
Peak memory 217084 kb
Host smart-60de3087-d704-4032-a360-a2ff47e5e559
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101401644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3101401644
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1645051176
Short name T200
Test name
Test status
Simulation time 23713935 ps
CPU time 1.6 seconds
Started Jul 13 04:47:38 PM PDT 24
Finished Jul 13 04:47:41 PM PDT 24
Peak memory 217720 kb
Host smart-ab54d501-da39-4bbd-8161-34a24b695ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645051176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1645051176
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.4166206168
Short name T775
Test name
Test status
Simulation time 566993799 ps
CPU time 16.1 seconds
Started Jul 13 04:47:35 PM PDT 24
Finished Jul 13 04:47:54 PM PDT 24
Peak memory 225392 kb
Host smart-57526dfb-4113-4c87-92da-aa7722d91d9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166206168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.4166206168
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.125218091
Short name T33
Test name
Test status
Simulation time 357138287 ps
CPU time 10.76 seconds
Started Jul 13 04:47:38 PM PDT 24
Finished Jul 13 04:47:51 PM PDT 24
Peak memory 224736 kb
Host smart-60bcfaff-f5d5-46dc-a2e3-e125177ee1e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125218091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.125218091
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1996622423
Short name T795
Test name
Test status
Simulation time 519448021 ps
CPU time 10.76 seconds
Started Jul 13 04:47:36 PM PDT 24
Finished Jul 13 04:47:50 PM PDT 24
Peak memory 217772 kb
Host smart-4f09e273-901c-4f12-95cc-49134728b307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996622423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1996622423
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1093047416
Short name T601
Test name
Test status
Simulation time 89828311 ps
CPU time 1.39 seconds
Started Jul 13 04:47:34 PM PDT 24
Finished Jul 13 04:47:36 PM PDT 24
Peak memory 217152 kb
Host smart-8541b797-9212-4071-a0bf-426ebfb8de24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093047416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1093047416
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.2508480287
Short name T588
Test name
Test status
Simulation time 2802728958 ps
CPU time 29 seconds
Started Jul 13 04:47:37 PM PDT 24
Finished Jul 13 04:48:08 PM PDT 24
Peak memory 250548 kb
Host smart-c59bceff-9c01-4b53-b892-db4fb8821063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508480287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2508480287
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.546063627
Short name T608
Test name
Test status
Simulation time 242835745 ps
CPU time 7.53 seconds
Started Jul 13 04:47:35 PM PDT 24
Finished Jul 13 04:47:45 PM PDT 24
Peak memory 250524 kb
Host smart-6f11122c-f610-4ed4-b133-af6a2d88fd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546063627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.546063627
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.4099942475
Short name T436
Test name
Test status
Simulation time 7538582513 ps
CPU time 108.85 seconds
Started Jul 13 04:47:35 PM PDT 24
Finished Jul 13 04:49:26 PM PDT 24
Peak memory 225580 kb
Host smart-10e3ce68-db16-4287-80fb-36a2d035d15b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099942475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.4099942475
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.2490043273
Short name T582
Test name
Test status
Simulation time 55019682162 ps
CPU time 595.42 seconds
Started Jul 13 04:47:35 PM PDT 24
Finished Jul 13 04:57:33 PM PDT 24
Peak memory 421588 kb
Host smart-5acef8f9-4d01-4c62-b964-ec9956506d51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2490043273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.2490043273
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3319286761
Short name T28
Test name
Test status
Simulation time 12599252 ps
CPU time 1.06 seconds
Started Jul 13 04:47:35 PM PDT 24
Finished Jul 13 04:47:38 PM PDT 24
Peak memory 208396 kb
Host smart-1e88ef4b-e18f-4580-a2be-1047a4421b7f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319286761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3319286761
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3055212003
Short name T503
Test name
Test status
Simulation time 97037893 ps
CPU time 1.05 seconds
Started Jul 13 04:47:37 PM PDT 24
Finished Jul 13 04:47:40 PM PDT 24
Peak memory 208456 kb
Host smart-84a9a49c-23f0-4832-b45a-ea35d31e74f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055212003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3055212003
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.692005358
Short name T239
Test name
Test status
Simulation time 305313794 ps
CPU time 9.63 seconds
Started Jul 13 04:47:34 PM PDT 24
Finished Jul 13 04:47:46 PM PDT 24
Peak memory 217772 kb
Host smart-96227dc4-ca91-43f2-8140-79717b7f3f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692005358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.692005358
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3218626905
Short name T292
Test name
Test status
Simulation time 222589758 ps
CPU time 6.38 seconds
Started Jul 13 04:47:36 PM PDT 24
Finished Jul 13 04:47:45 PM PDT 24
Peak memory 217124 kb
Host smart-d9cdb3e6-4e02-4fc7-b1ed-d1cb36ece27f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218626905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3218626905
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.1221177928
Short name T825
Test name
Test status
Simulation time 210805284 ps
CPU time 2.52 seconds
Started Jul 13 04:47:40 PM PDT 24
Finished Jul 13 04:47:43 PM PDT 24
Peak memory 221752 kb
Host smart-c357db42-cfd7-4f37-aa0b-c2c9d64f444a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221177928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1221177928
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.1161319884
Short name T783
Test name
Test status
Simulation time 670324254 ps
CPU time 14.08 seconds
Started Jul 13 04:47:36 PM PDT 24
Finished Jul 13 04:47:53 PM PDT 24
Peak memory 225508 kb
Host smart-1c9315a1-2362-48fd-bfc4-db631b0db668
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161319884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1161319884
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1285295607
Short name T749
Test name
Test status
Simulation time 398020398 ps
CPU time 13.77 seconds
Started Jul 13 04:47:34 PM PDT 24
Finished Jul 13 04:47:50 PM PDT 24
Peak memory 225448 kb
Host smart-11d406e3-7090-484d-b931-dcebfcf8b5a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285295607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1285295607
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.4215428123
Short name T491
Test name
Test status
Simulation time 1350722557 ps
CPU time 7.72 seconds
Started Jul 13 04:47:34 PM PDT 24
Finished Jul 13 04:47:44 PM PDT 24
Peak memory 217608 kb
Host smart-27a3062e-e64e-4bb2-a5c6-94d6d222807b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215428123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
4215428123
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2177003365
Short name T791
Test name
Test status
Simulation time 801698653 ps
CPU time 11.62 seconds
Started Jul 13 04:47:37 PM PDT 24
Finished Jul 13 04:47:51 PM PDT 24
Peak memory 224360 kb
Host smart-ccd0a306-f3c2-4668-a000-b28aafde43de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177003365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2177003365
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1751074105
Short name T779
Test name
Test status
Simulation time 92126571 ps
CPU time 1.48 seconds
Started Jul 13 04:47:35 PM PDT 24
Finished Jul 13 04:47:39 PM PDT 24
Peak memory 213136 kb
Host smart-5af19c6f-b404-43dd-81de-2643a05e0614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751074105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1751074105
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3529842269
Short name T329
Test name
Test status
Simulation time 679013808 ps
CPU time 25.17 seconds
Started Jul 13 04:47:37 PM PDT 24
Finished Jul 13 04:48:04 PM PDT 24
Peak memory 250424 kb
Host smart-c344ffd0-e865-4bb3-8950-c3b9e2ad393e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529842269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3529842269
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.382774708
Short name T686
Test name
Test status
Simulation time 179296285 ps
CPU time 6.5 seconds
Started Jul 13 04:47:37 PM PDT 24
Finished Jul 13 04:47:46 PM PDT 24
Peak memory 249872 kb
Host smart-248df6b0-9f52-4ebb-a4fd-46d5ad2e7f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382774708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.382774708
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2456159048
Short name T360
Test name
Test status
Simulation time 12446657266 ps
CPU time 55.26 seconds
Started Jul 13 04:47:36 PM PDT 24
Finished Jul 13 04:48:33 PM PDT 24
Peak memory 250416 kb
Host smart-37c42d3a-2888-49ea-84c0-cbf65b39cce7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456159048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2456159048
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2926729154
Short name T219
Test name
Test status
Simulation time 25576117 ps
CPU time 0.97 seconds
Started Jul 13 04:47:35 PM PDT 24
Finished Jul 13 04:47:38 PM PDT 24
Peak memory 208588 kb
Host smart-e6c3c916-d883-4b5e-97c0-bd4870d866b9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926729154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2926729154
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.583386535
Short name T223
Test name
Test status
Simulation time 61853137 ps
CPU time 0.93 seconds
Started Jul 13 04:47:37 PM PDT 24
Finished Jul 13 04:47:40 PM PDT 24
Peak memory 208336 kb
Host smart-a6f0dc6b-61a6-4727-aec9-d9c55d2c50c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583386535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.583386535
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1534525170
Short name T212
Test name
Test status
Simulation time 386750419 ps
CPU time 13.62 seconds
Started Jul 13 04:47:34 PM PDT 24
Finished Jul 13 04:47:48 PM PDT 24
Peak memory 225612 kb
Host smart-a528a2bc-4ac7-4577-b67a-9c1631e4cb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534525170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1534525170
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1156238141
Short name T26
Test name
Test status
Simulation time 269434310 ps
CPU time 2.17 seconds
Started Jul 13 04:47:37 PM PDT 24
Finished Jul 13 04:47:41 PM PDT 24
Peak memory 216604 kb
Host smart-96076c5f-41a2-410e-b2c0-a77638c77755
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156238141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1156238141
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.121095759
Short name T500
Test name
Test status
Simulation time 90124124 ps
CPU time 2.17 seconds
Started Jul 13 04:47:36 PM PDT 24
Finished Jul 13 04:47:41 PM PDT 24
Peak memory 217700 kb
Host smart-94f2e5c2-010b-4a9e-b7d0-517df07d7abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121095759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.121095759
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1203316820
Short name T45
Test name
Test status
Simulation time 254775663 ps
CPU time 11.54 seconds
Started Jul 13 04:47:37 PM PDT 24
Finished Jul 13 04:47:51 PM PDT 24
Peak memory 218380 kb
Host smart-659a1a64-8028-4dff-b8c2-60bf51923005
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203316820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1203316820
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1036047816
Short name T141
Test name
Test status
Simulation time 964085093 ps
CPU time 11.79 seconds
Started Jul 13 04:47:38 PM PDT 24
Finished Jul 13 04:47:51 PM PDT 24
Peak memory 225440 kb
Host smart-0c70c2ee-315b-4949-84c3-4af1167b34fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036047816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1036047816
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.256104618
Short name T3
Test name
Test status
Simulation time 278524426 ps
CPU time 7.78 seconds
Started Jul 13 04:47:39 PM PDT 24
Finished Jul 13 04:47:48 PM PDT 24
Peak memory 217624 kb
Host smart-9390d826-c5c8-47b9-b673-10c2c8dc52e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256104618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.256104618
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1868671044
Short name T363
Test name
Test status
Simulation time 602775877 ps
CPU time 12.58 seconds
Started Jul 13 04:47:38 PM PDT 24
Finished Jul 13 04:47:52 PM PDT 24
Peak memory 225464 kb
Host smart-8f123214-4b18-4064-b8d1-33379a09b178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868671044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1868671044
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3115576987
Short name T477
Test name
Test status
Simulation time 20218250 ps
CPU time 1.65 seconds
Started Jul 13 04:47:35 PM PDT 24
Finished Jul 13 04:47:39 PM PDT 24
Peak memory 213440 kb
Host smart-ea471c9e-50e2-4e2a-96a5-85adcaf9b9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115576987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3115576987
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3656923216
Short name T357
Test name
Test status
Simulation time 299287814 ps
CPU time 20.9 seconds
Started Jul 13 04:47:37 PM PDT 24
Finished Jul 13 04:48:00 PM PDT 24
Peak memory 250376 kb
Host smart-2f6f3c4c-9d11-4a33-9481-9e6cb2911d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656923216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3656923216
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.2345819982
Short name T747
Test name
Test status
Simulation time 388199661 ps
CPU time 8.15 seconds
Started Jul 13 04:47:35 PM PDT 24
Finished Jul 13 04:47:45 PM PDT 24
Peak memory 250416 kb
Host smart-13d22839-456e-49f4-adc7-c567507dd8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345819982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2345819982
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2834883099
Short name T405
Test name
Test status
Simulation time 4394636006 ps
CPU time 104.14 seconds
Started Jul 13 04:47:40 PM PDT 24
Finished Jul 13 04:49:24 PM PDT 24
Peak memory 269516 kb
Host smart-94f96cf5-26d1-4ca5-a1d5-822b90a4b205
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834883099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2834883099
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1265469883
Short name T297
Test name
Test status
Simulation time 79861028 ps
CPU time 0.79 seconds
Started Jul 13 04:47:37 PM PDT 24
Finished Jul 13 04:47:40 PM PDT 24
Peak memory 208352 kb
Host smart-1af25f54-7ad4-433e-beb8-1a09f9cfd0f9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265469883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1265469883
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.2865565355
Short name T420
Test name
Test status
Simulation time 49729235 ps
CPU time 1 seconds
Started Jul 13 04:47:53 PM PDT 24
Finished Jul 13 04:47:56 PM PDT 24
Peak memory 208400 kb
Host smart-060e9d3a-3f3b-4f37-b504-0f343e6b2ee7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865565355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2865565355
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1555671300
Short name T340
Test name
Test status
Simulation time 394361757 ps
CPU time 13.32 seconds
Started Jul 13 04:47:48 PM PDT 24
Finished Jul 13 04:48:03 PM PDT 24
Peak memory 217660 kb
Host smart-128374b6-4808-4545-a776-179d47955073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555671300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1555671300
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.942957481
Short name T333
Test name
Test status
Simulation time 79445255 ps
CPU time 1.37 seconds
Started Jul 13 04:47:44 PM PDT 24
Finished Jul 13 04:47:47 PM PDT 24
Peak memory 217076 kb
Host smart-6f759380-69cd-4a2a-a391-f0f1a56b51f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942957481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.942957481
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1408016384
Short name T470
Test name
Test status
Simulation time 38061332 ps
CPU time 2.56 seconds
Started Jul 13 04:47:45 PM PDT 24
Finished Jul 13 04:47:49 PM PDT 24
Peak memory 217508 kb
Host smart-0cc87d08-5284-4e55-80d6-322d37817f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408016384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1408016384
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.528658558
Short name T549
Test name
Test status
Simulation time 268734460 ps
CPU time 13.82 seconds
Started Jul 13 04:47:44 PM PDT 24
Finished Jul 13 04:47:59 PM PDT 24
Peak memory 217672 kb
Host smart-0e249d53-315c-4c2b-a2a6-90130f90cd1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528658558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.528658558
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2515998079
Short name T35
Test name
Test status
Simulation time 343102396 ps
CPU time 10.4 seconds
Started Jul 13 04:47:45 PM PDT 24
Finished Jul 13 04:47:58 PM PDT 24
Peak memory 225400 kb
Host smart-c5d6866a-6c68-42d8-873d-59169a452097
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515998079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2515998079
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3338588202
Short name T426
Test name
Test status
Simulation time 443495649 ps
CPU time 8.5 seconds
Started Jul 13 04:47:43 PM PDT 24
Finished Jul 13 04:47:52 PM PDT 24
Peak memory 225452 kb
Host smart-f8b89e77-000f-4b53-a386-9f73e6cecb87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338588202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3338588202
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1435761785
Short name T750
Test name
Test status
Simulation time 413870687 ps
CPU time 11.37 seconds
Started Jul 13 04:47:44 PM PDT 24
Finished Jul 13 04:47:57 PM PDT 24
Peak memory 217712 kb
Host smart-f6979c96-7e0b-4d69-9bec-7599a0ff5d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435761785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1435761785
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2728368599
Short name T315
Test name
Test status
Simulation time 28892108 ps
CPU time 2.03 seconds
Started Jul 13 04:47:39 PM PDT 24
Finished Jul 13 04:47:42 PM PDT 24
Peak memory 213336 kb
Host smart-4176925c-eb20-4ea9-9b5e-bb545e109855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728368599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2728368599
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1686258590
Short name T266
Test name
Test status
Simulation time 245842522 ps
CPU time 22.91 seconds
Started Jul 13 04:47:45 PM PDT 24
Finished Jul 13 04:48:10 PM PDT 24
Peak memory 250272 kb
Host smart-d9fca403-ef31-415b-a035-7ca7df22436a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686258590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1686258590
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.507627664
Short name T199
Test name
Test status
Simulation time 57372965 ps
CPU time 6.73 seconds
Started Jul 13 04:47:51 PM PDT 24
Finished Jul 13 04:48:01 PM PDT 24
Peak memory 250340 kb
Host smart-9c3601ff-ed6b-4791-bd0e-3bb3efb98bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507627664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.507627664
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.44280829
Short name T617
Test name
Test status
Simulation time 11273232665 ps
CPU time 114.53 seconds
Started Jul 13 04:47:44 PM PDT 24
Finished Jul 13 04:49:39 PM PDT 24
Peak memory 268320 kb
Host smart-7847d183-4a39-4d5f-84c9-a7b53b21da5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44280829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.lc_ctrl_stress_all.44280829
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.1977653130
Short name T134
Test name
Test status
Simulation time 13674266583 ps
CPU time 46.5 seconds
Started Jul 13 04:47:45 PM PDT 24
Finished Jul 13 04:48:34 PM PDT 24
Peak memory 242248 kb
Host smart-4a44e856-d09c-4dfa-b78d-a00c262a3568
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1977653130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.1977653130
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2095607352
Short name T702
Test name
Test status
Simulation time 133383897 ps
CPU time 0.98 seconds
Started Jul 13 04:47:42 PM PDT 24
Finished Jul 13 04:47:44 PM PDT 24
Peak memory 217264 kb
Host smart-4ac79400-8da7-421e-8381-e0407c02d84b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095607352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2095607352
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1491147608
Short name T744
Test name
Test status
Simulation time 22489539 ps
CPU time 1.37 seconds
Started Jul 13 04:47:49 PM PDT 24
Finished Jul 13 04:47:51 PM PDT 24
Peak memory 208504 kb
Host smart-50656f33-63af-4961-a4d9-43023a276a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491147608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1491147608
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1181109918
Short name T826
Test name
Test status
Simulation time 424243781 ps
CPU time 16.39 seconds
Started Jul 13 04:47:46 PM PDT 24
Finished Jul 13 04:48:04 PM PDT 24
Peak memory 217920 kb
Host smart-03b9ab15-4f76-4857-9970-f66192b96928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181109918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1181109918
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1647222979
Short name T815
Test name
Test status
Simulation time 890170304 ps
CPU time 5.63 seconds
Started Jul 13 04:47:44 PM PDT 24
Finished Jul 13 04:47:50 PM PDT 24
Peak memory 216692 kb
Host smart-d3e84bdf-7ffe-47bd-b6c6-9d00319a639d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647222979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1647222979
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.716122697
Short name T570
Test name
Test status
Simulation time 733486400 ps
CPU time 3.11 seconds
Started Jul 13 04:47:41 PM PDT 24
Finished Jul 13 04:47:45 PM PDT 24
Peak memory 217736 kb
Host smart-c5614c2a-7a66-47c3-8218-048f3c2415c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716122697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.716122697
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3731190630
Short name T501
Test name
Test status
Simulation time 1076884415 ps
CPU time 12.8 seconds
Started Jul 13 04:47:46 PM PDT 24
Finished Jul 13 04:48:01 PM PDT 24
Peak memory 218324 kb
Host smart-3edcc2bd-3dc5-453c-b23f-43f95200b1e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731190630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3731190630
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2682090611
Short name T723
Test name
Test status
Simulation time 1798774301 ps
CPU time 13.25 seconds
Started Jul 13 04:47:48 PM PDT 24
Finished Jul 13 04:48:02 PM PDT 24
Peak memory 225432 kb
Host smart-f40b1bdd-20bf-4666-a4ec-b6ee3ff3b643
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682090611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2682090611
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2597257197
Short name T264
Test name
Test status
Simulation time 328280986 ps
CPU time 8.92 seconds
Started Jul 13 04:47:46 PM PDT 24
Finished Jul 13 04:47:57 PM PDT 24
Peak memory 217480 kb
Host smart-693a190f-867e-49f6-85ca-e6704f368cdf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597257197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2597257197
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.760504998
Short name T746
Test name
Test status
Simulation time 1367605138 ps
CPU time 9.8 seconds
Started Jul 13 04:47:44 PM PDT 24
Finished Jul 13 04:47:55 PM PDT 24
Peak memory 224216 kb
Host smart-b49a910b-3657-4379-9abc-85f81a85e165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760504998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.760504998
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3597528128
Short name T866
Test name
Test status
Simulation time 85062773 ps
CPU time 2.84 seconds
Started Jul 13 04:47:48 PM PDT 24
Finished Jul 13 04:47:52 PM PDT 24
Peak memory 214236 kb
Host smart-922121be-2194-44fb-add3-9c1646c83b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597528128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3597528128
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.609800320
Short name T680
Test name
Test status
Simulation time 1054235673 ps
CPU time 24.21 seconds
Started Jul 13 04:47:53 PM PDT 24
Finished Jul 13 04:48:19 PM PDT 24
Peak memory 250420 kb
Host smart-869b5d90-eb16-49f0-a5dd-ce037f1fd755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609800320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.609800320
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3115050318
Short name T726
Test name
Test status
Simulation time 436633797 ps
CPU time 3.55 seconds
Started Jul 13 04:47:43 PM PDT 24
Finished Jul 13 04:47:48 PM PDT 24
Peak memory 225880 kb
Host smart-60c07ce1-a0e3-432e-8429-48b9933df57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115050318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3115050318
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3229965378
Short name T581
Test name
Test status
Simulation time 47558968691 ps
CPU time 337.11 seconds
Started Jul 13 04:47:46 PM PDT 24
Finished Jul 13 04:53:25 PM PDT 24
Peak memory 250464 kb
Host smart-c7b2047d-e278-4463-ac1a-d3dd5b435a31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229965378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3229965378
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3114707809
Short name T29
Test name
Test status
Simulation time 64407250 ps
CPU time 0.92 seconds
Started Jul 13 04:47:53 PM PDT 24
Finished Jul 13 04:47:56 PM PDT 24
Peak memory 208508 kb
Host smart-81584e0b-bc45-452a-b2a8-5fb14381218a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114707809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.3114707809
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3259810924
Short name T809
Test name
Test status
Simulation time 17575501 ps
CPU time 1 seconds
Started Jul 13 04:47:53 PM PDT 24
Finished Jul 13 04:47:56 PM PDT 24
Peak memory 208448 kb
Host smart-86e354ca-c561-43ae-b4a7-64a7c9add249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259810924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3259810924
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3278525322
Short name T411
Test name
Test status
Simulation time 201476074 ps
CPU time 9.29 seconds
Started Jul 13 04:47:47 PM PDT 24
Finished Jul 13 04:47:58 PM PDT 24
Peak memory 217652 kb
Host smart-0f4c8406-68a0-489f-9056-d67e9f73c065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278525322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3278525322
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2449230714
Short name T539
Test name
Test status
Simulation time 2580070574 ps
CPU time 15.9 seconds
Started Jul 13 04:47:51 PM PDT 24
Finished Jul 13 04:48:10 PM PDT 24
Peak memory 216540 kb
Host smart-b3fef440-c847-4d5e-9936-2537e9d696fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449230714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2449230714
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1510185768
Short name T455
Test name
Test status
Simulation time 129490571 ps
CPU time 3.04 seconds
Started Jul 13 04:47:48 PM PDT 24
Finished Jul 13 04:47:53 PM PDT 24
Peak memory 217716 kb
Host smart-49872b45-0428-49e3-96d7-2b0e91e1f014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510185768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1510185768
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.4117671083
Short name T208
Test name
Test status
Simulation time 420151100 ps
CPU time 7.44 seconds
Started Jul 13 04:47:43 PM PDT 24
Finished Jul 13 04:47:51 PM PDT 24
Peak memory 225448 kb
Host smart-7dc93608-5e33-4d08-833e-535b38cd5b12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117671083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.4117671083
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3546824270
Short name T216
Test name
Test status
Simulation time 458739083 ps
CPU time 9.92 seconds
Started Jul 13 04:47:43 PM PDT 24
Finished Jul 13 04:47:53 PM PDT 24
Peak memory 217672 kb
Host smart-9e83fbea-c65d-4b24-ba13-d343bbc6848a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546824270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
3546824270
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.4037472800
Short name T629
Test name
Test status
Simulation time 543643373 ps
CPU time 11.53 seconds
Started Jul 13 04:47:46 PM PDT 24
Finished Jul 13 04:48:00 PM PDT 24
Peak memory 224788 kb
Host smart-70fa9109-7c82-47bf-b388-72b5d5596877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037472800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.4037472800
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1045515484
Short name T859
Test name
Test status
Simulation time 18456202 ps
CPU time 1.5 seconds
Started Jul 13 04:47:44 PM PDT 24
Finished Jul 13 04:47:46 PM PDT 24
Peak memory 213356 kb
Host smart-3db20e4f-b2aa-4304-9fbb-f999a8d587c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045515484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1045515484
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2778135611
Short name T290
Test name
Test status
Simulation time 276076897 ps
CPU time 31.06 seconds
Started Jul 13 04:47:47 PM PDT 24
Finished Jul 13 04:48:20 PM PDT 24
Peak memory 250392 kb
Host smart-32c52bd2-b721-4372-b181-52958c64ab2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778135611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2778135611
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3901874507
Short name T648
Test name
Test status
Simulation time 177303354 ps
CPU time 11.45 seconds
Started Jul 13 04:47:51 PM PDT 24
Finished Jul 13 04:48:05 PM PDT 24
Peak memory 250276 kb
Host smart-c407917a-921d-4b9a-b8fa-a79a2315b6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901874507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3901874507
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.362989359
Short name T309
Test name
Test status
Simulation time 40125177882 ps
CPU time 192.82 seconds
Started Jul 13 04:47:44 PM PDT 24
Finished Jul 13 04:50:59 PM PDT 24
Peak memory 250528 kb
Host smart-18b85a23-56f2-4409-979c-709fe54efbed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362989359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.362989359
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.4119775456
Short name T437
Test name
Test status
Simulation time 14284420 ps
CPU time 0.89 seconds
Started Jul 13 04:47:45 PM PDT 24
Finished Jul 13 04:47:48 PM PDT 24
Peak memory 208380 kb
Host smart-3f061545-9e4c-4f60-a418-60b735b0e9f2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119775456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.4119775456
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.1188909074
Short name T367
Test name
Test status
Simulation time 12581369 ps
CPU time 0.93 seconds
Started Jul 13 04:47:52 PM PDT 24
Finished Jul 13 04:47:56 PM PDT 24
Peak memory 208344 kb
Host smart-96107f51-7b0f-412e-9633-83d071371d36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188909074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1188909074
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.542435252
Short name T730
Test name
Test status
Simulation time 3322576867 ps
CPU time 22.82 seconds
Started Jul 13 04:47:48 PM PDT 24
Finished Jul 13 04:48:12 PM PDT 24
Peak memory 218376 kb
Host smart-abc487a2-0ed7-42c8-acc5-a0a936948dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542435252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.542435252
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.288862604
Short name T25
Test name
Test status
Simulation time 1272323849 ps
CPU time 4.8 seconds
Started Jul 13 04:47:45 PM PDT 24
Finished Jul 13 04:47:52 PM PDT 24
Peak memory 217072 kb
Host smart-8be565d2-1f2d-48d7-ad62-af1eeba95c3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288862604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.288862604
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1691386828
Short name T672
Test name
Test status
Simulation time 46298902 ps
CPU time 2.13 seconds
Started Jul 13 04:47:41 PM PDT 24
Finished Jul 13 04:47:44 PM PDT 24
Peak memory 221648 kb
Host smart-b225062b-9a1e-486b-92ba-8101b53dbd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691386828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1691386828
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.2287685340
Short name T752
Test name
Test status
Simulation time 331145099 ps
CPU time 9.36 seconds
Started Jul 13 04:47:51 PM PDT 24
Finished Jul 13 04:48:03 PM PDT 24
Peak memory 224876 kb
Host smart-4a23d8df-4943-401f-871d-9b4d85e47d8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287685340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.2287685340
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.95419732
Short name T369
Test name
Test status
Simulation time 894310375 ps
CPU time 13.54 seconds
Started Jul 13 04:47:53 PM PDT 24
Finished Jul 13 04:48:09 PM PDT 24
Peak memory 225648 kb
Host smart-6f4e78e2-b20b-4bdf-bc66-7a660376440c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95419732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_dig
est.95419732
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.777309536
Short name T449
Test name
Test status
Simulation time 309667878 ps
CPU time 6.09 seconds
Started Jul 13 04:48:01 PM PDT 24
Finished Jul 13 04:48:09 PM PDT 24
Peak memory 223824 kb
Host smart-b8cacaf0-46e8-4f7b-8b8b-c0ed52c1c460
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777309536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.777309536
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3219361230
Short name T662
Test name
Test status
Simulation time 231207849 ps
CPU time 9.59 seconds
Started Jul 13 04:47:41 PM PDT 24
Finished Jul 13 04:47:51 PM PDT 24
Peak memory 217724 kb
Host smart-48762d9c-536c-4891-b782-64bf048e6600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219361230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3219361230
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2038085374
Short name T140
Test name
Test status
Simulation time 230236837 ps
CPU time 1.83 seconds
Started Jul 13 04:47:44 PM PDT 24
Finished Jul 13 04:47:46 PM PDT 24
Peak memory 217080 kb
Host smart-09118abe-9690-4dc5-b3e8-c04719555d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038085374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2038085374
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.417105523
Short name T652
Test name
Test status
Simulation time 300212334 ps
CPU time 22.03 seconds
Started Jul 13 04:47:48 PM PDT 24
Finished Jul 13 04:48:11 PM PDT 24
Peak memory 250328 kb
Host smart-6d987b7d-9ace-40c5-8b4e-193edb9a3aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417105523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.417105523
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3356295945
Short name T8
Test name
Test status
Simulation time 163405480 ps
CPU time 6 seconds
Started Jul 13 04:47:46 PM PDT 24
Finished Jul 13 04:47:54 PM PDT 24
Peak memory 246228 kb
Host smart-72f30117-50f3-4dfc-bce6-61632d79dc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356295945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3356295945
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.914422214
Short name T604
Test name
Test status
Simulation time 5417942407 ps
CPU time 40.15 seconds
Started Jul 13 04:47:56 PM PDT 24
Finished Jul 13 04:48:36 PM PDT 24
Peak memory 268132 kb
Host smart-c8fe8d42-cc5a-4c10-85cb-1e60093a597b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914422214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.914422214
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1782914007
Short name T543
Test name
Test status
Simulation time 12628255 ps
CPU time 1.09 seconds
Started Jul 13 04:47:51 PM PDT 24
Finished Jul 13 04:47:55 PM PDT 24
Peak memory 211328 kb
Host smart-5640efbe-804d-4cae-a3aa-4b0dc550c0a4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782914007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1782914007
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3471568108
Short name T254
Test name
Test status
Simulation time 83464591 ps
CPU time 1.02 seconds
Started Jul 13 04:47:53 PM PDT 24
Finished Jul 13 04:47:56 PM PDT 24
Peak memory 208460 kb
Host smart-e4415fb8-e4c3-4261-a8fb-632dd39b732b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471568108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3471568108
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2935672939
Short name T576
Test name
Test status
Simulation time 1127572073 ps
CPU time 11.09 seconds
Started Jul 13 04:47:50 PM PDT 24
Finished Jul 13 04:48:04 PM PDT 24
Peak memory 217868 kb
Host smart-d651c340-8b07-4fda-b430-cb00cf9e93c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935672939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2935672939
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3169991728
Short name T90
Test name
Test status
Simulation time 665343552 ps
CPU time 3.97 seconds
Started Jul 13 04:47:49 PM PDT 24
Finished Jul 13 04:47:55 PM PDT 24
Peak memory 217124 kb
Host smart-12cdb09c-fa5f-4e5a-8f2d-b8b8500aecd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169991728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3169991728
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.145683986
Short name T319
Test name
Test status
Simulation time 99455412 ps
CPU time 3.43 seconds
Started Jul 13 04:47:50 PM PDT 24
Finished Jul 13 04:47:56 PM PDT 24
Peak memory 217708 kb
Host smart-9639b4ee-7dba-43e5-b83a-e5414ae4cca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145683986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.145683986
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2170112695
Short name T732
Test name
Test status
Simulation time 1250825704 ps
CPU time 11.99 seconds
Started Jul 13 04:47:58 PM PDT 24
Finished Jul 13 04:48:11 PM PDT 24
Peak memory 225460 kb
Host smart-9a5ee73b-8618-4cd3-94c3-5ad5ebe781c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170112695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2170112695
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1050989803
Short name T312
Test name
Test status
Simulation time 3946469212 ps
CPU time 25.28 seconds
Started Jul 13 04:47:50 PM PDT 24
Finished Jul 13 04:48:18 PM PDT 24
Peak memory 225468 kb
Host smart-0936150c-38b4-438e-9e9e-97d5ee86347d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050989803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1050989803
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3335207309
Short name T515
Test name
Test status
Simulation time 690870268 ps
CPU time 7.33 seconds
Started Jul 13 04:47:52 PM PDT 24
Finished Jul 13 04:48:02 PM PDT 24
Peak memory 217652 kb
Host smart-586062f6-af59-4057-93cc-9061a5db78f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335207309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3335207309
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1889455331
Short name T317
Test name
Test status
Simulation time 1807181067 ps
CPU time 11.64 seconds
Started Jul 13 04:47:49 PM PDT 24
Finished Jul 13 04:48:03 PM PDT 24
Peak memory 224652 kb
Host smart-07ae5d22-8b52-4d5a-9768-d3faab12e6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889455331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1889455331
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.3654889474
Short name T82
Test name
Test status
Simulation time 149727053 ps
CPU time 3.24 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:48:06 PM PDT 24
Peak memory 217188 kb
Host smart-ee66064b-588e-4367-b5c1-43116aaea125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654889474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3654889474
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1104854681
Short name T409
Test name
Test status
Simulation time 889263356 ps
CPU time 20.74 seconds
Started Jul 13 04:47:53 PM PDT 24
Finished Jul 13 04:48:16 PM PDT 24
Peak memory 250460 kb
Host smart-2864bee3-87b8-45e0-a4dd-685f5cd44d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104854681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1104854681
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1035986398
Short name T190
Test name
Test status
Simulation time 78503043 ps
CPU time 8.84 seconds
Started Jul 13 04:47:51 PM PDT 24
Finished Jul 13 04:48:02 PM PDT 24
Peak memory 250464 kb
Host smart-d1b2f288-561f-4722-a0e9-53533b38beaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035986398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1035986398
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.924518192
Short name T497
Test name
Test status
Simulation time 23840137913 ps
CPU time 115.17 seconds
Started Jul 13 04:47:50 PM PDT 24
Finished Jul 13 04:49:48 PM PDT 24
Peak memory 270848 kb
Host smart-e1083b87-0d95-4369-9289-3bb25ddf4cfa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924518192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.924518192
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2500762956
Short name T314
Test name
Test status
Simulation time 34978184 ps
CPU time 0.85 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:48:03 PM PDT 24
Peak memory 208288 kb
Host smart-149e1ac4-14f8-4975-a5c0-6b9f47991455
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500762956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.2500762956
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2020538182
Short name T463
Test name
Test status
Simulation time 46172904 ps
CPU time 0.82 seconds
Started Jul 13 04:47:53 PM PDT 24
Finished Jul 13 04:47:56 PM PDT 24
Peak memory 208296 kb
Host smart-eabfe507-4b67-4f21-b262-883b541e66ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020538182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2020538182
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.468552316
Short name T811
Test name
Test status
Simulation time 2007893097 ps
CPU time 15.65 seconds
Started Jul 13 04:47:52 PM PDT 24
Finished Jul 13 04:48:10 PM PDT 24
Peak memory 225456 kb
Host smart-eb94beed-d783-4732-8e44-63df4253333a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468552316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.468552316
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3806106055
Short name T683
Test name
Test status
Simulation time 501866526 ps
CPU time 2.8 seconds
Started Jul 13 04:47:50 PM PDT 24
Finished Jul 13 04:47:56 PM PDT 24
Peak memory 217200 kb
Host smart-6d10f191-849a-4cd7-8bdb-632e99061e5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806106055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3806106055
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1515248837
Short name T204
Test name
Test status
Simulation time 39631636 ps
CPU time 2.55 seconds
Started Jul 13 04:47:50 PM PDT 24
Finished Jul 13 04:47:55 PM PDT 24
Peak memory 217660 kb
Host smart-b43e20af-ab52-4c32-be9f-ec5ccfd950a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515248837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1515248837
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3898288479
Short name T778
Test name
Test status
Simulation time 466154441 ps
CPU time 21.87 seconds
Started Jul 13 04:47:52 PM PDT 24
Finished Jul 13 04:48:16 PM PDT 24
Peak memory 225544 kb
Host smart-cd97efdb-bbe7-4bab-8b6a-c2c44da29016
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898288479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3898288479
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2594368982
Short name T258
Test name
Test status
Simulation time 376369669 ps
CPU time 9.98 seconds
Started Jul 13 04:47:51 PM PDT 24
Finished Jul 13 04:48:03 PM PDT 24
Peak memory 225444 kb
Host smart-7b9ea9b4-a32c-4be6-895b-76eaceb1e037
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594368982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2594368982
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2999424732
Short name T590
Test name
Test status
Simulation time 671738823 ps
CPU time 11.66 seconds
Started Jul 13 04:47:50 PM PDT 24
Finished Jul 13 04:48:04 PM PDT 24
Peak memory 217624 kb
Host smart-37427dcc-acf2-47a6-af9e-e0ba3a80b335
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999424732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2999424732
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1219785925
Short name T182
Test name
Test status
Simulation time 1446750807 ps
CPU time 12.59 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:48:14 PM PDT 24
Peak memory 217712 kb
Host smart-d967faac-cf4f-4a3f-aeee-1e998bf15a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219785925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1219785925
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3192262573
Short name T10
Test name
Test status
Simulation time 70952256 ps
CPU time 1 seconds
Started Jul 13 04:47:58 PM PDT 24
Finished Jul 13 04:47:59 PM PDT 24
Peak memory 208436 kb
Host smart-4b567014-e327-485b-ab09-94d40bf87162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192262573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3192262573
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1477716539
Short name T84
Test name
Test status
Simulation time 174737858 ps
CPU time 20.81 seconds
Started Jul 13 04:47:52 PM PDT 24
Finished Jul 13 04:48:15 PM PDT 24
Peak memory 243484 kb
Host smart-e33e22fb-b0e2-4d28-abc2-df7fc1636cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477716539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1477716539
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1648432906
Short name T34
Test name
Test status
Simulation time 74735398 ps
CPU time 8.38 seconds
Started Jul 13 04:47:53 PM PDT 24
Finished Jul 13 04:48:04 PM PDT 24
Peak memory 250420 kb
Host smart-8161519a-ed51-4228-99bd-769610dff4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648432906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1648432906
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1832845345
Short name T490
Test name
Test status
Simulation time 10034162642 ps
CPU time 315.48 seconds
Started Jul 13 04:48:01 PM PDT 24
Finished Jul 13 04:53:19 PM PDT 24
Peak memory 250456 kb
Host smart-05434187-dce7-407b-822b-1270f0047811
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832845345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1832845345
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.50621494
Short name T642
Test name
Test status
Simulation time 39368098145 ps
CPU time 868.14 seconds
Started Jul 13 04:47:53 PM PDT 24
Finished Jul 13 05:02:23 PM PDT 24
Peak memory 496416 kb
Host smart-8116e9c5-3ba6-4b0f-9336-30b6d285188b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=50621494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.50621494
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2891322183
Short name T364
Test name
Test status
Simulation time 44876562 ps
CPU time 0.81 seconds
Started Jul 13 04:47:53 PM PDT 24
Finished Jul 13 04:47:56 PM PDT 24
Peak memory 208252 kb
Host smart-28d6910c-d80d-4f3b-b590-582447a69f4d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891322183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2891322183
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.804543897
Short name T484
Test name
Test status
Simulation time 35997858 ps
CPU time 0.91 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:48:04 PM PDT 24
Peak memory 208320 kb
Host smart-08b6e94c-5142-4fd0-931e-7910c53e7ffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804543897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.804543897
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2960635509
Short name T567
Test name
Test status
Simulation time 596292074 ps
CPU time 12.82 seconds
Started Jul 13 04:48:02 PM PDT 24
Finished Jul 13 04:48:16 PM PDT 24
Peak memory 217680 kb
Host smart-f7209395-c28a-46b0-a057-21519926f065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960635509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2960635509
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.238322903
Short name T381
Test name
Test status
Simulation time 283965216 ps
CPU time 2.96 seconds
Started Jul 13 04:47:51 PM PDT 24
Finished Jul 13 04:47:56 PM PDT 24
Peak memory 217708 kb
Host smart-5699f0d3-09dc-4fb2-ac19-066e73ff43c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238322903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.238322903
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3325129763
Short name T392
Test name
Test status
Simulation time 386270050 ps
CPU time 13.29 seconds
Started Jul 13 04:47:59 PM PDT 24
Finished Jul 13 04:48:15 PM PDT 24
Peak memory 225532 kb
Host smart-ea724dd9-b3c0-404b-9737-0f60ec3b3e10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325129763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3325129763
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2419912909
Short name T225
Test name
Test status
Simulation time 822767182 ps
CPU time 10.13 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:48:12 PM PDT 24
Peak memory 217556 kb
Host smart-ecb041e4-a6ab-4248-b154-ff5c6e77ffeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419912909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2419912909
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1044099700
Short name T325
Test name
Test status
Simulation time 858744674 ps
CPU time 14.16 seconds
Started Jul 13 04:48:02 PM PDT 24
Finished Jul 13 04:48:18 PM PDT 24
Peak memory 225380 kb
Host smart-bff7ce3d-6656-448e-8761-503b8a065adc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044099700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1044099700
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.4122148015
Short name T719
Test name
Test status
Simulation time 416307790 ps
CPU time 9.4 seconds
Started Jul 13 04:47:58 PM PDT 24
Finished Jul 13 04:48:09 PM PDT 24
Peak memory 225528 kb
Host smart-adf7ac00-985a-4ae8-847c-71dee40ad0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122148015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.4122148015
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.826891167
Short name T657
Test name
Test status
Simulation time 65480040 ps
CPU time 1.04 seconds
Started Jul 13 04:47:53 PM PDT 24
Finished Jul 13 04:47:56 PM PDT 24
Peak memory 211540 kb
Host smart-20b02f5a-f3dd-469f-ac7d-eb417a951404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826891167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.826891167
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.52123503
Short name T407
Test name
Test status
Simulation time 679766920 ps
CPU time 24.07 seconds
Started Jul 13 04:48:01 PM PDT 24
Finished Jul 13 04:48:28 PM PDT 24
Peak memory 245388 kb
Host smart-03e97d85-636c-429d-ba3b-f455bb2ee6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52123503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.52123503
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3670180024
Short name T741
Test name
Test status
Simulation time 232538914 ps
CPU time 3.6 seconds
Started Jul 13 04:47:56 PM PDT 24
Finished Jul 13 04:48:00 PM PDT 24
Peak memory 221788 kb
Host smart-aa206e8b-4d13-49e8-83c2-e65eee34c754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670180024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3670180024
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3455071939
Short name T610
Test name
Test status
Simulation time 15513814099 ps
CPU time 55.9 seconds
Started Jul 13 04:47:57 PM PDT 24
Finished Jul 13 04:48:53 PM PDT 24
Peak memory 224484 kb
Host smart-af3f9990-7b76-4f21-a292-b6955e9ab01f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455071939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3455071939
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2912211009
Short name T737
Test name
Test status
Simulation time 37813867 ps
CPU time 0.93 seconds
Started Jul 13 04:47:51 PM PDT 24
Finished Jul 13 04:47:54 PM PDT 24
Peak memory 208544 kb
Host smart-ddbad9f3-2fea-4d59-a3de-9ef31ad0a752
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912211009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2912211009
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3222325239
Short name T87
Test name
Test status
Simulation time 11917133 ps
CPU time 1.02 seconds
Started Jul 13 04:46:13 PM PDT 24
Finished Jul 13 04:46:14 PM PDT 24
Peak memory 208492 kb
Host smart-dc5d8238-a8b3-4ac4-8e24-c0b8657e0de9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222325239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3222325239
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3298007458
Short name T194
Test name
Test status
Simulation time 11085362 ps
CPU time 0.93 seconds
Started Jul 13 04:46:05 PM PDT 24
Finished Jul 13 04:46:06 PM PDT 24
Peak memory 208608 kb
Host smart-44d49994-4689-4344-8f38-9ad81c14eeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298007458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3298007458
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.2852236217
Short name T417
Test name
Test status
Simulation time 588883744 ps
CPU time 9.32 seconds
Started Jul 13 04:46:04 PM PDT 24
Finished Jul 13 04:46:14 PM PDT 24
Peak memory 217684 kb
Host smart-e66bdd5e-880c-4ec5-a0a2-5e4f81fd45f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852236217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2852236217
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.4192674222
Short name T623
Test name
Test status
Simulation time 1489355502 ps
CPU time 5.17 seconds
Started Jul 13 04:46:00 PM PDT 24
Finished Jul 13 04:46:06 PM PDT 24
Peak memory 216596 kb
Host smart-5058c838-3b26-41f7-9969-c32c938697bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192674222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.4192674222
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3087169830
Short name T788
Test name
Test status
Simulation time 15043288855 ps
CPU time 23.56 seconds
Started Jul 13 04:46:02 PM PDT 24
Finished Jul 13 04:46:27 PM PDT 24
Peak memory 218380 kb
Host smart-553a418d-77f0-4d77-9e85-80063e5d9e7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087169830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3087169830
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.549844488
Short name T847
Test name
Test status
Simulation time 445454553 ps
CPU time 5.31 seconds
Started Jul 13 04:46:02 PM PDT 24
Finished Jul 13 04:46:09 PM PDT 24
Peak memory 217140 kb
Host smart-2810308e-8f0d-4442-8e75-38e9c590d7b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549844488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.549844488
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1340898771
Short name T740
Test name
Test status
Simulation time 747949271 ps
CPU time 5.65 seconds
Started Jul 13 04:46:02 PM PDT 24
Finished Jul 13 04:46:10 PM PDT 24
Peak memory 217652 kb
Host smart-4e2b5185-1564-41e4-bcee-d8a38a55b4bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340898771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1340898771
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1782132362
Short name T537
Test name
Test status
Simulation time 881115719 ps
CPU time 24.61 seconds
Started Jul 13 04:46:02 PM PDT 24
Finished Jul 13 04:46:29 PM PDT 24
Peak memory 217064 kb
Host smart-16b1ccd4-d3f4-4302-b3ae-3919fe2d2ed2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782132362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1782132362
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2355965015
Short name T453
Test name
Test status
Simulation time 94752571 ps
CPU time 3.54 seconds
Started Jul 13 04:46:03 PM PDT 24
Finished Jul 13 04:46:08 PM PDT 24
Peak memory 217000 kb
Host smart-cb217c53-55de-4993-a50a-45f45dae606a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355965015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2355965015
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3255410051
Short name T614
Test name
Test status
Simulation time 5789240971 ps
CPU time 40.96 seconds
Started Jul 13 04:46:00 PM PDT 24
Finished Jul 13 04:46:41 PM PDT 24
Peak memory 274932 kb
Host smart-c8509018-ea42-48e7-9fdb-bb69823b90cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255410051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3255410051
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2200751913
Short name T318
Test name
Test status
Simulation time 1735431600 ps
CPU time 18.95 seconds
Started Jul 13 04:46:02 PM PDT 24
Finished Jul 13 04:46:22 PM PDT 24
Peak memory 250396 kb
Host smart-598d3d18-f769-4667-993d-7fff17d5d500
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200751913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2200751913
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.673297944
Short name T651
Test name
Test status
Simulation time 208653533 ps
CPU time 2.52 seconds
Started Jul 13 04:46:02 PM PDT 24
Finished Jul 13 04:46:06 PM PDT 24
Peak memory 221820 kb
Host smart-e36e2359-2ee7-42a4-800f-de4efa68958d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673297944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.673297944
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2131278397
Short name T632
Test name
Test status
Simulation time 398134228 ps
CPU time 26.3 seconds
Started Jul 13 04:46:01 PM PDT 24
Finished Jul 13 04:46:29 PM PDT 24
Peak memory 213700 kb
Host smart-40ae63da-cfd5-4ac8-9a10-c44696ff13ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131278397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2131278397
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1023367622
Short name T423
Test name
Test status
Simulation time 468522794 ps
CPU time 9.06 seconds
Started Jul 13 04:46:10 PM PDT 24
Finished Jul 13 04:46:20 PM PDT 24
Peak memory 217732 kb
Host smart-500c5140-2c9b-4e0b-948a-008c5b2ea220
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023367622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1023367622
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2754047985
Short name T864
Test name
Test status
Simulation time 1209976282 ps
CPU time 9.91 seconds
Started Jul 13 04:46:11 PM PDT 24
Finished Jul 13 04:46:21 PM PDT 24
Peak memory 225460 kb
Host smart-83c1b2f7-f109-40ee-ac92-e37cd3d0610a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754047985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2754047985
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1949801455
Short name T279
Test name
Test status
Simulation time 1257853530 ps
CPU time 9.52 seconds
Started Jul 13 04:46:13 PM PDT 24
Finished Jul 13 04:46:23 PM PDT 24
Peak memory 217608 kb
Host smart-f7e5ddee-df88-4d89-86b3-970a3c0d07e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949801455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
949801455
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.474011723
Short name T59
Test name
Test status
Simulation time 1058655049 ps
CPU time 9.95 seconds
Started Jul 13 04:46:03 PM PDT 24
Finished Jul 13 04:46:14 PM PDT 24
Peak memory 225444 kb
Host smart-d2dcc33a-6716-46d2-b61f-46d7c9869c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474011723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.474011723
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.2293292320
Short name T810
Test name
Test status
Simulation time 102102808 ps
CPU time 2.13 seconds
Started Jul 13 04:45:59 PM PDT 24
Finished Jul 13 04:46:01 PM PDT 24
Peak memory 223224 kb
Host smart-3c098160-16e9-4177-ae69-d02d3bb284fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293292320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.2293292320
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.2726654343
Short name T215
Test name
Test status
Simulation time 205669769 ps
CPU time 18.08 seconds
Started Jul 13 04:46:02 PM PDT 24
Finished Jul 13 04:46:21 PM PDT 24
Peak memory 250400 kb
Host smart-d0aae53e-16a9-4f99-b75b-13a29abe33d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726654343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2726654343
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2448791401
Short name T487
Test name
Test status
Simulation time 222508634 ps
CPU time 3.55 seconds
Started Jul 13 04:46:01 PM PDT 24
Finished Jul 13 04:46:06 PM PDT 24
Peak memory 222080 kb
Host smart-7faec8a8-8954-4680-9f6c-4b5dddc0c7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448791401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2448791401
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3397080709
Short name T620
Test name
Test status
Simulation time 5923368822 ps
CPU time 191.26 seconds
Started Jul 13 04:46:10 PM PDT 24
Finished Jul 13 04:49:22 PM PDT 24
Peak memory 275176 kb
Host smart-dc724dda-63e6-4ac1-92e6-64111d5c0f46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397080709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3397080709
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.432833237
Short name T514
Test name
Test status
Simulation time 14588970 ps
CPU time 1 seconds
Started Jul 13 04:46:02 PM PDT 24
Finished Jul 13 04:46:04 PM PDT 24
Peak memory 208400 kb
Host smart-f9bb45a1-1c78-4f9d-967e-d0ce6b5b46ff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432833237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.432833237
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.283781575
Short name T275
Test name
Test status
Simulation time 36951551 ps
CPU time 1.25 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:48:04 PM PDT 24
Peak memory 208312 kb
Host smart-000b1971-9a81-4213-a462-41811b8c1abe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283781575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.283781575
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1960596854
Short name T548
Test name
Test status
Simulation time 250990649 ps
CPU time 8.29 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:48:11 PM PDT 24
Peak memory 225348 kb
Host smart-64178547-0b39-4b75-83b6-25f9ad46516e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960596854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1960596854
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1592827402
Short name T445
Test name
Test status
Simulation time 3787724355 ps
CPU time 6.87 seconds
Started Jul 13 04:47:58 PM PDT 24
Finished Jul 13 04:48:06 PM PDT 24
Peak memory 217224 kb
Host smart-d5635157-6ca6-4960-b06f-54548412a000
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592827402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1592827402
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2973938376
Short name T429
Test name
Test status
Simulation time 88316761 ps
CPU time 3.38 seconds
Started Jul 13 04:47:59 PM PDT 24
Finished Jul 13 04:48:04 PM PDT 24
Peak memory 222036 kb
Host smart-b5ea6158-48a0-4dfb-ab1c-85541d8ec8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973938376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2973938376
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.321202378
Short name T520
Test name
Test status
Simulation time 5535548993 ps
CPU time 12.7 seconds
Started Jul 13 04:47:58 PM PDT 24
Finished Jul 13 04:48:12 PM PDT 24
Peak memory 218424 kb
Host smart-602768d8-5841-4e61-a51a-5ad31c6884d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321202378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.321202378
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2368781303
Short name T782
Test name
Test status
Simulation time 531338299 ps
CPU time 9.45 seconds
Started Jul 13 04:47:59 PM PDT 24
Finished Jul 13 04:48:09 PM PDT 24
Peak memory 225380 kb
Host smart-e8e5c681-ce14-4d75-a79a-917b5c92e9f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368781303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2368781303
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.536564968
Short name T330
Test name
Test status
Simulation time 500887988 ps
CPU time 17.71 seconds
Started Jul 13 04:47:58 PM PDT 24
Finished Jul 13 04:48:16 PM PDT 24
Peak memory 217652 kb
Host smart-47a8c8b2-e398-4882-ad66-22db307423d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536564968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.536564968
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2148489793
Short name T842
Test name
Test status
Simulation time 933473821 ps
CPU time 10.4 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:48:13 PM PDT 24
Peak memory 225464 kb
Host smart-1d2151f6-1b67-4120-b0a3-250806153951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148489793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2148489793
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.2410174333
Short name T848
Test name
Test status
Simulation time 99130112 ps
CPU time 3.37 seconds
Started Jul 13 04:47:59 PM PDT 24
Finished Jul 13 04:48:04 PM PDT 24
Peak memory 217128 kb
Host smart-260650a7-db4b-42c7-ac16-285286ad6f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410174333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.2410174333
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.2536553497
Short name T144
Test name
Test status
Simulation time 260044279 ps
CPU time 30.27 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:48:32 PM PDT 24
Peak memory 245944 kb
Host smart-9efee023-a861-4354-9577-3200c6695a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536553497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2536553497
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2809692452
Short name T430
Test name
Test status
Simulation time 666394262 ps
CPU time 6.86 seconds
Started Jul 13 04:47:59 PM PDT 24
Finished Jul 13 04:48:08 PM PDT 24
Peak memory 249916 kb
Host smart-f500da59-46b4-443d-a141-6ca93d2f3c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809692452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2809692452
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2550160740
Short name T529
Test name
Test status
Simulation time 31700229441 ps
CPU time 164.22 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:50:46 PM PDT 24
Peak memory 283212 kb
Host smart-c03cd8e6-6b5d-4b57-a644-7e914bedc190
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550160740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2550160740
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1716038938
Short name T412
Test name
Test status
Simulation time 13816724 ps
CPU time 1.03 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:48:03 PM PDT 24
Peak memory 208412 kb
Host smart-f932b8e2-ec4c-4dd3-8a00-47564ddbd863
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716038938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1716038938
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2323798227
Short name T366
Test name
Test status
Simulation time 27816062 ps
CPU time 1.31 seconds
Started Jul 13 04:48:05 PM PDT 24
Finished Jul 13 04:48:07 PM PDT 24
Peak memory 208444 kb
Host smart-8fde3b77-c005-4d2d-b1ed-c91b15eb9396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323798227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2323798227
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1258517680
Short name T572
Test name
Test status
Simulation time 505970358 ps
CPU time 11.18 seconds
Started Jul 13 04:47:58 PM PDT 24
Finished Jul 13 04:48:09 PM PDT 24
Peak memory 217668 kb
Host smart-2a5d4596-fcb4-475f-9c77-c434d6fccb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258517680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1258517680
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1273720773
Short name T21
Test name
Test status
Simulation time 166577880 ps
CPU time 2.44 seconds
Started Jul 13 04:47:59 PM PDT 24
Finished Jul 13 04:48:02 PM PDT 24
Peak memory 217196 kb
Host smart-089deb50-42a9-4e6b-b68e-e5b168caa15c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273720773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1273720773
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1484180562
Short name T203
Test name
Test status
Simulation time 28748603 ps
CPU time 1.7 seconds
Started Jul 13 04:48:03 PM PDT 24
Finished Jul 13 04:48:06 PM PDT 24
Peak memory 217716 kb
Host smart-9276ac21-f370-4d33-835f-3e0e3a2645c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484180562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1484180562
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1878682318
Short name T347
Test name
Test status
Simulation time 1365271655 ps
CPU time 14.64 seconds
Started Jul 13 04:48:01 PM PDT 24
Finished Jul 13 04:48:18 PM PDT 24
Peak memory 225448 kb
Host smart-45201433-5372-41ad-9743-44dd30a9c206
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878682318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1878682318
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3771434974
Short name T554
Test name
Test status
Simulation time 2892059519 ps
CPU time 11.12 seconds
Started Jul 13 04:48:02 PM PDT 24
Finished Jul 13 04:48:15 PM PDT 24
Peak memory 225464 kb
Host smart-ee12815c-7d22-4550-8c15-5c5d4859e255
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771434974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.3771434974
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.230862195
Short name T734
Test name
Test status
Simulation time 1443302373 ps
CPU time 12.77 seconds
Started Jul 13 04:47:58 PM PDT 24
Finished Jul 13 04:48:12 PM PDT 24
Peak memory 217636 kb
Host smart-5dde2a95-4a38-4fa4-b9f0-2f8b2470b13d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230862195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.230862195
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3784030063
Short name T510
Test name
Test status
Simulation time 966273045 ps
CPU time 6.29 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:48:08 PM PDT 24
Peak memory 217724 kb
Host smart-5b85be94-de81-4df8-bd58-7c339c44121e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784030063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3784030063
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1007823221
Short name T438
Test name
Test status
Simulation time 444293835 ps
CPU time 2.64 seconds
Started Jul 13 04:48:01 PM PDT 24
Finished Jul 13 04:48:06 PM PDT 24
Peak memory 213720 kb
Host smart-7c93f404-ab49-49f4-a707-66fa1d9f04ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007823221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1007823221
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.219335530
Short name T522
Test name
Test status
Simulation time 1107089355 ps
CPU time 18 seconds
Started Jul 13 04:48:01 PM PDT 24
Finished Jul 13 04:48:21 PM PDT 24
Peak memory 250328 kb
Host smart-7d87d0e7-03f3-4088-b675-cdd9ac8a1b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219335530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.219335530
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2456964789
Short name T644
Test name
Test status
Simulation time 214065600 ps
CPU time 6.64 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:48:09 PM PDT 24
Peak memory 250388 kb
Host smart-e22cdd4f-1c06-4d2b-8b44-a5213f17df33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456964789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2456964789
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.4279614120
Short name T861
Test name
Test status
Simulation time 7449115319 ps
CPU time 263.05 seconds
Started Jul 13 04:47:58 PM PDT 24
Finished Jul 13 04:52:22 PM PDT 24
Peak memory 316172 kb
Host smart-d62bfae4-524e-40cb-a4db-1b0cefde4294
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279614120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.4279614120
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3446604884
Short name T242
Test name
Test status
Simulation time 14532980 ps
CPU time 1.06 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:48:03 PM PDT 24
Peak memory 211324 kb
Host smart-4e53246e-539b-4876-8759-2e1609efd5a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446604884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3446604884
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3071455913
Short name T541
Test name
Test status
Simulation time 20290077 ps
CPU time 0.81 seconds
Started Jul 13 04:48:07 PM PDT 24
Finished Jul 13 04:48:08 PM PDT 24
Peak memory 208272 kb
Host smart-e91d4f47-cddb-4ebe-b287-ed94cfb4b9f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071455913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3071455913
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3683718086
Short name T860
Test name
Test status
Simulation time 3049780285 ps
CPU time 15.81 seconds
Started Jul 13 04:47:59 PM PDT 24
Finished Jul 13 04:48:16 PM PDT 24
Peak memory 218428 kb
Host smart-24481a70-94ce-4fb4-bc7c-e5dbde6d2f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683718086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3683718086
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.4127600994
Short name T218
Test name
Test status
Simulation time 129992930 ps
CPU time 3.94 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:48:06 PM PDT 24
Peak memory 217124 kb
Host smart-c8b16659-c96e-4aae-bda6-1074803035f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127600994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.4127600994
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3651308907
Short name T452
Test name
Test status
Simulation time 48595090 ps
CPU time 2.25 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:48:04 PM PDT 24
Peak memory 221396 kb
Host smart-c5117542-b7e8-4d38-95e0-2c0b87d47bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651308907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3651308907
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1313097069
Short name T240
Test name
Test status
Simulation time 544028260 ps
CPU time 14.73 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:48:16 PM PDT 24
Peak memory 225420 kb
Host smart-5278d521-36bf-4ce2-be20-0a6b1c6b25fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313097069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1313097069
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3093135246
Short name T585
Test name
Test status
Simulation time 755989863 ps
CPU time 16.72 seconds
Started Jul 13 04:48:05 PM PDT 24
Finished Jul 13 04:48:22 PM PDT 24
Peak memory 225388 kb
Host smart-7f185ea3-3e31-49d9-90bf-6ef4fbf76a5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093135246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3093135246
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.210262644
Short name T462
Test name
Test status
Simulation time 1260263542 ps
CPU time 8.52 seconds
Started Jul 13 04:48:03 PM PDT 24
Finished Jul 13 04:48:13 PM PDT 24
Peak memory 225448 kb
Host smart-889bfd0c-f1cb-4d6a-b564-16b9200e0265
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210262644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.210262644
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.901373085
Short name T241
Test name
Test status
Simulation time 365628026 ps
CPU time 3.5 seconds
Started Jul 13 04:47:59 PM PDT 24
Finished Jul 13 04:48:03 PM PDT 24
Peak memory 217080 kb
Host smart-1c8c0080-6a45-4bfd-a94d-545656f9920f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901373085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.901373085
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3338216439
Short name T434
Test name
Test status
Simulation time 1359557776 ps
CPU time 30.65 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:48:33 PM PDT 24
Peak memory 250460 kb
Host smart-182f3a54-f012-403f-b354-9bb424b1784e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338216439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3338216439
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3881164287
Short name T513
Test name
Test status
Simulation time 85365553 ps
CPU time 8.97 seconds
Started Jul 13 04:48:02 PM PDT 24
Finished Jul 13 04:48:13 PM PDT 24
Peak memory 250392 kb
Host smart-ee18a116-c400-4644-9e14-e7b64a066845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881164287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3881164287
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.625233067
Short name T715
Test name
Test status
Simulation time 6453629504 ps
CPU time 101.6 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:49:44 PM PDT 24
Peak memory 271796 kb
Host smart-42739bd9-ad03-4e48-9301-f99545c63b06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625233067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.625233067
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3509923837
Short name T834
Test name
Test status
Simulation time 29827723163 ps
CPU time 265.19 seconds
Started Jul 13 04:48:06 PM PDT 24
Finished Jul 13 04:52:32 PM PDT 24
Peak memory 259664 kb
Host smart-ae025dfd-27bb-406a-be92-0b429da888c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3509923837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.3509923837
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.615338018
Short name T496
Test name
Test status
Simulation time 50797737 ps
CPU time 0.83 seconds
Started Jul 13 04:48:00 PM PDT 24
Finished Jul 13 04:48:03 PM PDT 24
Peak memory 208456 kb
Host smart-066e0739-4b0f-413d-8e7a-88f4fe25392b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615338018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct
rl_volatile_unlock_smoke.615338018
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.99688663
Short name T718
Test name
Test status
Simulation time 446704185 ps
CPU time 0.95 seconds
Started Jul 13 04:48:07 PM PDT 24
Finished Jul 13 04:48:08 PM PDT 24
Peak memory 208412 kb
Host smart-ff43a389-52b0-41ae-ae51-6d156ed8b528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99688663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.99688663
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3000381180
Short name T616
Test name
Test status
Simulation time 1218625090 ps
CPU time 11.86 seconds
Started Jul 13 04:48:08 PM PDT 24
Finished Jul 13 04:48:20 PM PDT 24
Peak memory 217680 kb
Host smart-91d1ec87-b4b2-4104-8a38-5ddd0bc0a394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000381180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3000381180
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2257420271
Short name T20
Test name
Test status
Simulation time 350717051 ps
CPU time 9.67 seconds
Started Jul 13 04:48:08 PM PDT 24
Finished Jul 13 04:48:18 PM PDT 24
Peak memory 217132 kb
Host smart-c5d14c10-6e7a-42a2-bf31-0bf20594a441
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257420271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2257420271
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3960694607
Short name T789
Test name
Test status
Simulation time 216057168 ps
CPU time 2.42 seconds
Started Jul 13 04:48:09 PM PDT 24
Finished Jul 13 04:48:13 PM PDT 24
Peak memory 217732 kb
Host smart-f129cf44-0cba-475e-8e39-4ea87f020982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960694607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3960694607
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3257505485
Short name T761
Test name
Test status
Simulation time 623744181 ps
CPU time 9.9 seconds
Started Jul 13 04:48:10 PM PDT 24
Finished Jul 13 04:48:22 PM PDT 24
Peak memory 225508 kb
Host smart-b921b4dd-7a63-4ead-85df-18b89d6e1230
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257505485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3257505485
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3674631669
Short name T374
Test name
Test status
Simulation time 2253479635 ps
CPU time 11.31 seconds
Started Jul 13 04:48:10 PM PDT 24
Finished Jul 13 04:48:23 PM PDT 24
Peak memory 225496 kb
Host smart-2b910bee-af8c-4dce-8afa-b117e59669ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674631669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3674631669
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.4176379775
Short name T850
Test name
Test status
Simulation time 442845930 ps
CPU time 7.79 seconds
Started Jul 13 04:48:10 PM PDT 24
Finished Jul 13 04:48:20 PM PDT 24
Peak memory 217608 kb
Host smart-426ccc05-5b88-4e56-bfb7-4531e587cc44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176379775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
4176379775
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3139674505
Short name T55
Test name
Test status
Simulation time 1409527524 ps
CPU time 9.78 seconds
Started Jul 13 04:48:09 PM PDT 24
Finished Jul 13 04:48:20 PM PDT 24
Peak memory 224364 kb
Host smart-6e09eee7-c21e-4615-8a79-161495133133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139674505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3139674505
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.810601680
Short name T71
Test name
Test status
Simulation time 60374591 ps
CPU time 2.84 seconds
Started Jul 13 04:48:11 PM PDT 24
Finished Jul 13 04:48:15 PM PDT 24
Peak memory 217080 kb
Host smart-1d5e6ee3-a3dc-43de-a6c5-17ff2cbd63fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810601680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.810601680
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.793215513
Short name T580
Test name
Test status
Simulation time 424980007 ps
CPU time 30.19 seconds
Started Jul 13 04:48:09 PM PDT 24
Finished Jul 13 04:48:41 PM PDT 24
Peak memory 250576 kb
Host smart-f2f4e017-062a-48ac-85f5-f3788c2fc7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793215513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.793215513
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1730246113
Short name T399
Test name
Test status
Simulation time 110784469 ps
CPU time 7.67 seconds
Started Jul 13 04:48:11 PM PDT 24
Finished Jul 13 04:48:20 PM PDT 24
Peak memory 250444 kb
Host smart-a882fdcb-0b5d-4b03-b6e2-f03313f5854c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730246113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1730246113
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2059004706
Short name T94
Test name
Test status
Simulation time 117465137710 ps
CPU time 256.44 seconds
Started Jul 13 04:48:08 PM PDT 24
Finished Jul 13 04:52:26 PM PDT 24
Peak memory 329388 kb
Host smart-a1bee78c-c06b-4553-9224-33c2f642a5ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059004706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2059004706
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.1410115564
Short name T47
Test name
Test status
Simulation time 87566873852 ps
CPU time 932.16 seconds
Started Jul 13 04:48:10 PM PDT 24
Finished Jul 13 05:03:44 PM PDT 24
Peak memory 332492 kb
Host smart-1e0a8338-5320-44b6-9b7d-1f79166f107c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1410115564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.1410115564
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3433324013
Short name T742
Test name
Test status
Simulation time 35103313 ps
CPU time 0.99 seconds
Started Jul 13 04:48:08 PM PDT 24
Finished Jul 13 04:48:11 PM PDT 24
Peak memory 211328 kb
Host smart-e57efc11-010f-4edd-8a8a-cf3072feb634
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433324013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3433324013
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1807741411
Short name T569
Test name
Test status
Simulation time 21557229 ps
CPU time 1.15 seconds
Started Jul 13 04:48:07 PM PDT 24
Finished Jul 13 04:48:09 PM PDT 24
Peak memory 208532 kb
Host smart-9e295cef-e478-4bbb-bb3f-7f90e5f8eddb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807741411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1807741411
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.616426296
Short name T622
Test name
Test status
Simulation time 1486381368 ps
CPU time 12.57 seconds
Started Jul 13 04:48:08 PM PDT 24
Finished Jul 13 04:48:23 PM PDT 24
Peak memory 217744 kb
Host smart-19a972a2-f062-45a9-b097-840476ee8811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616426296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.616426296
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.4143229919
Short name T613
Test name
Test status
Simulation time 165985830 ps
CPU time 1.3 seconds
Started Jul 13 04:48:09 PM PDT 24
Finished Jul 13 04:48:12 PM PDT 24
Peak memory 217200 kb
Host smart-c0964c48-c5e8-4edb-becd-240da57c2a82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143229919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.4143229919
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1467210227
Short name T547
Test name
Test status
Simulation time 55282618 ps
CPU time 1.46 seconds
Started Jul 13 04:48:07 PM PDT 24
Finished Jul 13 04:48:09 PM PDT 24
Peak memory 217732 kb
Host smart-939db496-ac31-4738-9713-c3e41404c0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467210227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1467210227
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.4009377031
Short name T607
Test name
Test status
Simulation time 326420639 ps
CPU time 11.4 seconds
Started Jul 13 04:48:08 PM PDT 24
Finished Jul 13 04:48:22 PM PDT 24
Peak memory 217836 kb
Host smart-fcb6e2e6-bee2-46de-96ba-5a1f20c8ae1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009377031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.4009377031
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3341593396
Short name T442
Test name
Test status
Simulation time 698409303 ps
CPU time 12.41 seconds
Started Jul 13 04:48:08 PM PDT 24
Finished Jul 13 04:48:23 PM PDT 24
Peak memory 225440 kb
Host smart-71f8df83-15c5-46af-82d9-4be3a399b760
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341593396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3341593396
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2149365503
Short name T181
Test name
Test status
Simulation time 1063295683 ps
CPU time 10.88 seconds
Started Jul 13 04:48:08 PM PDT 24
Finished Jul 13 04:48:20 PM PDT 24
Peak memory 224132 kb
Host smart-50fa9528-fca9-4cce-af83-8992bc10cbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149365503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2149365503
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3696540999
Short name T626
Test name
Test status
Simulation time 50836064 ps
CPU time 1.34 seconds
Started Jul 13 04:48:06 PM PDT 24
Finished Jul 13 04:48:07 PM PDT 24
Peak memory 213244 kb
Host smart-028f7fc7-5c5b-4958-9c7c-ff20682b2c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696540999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3696540999
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3976794777
Short name T220
Test name
Test status
Simulation time 810157840 ps
CPU time 32.74 seconds
Started Jul 13 04:48:10 PM PDT 24
Finished Jul 13 04:48:45 PM PDT 24
Peak memory 250392 kb
Host smart-00f26e92-c1d1-48d8-b6ae-20f3e24167a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976794777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3976794777
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1626765278
Short name T305
Test name
Test status
Simulation time 293452882 ps
CPU time 7.02 seconds
Started Jul 13 04:48:10 PM PDT 24
Finished Jul 13 04:48:19 PM PDT 24
Peak memory 246812 kb
Host smart-db9eca8f-a493-4c72-a6f0-1c0f58d30537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626765278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1626765278
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3040501732
Short name T344
Test name
Test status
Simulation time 46019512584 ps
CPU time 102.61 seconds
Started Jul 13 04:48:07 PM PDT 24
Finished Jul 13 04:49:50 PM PDT 24
Peak memory 280272 kb
Host smart-40ac6551-f497-4682-b76d-b99aca57a6fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040501732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3040501732
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.3376930452
Short name T137
Test name
Test status
Simulation time 31157316882 ps
CPU time 271.28 seconds
Started Jul 13 04:48:09 PM PDT 24
Finished Jul 13 04:52:42 PM PDT 24
Peak memory 275860 kb
Host smart-94a03ffa-952c-4492-9e3d-c28bf0f27627
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3376930452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.3376930452
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.801172842
Short name T695
Test name
Test status
Simulation time 44721866 ps
CPU time 0.8 seconds
Started Jul 13 04:48:08 PM PDT 24
Finished Jul 13 04:48:10 PM PDT 24
Peak memory 208132 kb
Host smart-a8e74e25-a01c-4843-b608-369b43958e6f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801172842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.801172842
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2824628239
Short name T512
Test name
Test status
Simulation time 77609863 ps
CPU time 1.06 seconds
Started Jul 13 04:48:06 PM PDT 24
Finished Jul 13 04:48:08 PM PDT 24
Peak memory 208516 kb
Host smart-9f8f424b-4e1e-42f8-a79d-34ed0dde4ec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824628239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2824628239
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1320250143
Short name T243
Test name
Test status
Simulation time 1200749914 ps
CPU time 15.05 seconds
Started Jul 13 04:48:10 PM PDT 24
Finished Jul 13 04:48:27 PM PDT 24
Peak memory 225460 kb
Host smart-153e5697-629e-46bf-8916-a29e3bb66fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320250143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1320250143
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.4111840409
Short name T332
Test name
Test status
Simulation time 319299936 ps
CPU time 3.81 seconds
Started Jul 13 04:48:08 PM PDT 24
Finished Jul 13 04:48:14 PM PDT 24
Peak memory 217076 kb
Host smart-0143ba1b-48c1-4f7d-8456-a452839455a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111840409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.4111840409
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.4213475293
Short name T653
Test name
Test status
Simulation time 283846809 ps
CPU time 2.94 seconds
Started Jul 13 04:48:07 PM PDT 24
Finished Jul 13 04:48:10 PM PDT 24
Peak memory 217708 kb
Host smart-d360274b-051b-4cc0-9973-fcb3515fdd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213475293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.4213475293
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3895718835
Short name T198
Test name
Test status
Simulation time 501460070 ps
CPU time 11.97 seconds
Started Jul 13 04:48:07 PM PDT 24
Finished Jul 13 04:48:19 PM PDT 24
Peak memory 225520 kb
Host smart-624234aa-f560-4e21-ab3b-d5ab0c672eb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895718835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3895718835
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.4241514647
Short name T235
Test name
Test status
Simulation time 375041247 ps
CPU time 9.52 seconds
Started Jul 13 04:48:10 PM PDT 24
Finished Jul 13 04:48:21 PM PDT 24
Peak memory 224236 kb
Host smart-c953a568-17f1-49ac-948a-54344bd64bc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241514647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.4241514647
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1010046170
Short name T244
Test name
Test status
Simulation time 1610724360 ps
CPU time 10.03 seconds
Started Jul 13 04:48:10 PM PDT 24
Finished Jul 13 04:48:22 PM PDT 24
Peak memory 217532 kb
Host smart-4b57f521-e4ee-4906-bc54-cabe78187bcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010046170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1010046170
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2785309141
Short name T526
Test name
Test status
Simulation time 185223976 ps
CPU time 8.5 seconds
Started Jul 13 04:48:07 PM PDT 24
Finished Jul 13 04:48:16 PM PDT 24
Peak memory 225496 kb
Host smart-47be87b9-5dff-4810-864d-17904c6b73df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785309141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2785309141
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1775050695
Short name T640
Test name
Test status
Simulation time 100923709 ps
CPU time 3.14 seconds
Started Jul 13 04:48:08 PM PDT 24
Finished Jul 13 04:48:12 PM PDT 24
Peak memory 214088 kb
Host smart-ebc79632-65fb-4af0-84d2-707171466d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775050695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1775050695
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.191060391
Short name T146
Test name
Test status
Simulation time 4747369616 ps
CPU time 31.43 seconds
Started Jul 13 04:48:10 PM PDT 24
Finished Jul 13 04:48:43 PM PDT 24
Peak memory 250544 kb
Host smart-e0151cc3-27dd-4834-be54-8a0fecc3ad2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191060391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.191060391
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3252466422
Short name T712
Test name
Test status
Simulation time 49086099 ps
CPU time 6.21 seconds
Started Jul 13 04:48:08 PM PDT 24
Finished Jul 13 04:48:16 PM PDT 24
Peak memory 249952 kb
Host smart-fa3809f0-cbe4-4589-90ab-21e291fe97af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252466422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3252466422
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2757715732
Short name T400
Test name
Test status
Simulation time 763418677 ps
CPU time 28.16 seconds
Started Jul 13 04:48:11 PM PDT 24
Finished Jul 13 04:48:40 PM PDT 24
Peak memory 220288 kb
Host smart-445eb277-d1ee-4412-94e6-20f527b313a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757715732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2757715732
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.2752761114
Short name T414
Test name
Test status
Simulation time 27728214905 ps
CPU time 1056.69 seconds
Started Jul 13 04:48:09 PM PDT 24
Finished Jul 13 05:05:47 PM PDT 24
Peak memory 528016 kb
Host smart-556315e8-1ec0-4514-a11f-4266ab696105
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2752761114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.2752761114
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.737080508
Short name T67
Test name
Test status
Simulation time 13168511 ps
CPU time 0.92 seconds
Started Jul 13 04:48:10 PM PDT 24
Finished Jul 13 04:48:12 PM PDT 24
Peak memory 211220 kb
Host smart-83f415be-421d-43f6-9258-3a8cccd18afe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737080508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.737080508
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3773970187
Short name T531
Test name
Test status
Simulation time 64788020 ps
CPU time 0.91 seconds
Started Jul 13 04:48:17 PM PDT 24
Finished Jul 13 04:48:20 PM PDT 24
Peak memory 208472 kb
Host smart-c773b3a3-c287-4000-8f0f-ce73ffe5daf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773970187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3773970187
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1340085346
Short name T508
Test name
Test status
Simulation time 930619204 ps
CPU time 15.84 seconds
Started Jul 13 04:48:16 PM PDT 24
Finished Jul 13 04:48:35 PM PDT 24
Peak memory 225452 kb
Host smart-5237dc3e-97e0-4d48-b8ad-fc894134cd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340085346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1340085346
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.142565075
Short name T673
Test name
Test status
Simulation time 225358004 ps
CPU time 5.83 seconds
Started Jul 13 04:48:18 PM PDT 24
Finished Jul 13 04:48:27 PM PDT 24
Peak memory 217128 kb
Host smart-164c6d74-620b-41a3-9936-be4e3f34353a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142565075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.142565075
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1619104456
Short name T700
Test name
Test status
Simulation time 73939391 ps
CPU time 3.06 seconds
Started Jul 13 04:48:18 PM PDT 24
Finished Jul 13 04:48:24 PM PDT 24
Peak memory 221816 kb
Host smart-63550306-c8eb-417e-a496-8eb1980c1cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619104456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1619104456
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1826136808
Short name T868
Test name
Test status
Simulation time 393432327 ps
CPU time 17.89 seconds
Started Jul 13 04:48:17 PM PDT 24
Finished Jul 13 04:48:38 PM PDT 24
Peak memory 225452 kb
Host smart-9588cdeb-8960-4ba2-999b-c00468ccd480
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826136808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1826136808
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1338172220
Short name T628
Test name
Test status
Simulation time 1908924312 ps
CPU time 13.54 seconds
Started Jul 13 04:48:16 PM PDT 24
Finished Jul 13 04:48:33 PM PDT 24
Peak memory 225412 kb
Host smart-104f713f-9ab8-44a1-a1ae-ca3037691e72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338172220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1338172220
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.249384215
Short name T837
Test name
Test status
Simulation time 1082515014 ps
CPU time 6.88 seconds
Started Jul 13 04:48:20 PM PDT 24
Finished Jul 13 04:48:29 PM PDT 24
Peak memory 224940 kb
Host smart-bbb97d02-221e-43b5-9d1f-11b6ddb8de65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249384215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.249384215
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3341053915
Short name T276
Test name
Test status
Simulation time 1502932764 ps
CPU time 14.89 seconds
Started Jul 13 04:48:21 PM PDT 24
Finished Jul 13 04:48:38 PM PDT 24
Peak memory 225444 kb
Host smart-71fb81f7-1f9b-4be2-8d81-cfd81ef0fe00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341053915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3341053915
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3900327413
Short name T202
Test name
Test status
Simulation time 227187293 ps
CPU time 2.29 seconds
Started Jul 13 04:48:11 PM PDT 24
Finished Jul 13 04:48:15 PM PDT 24
Peak memory 213784 kb
Host smart-42e5a467-5fc6-45d4-b9c5-c144ec570626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900327413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3900327413
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2060732276
Short name T246
Test name
Test status
Simulation time 984890355 ps
CPU time 26.87 seconds
Started Jul 13 04:48:09 PM PDT 24
Finished Jul 13 04:48:38 PM PDT 24
Peak memory 250408 kb
Host smart-c30df69b-f1e8-4593-8464-d030b3682ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060732276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2060732276
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.28672310
Short name T827
Test name
Test status
Simulation time 140929424 ps
CPU time 3.48 seconds
Started Jul 13 04:48:09 PM PDT 24
Finished Jul 13 04:48:14 PM PDT 24
Peak memory 225836 kb
Host smart-05aa2fa8-2b20-4046-b748-8497aeb3de05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28672310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.28672310
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.4275505297
Short name T466
Test name
Test status
Simulation time 2847907308 ps
CPU time 80.13 seconds
Started Jul 13 04:48:18 PM PDT 24
Finished Jul 13 04:49:41 PM PDT 24
Peak memory 250476 kb
Host smart-057ca49e-cd48-4785-9c77-baad35eb27ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275505297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.4275505297
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.1221397625
Short name T133
Test name
Test status
Simulation time 54977064320 ps
CPU time 367.67 seconds
Started Jul 13 04:48:16 PM PDT 24
Finished Jul 13 04:54:26 PM PDT 24
Peak memory 299420 kb
Host smart-311ef879-16c3-4a53-8a8b-b223ca0edc17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1221397625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.1221397625
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2957518264
Short name T676
Test name
Test status
Simulation time 13740327 ps
CPU time 1.02 seconds
Started Jul 13 04:48:07 PM PDT 24
Finished Jul 13 04:48:10 PM PDT 24
Peak memory 208400 kb
Host smart-7ee6a3e1-cacd-48d6-8a36-4d2d3b7f81a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957518264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2957518264
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.4199052635
Short name T764
Test name
Test status
Simulation time 19646263 ps
CPU time 1.18 seconds
Started Jul 13 04:48:14 PM PDT 24
Finished Jul 13 04:48:16 PM PDT 24
Peak memory 208496 kb
Host smart-d526b523-e20a-484d-b057-07129f5f6aaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199052635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.4199052635
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.422338023
Short name T440
Test name
Test status
Simulation time 338014966 ps
CPU time 16.19 seconds
Started Jul 13 04:48:17 PM PDT 24
Finished Jul 13 04:48:37 PM PDT 24
Peak memory 217712 kb
Host smart-fb1d3cbc-68c2-45c7-8d97-e79407b6c0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422338023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.422338023
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2999743426
Short name T597
Test name
Test status
Simulation time 1203990432 ps
CPU time 22.92 seconds
Started Jul 13 04:48:15 PM PDT 24
Finished Jul 13 04:48:40 PM PDT 24
Peak memory 217100 kb
Host smart-cb764a9c-cca1-4d66-8ff6-513416c3d067
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999743426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2999743426
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.3966196186
Short name T389
Test name
Test status
Simulation time 112057803 ps
CPU time 2.76 seconds
Started Jul 13 04:48:16 PM PDT 24
Finished Jul 13 04:48:20 PM PDT 24
Peak memory 217720 kb
Host smart-483efbdf-2461-45fd-8acb-d0f4ebe78ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966196186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3966196186
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1356848465
Short name T609
Test name
Test status
Simulation time 2957843027 ps
CPU time 19.45 seconds
Started Jul 13 04:48:16 PM PDT 24
Finished Jul 13 04:48:39 PM PDT 24
Peak memory 225500 kb
Host smart-862c6720-712d-4c45-9984-8b19dc5591f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356848465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1356848465
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1222477157
Short name T416
Test name
Test status
Simulation time 2907297079 ps
CPU time 10.43 seconds
Started Jul 13 04:48:14 PM PDT 24
Finished Jul 13 04:48:26 PM PDT 24
Peak memory 217680 kb
Host smart-fa398042-112c-4ad2-878b-d51e9b372c81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222477157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1222477157
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1450479207
Short name T849
Test name
Test status
Simulation time 398440389 ps
CPU time 9.27 seconds
Started Jul 13 04:48:16 PM PDT 24
Finished Jul 13 04:48:27 PM PDT 24
Peak memory 225452 kb
Host smart-18168e07-13d7-4161-8bb8-7c963c52de19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450479207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1450479207
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3148386278
Short name T296
Test name
Test status
Simulation time 30225344 ps
CPU time 2.57 seconds
Started Jul 13 04:48:17 PM PDT 24
Finished Jul 13 04:48:22 PM PDT 24
Peak memory 213632 kb
Host smart-c034d531-47fc-49c3-b740-d7bd5e1c3b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148386278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3148386278
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.235374075
Short name T552
Test name
Test status
Simulation time 190677879 ps
CPU time 24.15 seconds
Started Jul 13 04:48:14 PM PDT 24
Finished Jul 13 04:48:39 PM PDT 24
Peak memory 250512 kb
Host smart-1e99b8c8-d481-4df3-9c28-1b837c1c9f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235374075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.235374075
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1420358963
Short name T302
Test name
Test status
Simulation time 609134851 ps
CPU time 9.86 seconds
Started Jul 13 04:48:15 PM PDT 24
Finished Jul 13 04:48:26 PM PDT 24
Peak memory 250452 kb
Host smart-9783150c-ab00-4968-b043-29f1833b72f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420358963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1420358963
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2058189748
Short name T353
Test name
Test status
Simulation time 5573591117 ps
CPU time 55.32 seconds
Started Jul 13 04:48:16 PM PDT 24
Finished Jul 13 04:49:14 PM PDT 24
Peak memory 247128 kb
Host smart-4e9ee6cf-bf78-4057-a8c9-4d1ec0eee0d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058189748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2058189748
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.267595557
Short name T130
Test name
Test status
Simulation time 38745170175 ps
CPU time 344.54 seconds
Started Jul 13 04:48:22 PM PDT 24
Finished Jul 13 04:54:09 PM PDT 24
Peak memory 283304 kb
Host smart-537ac42e-4a84-47bf-b600-28b40bf09ee0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=267595557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.267595557
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3815394066
Short name T280
Test name
Test status
Simulation time 27436290 ps
CPU time 0.99 seconds
Started Jul 13 04:48:16 PM PDT 24
Finished Jul 13 04:48:20 PM PDT 24
Peak memory 208420 kb
Host smart-5e4a4a61-9397-4098-95f3-ef1e3822c2ea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815394066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3815394066
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3965195536
Short name T252
Test name
Test status
Simulation time 38037924 ps
CPU time 1.17 seconds
Started Jul 13 04:48:16 PM PDT 24
Finished Jul 13 04:48:20 PM PDT 24
Peak memory 208476 kb
Host smart-1bc3c4cc-0932-496f-b81a-d1dad849de0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965195536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3965195536
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.247920286
Short name T650
Test name
Test status
Simulation time 445883433 ps
CPU time 12.95 seconds
Started Jul 13 04:48:17 PM PDT 24
Finished Jul 13 04:48:33 PM PDT 24
Peak memory 217660 kb
Host smart-d96fd726-055f-482b-8fa1-e595ae79c95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247920286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.247920286
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.734032948
Short name T153
Test name
Test status
Simulation time 292113844 ps
CPU time 4.15 seconds
Started Jul 13 04:48:17 PM PDT 24
Finished Jul 13 04:48:25 PM PDT 24
Peak memory 217244 kb
Host smart-a9f5b9a0-2201-4796-9a50-5e43fbcbb155
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734032948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.734032948
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1026210262
Short name T720
Test name
Test status
Simulation time 220229144 ps
CPU time 2.96 seconds
Started Jul 13 04:48:18 PM PDT 24
Finished Jul 13 04:48:24 PM PDT 24
Peak memory 217544 kb
Host smart-d6601f90-0502-4dd1-937f-4970310175b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026210262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1026210262
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3769131187
Short name T294
Test name
Test status
Simulation time 823130885 ps
CPU time 9.53 seconds
Started Jul 13 04:48:16 PM PDT 24
Finished Jul 13 04:48:29 PM PDT 24
Peak memory 217688 kb
Host smart-8468e636-e14b-457a-9c71-70dc10f6aed1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769131187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3769131187
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.4259798162
Short name T631
Test name
Test status
Simulation time 1350316009 ps
CPU time 11.42 seconds
Started Jul 13 04:48:16 PM PDT 24
Finished Jul 13 04:48:29 PM PDT 24
Peak memory 225444 kb
Host smart-472682d9-c4ba-49a4-bd34-fa9763fbc9f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259798162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.4259798162
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2315870756
Short name T780
Test name
Test status
Simulation time 768889924 ps
CPU time 8.19 seconds
Started Jul 13 04:48:21 PM PDT 24
Finished Jul 13 04:48:32 PM PDT 24
Peak memory 217608 kb
Host smart-1198984b-6562-4dcc-923d-da1551b8f1e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315870756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2315870756
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3505690991
Short name T460
Test name
Test status
Simulation time 757408418 ps
CPU time 6.74 seconds
Started Jul 13 04:48:15 PM PDT 24
Finished Jul 13 04:48:22 PM PDT 24
Peak memory 224008 kb
Host smart-7a0327b4-319d-4583-8c4f-b4763b9f3ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505690991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3505690991
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3209345511
Short name T308
Test name
Test status
Simulation time 152068729 ps
CPU time 2.85 seconds
Started Jul 13 04:48:15 PM PDT 24
Finished Jul 13 04:48:19 PM PDT 24
Peak memory 214420 kb
Host smart-f3b3f355-7f19-4989-a922-0019fc814234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209345511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3209345511
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3916949539
Short name T555
Test name
Test status
Simulation time 341095929 ps
CPU time 34.11 seconds
Started Jul 13 04:48:19 PM PDT 24
Finished Jul 13 04:48:56 PM PDT 24
Peak memory 250384 kb
Host smart-33b574b8-eb00-4e0d-ac08-5b9d734702e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916949539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3916949539
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1731385222
Short name T222
Test name
Test status
Simulation time 401229914 ps
CPU time 7.08 seconds
Started Jul 13 04:48:22 PM PDT 24
Finished Jul 13 04:48:31 PM PDT 24
Peak memory 249876 kb
Host smart-a6e8b594-2fd4-4b31-a809-c235968e7a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731385222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1731385222
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3864768082
Short name T643
Test name
Test status
Simulation time 20238652363 ps
CPU time 427.33 seconds
Started Jul 13 04:48:16 PM PDT 24
Finished Jul 13 04:55:25 PM PDT 24
Peak memory 250536 kb
Host smart-be448dab-23ee-430c-b41b-36cc7a089a1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864768082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3864768082
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.520481896
Short name T135
Test name
Test status
Simulation time 304493354615 ps
CPU time 1943.44 seconds
Started Jul 13 04:48:15 PM PDT 24
Finished Jul 13 05:20:40 PM PDT 24
Peak memory 643872 kb
Host smart-998ce3a0-ffdc-4641-9c5d-0b2d07e16da0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=520481896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.520481896
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3659408112
Short name T784
Test name
Test status
Simulation time 91847798 ps
CPU time 1.11 seconds
Started Jul 13 04:48:16 PM PDT 24
Finished Jul 13 04:48:20 PM PDT 24
Peak memory 217168 kb
Host smart-3dd9e288-2862-475d-9c24-2226195496dd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659408112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3659408112
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.218885181
Short name T469
Test name
Test status
Simulation time 56959892 ps
CPU time 1.05 seconds
Started Jul 13 04:48:14 PM PDT 24
Finished Jul 13 04:48:16 PM PDT 24
Peak memory 208440 kb
Host smart-6240c88f-2ea0-48aa-b2c9-d1e7cdf5f01b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218885181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.218885181
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1861233928
Short name T855
Test name
Test status
Simulation time 1000650981 ps
CPU time 14.32 seconds
Started Jul 13 04:48:17 PM PDT 24
Finished Jul 13 04:48:35 PM PDT 24
Peak memory 217672 kb
Host smart-158e75ec-92c8-4403-8825-ae9635cd717f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861233928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1861233928
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1993582223
Short name T498
Test name
Test status
Simulation time 610159079 ps
CPU time 3.3 seconds
Started Jul 13 04:48:21 PM PDT 24
Finished Jul 13 04:48:27 PM PDT 24
Peak memory 217064 kb
Host smart-4b72e5ea-6b53-48e0-8873-fd57bf21b053
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993582223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1993582223
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1575462304
Short name T394
Test name
Test status
Simulation time 58976101 ps
CPU time 3.11 seconds
Started Jul 13 04:48:16 PM PDT 24
Finished Jul 13 04:48:22 PM PDT 24
Peak memory 217660 kb
Host smart-ded298b0-c707-42f9-b1a8-5f7b7a991520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575462304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1575462304
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2987014197
Short name T257
Test name
Test status
Simulation time 1652753378 ps
CPU time 18.34 seconds
Started Jul 13 04:48:19 PM PDT 24
Finished Jul 13 04:48:40 PM PDT 24
Peak memory 225472 kb
Host smart-2a6c5de6-8bb3-4ab4-b8d8-097780d9223c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987014197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2987014197
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2280061992
Short name T253
Test name
Test status
Simulation time 4425613552 ps
CPU time 14.71 seconds
Started Jul 13 04:48:22 PM PDT 24
Finished Jul 13 04:48:39 PM PDT 24
Peak memory 225484 kb
Host smart-b5966a3c-485d-43d6-8980-570da137b34f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280061992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2280061992
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.3856497480
Short name T511
Test name
Test status
Simulation time 856046968 ps
CPU time 11.96 seconds
Started Jul 13 04:48:16 PM PDT 24
Finished Jul 13 04:48:31 PM PDT 24
Peak memory 225444 kb
Host smart-1b80c31a-ccb2-4175-bf4f-8f9d399a270c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856497480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
3856497480
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.933996447
Short name T561
Test name
Test status
Simulation time 227022082 ps
CPU time 6.65 seconds
Started Jul 13 04:48:16 PM PDT 24
Finished Jul 13 04:48:25 PM PDT 24
Peak memory 223964 kb
Host smart-fcc232b3-4260-4612-ba34-efd78384be8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933996447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.933996447
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.102562039
Short name T457
Test name
Test status
Simulation time 52028704 ps
CPU time 1.12 seconds
Started Jul 13 04:48:15 PM PDT 24
Finished Jul 13 04:48:17 PM PDT 24
Peak memory 211720 kb
Host smart-7e0a2b18-40e1-4738-b3be-1c6980b027c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102562039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.102562039
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.2173221697
Short name T255
Test name
Test status
Simulation time 2350803673 ps
CPU time 20.57 seconds
Started Jul 13 04:48:19 PM PDT 24
Finished Jul 13 04:48:43 PM PDT 24
Peak memory 250492 kb
Host smart-13a98aef-85d0-4199-ad26-a44303684141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173221697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2173221697
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1780709975
Short name T390
Test name
Test status
Simulation time 55040781 ps
CPU time 2.94 seconds
Started Jul 13 04:48:17 PM PDT 24
Finished Jul 13 04:48:22 PM PDT 24
Peak memory 225824 kb
Host smart-6b6edb12-76ca-4355-8867-cb72f939bb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780709975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1780709975
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3646622041
Short name T147
Test name
Test status
Simulation time 12276678002 ps
CPU time 231.92 seconds
Started Jul 13 04:48:17 PM PDT 24
Finished Jul 13 04:52:12 PM PDT 24
Peak memory 275868 kb
Host smart-53a2d90b-888e-475d-99fe-1f869340bad1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646622041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3646622041
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.4104451320
Short name T31
Test name
Test status
Simulation time 124069687249 ps
CPU time 591.38 seconds
Started Jul 13 04:48:18 PM PDT 24
Finished Jul 13 04:58:12 PM PDT 24
Peak memory 283228 kb
Host smart-a9568140-e32f-4c98-aa84-201ffa8fa435
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4104451320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.4104451320
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.4087096038
Short name T377
Test name
Test status
Simulation time 43011916 ps
CPU time 0.85 seconds
Started Jul 13 04:48:14 PM PDT 24
Finished Jul 13 04:48:16 PM PDT 24
Peak memory 208456 kb
Host smart-9c087a07-9798-4ad1-add5-3a562afa3a35
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087096038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.4087096038
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1784755352
Short name T72
Test name
Test status
Simulation time 17326067 ps
CPU time 0.92 seconds
Started Jul 13 04:46:10 PM PDT 24
Finished Jul 13 04:46:11 PM PDT 24
Peak memory 208408 kb
Host smart-b9cdbf4d-b052-4182-b57d-e21cd3664212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784755352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1784755352
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1965551694
Short name T467
Test name
Test status
Simulation time 877853703 ps
CPU time 11.14 seconds
Started Jul 13 04:46:10 PM PDT 24
Finished Jul 13 04:46:22 PM PDT 24
Peak memory 217736 kb
Host smart-6db3987a-11bd-4a2f-a347-45b575f1a6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965551694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1965551694
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.775847713
Short name T428
Test name
Test status
Simulation time 349518506 ps
CPU time 9.73 seconds
Started Jul 13 04:46:12 PM PDT 24
Finished Jul 13 04:46:23 PM PDT 24
Peak memory 217056 kb
Host smart-1bfcb5c3-0335-403a-b061-dec0976209fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775847713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.775847713
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.319108207
Short name T448
Test name
Test status
Simulation time 18689117512 ps
CPU time 37.1 seconds
Started Jul 13 04:46:12 PM PDT 24
Finished Jul 13 04:46:50 PM PDT 24
Peak memory 219000 kb
Host smart-e1e2aa61-6a8f-4b9a-b9d1-719c8921645c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319108207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.319108207
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2462225013
Short name T634
Test name
Test status
Simulation time 227982141 ps
CPU time 3.53 seconds
Started Jul 13 04:46:10 PM PDT 24
Finished Jul 13 04:46:14 PM PDT 24
Peak memory 217104 kb
Host smart-1b1712cc-c739-429c-9c02-2bbe1db97b0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462225013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
462225013
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2713988390
Short name T806
Test name
Test status
Simulation time 397624255 ps
CPU time 7.39 seconds
Started Jul 13 04:46:11 PM PDT 24
Finished Jul 13 04:46:19 PM PDT 24
Peak memory 217628 kb
Host smart-82c356b9-66d8-4699-a80a-91a1348d417e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713988390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2713988390
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.222733770
Short name T75
Test name
Test status
Simulation time 875776899 ps
CPU time 27.05 seconds
Started Jul 13 04:46:12 PM PDT 24
Finished Jul 13 04:46:40 PM PDT 24
Peak memory 217000 kb
Host smart-098c9229-edd5-47f7-9139-b316fd134173
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222733770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.222733770
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1934271663
Short name T649
Test name
Test status
Simulation time 367985815 ps
CPU time 6.48 seconds
Started Jul 13 04:46:10 PM PDT 24
Finished Jul 13 04:46:17 PM PDT 24
Peak memory 217000 kb
Host smart-f94806d3-d64c-45bb-a796-1000b8b439c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934271663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1934271663
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2448243881
Short name T630
Test name
Test status
Simulation time 2946717365 ps
CPU time 43.62 seconds
Started Jul 13 04:46:12 PM PDT 24
Finished Jul 13 04:46:56 PM PDT 24
Peak memory 266856 kb
Host smart-23f4e3b1-ce3c-429d-992f-5d7a63778abb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448243881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2448243881
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1563747844
Short name T231
Test name
Test status
Simulation time 1390843343 ps
CPU time 10.27 seconds
Started Jul 13 04:46:12 PM PDT 24
Finished Jul 13 04:46:23 PM PDT 24
Peak memory 246832 kb
Host smart-a8b5117e-7b2a-401b-b738-2e59e6864547
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563747844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.1563747844
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3457213428
Short name T739
Test name
Test status
Simulation time 55675622 ps
CPU time 3.12 seconds
Started Jul 13 04:46:12 PM PDT 24
Finished Jul 13 04:46:16 PM PDT 24
Peak memory 221812 kb
Host smart-c52fb936-60f3-481b-b85d-c13f2ef398f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457213428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3457213428
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2618800660
Short name T83
Test name
Test status
Simulation time 1762599238 ps
CPU time 10.04 seconds
Started Jul 13 04:46:10 PM PDT 24
Finished Jul 13 04:46:21 PM PDT 24
Peak memory 214212 kb
Host smart-2b480f77-34b9-4418-ac80-3769b2eedf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618800660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2618800660
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2695712119
Short name T446
Test name
Test status
Simulation time 206312421 ps
CPU time 7.72 seconds
Started Jul 13 04:46:10 PM PDT 24
Finished Jul 13 04:46:18 PM PDT 24
Peak memory 225444 kb
Host smart-7ce68fdc-1809-41fc-8e66-a4e92ff849f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695712119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2695712119
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.237553607
Short name T248
Test name
Test status
Simulation time 2296261340 ps
CPU time 9.23 seconds
Started Jul 13 04:46:10 PM PDT 24
Finished Jul 13 04:46:20 PM PDT 24
Peak memory 217660 kb
Host smart-5e2fa525-0389-48b2-a84a-3c2ea9dfe05a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237553607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.237553607
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1891710313
Short name T727
Test name
Test status
Simulation time 278357868 ps
CPU time 11.63 seconds
Started Jul 13 04:46:11 PM PDT 24
Finished Jul 13 04:46:24 PM PDT 24
Peak memory 225444 kb
Host smart-e13a63e4-b953-476f-ad16-cec73a8f5749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891710313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1891710313
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2820837926
Short name T546
Test name
Test status
Simulation time 182267005 ps
CPU time 2.71 seconds
Started Jul 13 04:46:11 PM PDT 24
Finished Jul 13 04:46:14 PM PDT 24
Peak memory 223084 kb
Host smart-1739086c-0a1b-45da-965a-2bf35fd18e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820837926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2820837926
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.353817296
Short name T707
Test name
Test status
Simulation time 194906489 ps
CPU time 28.74 seconds
Started Jul 13 04:46:11 PM PDT 24
Finished Jul 13 04:46:41 PM PDT 24
Peak memory 250448 kb
Host smart-a9afbddf-7bbd-4936-86fc-97dbc78ec872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353817296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.353817296
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3308133821
Short name T504
Test name
Test status
Simulation time 79821607 ps
CPU time 7.66 seconds
Started Jul 13 04:46:08 PM PDT 24
Finished Jul 13 04:46:16 PM PDT 24
Peak memory 250492 kb
Host smart-e1432c15-f4bb-469b-bb68-76b8eaec5eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308133821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3308133821
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.3273359080
Short name T136
Test name
Test status
Simulation time 16407029957 ps
CPU time 549.38 seconds
Started Jul 13 04:46:10 PM PDT 24
Finished Jul 13 04:55:20 PM PDT 24
Peak memory 299800 kb
Host smart-a53e05d8-dc3f-4fd7-916b-6156a030a667
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3273359080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.3273359080
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1270523672
Short name T812
Test name
Test status
Simulation time 46218352 ps
CPU time 0.86 seconds
Started Jul 13 04:46:11 PM PDT 24
Finished Jul 13 04:46:12 PM PDT 24
Peak memory 208256 kb
Host smart-28a628c7-dca8-4c8b-a26c-a788ed9294d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270523672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1270523672
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.4275958192
Short name T665
Test name
Test status
Simulation time 14712840 ps
CPU time 1.05 seconds
Started Jul 13 04:46:20 PM PDT 24
Finished Jul 13 04:46:22 PM PDT 24
Peak memory 208408 kb
Host smart-2f4b854f-f3e9-48c5-b6dc-b949b919c8a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275958192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.4275958192
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.570102225
Short name T456
Test name
Test status
Simulation time 1636752990 ps
CPU time 17.6 seconds
Started Jul 13 04:46:21 PM PDT 24
Finished Jul 13 04:46:40 PM PDT 24
Peak memory 225464 kb
Host smart-916f9637-0fb2-4e14-b77c-0268f254b282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570102225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.570102225
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1258546920
Short name T338
Test name
Test status
Simulation time 401605022 ps
CPU time 3.11 seconds
Started Jul 13 04:46:19 PM PDT 24
Finished Jul 13 04:46:23 PM PDT 24
Peak memory 216440 kb
Host smart-2f5261ea-1e2e-4e57-8b9b-0dea99341b13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258546920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1258546920
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.809511075
Short name T689
Test name
Test status
Simulation time 5331994899 ps
CPU time 33.26 seconds
Started Jul 13 04:46:22 PM PDT 24
Finished Jul 13 04:46:57 PM PDT 24
Peak memory 218100 kb
Host smart-fa6bca15-e606-42e4-acd1-53cced1ea493
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809511075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.809511075
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.237673995
Short name T424
Test name
Test status
Simulation time 158141706 ps
CPU time 2.02 seconds
Started Jul 13 04:46:20 PM PDT 24
Finished Jul 13 04:46:23 PM PDT 24
Peak memory 217104 kb
Host smart-741816b9-4587-41b2-80d3-37d3253aad3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237673995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.237673995
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1920214842
Short name T269
Test name
Test status
Simulation time 1750916373 ps
CPU time 6.25 seconds
Started Jul 13 04:46:19 PM PDT 24
Finished Jul 13 04:46:27 PM PDT 24
Peak memory 217532 kb
Host smart-5f569c2c-4e39-4993-8a43-a91e236abbef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920214842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1920214842
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1077234588
Short name T395
Test name
Test status
Simulation time 5094732197 ps
CPU time 19.75 seconds
Started Jul 13 04:46:21 PM PDT 24
Finished Jul 13 04:46:42 PM PDT 24
Peak memory 217080 kb
Host smart-2e7e15b0-845e-4ba4-b972-1fdb4ab053af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077234588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1077234588
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1369271141
Short name T669
Test name
Test status
Simulation time 507684679 ps
CPU time 2.51 seconds
Started Jul 13 04:46:23 PM PDT 24
Finished Jul 13 04:46:27 PM PDT 24
Peak memory 217056 kb
Host smart-fb310565-8829-4244-842a-ee6ca600c197
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369271141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1369271141
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.750237228
Short name T342
Test name
Test status
Simulation time 23260407586 ps
CPU time 67.41 seconds
Started Jul 13 04:46:19 PM PDT 24
Finished Jul 13 04:47:27 PM PDT 24
Peak memory 276256 kb
Host smart-bce4e1f4-b10c-45b7-89e7-057585e43afd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750237228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.750237228
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3044420407
Short name T803
Test name
Test status
Simulation time 436388523 ps
CPU time 14.3 seconds
Started Jul 13 04:46:20 PM PDT 24
Finished Jul 13 04:46:36 PM PDT 24
Peak memory 250376 kb
Host smart-ea7f5387-15f1-4025-8a8b-a0cb3b94a801
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044420407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3044420407
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.368729234
Short name T345
Test name
Test status
Simulation time 24343920 ps
CPU time 1.5 seconds
Started Jul 13 04:46:21 PM PDT 24
Finished Jul 13 04:46:24 PM PDT 24
Peak memory 217708 kb
Host smart-3363fd17-caec-406b-a02e-375ad5f436c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368729234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.368729234
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2737459055
Short name T63
Test name
Test status
Simulation time 499797252 ps
CPU time 29.08 seconds
Started Jul 13 04:46:20 PM PDT 24
Finished Jul 13 04:46:50 PM PDT 24
Peak memory 217048 kb
Host smart-6bf405f1-6569-43cf-a44b-263a138c43ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737459055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2737459055
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3714509688
Short name T777
Test name
Test status
Simulation time 305892166 ps
CPU time 11.62 seconds
Started Jul 13 04:46:21 PM PDT 24
Finished Jul 13 04:46:35 PM PDT 24
Peak memory 218360 kb
Host smart-03fe498e-e00f-47cd-85bc-8e8a4a443cb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714509688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3714509688
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1655952854
Short name T833
Test name
Test status
Simulation time 885348659 ps
CPU time 16.52 seconds
Started Jul 13 04:46:20 PM PDT 24
Finished Jul 13 04:46:38 PM PDT 24
Peak memory 225388 kb
Host smart-26109aa4-e071-4b4c-90a2-474c0f25b6b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655952854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1655952854
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1670843203
Short name T361
Test name
Test status
Simulation time 251587208 ps
CPU time 10.17 seconds
Started Jul 13 04:46:18 PM PDT 24
Finished Jul 13 04:46:29 PM PDT 24
Peak memory 217664 kb
Host smart-0bd40734-95b5-4906-8bdf-48383f0b8933
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670843203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
670843203
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.4081909138
Short name T577
Test name
Test status
Simulation time 1484707076 ps
CPU time 8.87 seconds
Started Jul 13 04:46:18 PM PDT 24
Finished Jul 13 04:46:28 PM PDT 24
Peak memory 225464 kb
Host smart-3540b6bf-f93e-4377-8eb3-b7577796ffac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081909138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.4081909138
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1738516294
Short name T678
Test name
Test status
Simulation time 18148804 ps
CPU time 1.26 seconds
Started Jul 13 04:46:11 PM PDT 24
Finished Jul 13 04:46:13 PM PDT 24
Peak memory 217136 kb
Host smart-607fc213-d306-45dd-b5ee-97883af02eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738516294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1738516294
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3667128572
Short name T324
Test name
Test status
Simulation time 155039068 ps
CPU time 19.09 seconds
Started Jul 13 04:46:20 PM PDT 24
Finished Jul 13 04:46:41 PM PDT 24
Peak memory 250456 kb
Host smart-172cd8fd-e6d0-4a7e-a5a4-f6e0b4baaf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667128572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3667128572
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3647425202
Short name T189
Test name
Test status
Simulation time 101676003 ps
CPU time 9.08 seconds
Started Jul 13 04:46:22 PM PDT 24
Finished Jul 13 04:46:33 PM PDT 24
Peak memory 250440 kb
Host smart-f5f4d2cf-5d33-4aa8-a7e2-6502526c3095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647425202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3647425202
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2684335556
Short name T759
Test name
Test status
Simulation time 1605118625 ps
CPU time 75.42 seconds
Started Jul 13 04:46:20 PM PDT 24
Finished Jul 13 04:47:37 PM PDT 24
Peak memory 250400 kb
Host smart-961e59c7-a2cc-410e-965d-244e5fdff395
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684335556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2684335556
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2196903279
Short name T38
Test name
Test status
Simulation time 23189355 ps
CPU time 1.07 seconds
Started Jul 13 04:46:14 PM PDT 24
Finished Jul 13 04:46:15 PM PDT 24
Peak memory 212248 kb
Host smart-a559f1f7-9ee8-437e-9185-6bff47fd9d26
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196903279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2196903279
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.79176496
Short name T516
Test name
Test status
Simulation time 21883849 ps
CPU time 1.17 seconds
Started Jul 13 04:46:21 PM PDT 24
Finished Jul 13 04:46:24 PM PDT 24
Peak memory 208528 kb
Host smart-38fb46da-4e2a-4c8b-a85e-a4de648690f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79176496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.79176496
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1989821066
Short name T176
Test name
Test status
Simulation time 14152966 ps
CPU time 0.86 seconds
Started Jul 13 04:46:19 PM PDT 24
Finished Jul 13 04:46:21 PM PDT 24
Peak memory 208452 kb
Host smart-64a708f5-2297-4876-b033-d68aca25d00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989821066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1989821066
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1266899656
Short name T206
Test name
Test status
Simulation time 243769543 ps
CPU time 11.29 seconds
Started Jul 13 04:46:19 PM PDT 24
Finished Jul 13 04:46:31 PM PDT 24
Peak memory 225456 kb
Host smart-b487191a-9c21-4ad7-90db-415f8cebfeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266899656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1266899656
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2727578412
Short name T23
Test name
Test status
Simulation time 1592115379 ps
CPU time 9.33 seconds
Started Jul 13 04:46:23 PM PDT 24
Finished Jul 13 04:46:34 PM PDT 24
Peak memory 217120 kb
Host smart-d087c63c-23e3-482d-96b1-690e0a7b4e69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727578412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2727578412
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3617718380
Short name T725
Test name
Test status
Simulation time 1278392847 ps
CPU time 22.21 seconds
Started Jul 13 04:46:19 PM PDT 24
Finished Jul 13 04:46:42 PM PDT 24
Peak memory 217680 kb
Host smart-29a21f3f-1e8a-4fc6-a355-a35535323804
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617718380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3617718380
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1873707333
Short name T562
Test name
Test status
Simulation time 252076846 ps
CPU time 2.31 seconds
Started Jul 13 04:46:24 PM PDT 24
Finished Jul 13 04:46:27 PM PDT 24
Peak memory 217084 kb
Host smart-a70d17f0-4205-4008-8b9f-e99233098ce7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873707333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
873707333
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2661659250
Short name T721
Test name
Test status
Simulation time 286469011 ps
CPU time 9.15 seconds
Started Jul 13 04:46:23 PM PDT 24
Finished Jul 13 04:46:33 PM PDT 24
Peak memory 217664 kb
Host smart-9366f62d-fb8f-44ce-8849-f33286e3f41a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661659250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2661659250
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.4147458810
Short name T191
Test name
Test status
Simulation time 4622579059 ps
CPU time 20.35 seconds
Started Jul 13 04:46:20 PM PDT 24
Finished Jul 13 04:46:42 PM PDT 24
Peak memory 217184 kb
Host smart-deb3dba6-2152-4b04-84b1-e0f5594c2c72
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147458810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.4147458810
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2304715966
Short name T288
Test name
Test status
Simulation time 182479135 ps
CPU time 5.59 seconds
Started Jul 13 04:46:19 PM PDT 24
Finished Jul 13 04:46:25 PM PDT 24
Peak memory 216912 kb
Host smart-cef489d7-d675-458a-a013-e4d1130f1b8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304715966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2304715966
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.679209813
Short name T245
Test name
Test status
Simulation time 1093260440 ps
CPU time 29.34 seconds
Started Jul 13 04:46:23 PM PDT 24
Finished Jul 13 04:46:53 PM PDT 24
Peak memory 251140 kb
Host smart-05e1cd58-176f-47db-a939-74e0c6f07786
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679209813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.679209813
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1430411758
Short name T846
Test name
Test status
Simulation time 2279044141 ps
CPU time 13.29 seconds
Started Jul 13 04:46:19 PM PDT 24
Finished Jul 13 04:46:34 PM PDT 24
Peak memory 250408 kb
Host smart-e2c0476d-b675-48fd-bf30-c8e478c1ac9e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430411758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.1430411758
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3419004564
Short name T370
Test name
Test status
Simulation time 527067575 ps
CPU time 3.06 seconds
Started Jul 13 04:46:20 PM PDT 24
Finished Jul 13 04:46:24 PM PDT 24
Peak memory 217780 kb
Host smart-6f529e07-d687-47d1-9323-a8a7b9d055cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419004564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3419004564
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.4028166523
Short name T261
Test name
Test status
Simulation time 735593704 ps
CPU time 20.9 seconds
Started Jul 13 04:46:23 PM PDT 24
Finished Jul 13 04:46:45 PM PDT 24
Peak memory 217140 kb
Host smart-49df6b86-9f9f-4d2e-8d2d-3522790f1eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028166523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.4028166523
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2822726177
Short name T373
Test name
Test status
Simulation time 879955047 ps
CPU time 12.82 seconds
Started Jul 13 04:46:22 PM PDT 24
Finished Jul 13 04:46:36 PM PDT 24
Peak memory 218356 kb
Host smart-c8848f86-5645-4edb-9581-48779b55f070
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822726177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2822726177
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.994472820
Short name T615
Test name
Test status
Simulation time 2352430720 ps
CPU time 14.07 seconds
Started Jul 13 04:46:20 PM PDT 24
Finished Jul 13 04:46:35 PM PDT 24
Peak memory 225456 kb
Host smart-8ae8c811-5a6c-4251-898c-eeb084fe3818
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994472820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.994472820
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3953922212
Short name T813
Test name
Test status
Simulation time 1657161504 ps
CPU time 14.44 seconds
Started Jul 13 04:46:21 PM PDT 24
Finished Jul 13 04:46:37 PM PDT 24
Peak memory 217596 kb
Host smart-17d48aac-6420-4d6f-8058-f493856f6c73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953922212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
953922212
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.673481449
Short name T637
Test name
Test status
Simulation time 274044511 ps
CPU time 12.39 seconds
Started Jul 13 04:46:18 PM PDT 24
Finished Jul 13 04:46:31 PM PDT 24
Peak memory 217856 kb
Host smart-350bc8c1-d8f5-421b-9684-5efc733b6cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673481449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.673481449
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.808122935
Short name T655
Test name
Test status
Simulation time 63517275 ps
CPU time 3.15 seconds
Started Jul 13 04:46:22 PM PDT 24
Finished Jul 13 04:46:27 PM PDT 24
Peak memory 217204 kb
Host smart-68c0362f-4ee7-42c4-8bc0-545f2ce83b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808122935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.808122935
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1563097374
Short name T625
Test name
Test status
Simulation time 1219276047 ps
CPU time 30.32 seconds
Started Jul 13 04:46:20 PM PDT 24
Finished Jul 13 04:46:52 PM PDT 24
Peak memory 250260 kb
Host smart-5f04bbd7-5fff-4585-9e9c-6f9cfbc13597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563097374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1563097374
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1312757394
Short name T196
Test name
Test status
Simulation time 240675673 ps
CPU time 8 seconds
Started Jul 13 04:46:19 PM PDT 24
Finished Jul 13 04:46:28 PM PDT 24
Peak memory 250468 kb
Host smart-93638d54-8e20-45b4-8a91-63cd78c4b6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312757394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1312757394
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.229754368
Short name T358
Test name
Test status
Simulation time 2690386667 ps
CPU time 82.84 seconds
Started Jul 13 04:46:21 PM PDT 24
Finished Jul 13 04:47:45 PM PDT 24
Peak memory 266908 kb
Host smart-64ed07e7-1578-4791-ba3e-c3ad8c642aba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229754368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.229754368
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.3139612635
Short name T711
Test name
Test status
Simulation time 4146016947 ps
CPU time 155.97 seconds
Started Jul 13 04:46:19 PM PDT 24
Finished Jul 13 04:48:57 PM PDT 24
Peak memory 275544 kb
Host smart-a0107bcd-18e3-40d0-9f17-fe967be19086
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3139612635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.3139612635
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1721597522
Short name T495
Test name
Test status
Simulation time 30643611 ps
CPU time 0.93 seconds
Started Jul 13 04:46:19 PM PDT 24
Finished Jul 13 04:46:21 PM PDT 24
Peak memory 211148 kb
Host smart-f795df85-2edf-4aee-ad83-7e0ce4d58a06
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721597522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1721597522
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.50035912
Short name T375
Test name
Test status
Simulation time 15593885 ps
CPU time 1.11 seconds
Started Jul 13 04:46:30 PM PDT 24
Finished Jul 13 04:46:32 PM PDT 24
Peak memory 208536 kb
Host smart-465ce6a2-84ca-430d-b13d-481ebe41eedf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50035912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.50035912
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1970711626
Short name T179
Test name
Test status
Simulation time 11977934 ps
CPU time 1 seconds
Started Jul 13 04:46:31 PM PDT 24
Finished Jul 13 04:46:33 PM PDT 24
Peak memory 208596 kb
Host smart-31c0e8b2-50e3-4f90-bf0f-4f25ed808375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970711626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1970711626
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1626673093
Short name T674
Test name
Test status
Simulation time 547684245 ps
CPU time 16.34 seconds
Started Jul 13 04:46:21 PM PDT 24
Finished Jul 13 04:46:39 PM PDT 24
Peak memory 217616 kb
Host smart-a4ae8183-c7f4-4e38-b252-cb03646a99b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626673093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1626673093
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1598671200
Short name T690
Test name
Test status
Simulation time 438460508 ps
CPU time 4.64 seconds
Started Jul 13 04:46:30 PM PDT 24
Finished Jul 13 04:46:36 PM PDT 24
Peak memory 217068 kb
Host smart-c6b9eb44-43ee-422d-ac62-9a406ecf8beb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598671200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1598671200
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1577206444
Short name T671
Test name
Test status
Simulation time 12195974976 ps
CPU time 39.84 seconds
Started Jul 13 04:46:30 PM PDT 24
Finished Jul 13 04:47:10 PM PDT 24
Peak memory 218044 kb
Host smart-42044c1a-1c50-4da2-b272-8892f369a237
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577206444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1577206444
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.956286836
Short name T540
Test name
Test status
Simulation time 1756647250 ps
CPU time 10.06 seconds
Started Jul 13 04:46:36 PM PDT 24
Finished Jul 13 04:46:47 PM PDT 24
Peak memory 216996 kb
Host smart-e372ff4c-bcdb-4230-9bd0-f96169e2091d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956286836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.956286836
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3649668185
Short name T348
Test name
Test status
Simulation time 1056004485 ps
CPU time 15.59 seconds
Started Jul 13 04:46:31 PM PDT 24
Finished Jul 13 04:46:48 PM PDT 24
Peak memory 217508 kb
Host smart-661966f8-6829-433f-a580-4424b46d098e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649668185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3649668185
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.816395998
Short name T80
Test name
Test status
Simulation time 4567349191 ps
CPU time 34.17 seconds
Started Jul 13 04:46:34 PM PDT 24
Finished Jul 13 04:47:09 PM PDT 24
Peak memory 217336 kb
Host smart-84112319-babd-437e-802c-9be092f25891
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816395998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.816395998
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.947060966
Short name T459
Test name
Test status
Simulation time 2280929519 ps
CPU time 8.82 seconds
Started Jul 13 04:46:34 PM PDT 24
Finished Jul 13 04:46:44 PM PDT 24
Peak memory 217120 kb
Host smart-29f2269e-8819-460e-a31f-a884f26591f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947060966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.947060966
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1089239139
Short name T323
Test name
Test status
Simulation time 1363473813 ps
CPU time 54.61 seconds
Started Jul 13 04:46:31 PM PDT 24
Finished Jul 13 04:47:28 PM PDT 24
Peak memory 252224 kb
Host smart-176a5c20-38f6-4c0b-961e-ecc8f94bd0ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089239139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1089239139
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.478349431
Short name T488
Test name
Test status
Simulation time 271525909 ps
CPU time 12.97 seconds
Started Jul 13 04:46:31 PM PDT 24
Finished Jul 13 04:46:46 PM PDT 24
Peak memory 249828 kb
Host smart-dd0a67c1-0423-4448-9f4f-d2f8f9774a29
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478349431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.478349431
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2330210787
Short name T205
Test name
Test status
Simulation time 326983395 ps
CPU time 4.05 seconds
Started Jul 13 04:46:22 PM PDT 24
Finished Jul 13 04:46:28 PM PDT 24
Peak memory 221372 kb
Host smart-66a0bdad-bf61-4b6d-a94f-6616a0dbe5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330210787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2330210787
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.4249018639
Short name T785
Test name
Test status
Simulation time 382386956 ps
CPU time 12.63 seconds
Started Jul 13 04:46:22 PM PDT 24
Finished Jul 13 04:46:36 PM PDT 24
Peak memory 217128 kb
Host smart-db72f2e9-7500-499a-b5fc-d25f5aa834d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249018639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.4249018639
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.1883950104
Short name T530
Test name
Test status
Simulation time 1624020043 ps
CPU time 13.34 seconds
Started Jul 13 04:46:32 PM PDT 24
Finished Jul 13 04:46:47 PM PDT 24
Peak memory 218428 kb
Host smart-f29d57dc-9e58-42eb-89b5-0bbbf176b1b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883950104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1883950104
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3871838689
Short name T268
Test name
Test status
Simulation time 1017135801 ps
CPU time 12.74 seconds
Started Jul 13 04:46:32 PM PDT 24
Finished Jul 13 04:46:46 PM PDT 24
Peak memory 225396 kb
Host smart-145bb92e-e48d-49f4-82ce-b6187cc7b9a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871838689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3871838689
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.806536455
Short name T527
Test name
Test status
Simulation time 957196382 ps
CPU time 11.55 seconds
Started Jul 13 04:46:30 PM PDT 24
Finished Jul 13 04:46:42 PM PDT 24
Peak memory 217616 kb
Host smart-b2096960-a064-4768-9095-750054a36878
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806536455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.806536455
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.887986886
Short name T468
Test name
Test status
Simulation time 2534858670 ps
CPU time 9.32 seconds
Started Jul 13 04:46:23 PM PDT 24
Finished Jul 13 04:46:33 PM PDT 24
Peak memory 225484 kb
Host smart-f75e8580-f1fa-4871-b6c7-896b85c1b3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887986886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.887986886
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.595087959
Short name T696
Test name
Test status
Simulation time 48985989 ps
CPU time 2.08 seconds
Started Jul 13 04:46:20 PM PDT 24
Finished Jul 13 04:46:24 PM PDT 24
Peak memory 213536 kb
Host smart-06857dbc-d392-431d-9352-8170354a2fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595087959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.595087959
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2792989962
Short name T854
Test name
Test status
Simulation time 1556868840 ps
CPU time 17.23 seconds
Started Jul 13 04:46:20 PM PDT 24
Finished Jul 13 04:46:39 PM PDT 24
Peak memory 250496 kb
Host smart-b957aa4e-9256-4410-8e95-129cea572acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792989962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2792989962
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.1251447679
Short name T262
Test name
Test status
Simulation time 245569049 ps
CPU time 6.48 seconds
Started Jul 13 04:46:21 PM PDT 24
Finished Jul 13 04:46:29 PM PDT 24
Peak memory 250028 kb
Host smart-0cdc68c9-c9dc-4fb8-9422-5dad8a3bb7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251447679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1251447679
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1897441458
Short name T804
Test name
Test status
Simulation time 22991601558 ps
CPU time 131.09 seconds
Started Jul 13 04:46:35 PM PDT 24
Finished Jul 13 04:48:48 PM PDT 24
Peak memory 404248 kb
Host smart-0df48cba-9619-4d33-b2fc-665e49d1aac4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897441458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1897441458
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.1480784679
Short name T95
Test name
Test status
Simulation time 66411361130 ps
CPU time 353.27 seconds
Started Jul 13 04:46:33 PM PDT 24
Finished Jul 13 04:52:28 PM PDT 24
Peak memory 332568 kb
Host smart-add9c52d-f252-4879-ba8f-7dc561f5ec52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1480784679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.1480784679
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1903891651
Short name T267
Test name
Test status
Simulation time 12059170 ps
CPU time 0.97 seconds
Started Jul 13 04:46:22 PM PDT 24
Finished Jul 13 04:46:25 PM PDT 24
Peak memory 208060 kb
Host smart-c53b9490-91ab-4c22-975c-1658aa752d3c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903891651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1903891651
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2158596129
Short name T656
Test name
Test status
Simulation time 16986645 ps
CPU time 1.08 seconds
Started Jul 13 04:46:30 PM PDT 24
Finished Jul 13 04:46:32 PM PDT 24
Peak memory 208472 kb
Host smart-21f2b056-6b07-4c29-a111-b24d7406a787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158596129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2158596129
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3597405858
Short name T184
Test name
Test status
Simulation time 34566367 ps
CPU time 0.9 seconds
Started Jul 13 04:46:32 PM PDT 24
Finished Jul 13 04:46:35 PM PDT 24
Peak memory 208232 kb
Host smart-6d01d563-56ae-46b8-aa29-e23e0d14bf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597405858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3597405858
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.122504170
Short name T383
Test name
Test status
Simulation time 549555742 ps
CPU time 9.94 seconds
Started Jul 13 04:46:31 PM PDT 24
Finished Jul 13 04:46:42 PM PDT 24
Peak memory 225460 kb
Host smart-73740dae-1f74-4097-869c-9cfb2d8b99ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122504170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.122504170
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.1338887539
Short name T359
Test name
Test status
Simulation time 1057297497 ps
CPU time 2.35 seconds
Started Jul 13 04:46:33 PM PDT 24
Finished Jul 13 04:46:37 PM PDT 24
Peak memory 217196 kb
Host smart-caa7b471-b281-4394-bc90-b41abc348341
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338887539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1338887539
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1585415141
Short name T709
Test name
Test status
Simulation time 4686174662 ps
CPU time 43.8 seconds
Started Jul 13 04:46:36 PM PDT 24
Finished Jul 13 04:47:21 PM PDT 24
Peak memory 218308 kb
Host smart-38e8ffb3-5cba-42ce-96b4-97fd38e2223a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585415141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1585415141
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3435928532
Short name T694
Test name
Test status
Simulation time 310053796 ps
CPU time 2.61 seconds
Started Jul 13 04:46:30 PM PDT 24
Finished Jul 13 04:46:33 PM PDT 24
Peak memory 217168 kb
Host smart-66e79dd7-a3cb-4e7f-b412-5e072b078bd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435928532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
435928532
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2202339148
Short name T14
Test name
Test status
Simulation time 601421425 ps
CPU time 10.16 seconds
Started Jul 13 04:46:34 PM PDT 24
Finished Jul 13 04:46:46 PM PDT 24
Peak memory 223520 kb
Host smart-ebe50ee4-571f-48df-ba01-ad1cc5f01cf9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202339148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2202339148
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3031919953
Short name T697
Test name
Test status
Simulation time 7248374391 ps
CPU time 12.9 seconds
Started Jul 13 04:46:31 PM PDT 24
Finished Jul 13 04:46:46 PM PDT 24
Peak memory 217132 kb
Host smart-c643ff8a-b522-411e-af57-409f716ac045
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031919953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3031919953
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.991988529
Short name T193
Test name
Test status
Simulation time 722987596 ps
CPU time 17.8 seconds
Started Jul 13 04:46:32 PM PDT 24
Finished Jul 13 04:46:52 PM PDT 24
Peak memory 217008 kb
Host smart-fa8be2bc-0c6f-4b2f-909b-3b638c0eca8a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991988529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.991988529
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2813394974
Short name T792
Test name
Test status
Simulation time 1166739549 ps
CPU time 55.94 seconds
Started Jul 13 04:46:37 PM PDT 24
Finished Jul 13 04:47:34 PM PDT 24
Peak memory 266644 kb
Host smart-44a5ca8b-9561-43c9-b9f3-72cf92ebac08
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813394974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2813394974
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3669987523
Short name T769
Test name
Test status
Simulation time 249732633 ps
CPU time 12.09 seconds
Started Jul 13 04:46:32 PM PDT 24
Finished Jul 13 04:46:46 PM PDT 24
Peak memory 250232 kb
Host smart-b5f2a652-447e-4b9c-9883-b96cc9dff878
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669987523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3669987523
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1269492863
Short name T641
Test name
Test status
Simulation time 146842881 ps
CPU time 2.12 seconds
Started Jul 13 04:46:36 PM PDT 24
Finished Jul 13 04:46:39 PM PDT 24
Peak memory 217656 kb
Host smart-ae502725-3efb-4aa2-ad25-2d190f31b1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269492863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1269492863
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2234434061
Short name T79
Test name
Test status
Simulation time 635423627 ps
CPU time 18.29 seconds
Started Jul 13 04:46:31 PM PDT 24
Finished Jul 13 04:46:51 PM PDT 24
Peak memory 214176 kb
Host smart-5bc6dae2-7e85-4d66-8b32-6b3bd05a17f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234434061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2234434061
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.3939685954
Short name T213
Test name
Test status
Simulation time 287599325 ps
CPU time 12.13 seconds
Started Jul 13 04:46:29 PM PDT 24
Finished Jul 13 04:46:42 PM PDT 24
Peak memory 217724 kb
Host smart-61d182c4-92b9-4794-be84-8056f92551ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939685954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3939685954
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2531061752
Short name T195
Test name
Test status
Simulation time 1121832799 ps
CPU time 10.81 seconds
Started Jul 13 04:46:35 PM PDT 24
Finished Jul 13 04:46:47 PM PDT 24
Peak memory 225724 kb
Host smart-06cb0e59-e592-4fbf-914c-76a259c4a8fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531061752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2531061752
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1362143989
Short name T509
Test name
Test status
Simulation time 282757755 ps
CPU time 10.36 seconds
Started Jul 13 04:46:34 PM PDT 24
Finished Jul 13 04:46:46 PM PDT 24
Peak memory 224736 kb
Host smart-9dd17bb2-1b04-43cc-8d3d-53b73b2f56e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362143989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
362143989
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3243379592
Short name T238
Test name
Test status
Simulation time 3664366984 ps
CPU time 8.26 seconds
Started Jul 13 04:46:31 PM PDT 24
Finished Jul 13 04:46:41 PM PDT 24
Peak memory 224760 kb
Host smart-0037c9d1-a062-432c-8eb3-07182468fee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243379592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3243379592
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.310091968
Short name T851
Test name
Test status
Simulation time 42835486 ps
CPU time 1.51 seconds
Started Jul 13 04:46:31 PM PDT 24
Finished Jul 13 04:46:33 PM PDT 24
Peak memory 213120 kb
Host smart-ad2c4ebf-a35c-4ec9-9327-7304e760e91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310091968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.310091968
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1176271069
Short name T745
Test name
Test status
Simulation time 836748402 ps
CPU time 25.52 seconds
Started Jul 13 04:46:29 PM PDT 24
Finished Jul 13 04:46:55 PM PDT 24
Peak memory 250480 kb
Host smart-1cc64116-6c8e-4963-b219-bead4ee7297a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176271069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1176271069
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1312493817
Short name T658
Test name
Test status
Simulation time 116227929 ps
CPU time 6.21 seconds
Started Jul 13 04:46:33 PM PDT 24
Finished Jul 13 04:46:41 PM PDT 24
Peak memory 246200 kb
Host smart-0e6275c2-48bf-4cae-9d36-1920f0a3e748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312493817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1312493817
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1710272725
Short name T306
Test name
Test status
Simulation time 1534664890 ps
CPU time 50.65 seconds
Started Jul 13 04:46:33 PM PDT 24
Finished Jul 13 04:47:25 PM PDT 24
Peak memory 250444 kb
Host smart-f0eed621-7a16-45d4-b60e-06f8660f912a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710272725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1710272725
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.1882200965
Short name T132
Test name
Test status
Simulation time 14750601291 ps
CPU time 287.49 seconds
Started Jul 13 04:46:31 PM PDT 24
Finished Jul 13 04:51:20 PM PDT 24
Peak memory 332548 kb
Host smart-26a32905-922d-4702-a55d-c3493307ef4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1882200965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.1882200965
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1328321241
Short name T528
Test name
Test status
Simulation time 15436112 ps
CPU time 0.99 seconds
Started Jul 13 04:46:32 PM PDT 24
Finished Jul 13 04:46:35 PM PDT 24
Peak memory 211304 kb
Host smart-cc8012bd-8c9d-48d4-a4bb-f51ce416bac0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328321241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1328321241
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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