Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47817 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
1728 |
1 |
|
|
T8 |
11 |
|
T14 |
13 |
|
T29 |
8 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49044 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
501 |
1 |
|
|
T40 |
19 |
|
T58 |
13 |
|
T59 |
10 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47813 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
10 |
auto[1] |
1732 |
1 |
|
|
T4 |
2 |
|
T13 |
8 |
|
T15 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47849 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
1696 |
1 |
|
|
T13 |
10 |
|
T15 |
2 |
|
T17 |
15 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47856 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
1689 |
1 |
|
|
T13 |
9 |
|
T15 |
2 |
|
T17 |
12 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
45198 |
1 |
|
|
T2 |
15 |
|
T4 |
3 |
|
T8 |
90 |
no_err_inj |
4347 |
1 |
|
|
T1 |
16 |
|
T4 |
9 |
|
T15 |
18 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47818 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
1727 |
1 |
|
|
T8 |
10 |
|
T14 |
12 |
|
T29 |
13 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48979 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
566 |
1 |
|
|
T40 |
28 |
|
T58 |
12 |
|
T59 |
14 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
34469 |
1 |
|
|
T1 |
16 |
|
T8 |
90 |
|
T9 |
62 |
auto[1] |
15076 |
1 |
|
|
T2 |
15 |
|
T4 |
12 |
|
T14 |
80 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47871 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
1674 |
1 |
|
|
T13 |
7 |
|
T15 |
1 |
|
T17 |
7 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47848 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
1697 |
1 |
|
|
T13 |
10 |
|
T15 |
2 |
|
T17 |
13 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47923 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
1622 |
1 |
|
|
T13 |
11 |
|
T15 |
1 |
|
T17 |
6 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47799 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
1746 |
1 |
|
|
T8 |
8 |
|
T14 |
7 |
|
T29 |
15 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47334 |
1 |
|
|
T1 |
16 |
|
T4 |
12 |
|
T8 |
90 |
auto[1] |
2211 |
1 |
|
|
T2 |
15 |
|
T10 |
14 |
|
T12 |
12 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49015 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
530 |
1 |
|
|
T40 |
13 |
|
T58 |
12 |
|
T59 |
12 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48993 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
552 |
1 |
|
|
T40 |
18 |
|
T58 |
19 |
|
T59 |
10 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49006 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
539 |
1 |
|
|
T40 |
18 |
|
T58 |
9 |
|
T59 |
13 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47140 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T8 |
90 |
auto[1] |
2405 |
1 |
|
|
T4 |
12 |
|
T15 |
25 |
|
T18 |
15 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
45751 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
3794 |
1 |
|
|
T9 |
62 |
|
T46 |
77 |
|
T47 |
86 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47846 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
11 |
auto[1] |
1699 |
1 |
|
|
T4 |
1 |
|
T13 |
7 |
|
T15 |
1 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47786 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
1759 |
1 |
|
|
T13 |
6 |
|
T17 |
6 |
|
T18 |
18 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47875 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
1670 |
1 |
|
|
T13 |
10 |
|
T15 |
2 |
|
T17 |
13 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47778 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
1767 |
1 |
|
|
T8 |
13 |
|
T14 |
9 |
|
T29 |
12 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
44108 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
5437 |
1 |
|
|
T8 |
9 |
|
T14 |
12 |
|
T29 |
7 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
45863 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
3682 |
1 |
|
|
T11 |
87 |
|
T31 |
89 |
|
T30 |
86 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49545 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47823 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
1722 |
1 |
|
|
T8 |
11 |
|
T14 |
11 |
|
T29 |
13 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47798 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
1747 |
1 |
|
|
T8 |
11 |
|
T14 |
5 |
|
T29 |
21 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47834 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T4 |
12 |
auto[1] |
1711 |
1 |
|
|
T8 |
17 |
|
T14 |
11 |
|
T29 |
14 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
43969 |
1 |
|
|
T2 |
15 |
|
T8 |
90 |
|
T9 |
62 |
auto[0] |
no_err_inj |
3171 |
1 |
|
|
T1 |
16 |
|
T15 |
5 |
|
T34 |
16 |
auto[1] |
err_inj |
1229 |
1 |
|
|
T4 |
3 |
|
T15 |
12 |
|
T18 |
9 |
auto[1] |
no_err_inj |
1176 |
1 |
|
|
T4 |
9 |
|
T15 |
13 |
|
T18 |
6 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45517 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T8 |
90 |
auto[0] |
auto[1] |
1623 |
1 |
|
|
T13 |
6 |
|
T17 |
6 |
|
T18 |
18 |
auto[1] |
auto[0] |
2269 |
1 |
|
|
T4 |
12 |
|
T15 |
25 |
|
T18 |
15 |
auto[1] |
auto[1] |
136 |
1 |
|
|
T42 |
3 |
|
T81 |
1 |
|
T212 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45599 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T8 |
90 |
auto[0] |
auto[1] |
1541 |
1 |
|
|
T13 |
10 |
|
T17 |
13 |
|
T18 |
21 |
auto[1] |
auto[0] |
2249 |
1 |
|
|
T4 |
12 |
|
T15 |
23 |
|
T18 |
14 |
auto[1] |
auto[1] |
156 |
1 |
|
|
T15 |
2 |
|
T18 |
1 |
|
T42 |
4 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45598 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T8 |
90 |
auto[0] |
auto[1] |
1542 |
1 |
|
|
T13 |
10 |
|
T17 |
13 |
|
T18 |
20 |
auto[1] |
auto[0] |
2277 |
1 |
|
|
T4 |
12 |
|
T15 |
23 |
|
T18 |
14 |
auto[1] |
auto[1] |
128 |
1 |
|
|
T15 |
2 |
|
T18 |
1 |
|
T42 |
4 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45564 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T8 |
90 |
auto[0] |
auto[1] |
1576 |
1 |
|
|
T13 |
10 |
|
T17 |
15 |
|
T18 |
13 |
auto[1] |
auto[0] |
2285 |
1 |
|
|
T4 |
12 |
|
T15 |
23 |
|
T18 |
15 |
auto[1] |
auto[1] |
120 |
1 |
|
|
T15 |
2 |
|
T42 |
1 |
|
T81 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45599 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T8 |
90 |
auto[0] |
auto[1] |
1541 |
1 |
|
|
T13 |
9 |
|
T17 |
12 |
|
T18 |
18 |
auto[1] |
auto[0] |
2257 |
1 |
|
|
T4 |
12 |
|
T15 |
23 |
|
T18 |
15 |
auto[1] |
auto[1] |
148 |
1 |
|
|
T15 |
2 |
|
T42 |
3 |
|
T61 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45535 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T8 |
90 |
auto[0] |
auto[1] |
1605 |
1 |
|
|
T13 |
8 |
|
T17 |
10 |
|
T18 |
14 |
auto[1] |
auto[0] |
2278 |
1 |
|
|
T4 |
10 |
|
T15 |
24 |
|
T18 |
14 |
auto[1] |
auto[1] |
127 |
1 |
|
|
T4 |
2 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33538 |
1 |
|
|
T1 |
16 |
|
T8 |
79 |
|
T9 |
62 |
auto[0] |
auto[1] |
931 |
1 |
|
|
T8 |
11 |
|
T29 |
8 |
|
T33 |
11 |
auto[1] |
auto[0] |
14279 |
1 |
|
|
T2 |
15 |
|
T4 |
12 |
|
T14 |
67 |
auto[1] |
auto[1] |
797 |
1 |
|
|
T14 |
13 |
|
T15 |
12 |
|
T18 |
17 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33518 |
1 |
|
|
T1 |
16 |
|
T8 |
80 |
|
T9 |
62 |
auto[0] |
auto[1] |
951 |
1 |
|
|
T8 |
10 |
|
T29 |
13 |
|
T33 |
9 |
auto[1] |
auto[0] |
14300 |
1 |
|
|
T2 |
15 |
|
T4 |
12 |
|
T14 |
68 |
auto[1] |
auto[1] |
776 |
1 |
|
|
T14 |
12 |
|
T15 |
10 |
|
T18 |
20 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33154 |
1 |
|
|
T1 |
16 |
|
T8 |
90 |
|
T9 |
62 |
auto[0] |
auto[1] |
1315 |
1 |
|
|
T10 |
14 |
|
T12 |
12 |
|
T29 |
11 |
auto[1] |
auto[0] |
14180 |
1 |
|
|
T4 |
12 |
|
T14 |
80 |
|
T15 |
101 |
auto[1] |
auto[1] |
896 |
1 |
|
|
T2 |
15 |
|
T15 |
19 |
|
T16 |
16 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33499 |
1 |
|
|
T1 |
16 |
|
T8 |
82 |
|
T9 |
62 |
auto[0] |
auto[1] |
970 |
1 |
|
|
T8 |
8 |
|
T29 |
15 |
|
T33 |
12 |
auto[1] |
auto[0] |
14300 |
1 |
|
|
T2 |
15 |
|
T4 |
12 |
|
T14 |
73 |
auto[1] |
auto[1] |
776 |
1 |
|
|
T14 |
7 |
|
T15 |
14 |
|
T18 |
6 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29852 |
1 |
|
|
T1 |
16 |
|
T8 |
81 |
|
T9 |
62 |
auto[0] |
auto[1] |
4617 |
1 |
|
|
T8 |
9 |
|
T29 |
7 |
|
T32 |
63 |
auto[1] |
auto[0] |
14256 |
1 |
|
|
T2 |
15 |
|
T4 |
12 |
|
T14 |
68 |
auto[1] |
auto[1] |
820 |
1 |
|
|
T14 |
12 |
|
T15 |
16 |
|
T18 |
22 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33379 |
1 |
|
|
T1 |
16 |
|
T8 |
90 |
|
T9 |
62 |
auto[0] |
auto[1] |
1090 |
1 |
|
|
T13 |
6 |
|
T18 |
11 |
|
T42 |
42 |
auto[1] |
auto[0] |
14407 |
1 |
|
|
T2 |
15 |
|
T4 |
12 |
|
T14 |
80 |
auto[1] |
auto[1] |
669 |
1 |
|
|
T17 |
6 |
|
T18 |
7 |
|
T42 |
20 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33434 |
1 |
|
|
T1 |
16 |
|
T8 |
90 |
|
T9 |
62 |
auto[0] |
auto[1] |
1035 |
1 |
|
|
T13 |
7 |
|
T18 |
16 |
|
T42 |
54 |
auto[1] |
auto[0] |
14412 |
1 |
|
|
T2 |
15 |
|
T4 |
11 |
|
T14 |
80 |
auto[1] |
auto[1] |
664 |
1 |
|
|
T4 |
1 |
|
T15 |
1 |
|
T17 |
9 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33468 |
1 |
|
|
T1 |
16 |
|
T8 |
90 |
|
T9 |
62 |
auto[0] |
auto[1] |
1001 |
1 |
|
|
T13 |
10 |
|
T15 |
2 |
|
T18 |
12 |
auto[1] |
auto[0] |
14380 |
1 |
|
|
T2 |
15 |
|
T4 |
12 |
|
T14 |
80 |
auto[1] |
auto[1] |
696 |
1 |
|
|
T17 |
13 |
|
T18 |
10 |
|
T42 |
18 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33465 |
1 |
|
|
T1 |
16 |
|
T8 |
90 |
|
T9 |
62 |
auto[0] |
auto[1] |
1004 |
1 |
|
|
T13 |
7 |
|
T15 |
1 |
|
T18 |
12 |
auto[1] |
auto[0] |
14406 |
1 |
|
|
T2 |
15 |
|
T4 |
12 |
|
T14 |
80 |
auto[1] |
auto[1] |
670 |
1 |
|
|
T17 |
7 |
|
T18 |
4 |
|
T42 |
18 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33454 |
1 |
|
|
T1 |
16 |
|
T8 |
90 |
|
T9 |
62 |
auto[0] |
auto[1] |
1015 |
1 |
|
|
T13 |
10 |
|
T15 |
2 |
|
T18 |
5 |
auto[1] |
auto[0] |
14395 |
1 |
|
|
T2 |
15 |
|
T4 |
12 |
|
T14 |
80 |
auto[1] |
auto[1] |
681 |
1 |
|
|
T17 |
15 |
|
T18 |
8 |
|
T42 |
19 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33427 |
1 |
|
|
T1 |
16 |
|
T8 |
90 |
|
T9 |
62 |
auto[0] |
auto[1] |
1042 |
1 |
|
|
T13 |
8 |
|
T15 |
1 |
|
T18 |
6 |
auto[1] |
auto[0] |
14386 |
1 |
|
|
T2 |
15 |
|
T4 |
10 |
|
T14 |
80 |
auto[1] |
auto[1] |
690 |
1 |
|
|
T4 |
2 |
|
T17 |
10 |
|
T18 |
9 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33553 |
1 |
|
|
T1 |
16 |
|
T8 |
73 |
|
T9 |
62 |
auto[0] |
auto[1] |
916 |
1 |
|
|
T8 |
17 |
|
T29 |
14 |
|
T33 |
12 |
auto[1] |
auto[0] |
14281 |
1 |
|
|
T2 |
15 |
|
T4 |
12 |
|
T14 |
69 |
auto[1] |
auto[1] |
795 |
1 |
|
|
T14 |
11 |
|
T15 |
12 |
|
T18 |
14 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33487 |
1 |
|
|
T1 |
16 |
|
T8 |
79 |
|
T9 |
62 |
auto[0] |
auto[1] |
982 |
1 |
|
|
T8 |
11 |
|
T29 |
21 |
|
T33 |
9 |
auto[1] |
auto[0] |
14311 |
1 |
|
|
T2 |
15 |
|
T4 |
12 |
|
T14 |
75 |
auto[1] |
auto[1] |
765 |
1 |
|
|
T14 |
5 |
|
T15 |
10 |
|
T18 |
19 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33048 |
1 |
|
|
T1 |
16 |
|
T8 |
90 |
|
T9 |
62 |
auto[0] |
auto[1] |
1421 |
1 |
|
|
T15 |
15 |
|
T18 |
15 |
|
T42 |
28 |
auto[1] |
auto[0] |
14092 |
1 |
|
|
T2 |
15 |
|
T14 |
80 |
|
T15 |
110 |
auto[1] |
auto[1] |
984 |
1 |
|
|
T4 |
12 |
|
T15 |
10 |
|
T42 |
29 |