Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94293313

1

T1

5524

T2

40078

T3

25409

auto[1]

1318482

1

T2

588

T4

98

T8

495

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94298571

1

T1

5524

T2

39784

T3

25409

auto[1]

1313224

1

T2

882

T4

196

T8

594

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6601462	1			T1	1534		T2	1476		T3	93
auto[IdleSt]	22023579	1			T1	1340		T2	21810		T3	25316
auto[ClkMuxSt]	33236	1			T1	15		T2	15		T4	9
auto[CntIncrSt]	33085	1			T1	15		T2	15		T4	9
auto[CntProgSt]	1628762	1			T1	177		T2	520		T4	18
auto[TransCheckSt]	25772	1			T1	15		T4	9		T8	68
auto[TokenHashSt]	34225140	1			T1	1435		T4	202		T8	1102
auto[FlashRmaSt]	32123	1			T1	59		T4	23		T8	24
auto[TokenCheck0St]	11591	1			T1	15		T4	9		T8	18
auto[TokenCheck1St]	8552	1			T1	15		T4	9		T8	10
auto[TransProgSt]	439079	1			T1	170		T4	18		T8	327
auto[PostTransSt]	13059303	1			T1	709		T2	9360		T7	561
auto[ScrapSt]	168751	1			T1	25		T9	3		T34	30
auto[EscalateSt]	6444762	1			T2	7470		T4	3496		T8	1534
auto[InvalidSt]	10874829	1			T4	2777		T13	4266		T15	2434

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1769	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10874829	1			T4	2777		T13	4266		T15	2434
EscalateSt	6444762	1			T2	7470		T4	3496		T8	1534
ScrapSt	168751	1			T1	25		T9	3		T34	30
PostTransSt	13059303	1			T1	709		T2	9360		T7	561
TransProgSt	439079	1			T1	170		T4	18		T8	327
TokenCheck1St	8552	1			T1	15		T4	9		T8	10
TokenCheck0St	11591	1			T1	15		T4	9		T8	18
FlashRmaSt	32123	1			T1	59		T4	23		T8	24
TokenHashSt	34225140	1			T1	1435		T4	202		T8	1102
TransCheckSt	25772	1			T1	15		T4	9		T8	68
CntProgSt	1628762	1			T1	177		T2	520		T4	18
CntIncrSt	33085	1			T1	15		T2	15		T4	9
ClkMuxSt	33236	1			T1	15		T2	15		T4	9
IdleSt	22023579	1			T1	1340		T2	21810		T3	25316
ResetSt	6601462	1			T1	1534		T2	1476		T3	93
arcs[ResetSt=>IdleSt]	49966	1			T1	16		T2	16		T3	1
arcs[IdleSt=>ScrapSt]	250	1			T1	1		T9	1		T34	1
arcs[IdleSt=>ClkMuxSt]	33138	1			T1	15		T2	15		T4	9
arcs[ClkMuxSt=>CntIncrSt]	33085	1			T1	15		T2	15		T4	9
arcs[CntIncrSt=>PostTransSt]	1749	1			T8	11		T14	5		T29	21
arcs[CntIncrSt=>CntProgSt]	31277	1			T1	15		T2	15		T4	9
arcs[CntProgSt=>PostTransSt]	4409	1			T2	15		T8	11		T10	14
arcs[CntProgSt=>TransCheckSt]	25772	1			T1	15		T4	9		T8	68
arcs[TransCheckSt=>PostTransSt]	3553	1			T8	17		T11	48		T14	11
arcs[TransCheckSt=>TokenHashSt]	22099	1			T1	15		T4	9		T8	51
arcs[TokenHashSt=>PostTransSt]	9728	1			T8	33		T11	8		T14	32
arcs[TokenHashSt=>FlashRmaSt]	11701	1			T1	15		T4	9		T8	18
arcs[FlashRmaSt=>TokenCheck0St]	11591	1			T1	15		T4	9		T8	18
arcs[TokenCheck0St=>PostTransSt]	3020	1			T8	8		T11	17		T14	10
arcs[TokenCheck0St=>TokenCheck1St]	8552	1			T1	15		T4	9		T8	10
arcs[TokenCheck1St=>PostTransSt]	587	1			T8	2		T11	14		T14	1
arcs[TransProgSt=>PostTransSt]	7031	1			T1	15		T4	9		T8	8
arcs[IdleSt=>EscalateSt]	229	1			T46	5		T47	13		T48	5
arcs[ClkMuxSt=>EscalateSt]	53	1			T46	1		T47	2		T48	1
arcs[CntIncrSt=>EscalateSt]	59	1			T9	2		T46	2		T47	1
arcs[CntProgSt=>EscalateSt]	1096	1			T9	29		T46	31		T47	9
arcs[TransCheckSt=>EscalateSt]	120	1			T47	5		T48	2		T51	7
arcs[TokenHashSt=>EscalateSt]	670	1			T9	8		T18	1		T46	3
arcs[FlashRmaSt=>EscalateSt]	110	1			T46	3		T47	1		T48	6
arcs[TokenCheck0St=>EscalateSt]	19	1			T9	1		T33	1		T48	1
arcs[TokenCheck1St=>EscalateSt]	154	1			T9	2		T46	6		T47	4
arcs[TransProgSt=>EscalateSt]	780	1			T9	14		T46	20		T47	6
arcs[PostTransSt=>EscalateSt]	4645	1			T2	15		T8	11		T10	14
arcs[InvalidSt=>EscalateSt]	12514	1			T4	3		T13	57		T15	9

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6601280	1			T1	1534		T2	1476		T3	93
auto[0]	auto[IdleSt]	22023411	1			T1	1340		T2	21810		T3	25316
auto[0]	auto[ClkMuxSt]	33198	1			T1	15		T2	15		T4	9
auto[0]	auto[CntIncrSt]	33053	1			T1	15		T2	15		T4	9
auto[0]	auto[CntProgSt]	1628032	1			T1	177		T2	520		T4	18
auto[0]	auto[TransCheckSt]	25698	1			T1	15		T4	9		T8	68
auto[0]	auto[TokenHashSt]	34224689	1			T1	1435		T4	202		T8	1102
auto[0]	auto[FlashRmaSt]	32045	1			T1	59		T4	23		T8	24
auto[0]	auto[TokenCheck0St]	11579	1			T1	15		T4	9		T8	18
auto[0]	auto[TokenCheck1St]	8454	1			T1	15		T4	9		T8	10
auto[0]	auto[TransProgSt]	438553	1			T1	170		T4	18		T8	327
auto[0]	auto[PostTransSt]	13056936	1			T1	709		T2	9354		T7	561
auto[0]	auto[ScrapSt]	168716	1			T1	25		T9	2		T34	30
auto[0]	auto[EscalateSt]	5137291	1			T2	6888		T4	3399		T8	1044
auto[0]	auto[InvalidSt]	10868609	1			T4	2776		T13	4238		T15	2430
auto[1]	auto[ResetSt]	182	1			T9	2		T46	1		T47	1
auto[1]	auto[IdleSt]	168	1			T46	2		T47	10		T48	4
auto[1]	auto[ClkMuxSt]	38	1			T46	1		T47	2		T48	1
auto[1]	auto[CntIncrSt]	32	1			T9	1		T46	1		T47	1
auto[1]	auto[CntProgSt]	730	1			T9	17		T46	20		T47	7
auto[1]	auto[TransCheckSt]	74	1			T47	2		T48	1		T51	4
auto[1]	auto[TokenHashSt]	451	1			T9	6		T18	1		T47	15
auto[1]	auto[FlashRmaSt]	78	1			T46	2		T47	1		T48	4
auto[1]	auto[TokenCheck0St]	12	1			T33	1		T48	1		T98	1
auto[1]	auto[TokenCheck1St]	98	1			T9	1		T46	2		T47	4
auto[1]	auto[TransProgSt]	526	1			T9	9		T46	16		T47	2
auto[1]	auto[PostTransSt]	2367	1			T2	6		T8	5		T10	4
auto[1]	auto[ScrapSt]	35	1			T9	1		T47	1		T209	1
auto[1]	auto[EscalateSt]	1307471	1			T2	582		T4	97		T8	490
auto[1]	auto[InvalidSt]	6220	1			T4	1		T13	28		T15	4

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6601309	1			T1	1534		T2	1476		T3	93
auto[0]	auto[IdleSt]	22023431	1			T1	1340		T2	21810		T3	25316
auto[0]	auto[ClkMuxSt]	33202	1			T1	15		T2	15		T4	9
auto[0]	auto[CntIncrSt]	33037	1			T1	15		T2	15		T4	9
auto[0]	auto[CntProgSt]	1628025	1			T1	177		T2	520		T4	18
auto[0]	auto[TransCheckSt]	25701	1			T1	15		T4	9		T8	68
auto[0]	auto[TokenHashSt]	34224690	1			T1	1435		T4	202		T8	1102
auto[0]	auto[FlashRmaSt]	32049	1			T1	59		T4	23		T8	24
auto[0]	auto[TokenCheck0St]	11576	1			T1	15		T4	9		T8	18
auto[0]	auto[TokenCheck1St]	8447	1			T1	15		T4	9		T8	10
auto[0]	auto[TransProgSt]	438569	1			T1	170		T4	18		T8	327
auto[0]	auto[PostTransSt]	13056953	1			T1	709		T2	9351		T7	561
auto[0]	auto[ScrapSt]	168710	1			T1	25		T9	2		T34	30
auto[0]	auto[EscalateSt]	5142568	1			T2	6597		T4	3302		T8	946
auto[0]	auto[InvalidSt]	10868535	1			T4	2775		T13	4237		T15	2429
auto[1]	auto[ResetSt]	153	1			T9	4		T46	3		T47	2
auto[1]	auto[IdleSt]	148	1			T46	3		T47	7		T48	5
auto[1]	auto[ClkMuxSt]	34	1			T46	1		T51	2		T210	1
auto[1]	auto[CntIncrSt]	48	1			T9	1		T46	2		T51	1
auto[1]	auto[CntProgSt]	737	1			T9	22		T46	22		T47	7
auto[1]	auto[TransCheckSt]	71	1			T47	4		T48	2		T51	4
auto[1]	auto[TokenHashSt]	450	1			T9	5		T46	3		T47	18
auto[1]	auto[FlashRmaSt]	74	1			T46	2		T48	4		T211	2
auto[1]	auto[TokenCheck0St]	15	1			T9	1		T48	1		T210	1
auto[1]	auto[TokenCheck1St]	105	1			T9	2		T46	4		T47	3
auto[1]	auto[TransProgSt]	510	1			T9	12		T46	8		T47	4
auto[1]	auto[PostTransSt]	2350	1			T2	9		T8	6		T10	10
auto[1]	auto[ScrapSt]	41	1			T9	1		T46	1		T48	1
auto[1]	auto[EscalateSt]	1302194	1			T2	873		T4	194		T8	588
auto[1]	auto[InvalidSt]	6294	1			T4	2		T13	29		T15	5