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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.20 97.99 95.68 93.38 100.00 98.55 98.51 96.29


Total test records in report: 982
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T814 /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1867390246 Jul 14 05:30:19 PM PDT 24 Jul 14 05:30:31 PM PDT 24 286156922 ps
T815 /workspace/coverage/default/24.lc_ctrl_state_post_trans.2719634838 Jul 14 05:29:34 PM PDT 24 Jul 14 05:29:42 PM PDT 24 450392963 ps
T816 /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3790339547 Jul 14 05:28:38 PM PDT 24 Jul 14 05:28:41 PM PDT 24 97693092 ps
T817 /workspace/coverage/default/30.lc_ctrl_smoke.1795062803 Jul 14 05:29:58 PM PDT 24 Jul 14 05:30:02 PM PDT 24 63618859 ps
T818 /workspace/coverage/default/15.lc_ctrl_errors.2246905706 Jul 14 05:28:56 PM PDT 24 Jul 14 05:29:05 PM PDT 24 989575825 ps
T819 /workspace/coverage/default/25.lc_ctrl_alert_test.2169732188 Jul 14 05:29:40 PM PDT 24 Jul 14 05:29:41 PM PDT 24 68739699 ps
T820 /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2238704734 Jul 14 05:27:22 PM PDT 24 Jul 14 05:27:24 PM PDT 24 15902480 ps
T821 /workspace/coverage/default/44.lc_ctrl_sec_token_digest.4114208786 Jul 14 05:30:51 PM PDT 24 Jul 14 05:31:03 PM PDT 24 1465160580 ps
T822 /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3963468091 Jul 14 05:30:03 PM PDT 24 Jul 14 05:30:14 PM PDT 24 2010804734 ps
T823 /workspace/coverage/default/42.lc_ctrl_jtag_access.1770361288 Jul 14 05:30:38 PM PDT 24 Jul 14 05:30:48 PM PDT 24 385602143 ps
T824 /workspace/coverage/default/3.lc_ctrl_errors.4144176314 Jul 14 05:27:31 PM PDT 24 Jul 14 05:27:47 PM PDT 24 4241685288 ps
T825 /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1743748045 Jul 14 05:27:44 PM PDT 24 Jul 14 05:27:53 PM PDT 24 1038481790 ps
T826 /workspace/coverage/default/17.lc_ctrl_jtag_access.1832821431 Jul 14 05:29:09 PM PDT 24 Jul 14 05:29:16 PM PDT 24 2176782146 ps
T827 /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.38107197 Jul 14 05:29:11 PM PDT 24 Jul 14 05:30:36 PM PDT 24 47159528812 ps
T828 /workspace/coverage/default/3.lc_ctrl_state_failure.2893804340 Jul 14 05:27:32 PM PDT 24 Jul 14 05:28:05 PM PDT 24 1142010586 ps
T829 /workspace/coverage/default/15.lc_ctrl_state_failure.2406609613 Jul 14 05:28:56 PM PDT 24 Jul 14 05:29:27 PM PDT 24 2038122980 ps
T830 /workspace/coverage/default/42.lc_ctrl_stress_all.1926110349 Jul 14 05:30:38 PM PDT 24 Jul 14 05:32:57 PM PDT 24 76463224577 ps
T831 /workspace/coverage/default/2.lc_ctrl_jtag_priority.1771391711 Jul 14 05:27:31 PM PDT 24 Jul 14 05:27:40 PM PDT 24 983866952 ps
T832 /workspace/coverage/default/14.lc_ctrl_prog_failure.3856171810 Jul 14 05:28:51 PM PDT 24 Jul 14 05:28:55 PM PDT 24 1404711903 ps
T833 /workspace/coverage/default/40.lc_ctrl_prog_failure.1110521524 Jul 14 05:30:35 PM PDT 24 Jul 14 05:30:37 PM PDT 24 17576703 ps
T834 /workspace/coverage/default/6.lc_ctrl_errors.707810582 Jul 14 05:28:04 PM PDT 24 Jul 14 05:28:17 PM PDT 24 1578214321 ps
T835 /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1236310979 Jul 14 05:27:37 PM PDT 24 Jul 14 05:28:04 PM PDT 24 724319709 ps
T836 /workspace/coverage/default/14.lc_ctrl_smoke.33998720 Jul 14 05:28:52 PM PDT 24 Jul 14 05:28:55 PM PDT 24 132758081 ps
T837 /workspace/coverage/default/23.lc_ctrl_jtag_access.2074270661 Jul 14 05:29:36 PM PDT 24 Jul 14 05:29:56 PM PDT 24 1703272697 ps
T838 /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2065159173 Jul 14 05:28:30 PM PDT 24 Jul 14 05:28:39 PM PDT 24 376380299 ps
T839 /workspace/coverage/default/1.lc_ctrl_security_escalation.2663887541 Jul 14 05:27:15 PM PDT 24 Jul 14 05:27:23 PM PDT 24 1146493031 ps
T840 /workspace/coverage/default/44.lc_ctrl_state_post_trans.1134678710 Jul 14 05:30:47 PM PDT 24 Jul 14 05:30:55 PM PDT 24 82783710 ps
T841 /workspace/coverage/default/30.lc_ctrl_state_failure.3354790031 Jul 14 05:30:00 PM PDT 24 Jul 14 05:30:28 PM PDT 24 1042378894 ps
T842 /workspace/coverage/default/11.lc_ctrl_jtag_access.2126803474 Jul 14 05:28:41 PM PDT 24 Jul 14 05:28:48 PM PDT 24 900564461 ps
T70 /workspace/coverage/default/19.lc_ctrl_smoke.4267021872 Jul 14 05:29:22 PM PDT 24 Jul 14 05:29:28 PM PDT 24 1722889076 ps
T106 /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.4097553592 Jul 14 05:31:20 PM PDT 24 Jul 14 05:49:39 PM PDT 24 26677434712 ps
T843 /workspace/coverage/default/30.lc_ctrl_state_post_trans.2728880113 Jul 14 05:29:59 PM PDT 24 Jul 14 05:30:06 PM PDT 24 137075213 ps
T844 /workspace/coverage/default/35.lc_ctrl_errors.1282515072 Jul 14 05:30:16 PM PDT 24 Jul 14 05:30:30 PM PDT 24 1218317182 ps
T845 /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2933360728 Jul 14 05:28:37 PM PDT 24 Jul 14 05:28:45 PM PDT 24 2466889527 ps
T846 /workspace/coverage/default/7.lc_ctrl_security_escalation.2165470643 Jul 14 05:28:06 PM PDT 24 Jul 14 05:28:14 PM PDT 24 565954704 ps
T847 /workspace/coverage/default/47.lc_ctrl_stress_all.3488326401 Jul 14 05:31:21 PM PDT 24 Jul 14 05:39:25 PM PDT 24 15807639284 ps
T848 /workspace/coverage/default/12.lc_ctrl_security_escalation.1734616367 Jul 14 05:28:39 PM PDT 24 Jul 14 05:28:47 PM PDT 24 1000506770 ps
T849 /workspace/coverage/default/18.lc_ctrl_errors.1161452882 Jul 14 05:29:15 PM PDT 24 Jul 14 05:29:29 PM PDT 24 538965942 ps
T850 /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1949177081 Jul 14 05:29:24 PM PDT 24 Jul 14 05:29:37 PM PDT 24 1025292076 ps
T851 /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3697630251 Jul 14 05:28:24 PM PDT 24 Jul 14 05:29:08 PM PDT 24 3700773665 ps
T852 /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3840479122 Jul 14 05:29:28 PM PDT 24 Jul 14 05:29:38 PM PDT 24 801242663 ps
T853 /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2985032394 Jul 14 05:29:39 PM PDT 24 Jul 14 05:29:55 PM PDT 24 1600466631 ps
T854 /workspace/coverage/default/1.lc_ctrl_regwen_during_op.661616724 Jul 14 05:27:16 PM PDT 24 Jul 14 05:27:31 PM PDT 24 4166893607 ps
T855 /workspace/coverage/default/24.lc_ctrl_sec_token_mux.670331353 Jul 14 05:29:47 PM PDT 24 Jul 14 05:29:57 PM PDT 24 267670916 ps
T856 /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1790086642 Jul 14 05:29:03 PM PDT 24 Jul 14 05:29:36 PM PDT 24 4044650822 ps
T857 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1752472142 Jul 14 05:30:53 PM PDT 24 Jul 14 05:31:02 PM PDT 24 1424598725 ps
T858 /workspace/coverage/default/9.lc_ctrl_security_escalation.2812163729 Jul 14 05:28:23 PM PDT 24 Jul 14 05:28:32 PM PDT 24 798203533 ps
T110 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3827964752 Jul 14 05:22:42 PM PDT 24 Jul 14 05:22:44 PM PDT 24 204790717 ps
T116 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3775501860 Jul 14 05:22:36 PM PDT 24 Jul 14 05:22:40 PM PDT 24 95497887 ps
T117 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.476508510 Jul 14 05:22:54 PM PDT 24 Jul 14 05:22:57 PM PDT 24 39591297 ps
T139 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2858580568 Jul 14 05:23:11 PM PDT 24 Jul 14 05:23:14 PM PDT 24 55670006 ps
T111 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2804189835 Jul 14 05:22:41 PM PDT 24 Jul 14 05:22:43 PM PDT 24 575351799 ps
T147 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2588738443 Jul 14 05:23:26 PM PDT 24 Jul 14 05:23:28 PM PDT 24 16090526 ps
T112 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.301380211 Jul 14 05:23:31 PM PDT 24 Jul 14 05:23:34 PM PDT 24 36691271 ps
T103 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1241619749 Jul 14 05:23:18 PM PDT 24 Jul 14 05:23:22 PM PDT 24 239450428 ps
T104 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1344634165 Jul 14 05:23:25 PM PDT 24 Jul 14 05:23:29 PM PDT 24 298626661 ps
T148 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3385183624 Jul 14 05:23:00 PM PDT 24 Jul 14 05:23:03 PM PDT 24 54536098 ps
T859 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.920241446 Jul 14 05:22:42 PM PDT 24 Jul 14 05:22:44 PM PDT 24 239767807 ps
T860 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4228626007 Jul 14 05:22:40 PM PDT 24 Jul 14 05:22:45 PM PDT 24 439890087 ps
T861 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1899795790 Jul 14 05:23:02 PM PDT 24 Jul 14 05:23:06 PM PDT 24 69495275 ps
T105 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2601386151 Jul 14 05:23:26 PM PDT 24 Jul 14 05:23:31 PM PDT 24 300062720 ps
T184 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1525902037 Jul 14 05:23:24 PM PDT 24 Jul 14 05:23:26 PM PDT 24 20145719 ps
T185 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1596216966 Jul 14 05:23:14 PM PDT 24 Jul 14 05:23:15 PM PDT 24 22675285 ps
T862 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1672276370 Jul 14 05:23:03 PM PDT 24 Jul 14 05:23:06 PM PDT 24 72683230 ps
T197 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.492481584 Jul 14 05:23:12 PM PDT 24 Jul 14 05:23:14 PM PDT 24 13252155 ps
T108 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.692622527 Jul 14 05:23:21 PM PDT 24 Jul 14 05:23:24 PM PDT 24 39545358 ps
T863 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1163070458 Jul 14 05:22:42 PM PDT 24 Jul 14 05:22:45 PM PDT 24 244699645 ps
T107 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.4129722345 Jul 14 05:23:20 PM PDT 24 Jul 14 05:23:23 PM PDT 24 104713555 ps
T137 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2816382713 Jul 14 05:23:01 PM PDT 24 Jul 14 05:23:14 PM PDT 24 1908967492 ps
T864 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1050375303 Jul 14 05:23:03 PM PDT 24 Jul 14 05:23:06 PM PDT 24 30318007 ps
T865 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3112875029 Jul 14 05:22:35 PM PDT 24 Jul 14 05:22:37 PM PDT 24 92475171 ps
T109 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3910643439 Jul 14 05:23:16 PM PDT 24 Jul 14 05:23:22 PM PDT 24 159720001 ps
T138 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3591499960 Jul 14 05:23:07 PM PDT 24 Jul 14 05:23:10 PM PDT 24 326328118 ps
T198 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2217228296 Jul 14 05:23:22 PM PDT 24 Jul 14 05:23:24 PM PDT 24 30621502 ps
T199 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2196617876 Jul 14 05:23:26 PM PDT 24 Jul 14 05:23:28 PM PDT 24 30207288 ps
T866 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.155317605 Jul 14 05:23:01 PM PDT 24 Jul 14 05:23:04 PM PDT 24 16079028 ps
T200 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2435976063 Jul 14 05:23:03 PM PDT 24 Jul 14 05:23:06 PM PDT 24 70936705 ps
T867 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.57732047 Jul 14 05:22:56 PM PDT 24 Jul 14 05:23:09 PM PDT 24 517826360 ps
T201 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1384398653 Jul 14 05:23:26 PM PDT 24 Jul 14 05:23:28 PM PDT 24 87401779 ps
T202 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2154088036 Jul 14 05:23:15 PM PDT 24 Jul 14 05:23:17 PM PDT 24 78847702 ps
T868 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.512407055 Jul 14 05:22:54 PM PDT 24 Jul 14 05:22:56 PM PDT 24 80522096 ps
T869 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3185303120 Jul 14 05:23:11 PM PDT 24 Jul 14 05:23:14 PM PDT 24 185732961 ps
T115 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3372310046 Jul 14 05:23:18 PM PDT 24 Jul 14 05:23:22 PM PDT 24 156921925 ps
T130 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2857724416 Jul 14 05:22:52 PM PDT 24 Jul 14 05:22:54 PM PDT 24 163835610 ps
T203 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1901237838 Jul 14 05:23:06 PM PDT 24 Jul 14 05:23:07 PM PDT 24 47240197 ps
T161 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.110932509 Jul 14 05:23:22 PM PDT 24 Jul 14 05:23:24 PM PDT 24 29670617 ps
T131 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1554622916 Jul 14 05:23:21 PM PDT 24 Jul 14 05:23:27 PM PDT 24 113918388 ps
T121 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3085634188 Jul 14 05:23:25 PM PDT 24 Jul 14 05:23:28 PM PDT 24 249057607 ps
T171 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.294218717 Jul 14 05:23:26 PM PDT 24 Jul 14 05:23:28 PM PDT 24 47402950 ps
T870 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.4186781443 Jul 14 05:22:42 PM PDT 24 Jul 14 05:22:44 PM PDT 24 21818969 ps
T871 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2756075414 Jul 14 05:22:49 PM PDT 24 Jul 14 05:22:50 PM PDT 24 148682408 ps
T872 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3624846129 Jul 14 05:23:11 PM PDT 24 Jul 14 05:23:13 PM PDT 24 159037030 ps
T873 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3994090099 Jul 14 05:22:55 PM PDT 24 Jul 14 05:22:58 PM PDT 24 133965406 ps
T874 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.352468569 Jul 14 05:22:56 PM PDT 24 Jul 14 05:22:58 PM PDT 24 72403016 ps
T875 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2600326304 Jul 14 05:22:56 PM PDT 24 Jul 14 05:23:10 PM PDT 24 3462546692 ps
T186 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2520482963 Jul 14 05:22:54 PM PDT 24 Jul 14 05:22:57 PM PDT 24 12350208 ps
T172 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1185698126 Jul 14 05:23:11 PM PDT 24 Jul 14 05:23:15 PM PDT 24 226339906 ps
T876 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.878799008 Jul 14 05:23:23 PM PDT 24 Jul 14 05:23:24 PM PDT 24 26295446 ps
T123 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3397011924 Jul 14 05:23:02 PM PDT 24 Jul 14 05:23:06 PM PDT 24 277819347 ps
T877 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2220784879 Jul 14 05:22:54 PM PDT 24 Jul 14 05:22:56 PM PDT 24 34266587 ps
T878 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3650382973 Jul 14 05:22:35 PM PDT 24 Jul 14 05:22:40 PM PDT 24 624967227 ps
T879 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2306517612 Jul 14 05:22:45 PM PDT 24 Jul 14 05:22:46 PM PDT 24 133350951 ps
T880 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.595272083 Jul 14 05:23:19 PM PDT 24 Jul 14 05:23:23 PM PDT 24 51891204 ps
T881 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.147499281 Jul 14 05:22:45 PM PDT 24 Jul 14 05:22:47 PM PDT 24 248043742 ps
T135 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2127636046 Jul 14 05:23:19 PM PDT 24 Jul 14 05:23:22 PM PDT 24 42298441 ps
T113 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3293927860 Jul 14 05:22:38 PM PDT 24 Jul 14 05:22:42 PM PDT 24 775155255 ps
T124 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.309149762 Jul 14 05:23:07 PM PDT 24 Jul 14 05:23:12 PM PDT 24 119318077 ps
T882 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1126103114 Jul 14 05:23:08 PM PDT 24 Jul 14 05:23:14 PM PDT 24 5715942828 ps
T127 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4288744838 Jul 14 05:23:02 PM PDT 24 Jul 14 05:23:07 PM PDT 24 223173147 ps
T883 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2109820650 Jul 14 05:23:00 PM PDT 24 Jul 14 05:23:02 PM PDT 24 22071101 ps
T114 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3154256724 Jul 14 05:23:19 PM PDT 24 Jul 14 05:23:23 PM PDT 24 76487774 ps
T884 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2606823002 Jul 14 05:23:16 PM PDT 24 Jul 14 05:23:18 PM PDT 24 65226655 ps
T885 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4107371481 Jul 14 05:22:51 PM PDT 24 Jul 14 05:22:53 PM PDT 24 126259688 ps
T886 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.512140315 Jul 14 05:23:24 PM PDT 24 Jul 14 05:23:26 PM PDT 24 48965657 ps
T887 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2387838630 Jul 14 05:23:13 PM PDT 24 Jul 14 05:23:15 PM PDT 24 51488523 ps
T888 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1491135574 Jul 14 05:23:03 PM PDT 24 Jul 14 05:23:06 PM PDT 24 87348842 ps
T889 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3487987751 Jul 14 05:23:11 PM PDT 24 Jul 14 05:23:12 PM PDT 24 31163552 ps
T890 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1641336579 Jul 14 05:22:55 PM PDT 24 Jul 14 05:22:58 PM PDT 24 555690193 ps
T891 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1533751180 Jul 14 05:23:12 PM PDT 24 Jul 14 05:23:15 PM PDT 24 28509978 ps
T892 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1510389371 Jul 14 05:23:20 PM PDT 24 Jul 14 05:23:24 PM PDT 24 656236014 ps
T126 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.370740971 Jul 14 05:23:02 PM PDT 24 Jul 14 05:23:05 PM PDT 24 55784372 ps
T893 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1293153699 Jul 14 05:23:00 PM PDT 24 Jul 14 05:23:03 PM PDT 24 107365556 ps
T187 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3980230097 Jul 14 05:23:21 PM PDT 24 Jul 14 05:23:23 PM PDT 24 184995582 ps
T894 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1899274377 Jul 14 05:22:41 PM PDT 24 Jul 14 05:22:43 PM PDT 24 42240351 ps
T895 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.968345287 Jul 14 05:22:37 PM PDT 24 Jul 14 05:22:38 PM PDT 24 117181138 ps
T896 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1760011228 Jul 14 05:22:54 PM PDT 24 Jul 14 05:22:58 PM PDT 24 723451695 ps
T897 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.966644802 Jul 14 05:23:27 PM PDT 24 Jul 14 05:23:28 PM PDT 24 22773004 ps
T898 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1702010177 Jul 14 05:22:54 PM PDT 24 Jul 14 05:22:59 PM PDT 24 188745067 ps
T899 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.833968399 Jul 14 05:22:42 PM PDT 24 Jul 14 05:22:46 PM PDT 24 385921676 ps
T118 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.946591509 Jul 14 05:23:26 PM PDT 24 Jul 14 05:23:31 PM PDT 24 76823434 ps
T900 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3771032254 Jul 14 05:23:21 PM PDT 24 Jul 14 05:23:23 PM PDT 24 90087529 ps
T136 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.288679731 Jul 14 05:23:19 PM PDT 24 Jul 14 05:23:23 PM PDT 24 88742588 ps
T901 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.62831934 Jul 14 05:22:41 PM PDT 24 Jul 14 05:22:43 PM PDT 24 54297349 ps
T119 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.91262170 Jul 14 05:23:03 PM PDT 24 Jul 14 05:23:09 PM PDT 24 1135470516 ps
T902 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2872716061 Jul 14 05:23:07 PM PDT 24 Jul 14 05:23:12 PM PDT 24 332829942 ps
T903 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1513819262 Jul 14 05:22:48 PM PDT 24 Jul 14 05:22:50 PM PDT 24 187985958 ps
T904 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1061290883 Jul 14 05:23:34 PM PDT 24 Jul 14 05:23:36 PM PDT 24 267998199 ps
T905 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3690606313 Jul 14 05:23:00 PM PDT 24 Jul 14 05:23:13 PM PDT 24 2352861189 ps
T188 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1664667983 Jul 14 05:22:35 PM PDT 24 Jul 14 05:22:37 PM PDT 24 69353090 ps
T906 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.262042980 Jul 14 05:23:12 PM PDT 24 Jul 14 05:23:19 PM PDT 24 489531665 ps
T907 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2776548 Jul 14 05:22:49 PM PDT 24 Jul 14 05:22:51 PM PDT 24 438501504 ps
T908 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1453689049 Jul 14 05:23:05 PM PDT 24 Jul 14 05:23:08 PM PDT 24 58989862 ps
T909 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2552916415 Jul 14 05:23:11 PM PDT 24 Jul 14 05:23:16 PM PDT 24 180386717 ps
T910 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3141228469 Jul 14 05:23:01 PM PDT 24 Jul 14 05:23:05 PM PDT 24 404497800 ps
T911 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1283147476 Jul 14 05:23:01 PM PDT 24 Jul 14 05:23:04 PM PDT 24 203425761 ps
T132 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1344041196 Jul 14 05:22:58 PM PDT 24 Jul 14 05:23:02 PM PDT 24 282874288 ps
T912 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2905823834 Jul 14 05:23:28 PM PDT 24 Jul 14 05:23:30 PM PDT 24 32450614 ps
T913 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3803164514 Jul 14 05:23:07 PM PDT 24 Jul 14 05:23:09 PM PDT 24 78858973 ps
T125 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2965218084 Jul 14 05:22:54 PM PDT 24 Jul 14 05:22:57 PM PDT 24 119486494 ps
T914 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.964418321 Jul 14 05:22:35 PM PDT 24 Jul 14 05:22:39 PM PDT 24 723981940 ps
T915 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2076998439 Jul 14 05:23:21 PM PDT 24 Jul 14 05:23:23 PM PDT 24 168557367 ps
T916 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3839440867 Jul 14 05:23:27 PM PDT 24 Jul 14 05:23:30 PM PDT 24 75480536 ps
T917 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3133371996 Jul 14 05:22:58 PM PDT 24 Jul 14 05:23:23 PM PDT 24 1227762336 ps
T918 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3089911354 Jul 14 05:22:36 PM PDT 24 Jul 14 05:22:38 PM PDT 24 68210648 ps
T122 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3208751861 Jul 14 05:22:37 PM PDT 24 Jul 14 05:22:40 PM PDT 24 264269066 ps
T919 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2730207794 Jul 14 05:23:13 PM PDT 24 Jul 14 05:23:14 PM PDT 24 58826175 ps
T920 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3081758046 Jul 14 05:23:00 PM PDT 24 Jul 14 05:23:03 PM PDT 24 76194565 ps
T921 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3743396079 Jul 14 05:22:35 PM PDT 24 Jul 14 05:22:38 PM PDT 24 47794856 ps
T189 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3601145940 Jul 14 05:22:41 PM PDT 24 Jul 14 05:22:43 PM PDT 24 114866103 ps
T922 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.418204901 Jul 14 05:22:40 PM PDT 24 Jul 14 05:22:44 PM PDT 24 121751511 ps
T134 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3420469452 Jul 14 05:23:16 PM PDT 24 Jul 14 05:23:20 PM PDT 24 76859646 ps
T923 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.4026784700 Jul 14 05:23:27 PM PDT 24 Jul 14 05:23:30 PM PDT 24 382387710 ps
T924 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.420711287 Jul 14 05:22:35 PM PDT 24 Jul 14 05:22:51 PM PDT 24 5831734991 ps
T190 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1397774400 Jul 14 05:23:04 PM PDT 24 Jul 14 05:23:06 PM PDT 24 60810450 ps
T925 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.367335360 Jul 14 05:23:21 PM PDT 24 Jul 14 05:23:24 PM PDT 24 123022244 ps
T926 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1139490124 Jul 14 05:22:54 PM PDT 24 Jul 14 05:22:58 PM PDT 24 304790438 ps
T927 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2955597506 Jul 14 05:23:01 PM PDT 24 Jul 14 05:23:07 PM PDT 24 574989758 ps
T928 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2450112294 Jul 14 05:23:11 PM PDT 24 Jul 14 05:23:13 PM PDT 24 28705786 ps
T929 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.194640735 Jul 14 05:23:01 PM PDT 24 Jul 14 05:23:04 PM PDT 24 436971934 ps
T930 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.556761500 Jul 14 05:23:30 PM PDT 24 Jul 14 05:23:31 PM PDT 24 19265736 ps
T931 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2266234515 Jul 14 05:22:53 PM PDT 24 Jul 14 05:22:54 PM PDT 24 51731495 ps
T932 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3112853264 Jul 14 05:23:11 PM PDT 24 Jul 14 05:23:16 PM PDT 24 351714888 ps
T191 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2591328567 Jul 14 05:23:04 PM PDT 24 Jul 14 05:23:07 PM PDT 24 44255341 ps
T933 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1175774962 Jul 14 05:22:57 PM PDT 24 Jul 14 05:23:03 PM PDT 24 212336562 ps
T934 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3681404656 Jul 14 05:22:50 PM PDT 24 Jul 14 05:22:51 PM PDT 24 23759638 ps
T935 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2877428340 Jul 14 05:23:24 PM PDT 24 Jul 14 05:23:26 PM PDT 24 109242473 ps
T936 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1898805869 Jul 14 05:23:02 PM PDT 24 Jul 14 05:23:04 PM PDT 24 27551668 ps
T937 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2771408081 Jul 14 05:23:07 PM PDT 24 Jul 14 05:23:09 PM PDT 24 72500579 ps
T938 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3646515040 Jul 14 05:23:17 PM PDT 24 Jul 14 05:23:20 PM PDT 24 264710212 ps
T939 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3204664567 Jul 14 05:22:42 PM PDT 24 Jul 14 05:22:44 PM PDT 24 62337581 ps
T133 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2655173173 Jul 14 05:23:30 PM PDT 24 Jul 14 05:23:32 PM PDT 24 89108839 ps
T940 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.779585192 Jul 14 05:22:59 PM PDT 24 Jul 14 05:23:02 PM PDT 24 29094438 ps
T192 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.683046620 Jul 14 05:23:00 PM PDT 24 Jul 14 05:23:02 PM PDT 24 16730884 ps
T941 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2971278860 Jul 14 05:23:28 PM PDT 24 Jul 14 05:23:30 PM PDT 24 27867505 ps
T193 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3015549074 Jul 14 05:22:47 PM PDT 24 Jul 14 05:22:49 PM PDT 24 39986608 ps
T942 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1198570207 Jul 14 05:22:43 PM PDT 24 Jul 14 05:22:57 PM PDT 24 1124329224 ps
T943 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.4093490368 Jul 14 05:23:03 PM PDT 24 Jul 14 05:23:10 PM PDT 24 159647074 ps
T194 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1976767429 Jul 14 05:23:35 PM PDT 24 Jul 14 05:23:37 PM PDT 24 62022408 ps
T944 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4239076720 Jul 14 05:22:49 PM PDT 24 Jul 14 05:23:09 PM PDT 24 2493526087 ps
T196 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.39471501 Jul 14 05:23:31 PM PDT 24 Jul 14 05:23:33 PM PDT 24 16276951 ps
T128 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2406211249 Jul 14 05:22:42 PM PDT 24 Jul 14 05:22:44 PM PDT 24 244977962 ps
T945 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3911182684 Jul 14 05:23:03 PM PDT 24 Jul 14 05:23:14 PM PDT 24 1347738419 ps
T946 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.247324171 Jul 14 05:23:26 PM PDT 24 Jul 14 05:23:28 PM PDT 24 38501967 ps
T947 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1215834182 Jul 14 05:23:18 PM PDT 24 Jul 14 05:23:21 PM PDT 24 80741192 ps
T948 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1667466470 Jul 14 05:23:18 PM PDT 24 Jul 14 05:23:21 PM PDT 24 19484212 ps
T949 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3862554217 Jul 14 05:23:19 PM PDT 24 Jul 14 05:23:21 PM PDT 24 39034636 ps
T950 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.467429157 Jul 14 05:22:34 PM PDT 24 Jul 14 05:22:36 PM PDT 24 40967822 ps
T951 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3246892049 Jul 14 05:23:15 PM PDT 24 Jul 14 05:23:19 PM PDT 24 183193335 ps
T952 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.895557810 Jul 14 05:22:41 PM PDT 24 Jul 14 05:22:59 PM PDT 24 1380501579 ps
T953 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2736884170 Jul 14 05:22:37 PM PDT 24 Jul 14 05:22:40 PM PDT 24 57281514 ps
T954 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.648050127 Jul 14 05:23:08 PM PDT 24 Jul 14 05:23:13 PM PDT 24 330422196 ps
T955 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.82481567 Jul 14 05:23:31 PM PDT 24 Jul 14 05:23:33 PM PDT 24 67264010 ps
T956 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2965087499 Jul 14 05:22:37 PM PDT 24 Jul 14 05:22:39 PM PDT 24 21836033 ps
T957 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.72772213 Jul 14 05:22:46 PM PDT 24 Jul 14 05:22:47 PM PDT 24 15861783 ps
T958 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.772503280 Jul 14 05:23:15 PM PDT 24 Jul 14 05:23:21 PM PDT 24 1834235159 ps
T959 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1722279027 Jul 14 05:23:08 PM PDT 24 Jul 14 05:23:24 PM PDT 24 2569018626 ps
T960 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1176272478 Jul 14 05:22:36 PM PDT 24 Jul 14 05:22:41 PM PDT 24 1120527006 ps
T961 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1205752661 Jul 14 05:22:40 PM PDT 24 Jul 14 05:22:42 PM PDT 24 203754470 ps
T129 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3813087460 Jul 14 05:23:17 PM PDT 24 Jul 14 05:23:21 PM PDT 24 351341124 ps
T195 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2681780069 Jul 14 05:22:58 PM PDT 24 Jul 14 05:23:00 PM PDT 24 10952768 ps
T962 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2189779383 Jul 14 05:23:01 PM PDT 24 Jul 14 05:23:05 PM PDT 24 477518945 ps
T963 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3903721953 Jul 14 05:22:51 PM PDT 24 Jul 14 05:22:52 PM PDT 24 17593353 ps
T964 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2999143092 Jul 14 05:23:04 PM PDT 24 Jul 14 05:23:06 PM PDT 24 226110611 ps
T965 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3368919185 Jul 14 05:23:09 PM PDT 24 Jul 14 05:23:11 PM PDT 24 16810315 ps
T966 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.604670854 Jul 14 05:23:19 PM PDT 24 Jul 14 05:23:24 PM PDT 24 130922145 ps
T967 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3547611706 Jul 14 05:23:34 PM PDT 24 Jul 14 05:23:35 PM PDT 24 27356456 ps
T968 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3346859529 Jul 14 05:22:36 PM PDT 24 Jul 14 05:22:45 PM PDT 24 374440855 ps
T969 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.190136133 Jul 14 05:23:30 PM PDT 24 Jul 14 05:23:33 PM PDT 24 37437562 ps
T970 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.521017437 Jul 14 05:23:08 PM PDT 24 Jul 14 05:23:25 PM PDT 24 1455152543 ps
T971 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.211244457 Jul 14 05:23:00 PM PDT 24 Jul 14 05:23:03 PM PDT 24 149194608 ps
T972 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2198311066 Jul 14 05:23:20 PM PDT 24 Jul 14 05:23:22 PM PDT 24 70284430 ps
T973 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3518197154 Jul 14 05:22:57 PM PDT 24 Jul 14 05:22:59 PM PDT 24 154310430 ps
T974 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2179647689 Jul 14 05:23:18 PM PDT 24 Jul 14 05:23:21 PM PDT 24 22514630 ps
T975 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.464911951 Jul 14 05:23:00 PM PDT 24 Jul 14 05:23:03 PM PDT 24 22524106 ps
T120 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3230957924 Jul 14 05:23:25 PM PDT 24 Jul 14 05:23:29 PM PDT 24 76894722 ps
T976 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2432128022 Jul 14 05:22:48 PM PDT 24 Jul 14 05:22:50 PM PDT 24 43525906 ps
T977 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3799808354 Jul 14 05:23:15 PM PDT 24 Jul 14 05:23:17 PM PDT 24 248111208 ps
T978 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1812285428 Jul 14 05:23:16 PM PDT 24 Jul 14 05:23:18 PM PDT 24 213232870 ps
T979 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.530541844 Jul 14 05:22:55 PM PDT 24 Jul 14 05:22:57 PM PDT 24 52624548 ps
T980 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3998394002 Jul 14 05:22:42 PM PDT 24 Jul 14 05:22:44 PM PDT 24 87006112 ps
T981 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2721118611 Jul 14 05:22:38 PM PDT 24 Jul 14 05:22:40 PM PDT 24 23739257 ps
T982 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1358499451 Jul 14 05:23:22 PM PDT 24 Jul 14 05:23:27 PM PDT 24 1558410619 ps

Test location /workspace/coverage/default/8.lc_ctrl_errors.3298971291
Short name T8
Test name
Test status
Simulation time 361049479 ps
CPU time 15.97 seconds
Started Jul 14 05:28:11 PM PDT 24
Finished Jul 14 05:28:27 PM PDT 24
Peak memory 217716 kb
Host smart-e2190b16-ef78-4d32-aaf5-21c226ed5f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298971291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3298971291
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.3504366105
Short name T18
Test name
Test status
Simulation time 13553408678 ps
CPU time 187 seconds
Started Jul 14 05:30:16 PM PDT 24
Finished Jul 14 05:33:24 PM PDT 24
Peak memory 282548 kb
Host smart-619e1d81-e9c7-471f-9a9d-d27ed8abb483
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3504366105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.3504366105
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1558685861
Short name T210
Test name
Test status
Simulation time 494224783 ps
CPU time 11.78 seconds
Started Jul 14 05:29:45 PM PDT 24
Finished Jul 14 05:29:57 PM PDT 24
Peak memory 217756 kb
Host smart-a92974c6-27aa-4be4-8369-6b0f47d94954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558685861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1558685861
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3830260788
Short name T273
Test name
Test status
Simulation time 675792881 ps
CPU time 11.6 seconds
Started Jul 14 05:30:50 PM PDT 24
Finished Jul 14 05:31:04 PM PDT 24
Peak memory 218404 kb
Host smart-00fd57d9-f553-4e44-9f99-2294a3c2b1b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830260788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3830260788
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2125557140
Short name T7
Test name
Test status
Simulation time 33016753 ps
CPU time 0.86 seconds
Started Jul 14 05:30:16 PM PDT 24
Finished Jul 14 05:30:18 PM PDT 24
Peak memory 208264 kb
Host smart-4c5671d6-4bc8-49cf-9afe-2519f9773c20
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125557140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2125557140
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.692622527
Short name T108
Test name
Test status
Simulation time 39545358 ps
CPU time 1.95 seconds
Started Jul 14 05:23:21 PM PDT 24
Finished Jul 14 05:23:24 PM PDT 24
Peak memory 224472 kb
Host smart-0db4f273-3639-4d35-be73-aa2ac33c54ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692622527 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.692622527
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3739061775
Short name T42
Test name
Test status
Simulation time 192509094261 ps
CPU time 1721.09 seconds
Started Jul 14 05:31:18 PM PDT 24
Finished Jul 14 05:59:59 PM PDT 24
Peak memory 660284 kb
Host smart-f4b7ffcb-5112-4177-be3d-7e67250b2e76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3739061775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.3739061775
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2618639513
Short name T11
Test name
Test status
Simulation time 710077023 ps
CPU time 10.67 seconds
Started Jul 14 05:29:58 PM PDT 24
Finished Jul 14 05:30:09 PM PDT 24
Peak memory 217724 kb
Host smart-93b0d39c-acea-48c0-9698-7fa20d59ee2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618639513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2618639513
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.388244398
Short name T49
Test name
Test status
Simulation time 800639701 ps
CPU time 38.87 seconds
Started Jul 14 05:27:20 PM PDT 24
Finished Jul 14 05:27:59 PM PDT 24
Peak memory 269620 kb
Host smart-83bcf508-b52b-4961-af0e-878c7e225b75
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388244398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.388244398
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2988818592
Short name T151
Test name
Test status
Simulation time 398112985 ps
CPU time 11.6 seconds
Started Jul 14 05:29:13 PM PDT 24
Finished Jul 14 05:29:25 PM PDT 24
Peak memory 225520 kb
Host smart-3715eba5-fc8f-4deb-a210-a167bb1324a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988818592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2988818592
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.684928877
Short name T19
Test name
Test status
Simulation time 1049160076 ps
CPU time 5.88 seconds
Started Jul 14 05:29:41 PM PDT 24
Finished Jul 14 05:29:48 PM PDT 24
Peak memory 217140 kb
Host smart-23658f71-f5d2-4b4b-8d50-0717bc5be69b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684928877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.684928877
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1241619749
Short name T103
Test name
Test status
Simulation time 239450428 ps
CPU time 2.09 seconds
Started Jul 14 05:23:18 PM PDT 24
Finished Jul 14 05:23:22 PM PDT 24
Peak memory 221996 kb
Host smart-fa28780d-d69a-416e-bc92-807c5f891422
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241619749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1241619749
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2296225298
Short name T88
Test name
Test status
Simulation time 99922970 ps
CPU time 1.04 seconds
Started Jul 14 05:28:49 PM PDT 24
Finished Jul 14 05:28:51 PM PDT 24
Peak memory 208460 kb
Host smart-929892cb-9ad9-4a3d-a95f-203f56d22e94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296225298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2296225298
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1664667983
Short name T188
Test name
Test status
Simulation time 69353090 ps
CPU time 1.05 seconds
Started Jul 14 05:22:35 PM PDT 24
Finished Jul 14 05:22:37 PM PDT 24
Peak memory 211484 kb
Host smart-78022e69-4790-4f23-a0a0-62b8f47752b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664667983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1664667983
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2804189835
Short name T111
Test name
Test status
Simulation time 575351799 ps
CPU time 1.46 seconds
Started Jul 14 05:22:41 PM PDT 24
Finished Jul 14 05:22:43 PM PDT 24
Peak memory 217192 kb
Host smart-79668983-cb45-4d42-9e20-01482137cfa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804189835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2804189835
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3363860233
Short name T9
Test name
Test status
Simulation time 929792056 ps
CPU time 6.46 seconds
Started Jul 14 05:28:02 PM PDT 24
Finished Jul 14 05:28:10 PM PDT 24
Peak memory 224200 kb
Host smart-d7d5b08b-0b89-48aa-b4c9-d256cfc9e0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363860233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3363860233
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3293927860
Short name T113
Test name
Test status
Simulation time 775155255 ps
CPU time 3.71 seconds
Started Jul 14 05:22:38 PM PDT 24
Finished Jul 14 05:22:42 PM PDT 24
Peak memory 217560 kb
Host smart-8572f525-4133-4051-a2d3-38eec39cf4ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329392
7860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3293927860
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.167912927
Short name T99
Test name
Test status
Simulation time 26463774293 ps
CPU time 656.58 seconds
Started Jul 14 05:30:40 PM PDT 24
Finished Jul 14 05:41:37 PM PDT 24
Peak memory 496308 kb
Host smart-18dccffa-7f3d-48a2-a39a-1be6479cbfa3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=167912927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.167912927
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.309149762
Short name T124
Test name
Test status
Simulation time 119318077 ps
CPU time 4.44 seconds
Started Jul 14 05:23:07 PM PDT 24
Finished Jul 14 05:23:12 PM PDT 24
Peak memory 217348 kb
Host smart-67060caf-5f37-4733-8ef2-a9f2f7d2acd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309149762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.309149762
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3813087460
Short name T129
Test name
Test status
Simulation time 351341124 ps
CPU time 3.39 seconds
Started Jul 14 05:23:17 PM PDT 24
Finished Jul 14 05:23:21 PM PDT 24
Peak memory 221868 kb
Host smart-630d400d-b3c0-4302-bcbf-410091ad9d98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813087460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3813087460
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.4037763074
Short name T277
Test name
Test status
Simulation time 31582948 ps
CPU time 0.74 seconds
Started Jul 14 05:28:39 PM PDT 24
Finished Jul 14 05:28:40 PM PDT 24
Peak memory 208184 kb
Host smart-4273ed17-8b62-4a9c-9e23-1297b9614c92
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037763074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.4037763074
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3230957924
Short name T120
Test name
Test status
Simulation time 76894722 ps
CPU time 3.55 seconds
Started Jul 14 05:23:25 PM PDT 24
Finished Jul 14 05:23:29 PM PDT 24
Peak memory 213024 kb
Host smart-2e1a9867-7421-4278-862c-2e358361da88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230957924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3230957924
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2162585269
Short name T32
Test name
Test status
Simulation time 276489608 ps
CPU time 11.27 seconds
Started Jul 14 05:30:09 PM PDT 24
Finished Jul 14 05:30:21 PM PDT 24
Peak memory 217636 kb
Host smart-6b1aec14-11c1-4767-b313-7796ac8bf969
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162585269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2162585269
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2601386151
Short name T105
Test name
Test status
Simulation time 300062720 ps
CPU time 3.81 seconds
Started Jul 14 05:23:26 PM PDT 24
Finished Jul 14 05:23:31 PM PDT 24
Peak memory 221872 kb
Host smart-51ee3080-91da-4f23-85da-939e35884161
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601386151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2601386151
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3827964752
Short name T110
Test name
Test status
Simulation time 204790717 ps
CPU time 1.4 seconds
Started Jul 14 05:22:42 PM PDT 24
Finished Jul 14 05:22:44 PM PDT 24
Peak memory 209236 kb
Host smart-b6f4d04f-2aa7-4596-ad08-659482896ac1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827964752 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3827964752
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1984313518
Short name T56
Test name
Test status
Simulation time 1749214858 ps
CPU time 60.13 seconds
Started Jul 14 05:29:02 PM PDT 24
Finished Jul 14 05:30:03 PM PDT 24
Peak memory 271676 kb
Host smart-4673f6cd-946c-4f32-b827-0e68ec60bf14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984313518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1984313518
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3158118124
Short name T46
Test name
Test status
Simulation time 348145664 ps
CPU time 12.98 seconds
Started Jul 14 05:30:00 PM PDT 24
Finished Jul 14 05:30:14 PM PDT 24
Peak memory 217792 kb
Host smart-8f74b349-0313-4252-832a-20608d1ab761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158118124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3158118124
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4288744838
Short name T127
Test name
Test status
Simulation time 223173147 ps
CPU time 4 seconds
Started Jul 14 05:23:02 PM PDT 24
Finished Jul 14 05:23:07 PM PDT 24
Peak memory 217380 kb
Host smart-6737b79b-5851-4eb1-850a-d5b9051da3f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288744838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.4288744838
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.91262170
Short name T119
Test name
Test status
Simulation time 1135470516 ps
CPU time 4.34 seconds
Started Jul 14 05:23:03 PM PDT 24
Finished Jul 14 05:23:09 PM PDT 24
Peak memory 217420 kb
Host smart-26ec46d5-bc07-4409-8266-2e54e44ed45f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91262170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_er
r.91262170
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1875754471
Short name T213
Test name
Test status
Simulation time 279617419 ps
CPU time 10.51 seconds
Started Jul 14 05:27:19 PM PDT 24
Finished Jul 14 05:27:30 PM PDT 24
Peak memory 217668 kb
Host smart-80e155ba-e4c8-4db9-9596-075f17651a40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875754471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1875754471
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1820405065
Short name T205
Test name
Test status
Simulation time 30959489 ps
CPU time 0.89 seconds
Started Jul 14 05:27:25 PM PDT 24
Finished Jul 14 05:27:27 PM PDT 24
Peak memory 208376 kb
Host smart-70712c56-e557-4575-93f5-9519313b91ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820405065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1820405065
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2892498941
Short name T206
Test name
Test status
Simulation time 38580134 ps
CPU time 0.83 seconds
Started Jul 14 05:27:55 PM PDT 24
Finished Jul 14 05:27:57 PM PDT 24
Peak memory 208448 kb
Host smart-e6d9e903-8d5a-4b44-8629-cead397acec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892498941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2892498941
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.4159972276
Short name T208
Test name
Test status
Simulation time 48754418 ps
CPU time 0.84 seconds
Started Jul 14 05:28:08 PM PDT 24
Finished Jul 14 05:28:10 PM PDT 24
Peak memory 208404 kb
Host smart-959dce41-98d4-4472-9246-03778cb0441a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159972276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.4159972276
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3292214027
Short name T65
Test name
Test status
Simulation time 13833313 ps
CPU time 0.84 seconds
Started Jul 14 05:28:22 PM PDT 24
Finished Jul 14 05:28:24 PM PDT 24
Peak memory 208336 kb
Host smart-b9f188e9-1d9a-4806-93b7-1f8303f79060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292214027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3292214027
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3962745353
Short name T1
Test name
Test status
Simulation time 230228852 ps
CPU time 2.65 seconds
Started Jul 14 05:29:39 PM PDT 24
Finished Jul 14 05:29:42 PM PDT 24
Peak memory 213716 kb
Host smart-233d81d2-50d6-4fb9-b8e1-7c121b7ba0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962745353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3962745353
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3208751861
Short name T122
Test name
Test status
Simulation time 264269066 ps
CPU time 2.17 seconds
Started Jul 14 05:22:37 PM PDT 24
Finished Jul 14 05:22:40 PM PDT 24
Peak memory 221560 kb
Host smart-81e112f6-da7c-406a-b38a-e18e781bd445
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208751861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3208751861
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.418204901
Short name T922
Test name
Test status
Simulation time 121751511 ps
CPU time 3.45 seconds
Started Jul 14 05:22:40 PM PDT 24
Finished Jul 14 05:22:44 PM PDT 24
Peak memory 217848 kb
Host smart-f54dfa67-6afd-4bfc-a5fc-85d3b63e975c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418204901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.418204901
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.4129722345
Short name T107
Test name
Test status
Simulation time 104713555 ps
CPU time 2.94 seconds
Started Jul 14 05:23:20 PM PDT 24
Finished Jul 14 05:23:23 PM PDT 24
Peak memory 221788 kb
Host smart-356e1c46-e8df-46ab-bf8b-f6c8a9838c10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129722345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.4129722345
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1554622916
Short name T131
Test name
Test status
Simulation time 113918388 ps
CPU time 4.37 seconds
Started Jul 14 05:23:21 PM PDT 24
Finished Jul 14 05:23:27 PM PDT 24
Peak memory 217360 kb
Host smart-c6016fbf-4a3b-4b87-b00c-83ff2563f002
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554622916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1554622916
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.1165359480
Short name T43
Test name
Test status
Simulation time 239129434 ps
CPU time 11.69 seconds
Started Jul 14 05:28:34 PM PDT 24
Finished Jul 14 05:28:46 PM PDT 24
Peak memory 217644 kb
Host smart-35d22820-316a-43b8-a7a2-220b090c0bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165359480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1165359480
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.968345287
Short name T895
Test name
Test status
Simulation time 117181138 ps
CPU time 0.99 seconds
Started Jul 14 05:22:37 PM PDT 24
Finished Jul 14 05:22:38 PM PDT 24
Peak memory 209240 kb
Host smart-fb14f601-68d8-433b-a7d4-7ce20e7785e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968345287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.968345287
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2965087499
Short name T956
Test name
Test status
Simulation time 21836033 ps
CPU time 1.44 seconds
Started Jul 14 05:22:37 PM PDT 24
Finished Jul 14 05:22:39 PM PDT 24
Peak memory 209268 kb
Host smart-a8a09e92-c851-4680-b044-6c81aacbc96a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965087499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2965087499
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2721118611
Short name T981
Test name
Test status
Simulation time 23739257 ps
CPU time 1.48 seconds
Started Jul 14 05:22:38 PM PDT 24
Finished Jul 14 05:22:40 PM PDT 24
Peak memory 219072 kb
Host smart-1aed119b-8e2e-4342-b490-bc903edd3c70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721118611 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2721118611
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3089911354
Short name T918
Test name
Test status
Simulation time 68210648 ps
CPU time 1.16 seconds
Started Jul 14 05:22:36 PM PDT 24
Finished Jul 14 05:22:38 PM PDT 24
Peak memory 209140 kb
Host smart-7651a8ad-ffc9-452c-8adf-5d0bcbcdd6bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089911354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3089911354
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3112875029
Short name T865
Test name
Test status
Simulation time 92475171 ps
CPU time 1.44 seconds
Started Jul 14 05:22:35 PM PDT 24
Finished Jul 14 05:22:37 PM PDT 24
Peak memory 208968 kb
Host smart-fe571b87-45ca-4ae6-aef2-09f5477f17ba
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112875029 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3112875029
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.420711287
Short name T924
Test name
Test status
Simulation time 5831734991 ps
CPU time 15.29 seconds
Started Jul 14 05:22:35 PM PDT 24
Finished Jul 14 05:22:51 PM PDT 24
Peak memory 209132 kb
Host smart-be0dd425-fb87-4e29-82f8-dca3b159d2ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420711287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.420711287
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1176272478
Short name T960
Test name
Test status
Simulation time 1120527006 ps
CPU time 4.77 seconds
Started Jul 14 05:22:36 PM PDT 24
Finished Jul 14 05:22:41 PM PDT 24
Peak memory 208604 kb
Host smart-80846d31-64e1-46ca-b6e1-a1989aec2540
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176272478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1176272478
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3743396079
Short name T921
Test name
Test status
Simulation time 47794856 ps
CPU time 1.8 seconds
Started Jul 14 05:22:35 PM PDT 24
Finished Jul 14 05:22:38 PM PDT 24
Peak memory 210528 kb
Host smart-1e552628-0a85-4cce-a2ec-ea4f2cee6eed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743396079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3743396079
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3650382973
Short name T878
Test name
Test status
Simulation time 624967227 ps
CPU time 4.38 seconds
Started Jul 14 05:22:35 PM PDT 24
Finished Jul 14 05:22:40 PM PDT 24
Peak memory 219080 kb
Host smart-09da9370-f538-4070-8216-99860d457cf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365038
2973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3650382973
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.964418321
Short name T914
Test name
Test status
Simulation time 723981940 ps
CPU time 4.42 seconds
Started Jul 14 05:22:35 PM PDT 24
Finished Jul 14 05:22:39 PM PDT 24
Peak memory 217232 kb
Host smart-38e0498c-f2ae-4ef7-a8e0-e82db111d2d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964418321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.964418321
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.4186781443
Short name T870
Test name
Test status
Simulation time 21818969 ps
CPU time 1.27 seconds
Started Jul 14 05:22:42 PM PDT 24
Finished Jul 14 05:22:44 PM PDT 24
Peak memory 209236 kb
Host smart-6aceb07e-9985-42bd-b4f8-a3275afee584
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186781443 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.4186781443
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.467429157
Short name T950
Test name
Test status
Simulation time 40967822 ps
CPU time 1.24 seconds
Started Jul 14 05:22:34 PM PDT 24
Finished Jul 14 05:22:36 PM PDT 24
Peak memory 217488 kb
Host smart-af1f1bf4-eca2-469e-a4de-dfb03d3c1ff4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467429157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
same_csr_outstanding.467429157
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2736884170
Short name T953
Test name
Test status
Simulation time 57281514 ps
CPU time 2.38 seconds
Started Jul 14 05:22:37 PM PDT 24
Finished Jul 14 05:22:40 PM PDT 24
Peak memory 217352 kb
Host smart-df41a6f9-023a-4693-91aa-1c64f3c23efb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736884170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2736884170
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3601145940
Short name T189
Test name
Test status
Simulation time 114866103 ps
CPU time 1.3 seconds
Started Jul 14 05:22:41 PM PDT 24
Finished Jul 14 05:22:43 PM PDT 24
Peak memory 209148 kb
Host smart-bf2e9c0d-e90e-4f1e-abb5-c6e507b469f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601145940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3601145940
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1163070458
Short name T863
Test name
Test status
Simulation time 244699645 ps
CPU time 1.76 seconds
Started Jul 14 05:22:42 PM PDT 24
Finished Jul 14 05:22:45 PM PDT 24
Peak memory 209132 kb
Host smart-dc4160d4-360a-487f-aa56-dfb864435e6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163070458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1163070458
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1899274377
Short name T894
Test name
Test status
Simulation time 42240351 ps
CPU time 1.03 seconds
Started Jul 14 05:22:41 PM PDT 24
Finished Jul 14 05:22:43 PM PDT 24
Peak memory 209712 kb
Host smart-557d00f8-2811-4db9-81f5-81b99493cf68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899274377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1899274377
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3998394002
Short name T980
Test name
Test status
Simulation time 87006112 ps
CPU time 1.38 seconds
Started Jul 14 05:22:42 PM PDT 24
Finished Jul 14 05:22:44 PM PDT 24
Peak memory 219356 kb
Host smart-f34bf02a-0ec6-483b-9501-3f579d33692f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998394002 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3998394002
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.72772213
Short name T957
Test name
Test status
Simulation time 15861783 ps
CPU time 1.1 seconds
Started Jul 14 05:22:46 PM PDT 24
Finished Jul 14 05:22:47 PM PDT 24
Peak memory 209028 kb
Host smart-4b933040-da57-40f7-9d84-8f1e010ae036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72772213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.72772213
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1205752661
Short name T961
Test name
Test status
Simulation time 203754470 ps
CPU time 1.43 seconds
Started Jul 14 05:22:40 PM PDT 24
Finished Jul 14 05:22:42 PM PDT 24
Peak memory 208652 kb
Host smart-2d903213-8efd-4fd4-804c-f0b3f8962538
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205752661 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1205752661
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3346859529
Short name T968
Test name
Test status
Simulation time 374440855 ps
CPU time 8.54 seconds
Started Jul 14 05:22:36 PM PDT 24
Finished Jul 14 05:22:45 PM PDT 24
Peak memory 209076 kb
Host smart-31eba8ed-ea08-4ada-a5e8-05b83b37d2f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346859529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3346859529
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.895557810
Short name T952
Test name
Test status
Simulation time 1380501579 ps
CPU time 17.46 seconds
Started Jul 14 05:22:41 PM PDT 24
Finished Jul 14 05:22:59 PM PDT 24
Peak memory 209112 kb
Host smart-1dba36ef-44e5-46c1-86c3-7bd088f8f8eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895557810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.895557810
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3775501860
Short name T116
Test name
Test status
Simulation time 95497887 ps
CPU time 3.12 seconds
Started Jul 14 05:22:36 PM PDT 24
Finished Jul 14 05:22:40 PM PDT 24
Peak memory 217368 kb
Host smart-53960eef-8b0e-46c3-a463-0ef74c7346e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775501860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3775501860
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.147499281
Short name T881
Test name
Test status
Simulation time 248043742 ps
CPU time 1.49 seconds
Started Jul 14 05:22:45 PM PDT 24
Finished Jul 14 05:22:47 PM PDT 24
Peak memory 209188 kb
Host smart-c3df2e66-86ee-4b6a-98b7-73f6a1c539f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147499281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.147499281
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2406211249
Short name T128
Test name
Test status
Simulation time 244977962 ps
CPU time 1.95 seconds
Started Jul 14 05:22:42 PM PDT 24
Finished Jul 14 05:22:44 PM PDT 24
Peak memory 221976 kb
Host smart-8c5f4c52-3f18-428a-ab21-85f59a49ca1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406211249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2406211249
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.247324171
Short name T946
Test name
Test status
Simulation time 38501967 ps
CPU time 1.35 seconds
Started Jul 14 05:23:26 PM PDT 24
Finished Jul 14 05:23:28 PM PDT 24
Peak memory 217388 kb
Host smart-d5e0d3e7-dcda-4635-b7fe-2a93744eaf0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247324171 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.247324171
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3980230097
Short name T187
Test name
Test status
Simulation time 184995582 ps
CPU time 1.01 seconds
Started Jul 14 05:23:21 PM PDT 24
Finished Jul 14 05:23:23 PM PDT 24
Peak memory 209048 kb
Host smart-9a63cdce-6010-4aaf-8f37-4d5afe50911a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980230097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3980230097
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2217228296
Short name T198
Test name
Test status
Simulation time 30621502 ps
CPU time 1.54 seconds
Started Jul 14 05:23:22 PM PDT 24
Finished Jul 14 05:23:24 PM PDT 24
Peak memory 209136 kb
Host smart-86c6c427-023f-46d9-8334-f4a5130b474d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217228296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2217228296
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1215834182
Short name T947
Test name
Test status
Simulation time 80741192 ps
CPU time 2.26 seconds
Started Jul 14 05:23:18 PM PDT 24
Finished Jul 14 05:23:21 PM PDT 24
Peak memory 217948 kb
Host smart-61d43fe6-65ba-402f-bb19-999654428bcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215834182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1215834182
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.110932509
Short name T161
Test name
Test status
Simulation time 29670617 ps
CPU time 1.02 seconds
Started Jul 14 05:23:22 PM PDT 24
Finished Jul 14 05:23:24 PM PDT 24
Peak memory 219128 kb
Host smart-522ac581-ef08-41eb-aa91-f945c4461e49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110932509 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.110932509
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3862554217
Short name T949
Test name
Test status
Simulation time 39034636 ps
CPU time 0.83 seconds
Started Jul 14 05:23:19 PM PDT 24
Finished Jul 14 05:23:21 PM PDT 24
Peak memory 209164 kb
Host smart-23711fad-4741-4c33-a853-181b97084df8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862554217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3862554217
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2076998439
Short name T915
Test name
Test status
Simulation time 168557367 ps
CPU time 1.47 seconds
Started Jul 14 05:23:21 PM PDT 24
Finished Jul 14 05:23:23 PM PDT 24
Peak memory 217376 kb
Host smart-703f4fad-45f9-40a0-960b-aa119fa72905
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076998439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.2076998439
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.604670854
Short name T966
Test name
Test status
Simulation time 130922145 ps
CPU time 3.3 seconds
Started Jul 14 05:23:19 PM PDT 24
Finished Jul 14 05:23:24 PM PDT 24
Peak memory 217376 kb
Host smart-a439a8ab-f335-43f4-8f42-48b77e33e335
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604670854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.604670854
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2179647689
Short name T974
Test name
Test status
Simulation time 22514630 ps
CPU time 0.97 seconds
Started Jul 14 05:23:18 PM PDT 24
Finished Jul 14 05:23:21 PM PDT 24
Peak memory 209272 kb
Host smart-af8e0d4a-af32-425b-8e87-bc53609c7b80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179647689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2179647689
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.595272083
Short name T880
Test name
Test status
Simulation time 51891204 ps
CPU time 2.18 seconds
Started Jul 14 05:23:19 PM PDT 24
Finished Jul 14 05:23:23 PM PDT 24
Peak memory 217440 kb
Host smart-20ce360a-cb22-4dc8-95ad-2abeb844c280
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595272083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.595272083
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3372310046
Short name T115
Test name
Test status
Simulation time 156921925 ps
CPU time 3.02 seconds
Started Jul 14 05:23:18 PM PDT 24
Finished Jul 14 05:23:22 PM PDT 24
Peak memory 218132 kb
Host smart-21e89357-53c8-4888-b261-479d13ef87b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372310046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3372310046
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.946591509
Short name T118
Test name
Test status
Simulation time 76823434 ps
CPU time 3.64 seconds
Started Jul 14 05:23:26 PM PDT 24
Finished Jul 14 05:23:31 PM PDT 24
Peak memory 213040 kb
Host smart-c7146fb6-1c57-4107-bb9c-8a91a765f0bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946591509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.946591509
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.367335360
Short name T925
Test name
Test status
Simulation time 123022244 ps
CPU time 1.56 seconds
Started Jul 14 05:23:21 PM PDT 24
Finished Jul 14 05:23:24 PM PDT 24
Peak memory 223808 kb
Host smart-88618f0a-88f5-42e1-8106-0000de8b6aa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367335360 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.367335360
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.878799008
Short name T876
Test name
Test status
Simulation time 26295446 ps
CPU time 0.82 seconds
Started Jul 14 05:23:23 PM PDT 24
Finished Jul 14 05:23:24 PM PDT 24
Peak memory 208712 kb
Host smart-3f92f6b4-e440-4072-a662-a63d6bb4ec57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878799008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.878799008
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2877428340
Short name T935
Test name
Test status
Simulation time 109242473 ps
CPU time 1.04 seconds
Started Jul 14 05:23:24 PM PDT 24
Finished Jul 14 05:23:26 PM PDT 24
Peak memory 217236 kb
Host smart-ee181178-24ba-4bd3-ae9b-24cfffad1698
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877428340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2877428340
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1510389371
Short name T892
Test name
Test status
Simulation time 656236014 ps
CPU time 3.6 seconds
Started Jul 14 05:23:20 PM PDT 24
Finished Jul 14 05:23:24 PM PDT 24
Peak memory 217432 kb
Host smart-edcf7eb3-449c-45e8-8691-1fbfdd66dfab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510389371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1510389371
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2127636046
Short name T135
Test name
Test status
Simulation time 42298441 ps
CPU time 1.83 seconds
Started Jul 14 05:23:19 PM PDT 24
Finished Jul 14 05:23:22 PM PDT 24
Peak memory 221720 kb
Host smart-b7994166-2580-4f83-85f2-29bdbe34d443
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127636046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2127636046
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1667466470
Short name T948
Test name
Test status
Simulation time 19484212 ps
CPU time 1.4 seconds
Started Jul 14 05:23:18 PM PDT 24
Finished Jul 14 05:23:21 PM PDT 24
Peak memory 217472 kb
Host smart-eaee133e-814d-4727-b085-4a4aae843429
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667466470 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1667466470
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2588738443
Short name T147
Test name
Test status
Simulation time 16090526 ps
CPU time 0.95 seconds
Started Jul 14 05:23:26 PM PDT 24
Finished Jul 14 05:23:28 PM PDT 24
Peak memory 209092 kb
Host smart-74b60ce7-babe-4737-a5c1-d02e075dc363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588738443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2588738443
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2198311066
Short name T972
Test name
Test status
Simulation time 70284430 ps
CPU time 1.21 seconds
Started Jul 14 05:23:20 PM PDT 24
Finished Jul 14 05:23:22 PM PDT 24
Peak memory 209212 kb
Host smart-76731535-5aad-44f2-bdfe-0f7456281fed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198311066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2198311066
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3154256724
Short name T114
Test name
Test status
Simulation time 76487774 ps
CPU time 2.38 seconds
Started Jul 14 05:23:19 PM PDT 24
Finished Jul 14 05:23:23 PM PDT 24
Peak memory 217676 kb
Host smart-eb863682-6851-44d5-a659-617a76c0bc5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154256724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3154256724
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.288679731
Short name T136
Test name
Test status
Simulation time 88742588 ps
CPU time 2.81 seconds
Started Jul 14 05:23:19 PM PDT 24
Finished Jul 14 05:23:23 PM PDT 24
Peak memory 222100 kb
Host smart-dce05668-b5e1-49b9-aca4-73408d8e914a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288679731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.288679731
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1061290883
Short name T904
Test name
Test status
Simulation time 267998199 ps
CPU time 1.62 seconds
Started Jul 14 05:23:34 PM PDT 24
Finished Jul 14 05:23:36 PM PDT 24
Peak memory 217720 kb
Host smart-ee26df70-4b4d-4638-ad93-377f5088e546
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061290883 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1061290883
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.512140315
Short name T886
Test name
Test status
Simulation time 48965657 ps
CPU time 1.13 seconds
Started Jul 14 05:23:24 PM PDT 24
Finished Jul 14 05:23:26 PM PDT 24
Peak memory 209144 kb
Host smart-93a1cddc-d403-4c86-97c5-05aa44830baf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512140315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.512140315
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1384398653
Short name T201
Test name
Test status
Simulation time 87401779 ps
CPU time 1.12 seconds
Started Jul 14 05:23:26 PM PDT 24
Finished Jul 14 05:23:28 PM PDT 24
Peak memory 217360 kb
Host smart-140d9509-0151-49b6-b3b2-c8f267492e26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384398653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1384398653
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1358499451
Short name T982
Test name
Test status
Simulation time 1558410619 ps
CPU time 4.31 seconds
Started Jul 14 05:23:22 PM PDT 24
Finished Jul 14 05:23:27 PM PDT 24
Peak memory 218000 kb
Host smart-246c6f88-2b29-48e9-bc2f-6aebcba285ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358499451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1358499451
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.294218717
Short name T171
Test name
Test status
Simulation time 47402950 ps
CPU time 1.53 seconds
Started Jul 14 05:23:26 PM PDT 24
Finished Jul 14 05:23:28 PM PDT 24
Peak memory 217504 kb
Host smart-c7ef29d5-6ff8-406c-a896-20fe13e01309
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294218717 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.294218717
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2971278860
Short name T941
Test name
Test status
Simulation time 27867505 ps
CPU time 0.84 seconds
Started Jul 14 05:23:28 PM PDT 24
Finished Jul 14 05:23:30 PM PDT 24
Peak memory 209080 kb
Host smart-6da6407d-299e-4f16-b862-171599439985
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971278860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2971278860
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2196617876
Short name T199
Test name
Test status
Simulation time 30207288 ps
CPU time 1.13 seconds
Started Jul 14 05:23:26 PM PDT 24
Finished Jul 14 05:23:28 PM PDT 24
Peak memory 209144 kb
Host smart-2b8300a8-0bbc-47ce-bbb2-6430da3d247a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196617876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2196617876
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.4026784700
Short name T923
Test name
Test status
Simulation time 382387710 ps
CPU time 3.05 seconds
Started Jul 14 05:23:27 PM PDT 24
Finished Jul 14 05:23:30 PM PDT 24
Peak memory 217376 kb
Host smart-195d6d28-d1b3-4f55-b808-814f7da607ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026784700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.4026784700
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3085634188
Short name T121
Test name
Test status
Simulation time 249057607 ps
CPU time 2.28 seconds
Started Jul 14 05:23:25 PM PDT 24
Finished Jul 14 05:23:28 PM PDT 24
Peak memory 217436 kb
Host smart-07ec24ac-1092-4f66-b25f-94ef27939113
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085634188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.3085634188
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2905823834
Short name T912
Test name
Test status
Simulation time 32450614 ps
CPU time 1.82 seconds
Started Jul 14 05:23:28 PM PDT 24
Finished Jul 14 05:23:30 PM PDT 24
Peak memory 219068 kb
Host smart-4fa89ba4-c1fc-47cd-8895-af905c8cc220
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905823834 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2905823834
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1525902037
Short name T184
Test name
Test status
Simulation time 20145719 ps
CPU time 1.21 seconds
Started Jul 14 05:23:24 PM PDT 24
Finished Jul 14 05:23:26 PM PDT 24
Peak memory 209204 kb
Host smart-975bc421-5ad1-425c-a660-28de858bcfb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525902037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1525902037
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.966644802
Short name T897
Test name
Test status
Simulation time 22773004 ps
CPU time 1.01 seconds
Started Jul 14 05:23:27 PM PDT 24
Finished Jul 14 05:23:28 PM PDT 24
Peak memory 209220 kb
Host smart-bf87323c-6963-43fe-90dc-a9dd6b5845d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966644802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.966644802
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3839440867
Short name T916
Test name
Test status
Simulation time 75480536 ps
CPU time 2.54 seconds
Started Jul 14 05:23:27 PM PDT 24
Finished Jul 14 05:23:30 PM PDT 24
Peak memory 218456 kb
Host smart-35aaeb47-b0e2-477e-9634-38bed50571a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839440867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3839440867
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.82481567
Short name T955
Test name
Test status
Simulation time 67264010 ps
CPU time 1.1 seconds
Started Jul 14 05:23:31 PM PDT 24
Finished Jul 14 05:23:33 PM PDT 24
Peak memory 218388 kb
Host smart-1e4273f0-548e-49d9-bf3e-ec43d95b9d56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82481567 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.82481567
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1976767429
Short name T194
Test name
Test status
Simulation time 62022408 ps
CPU time 1.03 seconds
Started Jul 14 05:23:35 PM PDT 24
Finished Jul 14 05:23:37 PM PDT 24
Peak memory 209280 kb
Host smart-f23282c7-5bd0-4da1-8a58-103efb39605d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976767429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1976767429
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.301380211
Short name T112
Test name
Test status
Simulation time 36691271 ps
CPU time 1.72 seconds
Started Jul 14 05:23:31 PM PDT 24
Finished Jul 14 05:23:34 PM PDT 24
Peak memory 217288 kb
Host smart-76563c1c-9146-4b57-8920-2d58c364dde1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301380211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.301380211
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1344634165
Short name T104
Test name
Test status
Simulation time 298626661 ps
CPU time 3.37 seconds
Started Jul 14 05:23:25 PM PDT 24
Finished Jul 14 05:23:29 PM PDT 24
Peak memory 217408 kb
Host smart-c3ed015e-d4ef-41ee-a598-0703e5253b02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344634165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1344634165
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.556761500
Short name T930
Test name
Test status
Simulation time 19265736 ps
CPU time 1.09 seconds
Started Jul 14 05:23:30 PM PDT 24
Finished Jul 14 05:23:31 PM PDT 24
Peak memory 217364 kb
Host smart-6b074d20-0878-4300-a114-04ac5f9e7c03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556761500 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.556761500
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.39471501
Short name T196
Test name
Test status
Simulation time 16276951 ps
CPU time 0.96 seconds
Started Jul 14 05:23:31 PM PDT 24
Finished Jul 14 05:23:33 PM PDT 24
Peak memory 208904 kb
Host smart-f23c80ad-d330-46f4-ac73-93e49d1c6014
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39471501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.39471501
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3547611706
Short name T967
Test name
Test status
Simulation time 27356456 ps
CPU time 1.13 seconds
Started Jul 14 05:23:34 PM PDT 24
Finished Jul 14 05:23:35 PM PDT 24
Peak memory 209236 kb
Host smart-4a5887e6-f0a4-4132-b2a7-ae3ee8ed72ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547611706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3547611706
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.190136133
Short name T969
Test name
Test status
Simulation time 37437562 ps
CPU time 2.89 seconds
Started Jul 14 05:23:30 PM PDT 24
Finished Jul 14 05:23:33 PM PDT 24
Peak memory 217436 kb
Host smart-f7c418cd-6700-4b68-a3c0-aa46d4393847
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190136133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.190136133
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2655173173
Short name T133
Test name
Test status
Simulation time 89108839 ps
CPU time 1.9 seconds
Started Jul 14 05:23:30 PM PDT 24
Finished Jul 14 05:23:32 PM PDT 24
Peak memory 221720 kb
Host smart-29104ceb-60a2-43cc-81c9-8fc369291d26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655173173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2655173173
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3015549074
Short name T193
Test name
Test status
Simulation time 39986608 ps
CPU time 0.96 seconds
Started Jul 14 05:22:47 PM PDT 24
Finished Jul 14 05:22:49 PM PDT 24
Peak memory 208872 kb
Host smart-53b1e681-e8e8-475b-96ca-3f507ba69951
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015549074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3015549074
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1513819262
Short name T903
Test name
Test status
Simulation time 187985958 ps
CPU time 2.06 seconds
Started Jul 14 05:22:48 PM PDT 24
Finished Jul 14 05:22:50 PM PDT 24
Peak memory 217148 kb
Host smart-704d1e59-6874-43e9-ac20-581a88fc1301
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513819262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1513819262
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3903721953
Short name T963
Test name
Test status
Simulation time 17593353 ps
CPU time 1.02 seconds
Started Jul 14 05:22:51 PM PDT 24
Finished Jul 14 05:22:52 PM PDT 24
Peak memory 209344 kb
Host smart-000ca8c7-137a-4950-a4fe-45b3593519d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903721953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3903721953
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2266234515
Short name T931
Test name
Test status
Simulation time 51731495 ps
CPU time 0.97 seconds
Started Jul 14 05:22:53 PM PDT 24
Finished Jul 14 05:22:54 PM PDT 24
Peak memory 219392 kb
Host smart-6e931593-4b39-4b51-97e7-fee7e5b746a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266234515 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2266234515
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3681404656
Short name T934
Test name
Test status
Simulation time 23759638 ps
CPU time 0.93 seconds
Started Jul 14 05:22:50 PM PDT 24
Finished Jul 14 05:22:51 PM PDT 24
Peak memory 209132 kb
Host smart-4baa78b7-a25d-443c-ac1e-9973a0716005
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681404656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3681404656
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3204664567
Short name T939
Test name
Test status
Simulation time 62337581 ps
CPU time 1.34 seconds
Started Jul 14 05:22:42 PM PDT 24
Finished Jul 14 05:22:44 PM PDT 24
Peak memory 208960 kb
Host smart-c987dff2-f591-47b5-b817-bec16dc7aa47
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204664567 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3204664567
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4228626007
Short name T860
Test name
Test status
Simulation time 439890087 ps
CPU time 4.87 seconds
Started Jul 14 05:22:40 PM PDT 24
Finished Jul 14 05:22:45 PM PDT 24
Peak memory 208972 kb
Host smart-802ca967-e04b-42b7-986f-491ec21b8a2b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228626007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.4228626007
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1198570207
Short name T942
Test name
Test status
Simulation time 1124329224 ps
CPU time 13.4 seconds
Started Jul 14 05:22:43 PM PDT 24
Finished Jul 14 05:22:57 PM PDT 24
Peak memory 209040 kb
Host smart-ec769bc9-e617-4576-bf0c-fe1c1d7a9b84
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198570207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1198570207
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.920241446
Short name T859
Test name
Test status
Simulation time 239767807 ps
CPU time 1.34 seconds
Started Jul 14 05:22:42 PM PDT 24
Finished Jul 14 05:22:44 PM PDT 24
Peak memory 210564 kb
Host smart-2bc68348-b18d-427a-bb6b-8d5ac36002e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920241446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.920241446
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.833968399
Short name T899
Test name
Test status
Simulation time 385921676 ps
CPU time 3.53 seconds
Started Jul 14 05:22:42 PM PDT 24
Finished Jul 14 05:22:46 PM PDT 24
Peak memory 217244 kb
Host smart-588c0f7e-92c0-4112-b18c-2eb5dfe23604
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833968
399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.833968399
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2306517612
Short name T879
Test name
Test status
Simulation time 133350951 ps
CPU time 1.41 seconds
Started Jul 14 05:22:45 PM PDT 24
Finished Jul 14 05:22:46 PM PDT 24
Peak memory 209192 kb
Host smart-208de10f-377b-49ce-8032-58208fdb3dd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306517612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2306517612
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.62831934
Short name T901
Test name
Test status
Simulation time 54297349 ps
CPU time 1.43 seconds
Started Jul 14 05:22:41 PM PDT 24
Finished Jul 14 05:22:43 PM PDT 24
Peak memory 209184 kb
Host smart-37f572ca-31a3-456c-8fca-667408731900
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62831934 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.62831934
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2432128022
Short name T976
Test name
Test status
Simulation time 43525906 ps
CPU time 0.97 seconds
Started Jul 14 05:22:48 PM PDT 24
Finished Jul 14 05:22:50 PM PDT 24
Peak memory 209208 kb
Host smart-eb611bfb-bbac-478a-9b25-54f827fc5bf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432128022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2432128022
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2776548
Short name T907
Test name
Test status
Simulation time 438501504 ps
CPU time 1.54 seconds
Started Jul 14 05:22:49 PM PDT 24
Finished Jul 14 05:22:51 PM PDT 24
Peak memory 217336 kb
Host smart-a3bc2dae-3432-433b-a887-ebfe3246cf87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2776548
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2857724416
Short name T130
Test name
Test status
Simulation time 163835610 ps
CPU time 1.88 seconds
Started Jul 14 05:22:52 PM PDT 24
Finished Jul 14 05:22:54 PM PDT 24
Peak memory 221776 kb
Host smart-8d9b5a6a-3418-4ba1-b09c-fc92979818bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857724416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2857724416
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.512407055
Short name T868
Test name
Test status
Simulation time 80522096 ps
CPU time 1.06 seconds
Started Jul 14 05:22:54 PM PDT 24
Finished Jul 14 05:22:56 PM PDT 24
Peak memory 209220 kb
Host smart-9d1f8886-7d1f-4589-84ac-ec14be4722f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512407055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.512407055
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.476508510
Short name T117
Test name
Test status
Simulation time 39591297 ps
CPU time 1.16 seconds
Started Jul 14 05:22:54 PM PDT 24
Finished Jul 14 05:22:57 PM PDT 24
Peak memory 208868 kb
Host smart-45f37e3e-1297-4a0a-b400-318bdbf5d598
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476508510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.476508510
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2520482963
Short name T186
Test name
Test status
Simulation time 12350208 ps
CPU time 1 seconds
Started Jul 14 05:22:54 PM PDT 24
Finished Jul 14 05:22:57 PM PDT 24
Peak memory 208988 kb
Host smart-78524eab-d765-4c3f-9909-cb7a2ff6434f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520482963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2520482963
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.530541844
Short name T979
Test name
Test status
Simulation time 52624548 ps
CPU time 1.05 seconds
Started Jul 14 05:22:55 PM PDT 24
Finished Jul 14 05:22:57 PM PDT 24
Peak memory 217504 kb
Host smart-a5b886ed-3bb0-4aa0-92ab-fc967fbc7f79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530541844 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.530541844
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2681780069
Short name T195
Test name
Test status
Simulation time 10952768 ps
CPU time 0.84 seconds
Started Jul 14 05:22:58 PM PDT 24
Finished Jul 14 05:23:00 PM PDT 24
Peak memory 208660 kb
Host smart-5e88cab9-16e7-4903-804e-5c17049156bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681780069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2681780069
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.352468569
Short name T874
Test name
Test status
Simulation time 72403016 ps
CPU time 1.07 seconds
Started Jul 14 05:22:56 PM PDT 24
Finished Jul 14 05:22:58 PM PDT 24
Peak memory 208964 kb
Host smart-b57967ca-64e0-4934-adae-1e0c98492718
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352468569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.352468569
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.57732047
Short name T867
Test name
Test status
Simulation time 517826360 ps
CPU time 12.34 seconds
Started Jul 14 05:22:56 PM PDT 24
Finished Jul 14 05:23:09 PM PDT 24
Peak memory 209100 kb
Host smart-c77d4eff-3ec2-4682-b9d7-58d41bc06d13
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57732047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.lc_ctrl_jtag_csr_aliasing.57732047
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4239076720
Short name T944
Test name
Test status
Simulation time 2493526087 ps
CPU time 20.13 seconds
Started Jul 14 05:22:49 PM PDT 24
Finished Jul 14 05:23:09 PM PDT 24
Peak memory 209128 kb
Host smart-b46c7df4-1904-4c25-80dd-720753b453a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239076720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.4239076720
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2756075414
Short name T871
Test name
Test status
Simulation time 148682408 ps
CPU time 1.37 seconds
Started Jul 14 05:22:49 PM PDT 24
Finished Jul 14 05:22:50 PM PDT 24
Peak memory 210588 kb
Host smart-91ba374a-f940-4408-9d54-ec8582576709
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756075414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2756075414
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1760011228
Short name T896
Test name
Test status
Simulation time 723451695 ps
CPU time 2.18 seconds
Started Jul 14 05:22:54 PM PDT 24
Finished Jul 14 05:22:58 PM PDT 24
Peak memory 218180 kb
Host smart-8ca5034e-351d-442a-9b2f-8d5db2b078d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176001
1228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1760011228
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4107371481
Short name T885
Test name
Test status
Simulation time 126259688 ps
CPU time 1.75 seconds
Started Jul 14 05:22:51 PM PDT 24
Finished Jul 14 05:22:53 PM PDT 24
Peak memory 209072 kb
Host smart-da87b302-32b2-42ab-b820-ba13aa664fbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107371481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.4107371481
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.464911951
Short name T975
Test name
Test status
Simulation time 22524106 ps
CPU time 1.33 seconds
Started Jul 14 05:23:00 PM PDT 24
Finished Jul 14 05:23:03 PM PDT 24
Peak memory 209152 kb
Host smart-fc6e197d-4ca9-48ad-8464-70c4b0b2fcc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464911951 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.464911951
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.211244457
Short name T971
Test name
Test status
Simulation time 149194608 ps
CPU time 1.86 seconds
Started Jul 14 05:23:00 PM PDT 24
Finished Jul 14 05:23:03 PM PDT 24
Peak memory 217348 kb
Host smart-48aa83e9-c118-456c-9d18-f3b5be6ec2ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211244457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.211244457
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2955597506
Short name T927
Test name
Test status
Simulation time 574989758 ps
CPU time 5.53 seconds
Started Jul 14 05:23:01 PM PDT 24
Finished Jul 14 05:23:07 PM PDT 24
Peak memory 217356 kb
Host smart-377aa8c8-e636-4dcb-a23c-3cd8dbbf6f3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955597506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2955597506
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2965218084
Short name T125
Test name
Test status
Simulation time 119486494 ps
CPU time 2.64 seconds
Started Jul 14 05:22:54 PM PDT 24
Finished Jul 14 05:22:57 PM PDT 24
Peak memory 217444 kb
Host smart-ec5134d0-0403-495d-a49a-9bce74d6ae4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965218084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2965218084
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2591328567
Short name T191
Test name
Test status
Simulation time 44255341 ps
CPU time 1.97 seconds
Started Jul 14 05:23:04 PM PDT 24
Finished Jul 14 05:23:07 PM PDT 24
Peak memory 209160 kb
Host smart-328e2741-c248-4c33-8c03-42d18b707b08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591328567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2591328567
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1050375303
Short name T864
Test name
Test status
Simulation time 30318007 ps
CPU time 1.89 seconds
Started Jul 14 05:23:03 PM PDT 24
Finished Jul 14 05:23:06 PM PDT 24
Peak memory 209100 kb
Host smart-f6795d88-6edc-4a39-937e-7ea22feb7482
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050375303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1050375303
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.683046620
Short name T192
Test name
Test status
Simulation time 16730884 ps
CPU time 0.99 seconds
Started Jul 14 05:23:00 PM PDT 24
Finished Jul 14 05:23:02 PM PDT 24
Peak memory 209828 kb
Host smart-fe4f52c5-1fc5-4344-bde1-8d6c3976e137
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683046620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.683046620
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1491135574
Short name T888
Test name
Test status
Simulation time 87348842 ps
CPU time 1.72 seconds
Started Jul 14 05:23:03 PM PDT 24
Finished Jul 14 05:23:06 PM PDT 24
Peak memory 217544 kb
Host smart-47b29ac5-6216-48d4-8572-6ec672da5c12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491135574 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1491135574
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2109820650
Short name T883
Test name
Test status
Simulation time 22071101 ps
CPU time 0.9 seconds
Started Jul 14 05:23:00 PM PDT 24
Finished Jul 14 05:23:02 PM PDT 24
Peak memory 209068 kb
Host smart-bcf0ce63-ec22-4bdc-9020-ad558f845844
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109820650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2109820650
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3518197154
Short name T973
Test name
Test status
Simulation time 154310430 ps
CPU time 1.92 seconds
Started Jul 14 05:22:57 PM PDT 24
Finished Jul 14 05:22:59 PM PDT 24
Peak memory 208440 kb
Host smart-00961c1a-0f6f-4706-9620-ea008ae8bf70
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518197154 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3518197154
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1702010177
Short name T898
Test name
Test status
Simulation time 188745067 ps
CPU time 3.39 seconds
Started Jul 14 05:22:54 PM PDT 24
Finished Jul 14 05:22:59 PM PDT 24
Peak memory 209024 kb
Host smart-756e064c-1d4b-4878-a1a6-0983065e04ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702010177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1702010177
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2600326304
Short name T875
Test name
Test status
Simulation time 3462546692 ps
CPU time 13.87 seconds
Started Jul 14 05:22:56 PM PDT 24
Finished Jul 14 05:23:10 PM PDT 24
Peak memory 217256 kb
Host smart-a116541f-fac3-4f90-b563-b193af9cf5ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600326304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2600326304
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3994090099
Short name T873
Test name
Test status
Simulation time 133965406 ps
CPU time 2 seconds
Started Jul 14 05:22:55 PM PDT 24
Finished Jul 14 05:22:58 PM PDT 24
Peak memory 217372 kb
Host smart-788d904e-539b-46c5-87a1-2115964d93cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994090099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3994090099
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1175774962
Short name T933
Test name
Test status
Simulation time 212336562 ps
CPU time 5.54 seconds
Started Jul 14 05:22:57 PM PDT 24
Finished Jul 14 05:23:03 PM PDT 24
Peak memory 217412 kb
Host smart-b1b4e4ee-97de-4acd-9ddd-1c48f9cd5acd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117577
4962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1175774962
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1641336579
Short name T890
Test name
Test status
Simulation time 555690193 ps
CPU time 1.86 seconds
Started Jul 14 05:22:55 PM PDT 24
Finished Jul 14 05:22:58 PM PDT 24
Peak memory 209172 kb
Host smart-32265b97-fc43-4404-89b1-fd0284708a9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641336579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1641336579
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2220784879
Short name T877
Test name
Test status
Simulation time 34266587 ps
CPU time 1.27 seconds
Started Jul 14 05:22:54 PM PDT 24
Finished Jul 14 05:22:56 PM PDT 24
Peak memory 209116 kb
Host smart-71bc4058-ff95-4561-ad38-a39e1b3fab88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220784879 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2220784879
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1293153699
Short name T893
Test name
Test status
Simulation time 107365556 ps
CPU time 1.19 seconds
Started Jul 14 05:23:00 PM PDT 24
Finished Jul 14 05:23:03 PM PDT 24
Peak memory 217368 kb
Host smart-cc5d2318-75ae-416f-9af1-07254d35e4ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293153699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1293153699
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1139490124
Short name T926
Test name
Test status
Simulation time 304790438 ps
CPU time 2.5 seconds
Started Jul 14 05:22:54 PM PDT 24
Finished Jul 14 05:22:58 PM PDT 24
Peak memory 217788 kb
Host smart-44e2b0b8-7934-4bbd-a83b-e088c98e7d23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139490124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1139490124
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1344041196
Short name T132
Test name
Test status
Simulation time 282874288 ps
CPU time 1.93 seconds
Started Jul 14 05:22:58 PM PDT 24
Finished Jul 14 05:23:02 PM PDT 24
Peak memory 221740 kb
Host smart-bb9a97a2-ca27-46bd-9456-b421d4f9e3d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344041196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1344041196
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.370740971
Short name T126
Test name
Test status
Simulation time 55784372 ps
CPU time 1.2 seconds
Started Jul 14 05:23:02 PM PDT 24
Finished Jul 14 05:23:05 PM PDT 24
Peak memory 219284 kb
Host smart-6612c07b-79a6-437a-a7f6-78c78341076c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370740971 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.370740971
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.155317605
Short name T866
Test name
Test status
Simulation time 16079028 ps
CPU time 0.89 seconds
Started Jul 14 05:23:01 PM PDT 24
Finished Jul 14 05:23:04 PM PDT 24
Peak memory 209084 kb
Host smart-430be531-2bb6-4176-8e9e-a0718aa5e4e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155317605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.155317605
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1672276370
Short name T862
Test name
Test status
Simulation time 72683230 ps
CPU time 1.6 seconds
Started Jul 14 05:23:03 PM PDT 24
Finished Jul 14 05:23:06 PM PDT 24
Peak memory 208996 kb
Host smart-087f9099-6ec5-4ac6-8dd5-d52793998a3f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672276370 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1672276370
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3133371996
Short name T917
Test name
Test status
Simulation time 1227762336 ps
CPU time 23.75 seconds
Started Jul 14 05:22:58 PM PDT 24
Finished Jul 14 05:23:23 PM PDT 24
Peak memory 209072 kb
Host smart-c126de40-e73c-4eb6-8cf1-5ab9d22be350
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133371996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3133371996
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3690606313
Short name T905
Test name
Test status
Simulation time 2352861189 ps
CPU time 11.9 seconds
Started Jul 14 05:23:00 PM PDT 24
Finished Jul 14 05:23:13 PM PDT 24
Peak memory 209068 kb
Host smart-a466af31-fb0b-4664-b0de-4d17120bb814
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690606313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3690606313
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2189779383
Short name T962
Test name
Test status
Simulation time 477518945 ps
CPU time 1.89 seconds
Started Jul 14 05:23:01 PM PDT 24
Finished Jul 14 05:23:05 PM PDT 24
Peak memory 210700 kb
Host smart-e24747d6-ba45-4343-ba24-6797f3c8a997
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189779383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2189779383
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3141228469
Short name T910
Test name
Test status
Simulation time 404497800 ps
CPU time 2.49 seconds
Started Jul 14 05:23:01 PM PDT 24
Finished Jul 14 05:23:05 PM PDT 24
Peak memory 218900 kb
Host smart-64d8e1e6-bdce-43ba-aa5f-a9682b5e2494
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314122
8469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3141228469
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.194640735
Short name T929
Test name
Test status
Simulation time 436971934 ps
CPU time 1.43 seconds
Started Jul 14 05:23:01 PM PDT 24
Finished Jul 14 05:23:04 PM PDT 24
Peak memory 217136 kb
Host smart-2267e380-3ce1-4fb3-b213-8c2dbedcf956
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194640735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.194640735
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3385183624
Short name T148
Test name
Test status
Simulation time 54536098 ps
CPU time 1.57 seconds
Started Jul 14 05:23:00 PM PDT 24
Finished Jul 14 05:23:03 PM PDT 24
Peak memory 209136 kb
Host smart-862e56aa-6a53-43a7-ae99-c852ab0447a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385183624 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3385183624
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1283147476
Short name T911
Test name
Test status
Simulation time 203425761 ps
CPU time 1.09 seconds
Started Jul 14 05:23:01 PM PDT 24
Finished Jul 14 05:23:04 PM PDT 24
Peak memory 209108 kb
Host smart-3f1b93f7-671c-4973-a4c4-0014a28e43f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283147476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1283147476
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.4093490368
Short name T943
Test name
Test status
Simulation time 159647074 ps
CPU time 6.18 seconds
Started Jul 14 05:23:03 PM PDT 24
Finished Jul 14 05:23:10 PM PDT 24
Peak memory 217404 kb
Host smart-3f2cd148-aadc-4b50-aa43-3b453353a408
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093490368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.4093490368
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2771408081
Short name T937
Test name
Test status
Simulation time 72500579 ps
CPU time 1.58 seconds
Started Jul 14 05:23:07 PM PDT 24
Finished Jul 14 05:23:09 PM PDT 24
Peak memory 219860 kb
Host smart-b92a741b-46db-4376-be22-7c0e631db221
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771408081 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2771408081
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1397774400
Short name T190
Test name
Test status
Simulation time 60810450 ps
CPU time 1.05 seconds
Started Jul 14 05:23:04 PM PDT 24
Finished Jul 14 05:23:06 PM PDT 24
Peak memory 209228 kb
Host smart-418ca621-72e7-4e20-ac75-2588c6352ff6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397774400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1397774400
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1899795790
Short name T861
Test name
Test status
Simulation time 69495275 ps
CPU time 2.23 seconds
Started Jul 14 05:23:02 PM PDT 24
Finished Jul 14 05:23:06 PM PDT 24
Peak memory 208956 kb
Host smart-5ff28e17-db7c-443e-8e9b-da0a3ac01294
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899795790 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1899795790
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2816382713
Short name T137
Test name
Test status
Simulation time 1908967492 ps
CPU time 12 seconds
Started Jul 14 05:23:01 PM PDT 24
Finished Jul 14 05:23:14 PM PDT 24
Peak memory 209232 kb
Host smart-c53d4197-5981-4724-91eb-8c54e82fa4ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816382713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2816382713
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3911182684
Short name T945
Test name
Test status
Simulation time 1347738419 ps
CPU time 9.82 seconds
Started Jul 14 05:23:03 PM PDT 24
Finished Jul 14 05:23:14 PM PDT 24
Peak memory 209084 kb
Host smart-58e10356-fb7b-4311-b9bf-29927dbdadf9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911182684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3911182684
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2999143092
Short name T964
Test name
Test status
Simulation time 226110611 ps
CPU time 1.34 seconds
Started Jul 14 05:23:04 PM PDT 24
Finished Jul 14 05:23:06 PM PDT 24
Peak memory 210588 kb
Host smart-85d39b7c-47e1-41b4-904d-c9f9b58482f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999143092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2999143092
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3397011924
Short name T123
Test name
Test status
Simulation time 277819347 ps
CPU time 2.32 seconds
Started Jul 14 05:23:02 PM PDT 24
Finished Jul 14 05:23:06 PM PDT 24
Peak memory 217412 kb
Host smart-1ba6c1f0-6885-4f0a-aab4-0c8d3512e190
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339701
1924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3397011924
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3081758046
Short name T920
Test name
Test status
Simulation time 76194565 ps
CPU time 1.16 seconds
Started Jul 14 05:23:00 PM PDT 24
Finished Jul 14 05:23:03 PM PDT 24
Peak memory 217032 kb
Host smart-b0b40c55-6272-4414-89fc-58fd9778c5d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081758046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3081758046
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1898805869
Short name T936
Test name
Test status
Simulation time 27551668 ps
CPU time 1.07 seconds
Started Jul 14 05:23:02 PM PDT 24
Finished Jul 14 05:23:04 PM PDT 24
Peak memory 209200 kb
Host smart-27736987-da65-47bf-86e9-cd29a75f64c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898805869 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1898805869
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2435976063
Short name T200
Test name
Test status
Simulation time 70936705 ps
CPU time 1.24 seconds
Started Jul 14 05:23:03 PM PDT 24
Finished Jul 14 05:23:06 PM PDT 24
Peak memory 208972 kb
Host smart-8b2679b7-cbb4-41a2-b5dd-8fe45505c2c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435976063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2435976063
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.779585192
Short name T940
Test name
Test status
Simulation time 29094438 ps
CPU time 2.3 seconds
Started Jul 14 05:22:59 PM PDT 24
Finished Jul 14 05:23:02 PM PDT 24
Peak memory 217536 kb
Host smart-d334fc7e-e339-4c6a-b34a-4ea50d6a7b99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779585192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.779585192
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2450112294
Short name T928
Test name
Test status
Simulation time 28705786 ps
CPU time 1.25 seconds
Started Jul 14 05:23:11 PM PDT 24
Finished Jul 14 05:23:13 PM PDT 24
Peak memory 217672 kb
Host smart-a7b77eae-2f64-4d7a-85ed-81eb542f9c6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450112294 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2450112294
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3487987751
Short name T889
Test name
Test status
Simulation time 31163552 ps
CPU time 0.83 seconds
Started Jul 14 05:23:11 PM PDT 24
Finished Jul 14 05:23:12 PM PDT 24
Peak memory 208752 kb
Host smart-940fc34b-7910-4c3b-a14f-8be094bf36f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487987751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3487987751
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1453689049
Short name T908
Test name
Test status
Simulation time 58989862 ps
CPU time 2.19 seconds
Started Jul 14 05:23:05 PM PDT 24
Finished Jul 14 05:23:08 PM PDT 24
Peak memory 208908 kb
Host smart-cfdfe6d7-6e3e-4df8-b236-f2974a5fe7ab
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453689049 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1453689049
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1126103114
Short name T882
Test name
Test status
Simulation time 5715942828 ps
CPU time 5.4 seconds
Started Jul 14 05:23:08 PM PDT 24
Finished Jul 14 05:23:14 PM PDT 24
Peak memory 209180 kb
Host smart-71b0606c-8422-4d6a-8ab9-0aa999218db0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126103114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1126103114
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1722279027
Short name T959
Test name
Test status
Simulation time 2569018626 ps
CPU time 15.34 seconds
Started Jul 14 05:23:08 PM PDT 24
Finished Jul 14 05:23:24 PM PDT 24
Peak memory 209168 kb
Host smart-297ee258-4b64-4861-959f-8554cc09c676
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722279027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1722279027
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.648050127
Short name T954
Test name
Test status
Simulation time 330422196 ps
CPU time 3.85 seconds
Started Jul 14 05:23:08 PM PDT 24
Finished Jul 14 05:23:13 PM PDT 24
Peak memory 217300 kb
Host smart-3961beaf-8a28-4de0-b4cf-9f951be2689c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648050127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.648050127
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2872716061
Short name T902
Test name
Test status
Simulation time 332829942 ps
CPU time 4.57 seconds
Started Jul 14 05:23:07 PM PDT 24
Finished Jul 14 05:23:12 PM PDT 24
Peak memory 217432 kb
Host smart-8f2d2491-07db-4f27-a0af-4796818fcb93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287271
6061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2872716061
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3624846129
Short name T872
Test name
Test status
Simulation time 159037030 ps
CPU time 1.69 seconds
Started Jul 14 05:23:11 PM PDT 24
Finished Jul 14 05:23:13 PM PDT 24
Peak memory 217008 kb
Host smart-b6cc02a9-b547-48ba-bc44-b75246a4ecf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624846129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3624846129
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3803164514
Short name T913
Test name
Test status
Simulation time 78858973 ps
CPU time 1.44 seconds
Started Jul 14 05:23:07 PM PDT 24
Finished Jul 14 05:23:09 PM PDT 24
Peak memory 211184 kb
Host smart-c262ddbc-2ede-478d-a8ca-eadd349e9f05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803164514 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3803164514
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1901237838
Short name T203
Test name
Test status
Simulation time 47240197 ps
CPU time 1.09 seconds
Started Jul 14 05:23:06 PM PDT 24
Finished Jul 14 05:23:07 PM PDT 24
Peak memory 217432 kb
Host smart-30b3967a-f0a9-4f09-96f6-e05c1cdb5ad1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901237838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1901237838
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2552916415
Short name T909
Test name
Test status
Simulation time 180386717 ps
CPU time 4.25 seconds
Started Jul 14 05:23:11 PM PDT 24
Finished Jul 14 05:23:16 PM PDT 24
Peak memory 217464 kb
Host smart-6b98c9d5-dc70-443d-bbff-06b4071f751e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552916415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2552916415
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2606823002
Short name T884
Test name
Test status
Simulation time 65226655 ps
CPU time 1.27 seconds
Started Jul 14 05:23:16 PM PDT 24
Finished Jul 14 05:23:18 PM PDT 24
Peak memory 218372 kb
Host smart-2c4000fe-76eb-43b2-bca9-b850d63f7379
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606823002 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.2606823002
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.492481584
Short name T197
Test name
Test status
Simulation time 13252155 ps
CPU time 1 seconds
Started Jul 14 05:23:12 PM PDT 24
Finished Jul 14 05:23:14 PM PDT 24
Peak memory 209148 kb
Host smart-1b48ba7e-4b6c-41a5-8132-771e8e1ea53d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492481584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.492481584
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2387838630
Short name T887
Test name
Test status
Simulation time 51488523 ps
CPU time 1.41 seconds
Started Jul 14 05:23:13 PM PDT 24
Finished Jul 14 05:23:15 PM PDT 24
Peak memory 208972 kb
Host smart-d66d7d24-c9b0-4d5e-a7f3-9132f08cea46
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387838630 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2387838630
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.521017437
Short name T970
Test name
Test status
Simulation time 1455152543 ps
CPU time 16.4 seconds
Started Jul 14 05:23:08 PM PDT 24
Finished Jul 14 05:23:25 PM PDT 24
Peak memory 209060 kb
Host smart-89378f7d-5631-4fc8-b4d0-4cdcacbf4a1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521017437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.521017437
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3112853264
Short name T932
Test name
Test status
Simulation time 351714888 ps
CPU time 4.69 seconds
Started Jul 14 05:23:11 PM PDT 24
Finished Jul 14 05:23:16 PM PDT 24
Peak memory 209152 kb
Host smart-652b58dd-b57d-4c93-ac62-42bfd5be2700
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112853264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3112853264
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3185303120
Short name T869
Test name
Test status
Simulation time 185732961 ps
CPU time 1.79 seconds
Started Jul 14 05:23:11 PM PDT 24
Finished Jul 14 05:23:14 PM PDT 24
Peak memory 210668 kb
Host smart-99a5360c-3623-4752-8b3f-5f5150217699
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185303120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3185303120
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1185698126
Short name T172
Test name
Test status
Simulation time 226339906 ps
CPU time 2.36 seconds
Started Jul 14 05:23:11 PM PDT 24
Finished Jul 14 05:23:15 PM PDT 24
Peak memory 220368 kb
Host smart-474a2fea-134c-4a8e-a4a3-63bc52346803
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118569
8126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1185698126
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3591499960
Short name T138
Test name
Test status
Simulation time 326328118 ps
CPU time 1.57 seconds
Started Jul 14 05:23:07 PM PDT 24
Finished Jul 14 05:23:10 PM PDT 24
Peak memory 208948 kb
Host smart-1cc43447-0b65-4311-8cac-b2a8bd52dfa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591499960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3591499960
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3368919185
Short name T965
Test name
Test status
Simulation time 16810315 ps
CPU time 1.2 seconds
Started Jul 14 05:23:09 PM PDT 24
Finished Jul 14 05:23:11 PM PDT 24
Peak memory 209132 kb
Host smart-820dd61e-0b80-4963-8b34-270855f05dc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368919185 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3368919185
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3799808354
Short name T977
Test name
Test status
Simulation time 248111208 ps
CPU time 1.37 seconds
Started Jul 14 05:23:15 PM PDT 24
Finished Jul 14 05:23:17 PM PDT 24
Peak memory 217448 kb
Host smart-373fc74c-cd36-404b-90cb-29833c65f0a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799808354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3799808354
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3910643439
Short name T109
Test name
Test status
Simulation time 159720001 ps
CPU time 5.81 seconds
Started Jul 14 05:23:16 PM PDT 24
Finished Jul 14 05:23:22 PM PDT 24
Peak memory 217468 kb
Host smart-e0f18e6e-1f85-470c-9519-ef0a0d64f7ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910643439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3910643439
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3771032254
Short name T900
Test name
Test status
Simulation time 90087529 ps
CPU time 1.26 seconds
Started Jul 14 05:23:21 PM PDT 24
Finished Jul 14 05:23:23 PM PDT 24
Peak memory 217552 kb
Host smart-24f2ed44-6434-4fd0-952d-d0ebfac62eeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771032254 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3771032254
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1596216966
Short name T185
Test name
Test status
Simulation time 22675285 ps
CPU time 0.88 seconds
Started Jul 14 05:23:14 PM PDT 24
Finished Jul 14 05:23:15 PM PDT 24
Peak memory 209156 kb
Host smart-e5d56925-36fb-4aeb-8a65-2b0c521f2c55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596216966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1596216966
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1533751180
Short name T891
Test name
Test status
Simulation time 28509978 ps
CPU time 1.32 seconds
Started Jul 14 05:23:12 PM PDT 24
Finished Jul 14 05:23:15 PM PDT 24
Peak memory 209148 kb
Host smart-5780e46b-b47b-43a4-840c-3c0fa35fdac4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533751180 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1533751180
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.772503280
Short name T958
Test name
Test status
Simulation time 1834235159 ps
CPU time 4.88 seconds
Started Jul 14 05:23:15 PM PDT 24
Finished Jul 14 05:23:21 PM PDT 24
Peak memory 209112 kb
Host smart-30482a48-4eec-4940-b4ee-daf3b77c91e8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772503280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.772503280
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.262042980
Short name T906
Test name
Test status
Simulation time 489531665 ps
CPU time 5.62 seconds
Started Jul 14 05:23:12 PM PDT 24
Finished Jul 14 05:23:19 PM PDT 24
Peak memory 209044 kb
Host smart-78c1becf-53b6-450a-ad13-2c3b353e8ed9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262042980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.262042980
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3646515040
Short name T938
Test name
Test status
Simulation time 264710212 ps
CPU time 2.33 seconds
Started Jul 14 05:23:17 PM PDT 24
Finished Jul 14 05:23:20 PM PDT 24
Peak memory 217284 kb
Host smart-287f43e1-25db-433a-9e23-3a4b086b4029
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646515040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3646515040
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1812285428
Short name T978
Test name
Test status
Simulation time 213232870 ps
CPU time 1.79 seconds
Started Jul 14 05:23:16 PM PDT 24
Finished Jul 14 05:23:18 PM PDT 24
Peak memory 218936 kb
Host smart-6bbd0fbe-0a12-48ec-9b5b-4c7f3effe9ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181228
5428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1812285428
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2858580568
Short name T139
Test name
Test status
Simulation time 55670006 ps
CPU time 1.71 seconds
Started Jul 14 05:23:11 PM PDT 24
Finished Jul 14 05:23:14 PM PDT 24
Peak memory 209136 kb
Host smart-80157c62-6942-4c9f-b8f2-75596823b8ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858580568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.2858580568
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2730207794
Short name T919
Test name
Test status
Simulation time 58826175 ps
CPU time 1.03 seconds
Started Jul 14 05:23:13 PM PDT 24
Finished Jul 14 05:23:14 PM PDT 24
Peak memory 217488 kb
Host smart-9fe8c164-b731-4f7a-8a24-cfaced27418b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730207794 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2730207794
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2154088036
Short name T202
Test name
Test status
Simulation time 78847702 ps
CPU time 1.4 seconds
Started Jul 14 05:23:15 PM PDT 24
Finished Jul 14 05:23:17 PM PDT 24
Peak memory 209108 kb
Host smart-8a1626c8-e287-4768-9dae-b31a102006e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154088036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2154088036
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3246892049
Short name T951
Test name
Test status
Simulation time 183193335 ps
CPU time 3.14 seconds
Started Jul 14 05:23:15 PM PDT 24
Finished Jul 14 05:23:19 PM PDT 24
Peak memory 217332 kb
Host smart-b398d048-017d-4e52-8814-0069408cd06e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246892049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3246892049
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3420469452
Short name T134
Test name
Test status
Simulation time 76859646 ps
CPU time 2.68 seconds
Started Jul 14 05:23:16 PM PDT 24
Finished Jul 14 05:23:20 PM PDT 24
Peak memory 217464 kb
Host smart-aed353ab-339d-4dec-9b17-ca61ab10977c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420469452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3420469452
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1591978345
Short name T792
Test name
Test status
Simulation time 31642647 ps
CPU time 0.91 seconds
Started Jul 14 05:27:08 PM PDT 24
Finished Jul 14 05:27:10 PM PDT 24
Peak memory 208448 kb
Host smart-82264ed3-b5ed-41d2-ae02-83efbf712746
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591978345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1591978345
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3740379628
Short name T162
Test name
Test status
Simulation time 12554891 ps
CPU time 0.98 seconds
Started Jul 14 05:27:08 PM PDT 24
Finished Jul 14 05:27:10 PM PDT 24
Peak memory 208320 kb
Host smart-2d32a007-64da-4a79-9bb1-852a53c15fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740379628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3740379628
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.709367994
Short name T334
Test name
Test status
Simulation time 616613258 ps
CPU time 15.02 seconds
Started Jul 14 05:27:12 PM PDT 24
Finished Jul 14 05:27:27 PM PDT 24
Peak memory 217712 kb
Host smart-ad24bca0-440e-4785-89d6-6585d3f3eaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709367994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.709367994
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.135448075
Short name T470
Test name
Test status
Simulation time 514495771 ps
CPU time 3.48 seconds
Started Jul 14 05:27:10 PM PDT 24
Finished Jul 14 05:27:14 PM PDT 24
Peak memory 216600 kb
Host smart-47b07800-43ea-4dd0-91e0-7b86cda5b43c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135448075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.135448075
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.748834589
Short name T272
Test name
Test status
Simulation time 1671781470 ps
CPU time 44.22 seconds
Started Jul 14 05:27:11 PM PDT 24
Finished Jul 14 05:27:56 PM PDT 24
Peak memory 218224 kb
Host smart-644bb5a0-e09e-4b0a-a2ad-51e162780f1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748834589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.748834589
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.616802595
Short name T463
Test name
Test status
Simulation time 2156396312 ps
CPU time 5.72 seconds
Started Jul 14 05:27:09 PM PDT 24
Finished Jul 14 05:27:15 PM PDT 24
Peak memory 217240 kb
Host smart-4766500d-cf3d-440e-9403-bc95006b66b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616802595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.616802595
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3581107349
Short name T469
Test name
Test status
Simulation time 6125356577 ps
CPU time 10.31 seconds
Started Jul 14 05:27:09 PM PDT 24
Finished Jul 14 05:27:20 PM PDT 24
Peak memory 217628 kb
Host smart-ec7cc002-02da-4b78-8a49-6bd13dadec26
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581107349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3581107349
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.410797586
Short name T665
Test name
Test status
Simulation time 1168481538 ps
CPU time 21.29 seconds
Started Jul 14 05:27:08 PM PDT 24
Finished Jul 14 05:27:29 PM PDT 24
Peak memory 217048 kb
Host smart-6d4e9ccd-ac5c-4b8b-b94c-1fff695e405a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410797586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.410797586
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.332700884
Short name T699
Test name
Test status
Simulation time 314961585 ps
CPU time 4.92 seconds
Started Jul 14 05:27:09 PM PDT 24
Finished Jul 14 05:27:15 PM PDT 24
Peak memory 216944 kb
Host smart-0cec1e6f-3f1c-4a5e-bafe-96dd36e2310e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332700884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.332700884
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.862760037
Short name T737
Test name
Test status
Simulation time 7674216486 ps
CPU time 72.46 seconds
Started Jul 14 05:27:09 PM PDT 24
Finished Jul 14 05:28:23 PM PDT 24
Peak memory 251892 kb
Host smart-6c68bf27-aa82-4ffe-99bb-81af315b49d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862760037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_state_failure.862760037
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2424926720
Short name T504
Test name
Test status
Simulation time 788777736 ps
CPU time 7.33 seconds
Started Jul 14 05:27:10 PM PDT 24
Finished Jul 14 05:27:18 PM PDT 24
Peak memory 222308 kb
Host smart-08222f35-62c7-42b2-8207-17f95724bfdc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424926720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2424926720
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1777273730
Short name T320
Test name
Test status
Simulation time 95780157 ps
CPU time 3.3 seconds
Started Jul 14 05:27:03 PM PDT 24
Finished Jul 14 05:27:07 PM PDT 24
Peak memory 217600 kb
Host smart-aba5fe67-9e9c-449c-a83d-1c77a8c79a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777273730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1777273730
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3638481432
Short name T477
Test name
Test status
Simulation time 5744320352 ps
CPU time 11.82 seconds
Started Jul 14 05:27:08 PM PDT 24
Finished Jul 14 05:27:20 PM PDT 24
Peak memory 214852 kb
Host smart-15a9e40b-2a98-49a7-99b8-1e7a2d9cacca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638481432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3638481432
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.4267984414
Short name T50
Test name
Test status
Simulation time 856431568 ps
CPU time 24.06 seconds
Started Jul 14 05:27:10 PM PDT 24
Finished Jul 14 05:27:35 PM PDT 24
Peak memory 268408 kb
Host smart-dd7d5645-11ca-4923-b078-bfd308f6beff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267984414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.4267984414
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3765777063
Short name T534
Test name
Test status
Simulation time 309134801 ps
CPU time 13.29 seconds
Started Jul 14 05:27:11 PM PDT 24
Finished Jul 14 05:27:25 PM PDT 24
Peak memory 217692 kb
Host smart-c290c489-d51d-4e45-873d-783b8f8415a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765777063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3765777063
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1094503760
Short name T31
Test name
Test status
Simulation time 615633549 ps
CPU time 9.31 seconds
Started Jul 14 05:27:09 PM PDT 24
Finished Jul 14 05:27:19 PM PDT 24
Peak memory 217664 kb
Host smart-cb813cf2-0588-4b5d-95d0-7509e27d82dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094503760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
094503760
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.1084050647
Short name T793
Test name
Test status
Simulation time 766482556 ps
CPU time 8.68 seconds
Started Jul 14 05:27:09 PM PDT 24
Finished Jul 14 05:27:19 PM PDT 24
Peak memory 225388 kb
Host smart-94869b07-03ca-47e2-8584-68c10bea97e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084050647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1084050647
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1264769085
Short name T407
Test name
Test status
Simulation time 112825364 ps
CPU time 2.01 seconds
Started Jul 14 05:27:07 PM PDT 24
Finished Jul 14 05:27:09 PM PDT 24
Peak memory 213412 kb
Host smart-69b51a43-f924-4746-8605-d0b6e985fa05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264769085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1264769085
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1203765402
Short name T797
Test name
Test status
Simulation time 998597234 ps
CPU time 28.7 seconds
Started Jul 14 05:27:02 PM PDT 24
Finished Jul 14 05:27:31 PM PDT 24
Peak memory 250416 kb
Host smart-3c8c1d18-855e-4cd9-b76f-ca989d1ad442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203765402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1203765402
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.4256827097
Short name T229
Test name
Test status
Simulation time 236580015 ps
CPU time 6.63 seconds
Started Jul 14 05:27:03 PM PDT 24
Finished Jul 14 05:27:10 PM PDT 24
Peak memory 249928 kb
Host smart-72124ba8-d0bf-4000-af64-0e12486813fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256827097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.4256827097
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2906973411
Short name T75
Test name
Test status
Simulation time 8630980886 ps
CPU time 83.69 seconds
Started Jul 14 05:27:10 PM PDT 24
Finished Jul 14 05:28:35 PM PDT 24
Peak memory 266964 kb
Host smart-c2438123-465a-472e-96f0-097a4d06e9af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906973411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2906973411
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.108436616
Short name T435
Test name
Test status
Simulation time 12557475 ps
CPU time 0.82 seconds
Started Jul 14 05:27:07 PM PDT 24
Finished Jul 14 05:27:08 PM PDT 24
Peak memory 208280 kb
Host smart-f2ef3c43-d470-4449-b811-8d514ae444fd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108436616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.108436616
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2536850281
Short name T365
Test name
Test status
Simulation time 88263437 ps
CPU time 1.2 seconds
Started Jul 14 05:27:23 PM PDT 24
Finished Jul 14 05:27:25 PM PDT 24
Peak memory 208432 kb
Host smart-2c8615df-1d8e-4755-b933-a00c3d19b645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536850281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2536850281
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1505892203
Short name T485
Test name
Test status
Simulation time 14086950 ps
CPU time 0.95 seconds
Started Jul 14 05:27:15 PM PDT 24
Finished Jul 14 05:27:16 PM PDT 24
Peak memory 208544 kb
Host smart-1a089e01-458a-4a65-b644-ff3953e5cc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505892203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1505892203
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3031919498
Short name T242
Test name
Test status
Simulation time 388670513 ps
CPU time 10.27 seconds
Started Jul 14 05:27:16 PM PDT 24
Finished Jul 14 05:27:26 PM PDT 24
Peak memory 217608 kb
Host smart-51fb0ffb-87c6-4d68-9171-ac09d14d6d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031919498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3031919498
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1651382153
Short name T24
Test name
Test status
Simulation time 1150193243 ps
CPU time 5.2 seconds
Started Jul 14 05:27:22 PM PDT 24
Finished Jul 14 05:27:28 PM PDT 24
Peak memory 217096 kb
Host smart-a9d8c1f2-1dd4-4bd2-a46f-6b366babb1c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651382153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1651382153
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2460528123
Short name T720
Test name
Test status
Simulation time 7309835914 ps
CPU time 25.59 seconds
Started Jul 14 05:27:22 PM PDT 24
Finished Jul 14 05:27:48 PM PDT 24
Peak memory 217716 kb
Host smart-d2ff4472-113e-4388-b0b6-cc9c2d80ae09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460528123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2460528123
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.4233349113
Short name T465
Test name
Test status
Simulation time 433708629 ps
CPU time 3.37 seconds
Started Jul 14 05:27:22 PM PDT 24
Finished Jul 14 05:27:26 PM PDT 24
Peak memory 217080 kb
Host smart-5c1578fc-e359-4a63-ad00-f7fb7559c50c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233349113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.4
233349113
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2951531691
Short name T230
Test name
Test status
Simulation time 3525417951 ps
CPU time 24.66 seconds
Started Jul 14 05:27:14 PM PDT 24
Finished Jul 14 05:27:39 PM PDT 24
Peak memory 225516 kb
Host smart-be75dc61-b376-465a-b4a5-1494c6780fa2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951531691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2951531691
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.4084282167
Short name T583
Test name
Test status
Simulation time 1449268547 ps
CPU time 18.42 seconds
Started Jul 14 05:27:23 PM PDT 24
Finished Jul 14 05:27:42 PM PDT 24
Peak memory 217052 kb
Host smart-79047da0-1a75-46d9-a4c2-11f94fa7518f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084282167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.4084282167
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1850546944
Short name T369
Test name
Test status
Simulation time 764422169 ps
CPU time 2.66 seconds
Started Jul 14 05:27:15 PM PDT 24
Finished Jul 14 05:27:18 PM PDT 24
Peak memory 217036 kb
Host smart-bd152612-792e-4c35-bddf-437a4fde8463
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850546944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1850546944
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2757760478
Short name T83
Test name
Test status
Simulation time 8940098652 ps
CPU time 37.35 seconds
Started Jul 14 05:27:17 PM PDT 24
Finished Jul 14 05:27:55 PM PDT 24
Peak memory 266728 kb
Host smart-2317af1a-391b-4017-b636-0adc68e0d3c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757760478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2757760478
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2566144712
Short name T280
Test name
Test status
Simulation time 4139093938 ps
CPU time 25.94 seconds
Started Jul 14 05:27:17 PM PDT 24
Finished Jul 14 05:27:44 PM PDT 24
Peak memory 250328 kb
Host smart-70c08bc6-856c-44a0-b9c0-1e1cb8fbd7d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566144712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2566144712
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2801978149
Short name T674
Test name
Test status
Simulation time 104263096 ps
CPU time 3.19 seconds
Started Jul 14 05:27:16 PM PDT 24
Finished Jul 14 05:27:19 PM PDT 24
Peak memory 217684 kb
Host smart-217124fe-177d-4063-967b-f3ed93d06e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801978149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2801978149
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.661616724
Short name T854
Test name
Test status
Simulation time 4166893607 ps
CPU time 14.3 seconds
Started Jul 14 05:27:16 PM PDT 24
Finished Jul 14 05:27:31 PM PDT 24
Peak memory 214716 kb
Host smart-1abcc52d-403a-4bc7-b053-223fb9f561c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661616724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.661616724
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.4127068744
Short name T510
Test name
Test status
Simulation time 250433686 ps
CPU time 8.08 seconds
Started Jul 14 05:27:22 PM PDT 24
Finished Jul 14 05:27:31 PM PDT 24
Peak memory 225384 kb
Host smart-ea516db4-69a4-497d-9ae8-edfd1ed5bf47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127068744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.4127068744
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3147403854
Short name T569
Test name
Test status
Simulation time 3329962846 ps
CPU time 9.36 seconds
Started Jul 14 05:27:19 PM PDT 24
Finished Jul 14 05:27:29 PM PDT 24
Peak memory 225380 kb
Host smart-a5c5ad05-4901-4994-b0ba-19ed20867520
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147403854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
147403854
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2663887541
Short name T839
Test name
Test status
Simulation time 1146493031 ps
CPU time 7.54 seconds
Started Jul 14 05:27:15 PM PDT 24
Finished Jul 14 05:27:23 PM PDT 24
Peak memory 217844 kb
Host smart-55052ceb-8e45-4709-bd30-5d15b1dfb2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663887541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2663887541
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2123305175
Short name T216
Test name
Test status
Simulation time 32896898 ps
CPU time 2.56 seconds
Started Jul 14 05:27:14 PM PDT 24
Finished Jul 14 05:27:17 PM PDT 24
Peak memory 213956 kb
Host smart-83066802-2fd3-4d02-92eb-09d13c0c16bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123305175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2123305175
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1049961159
Short name T412
Test name
Test status
Simulation time 168865108 ps
CPU time 27.21 seconds
Started Jul 14 05:27:17 PM PDT 24
Finished Jul 14 05:27:45 PM PDT 24
Peak memory 250336 kb
Host smart-5aa16663-5c0f-4b29-974f-02b9d72c36c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049961159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1049961159
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2592152366
Short name T215
Test name
Test status
Simulation time 85354072 ps
CPU time 7.54 seconds
Started Jul 14 05:27:15 PM PDT 24
Finished Jul 14 05:27:23 PM PDT 24
Peak memory 246340 kb
Host smart-8ed64768-75c6-4de5-a147-a9483533d35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592152366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2592152366
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3374612544
Short name T76
Test name
Test status
Simulation time 3086331477 ps
CPU time 13.94 seconds
Started Jul 14 05:27:21 PM PDT 24
Finished Jul 14 05:27:36 PM PDT 24
Peak memory 217192 kb
Host smart-108c38ed-72cf-4d5e-8d8f-d59b6feece70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374612544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3374612544
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.1972091872
Short name T537
Test name
Test status
Simulation time 25455747459 ps
CPU time 940.68 seconds
Started Jul 14 05:27:23 PM PDT 24
Finished Jul 14 05:43:05 PM PDT 24
Peak memory 299904 kb
Host smart-f1e0777c-1cde-41bd-b0f6-a5e4e2f4c014
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1972091872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.1972091872
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.35295078
Short name T683
Test name
Test status
Simulation time 13808711 ps
CPU time 0.81 seconds
Started Jul 14 05:27:14 PM PDT 24
Finished Jul 14 05:27:15 PM PDT 24
Peak memory 208212 kb
Host smart-26434233-e30b-4410-ac52-c5b40423d612
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35295078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_volatile_unlock_smoke.35295078
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.4163264833
Short name T774
Test name
Test status
Simulation time 89311366 ps
CPU time 1.18 seconds
Started Jul 14 05:28:33 PM PDT 24
Finished Jul 14 05:28:34 PM PDT 24
Peak memory 208468 kb
Host smart-1d537e6a-7e4d-4655-ba73-2722b83f9a00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163264833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.4163264833
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1915994980
Short name T741
Test name
Test status
Simulation time 939523867 ps
CPU time 12.19 seconds
Started Jul 14 05:28:28 PM PDT 24
Finished Jul 14 05:28:41 PM PDT 24
Peak memory 217708 kb
Host smart-64f52efa-e378-4b9e-887f-61fbd39bedc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915994980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1915994980
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.449303652
Short name T6
Test name
Test status
Simulation time 954194469 ps
CPU time 6.67 seconds
Started Jul 14 05:28:31 PM PDT 24
Finished Jul 14 05:28:38 PM PDT 24
Peak memory 216664 kb
Host smart-21716f06-ec63-450c-aa7f-141f2b7c2a0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449303652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.449303652
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.3353842198
Short name T388
Test name
Test status
Simulation time 11447276495 ps
CPU time 41.24 seconds
Started Jul 14 05:28:25 PM PDT 24
Finished Jul 14 05:29:07 PM PDT 24
Peak memory 218244 kb
Host smart-8ffb7715-81ff-4094-ad6d-75555426913a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353842198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.3353842198
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2448766142
Short name T329
Test name
Test status
Simulation time 679500930 ps
CPU time 10.3 seconds
Started Jul 14 05:28:27 PM PDT 24
Finished Jul 14 05:28:38 PM PDT 24
Peak memory 217680 kb
Host smart-d65e1242-9c8b-4f12-b23b-0dd497077025
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448766142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2448766142
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3173498713
Short name T290
Test name
Test status
Simulation time 317298218 ps
CPU time 9.47 seconds
Started Jul 14 05:28:27 PM PDT 24
Finished Jul 14 05:28:37 PM PDT 24
Peak memory 217020 kb
Host smart-de65efd3-a525-4eb8-acd8-7f7775c0e52e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173498713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3173498713
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3534192697
Short name T690
Test name
Test status
Simulation time 1084704273 ps
CPU time 47.41 seconds
Started Jul 14 05:28:29 PM PDT 24
Finished Jul 14 05:29:17 PM PDT 24
Peak memory 252352 kb
Host smart-e34fb43c-2b15-4203-a902-1e9642b00c0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534192697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3534192697
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3904903106
Short name T227
Test name
Test status
Simulation time 252192513 ps
CPU time 12.21 seconds
Started Jul 14 05:28:28 PM PDT 24
Finished Jul 14 05:28:40 PM PDT 24
Peak memory 245900 kb
Host smart-b33bfda5-619e-495a-bc82-2faed4076ecb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904903106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3904903106
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.373464554
Short name T374
Test name
Test status
Simulation time 154470857 ps
CPU time 1.88 seconds
Started Jul 14 05:28:27 PM PDT 24
Finished Jul 14 05:28:29 PM PDT 24
Peak memory 217648 kb
Host smart-24c00447-e968-4bd6-b744-9030ff3f7657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373464554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.373464554
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.2717782861
Short name T456
Test name
Test status
Simulation time 1530007009 ps
CPU time 19.74 seconds
Started Jul 14 05:28:35 PM PDT 24
Finished Jul 14 05:28:55 PM PDT 24
Peak memory 217896 kb
Host smart-1d2d8323-eb28-4fde-9821-9f87447121e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717782861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2717782861
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3849952349
Short name T447
Test name
Test status
Simulation time 346615409 ps
CPU time 13.46 seconds
Started Jul 14 05:28:33 PM PDT 24
Finished Jul 14 05:28:47 PM PDT 24
Peak memory 225344 kb
Host smart-13e3c03b-7bf6-402d-b414-249fc5bc2427
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849952349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3849952349
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.956849165
Short name T94
Test name
Test status
Simulation time 1379068010 ps
CPU time 9.68 seconds
Started Jul 14 05:28:36 PM PDT 24
Finished Jul 14 05:28:47 PM PDT 24
Peak memory 217500 kb
Host smart-96ad943d-2660-4a23-8d3f-0f0fbe3ddaea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956849165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.956849165
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1867475489
Short name T157
Test name
Test status
Simulation time 3005292021 ps
CPU time 14.02 seconds
Started Jul 14 05:28:31 PM PDT 24
Finished Jul 14 05:28:45 PM PDT 24
Peak memory 217780 kb
Host smart-15c92d68-4865-43a7-819d-903709790a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867475489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1867475489
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.2493789137
Short name T78
Test name
Test status
Simulation time 92396695 ps
CPU time 2.22 seconds
Started Jul 14 05:28:29 PM PDT 24
Finished Jul 14 05:28:32 PM PDT 24
Peak memory 213656 kb
Host smart-70d37709-cc92-4c4f-9f42-748122e285ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493789137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2493789137
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3954017872
Short name T13
Test name
Test status
Simulation time 578709934 ps
CPU time 27.03 seconds
Started Jul 14 05:28:30 PM PDT 24
Finished Jul 14 05:28:58 PM PDT 24
Peak memory 250496 kb
Host smart-60b9b10b-979c-4e39-8a7c-794dcb3f3a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954017872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3954017872
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2975115866
Short name T785
Test name
Test status
Simulation time 52132149 ps
CPU time 8.9 seconds
Started Jul 14 05:28:31 PM PDT 24
Finished Jul 14 05:28:40 PM PDT 24
Peak memory 250400 kb
Host smart-1540acb3-d381-4cb6-89b2-b6462206a534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975115866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2975115866
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1729610386
Short name T183
Test name
Test status
Simulation time 23575255328 ps
CPU time 85.11 seconds
Started Jul 14 05:28:34 PM PDT 24
Finished Jul 14 05:30:00 PM PDT 24
Peak memory 225520 kb
Host smart-0e57527a-f523-4c0c-b466-fbba76c457f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729610386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1729610386
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2749333944
Short name T596
Test name
Test status
Simulation time 37666526 ps
CPU time 1.06 seconds
Started Jul 14 05:28:26 PM PDT 24
Finished Jul 14 05:28:28 PM PDT 24
Peak memory 211304 kb
Host smart-c3c5d78f-0df7-41e4-a5ce-322605b67af6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749333944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2749333944
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2778007519
Short name T522
Test name
Test status
Simulation time 19664638 ps
CPU time 1.2 seconds
Started Jul 14 05:28:42 PM PDT 24
Finished Jul 14 05:28:44 PM PDT 24
Peak memory 208400 kb
Host smart-ce44c648-e478-4814-9cf9-5267d83a85dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778007519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2778007519
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2126803474
Short name T842
Test name
Test status
Simulation time 900564461 ps
CPU time 6.46 seconds
Started Jul 14 05:28:41 PM PDT 24
Finished Jul 14 05:28:48 PM PDT 24
Peak memory 216848 kb
Host smart-7be65344-1e4e-4f9c-9d42-0f189ea8773d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126803474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2126803474
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.677403303
Short name T237
Test name
Test status
Simulation time 3823860732 ps
CPU time 104.8 seconds
Started Jul 14 05:28:43 PM PDT 24
Finished Jul 14 05:30:28 PM PDT 24
Peak memory 218620 kb
Host smart-c0a8cc1a-7bc2-4a99-bf88-ff7acf01ffcb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677403303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er
rors.677403303
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.801973473
Short name T235
Test name
Test status
Simulation time 1688443320 ps
CPU time 7.29 seconds
Started Jul 14 05:28:37 PM PDT 24
Finished Jul 14 05:28:45 PM PDT 24
Peak memory 217592 kb
Host smart-1debe5e7-ebb2-4c74-8cd6-4e37f07c0760
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801973473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.801973473
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2933360728
Short name T845
Test name
Test status
Simulation time 2466889527 ps
CPU time 6.98 seconds
Started Jul 14 05:28:37 PM PDT 24
Finished Jul 14 05:28:45 PM PDT 24
Peak memory 217068 kb
Host smart-92a6d401-ea09-4868-8457-a2851f0000c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933360728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2933360728
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1793493193
Short name T457
Test name
Test status
Simulation time 3765495875 ps
CPU time 71.61 seconds
Started Jul 14 05:28:33 PM PDT 24
Finished Jul 14 05:29:45 PM PDT 24
Peak memory 277512 kb
Host smart-965a53bd-c415-47c0-bce6-6dd7050fec04
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793493193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.1793493193
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3669073743
Short name T245
Test name
Test status
Simulation time 582935585 ps
CPU time 22.24 seconds
Started Jul 14 05:28:34 PM PDT 24
Finished Jul 14 05:28:57 PM PDT 24
Peak memory 242188 kb
Host smart-1dca15bc-1e3d-4339-91b8-155b3d3889dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669073743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3669073743
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2845404993
Short name T311
Test name
Test status
Simulation time 82789846 ps
CPU time 3.37 seconds
Started Jul 14 05:28:36 PM PDT 24
Finished Jul 14 05:28:40 PM PDT 24
Peak memory 217700 kb
Host smart-36c84341-577f-4844-a42d-7df06ff68ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845404993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2845404993
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.520413181
Short name T535
Test name
Test status
Simulation time 264097865 ps
CPU time 12.7 seconds
Started Jul 14 05:28:41 PM PDT 24
Finished Jul 14 05:28:54 PM PDT 24
Peak memory 217608 kb
Host smart-5ee19251-edf7-438c-a7e7-0031d9319cee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520413181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.520413181
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2797197416
Short name T347
Test name
Test status
Simulation time 816544533 ps
CPU time 7.29 seconds
Started Jul 14 05:28:41 PM PDT 24
Finished Jul 14 05:28:49 PM PDT 24
Peak memory 225440 kb
Host smart-b2c5ac45-cdec-4d98-aa1b-0b9c18d41055
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797197416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2797197416
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1356050112
Short name T740
Test name
Test status
Simulation time 627899039 ps
CPU time 8.93 seconds
Started Jul 14 05:28:42 PM PDT 24
Finished Jul 14 05:28:52 PM PDT 24
Peak memory 217544 kb
Host smart-ed976bbe-a37e-4223-828e-5125c73d5d58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356050112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1356050112
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2798795923
Short name T721
Test name
Test status
Simulation time 586484236 ps
CPU time 8.65 seconds
Started Jul 14 05:28:34 PM PDT 24
Finished Jul 14 05:28:43 PM PDT 24
Peak memory 225020 kb
Host smart-88363272-23f5-4d71-aa4e-54d3324ff55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798795923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2798795923
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2553544943
Short name T525
Test name
Test status
Simulation time 20585714 ps
CPU time 1.55 seconds
Started Jul 14 05:28:32 PM PDT 24
Finished Jul 14 05:28:34 PM PDT 24
Peak memory 213160 kb
Host smart-7e3595de-bb70-4b01-8e5d-bbfa9afdf789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553544943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2553544943
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.85592520
Short name T101
Test name
Test status
Simulation time 922704386 ps
CPU time 25.64 seconds
Started Jul 14 05:28:36 PM PDT 24
Finished Jul 14 05:29:03 PM PDT 24
Peak memory 250304 kb
Host smart-d1f2cc03-33d9-477e-a26b-6f72bf0258ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85592520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.85592520
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1411632354
Short name T81
Test name
Test status
Simulation time 70121640 ps
CPU time 7.43 seconds
Started Jul 14 05:28:34 PM PDT 24
Finished Jul 14 05:28:42 PM PDT 24
Peak memory 247080 kb
Host smart-34eb5850-9df2-48a8-90ca-8ff3bde41771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411632354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1411632354
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2317334429
Short name T160
Test name
Test status
Simulation time 5503859541 ps
CPU time 48.4 seconds
Started Jul 14 05:28:39 PM PDT 24
Finished Jul 14 05:29:28 PM PDT 24
Peak memory 250648 kb
Host smart-21d5d253-40ec-42e4-9fc8-d5c7c5dd25a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317334429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2317334429
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.269569189
Short name T459
Test name
Test status
Simulation time 38652709 ps
CPU time 0.96 seconds
Started Jul 14 05:28:32 PM PDT 24
Finished Jul 14 05:28:34 PM PDT 24
Peak memory 211256 kb
Host smart-70d78ac0-63a8-4e98-b8e0-e0add225fe96
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269569189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_volatile_unlock_smoke.269569189
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1203008760
Short name T344
Test name
Test status
Simulation time 54947905 ps
CPU time 1.29 seconds
Started Jul 14 05:28:46 PM PDT 24
Finished Jul 14 05:28:48 PM PDT 24
Peak memory 208532 kb
Host smart-ea5e2c46-74ce-43fc-b4bf-a716d69657db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203008760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1203008760
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1393443135
Short name T508
Test name
Test status
Simulation time 489306146 ps
CPU time 17.06 seconds
Started Jul 14 05:28:40 PM PDT 24
Finished Jul 14 05:28:58 PM PDT 24
Peak memory 217664 kb
Host smart-d38f8f9c-916a-4e94-922a-43c3f9416343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393443135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1393443135
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2258088220
Short name T306
Test name
Test status
Simulation time 2352726641 ps
CPU time 14.27 seconds
Started Jul 14 05:28:38 PM PDT 24
Finished Jul 14 05:28:53 PM PDT 24
Peak memory 217200 kb
Host smart-b70fa81b-9266-427c-b479-73445e7bf96c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258088220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2258088220
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3027401977
Short name T275
Test name
Test status
Simulation time 8364569372 ps
CPU time 38.57 seconds
Started Jul 14 05:28:41 PM PDT 24
Finished Jul 14 05:29:20 PM PDT 24
Peak memory 218352 kb
Host smart-ad446aa7-5b97-40b5-8a52-002655ba191d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027401977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3027401977
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.686807239
Short name T149
Test name
Test status
Simulation time 336073065 ps
CPU time 6.67 seconds
Started Jul 14 05:28:40 PM PDT 24
Finished Jul 14 05:28:47 PM PDT 24
Peak memory 217616 kb
Host smart-86df186b-5b94-4f34-b101-f95d02f73495
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686807239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.686807239
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3790339547
Short name T816
Test name
Test status
Simulation time 97693092 ps
CPU time 2.12 seconds
Started Jul 14 05:28:38 PM PDT 24
Finished Jul 14 05:28:41 PM PDT 24
Peak memory 217040 kb
Host smart-e4446160-4850-4a77-b1cd-f5104cece175
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790339547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3790339547
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.587253013
Short name T319
Test name
Test status
Simulation time 11404602352 ps
CPU time 125.84 seconds
Started Jul 14 05:28:41 PM PDT 24
Finished Jul 14 05:30:48 PM PDT 24
Peak memory 278164 kb
Host smart-d339c576-1d1f-4ab8-91cb-6ed4e2b73aa1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587253013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_state_failure.587253013
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2391068570
Short name T795
Test name
Test status
Simulation time 1819514638 ps
CPU time 10.71 seconds
Started Jul 14 05:28:40 PM PDT 24
Finished Jul 14 05:28:51 PM PDT 24
Peak memory 223620 kb
Host smart-41ecdf51-ab2b-4980-9eb0-45caad8e59ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391068570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2391068570
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.4113411982
Short name T484
Test name
Test status
Simulation time 444729814 ps
CPU time 4.06 seconds
Started Jul 14 05:28:38 PM PDT 24
Finished Jul 14 05:28:43 PM PDT 24
Peak memory 217528 kb
Host smart-bb352954-7b8a-4fa3-a87f-45b596d4c29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113411982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.4113411982
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1572674735
Short name T312
Test name
Test status
Simulation time 315714599 ps
CPU time 17.07 seconds
Started Jul 14 05:28:48 PM PDT 24
Finished Jul 14 05:29:05 PM PDT 24
Peak memory 225576 kb
Host smart-d86b43c8-665f-4d72-a3e1-764172e30eeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572674735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1572674735
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3203151983
Short name T284
Test name
Test status
Simulation time 348609991 ps
CPU time 12.27 seconds
Started Jul 14 05:28:45 PM PDT 24
Finished Jul 14 05:28:58 PM PDT 24
Peak memory 225460 kb
Host smart-512dc7cb-e791-47ab-bfc7-fb33113af9d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203151983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3203151983
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1063025788
Short name T502
Test name
Test status
Simulation time 392892432 ps
CPU time 9.63 seconds
Started Jul 14 05:28:47 PM PDT 24
Finished Jul 14 05:28:57 PM PDT 24
Peak memory 225456 kb
Host smart-b6ec31d6-4fd9-45a7-9641-ae40d6a1f101
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063025788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1063025788
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1734616367
Short name T848
Test name
Test status
Simulation time 1000506770 ps
CPU time 7.08 seconds
Started Jul 14 05:28:39 PM PDT 24
Finished Jul 14 05:28:47 PM PDT 24
Peak memory 224656 kb
Host smart-bea0451c-3cbc-4373-aba5-35bb4bf94f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734616367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1734616367
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3197839425
Short name T380
Test name
Test status
Simulation time 54304654 ps
CPU time 2.16 seconds
Started Jul 14 05:28:43 PM PDT 24
Finished Jul 14 05:28:45 PM PDT 24
Peak memory 213720 kb
Host smart-5bf147d8-a417-4c31-af6a-a3b3abb53290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197839425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3197839425
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.729609746
Short name T627
Test name
Test status
Simulation time 329525895 ps
CPU time 29.15 seconds
Started Jul 14 05:28:39 PM PDT 24
Finished Jul 14 05:29:09 PM PDT 24
Peak memory 250424 kb
Host smart-63414ab4-7054-4968-a331-2e597a56cc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729609746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.729609746
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2356965507
Short name T443
Test name
Test status
Simulation time 264169745 ps
CPU time 8.13 seconds
Started Jul 14 05:28:42 PM PDT 24
Finished Jul 14 05:28:51 PM PDT 24
Peak memory 250388 kb
Host smart-c40203f4-b9e9-4946-87c4-21b00e5659e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356965507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2356965507
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.271549414
Short name T52
Test name
Test status
Simulation time 9645963611 ps
CPU time 171.44 seconds
Started Jul 14 05:28:43 PM PDT 24
Finished Jul 14 05:31:35 PM PDT 24
Peak memory 276228 kb
Host smart-5894f4a7-b2c8-4bf9-804a-3f09b0785d9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271549414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.271549414
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1804312329
Short name T268
Test name
Test status
Simulation time 310982551 ps
CPU time 12.87 seconds
Started Jul 14 05:28:45 PM PDT 24
Finished Jul 14 05:28:58 PM PDT 24
Peak memory 217688 kb
Host smart-0a843904-bf37-48fb-b357-26cdb434df57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804312329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1804312329
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3898835330
Short name T701
Test name
Test status
Simulation time 364152220 ps
CPU time 5.22 seconds
Started Jul 14 05:28:45 PM PDT 24
Finished Jul 14 05:28:51 PM PDT 24
Peak memory 216800 kb
Host smart-b4c3da1d-44f8-4028-b3a8-b0c2be86e43e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898835330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3898835330
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2064334995
Short name T313
Test name
Test status
Simulation time 20625754281 ps
CPU time 51.49 seconds
Started Jul 14 05:28:44 PM PDT 24
Finished Jul 14 05:29:36 PM PDT 24
Peak memory 218392 kb
Host smart-89cefb83-57f0-4371-82b0-78ed5f11e31d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064334995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2064334995
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2464708874
Short name T640
Test name
Test status
Simulation time 231036156 ps
CPU time 2.75 seconds
Started Jul 14 05:28:48 PM PDT 24
Finished Jul 14 05:28:51 PM PDT 24
Peak memory 220892 kb
Host smart-76c7e0aa-f901-4ac7-bc60-4e59d0c67225
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464708874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2464708874
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2166974684
Short name T304
Test name
Test status
Simulation time 349879379 ps
CPU time 8.53 seconds
Started Jul 14 05:28:47 PM PDT 24
Finished Jul 14 05:28:56 PM PDT 24
Peak memory 216996 kb
Host smart-2fe19efd-551d-415a-a1e4-fa3497999630
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166974684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2166974684
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2465324988
Short name T652
Test name
Test status
Simulation time 7454289246 ps
CPU time 73.38 seconds
Started Jul 14 05:28:44 PM PDT 24
Finished Jul 14 05:29:58 PM PDT 24
Peak memory 266860 kb
Host smart-7f501402-48b8-4ce6-918a-34ccbcf00a39
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465324988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2465324988
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2926590440
Short name T166
Test name
Test status
Simulation time 360319349 ps
CPU time 11.69 seconds
Started Jul 14 05:28:44 PM PDT 24
Finished Jul 14 05:28:56 PM PDT 24
Peak memory 225752 kb
Host smart-29231546-b601-4ecd-a48a-9e355cc815cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926590440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2926590440
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2417903449
Short name T630
Test name
Test status
Simulation time 34464716 ps
CPU time 1.93 seconds
Started Jul 14 05:28:45 PM PDT 24
Finished Jul 14 05:28:48 PM PDT 24
Peak memory 217700 kb
Host smart-3279ba88-615d-4371-a493-9a2b7d34d09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417903449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2417903449
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1707315559
Short name T309
Test name
Test status
Simulation time 334417644 ps
CPU time 13.08 seconds
Started Jul 14 05:28:51 PM PDT 24
Finished Jul 14 05:29:05 PM PDT 24
Peak memory 225404 kb
Host smart-818c43d5-d79c-4c0c-b5d4-9578472f6ac0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707315559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1707315559
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.871138404
Short name T658
Test name
Test status
Simulation time 6437766304 ps
CPU time 12.37 seconds
Started Jul 14 05:28:51 PM PDT 24
Finished Jul 14 05:29:04 PM PDT 24
Peak memory 225496 kb
Host smart-48ba8cb2-e9a3-4f28-9a9f-a66d0dde2f76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871138404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.871138404
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.1956549961
Short name T98
Test name
Test status
Simulation time 1208934356 ps
CPU time 9.79 seconds
Started Jul 14 05:28:46 PM PDT 24
Finished Jul 14 05:28:56 PM PDT 24
Peak memory 225436 kb
Host smart-2c238443-223d-41ed-ac6d-5cee467a60c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956549961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1956549961
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1470656885
Short name T425
Test name
Test status
Simulation time 286775761 ps
CPU time 3.49 seconds
Started Jul 14 05:28:44 PM PDT 24
Finished Jul 14 05:28:48 PM PDT 24
Peak memory 217144 kb
Host smart-8fdbc6cf-7cae-4a4f-92df-2e6ff5e93a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470656885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1470656885
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.4156330675
Short name T478
Test name
Test status
Simulation time 2724098402 ps
CPU time 31.62 seconds
Started Jul 14 05:28:46 PM PDT 24
Finished Jul 14 05:29:18 PM PDT 24
Peak memory 250436 kb
Host smart-c80404c9-5ffb-4803-8da6-7f6705997209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156330675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.4156330675
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.773160248
Short name T561
Test name
Test status
Simulation time 307376431 ps
CPU time 9.85 seconds
Started Jul 14 05:28:47 PM PDT 24
Finished Jul 14 05:28:57 PM PDT 24
Peak memory 250436 kb
Host smart-2557afa8-def3-4cf1-a8bb-67291848893a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773160248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.773160248
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3958772544
Short name T476
Test name
Test status
Simulation time 9413251466 ps
CPU time 82.82 seconds
Started Jul 14 05:28:51 PM PDT 24
Finished Jul 14 05:30:14 PM PDT 24
Peak memory 225556 kb
Host smart-7000eca6-b235-44c5-9121-26afc2051c6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958772544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3958772544
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1835076534
Short name T581
Test name
Test status
Simulation time 23973933 ps
CPU time 1.03 seconds
Started Jul 14 05:28:44 PM PDT 24
Finished Jul 14 05:28:45 PM PDT 24
Peak memory 211208 kb
Host smart-b57df218-db84-4825-9086-b3b23d494891
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835076534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.1835076534
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2366995371
Short name T693
Test name
Test status
Simulation time 16782925 ps
CPU time 1.05 seconds
Started Jul 14 05:28:56 PM PDT 24
Finished Jul 14 05:28:59 PM PDT 24
Peak memory 208436 kb
Host smart-bf74cbd0-a188-4cd2-8ce4-bb1cd2d0f6da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366995371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2366995371
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1556656825
Short name T150
Test name
Test status
Simulation time 363878286 ps
CPU time 17.88 seconds
Started Jul 14 05:28:50 PM PDT 24
Finished Jul 14 05:29:08 PM PDT 24
Peak memory 217712 kb
Host smart-53972013-7fea-4b20-8214-d191f89eb854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556656825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1556656825
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2261024613
Short name T579
Test name
Test status
Simulation time 479368570 ps
CPU time 13.04 seconds
Started Jul 14 05:28:53 PM PDT 24
Finished Jul 14 05:29:06 PM PDT 24
Peak memory 216620 kb
Host smart-758f6b4d-3d06-4a11-a39a-a6c02a629be0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261024613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2261024613
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.880331575
Short name T432
Test name
Test status
Simulation time 2408226661 ps
CPU time 18.69 seconds
Started Jul 14 05:28:49 PM PDT 24
Finished Jul 14 05:29:08 PM PDT 24
Peak memory 218460 kb
Host smart-5cbac0cc-0a50-481b-890a-c4334ff59729
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880331575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.880331575
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.142759661
Short name T718
Test name
Test status
Simulation time 1166951371 ps
CPU time 5.21 seconds
Started Jul 14 05:28:53 PM PDT 24
Finished Jul 14 05:28:58 PM PDT 24
Peak memory 221344 kb
Host smart-9d5751fc-ee68-49fd-b30c-310e8af51b7d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142759661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.142759661
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.718278519
Short name T799
Test name
Test status
Simulation time 319298405 ps
CPU time 3.33 seconds
Started Jul 14 05:28:50 PM PDT 24
Finished Jul 14 05:28:53 PM PDT 24
Peak memory 217000 kb
Host smart-f85d02ed-aadb-4558-aac8-1ab62aa8d0e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718278519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
718278519
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3092538414
Short name T765
Test name
Test status
Simulation time 966434102 ps
CPU time 29.15 seconds
Started Jul 14 05:28:52 PM PDT 24
Finished Jul 14 05:29:22 PM PDT 24
Peak memory 250136 kb
Host smart-67f4bb28-1dc0-4ae8-b1c3-fe4723564082
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092538414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3092538414
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.191597428
Short name T576
Test name
Test status
Simulation time 2020930516 ps
CPU time 6.72 seconds
Started Jul 14 05:28:51 PM PDT 24
Finished Jul 14 05:28:59 PM PDT 24
Peak memory 222236 kb
Host smart-3ddf900b-caf4-46d7-9a70-7de345547f56
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191597428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.191597428
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3856171810
Short name T832
Test name
Test status
Simulation time 1404711903 ps
CPU time 2.91 seconds
Started Jul 14 05:28:51 PM PDT 24
Finished Jul 14 05:28:55 PM PDT 24
Peak memory 217624 kb
Host smart-38edfeb9-e408-4ab7-8619-e1c3dda2fe80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856171810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3856171810
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.310278695
Short name T803
Test name
Test status
Simulation time 1492288834 ps
CPU time 13.76 seconds
Started Jul 14 05:28:48 PM PDT 24
Finished Jul 14 05:29:02 PM PDT 24
Peak memory 218416 kb
Host smart-103c69c0-8d34-4861-89ba-de72684e4263
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310278695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.310278695
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1889872164
Short name T726
Test name
Test status
Simulation time 264042292 ps
CPU time 13.26 seconds
Started Jul 14 05:28:49 PM PDT 24
Finished Jul 14 05:29:03 PM PDT 24
Peak memory 225444 kb
Host smart-eb32ebb4-b413-4ba3-b75c-c30ddb4a3f02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889872164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1889872164
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2150950367
Short name T805
Test name
Test status
Simulation time 2000900441 ps
CPU time 7 seconds
Started Jul 14 05:28:52 PM PDT 24
Finished Jul 14 05:29:00 PM PDT 24
Peak memory 217376 kb
Host smart-54d24d7f-6362-477c-9066-ac8c46b1daf9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150950367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2150950367
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1547949756
Short name T531
Test name
Test status
Simulation time 1100964814 ps
CPU time 9.84 seconds
Started Jul 14 05:28:49 PM PDT 24
Finished Jul 14 05:28:59 PM PDT 24
Peak memory 224556 kb
Host smart-144b0bbc-f480-46eb-baaa-94cea4660f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547949756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1547949756
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.33998720
Short name T836
Test name
Test status
Simulation time 132758081 ps
CPU time 2.8 seconds
Started Jul 14 05:28:52 PM PDT 24
Finished Jul 14 05:28:55 PM PDT 24
Peak memory 223600 kb
Host smart-7500b851-e694-4b40-a14f-489e5077409c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33998720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.33998720
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.4112631405
Short name T621
Test name
Test status
Simulation time 2089160713 ps
CPU time 31.05 seconds
Started Jul 14 05:28:50 PM PDT 24
Finished Jul 14 05:29:22 PM PDT 24
Peak memory 250436 kb
Host smart-7ac2618b-f1b9-478e-97f7-1d4456b6c2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112631405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.4112631405
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2306346565
Short name T772
Test name
Test status
Simulation time 371673141 ps
CPU time 3.95 seconds
Started Jul 14 05:28:52 PM PDT 24
Finished Jul 14 05:28:56 PM PDT 24
Peak memory 225832 kb
Host smart-19be995d-ab6b-4aa3-a9ab-21453943d27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306346565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2306346565
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.178184411
Short name T39
Test name
Test status
Simulation time 10808179308 ps
CPU time 189.92 seconds
Started Jul 14 05:28:50 PM PDT 24
Finished Jul 14 05:32:01 PM PDT 24
Peak memory 275068 kb
Host smart-a59a04db-512e-44ab-995f-68bc582fda92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178184411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.178184411
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.844674470
Short name T258
Test name
Test status
Simulation time 10554396 ps
CPU time 0.87 seconds
Started Jul 14 05:28:50 PM PDT 24
Finished Jul 14 05:28:52 PM PDT 24
Peak memory 208500 kb
Host smart-fd4c4ed7-f5d4-4fa3-b68f-0ed578b4909b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844674470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.844674470
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.4131731185
Short name T259
Test name
Test status
Simulation time 79821380 ps
CPU time 1 seconds
Started Jul 14 05:29:04 PM PDT 24
Finished Jul 14 05:29:05 PM PDT 24
Peak memory 208492 kb
Host smart-175d93a1-3f24-4db2-8f96-0d3d49eeda03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131731185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.4131731185
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2246905706
Short name T818
Test name
Test status
Simulation time 989575825 ps
CPU time 8.45 seconds
Started Jul 14 05:28:56 PM PDT 24
Finished Jul 14 05:29:05 PM PDT 24
Peak memory 217680 kb
Host smart-5db64f23-f0b7-4532-a662-6525e4a1938a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246905706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2246905706
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2360224643
Short name T23
Test name
Test status
Simulation time 1490254884 ps
CPU time 16.58 seconds
Started Jul 14 05:28:55 PM PDT 24
Finished Jul 14 05:29:12 PM PDT 24
Peak memory 217116 kb
Host smart-1420c2f8-b021-461c-8c63-6a0ae589e567
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360224643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2360224643
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1434361702
Short name T14
Test name
Test status
Simulation time 11659433686 ps
CPU time 42.93 seconds
Started Jul 14 05:28:57 PM PDT 24
Finished Jul 14 05:29:41 PM PDT 24
Peak memory 219072 kb
Host smart-66d120e6-bfa1-4c2d-b9c2-ff19be7225fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434361702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1434361702
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.486193116
Short name T724
Test name
Test status
Simulation time 962822313 ps
CPU time 4.27 seconds
Started Jul 14 05:28:56 PM PDT 24
Finished Jul 14 05:29:01 PM PDT 24
Peak memory 217668 kb
Host smart-74b64973-b5ef-4e6e-a2be-14344ea1022e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486193116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.486193116
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2756844555
Short name T692
Test name
Test status
Simulation time 1068555836 ps
CPU time 3.81 seconds
Started Jul 14 05:28:59 PM PDT 24
Finished Jul 14 05:29:03 PM PDT 24
Peak memory 216952 kb
Host smart-7fdb60cc-9c0e-470e-a359-57c081671de3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756844555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2756844555
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.343683785
Short name T471
Test name
Test status
Simulation time 2314667101 ps
CPU time 50.79 seconds
Started Jul 14 05:28:56 PM PDT 24
Finished Jul 14 05:29:47 PM PDT 24
Peak memory 277272 kb
Host smart-179b3f96-145b-43af-a3c1-28b9746e38f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343683785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.343683785
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1526064356
Short name T352
Test name
Test status
Simulation time 665971653 ps
CPU time 15 seconds
Started Jul 14 05:28:58 PM PDT 24
Finished Jul 14 05:29:14 PM PDT 24
Peak memory 246080 kb
Host smart-b4f33ed7-1eb4-47fc-80ad-5cd260a41d62
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526064356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1526064356
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1644658345
Short name T173
Test name
Test status
Simulation time 106631161 ps
CPU time 3.47 seconds
Started Jul 14 05:28:54 PM PDT 24
Finished Jul 14 05:28:58 PM PDT 24
Peak memory 217720 kb
Host smart-8b7513f4-50b1-4876-931e-0c18cf822d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644658345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1644658345
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3232517862
Short name T700
Test name
Test status
Simulation time 1110364054 ps
CPU time 9.74 seconds
Started Jul 14 05:28:57 PM PDT 24
Finished Jul 14 05:29:07 PM PDT 24
Peak memory 217556 kb
Host smart-66b8c9f1-0445-4e60-8cf1-64212d9d4f5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232517862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3232517862
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2489514408
Short name T30
Test name
Test status
Simulation time 453245756 ps
CPU time 12.58 seconds
Started Jul 14 05:28:57 PM PDT 24
Finished Jul 14 05:29:10 PM PDT 24
Peak memory 225456 kb
Host smart-d561321c-120a-4ce9-88a8-5646d466036b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489514408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2489514408
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.831350440
Short name T403
Test name
Test status
Simulation time 1267652433 ps
CPU time 7.53 seconds
Started Jul 14 05:28:56 PM PDT 24
Finished Jul 14 05:29:05 PM PDT 24
Peak memory 225444 kb
Host smart-ce99c73b-d4db-4da9-ae26-d5425cc9b6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831350440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.831350440
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.144629900
Short name T536
Test name
Test status
Simulation time 979015877 ps
CPU time 4.47 seconds
Started Jul 14 05:28:55 PM PDT 24
Finished Jul 14 05:29:00 PM PDT 24
Peak memory 217088 kb
Host smart-bb712563-d882-45ca-9743-35f33ba6f623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144629900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.144629900
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2406609613
Short name T829
Test name
Test status
Simulation time 2038122980 ps
CPU time 30.12 seconds
Started Jul 14 05:28:56 PM PDT 24
Finished Jul 14 05:29:27 PM PDT 24
Peak memory 250448 kb
Host smart-61f4dbe1-0de3-4566-8e6d-cef06d609e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406609613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2406609613
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.4187212705
Short name T323
Test name
Test status
Simulation time 360187956 ps
CPU time 6.65 seconds
Started Jul 14 05:29:01 PM PDT 24
Finished Jul 14 05:29:08 PM PDT 24
Peak memory 243900 kb
Host smart-8f1ab193-9919-4a4d-ab55-0d4f33fdc320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187212705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.4187212705
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.523761169
Short name T224
Test name
Test status
Simulation time 3136488979 ps
CPU time 53.7 seconds
Started Jul 14 05:28:56 PM PDT 24
Finished Jul 14 05:29:51 PM PDT 24
Peak memory 225452 kb
Host smart-715960f5-fb31-4776-b2dd-30fc9b0e1db0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523761169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.523761169
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2161474117
Short name T406
Test name
Test status
Simulation time 20341517 ps
CPU time 1.06 seconds
Started Jul 14 05:28:57 PM PDT 24
Finished Jul 14 05:28:59 PM PDT 24
Peak memory 217124 kb
Host smart-8186b612-b8cb-480f-98c7-8254ec4f3c36
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161474117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2161474117
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.565080390
Short name T493
Test name
Test status
Simulation time 19054290 ps
CPU time 0.96 seconds
Started Jul 14 05:29:03 PM PDT 24
Finished Jul 14 05:29:05 PM PDT 24
Peak memory 208500 kb
Host smart-7c9884ea-9b6c-49b8-b1cd-575a07cfa4e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565080390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.565080390
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.4282891333
Short name T223
Test name
Test status
Simulation time 321252963 ps
CPU time 10.04 seconds
Started Jul 14 05:29:03 PM PDT 24
Finished Jul 14 05:29:13 PM PDT 24
Peak memory 225436 kb
Host smart-c4124ea8-22d2-40e2-9036-b526dbaf400a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282891333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.4282891333
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.268656141
Short name T371
Test name
Test status
Simulation time 1345417589 ps
CPU time 15.54 seconds
Started Jul 14 05:29:03 PM PDT 24
Finished Jul 14 05:29:19 PM PDT 24
Peak memory 216764 kb
Host smart-b558b030-5cc1-4d4e-b43e-30d98446f688
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268656141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.268656141
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1718178672
Short name T393
Test name
Test status
Simulation time 3506805018 ps
CPU time 45.55 seconds
Started Jul 14 05:29:05 PM PDT 24
Finished Jul 14 05:29:52 PM PDT 24
Peak memory 218612 kb
Host smart-80999d73-4e5b-466f-8e0c-e4fdaa0b2eeb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718178672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1718178672
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1162239396
Short name T16
Test name
Test status
Simulation time 695068031 ps
CPU time 11.22 seconds
Started Jul 14 05:29:06 PM PDT 24
Finished Jul 14 05:29:18 PM PDT 24
Peak memory 217588 kb
Host smart-7556cf51-dfa6-468c-bcdc-c4425c9ca97e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162239396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1162239396
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3081689764
Short name T505
Test name
Test status
Simulation time 574576931 ps
CPU time 7.95 seconds
Started Jul 14 05:29:04 PM PDT 24
Finished Jul 14 05:29:13 PM PDT 24
Peak memory 217052 kb
Host smart-eae407a2-6dce-4490-ae93-7df3c4e637ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081689764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3081689764
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1790086642
Short name T856
Test name
Test status
Simulation time 4044650822 ps
CPU time 32.3 seconds
Started Jul 14 05:29:03 PM PDT 24
Finished Jul 14 05:29:36 PM PDT 24
Peak memory 250528 kb
Host smart-b4a447ac-c8bc-4d53-8ae1-ff6e3e9840eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790086642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1790086642
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2371761773
Short name T92
Test name
Test status
Simulation time 6699413569 ps
CPU time 10.49 seconds
Started Jul 14 05:29:03 PM PDT 24
Finished Jul 14 05:29:14 PM PDT 24
Peak memory 246572 kb
Host smart-666154a9-76cf-4c62-9b07-5ff0be7c0e28
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371761773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.2371761773
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.4043957305
Short name T263
Test name
Test status
Simulation time 192261975 ps
CPU time 2.52 seconds
Started Jul 14 05:29:05 PM PDT 24
Finished Jul 14 05:29:08 PM PDT 24
Peak memory 221924 kb
Host smart-28434d9c-b5dc-4eea-949a-d92d1a742817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043957305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.4043957305
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.370995605
Short name T40
Test name
Test status
Simulation time 1273275748 ps
CPU time 15.13 seconds
Started Jul 14 05:29:02 PM PDT 24
Finished Jul 14 05:29:18 PM PDT 24
Peak memory 218428 kb
Host smart-672a4cdd-ea62-4932-b654-743aae0108ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370995605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.370995605
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.779994880
Short name T533
Test name
Test status
Simulation time 276807747 ps
CPU time 12.26 seconds
Started Jul 14 05:29:03 PM PDT 24
Finished Jul 14 05:29:16 PM PDT 24
Peak memory 225396 kb
Host smart-ba2f0fb8-e83d-444c-b194-fded34a6673b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779994880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.779994880
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3436474399
Short name T423
Test name
Test status
Simulation time 1792596592 ps
CPU time 11.53 seconds
Started Jul 14 05:29:03 PM PDT 24
Finished Jul 14 05:29:15 PM PDT 24
Peak memory 225416 kb
Host smart-ca4c928b-03f3-4e95-b648-a29d8aa5cec6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436474399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3436474399
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.504014430
Short name T307
Test name
Test status
Simulation time 772067132 ps
CPU time 10.03 seconds
Started Jul 14 05:29:01 PM PDT 24
Finished Jul 14 05:29:12 PM PDT 24
Peak memory 225500 kb
Host smart-5420e7d6-f9b1-47cb-a9da-5d51277e8bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504014430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.504014430
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1702657964
Short name T80
Test name
Test status
Simulation time 22305363 ps
CPU time 1.4 seconds
Started Jul 14 05:29:01 PM PDT 24
Finished Jul 14 05:29:02 PM PDT 24
Peak memory 213096 kb
Host smart-d0eac638-6258-4ae6-bb05-deb379825d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702657964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1702657964
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1027947880
Short name T639
Test name
Test status
Simulation time 241499657 ps
CPU time 31.3 seconds
Started Jul 14 05:29:02 PM PDT 24
Finished Jul 14 05:29:34 PM PDT 24
Peak memory 245816 kb
Host smart-2d227e6e-4ddd-4517-adef-342cf187a8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027947880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1027947880
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2530564040
Short name T731
Test name
Test status
Simulation time 228606764 ps
CPU time 6.89 seconds
Started Jul 14 05:29:03 PM PDT 24
Finished Jul 14 05:29:11 PM PDT 24
Peak memory 249944 kb
Host smart-ebb48b6f-ef9d-4229-a511-95f52c985f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530564040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2530564040
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3329880684
Short name T702
Test name
Test status
Simulation time 35894860 ps
CPU time 0.99 seconds
Started Jul 14 05:29:02 PM PDT 24
Finished Jul 14 05:29:04 PM PDT 24
Peak memory 211344 kb
Host smart-e697f285-8470-45de-b1ab-70f710af99a4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329880684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3329880684
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.554202492
Short name T472
Test name
Test status
Simulation time 24162876 ps
CPU time 1.29 seconds
Started Jul 14 05:29:08 PM PDT 24
Finished Jul 14 05:29:10 PM PDT 24
Peak memory 208444 kb
Host smart-e0fa2788-f906-49e3-9a2f-be5281122d91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554202492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.554202492
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2803025301
Short name T176
Test name
Test status
Simulation time 1721928795 ps
CPU time 17.24 seconds
Started Jul 14 05:29:08 PM PDT 24
Finished Jul 14 05:29:26 PM PDT 24
Peak memory 225476 kb
Host smart-d415b87c-d0bf-462b-86be-fff72fe3814f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803025301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2803025301
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1832821431
Short name T826
Test name
Test status
Simulation time 2176782146 ps
CPU time 6.25 seconds
Started Jul 14 05:29:09 PM PDT 24
Finished Jul 14 05:29:16 PM PDT 24
Peak memory 217124 kb
Host smart-771d46be-a87d-425d-a3b8-9e6957ee7d6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832821431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1832821431
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1185327041
Short name T221
Test name
Test status
Simulation time 8393227159 ps
CPU time 31.49 seconds
Started Jul 14 05:29:08 PM PDT 24
Finished Jul 14 05:29:40 PM PDT 24
Peak memory 219008 kb
Host smart-0e82d3b4-4c84-49ed-9fca-4c89d94db440
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185327041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1185327041
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3209145428
Short name T586
Test name
Test status
Simulation time 1382371525 ps
CPU time 11 seconds
Started Jul 14 05:29:09 PM PDT 24
Finished Jul 14 05:29:20 PM PDT 24
Peak memory 217644 kb
Host smart-ebd053c9-7464-4575-bd92-1497210e48f6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209145428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3209145428
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.202705627
Short name T599
Test name
Test status
Simulation time 111579976 ps
CPU time 2.39 seconds
Started Jul 14 05:29:08 PM PDT 24
Finished Jul 14 05:29:11 PM PDT 24
Peak memory 217084 kb
Host smart-201828db-974b-46ec-b459-8bc38fab2f0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202705627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
202705627
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2304088742
Short name T813
Test name
Test status
Simulation time 6940670347 ps
CPU time 77.98 seconds
Started Jul 14 05:29:09 PM PDT 24
Finished Jul 14 05:30:28 PM PDT 24
Peak memory 276684 kb
Host smart-99d60dbe-53a1-4be4-b8ce-a73bf666e02f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304088742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2304088742
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3829548435
Short name T361
Test name
Test status
Simulation time 1349409071 ps
CPU time 12.84 seconds
Started Jul 14 05:29:07 PM PDT 24
Finished Jul 14 05:29:20 PM PDT 24
Peak memory 250320 kb
Host smart-ad1cd818-aebc-4eda-acc2-4935bea94ff3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829548435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3829548435
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3198994943
Short name T228
Test name
Test status
Simulation time 134125277 ps
CPU time 2.42 seconds
Started Jul 14 05:29:05 PM PDT 24
Finished Jul 14 05:29:08 PM PDT 24
Peak memory 217696 kb
Host smart-c877718a-b72c-41c6-91c0-47c07a56434c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198994943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3198994943
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1727231087
Short name T175
Test name
Test status
Simulation time 258895103 ps
CPU time 12.16 seconds
Started Jul 14 05:29:06 PM PDT 24
Finished Jul 14 05:29:19 PM PDT 24
Peak memory 217608 kb
Host smart-be3eec58-f11b-4763-b9b9-0c8d99eccb0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727231087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1727231087
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.4123206977
Short name T270
Test name
Test status
Simulation time 1406222430 ps
CPU time 15.29 seconds
Started Jul 14 05:29:07 PM PDT 24
Finished Jul 14 05:29:24 PM PDT 24
Peak memory 225412 kb
Host smart-ed96f841-98b5-4227-a0cd-851260e713c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123206977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.4123206977
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.256519219
Short name T370
Test name
Test status
Simulation time 533474120 ps
CPU time 10.32 seconds
Started Jul 14 05:29:07 PM PDT 24
Finished Jul 14 05:29:19 PM PDT 24
Peak memory 225416 kb
Host smart-a5b1f9a4-cb4a-4dc6-ad09-6635d3d64707
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256519219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.256519219
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.817628884
Short name T440
Test name
Test status
Simulation time 3122032031 ps
CPU time 8.19 seconds
Started Jul 14 05:29:06 PM PDT 24
Finished Jul 14 05:29:15 PM PDT 24
Peak memory 225540 kb
Host smart-a14a1db9-3398-468c-b7bb-006a737f8528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817628884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.817628884
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3916366674
Short name T550
Test name
Test status
Simulation time 614743403 ps
CPU time 4.67 seconds
Started Jul 14 05:29:04 PM PDT 24
Finished Jul 14 05:29:10 PM PDT 24
Peak memory 214284 kb
Host smart-9d6f7795-f6b0-491d-8f7b-f5057a01a474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916366674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3916366674
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.440067289
Short name T578
Test name
Test status
Simulation time 469977417 ps
CPU time 17.86 seconds
Started Jul 14 05:29:02 PM PDT 24
Finished Jul 14 05:29:21 PM PDT 24
Peak memory 250404 kb
Host smart-d1a41b55-9850-4258-b491-966fca56b1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440067289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.440067289
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3181397309
Short name T791
Test name
Test status
Simulation time 275796218 ps
CPU time 3.11 seconds
Started Jul 14 05:29:02 PM PDT 24
Finished Jul 14 05:29:05 PM PDT 24
Peak memory 223788 kb
Host smart-6d5b06e5-2eba-425d-8d41-46bd93b975ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181397309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3181397309
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3214539701
Short name T467
Test name
Test status
Simulation time 38835212606 ps
CPU time 349.87 seconds
Started Jul 14 05:29:07 PM PDT 24
Finished Jul 14 05:34:57 PM PDT 24
Peak memory 269988 kb
Host smart-1f282988-7288-4e07-b5cd-f9488a8c8a90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214539701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3214539701
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2374503396
Short name T464
Test name
Test status
Simulation time 13845391 ps
CPU time 0.95 seconds
Started Jul 14 05:29:03 PM PDT 24
Finished Jul 14 05:29:05 PM PDT 24
Peak memory 211264 kb
Host smart-86e13a0e-8327-4308-9a43-7ec887203555
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374503396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2374503396
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2686615083
Short name T271
Test name
Test status
Simulation time 52467908 ps
CPU time 0.98 seconds
Started Jul 14 05:29:19 PM PDT 24
Finished Jul 14 05:29:21 PM PDT 24
Peak memory 208428 kb
Host smart-4b9fd5c5-3e92-4ffe-b3f7-512c7870a1d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686615083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2686615083
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.1161452882
Short name T849
Test name
Test status
Simulation time 538965942 ps
CPU time 13.45 seconds
Started Jul 14 05:29:15 PM PDT 24
Finished Jul 14 05:29:29 PM PDT 24
Peak memory 225436 kb
Host smart-e265e50e-e4d7-4a5d-beca-8eb085584fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161452882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1161452882
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1931034997
Short name T766
Test name
Test status
Simulation time 1077635001 ps
CPU time 11.1 seconds
Started Jul 14 05:29:16 PM PDT 24
Finished Jul 14 05:29:28 PM PDT 24
Peak memory 216900 kb
Host smart-8902335a-6094-45a4-b422-f946a7af1976
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931034997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1931034997
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1460228185
Short name T587
Test name
Test status
Simulation time 12951315707 ps
CPU time 36.39 seconds
Started Jul 14 05:29:13 PM PDT 24
Finished Jul 14 05:29:49 PM PDT 24
Peak memory 218336 kb
Host smart-93e23316-ed34-4e36-8976-7687bae52fa5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460228185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1460228185
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.404688806
Short name T619
Test name
Test status
Simulation time 1335580988 ps
CPU time 7.71 seconds
Started Jul 14 05:29:11 PM PDT 24
Finished Jul 14 05:29:19 PM PDT 24
Peak memory 217656 kb
Host smart-8daf812f-652e-4918-943d-7ae79efb666e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404688806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.404688806
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2488747638
Short name T348
Test name
Test status
Simulation time 754367163 ps
CPU time 3.71 seconds
Started Jul 14 05:29:11 PM PDT 24
Finished Jul 14 05:29:15 PM PDT 24
Peak memory 217016 kb
Host smart-8da30fb8-0bbb-4c74-8940-1ec39b2ea3f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488747638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2488747638
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.38107197
Short name T827
Test name
Test status
Simulation time 47159528812 ps
CPU time 84.02 seconds
Started Jul 14 05:29:11 PM PDT 24
Finished Jul 14 05:30:36 PM PDT 24
Peak memory 282480 kb
Host smart-b30fbf05-7d34-4d96-9302-00d54ccbfe4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38107197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_state_failure.38107197
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3412728593
Short name T96
Test name
Test status
Simulation time 619411585 ps
CPU time 14.57 seconds
Started Jul 14 05:29:18 PM PDT 24
Finished Jul 14 05:29:34 PM PDT 24
Peak memory 249848 kb
Host smart-9514f0fe-a4a9-4164-b102-7c391f72a5c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412728593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3412728593
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2065357051
Short name T770
Test name
Test status
Simulation time 370200151 ps
CPU time 3.4 seconds
Started Jul 14 05:29:13 PM PDT 24
Finished Jul 14 05:29:17 PM PDT 24
Peak memory 217720 kb
Host smart-f091af44-6e82-4fb0-a137-c2ad84e82a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065357051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2065357051
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.4101398144
Short name T308
Test name
Test status
Simulation time 378705310 ps
CPU time 11.95 seconds
Started Jul 14 05:29:19 PM PDT 24
Finished Jul 14 05:29:32 PM PDT 24
Peak memory 217620 kb
Host smart-cf89d051-2585-45e3-a351-1e15d6f434e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101398144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.4101398144
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.2900780366
Short name T528
Test name
Test status
Simulation time 940424880 ps
CPU time 10.09 seconds
Started Jul 14 05:29:13 PM PDT 24
Finished Jul 14 05:29:24 PM PDT 24
Peak memory 217680 kb
Host smart-3b4a00f3-f3bb-4c8e-b200-587d62667ea3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900780366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.2900780366
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1528568093
Short name T750
Test name
Test status
Simulation time 925473645 ps
CPU time 6.55 seconds
Started Jul 14 05:29:13 PM PDT 24
Finished Jul 14 05:29:20 PM PDT 24
Peak memory 217668 kb
Host smart-4c3ae97f-797f-47da-855b-31570800fd1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528568093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1528568093
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.447757655
Short name T377
Test name
Test status
Simulation time 75381675 ps
CPU time 1.49 seconds
Started Jul 14 05:29:07 PM PDT 24
Finished Jul 14 05:29:09 PM PDT 24
Peak memory 213144 kb
Host smart-f80e33f3-db81-45cc-92d1-60d5e8a4145a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447757655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.447757655
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2474372848
Short name T734
Test name
Test status
Simulation time 1523711881 ps
CPU time 28.3 seconds
Started Jul 14 05:29:08 PM PDT 24
Finished Jul 14 05:29:37 PM PDT 24
Peak memory 250484 kb
Host smart-abfb4666-0d98-4052-b971-2673f31d918e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474372848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2474372848
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.65396401
Short name T351
Test name
Test status
Simulation time 349590861 ps
CPU time 7.03 seconds
Started Jul 14 05:29:18 PM PDT 24
Finished Jul 14 05:29:27 PM PDT 24
Peak memory 246644 kb
Host smart-7d6bf491-d31c-44cb-a6d4-2881d89f6a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65396401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.65396401
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.494396018
Short name T682
Test name
Test status
Simulation time 2450481774 ps
CPU time 66.41 seconds
Started Jul 14 05:29:12 PM PDT 24
Finished Jul 14 05:30:19 PM PDT 24
Peak memory 251880 kb
Host smart-1345912a-06ec-4122-8fa3-aaeb89b0caf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494396018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.494396018
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3729794515
Short name T788
Test name
Test status
Simulation time 36854882 ps
CPU time 0.89 seconds
Started Jul 14 05:29:09 PM PDT 24
Finished Jul 14 05:29:10 PM PDT 24
Peak memory 211320 kb
Host smart-78a03645-70d1-41e5-b560-83a3523fd4c9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729794515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.3729794515
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3226181260
Short name T714
Test name
Test status
Simulation time 51141064 ps
CPU time 0.86 seconds
Started Jul 14 05:29:20 PM PDT 24
Finished Jul 14 05:29:22 PM PDT 24
Peak memory 208332 kb
Host smart-70d757ac-ec33-4951-ae25-18ecd324f669
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226181260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3226181260
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1886580855
Short name T409
Test name
Test status
Simulation time 167477555 ps
CPU time 9.04 seconds
Started Jul 14 05:29:21 PM PDT 24
Finished Jul 14 05:29:30 PM PDT 24
Peak memory 217628 kb
Host smart-f6e63caa-77aa-41b3-8810-aad73e98e5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886580855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1886580855
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2260400946
Short name T449
Test name
Test status
Simulation time 1289463731 ps
CPU time 3.41 seconds
Started Jul 14 05:29:18 PM PDT 24
Finished Jul 14 05:29:22 PM PDT 24
Peak memory 216624 kb
Host smart-77646517-a87e-47ee-967c-1b3ebb25cf5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260400946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2260400946
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3637950768
Short name T372
Test name
Test status
Simulation time 2735450206 ps
CPU time 39.38 seconds
Started Jul 14 05:29:17 PM PDT 24
Finished Jul 14 05:29:58 PM PDT 24
Peak memory 218344 kb
Host smart-4f800e29-550d-4d7a-981e-4c1fb41a9eb7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637950768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3637950768
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.815340532
Short name T404
Test name
Test status
Simulation time 1900464500 ps
CPU time 9.72 seconds
Started Jul 14 05:29:19 PM PDT 24
Finished Jul 14 05:29:30 PM PDT 24
Peak memory 223636 kb
Host smart-918422ff-ba92-4e7b-900f-7d767d6ffbf9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815340532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.815340532
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2053087845
Short name T346
Test name
Test status
Simulation time 346466130 ps
CPU time 5.92 seconds
Started Jul 14 05:29:19 PM PDT 24
Finished Jul 14 05:29:26 PM PDT 24
Peak memory 217064 kb
Host smart-5592edd0-ae0d-40d8-b649-a660d21f57f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053087845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2053087845
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2336908680
Short name T669
Test name
Test status
Simulation time 2793678108 ps
CPU time 36.73 seconds
Started Jul 14 05:29:21 PM PDT 24
Finished Jul 14 05:29:58 PM PDT 24
Peak memory 250444 kb
Host smart-79879421-5cde-459d-8077-76777f442249
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336908680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2336908680
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.967597953
Short name T446
Test name
Test status
Simulation time 1142296468 ps
CPU time 21.07 seconds
Started Jul 14 05:29:17 PM PDT 24
Finished Jul 14 05:29:39 PM PDT 24
Peak memory 250332 kb
Host smart-d8fc42b5-cfad-486b-8b2c-b0347e169e34
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967597953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.967597953
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3241162297
Short name T376
Test name
Test status
Simulation time 230133359 ps
CPU time 3.2 seconds
Started Jul 14 05:29:20 PM PDT 24
Finished Jul 14 05:29:24 PM PDT 24
Peak memory 217704 kb
Host smart-6c3bcbd3-6768-4823-a5f3-9ede0335eed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241162297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3241162297
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.498925507
Short name T283
Test name
Test status
Simulation time 1292587557 ps
CPU time 9.75 seconds
Started Jul 14 05:29:20 PM PDT 24
Finished Jul 14 05:29:30 PM PDT 24
Peak memory 217640 kb
Host smart-9428c858-b3b4-48bd-a0c4-6ca85fdb199a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498925507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.498925507
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.4082233872
Short name T565
Test name
Test status
Simulation time 681487529 ps
CPU time 12.8 seconds
Started Jul 14 05:29:22 PM PDT 24
Finished Jul 14 05:29:36 PM PDT 24
Peak memory 225436 kb
Host smart-d3951bfe-ec63-434b-a6bd-8d229e9bb6b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082233872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.4082233872
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2051854205
Short name T761
Test name
Test status
Simulation time 749866980 ps
CPU time 6.52 seconds
Started Jul 14 05:29:18 PM PDT 24
Finished Jul 14 05:29:25 PM PDT 24
Peak memory 217612 kb
Host smart-bc1b176d-d14b-4a0d-9cd6-6228fbda6291
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051854205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2051854205
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1715485204
Short name T350
Test name
Test status
Simulation time 589378426 ps
CPU time 9.58 seconds
Started Jul 14 05:29:19 PM PDT 24
Finished Jul 14 05:29:29 PM PDT 24
Peak memory 217756 kb
Host smart-4f0ac5e2-c9a9-41bf-aed3-465303624db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715485204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1715485204
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.4267021872
Short name T70
Test name
Test status
Simulation time 1722889076 ps
CPU time 5.26 seconds
Started Jul 14 05:29:22 PM PDT 24
Finished Jul 14 05:29:28 PM PDT 24
Peak memory 217148 kb
Host smart-f11bc90f-c8d2-4273-8683-a3b02cdfaac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267021872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.4267021872
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.890509507
Short name T396
Test name
Test status
Simulation time 208361294 ps
CPU time 27.65 seconds
Started Jul 14 05:29:18 PM PDT 24
Finished Jul 14 05:29:47 PM PDT 24
Peak memory 250404 kb
Host smart-00cedacd-f247-4c3c-a17a-fb13ea066c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890509507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.890509507
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2993437130
Short name T668
Test name
Test status
Simulation time 49247272 ps
CPU time 3.25 seconds
Started Jul 14 05:29:20 PM PDT 24
Finished Jul 14 05:29:24 PM PDT 24
Peak memory 221736 kb
Host smart-d028f250-9298-457b-ae2c-501c7f43a5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993437130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2993437130
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1220930706
Short name T60
Test name
Test status
Simulation time 2424861968 ps
CPU time 71.91 seconds
Started Jul 14 05:29:18 PM PDT 24
Finished Jul 14 05:30:30 PM PDT 24
Peak memory 217216 kb
Host smart-2bdd2eb8-e615-4bc4-b481-b3e1d4f9ab85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220930706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1220930706
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.565771953
Short name T662
Test name
Test status
Simulation time 135795326 ps
CPU time 0.9 seconds
Started Jul 14 05:29:21 PM PDT 24
Finished Jul 14 05:29:23 PM PDT 24
Peak memory 208524 kb
Host smart-c3615c8a-8c23-43d8-a41e-30abfb1b0cba
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565771953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.565771953
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3017716082
Short name T644
Test name
Test status
Simulation time 108221598 ps
CPU time 1.43 seconds
Started Jul 14 05:27:31 PM PDT 24
Finished Jul 14 05:27:33 PM PDT 24
Peak memory 208484 kb
Host smart-2adba625-eb2a-4053-a5c9-6c4a9d3da8e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017716082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3017716082
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2650253169
Short name T179
Test name
Test status
Simulation time 1547951707 ps
CPU time 17.16 seconds
Started Jul 14 05:27:27 PM PDT 24
Finished Jul 14 05:27:44 PM PDT 24
Peak memory 225512 kb
Host smart-3fef2e62-c78d-41c8-844d-3e7de0c881ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650253169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2650253169
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.3137421216
Short name T540
Test name
Test status
Simulation time 790681903 ps
CPU time 4.68 seconds
Started Jul 14 05:27:32 PM PDT 24
Finished Jul 14 05:27:38 PM PDT 24
Peak memory 216908 kb
Host smart-df95b3f2-5a38-4303-974c-1959571be3eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137421216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.3137421216
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1370497154
Short name T735
Test name
Test status
Simulation time 10670983737 ps
CPU time 42.14 seconds
Started Jul 14 05:27:32 PM PDT 24
Finished Jul 14 05:28:15 PM PDT 24
Peak memory 218288 kb
Host smart-a77acba6-c0f0-4c26-840d-e5d7ff9a5bf6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370497154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1370497154
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1771391711
Short name T831
Test name
Test status
Simulation time 983866952 ps
CPU time 7.43 seconds
Started Jul 14 05:27:31 PM PDT 24
Finished Jul 14 05:27:40 PM PDT 24
Peak memory 217096 kb
Host smart-eafd3d5e-f97b-4cc3-ad8d-431277417ca0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771391711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
771391711
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1351499968
Short name T529
Test name
Test status
Simulation time 149999860 ps
CPU time 1.98 seconds
Started Jul 14 05:27:25 PM PDT 24
Finished Jul 14 05:27:27 PM PDT 24
Peak memory 217668 kb
Host smart-ed245e9a-83d9-4931-a10f-2b7a97b82d8d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351499968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.1351499968
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3599419148
Short name T77
Test name
Test status
Simulation time 1143279062 ps
CPU time 14.55 seconds
Started Jul 14 05:27:32 PM PDT 24
Finished Jul 14 05:27:47 PM PDT 24
Peak memory 217088 kb
Host smart-29665083-8aa9-417b-9394-123e39131344
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599419148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.3599419148
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.906108737
Short name T64
Test name
Test status
Simulation time 837484150 ps
CPU time 5.91 seconds
Started Jul 14 05:27:26 PM PDT 24
Finished Jul 14 05:27:32 PM PDT 24
Peak memory 217068 kb
Host smart-8d9c53bd-8861-4605-a8ae-5818797bbf9b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906108737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.906108737
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.920464127
Short name T625
Test name
Test status
Simulation time 8778066069 ps
CPU time 60.21 seconds
Started Jul 14 05:27:26 PM PDT 24
Finished Jul 14 05:28:26 PM PDT 24
Peak memory 275936 kb
Host smart-daeae045-8d66-4da7-9801-b34648326814
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920464127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.920464127
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.4058014016
Short name T752
Test name
Test status
Simulation time 790970819 ps
CPU time 17.13 seconds
Started Jul 14 05:27:27 PM PDT 24
Finished Jul 14 05:27:45 PM PDT 24
Peak memory 250264 kb
Host smart-74a2487f-e74b-4fbe-9efe-0055ad829c3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058014016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.4058014016
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.680042250
Short name T250
Test name
Test status
Simulation time 123854998 ps
CPU time 2.84 seconds
Started Jul 14 05:27:23 PM PDT 24
Finished Jul 14 05:27:27 PM PDT 24
Peak memory 217684 kb
Host smart-8e168431-f51e-4ac4-96af-883e2fb14e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680042250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.680042250
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1854446928
Short name T79
Test name
Test status
Simulation time 1189745833 ps
CPU time 7.6 seconds
Started Jul 14 05:27:33 PM PDT 24
Finished Jul 14 05:27:42 PM PDT 24
Peak memory 217068 kb
Host smart-48da3e5b-ad10-41bf-84fd-53bfb1b4d5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854446928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1854446928
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.261199986
Short name T84
Test name
Test status
Simulation time 116105152 ps
CPU time 24 seconds
Started Jul 14 05:27:33 PM PDT 24
Finished Jul 14 05:27:58 PM PDT 24
Peak memory 281256 kb
Host smart-8c4487f2-87e8-436e-9d08-689ac9c5ccb4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261199986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.261199986
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3866644238
Short name T233
Test name
Test status
Simulation time 1056313134 ps
CPU time 10.21 seconds
Started Jul 14 05:27:29 PM PDT 24
Finished Jul 14 05:27:40 PM PDT 24
Peak memory 225400 kb
Host smart-65ecabd2-470b-4177-bc3b-2fab83aca1f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866644238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3866644238
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3148328531
Short name T594
Test name
Test status
Simulation time 1034828953 ps
CPU time 9.04 seconds
Started Jul 14 05:27:34 PM PDT 24
Finished Jul 14 05:27:44 PM PDT 24
Peak memory 217644 kb
Host smart-6b426f2f-454f-4284-bd51-4206bcf05f82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148328531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
148328531
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.864353407
Short name T328
Test name
Test status
Simulation time 622703700 ps
CPU time 8.37 seconds
Started Jul 14 05:27:28 PM PDT 24
Finished Jul 14 05:27:36 PM PDT 24
Peak memory 217768 kb
Host smart-e96a8fd2-c3b2-4246-8e36-f4df67548b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864353407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.864353407
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1637747523
Short name T779
Test name
Test status
Simulation time 217877851 ps
CPU time 2.92 seconds
Started Jul 14 05:27:21 PM PDT 24
Finished Jul 14 05:27:25 PM PDT 24
Peak memory 217048 kb
Host smart-a42bd9c0-b992-439f-8d88-d47afc3562d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637747523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1637747523
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3853546680
Short name T626
Test name
Test status
Simulation time 1456944025 ps
CPU time 29.95 seconds
Started Jul 14 05:27:22 PM PDT 24
Finished Jul 14 05:27:53 PM PDT 24
Peak memory 250444 kb
Host smart-8414b37f-7777-4b87-8ac8-0e7a2a723821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853546680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3853546680
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1135775096
Short name T163
Test name
Test status
Simulation time 408283712 ps
CPU time 6.61 seconds
Started Jul 14 05:27:21 PM PDT 24
Finished Jul 14 05:27:28 PM PDT 24
Peak memory 246664 kb
Host smart-492fbe9c-8b6c-42eb-bfe2-99e0ef403bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135775096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1135775096
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.3833126406
Short name T556
Test name
Test status
Simulation time 34153476287 ps
CPU time 176.42 seconds
Started Jul 14 05:27:32 PM PDT 24
Finished Jul 14 05:30:29 PM PDT 24
Peak memory 283276 kb
Host smart-093c3602-58a6-4751-876a-802d06a66913
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833126406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.3833126406
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2238704734
Short name T820
Test name
Test status
Simulation time 15902480 ps
CPU time 0.83 seconds
Started Jul 14 05:27:22 PM PDT 24
Finished Jul 14 05:27:24 PM PDT 24
Peak memory 208488 kb
Host smart-6039a723-738f-45ff-938c-501e61f2d6ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238704734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2238704734
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3625289441
Short name T86
Test name
Test status
Simulation time 26835555 ps
CPU time 1.07 seconds
Started Jul 14 05:29:26 PM PDT 24
Finished Jul 14 05:29:27 PM PDT 24
Peak memory 208348 kb
Host smart-73f0bc30-b52e-4e8f-84e1-25f97f3e6289
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625289441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3625289441
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.982211897
Short name T697
Test name
Test status
Simulation time 986712164 ps
CPU time 9.01 seconds
Started Jul 14 05:29:22 PM PDT 24
Finished Jul 14 05:29:32 PM PDT 24
Peak memory 225508 kb
Host smart-f075c66b-859b-4582-ae4f-988154acd90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982211897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.982211897
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.895486576
Short name T566
Test name
Test status
Simulation time 920066994 ps
CPU time 6.22 seconds
Started Jul 14 05:29:22 PM PDT 24
Finished Jul 14 05:29:29 PM PDT 24
Peak memory 216912 kb
Host smart-37f9853d-ba26-4bfa-a16c-2d11a372dc62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895486576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.895486576
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.151343095
Short name T754
Test name
Test status
Simulation time 23271369 ps
CPU time 1.77 seconds
Started Jul 14 05:29:18 PM PDT 24
Finished Jul 14 05:29:21 PM PDT 24
Peak memory 217604 kb
Host smart-108376c2-69c4-42d2-a61d-079a3831b7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151343095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.151343095
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1133736021
Short name T300
Test name
Test status
Simulation time 1505131618 ps
CPU time 18.21 seconds
Started Jul 14 05:29:28 PM PDT 24
Finished Jul 14 05:29:46 PM PDT 24
Peak memory 225504 kb
Host smart-df10cb39-6ee6-4831-8e24-41507f921cd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133736021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1133736021
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1949177081
Short name T850
Test name
Test status
Simulation time 1025292076 ps
CPU time 12.36 seconds
Started Jul 14 05:29:24 PM PDT 24
Finished Jul 14 05:29:37 PM PDT 24
Peak memory 225436 kb
Host smart-77017ea9-729f-4db2-be6d-c59708f903bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949177081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.1949177081
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2828679385
Short name T91
Test name
Test status
Simulation time 1088906312 ps
CPU time 17.93 seconds
Started Jul 14 05:29:24 PM PDT 24
Finished Jul 14 05:29:42 PM PDT 24
Peak memory 217640 kb
Host smart-2a4e9afd-96e7-4f78-a39d-b83a4c4b855a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828679385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2828679385
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2050863451
Short name T378
Test name
Test status
Simulation time 1384825434 ps
CPU time 13.38 seconds
Started Jul 14 05:29:25 PM PDT 24
Finished Jul 14 05:29:38 PM PDT 24
Peak memory 225444 kb
Host smart-a78d279c-ad40-425e-87ba-d11d0e494b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050863451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2050863451
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2037822256
Short name T488
Test name
Test status
Simulation time 159426579 ps
CPU time 1.93 seconds
Started Jul 14 05:29:22 PM PDT 24
Finished Jul 14 05:29:25 PM PDT 24
Peak memory 217008 kb
Host smart-2bbf568f-156b-4aea-b840-0efa3d3e24ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037822256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2037822256
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3470841030
Short name T582
Test name
Test status
Simulation time 211462290 ps
CPU time 26.14 seconds
Started Jul 14 05:29:22 PM PDT 24
Finished Jul 14 05:29:49 PM PDT 24
Peak memory 250516 kb
Host smart-8ca87bce-836c-467b-a7e3-ff7dc1a4cff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470841030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3470841030
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.497146797
Short name T634
Test name
Test status
Simulation time 55849889 ps
CPU time 7.45 seconds
Started Jul 14 05:29:21 PM PDT 24
Finished Jul 14 05:29:30 PM PDT 24
Peak memory 250448 kb
Host smart-b12f1621-06f8-413d-9868-3de8a801112e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497146797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.497146797
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3348390177
Short name T152
Test name
Test status
Simulation time 66235107069 ps
CPU time 319.39 seconds
Started Jul 14 05:29:26 PM PDT 24
Finished Jul 14 05:34:46 PM PDT 24
Peak memory 267924 kb
Host smart-81db68a8-6d4f-48c2-bcc2-d39126b98919
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348390177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3348390177
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.854068572
Short name T141
Test name
Test status
Simulation time 53774009148 ps
CPU time 1050.96 seconds
Started Jul 14 05:29:25 PM PDT 24
Finished Jul 14 05:46:56 PM PDT 24
Peak memory 283412 kb
Host smart-abfc1f96-dbe8-4b91-881e-9cc3783f179a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=854068572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.854068572
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2343139573
Short name T653
Test name
Test status
Simulation time 132770873 ps
CPU time 0.89 seconds
Started Jul 14 05:29:19 PM PDT 24
Finished Jul 14 05:29:20 PM PDT 24
Peak memory 208588 kb
Host smart-909697f7-ec75-45af-a981-6a8a1b134e1f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343139573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2343139573
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.772495877
Short name T711
Test name
Test status
Simulation time 30857982 ps
CPU time 0.94 seconds
Started Jul 14 05:29:27 PM PDT 24
Finished Jul 14 05:29:28 PM PDT 24
Peak memory 208392 kb
Host smart-234f74d9-c04a-4578-8a39-6fc6a9f909de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772495877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.772495877
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1487289392
Short name T696
Test name
Test status
Simulation time 1152666904 ps
CPU time 14.63 seconds
Started Jul 14 05:29:25 PM PDT 24
Finished Jul 14 05:29:40 PM PDT 24
Peak memory 217640 kb
Host smart-8288305e-3dde-4bf2-a60a-d26f6fb5205e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487289392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1487289392
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1057766693
Short name T289
Test name
Test status
Simulation time 254256788 ps
CPU time 1.36 seconds
Started Jul 14 05:29:29 PM PDT 24
Finished Jul 14 05:29:31 PM PDT 24
Peak memory 216528 kb
Host smart-91d34f32-3d74-4a1a-8928-39c5d7806b05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057766693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1057766693
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3346377358
Short name T705
Test name
Test status
Simulation time 543694215 ps
CPU time 3.89 seconds
Started Jul 14 05:29:24 PM PDT 24
Finished Jul 14 05:29:28 PM PDT 24
Peak memory 217672 kb
Host smart-170067ce-2b26-424c-8084-3ce4d57badd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346377358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3346377358
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.568254417
Short name T491
Test name
Test status
Simulation time 2038506452 ps
CPU time 12.44 seconds
Started Jul 14 05:29:30 PM PDT 24
Finished Jul 14 05:29:43 PM PDT 24
Peak memory 225364 kb
Host smart-9c703279-2449-46b8-a699-c54d3fa90a83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568254417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_di
gest.568254417
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3245486614
Short name T681
Test name
Test status
Simulation time 884208913 ps
CPU time 8.07 seconds
Started Jul 14 05:29:32 PM PDT 24
Finished Jul 14 05:29:40 PM PDT 24
Peak memory 225256 kb
Host smart-ff19ab32-7894-4b06-8acf-d9f11912b219
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245486614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3245486614
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2269365957
Short name T211
Test name
Test status
Simulation time 628830271 ps
CPU time 12.79 seconds
Started Jul 14 05:29:22 PM PDT 24
Finished Jul 14 05:29:35 PM PDT 24
Peak memory 225484 kb
Host smart-65b27549-275c-4df4-a7ca-e442d96ae312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269365957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2269365957
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.527636103
Short name T261
Test name
Test status
Simulation time 141649640 ps
CPU time 2.2 seconds
Started Jul 14 05:29:25 PM PDT 24
Finished Jul 14 05:29:28 PM PDT 24
Peak memory 213588 kb
Host smart-2356f383-528b-45ee-bfd4-4570f6eccae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527636103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.527636103
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3107833109
Short name T219
Test name
Test status
Simulation time 403298582 ps
CPU time 26.92 seconds
Started Jul 14 05:29:22 PM PDT 24
Finished Jul 14 05:29:50 PM PDT 24
Peak memory 244596 kb
Host smart-39e98640-9db6-41b9-b2d9-c50825cf40cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107833109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3107833109
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3024573639
Short name T495
Test name
Test status
Simulation time 1261853223 ps
CPU time 3.07 seconds
Started Jul 14 05:29:24 PM PDT 24
Finished Jul 14 05:29:28 PM PDT 24
Peak memory 221912 kb
Host smart-42ab1aed-c493-4fa7-8fc6-6c4f54a955f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024573639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3024573639
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2861114069
Short name T632
Test name
Test status
Simulation time 19172635720 ps
CPU time 431.59 seconds
Started Jul 14 05:29:32 PM PDT 24
Finished Jul 14 05:36:44 PM PDT 24
Peak memory 315956 kb
Host smart-8d732d9d-a12d-45a0-94b5-abebc793f4c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861114069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2861114069
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.881518007
Short name T366
Test name
Test status
Simulation time 41290778 ps
CPU time 0.8 seconds
Started Jul 14 05:29:24 PM PDT 24
Finished Jul 14 05:29:25 PM PDT 24
Peak memory 208204 kb
Host smart-2011fa14-fd84-4e83-b9f2-58c203e4da3b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881518007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.881518007
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.643835286
Short name T773
Test name
Test status
Simulation time 83855612 ps
CPU time 1.24 seconds
Started Jul 14 05:29:29 PM PDT 24
Finished Jul 14 05:29:30 PM PDT 24
Peak memory 208476 kb
Host smart-df1a9060-9041-4a8b-8b1f-11dccd9fff29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643835286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.643835286
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1229199249
Short name T524
Test name
Test status
Simulation time 628424089 ps
CPU time 15.12 seconds
Started Jul 14 05:29:28 PM PDT 24
Finished Jul 14 05:29:44 PM PDT 24
Peak memory 225504 kb
Host smart-420db3c3-381c-40d1-9213-d4d7f571d654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229199249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1229199249
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2317250953
Short name T474
Test name
Test status
Simulation time 210989432 ps
CPU time 6.51 seconds
Started Jul 14 05:29:28 PM PDT 24
Finished Jul 14 05:29:35 PM PDT 24
Peak memory 217120 kb
Host smart-8f58701d-8145-4bde-b12a-4ee545cda438
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317250953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.2317250953
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1757735361
Short name T342
Test name
Test status
Simulation time 295040696 ps
CPU time 3.19 seconds
Started Jul 14 05:29:28 PM PDT 24
Finished Jul 14 05:29:32 PM PDT 24
Peak memory 217716 kb
Host smart-8d0d7e9e-20b2-411f-93b2-d05ed297e7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757735361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1757735361
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1366461714
Short name T591
Test name
Test status
Simulation time 1087481078 ps
CPU time 9.75 seconds
Started Jul 14 05:29:30 PM PDT 24
Finished Jul 14 05:29:40 PM PDT 24
Peak memory 218356 kb
Host smart-a760fc7d-595a-4602-9dee-aafc44e66032
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366461714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1366461714
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.607620054
Short name T620
Test name
Test status
Simulation time 235355242 ps
CPU time 8.42 seconds
Started Jul 14 05:29:28 PM PDT 24
Finished Jul 14 05:29:37 PM PDT 24
Peak memory 225388 kb
Host smart-2a272c0b-34f8-41dd-b3dc-fd540dcfe787
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607620054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di
gest.607620054
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3840479122
Short name T852
Test name
Test status
Simulation time 801242663 ps
CPU time 9.12 seconds
Started Jul 14 05:29:28 PM PDT 24
Finished Jul 14 05:29:38 PM PDT 24
Peak memory 225424 kb
Host smart-33dd6c7a-7833-4139-be6f-cd105b64e357
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840479122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3840479122
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1182781312
Short name T670
Test name
Test status
Simulation time 397785869 ps
CPU time 9.5 seconds
Started Jul 14 05:29:30 PM PDT 24
Finished Jul 14 05:29:40 PM PDT 24
Peak memory 217776 kb
Host smart-5d21bed6-d4c4-4503-8661-5294f0b48a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182781312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1182781312
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3006828846
Short name T295
Test name
Test status
Simulation time 41796990 ps
CPU time 1.04 seconds
Started Jul 14 05:29:32 PM PDT 24
Finished Jul 14 05:29:33 PM PDT 24
Peak memory 216972 kb
Host smart-cb3b0f88-660e-41fd-88e1-7d6afab1dc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006828846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3006828846
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1463749083
Short name T654
Test name
Test status
Simulation time 297798491 ps
CPU time 38.01 seconds
Started Jul 14 05:29:31 PM PDT 24
Finished Jul 14 05:30:10 PM PDT 24
Peak memory 250448 kb
Host smart-5f265d92-3e54-45a2-a37e-4d7f077beb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463749083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1463749083
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1225969934
Short name T433
Test name
Test status
Simulation time 111777933 ps
CPU time 6.79 seconds
Started Jul 14 05:29:26 PM PDT 24
Finished Jul 14 05:29:34 PM PDT 24
Peak memory 246040 kb
Host smart-6ac142f9-1dbe-417d-9481-1adf071cfc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225969934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1225969934
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.462748772
Short name T453
Test name
Test status
Simulation time 4140409088 ps
CPU time 87.01 seconds
Started Jul 14 05:29:32 PM PDT 24
Finished Jul 14 05:31:00 PM PDT 24
Peak memory 274212 kb
Host smart-a14c18d0-dc13-4890-9690-4d828fa4db03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462748772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.462748772
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.4275137712
Short name T719
Test name
Test status
Simulation time 28283374 ps
CPU time 1.05 seconds
Started Jul 14 05:29:30 PM PDT 24
Finished Jul 14 05:29:31 PM PDT 24
Peak memory 217264 kb
Host smart-0a9e4198-1893-44c6-a0ce-f54dce289bb4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275137712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.4275137712
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.283102519
Short name T274
Test name
Test status
Simulation time 27387227 ps
CPU time 1.33 seconds
Started Jul 14 05:29:34 PM PDT 24
Finished Jul 14 05:29:36 PM PDT 24
Peak memory 208460 kb
Host smart-6268ac53-bf63-4b46-8ba5-edd2a664f827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283102519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.283102519
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3234925086
Short name T606
Test name
Test status
Simulation time 885848421 ps
CPU time 9.86 seconds
Started Jul 14 05:29:35 PM PDT 24
Finished Jul 14 05:29:45 PM PDT 24
Peak memory 217808 kb
Host smart-dcacec06-4566-4fd3-a6e7-bfc0ea3b5e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234925086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3234925086
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2074270661
Short name T837
Test name
Test status
Simulation time 1703272697 ps
CPU time 19.24 seconds
Started Jul 14 05:29:36 PM PDT 24
Finished Jul 14 05:29:56 PM PDT 24
Peak memory 217116 kb
Host smart-0bf47b35-8c45-4137-830b-10d32d0d05bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074270661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2074270661
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.753883786
Short name T749
Test name
Test status
Simulation time 59950496 ps
CPU time 3.27 seconds
Started Jul 14 05:29:34 PM PDT 24
Finished Jul 14 05:29:38 PM PDT 24
Peak memory 221800 kb
Host smart-eb3c6554-e6aa-49fc-a6b7-6efeed3134d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753883786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.753883786
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1978912405
Short name T359
Test name
Test status
Simulation time 178234289 ps
CPU time 8.53 seconds
Started Jul 14 05:29:34 PM PDT 24
Finished Jul 14 05:29:43 PM PDT 24
Peak memory 225440 kb
Host smart-244c87cf-7a52-4752-a313-937c14f8dda8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978912405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1978912405
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2191171177
Short name T802
Test name
Test status
Simulation time 292834121 ps
CPU time 10.92 seconds
Started Jul 14 05:29:44 PM PDT 24
Finished Jul 14 05:29:55 PM PDT 24
Peak memory 217644 kb
Host smart-b4dbdb8c-5262-4631-b172-85f53b1b069b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191171177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2191171177
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3278781358
Short name T600
Test name
Test status
Simulation time 755217998 ps
CPU time 14.16 seconds
Started Jul 14 05:29:35 PM PDT 24
Finished Jul 14 05:29:50 PM PDT 24
Peak memory 225420 kb
Host smart-628f7859-4e41-4a3b-b102-9205d79c4282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278781358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3278781358
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.727383890
Short name T93
Test name
Test status
Simulation time 114305120 ps
CPU time 6.91 seconds
Started Jul 14 05:29:44 PM PDT 24
Finished Jul 14 05:29:51 PM PDT 24
Peak memory 217116 kb
Host smart-d8527b75-c901-40fd-98fa-b218da2e0aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727383890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.727383890
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3719298445
Short name T400
Test name
Test status
Simulation time 2238354781 ps
CPU time 38.47 seconds
Started Jul 14 05:29:34 PM PDT 24
Finished Jul 14 05:30:13 PM PDT 24
Peak memory 250520 kb
Host smart-3c31118b-8f0d-4ae5-a7f0-2f518fc202d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719298445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3719298445
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.141366844
Short name T431
Test name
Test status
Simulation time 367293822 ps
CPU time 6.91 seconds
Started Jul 14 05:29:36 PM PDT 24
Finished Jul 14 05:29:43 PM PDT 24
Peak memory 246400 kb
Host smart-72769a5f-a275-4ed2-98b7-be623fbb4c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141366844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.141366844
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.4178783588
Short name T421
Test name
Test status
Simulation time 19921878336 ps
CPU time 177.7 seconds
Started Jul 14 05:29:36 PM PDT 24
Finished Jul 14 05:32:34 PM PDT 24
Peak memory 283104 kb
Host smart-0d17638c-e16b-4c23-bcb1-7bb6995b9b72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178783588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.4178783588
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3258177996
Short name T709
Test name
Test status
Simulation time 25998836 ps
CPU time 1.13 seconds
Started Jul 14 05:29:34 PM PDT 24
Finished Jul 14 05:29:36 PM PDT 24
Peak memory 212356 kb
Host smart-da00f881-f7fd-4cd0-8833-e0e0e1ba3480
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258177996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3258177996
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.166310195
Short name T358
Test name
Test status
Simulation time 22862718 ps
CPU time 0.95 seconds
Started Jul 14 05:29:41 PM PDT 24
Finished Jul 14 05:29:42 PM PDT 24
Peak memory 208452 kb
Host smart-dd58a6ab-23c7-4021-bb28-aac71673f5c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166310195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.166310195
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.4134843338
Short name T231
Test name
Test status
Simulation time 1896303274 ps
CPU time 16.88 seconds
Started Jul 14 05:29:35 PM PDT 24
Finished Jul 14 05:29:53 PM PDT 24
Peak memory 225500 kb
Host smart-ce200daa-5305-4aeb-88f0-f69138e81ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134843338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.4134843338
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.600251783
Short name T333
Test name
Test status
Simulation time 462972503 ps
CPU time 6.88 seconds
Started Jul 14 05:29:33 PM PDT 24
Finished Jul 14 05:29:41 PM PDT 24
Peak memory 217096 kb
Host smart-f9e65be7-042f-4fdb-b1b6-be1a8dc2614b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600251783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.600251783
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.4055653255
Short name T608
Test name
Test status
Simulation time 338032677 ps
CPU time 2.85 seconds
Started Jul 14 05:29:34 PM PDT 24
Finished Jul 14 05:29:38 PM PDT 24
Peak memory 217720 kb
Host smart-6643c2cd-3bf6-45d8-9600-51566165fafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055653255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.4055653255
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2734035941
Short name T59
Test name
Test status
Simulation time 1053758587 ps
CPU time 12.51 seconds
Started Jul 14 05:29:36 PM PDT 24
Finished Jul 14 05:29:49 PM PDT 24
Peak memory 225456 kb
Host smart-aa7978b2-b976-4448-b576-3e3ec11a752e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734035941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2734035941
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.384568674
Short name T391
Test name
Test status
Simulation time 1177611560 ps
CPU time 10.06 seconds
Started Jul 14 05:29:40 PM PDT 24
Finished Jul 14 05:29:51 PM PDT 24
Peak memory 225372 kb
Host smart-0272f000-b06a-45b5-8c73-e60f77b573c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384568674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.384568674
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.670331353
Short name T855
Test name
Test status
Simulation time 267670916 ps
CPU time 9.76 seconds
Started Jul 14 05:29:47 PM PDT 24
Finished Jul 14 05:29:57 PM PDT 24
Peak memory 225424 kb
Host smart-bf95aba9-363e-4ef6-a0f2-a0e12abed1b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670331353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.670331353
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1202289030
Short name T613
Test name
Test status
Simulation time 754901597 ps
CPU time 6.8 seconds
Started Jul 14 05:29:34 PM PDT 24
Finished Jul 14 05:29:41 PM PDT 24
Peak memory 224904 kb
Host smart-f1f9362c-746a-4b87-81a3-677d3db17e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202289030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1202289030
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.888405375
Short name T452
Test name
Test status
Simulation time 194939418 ps
CPU time 2.31 seconds
Started Jul 14 05:29:36 PM PDT 24
Finished Jul 14 05:29:39 PM PDT 24
Peak memory 213476 kb
Host smart-7d9d55f8-a8e7-4eb4-a863-d5cf2f7df10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888405375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.888405375
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3930943316
Short name T691
Test name
Test status
Simulation time 211718241 ps
CPU time 21.65 seconds
Started Jul 14 05:29:36 PM PDT 24
Finished Jul 14 05:29:59 PM PDT 24
Peak memory 250428 kb
Host smart-6f59ac51-78cc-43fb-aa8f-1ae938673e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930943316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3930943316
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2719634838
Short name T815
Test name
Test status
Simulation time 450392963 ps
CPU time 7.16 seconds
Started Jul 14 05:29:34 PM PDT 24
Finished Jul 14 05:29:42 PM PDT 24
Peak memory 250416 kb
Host smart-7102e75b-3780-497f-95f5-488ab97a5f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719634838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2719634838
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3668742755
Short name T603
Test name
Test status
Simulation time 40187580 ps
CPU time 0.96 seconds
Started Jul 14 05:29:44 PM PDT 24
Finished Jul 14 05:29:46 PM PDT 24
Peak memory 208360 kb
Host smart-abe06458-74bb-429b-8e14-395070b1e698
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668742755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3668742755
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2169732188
Short name T819
Test name
Test status
Simulation time 68739699 ps
CPU time 0.94 seconds
Started Jul 14 05:29:40 PM PDT 24
Finished Jul 14 05:29:41 PM PDT 24
Peak memory 208456 kb
Host smart-fb3c862d-b5c1-4f72-b2e3-b6822bd06999
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169732188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2169732188
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3869708250
Short name T804
Test name
Test status
Simulation time 2133667175 ps
CPU time 13.52 seconds
Started Jul 14 05:29:44 PM PDT 24
Finished Jul 14 05:29:58 PM PDT 24
Peak memory 225496 kb
Host smart-7d7a9f6a-5f8f-4dc0-b75f-51102e5d15f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869708250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3869708250
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.112506334
Short name T518
Test name
Test status
Simulation time 126055897 ps
CPU time 3.95 seconds
Started Jul 14 05:29:42 PM PDT 24
Finished Jul 14 05:29:47 PM PDT 24
Peak memory 217636 kb
Host smart-9054157c-aa51-4689-ae76-3309a71e4f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112506334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.112506334
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.3012206681
Short name T316
Test name
Test status
Simulation time 624546807 ps
CPU time 16.87 seconds
Started Jul 14 05:29:40 PM PDT 24
Finished Jul 14 05:29:58 PM PDT 24
Peak memory 225500 kb
Host smart-6d2e614e-f594-4e91-a150-c8d9911eb037
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012206681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3012206681
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2985032394
Short name T853
Test name
Test status
Simulation time 1600466631 ps
CPU time 15.61 seconds
Started Jul 14 05:29:39 PM PDT 24
Finished Jul 14 05:29:55 PM PDT 24
Peak memory 217640 kb
Host smart-31b5b117-6414-4dcc-8a73-373732950af2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985032394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2985032394
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.4085765160
Short name T595
Test name
Test status
Simulation time 1066919249 ps
CPU time 8.21 seconds
Started Jul 14 05:29:42 PM PDT 24
Finished Jul 14 05:29:50 PM PDT 24
Peak memory 217544 kb
Host smart-f8e4c14d-1ecf-4113-b2da-32f06bdcb2ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085765160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
4085765160
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2306798111
Short name T571
Test name
Test status
Simulation time 1597705906 ps
CPU time 10 seconds
Started Jul 14 05:29:47 PM PDT 24
Finished Jul 14 05:29:58 PM PDT 24
Peak memory 225568 kb
Host smart-93c1a42d-0f9f-45c2-9376-2d64a350f928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306798111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2306798111
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2788655062
Short name T69
Test name
Test status
Simulation time 250785217 ps
CPU time 3.17 seconds
Started Jul 14 05:29:42 PM PDT 24
Finished Jul 14 05:29:45 PM PDT 24
Peak memory 222164 kb
Host smart-0539e3aa-c664-4578-898e-e122bcb865a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788655062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2788655062
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2385620826
Short name T602
Test name
Test status
Simulation time 1007049790 ps
CPU time 30.97 seconds
Started Jul 14 05:29:40 PM PDT 24
Finished Jul 14 05:30:11 PM PDT 24
Peak memory 250460 kb
Host smart-9533b09a-4a78-4ca3-82a9-a8f73c3291b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385620826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2385620826
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.591159309
Short name T255
Test name
Test status
Simulation time 1066633800 ps
CPU time 11.54 seconds
Started Jul 14 05:29:41 PM PDT 24
Finished Jul 14 05:29:53 PM PDT 24
Peak memory 246496 kb
Host smart-8e429b77-161e-47dd-aea1-8d9d09f255e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591159309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.591159309
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1400992744
Short name T67
Test name
Test status
Simulation time 11514445032 ps
CPU time 191.66 seconds
Started Jul 14 05:29:44 PM PDT 24
Finished Jul 14 05:32:56 PM PDT 24
Peak memory 250500 kb
Host smart-8d907215-9cb3-4f02-b92a-8d68633cfcb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400992744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1400992744
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3634173379
Short name T503
Test name
Test status
Simulation time 29421735 ps
CPU time 0.97 seconds
Started Jul 14 05:29:41 PM PDT 24
Finished Jul 14 05:29:43 PM PDT 24
Peak memory 211328 kb
Host smart-948b91c9-cddd-4068-ac60-eaf3847ee030
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634173379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3634173379
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1039033095
Short name T768
Test name
Test status
Simulation time 46986937 ps
CPU time 1.18 seconds
Started Jul 14 05:29:48 PM PDT 24
Finished Jul 14 05:29:50 PM PDT 24
Peak memory 208532 kb
Host smart-c8a5bfb0-64cf-4d62-9c72-bb49dd77a318
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039033095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1039033095
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1222759551
Short name T241
Test name
Test status
Simulation time 324085161 ps
CPU time 10.02 seconds
Started Jul 14 05:29:46 PM PDT 24
Finished Jul 14 05:29:57 PM PDT 24
Peak memory 217708 kb
Host smart-969a9f13-35e7-443d-953f-3e7c31a9d2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222759551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1222759551
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.2621085345
Short name T379
Test name
Test status
Simulation time 858469730 ps
CPU time 2.47 seconds
Started Jul 14 05:29:48 PM PDT 24
Finished Jul 14 05:29:51 PM PDT 24
Peak memory 216520 kb
Host smart-c6bfcba4-b453-4da9-ad7e-bfaf5a1d7c52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621085345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.2621085345
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3082096818
Short name T570
Test name
Test status
Simulation time 56550077 ps
CPU time 1.8 seconds
Started Jul 14 05:29:46 PM PDT 24
Finished Jul 14 05:29:48 PM PDT 24
Peak memory 217760 kb
Host smart-cd504488-0152-498a-9710-b3cd7b0fee27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082096818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3082096818
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.3845731005
Short name T415
Test name
Test status
Simulation time 559779262 ps
CPU time 12.27 seconds
Started Jul 14 05:29:45 PM PDT 24
Finished Jul 14 05:29:58 PM PDT 24
Peak memory 225440 kb
Host smart-d00518f6-c092-4047-ab93-ca099bd5571d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845731005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3845731005
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.914223952
Short name T545
Test name
Test status
Simulation time 312274990 ps
CPU time 12.47 seconds
Started Jul 14 05:29:46 PM PDT 24
Finished Jul 14 05:29:59 PM PDT 24
Peak memory 225424 kb
Host smart-2bad0566-3936-483a-bfbc-e39401a95a59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914223952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.914223952
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1739138839
Short name T612
Test name
Test status
Simulation time 314419593 ps
CPU time 8.27 seconds
Started Jul 14 05:29:47 PM PDT 24
Finished Jul 14 05:29:56 PM PDT 24
Peak memory 217660 kb
Host smart-b5a6ee74-b88c-46da-ad40-5ea65b3fe24c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739138839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1739138839
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3303914249
Short name T178
Test name
Test status
Simulation time 269451169 ps
CPU time 25.85 seconds
Started Jul 14 05:29:46 PM PDT 24
Finished Jul 14 05:30:12 PM PDT 24
Peak memory 250452 kb
Host smart-3cbbaa7e-5aa5-4eba-a7f6-42e35ad20a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303914249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3303914249
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1938302463
Short name T301
Test name
Test status
Simulation time 144056509 ps
CPU time 6.24 seconds
Started Jul 14 05:29:44 PM PDT 24
Finished Jul 14 05:29:50 PM PDT 24
Peak memory 246640 kb
Host smart-70739221-e848-455f-9cf0-630ce5b5c6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938302463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1938302463
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1844676170
Short name T45
Test name
Test status
Simulation time 16877369883 ps
CPU time 172.34 seconds
Started Jul 14 05:29:48 PM PDT 24
Finished Jul 14 05:32:41 PM PDT 24
Peak memory 283236 kb
Host smart-6262c1d5-53e2-4760-8a25-95a9e951d440
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844676170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1844676170
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.3799531055
Short name T727
Test name
Test status
Simulation time 109569640 ps
CPU time 0.8 seconds
Started Jul 14 05:29:47 PM PDT 24
Finished Jul 14 05:29:49 PM PDT 24
Peak memory 208260 kb
Host smart-bc126593-3cd8-48af-9c1e-1b630e11c475
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799531055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.3799531055
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.1038975685
Short name T450
Test name
Test status
Simulation time 97500368 ps
CPU time 1.33 seconds
Started Jul 14 05:29:51 PM PDT 24
Finished Jul 14 05:29:53 PM PDT 24
Peak memory 208428 kb
Host smart-dd450765-800b-411f-a904-303575cb1d55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038975685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1038975685
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.629476327
Short name T341
Test name
Test status
Simulation time 412690747 ps
CPU time 17.27 seconds
Started Jul 14 05:29:47 PM PDT 24
Finished Jul 14 05:30:05 PM PDT 24
Peak memory 217636 kb
Host smart-0f6a9ec8-fbac-4a9e-9d2a-1cedde0db6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629476327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.629476327
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1305254483
Short name T643
Test name
Test status
Simulation time 227500154 ps
CPU time 3.46 seconds
Started Jul 14 05:29:45 PM PDT 24
Finished Jul 14 05:29:49 PM PDT 24
Peak memory 217116 kb
Host smart-22df98a8-4ecb-460f-984a-22ad1e7cab82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305254483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1305254483
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3626260355
Short name T426
Test name
Test status
Simulation time 61495687 ps
CPU time 3.63 seconds
Started Jul 14 05:29:47 PM PDT 24
Finished Jul 14 05:29:51 PM PDT 24
Peak memory 217672 kb
Host smart-3b00a4dd-1b33-4ad7-b444-9f8db4fe2e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626260355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3626260355
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.1236077281
Short name T509
Test name
Test status
Simulation time 3051315923 ps
CPU time 8.6 seconds
Started Jul 14 05:29:44 PM PDT 24
Finished Jul 14 05:29:53 PM PDT 24
Peak memory 225560 kb
Host smart-15787eba-a089-427b-ab91-52aa4efcae97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236077281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.1236077281
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.977862258
Short name T487
Test name
Test status
Simulation time 337203222 ps
CPU time 13.34 seconds
Started Jul 14 05:29:54 PM PDT 24
Finished Jul 14 05:30:07 PM PDT 24
Peak memory 225436 kb
Host smart-bde94523-93f0-40b1-bd2f-56f728dc4c0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977862258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di
gest.977862258
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2266481679
Short name T723
Test name
Test status
Simulation time 449601259 ps
CPU time 9.93 seconds
Started Jul 14 05:29:53 PM PDT 24
Finished Jul 14 05:30:04 PM PDT 24
Peak memory 217624 kb
Host smart-fbadad09-e0d1-4f8f-886d-b5118d831f3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266481679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2266481679
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3379284333
Short name T441
Test name
Test status
Simulation time 685953233 ps
CPU time 12.73 seconds
Started Jul 14 05:29:48 PM PDT 24
Finished Jul 14 05:30:01 PM PDT 24
Peak memory 217740 kb
Host smart-01278fbf-2e1a-4fd2-b88a-69a7d93b08db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379284333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3379284333
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.947660004
Short name T55
Test name
Test status
Simulation time 34723529 ps
CPU time 2.65 seconds
Started Jul 14 05:29:46 PM PDT 24
Finished Jul 14 05:29:50 PM PDT 24
Peak memory 214060 kb
Host smart-5d671be2-d6f0-4ada-af10-d04a2f65d8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947660004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.947660004
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1693734651
Short name T408
Test name
Test status
Simulation time 370374962 ps
CPU time 33.99 seconds
Started Jul 14 05:29:47 PM PDT 24
Finished Jul 14 05:30:22 PM PDT 24
Peak memory 250408 kb
Host smart-b774deae-a37b-465f-a759-c8f71e2c3924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693734651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1693734651
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.317450348
Short name T604
Test name
Test status
Simulation time 475040538 ps
CPU time 3.67 seconds
Started Jul 14 05:29:47 PM PDT 24
Finished Jul 14 05:29:52 PM PDT 24
Peak memory 222148 kb
Host smart-f474dfee-dae4-4d3d-8200-796b9bb6f94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317450348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.317450348
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.292838219
Short name T405
Test name
Test status
Simulation time 7967190421 ps
CPU time 124.91 seconds
Started Jul 14 05:29:51 PM PDT 24
Finished Jul 14 05:31:57 PM PDT 24
Peak memory 250480 kb
Host smart-9c2200e2-0ad5-4b2c-8148-3bbf2aa5cc9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292838219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.292838219
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.2450149840
Short name T145
Test name
Test status
Simulation time 41756976350 ps
CPU time 621.03 seconds
Started Jul 14 05:29:54 PM PDT 24
Finished Jul 14 05:40:16 PM PDT 24
Peak memory 250652 kb
Host smart-a64d3983-8dc6-4409-9cac-88a8e0a5349b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2450149840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.2450149840
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2712615919
Short name T725
Test name
Test status
Simulation time 16310196 ps
CPU time 0.77 seconds
Started Jul 14 05:29:48 PM PDT 24
Finished Jul 14 05:29:50 PM PDT 24
Peak memory 208160 kb
Host smart-71e37476-df14-40ab-b2a1-e803b7284cfd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712615919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2712615919
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2514241487
Short name T775
Test name
Test status
Simulation time 17017304 ps
CPU time 1.16 seconds
Started Jul 14 05:29:51 PM PDT 24
Finished Jul 14 05:29:53 PM PDT 24
Peak memory 208484 kb
Host smart-f2fe61a3-6dd2-4d47-9aaa-5214486959bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514241487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2514241487
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2915180865
Short name T424
Test name
Test status
Simulation time 1605076184 ps
CPU time 11.2 seconds
Started Jul 14 05:29:53 PM PDT 24
Finished Jul 14 05:30:05 PM PDT 24
Peak memory 217676 kb
Host smart-217033f1-f539-441e-9387-d1d2624b42d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915180865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2915180865
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.9056679
Short name T287
Test name
Test status
Simulation time 711455782 ps
CPU time 17.48 seconds
Started Jul 14 05:29:54 PM PDT 24
Finished Jul 14 05:30:12 PM PDT 24
Peak memory 217048 kb
Host smart-47b5235c-cc91-4373-8061-1562578bb594
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9056679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.9056679
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2274586105
Short name T314
Test name
Test status
Simulation time 559770652 ps
CPU time 4.01 seconds
Started Jul 14 05:29:53 PM PDT 24
Finished Jul 14 05:29:58 PM PDT 24
Peak memory 217720 kb
Host smart-42dd6263-7e28-4049-b88a-7bf807cd60f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274586105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2274586105
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.464499364
Short name T563
Test name
Test status
Simulation time 1128869309 ps
CPU time 11.33 seconds
Started Jul 14 05:29:52 PM PDT 24
Finished Jul 14 05:30:04 PM PDT 24
Peak memory 217600 kb
Host smart-ee0f3d1d-8cac-48e5-a6ba-a970b691abfd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464499364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_di
gest.464499364
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1337273446
Short name T362
Test name
Test status
Simulation time 477805997 ps
CPU time 7.5 seconds
Started Jul 14 05:29:52 PM PDT 24
Finished Jul 14 05:30:01 PM PDT 24
Peak memory 217664 kb
Host smart-216b69ca-db51-4581-8e79-d08b15bf18f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337273446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1337273446
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1437840369
Short name T427
Test name
Test status
Simulation time 363991149 ps
CPU time 10.06 seconds
Started Jul 14 05:29:51 PM PDT 24
Finished Jul 14 05:30:02 PM PDT 24
Peak memory 225560 kb
Host smart-57182594-2ed8-4cf5-a7f6-644ed13ee69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437840369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1437840369
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1826364800
Short name T169
Test name
Test status
Simulation time 207178472 ps
CPU time 3.3 seconds
Started Jul 14 05:29:52 PM PDT 24
Finished Jul 14 05:29:55 PM PDT 24
Peak memory 217100 kb
Host smart-99593990-c13a-4442-8862-f5de17772ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826364800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1826364800
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3923319335
Short name T809
Test name
Test status
Simulation time 3280239744 ps
CPU time 26.46 seconds
Started Jul 14 05:29:51 PM PDT 24
Finished Jul 14 05:30:18 PM PDT 24
Peak memory 250444 kb
Host smart-753456f0-c23e-4b81-abb3-ac4f1bf6a850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923319335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3923319335
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3695410570
Short name T728
Test name
Test status
Simulation time 59959595 ps
CPU time 6.91 seconds
Started Jul 14 05:29:51 PM PDT 24
Finished Jul 14 05:29:59 PM PDT 24
Peak memory 246804 kb
Host smart-6ba7bef4-6fde-40c1-bf9d-fe057bf6ee7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695410570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3695410570
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3491007399
Short name T778
Test name
Test status
Simulation time 5965348937 ps
CPU time 68.17 seconds
Started Jul 14 05:29:51 PM PDT 24
Finished Jul 14 05:30:59 PM PDT 24
Peak memory 270444 kb
Host smart-c6afd043-6636-488b-b008-25c0bff0adda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491007399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3491007399
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.698020697
Short name T616
Test name
Test status
Simulation time 152516992051 ps
CPU time 1367.67 seconds
Started Jul 14 05:29:52 PM PDT 24
Finished Jul 14 05:52:41 PM PDT 24
Peak memory 299808 kb
Host smart-11ca0f95-7763-412d-bcbf-232201bf65a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=698020697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.698020697
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1530582870
Short name T236
Test name
Test status
Simulation time 15263480 ps
CPU time 0.91 seconds
Started Jul 14 05:29:52 PM PDT 24
Finished Jul 14 05:29:53 PM PDT 24
Peak memory 211284 kb
Host smart-36202af7-454e-4251-893d-9f8beb83fb9e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530582870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1530582870
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.4285500095
Short name T496
Test name
Test status
Simulation time 18326457 ps
CPU time 1.04 seconds
Started Jul 14 05:29:58 PM PDT 24
Finished Jul 14 05:30:00 PM PDT 24
Peak memory 208700 kb
Host smart-5d3f5142-0035-4e2f-93b0-b5250f22e816
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285500095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.4285500095
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1990444026
Short name T220
Test name
Test status
Simulation time 1611391161 ps
CPU time 11.51 seconds
Started Jul 14 05:29:57 PM PDT 24
Finished Jul 14 05:30:09 PM PDT 24
Peak memory 217736 kb
Host smart-e75a92fc-1599-4718-b313-e510b7d558e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990444026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1990444026
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.581627472
Short name T498
Test name
Test status
Simulation time 11454649652 ps
CPU time 15.25 seconds
Started Jul 14 05:29:58 PM PDT 24
Finished Jul 14 05:30:14 PM PDT 24
Peak memory 217184 kb
Host smart-28a66298-de8e-4937-8c46-951073395e64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581627472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.581627472
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1243997115
Short name T667
Test name
Test status
Simulation time 304707191 ps
CPU time 3.43 seconds
Started Jul 14 05:29:59 PM PDT 24
Finished Jul 14 05:30:04 PM PDT 24
Peak memory 221896 kb
Host smart-3ae6b89b-aafc-4966-8c42-b65a5e34a373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243997115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1243997115
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2890845867
Short name T753
Test name
Test status
Simulation time 1100964260 ps
CPU time 11.67 seconds
Started Jul 14 05:29:59 PM PDT 24
Finished Jul 14 05:30:12 PM PDT 24
Peak memory 217712 kb
Host smart-6c0d3d65-ab0b-4a05-b5d5-ce0f64696921
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890845867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2890845867
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2051007442
Short name T285
Test name
Test status
Simulation time 274061002 ps
CPU time 7.58 seconds
Started Jul 14 05:29:58 PM PDT 24
Finished Jul 14 05:30:06 PM PDT 24
Peak memory 225460 kb
Host smart-4bdd3be2-a5dc-448c-ad54-0dcb4b90f233
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051007442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2051007442
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.441948212
Short name T554
Test name
Test status
Simulation time 80090474 ps
CPU time 5.68 seconds
Started Jul 14 05:29:53 PM PDT 24
Finished Jul 14 05:29:59 PM PDT 24
Peak memory 217200 kb
Host smart-fa04ffc0-5b80-49c3-8648-93ede1d98d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441948212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.441948212
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1226555649
Short name T671
Test name
Test status
Simulation time 492397889 ps
CPU time 25.92 seconds
Started Jul 14 05:29:56 PM PDT 24
Finished Jul 14 05:30:22 PM PDT 24
Peak memory 250460 kb
Host smart-8260e899-3583-474a-8609-0eb77c600479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226555649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1226555649
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.456628984
Short name T512
Test name
Test status
Simulation time 418978009 ps
CPU time 8.36 seconds
Started Jul 14 05:30:00 PM PDT 24
Finished Jul 14 05:30:09 PM PDT 24
Peak memory 250352 kb
Host smart-318bccd5-85a7-4529-8da0-a07cec1b9c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456628984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.456628984
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1636826857
Short name T238
Test name
Test status
Simulation time 16899254715 ps
CPU time 116.8 seconds
Started Jul 14 05:29:59 PM PDT 24
Finished Jul 14 05:31:57 PM PDT 24
Peak memory 250348 kb
Host smart-c02ce497-8979-4893-9778-2b86af6dde9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636826857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1636826857
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1888587379
Short name T36
Test name
Test status
Simulation time 12683591 ps
CPU time 0.95 seconds
Started Jul 14 05:29:53 PM PDT 24
Finished Jul 14 05:29:55 PM PDT 24
Peak memory 211268 kb
Host smart-6cb124fe-732c-4007-bc60-1b9691e6b33f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888587379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1888587379
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3784190193
Short name T436
Test name
Test status
Simulation time 47858761 ps
CPU time 1.35 seconds
Started Jul 14 05:27:42 PM PDT 24
Finished Jul 14 05:27:44 PM PDT 24
Peak memory 208436 kb
Host smart-e9558acf-2ee8-4a6a-aadd-ae84c852b633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784190193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3784190193
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3284248421
Short name T798
Test name
Test status
Simulation time 10289013 ps
CPU time 0.83 seconds
Started Jul 14 05:27:37 PM PDT 24
Finished Jul 14 05:27:39 PM PDT 24
Peak memory 208468 kb
Host smart-fa08da1a-902c-4e9b-92b4-038fab9fffc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284248421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3284248421
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.4144176314
Short name T824
Test name
Test status
Simulation time 4241685288 ps
CPU time 15.45 seconds
Started Jul 14 05:27:31 PM PDT 24
Finished Jul 14 05:27:47 PM PDT 24
Peak memory 225560 kb
Host smart-418cdfe1-815d-4ae7-8eac-d4503ee6bf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144176314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.4144176314
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3267868122
Short name T598
Test name
Test status
Simulation time 471059348 ps
CPU time 5.88 seconds
Started Jul 14 05:27:39 PM PDT 24
Finished Jul 14 05:27:45 PM PDT 24
Peak memory 216788 kb
Host smart-5940997a-f827-456b-8e7e-f02d1d36cf87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267868122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3267868122
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2957266561
Short name T340
Test name
Test status
Simulation time 19832879888 ps
CPU time 43.03 seconds
Started Jul 14 05:27:36 PM PDT 24
Finished Jul 14 05:28:20 PM PDT 24
Peak memory 217780 kb
Host smart-23d3d8bf-c054-4591-8232-1cfc40a1765c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957266561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2957266561
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2019467310
Short name T807
Test name
Test status
Simulation time 2655685481 ps
CPU time 8.02 seconds
Started Jul 14 05:27:43 PM PDT 24
Finished Jul 14 05:27:52 PM PDT 24
Peak memory 217192 kb
Host smart-42f23e95-cc8d-4a7e-acaf-bbe58f066585
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019467310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
019467310
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.859538439
Short name T260
Test name
Test status
Simulation time 1223365462 ps
CPU time 6.19 seconds
Started Jul 14 05:27:40 PM PDT 24
Finished Jul 14 05:27:46 PM PDT 24
Peak memory 222668 kb
Host smart-f04869ed-8962-41b1-8430-0d85215ebfd2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859538439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
prog_failure.859538439
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2338054578
Short name T708
Test name
Test status
Simulation time 6131756589 ps
CPU time 22.72 seconds
Started Jul 14 05:27:38 PM PDT 24
Finished Jul 14 05:28:01 PM PDT 24
Peak memory 217160 kb
Host smart-7527c8fe-9e37-44ee-931c-80cf355f3110
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338054578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2338054578
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2596788341
Short name T689
Test name
Test status
Simulation time 308378945 ps
CPU time 4.95 seconds
Started Jul 14 05:27:39 PM PDT 24
Finished Jul 14 05:27:44 PM PDT 24
Peak memory 216984 kb
Host smart-b7dff465-207a-41d6-ae44-3b42dc29c7f6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596788341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2596788341
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1157670736
Short name T317
Test name
Test status
Simulation time 12983911851 ps
CPU time 34.54 seconds
Started Jul 14 05:27:38 PM PDT 24
Finished Jul 14 05:28:13 PM PDT 24
Peak memory 250560 kb
Host smart-757edb9e-63cd-4c7f-a72d-e92659c35426
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157670736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1157670736
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1236310979
Short name T835
Test name
Test status
Simulation time 724319709 ps
CPU time 25.51 seconds
Started Jul 14 05:27:37 PM PDT 24
Finished Jul 14 05:28:04 PM PDT 24
Peak memory 250520 kb
Host smart-803480cb-303d-45db-9748-5958a4f9caf8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236310979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.1236310979
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.374362703
Short name T159
Test name
Test status
Simulation time 172937611 ps
CPU time 3.21 seconds
Started Jul 14 05:27:32 PM PDT 24
Finished Jul 14 05:27:36 PM PDT 24
Peak memory 221992 kb
Host smart-f9668ee0-d1aa-483b-b1e7-8379eade931b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374362703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.374362703
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1311682450
Short name T182
Test name
Test status
Simulation time 1243606091 ps
CPU time 12.8 seconds
Started Jul 14 05:27:37 PM PDT 24
Finished Jul 14 05:27:50 PM PDT 24
Peak memory 214192 kb
Host smart-9e0aa3df-3295-4990-8906-6b39f7b4db39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311682450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1311682450
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1130694863
Short name T66
Test name
Test status
Simulation time 134590569 ps
CPU time 23.76 seconds
Started Jul 14 05:27:42 PM PDT 24
Finished Jul 14 05:28:07 PM PDT 24
Peak memory 268544 kb
Host smart-de82dfce-2659-4b16-8b2b-7436b8d70f37
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130694863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1130694863
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2538527965
Short name T434
Test name
Test status
Simulation time 1689289752 ps
CPU time 18.26 seconds
Started Jul 14 05:27:37 PM PDT 24
Finished Jul 14 05:27:57 PM PDT 24
Peak memory 219448 kb
Host smart-ec297909-a3ac-4e58-a62a-4267729ab5e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538527965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2538527965
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2902279953
Short name T401
Test name
Test status
Simulation time 1772368304 ps
CPU time 10.76 seconds
Started Jul 14 05:27:47 PM PDT 24
Finished Jul 14 05:27:59 PM PDT 24
Peak memory 225312 kb
Host smart-fa329970-f504-4b5f-8c49-e290d4409e69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902279953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2902279953
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2587811657
Short name T704
Test name
Test status
Simulation time 286127173 ps
CPU time 10.8 seconds
Started Jul 14 05:27:37 PM PDT 24
Finished Jul 14 05:27:49 PM PDT 24
Peak memory 217892 kb
Host smart-c79344fd-a482-4601-a16f-94b0b1c600c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587811657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
587811657
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2886878861
Short name T360
Test name
Test status
Simulation time 435934162 ps
CPU time 15.5 seconds
Started Jul 14 05:27:43 PM PDT 24
Finished Jul 14 05:27:59 PM PDT 24
Peak memory 225452 kb
Host smart-2e52ecd9-ce52-4a7c-b09e-5e8635c55c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886878861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2886878861
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3460567001
Short name T429
Test name
Test status
Simulation time 827245749 ps
CPU time 5.44 seconds
Started Jul 14 05:27:33 PM PDT 24
Finished Jul 14 05:27:40 PM PDT 24
Peak memory 217060 kb
Host smart-3aed9fc8-800a-4d73-8a94-1e5c0ea2b9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460567001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3460567001
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2893804340
Short name T828
Test name
Test status
Simulation time 1142010586 ps
CPU time 32.51 seconds
Started Jul 14 05:27:32 PM PDT 24
Finished Jul 14 05:28:05 PM PDT 24
Peak memory 250700 kb
Host smart-b6c44089-373c-4e84-8091-7685cd3b25e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893804340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2893804340
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1122371479
Short name T337
Test name
Test status
Simulation time 192654712 ps
CPU time 3.2 seconds
Started Jul 14 05:27:36 PM PDT 24
Finished Jul 14 05:27:40 PM PDT 24
Peak memory 221976 kb
Host smart-1be90fb3-72af-427a-9d55-acffe8975720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122371479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1122371479
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.814597033
Short name T515
Test name
Test status
Simulation time 935268389 ps
CPU time 23.83 seconds
Started Jul 14 05:27:43 PM PDT 24
Finished Jul 14 05:28:08 PM PDT 24
Peak memory 250032 kb
Host smart-c76e918f-b6fa-4b52-b571-f20f231c1952
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814597033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.814597033
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1475196400
Short name T585
Test name
Test status
Simulation time 23781860 ps
CPU time 0.96 seconds
Started Jul 14 05:27:33 PM PDT 24
Finished Jul 14 05:27:35 PM PDT 24
Peak memory 208368 kb
Host smart-ddbdc967-ebb5-4cd6-86a6-5a74d04768d1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475196400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1475196400
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2058805818
Short name T684
Test name
Test status
Simulation time 16889779 ps
CPU time 1.18 seconds
Started Jul 14 05:29:58 PM PDT 24
Finished Jul 14 05:30:00 PM PDT 24
Peak memory 208504 kb
Host smart-65028c73-298a-4a0c-82e2-162b40c57ef8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058805818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2058805818
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3584024723
Short name T516
Test name
Test status
Simulation time 251681801 ps
CPU time 11.67 seconds
Started Jul 14 05:29:59 PM PDT 24
Finished Jul 14 05:30:12 PM PDT 24
Peak memory 217616 kb
Host smart-43a18f99-85d5-4a68-aae7-4cb0b52c3be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584024723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3584024723
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.3838626952
Short name T615
Test name
Test status
Simulation time 2463185100 ps
CPU time 16.33 seconds
Started Jul 14 05:29:59 PM PDT 24
Finished Jul 14 05:30:16 PM PDT 24
Peak memory 217140 kb
Host smart-45bb37be-4231-478f-a479-b1fff6c3ec6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838626952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3838626952
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3117353310
Short name T243
Test name
Test status
Simulation time 60802504 ps
CPU time 3.18 seconds
Started Jul 14 05:30:00 PM PDT 24
Finished Jul 14 05:30:04 PM PDT 24
Peak memory 217704 kb
Host smart-c374a0a7-0ec3-4f48-b212-f1dfeff2d267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117353310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3117353310
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.542462700
Short name T387
Test name
Test status
Simulation time 901014384 ps
CPU time 12.86 seconds
Started Jul 14 05:29:57 PM PDT 24
Finished Jul 14 05:30:11 PM PDT 24
Peak memory 225512 kb
Host smart-474e56d4-ed46-41c5-8b5f-7b0dfd380baf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542462700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.542462700
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.738842614
Short name T257
Test name
Test status
Simulation time 1182064500 ps
CPU time 8.21 seconds
Started Jul 14 05:29:58 PM PDT 24
Finished Jul 14 05:30:07 PM PDT 24
Peak memory 225496 kb
Host smart-f003ebe8-3357-4d3f-a5f4-18bfbde4a8fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738842614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.738842614
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3250848178
Short name T291
Test name
Test status
Simulation time 869864283 ps
CPU time 9.75 seconds
Started Jul 14 05:30:00 PM PDT 24
Finished Jul 14 05:30:11 PM PDT 24
Peak memory 217664 kb
Host smart-8d6981a9-26fb-4037-8792-5424d05a7cf7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250848178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3250848178
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1903665764
Short name T736
Test name
Test status
Simulation time 450691579 ps
CPU time 10.22 seconds
Started Jul 14 05:30:00 PM PDT 24
Finished Jul 14 05:30:11 PM PDT 24
Peak memory 224356 kb
Host smart-f6ac9f35-662e-4cd4-bf68-d7dd285feaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903665764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1903665764
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1795062803
Short name T817
Test name
Test status
Simulation time 63618859 ps
CPU time 3.22 seconds
Started Jul 14 05:29:58 PM PDT 24
Finished Jul 14 05:30:02 PM PDT 24
Peak memory 217056 kb
Host smart-858f3cd2-ef12-445b-87ad-2f40ca16c242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795062803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1795062803
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3354790031
Short name T841
Test name
Test status
Simulation time 1042378894 ps
CPU time 27.24 seconds
Started Jul 14 05:30:00 PM PDT 24
Finished Jul 14 05:30:28 PM PDT 24
Peak memory 250348 kb
Host smart-07802c30-7dde-4c68-87cc-7ff621f550ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354790031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3354790031
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2728880113
Short name T843
Test name
Test status
Simulation time 137075213 ps
CPU time 6.72 seconds
Started Jul 14 05:29:59 PM PDT 24
Finished Jul 14 05:30:06 PM PDT 24
Peak memory 246412 kb
Host smart-72c1f421-fad2-4d32-b7a7-0d525fb241f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728880113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2728880113
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2125309206
Short name T650
Test name
Test status
Simulation time 7967912821 ps
CPU time 70.33 seconds
Started Jul 14 05:29:57 PM PDT 24
Finished Jul 14 05:31:08 PM PDT 24
Peak memory 250508 kb
Host smart-ff671c9b-6000-4f38-a69f-4c5a9ed98cbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125309206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2125309206
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.616781728
Short name T363
Test name
Test status
Simulation time 11964485 ps
CPU time 0.78 seconds
Started Jul 14 05:29:58 PM PDT 24
Finished Jul 14 05:30:00 PM PDT 24
Peak memory 208316 kb
Host smart-6479d8c5-aae2-4bed-a55d-de1ac09c74b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616781728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.616781728
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3321815147
Short name T154
Test name
Test status
Simulation time 198792344 ps
CPU time 0.86 seconds
Started Jul 14 05:30:05 PM PDT 24
Finished Jul 14 05:30:07 PM PDT 24
Peak memory 208252 kb
Host smart-ffb0cd32-01e3-489f-8997-df42c80ad379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321815147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3321815147
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.595385591
Short name T811
Test name
Test status
Simulation time 1098022475 ps
CPU time 12.4 seconds
Started Jul 14 05:30:04 PM PDT 24
Finished Jul 14 05:30:18 PM PDT 24
Peak memory 217704 kb
Host smart-d15eb62a-55a6-4c14-a78c-328655d5983e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595385591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.595385591
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.4209610898
Short name T553
Test name
Test status
Simulation time 547051328 ps
CPU time 3.66 seconds
Started Jul 14 05:30:05 PM PDT 24
Finished Jul 14 05:30:10 PM PDT 24
Peak memory 216620 kb
Host smart-76453ca3-2227-4ecc-a3a4-55ee05f762b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209610898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.4209610898
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.768456762
Short name T687
Test name
Test status
Simulation time 65109720 ps
CPU time 2.93 seconds
Started Jul 14 05:30:04 PM PDT 24
Finished Jul 14 05:30:08 PM PDT 24
Peak memory 217668 kb
Host smart-ceaa02fa-c407-4ec0-9c5f-0d333e9bc620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768456762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.768456762
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.685075175
Short name T686
Test name
Test status
Simulation time 692227754 ps
CPU time 15.57 seconds
Started Jul 14 05:30:03 PM PDT 24
Finished Jul 14 05:30:20 PM PDT 24
Peak memory 225428 kb
Host smart-052f631d-4c2a-4906-bc4f-00b6ec2095bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685075175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di
gest.685075175
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3963468091
Short name T822
Test name
Test status
Simulation time 2010804734 ps
CPU time 9.49 seconds
Started Jul 14 05:30:03 PM PDT 24
Finished Jul 14 05:30:14 PM PDT 24
Peak memory 217544 kb
Host smart-72e5ea2d-30eb-429a-9409-b7219d585ce5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963468091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3963468091
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1345482371
Short name T411
Test name
Test status
Simulation time 881627034 ps
CPU time 9.83 seconds
Started Jul 14 05:30:01 PM PDT 24
Finished Jul 14 05:30:11 PM PDT 24
Peak memory 217784 kb
Host smart-a90e1aa0-fa58-481e-8e9f-921b7c0fd42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345482371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1345482371
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1932954195
Short name T244
Test name
Test status
Simulation time 952038496 ps
CPU time 7.22 seconds
Started Jul 14 05:29:58 PM PDT 24
Finished Jul 14 05:30:06 PM PDT 24
Peak memory 217152 kb
Host smart-376389ed-2a2d-47f4-9fb0-f4098b83be46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932954195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1932954195
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.898256778
Short name T607
Test name
Test status
Simulation time 1341058691 ps
CPU time 32.05 seconds
Started Jul 14 05:30:04 PM PDT 24
Finished Jul 14 05:30:37 PM PDT 24
Peak memory 250452 kb
Host smart-ede22275-8069-423c-ba25-ea878c0f6614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898256778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.898256778
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2705523376
Short name T783
Test name
Test status
Simulation time 240426063 ps
CPU time 7.35 seconds
Started Jul 14 05:30:05 PM PDT 24
Finished Jul 14 05:30:14 PM PDT 24
Peak memory 249876 kb
Host smart-876de18c-c718-428c-bdad-fdbb526d2838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705523376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2705523376
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.4286634307
Short name T706
Test name
Test status
Simulation time 3773450090 ps
CPU time 25.65 seconds
Started Jul 14 05:30:03 PM PDT 24
Finished Jul 14 05:30:31 PM PDT 24
Peak memory 250400 kb
Host smart-4c367f88-a97f-492f-a194-f51f116cde8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286634307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.4286634307
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.431288401
Short name T593
Test name
Test status
Simulation time 14649395 ps
CPU time 1.07 seconds
Started Jul 14 05:29:59 PM PDT 24
Finished Jul 14 05:30:01 PM PDT 24
Peak memory 208432 kb
Host smart-0ef6bbb4-c758-4511-94f3-e0dba42a692b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431288401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ct
rl_volatile_unlock_smoke.431288401
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3855296081
Short name T324
Test name
Test status
Simulation time 19325112 ps
CPU time 0.9 seconds
Started Jul 14 05:30:10 PM PDT 24
Finished Jul 14 05:30:11 PM PDT 24
Peak memory 208428 kb
Host smart-8c90ba4c-c08c-4c35-9358-9c18f414cb1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855296081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3855296081
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3093278670
Short name T335
Test name
Test status
Simulation time 340150581 ps
CPU time 12.09 seconds
Started Jul 14 05:30:03 PM PDT 24
Finished Jul 14 05:30:16 PM PDT 24
Peak memory 225508 kb
Host smart-c128909c-3f5c-44c1-a0b0-c5871122ec97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093278670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3093278670
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.577273769
Short name T743
Test name
Test status
Simulation time 278865947 ps
CPU time 7.17 seconds
Started Jul 14 05:30:04 PM PDT 24
Finished Jul 14 05:30:12 PM PDT 24
Peak memory 217088 kb
Host smart-9e1e0756-6228-4f20-9ab4-9bddd532643e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577273769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.577273769
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.287946354
Short name T551
Test name
Test status
Simulation time 929940377 ps
CPU time 4.72 seconds
Started Jul 14 05:30:06 PM PDT 24
Finished Jul 14 05:30:12 PM PDT 24
Peak memory 217636 kb
Host smart-bc0588cf-dda8-4ff2-8582-c31a69ea26dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287946354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.287946354
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3299077109
Short name T812
Test name
Test status
Simulation time 1939056822 ps
CPU time 12.84 seconds
Started Jul 14 05:30:04 PM PDT 24
Finished Jul 14 05:30:19 PM PDT 24
Peak memory 225088 kb
Host smart-621f10d6-c761-4442-ae5e-ca3ed3a6f22d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299077109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3299077109
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3674079187
Short name T266
Test name
Test status
Simulation time 484125808 ps
CPU time 12.42 seconds
Started Jul 14 05:30:05 PM PDT 24
Finished Jul 14 05:30:19 PM PDT 24
Peak memory 225452 kb
Host smart-4bcde407-ea5f-4916-80eb-d3952b8bda2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674079187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3674079187
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1706622937
Short name T771
Test name
Test status
Simulation time 199078908 ps
CPU time 6.29 seconds
Started Jul 14 05:30:05 PM PDT 24
Finished Jul 14 05:30:13 PM PDT 24
Peak memory 224232 kb
Host smart-86ed0d23-65da-4ede-9893-0a2181e734e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706622937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1706622937
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.55087183
Short name T589
Test name
Test status
Simulation time 876800610 ps
CPU time 7.65 seconds
Started Jul 14 05:30:04 PM PDT 24
Finished Jul 14 05:30:13 PM PDT 24
Peak memory 217652 kb
Host smart-4742341f-1d92-4f5c-8ad2-0fadb91bd8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55087183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.55087183
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.922018849
Short name T246
Test name
Test status
Simulation time 31721347 ps
CPU time 1.03 seconds
Started Jul 14 05:30:03 PM PDT 24
Finished Jul 14 05:30:05 PM PDT 24
Peak memory 217076 kb
Host smart-4747542c-4c47-47b1-88a7-045a3edf88d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922018849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.922018849
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2143312442
Short name T402
Test name
Test status
Simulation time 881538664 ps
CPU time 17.32 seconds
Started Jul 14 05:30:04 PM PDT 24
Finished Jul 14 05:30:22 PM PDT 24
Peak memory 250468 kb
Host smart-6032f39a-d67e-479d-9093-4908e51506e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143312442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2143312442
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.4030917237
Short name T698
Test name
Test status
Simulation time 724499616 ps
CPU time 7.96 seconds
Started Jul 14 05:30:04 PM PDT 24
Finished Jul 14 05:30:13 PM PDT 24
Peak memory 250424 kb
Host smart-5fb631c4-0c59-4dd2-a19a-edfdd84e02c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030917237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.4030917237
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.4016371114
Short name T549
Test name
Test status
Simulation time 2415263332 ps
CPU time 85.98 seconds
Started Jul 14 05:30:03 PM PDT 24
Finished Jul 14 05:31:30 PM PDT 24
Peak memory 283228 kb
Host smart-0542d4b5-b846-4b3d-9562-bf530536099f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016371114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.4016371114
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2504600763
Short name T143
Test name
Test status
Simulation time 115271453135 ps
CPU time 938.78 seconds
Started Jul 14 05:30:09 PM PDT 24
Finished Jul 14 05:45:48 PM PDT 24
Peak memory 283660 kb
Host smart-16197c9b-9f04-433a-9a33-ef145973714b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2504600763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.2504600763
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.249350281
Short name T462
Test name
Test status
Simulation time 40829287 ps
CPU time 1.36 seconds
Started Jul 14 05:30:04 PM PDT 24
Finished Jul 14 05:30:07 PM PDT 24
Peak memory 212360 kb
Host smart-ae33999f-d2c4-462d-8e83-fe912bcbf42b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249350281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.249350281
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.582888598
Short name T730
Test name
Test status
Simulation time 20348181 ps
CPU time 0.94 seconds
Started Jul 14 05:30:08 PM PDT 24
Finished Jul 14 05:30:09 PM PDT 24
Peak memory 208464 kb
Host smart-82dff06a-b45f-47f9-8bdd-1b41ac24dbc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582888598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.582888598
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.60591501
Short name T33
Test name
Test status
Simulation time 2985507393 ps
CPU time 14.63 seconds
Started Jul 14 05:30:08 PM PDT 24
Finished Jul 14 05:30:23 PM PDT 24
Peak memory 218400 kb
Host smart-07d763a1-96b4-4f3d-ac91-630323c2b22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60591501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.60591501
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3896150174
Short name T572
Test name
Test status
Simulation time 3275939628 ps
CPU time 3.83 seconds
Started Jul 14 05:30:11 PM PDT 24
Finished Jul 14 05:30:16 PM PDT 24
Peak memory 217180 kb
Host smart-85367bf8-bbe4-4440-b183-611d6bad114b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896150174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3896150174
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1356233099
Short name T486
Test name
Test status
Simulation time 220851001 ps
CPU time 2.49 seconds
Started Jul 14 05:30:09 PM PDT 24
Finished Jul 14 05:30:12 PM PDT 24
Peak memory 217632 kb
Host smart-d62533af-bdcf-49d0-b072-8bec8a12c368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356233099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1356233099
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.3259115660
Short name T58
Test name
Test status
Simulation time 1961044537 ps
CPU time 10.76 seconds
Started Jul 14 05:30:07 PM PDT 24
Finished Jul 14 05:30:18 PM PDT 24
Peak memory 225456 kb
Host smart-085de487-49ac-4119-98f9-12c5d0459dac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259115660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.3259115660
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3033452371
Short name T678
Test name
Test status
Simulation time 575712920 ps
CPU time 8.12 seconds
Started Jul 14 05:30:08 PM PDT 24
Finished Jul 14 05:30:16 PM PDT 24
Peak memory 217604 kb
Host smart-9c48080d-696c-46e8-a10a-bd83e731c6e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033452371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3033452371
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3357410302
Short name T451
Test name
Test status
Simulation time 1223040734 ps
CPU time 8.7 seconds
Started Jul 14 05:30:11 PM PDT 24
Finished Jul 14 05:30:21 PM PDT 24
Peak memory 225536 kb
Host smart-3ac53c71-6fc6-4a96-ab8e-b700ecc3fcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357410302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3357410302
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1399493426
Short name T659
Test name
Test status
Simulation time 47088500 ps
CPU time 3.02 seconds
Started Jul 14 05:30:08 PM PDT 24
Finished Jul 14 05:30:11 PM PDT 24
Peak memory 217244 kb
Host smart-271239e7-8b8d-45a9-91f9-6318026cf41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399493426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1399493426
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3154483799
Short name T395
Test name
Test status
Simulation time 2573128298 ps
CPU time 29.27 seconds
Started Jul 14 05:30:11 PM PDT 24
Finished Jul 14 05:30:41 PM PDT 24
Peak memory 250440 kb
Host smart-69185af5-3730-4f26-8e37-6105f663e57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154483799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3154483799
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2537606333
Short name T685
Test name
Test status
Simulation time 108191146 ps
CPU time 7.74 seconds
Started Jul 14 05:30:11 PM PDT 24
Finished Jul 14 05:30:20 PM PDT 24
Peak memory 246560 kb
Host smart-644dbc8e-3bec-46da-939b-55f4d0862664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537606333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2537606333
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.3229220850
Short name T381
Test name
Test status
Simulation time 3777151973 ps
CPU time 134.59 seconds
Started Jul 14 05:30:09 PM PDT 24
Finished Jul 14 05:32:24 PM PDT 24
Peak memory 250448 kb
Host smart-bc3f1575-cf77-4ab3-9779-cc6d594c682c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229220850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.3229220850
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.2172072107
Short name T153
Test name
Test status
Simulation time 42074806058 ps
CPU time 1269.79 seconds
Started Jul 14 05:30:08 PM PDT 24
Finished Jul 14 05:51:19 PM PDT 24
Peak memory 316136 kb
Host smart-c95d54d1-df80-4baf-9fe7-5b72460ff9fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2172072107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.2172072107
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1266186723
Short name T28
Test name
Test status
Simulation time 10940481 ps
CPU time 0.96 seconds
Started Jul 14 05:30:11 PM PDT 24
Finished Jul 14 05:30:13 PM PDT 24
Peak memory 208544 kb
Host smart-a14858e5-69b7-4f67-aaf8-0e34ad140d57
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266186723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1266186723
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2828789967
Short name T562
Test name
Test status
Simulation time 54383247 ps
CPU time 1.06 seconds
Started Jul 14 05:30:15 PM PDT 24
Finished Jul 14 05:30:17 PM PDT 24
Peak memory 208600 kb
Host smart-9864dcd3-9733-4af9-bd45-27755bcc21a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828789967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2828789967
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1876716850
Short name T475
Test name
Test status
Simulation time 420761853 ps
CPU time 12.85 seconds
Started Jul 14 05:30:15 PM PDT 24
Finished Jul 14 05:30:28 PM PDT 24
Peak memory 217776 kb
Host smart-20ad5820-878c-44d1-8fd6-83011b7fc67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876716850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1876716850
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1901355770
Short name T5
Test name
Test status
Simulation time 286893463 ps
CPU time 7.91 seconds
Started Jul 14 05:30:17 PM PDT 24
Finished Jul 14 05:30:26 PM PDT 24
Peak memory 217008 kb
Host smart-fdf5312e-5e81-4c92-915a-691e9f9afe7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901355770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1901355770
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3877737966
Short name T276
Test name
Test status
Simulation time 158970414 ps
CPU time 2.44 seconds
Started Jul 14 05:30:14 PM PDT 24
Finished Jul 14 05:30:17 PM PDT 24
Peak memory 217720 kb
Host smart-08e1256c-9fed-4219-8a8b-56e87d2b483c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877737966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3877737966
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.577228206
Short name T253
Test name
Test status
Simulation time 1678102139 ps
CPU time 10.91 seconds
Started Jul 14 05:30:14 PM PDT 24
Finished Jul 14 05:30:26 PM PDT 24
Peak memory 225448 kb
Host smart-d9553011-8831-4927-bbda-a3009e2bfdf9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577228206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.577228206
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2798287767
Short name T265
Test name
Test status
Simulation time 238129283 ps
CPU time 6.16 seconds
Started Jul 14 05:30:14 PM PDT 24
Finished Jul 14 05:30:21 PM PDT 24
Peak memory 217604 kb
Host smart-e6b226f6-ad5e-44ed-88a0-c35ad68dfd4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798287767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2798287767
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.4162193682
Short name T345
Test name
Test status
Simulation time 330564434 ps
CPU time 8.51 seconds
Started Jul 14 05:30:16 PM PDT 24
Finished Jul 14 05:30:26 PM PDT 24
Peak memory 224508 kb
Host smart-6a6b1c50-f79f-4e65-a941-852b671d295e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162193682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.4162193682
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3612040117
Short name T777
Test name
Test status
Simulation time 19444244 ps
CPU time 1.47 seconds
Started Jul 14 05:30:09 PM PDT 24
Finished Jul 14 05:30:11 PM PDT 24
Peak memory 217188 kb
Host smart-5fd65839-4804-4a3b-ad28-62eef5005599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612040117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3612040117
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2097186999
Short name T482
Test name
Test status
Simulation time 811342492 ps
CPU time 22.15 seconds
Started Jul 14 05:30:16 PM PDT 24
Finished Jul 14 05:30:39 PM PDT 24
Peak memory 250440 kb
Host smart-02bcacb1-879a-40ff-aa69-c916f443dc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097186999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2097186999
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1249205838
Short name T375
Test name
Test status
Simulation time 55906979 ps
CPU time 8.84 seconds
Started Jul 14 05:30:16 PM PDT 24
Finished Jul 14 05:30:26 PM PDT 24
Peak memory 250448 kb
Host smart-6bf60be8-adc2-470a-be2c-28468ecbc3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249205838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1249205838
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.4014099576
Short name T722
Test name
Test status
Simulation time 22306144471 ps
CPU time 174.22 seconds
Started Jul 14 05:30:18 PM PDT 24
Finished Jul 14 05:33:13 PM PDT 24
Peak memory 275504 kb
Host smart-2284155d-1caf-46e7-9f87-dd1e0111650e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014099576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.4014099576
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1262935547
Short name T87
Test name
Test status
Simulation time 58604878 ps
CPU time 1.06 seconds
Started Jul 14 05:30:15 PM PDT 24
Finished Jul 14 05:30:17 PM PDT 24
Peak memory 208408 kb
Host smart-e4520be3-92fe-485b-9334-5f9e9f662731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262935547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1262935547
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1282515072
Short name T844
Test name
Test status
Simulation time 1218317182 ps
CPU time 12.55 seconds
Started Jul 14 05:30:16 PM PDT 24
Finished Jul 14 05:30:30 PM PDT 24
Peak memory 225484 kb
Host smart-4695d3f4-32b7-4540-81ff-2390519d7e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282515072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1282515072
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.91315609
Short name T657
Test name
Test status
Simulation time 211057878 ps
CPU time 3.07 seconds
Started Jul 14 05:30:16 PM PDT 24
Finished Jul 14 05:30:20 PM PDT 24
Peak memory 216608 kb
Host smart-4a08103a-fc52-4ea1-98c9-737abfa4b398
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91315609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.91315609
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3545769025
Short name T168
Test name
Test status
Simulation time 236000756 ps
CPU time 3.56 seconds
Started Jul 14 05:30:16 PM PDT 24
Finished Jul 14 05:30:20 PM PDT 24
Peak memory 217660 kb
Host smart-1e2867c8-9810-45a3-a871-7ca19a53e3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545769025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3545769025
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.491938664
Short name T299
Test name
Test status
Simulation time 2247442785 ps
CPU time 13.06 seconds
Started Jul 14 05:30:15 PM PDT 24
Finished Jul 14 05:30:30 PM PDT 24
Peak memory 218392 kb
Host smart-d2190ea6-97a5-40d0-bae5-a9e4c9e8efb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491938664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.491938664
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1256867164
Short name T428
Test name
Test status
Simulation time 6006350468 ps
CPU time 14.25 seconds
Started Jul 14 05:30:15 PM PDT 24
Finished Jul 14 05:30:30 PM PDT 24
Peak memory 225504 kb
Host smart-614f7aef-946b-4fe1-96d0-7845165a51d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256867164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.1256867164
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1867390246
Short name T814
Test name
Test status
Simulation time 286156922 ps
CPU time 11.93 seconds
Started Jul 14 05:30:19 PM PDT 24
Finished Jul 14 05:30:31 PM PDT 24
Peak memory 217544 kb
Host smart-29d27db0-d531-4897-8c2b-a8884becd838
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867390246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1867390246
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2026416256
Short name T296
Test name
Test status
Simulation time 639071080 ps
CPU time 8.43 seconds
Started Jul 14 05:30:15 PM PDT 24
Finished Jul 14 05:30:24 PM PDT 24
Peak memory 224012 kb
Host smart-8b0987da-9667-4ec9-aa1a-f256b1f1e16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026416256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2026416256
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.356028975
Short name T784
Test name
Test status
Simulation time 128767149 ps
CPU time 3.4 seconds
Started Jul 14 05:30:14 PM PDT 24
Finished Jul 14 05:30:18 PM PDT 24
Peak memory 217104 kb
Host smart-43cb0495-d83d-4c3e-b592-177db9694ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356028975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.356028975
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.4191572457
Short name T455
Test name
Test status
Simulation time 494124198 ps
CPU time 26.04 seconds
Started Jul 14 05:30:15 PM PDT 24
Finished Jul 14 05:30:43 PM PDT 24
Peak memory 250420 kb
Host smart-46a6ae0b-35ec-475d-888d-91e1a3b9557b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191572457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.4191572457
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.302349285
Short name T676
Test name
Test status
Simulation time 124921440 ps
CPU time 4 seconds
Started Jul 14 05:30:15 PM PDT 24
Finished Jul 14 05:30:20 PM PDT 24
Peak memory 221928 kb
Host smart-04d5fd7e-e488-4ee5-9fde-28c7891b0878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302349285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.302349285
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1323265654
Short name T15
Test name
Test status
Simulation time 5690278398 ps
CPU time 172.6 seconds
Started Jul 14 05:30:14 PM PDT 24
Finished Jul 14 05:33:08 PM PDT 24
Peak memory 251100 kb
Host smart-2b7f2b9f-2604-4993-a9b0-57499d70af6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323265654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1323265654
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2082629445
Short name T655
Test name
Test status
Simulation time 15686843 ps
CPU time 1.02 seconds
Started Jul 14 05:30:16 PM PDT 24
Finished Jul 14 05:30:18 PM PDT 24
Peak memory 208528 kb
Host smart-4984b6d6-4a57-4505-a7c2-0585a0926608
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082629445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2082629445
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.2144037817
Short name T499
Test name
Test status
Simulation time 16500220 ps
CPU time 1.1 seconds
Started Jul 14 05:30:28 PM PDT 24
Finished Jul 14 05:30:31 PM PDT 24
Peak memory 208460 kb
Host smart-69fc04ac-1714-4842-9075-e89bfe1fd226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144037817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2144037817
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1234548406
Short name T386
Test name
Test status
Simulation time 2008511796 ps
CPU time 12.83 seconds
Started Jul 14 05:30:29 PM PDT 24
Finished Jul 14 05:30:44 PM PDT 24
Peak memory 217696 kb
Host smart-377487ea-c50e-402e-a593-1fcee6faaea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234548406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1234548406
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3281698095
Short name T22
Test name
Test status
Simulation time 399364483 ps
CPU time 3.9 seconds
Started Jul 14 05:30:29 PM PDT 24
Finished Jul 14 05:30:35 PM PDT 24
Peak memory 216724 kb
Host smart-b35124b9-10ce-4505-be5a-65996e553551
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281698095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3281698095
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3505215737
Short name T489
Test name
Test status
Simulation time 144337279 ps
CPU time 3.12 seconds
Started Jul 14 05:30:25 PM PDT 24
Finished Jul 14 05:30:28 PM PDT 24
Peak memory 217680 kb
Host smart-a7aae1f8-f5e8-4d23-9bd2-807dcaa8cf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505215737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3505215737
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1631263405
Short name T733
Test name
Test status
Simulation time 3725365053 ps
CPU time 14.46 seconds
Started Jul 14 05:30:26 PM PDT 24
Finished Jul 14 05:30:42 PM PDT 24
Peak memory 225520 kb
Host smart-a0a86cb7-b938-4b08-912d-609787499caa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631263405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1631263405
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.349782220
Short name T756
Test name
Test status
Simulation time 1312551736 ps
CPU time 11.5 seconds
Started Jul 14 05:30:29 PM PDT 24
Finished Jul 14 05:30:43 PM PDT 24
Peak memory 225420 kb
Host smart-0fd198da-8435-443e-b1cc-06004e30bc3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349782220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.349782220
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2689869561
Short name T539
Test name
Test status
Simulation time 993223156 ps
CPU time 7.64 seconds
Started Jul 14 05:30:25 PM PDT 24
Finished Jul 14 05:30:33 PM PDT 24
Peak memory 217636 kb
Host smart-78ec0fd6-4843-4b0a-b68f-6b4258c5e620
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689869561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2689869561
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3501955506
Short name T575
Test name
Test status
Simulation time 406563018 ps
CPU time 6.88 seconds
Started Jul 14 05:30:26 PM PDT 24
Finished Jul 14 05:30:34 PM PDT 24
Peak memory 225492 kb
Host smart-6387e77e-2b00-436a-b65c-59fbb0418e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501955506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3501955506
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3999716559
Short name T458
Test name
Test status
Simulation time 28792818 ps
CPU time 2 seconds
Started Jul 14 05:30:15 PM PDT 24
Finished Jul 14 05:30:18 PM PDT 24
Peak memory 213432 kb
Host smart-4f617d3d-956d-4d9f-8716-c991dc14a30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999716559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3999716559
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2174334594
Short name T354
Test name
Test status
Simulation time 3107560176 ps
CPU time 30.27 seconds
Started Jul 14 05:30:27 PM PDT 24
Finished Jul 14 05:31:00 PM PDT 24
Peak memory 250508 kb
Host smart-b95b5719-ff8e-45a4-9332-2ce90f28dd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174334594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2174334594
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.1181375265
Short name T501
Test name
Test status
Simulation time 143230138 ps
CPU time 6.25 seconds
Started Jul 14 05:30:29 PM PDT 24
Finished Jul 14 05:30:37 PM PDT 24
Peak memory 246412 kb
Host smart-42c49e87-441d-4fbc-923d-8544fa07804a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181375265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1181375265
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.4286126717
Short name T57
Test name
Test status
Simulation time 2243894988 ps
CPU time 74.05 seconds
Started Jul 14 05:30:26 PM PDT 24
Finished Jul 14 05:31:41 PM PDT 24
Peak memory 250516 kb
Host smart-7907ea48-7c8b-4763-a9db-2303412dfcd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286126717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.4286126717
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.3239677800
Short name T89
Test name
Test status
Simulation time 26888923366 ps
CPU time 433.88 seconds
Started Jul 14 05:30:27 PM PDT 24
Finished Jul 14 05:37:43 PM PDT 24
Peak memory 349444 kb
Host smart-e8daaced-458d-4af7-960f-d0501302b04f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3239677800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.3239677800
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1707905903
Short name T27
Test name
Test status
Simulation time 14656864 ps
CPU time 0.95 seconds
Started Jul 14 05:30:14 PM PDT 24
Finished Jul 14 05:30:16 PM PDT 24
Peak memory 211316 kb
Host smart-59362d7d-c099-4eaf-a166-9ef16ee1ab72
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707905903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1707905903
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1893036836
Short name T494
Test name
Test status
Simulation time 20888640 ps
CPU time 1.01 seconds
Started Jul 14 05:30:29 PM PDT 24
Finished Jul 14 05:30:32 PM PDT 24
Peak memory 208412 kb
Host smart-8511e5e9-6780-4e98-b49c-43abe2501005
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893036836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1893036836
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.605480763
Short name T732
Test name
Test status
Simulation time 1071651507 ps
CPU time 12.27 seconds
Started Jul 14 05:30:27 PM PDT 24
Finished Jul 14 05:30:41 PM PDT 24
Peak memory 225520 kb
Host smart-a6347279-247f-4f49-84a6-3ae24e9b8fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605480763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.605480763
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2701228910
Short name T20
Test name
Test status
Simulation time 174905917 ps
CPU time 3.14 seconds
Started Jul 14 05:30:28 PM PDT 24
Finished Jul 14 05:30:34 PM PDT 24
Peak memory 216568 kb
Host smart-36038c7c-55c0-40d0-91f4-25fae36995e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701228910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2701228910
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2435364793
Short name T577
Test name
Test status
Simulation time 178171084 ps
CPU time 3.28 seconds
Started Jul 14 05:30:30 PM PDT 24
Finished Jul 14 05:30:35 PM PDT 24
Peak memory 217700 kb
Host smart-c7fe1e63-b9ad-49e5-b442-d3c22203f8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435364793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2435364793
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.642246087
Short name T383
Test name
Test status
Simulation time 1720341658 ps
CPU time 14.77 seconds
Started Jul 14 05:30:27 PM PDT 24
Finished Jul 14 05:30:43 PM PDT 24
Peak memory 218476 kb
Host smart-d0909974-8262-49fa-9abe-84d420ce426d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642246087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.642246087
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3270380072
Short name T729
Test name
Test status
Simulation time 442254261 ps
CPU time 12.74 seconds
Started Jul 14 05:30:29 PM PDT 24
Finished Jul 14 05:30:44 PM PDT 24
Peak memory 225424 kb
Host smart-9da68c99-80b2-48e3-b3ed-4655da20c5c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270380072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3270380072
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3931007665
Short name T646
Test name
Test status
Simulation time 1495152454 ps
CPU time 9.37 seconds
Started Jul 14 05:30:29 PM PDT 24
Finished Jul 14 05:30:40 PM PDT 24
Peak memory 225360 kb
Host smart-cb103614-6aee-4c11-ab81-4dec273e73ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931007665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3931007665
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.341298431
Short name T48
Test name
Test status
Simulation time 1883690107 ps
CPU time 9.32 seconds
Started Jul 14 05:30:27 PM PDT 24
Finished Jul 14 05:30:38 PM PDT 24
Peak memory 225504 kb
Host smart-41ba8301-cbd4-46ef-8f05-b710dbe089ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341298431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.341298431
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.3192767119
Short name T385
Test name
Test status
Simulation time 103678535 ps
CPU time 6.16 seconds
Started Jul 14 05:30:29 PM PDT 24
Finished Jul 14 05:30:37 PM PDT 24
Peak memory 217140 kb
Host smart-2925351f-5ede-40ae-8a06-6a535cf6b8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192767119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3192767119
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2853472216
Short name T218
Test name
Test status
Simulation time 298153790 ps
CPU time 20.85 seconds
Started Jul 14 05:30:28 PM PDT 24
Finished Jul 14 05:30:51 PM PDT 24
Peak memory 250456 kb
Host smart-32c531bd-1ca5-415a-a359-6eebe45dd749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853472216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2853472216
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.4139173243
Short name T559
Test name
Test status
Simulation time 256830652 ps
CPU time 8.15 seconds
Started Jul 14 05:30:26 PM PDT 24
Finished Jul 14 05:30:35 PM PDT 24
Peak memory 250488 kb
Host smart-b6a5007e-e27a-4ee0-b5bd-628dcba9e0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139173243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.4139173243
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2511574478
Short name T29
Test name
Test status
Simulation time 474842744 ps
CPU time 15.97 seconds
Started Jul 14 05:30:27 PM PDT 24
Finished Jul 14 05:30:44 PM PDT 24
Peak memory 225500 kb
Host smart-7d6ffb5a-9404-4b5b-aa73-bc4459037f16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511574478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2511574478
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.1904540182
Short name T146
Test name
Test status
Simulation time 122273100786 ps
CPU time 1116.53 seconds
Started Jul 14 05:30:27 PM PDT 24
Finished Jul 14 05:49:05 PM PDT 24
Peak memory 496384 kb
Host smart-5eb32d50-2b6d-47cd-8291-0e4649ba9123
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1904540182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.1904540182
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3097070104
Short name T647
Test name
Test status
Simulation time 38198968 ps
CPU time 0.78 seconds
Started Jul 14 05:30:25 PM PDT 24
Finished Jul 14 05:30:26 PM PDT 24
Peak memory 208164 kb
Host smart-8e99e448-718b-48d8-9f9a-46aa3f549cf8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097070104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3097070104
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3661885072
Short name T170
Test name
Test status
Simulation time 45287626 ps
CPU time 1.34 seconds
Started Jul 14 05:30:29 PM PDT 24
Finished Jul 14 05:30:33 PM PDT 24
Peak memory 208508 kb
Host smart-57ebddf0-19b6-4e19-af29-ad41c7355b84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661885072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3661885072
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.3658954455
Short name T37
Test name
Test status
Simulation time 302974703 ps
CPU time 14.52 seconds
Started Jul 14 05:30:28 PM PDT 24
Finished Jul 14 05:30:45 PM PDT 24
Peak memory 225460 kb
Host smart-d3231e65-f268-422c-80d5-6d1c47e00457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658954455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3658954455
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1391220782
Short name T745
Test name
Test status
Simulation time 2054726970 ps
CPU time 9.31 seconds
Started Jul 14 05:30:28 PM PDT 24
Finished Jul 14 05:30:39 PM PDT 24
Peak memory 217052 kb
Host smart-fdf95e1a-7683-4950-98c2-9de89bd2f888
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391220782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1391220782
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.4265589892
Short name T282
Test name
Test status
Simulation time 89622262 ps
CPU time 4.15 seconds
Started Jul 14 05:30:27 PM PDT 24
Finished Jul 14 05:30:33 PM PDT 24
Peak memory 217644 kb
Host smart-faef2fb8-c525-4775-8333-3882bd337608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265589892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.4265589892
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2594761415
Short name T538
Test name
Test status
Simulation time 1461701936 ps
CPU time 14.6 seconds
Started Jul 14 05:30:28 PM PDT 24
Finished Jul 14 05:30:44 PM PDT 24
Peak memory 225472 kb
Host smart-6cce9d89-0a14-4171-8712-7c2b51617362
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594761415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2594761415
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3744905949
Short name T794
Test name
Test status
Simulation time 1496284439 ps
CPU time 13.8 seconds
Started Jul 14 05:30:28 PM PDT 24
Finished Jul 14 05:30:44 PM PDT 24
Peak memory 225440 kb
Host smart-f0958b1f-a965-4216-94e1-bcde24e4fa59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744905949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3744905949
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.958152065
Short name T680
Test name
Test status
Simulation time 288618000 ps
CPU time 12.24 seconds
Started Jul 14 05:30:29 PM PDT 24
Finished Jul 14 05:30:43 PM PDT 24
Peak memory 225420 kb
Host smart-b8f2adee-cafb-4b99-a8de-a0fe8715c0b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958152065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.958152065
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2327106062
Short name T209
Test name
Test status
Simulation time 1376106622 ps
CPU time 9.71 seconds
Started Jul 14 05:30:27 PM PDT 24
Finished Jul 14 05:30:38 PM PDT 24
Peak memory 225520 kb
Host smart-b00a0535-afa3-42ca-a8f6-4fb69f0efb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327106062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2327106062
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.334849736
Short name T636
Test name
Test status
Simulation time 172270551 ps
CPU time 2.79 seconds
Started Jul 14 05:30:26 PM PDT 24
Finished Jul 14 05:30:30 PM PDT 24
Peak memory 214012 kb
Host smart-4b73ef6b-e923-4ace-a3e4-02f59650c4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334849736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.334849736
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2844543542
Short name T331
Test name
Test status
Simulation time 405331238 ps
CPU time 25.27 seconds
Started Jul 14 05:30:28 PM PDT 24
Finished Jul 14 05:30:55 PM PDT 24
Peak memory 250384 kb
Host smart-7747759c-2512-456c-bc86-2e314f1a0219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844543542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2844543542
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2033526499
Short name T226
Test name
Test status
Simulation time 225604743 ps
CPU time 6.29 seconds
Started Jul 14 05:30:30 PM PDT 24
Finished Jul 14 05:30:38 PM PDT 24
Peak memory 249944 kb
Host smart-daceb117-1d42-4734-b394-99475cadd7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033526499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2033526499
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.53512776
Short name T759
Test name
Test status
Simulation time 19970349828 ps
CPU time 280.86 seconds
Started Jul 14 05:30:25 PM PDT 24
Finished Jul 14 05:35:07 PM PDT 24
Peak memory 250424 kb
Host smart-37c6031c-c0c6-4e17-bfff-b85115a3ce67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53512776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.lc_ctrl_stress_all.53512776
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1063788831
Short name T513
Test name
Test status
Simulation time 35435089 ps
CPU time 1.04 seconds
Started Jul 14 05:30:27 PM PDT 24
Finished Jul 14 05:30:29 PM PDT 24
Peak memory 211336 kb
Host smart-abb7e67b-e83c-4e2e-b20b-7316cb895ce7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063788831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1063788831
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1804752052
Short name T744
Test name
Test status
Simulation time 76465464 ps
CPU time 0.94 seconds
Started Jul 14 05:30:35 PM PDT 24
Finished Jul 14 05:30:37 PM PDT 24
Peak memory 208424 kb
Host smart-c83a0ddb-ae2b-43c7-85da-d0ab733794b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804752052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1804752052
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2622935977
Short name T782
Test name
Test status
Simulation time 593107113 ps
CPU time 10.35 seconds
Started Jul 14 05:30:33 PM PDT 24
Finished Jul 14 05:30:44 PM PDT 24
Peak memory 225504 kb
Host smart-01fb442d-6d59-429a-b0c7-25fb746fce96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622935977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2622935977
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.4146337989
Short name T338
Test name
Test status
Simulation time 806548314 ps
CPU time 19.37 seconds
Started Jul 14 05:30:35 PM PDT 24
Finished Jul 14 05:30:55 PM PDT 24
Peak memory 216884 kb
Host smart-c7a67513-1e81-4363-ae42-7064f1b3e7ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146337989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.4146337989
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3775153422
Short name T239
Test name
Test status
Simulation time 193083947 ps
CPU time 1.8 seconds
Started Jul 14 05:30:30 PM PDT 24
Finished Jul 14 05:30:33 PM PDT 24
Peak memory 217700 kb
Host smart-26b14345-74dc-45a3-a0d4-8d515edb21c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775153422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3775153422
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1380429908
Short name T410
Test name
Test status
Simulation time 569573395 ps
CPU time 23.11 seconds
Started Jul 14 05:30:34 PM PDT 24
Finished Jul 14 05:30:58 PM PDT 24
Peak memory 225460 kb
Host smart-fa309b2a-f0f4-45f7-9c88-2de72aec8d3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380429908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1380429908
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3448840059
Short name T251
Test name
Test status
Simulation time 893223692 ps
CPU time 7.63 seconds
Started Jul 14 05:30:34 PM PDT 24
Finished Jul 14 05:30:42 PM PDT 24
Peak memory 225420 kb
Host smart-6ebcee39-9d8b-43c1-a890-25827d6d924c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448840059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3448840059
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.4029595712
Short name T167
Test name
Test status
Simulation time 524858592 ps
CPU time 17.84 seconds
Started Jul 14 05:30:32 PM PDT 24
Finished Jul 14 05:30:50 PM PDT 24
Peak memory 225432 kb
Host smart-8f8c2863-8f24-4758-8c69-75e6b419417d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029595712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
4029595712
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3582933083
Short name T762
Test name
Test status
Simulation time 335068173 ps
CPU time 10.87 seconds
Started Jul 14 05:30:35 PM PDT 24
Finished Jul 14 05:30:47 PM PDT 24
Peak memory 224352 kb
Host smart-7900e868-79bb-4d32-b371-49213993d9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582933083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3582933083
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1169563588
Short name T248
Test name
Test status
Simulation time 306507168 ps
CPU time 1.63 seconds
Started Jul 14 05:30:28 PM PDT 24
Finished Jul 14 05:30:32 PM PDT 24
Peak memory 213232 kb
Host smart-a8384878-3079-4001-b3b7-1c357b07b905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169563588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1169563588
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2435975387
Short name T580
Test name
Test status
Simulation time 230248381 ps
CPU time 20.5 seconds
Started Jul 14 05:30:28 PM PDT 24
Finished Jul 14 05:30:51 PM PDT 24
Peak memory 250384 kb
Host smart-be6dd9ae-84ce-4f72-be94-1daebfd979c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435975387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2435975387
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3190692917
Short name T438
Test name
Test status
Simulation time 308054241 ps
CPU time 4.1 seconds
Started Jul 14 05:30:28 PM PDT 24
Finished Jul 14 05:30:34 PM PDT 24
Peak memory 225820 kb
Host smart-e1f70fb3-e672-40e2-87d5-7ba0892f95d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190692917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3190692917
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3591439280
Short name T557
Test name
Test status
Simulation time 2461718394 ps
CPU time 70.73 seconds
Started Jul 14 05:30:34 PM PDT 24
Finished Jul 14 05:31:46 PM PDT 24
Peak memory 266888 kb
Host smart-68fb6341-1a86-4429-87b7-60e22fdca2cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591439280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3591439280
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1529055700
Short name T530
Test name
Test status
Simulation time 18951789 ps
CPU time 0.88 seconds
Started Jul 14 05:30:29 PM PDT 24
Finished Jul 14 05:30:32 PM PDT 24
Peak memory 208368 kb
Host smart-47ba3d98-0d1d-4571-bc40-7f6fe10ef612
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529055700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1529055700
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2235178389
Short name T327
Test name
Test status
Simulation time 22420856 ps
CPU time 1.06 seconds
Started Jul 14 05:27:48 PM PDT 24
Finished Jul 14 05:27:49 PM PDT 24
Peak memory 208460 kb
Host smart-5e547b8d-67f4-416e-a16e-f6081c1a3d11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235178389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2235178389
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.477472647
Short name T204
Test name
Test status
Simulation time 33172914 ps
CPU time 0.98 seconds
Started Jul 14 05:27:48 PM PDT 24
Finished Jul 14 05:27:49 PM PDT 24
Peak memory 208240 kb
Host smart-c0fcdac4-2c35-4eb0-864a-4e24132a0372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477472647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.477472647
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.487956943
Short name T41
Test name
Test status
Simulation time 740642971 ps
CPU time 13.9 seconds
Started Jul 14 05:27:42 PM PDT 24
Finished Jul 14 05:27:57 PM PDT 24
Peak memory 225496 kb
Host smart-1725e850-8591-48a7-8317-e2aff9efa66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487956943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.487956943
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.464391814
Short name T398
Test name
Test status
Simulation time 895585287 ps
CPU time 2.65 seconds
Started Jul 14 05:27:52 PM PDT 24
Finished Jul 14 05:27:55 PM PDT 24
Peak memory 217124 kb
Host smart-b9839642-cf06-495a-8f5b-5c9f82f86305
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464391814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.464391814
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3247807796
Short name T786
Test name
Test status
Simulation time 6463338874 ps
CPU time 49.99 seconds
Started Jul 14 05:27:48 PM PDT 24
Finished Jul 14 05:28:39 PM PDT 24
Peak memory 218340 kb
Host smart-ed34cadb-192d-40b4-99d1-c2c1a8997c56
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247807796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3247807796
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.4204405353
Short name T90
Test name
Test status
Simulation time 161129922 ps
CPU time 4.71 seconds
Started Jul 14 05:27:51 PM PDT 24
Finished Jul 14 05:27:56 PM PDT 24
Peak memory 217172 kb
Host smart-f11542bd-0a1c-4cd9-803b-b4570ae7b25a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204405353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.4
204405353
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.666153520
Short name T790
Test name
Test status
Simulation time 1266137351 ps
CPU time 10.2 seconds
Started Jul 14 05:27:48 PM PDT 24
Finished Jul 14 05:27:59 PM PDT 24
Peak memory 217612 kb
Host smart-918e027c-6475-4d5e-8db3-938cab6b3cf6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666153520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.666153520
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.461604573
Short name T546
Test name
Test status
Simulation time 1470066038 ps
CPU time 22.76 seconds
Started Jul 14 05:27:51 PM PDT 24
Finished Jul 14 05:28:14 PM PDT 24
Peak memory 217064 kb
Host smart-ab1175a9-d961-4d41-a737-24355368b66f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461604573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.461604573
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2450760454
Short name T649
Test name
Test status
Simulation time 915531091 ps
CPU time 7.18 seconds
Started Jul 14 05:27:44 PM PDT 24
Finished Jul 14 05:27:53 PM PDT 24
Peak memory 217044 kb
Host smart-8030ec84-1576-40a1-8017-49d60eb5b2df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450760454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2450760454
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1092464245
Short name T214
Test name
Test status
Simulation time 2837967437 ps
CPU time 62.83 seconds
Started Jul 14 05:27:48 PM PDT 24
Finished Jul 14 05:28:51 PM PDT 24
Peak memory 250320 kb
Host smart-0713798b-0157-4318-a12b-62c342f800cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092464245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1092464245
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1546407852
Short name T764
Test name
Test status
Simulation time 647050511 ps
CPU time 11.54 seconds
Started Jul 14 05:27:45 PM PDT 24
Finished Jul 14 05:27:57 PM PDT 24
Peak memory 219768 kb
Host smart-270c236f-9c0b-43f0-b22e-8dc4176aea59
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546407852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1546407852
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1134092080
Short name T760
Test name
Test status
Simulation time 44964685 ps
CPU time 2.26 seconds
Started Jul 14 05:27:42 PM PDT 24
Finished Jul 14 05:27:44 PM PDT 24
Peak memory 221652 kb
Host smart-55e9d611-9458-44f4-9780-5542c0302cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134092080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1134092080
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3578112520
Short name T560
Test name
Test status
Simulation time 1378766312 ps
CPU time 20.5 seconds
Started Jul 14 05:27:43 PM PDT 24
Finished Jul 14 05:28:05 PM PDT 24
Peak memory 217044 kb
Host smart-bd26a6ba-1f14-4188-9dea-51acc4b3d591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578112520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3578112520
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3038942821
Short name T85
Test name
Test status
Simulation time 824587357 ps
CPU time 37.11 seconds
Started Jul 14 05:27:47 PM PDT 24
Finished Jul 14 05:28:25 PM PDT 24
Peak memory 269756 kb
Host smart-4eff0bef-d80a-4cbc-a031-e37c0766d064
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038942821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3038942821
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.20664385
Short name T590
Test name
Test status
Simulation time 350462655 ps
CPU time 13.92 seconds
Started Jul 14 05:27:49 PM PDT 24
Finished Jul 14 05:28:04 PM PDT 24
Peak memory 225432 kb
Host smart-a90676b2-ea19-444f-a421-bdfc6fa94ef3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20664385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dige
st.20664385
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1743748045
Short name T825
Test name
Test status
Simulation time 1038481790 ps
CPU time 7.46 seconds
Started Jul 14 05:27:44 PM PDT 24
Finished Jul 14 05:27:53 PM PDT 24
Peak memory 225392 kb
Host smart-78db6490-9a93-4c29-9a68-88628ba3bb20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743748045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
743748045
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2916988881
Short name T51
Test name
Test status
Simulation time 295753611 ps
CPU time 9.08 seconds
Started Jul 14 05:27:43 PM PDT 24
Finished Jul 14 05:27:53 PM PDT 24
Peak memory 224988 kb
Host smart-d2839525-102e-4ea7-8365-04dde5fe60a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916988881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2916988881
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3292242819
Short name T343
Test name
Test status
Simulation time 50207500 ps
CPU time 1.19 seconds
Started Jul 14 05:27:45 PM PDT 24
Finished Jul 14 05:27:47 PM PDT 24
Peak memory 213000 kb
Host smart-fa1d7d72-868c-4106-827d-c920292fe930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292242819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3292242819
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3472706443
Short name T468
Test name
Test status
Simulation time 1153904077 ps
CPU time 29.26 seconds
Started Jul 14 05:27:45 PM PDT 24
Finished Jul 14 05:28:15 PM PDT 24
Peak memory 250396 kb
Host smart-25651d3f-b861-4f97-96e0-bd7f56d094f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472706443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3472706443
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3444028679
Short name T664
Test name
Test status
Simulation time 299676752 ps
CPU time 7.46 seconds
Started Jul 14 05:27:53 PM PDT 24
Finished Jul 14 05:28:01 PM PDT 24
Peak memory 246148 kb
Host smart-e79b4e86-b0db-4bfd-a136-57b843f860e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444028679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3444028679
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3540229297
Short name T61
Test name
Test status
Simulation time 20605473508 ps
CPU time 180.99 seconds
Started Jul 14 05:27:48 PM PDT 24
Finished Jul 14 05:30:50 PM PDT 24
Peak memory 266924 kb
Host smart-070e27a6-ae77-4419-88a4-4d940a7fc9ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540229297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3540229297
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1772561333
Short name T688
Test name
Test status
Simulation time 13261955 ps
CPU time 1.08 seconds
Started Jul 14 05:27:46 PM PDT 24
Finished Jul 14 05:27:47 PM PDT 24
Peak memory 211248 kb
Host smart-32b7a43c-05fc-414d-bf43-ef5a68ba6765
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772561333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1772561333
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.2196858698
Short name T97
Test name
Test status
Simulation time 41511973 ps
CPU time 0.81 seconds
Started Jul 14 05:30:30 PM PDT 24
Finished Jul 14 05:30:32 PM PDT 24
Peak memory 208532 kb
Host smart-ad42affb-471f-42b0-8cc2-f5fa72a8e03e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196858698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2196858698
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.4185363014
Short name T787
Test name
Test status
Simulation time 1308687719 ps
CPU time 13.71 seconds
Started Jul 14 05:30:37 PM PDT 24
Finished Jul 14 05:30:52 PM PDT 24
Peak memory 217712 kb
Host smart-28f2a605-9815-46e3-b0aa-ea39405ab0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185363014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.4185363014
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3393176612
Short name T637
Test name
Test status
Simulation time 138925761 ps
CPU time 1.71 seconds
Started Jul 14 05:30:34 PM PDT 24
Finished Jul 14 05:30:36 PM PDT 24
Peak memory 217088 kb
Host smart-6f4fc567-5a99-499f-adf5-5fededa64968
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393176612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3393176612
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1110521524
Short name T833
Test name
Test status
Simulation time 17576703 ps
CPU time 1.6 seconds
Started Jul 14 05:30:35 PM PDT 24
Finished Jul 14 05:30:37 PM PDT 24
Peak memory 217684 kb
Host smart-8b2066a6-195a-46d1-b64e-bc72be43302a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110521524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1110521524
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.3244210307
Short name T755
Test name
Test status
Simulation time 339422893 ps
CPU time 13.48 seconds
Started Jul 14 05:30:33 PM PDT 24
Finished Jul 14 05:30:47 PM PDT 24
Peak memory 225428 kb
Host smart-5ed373c8-59a1-4d34-b95c-226fc8ae180f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244210307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3244210307
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.885103937
Short name T716
Test name
Test status
Simulation time 851967609 ps
CPU time 8.12 seconds
Started Jul 14 05:30:33 PM PDT 24
Finished Jul 14 05:30:42 PM PDT 24
Peak memory 225520 kb
Host smart-6be0f1b5-cb6d-4891-91d2-77f90408ba94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885103937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_di
gest.885103937
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1375698747
Short name T673
Test name
Test status
Simulation time 440830713 ps
CPU time 11.06 seconds
Started Jul 14 05:30:34 PM PDT 24
Finished Jul 14 05:30:45 PM PDT 24
Peak memory 217620 kb
Host smart-d15d9a81-e52b-4076-a2a0-e0ac215cbc8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375698747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1375698747
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1628722109
Short name T356
Test name
Test status
Simulation time 401150247 ps
CPU time 6.68 seconds
Started Jul 14 05:30:33 PM PDT 24
Finished Jul 14 05:30:41 PM PDT 24
Peak memory 217768 kb
Host smart-ca5b25c7-d693-4103-a96f-df031bd10638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628722109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1628722109
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1676093301
Short name T68
Test name
Test status
Simulation time 40184014 ps
CPU time 2.54 seconds
Started Jul 14 05:30:35 PM PDT 24
Finished Jul 14 05:30:39 PM PDT 24
Peak memory 213860 kb
Host smart-e4e28136-4ab1-4d29-80c4-6bb3ebb4c713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676093301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1676093301
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.4111736627
Short name T806
Test name
Test status
Simulation time 778345347 ps
CPU time 18.85 seconds
Started Jul 14 05:30:33 PM PDT 24
Finished Jul 14 05:30:53 PM PDT 24
Peak memory 245164 kb
Host smart-bccaa522-4be1-4213-9e36-0e95f71a22c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111736627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.4111736627
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2521824651
Short name T573
Test name
Test status
Simulation time 381116198 ps
CPU time 3.23 seconds
Started Jul 14 05:30:36 PM PDT 24
Finished Jul 14 05:30:40 PM PDT 24
Peak memory 225872 kb
Host smart-cd5c64c4-605e-4d84-b864-3f1d9c5c2b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521824651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2521824651
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3978407431
Short name T448
Test name
Test status
Simulation time 3429214282 ps
CPU time 144.22 seconds
Started Jul 14 05:30:35 PM PDT 24
Finished Jul 14 05:33:00 PM PDT 24
Peak memory 275964 kb
Host smart-9f3ddcd7-be2e-40c9-963e-2f6dbac36e9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978407431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3978407431
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.3168506283
Short name T597
Test name
Test status
Simulation time 283268649201 ps
CPU time 376.91 seconds
Started Jul 14 05:30:36 PM PDT 24
Finished Jul 14 05:36:53 PM PDT 24
Peak memory 432572 kb
Host smart-6fe0c37f-8a1a-4346-bed5-5eb7d17387da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3168506283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.3168506283
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1307661981
Short name T796
Test name
Test status
Simulation time 14246455 ps
CPU time 0.75 seconds
Started Jul 14 05:30:36 PM PDT 24
Finished Jul 14 05:30:37 PM PDT 24
Peak memory 207612 kb
Host smart-76262994-3a99-43a6-953f-e77387996e23
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307661981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1307661981
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3430882662
Short name T746
Test name
Test status
Simulation time 18801096 ps
CPU time 1.15 seconds
Started Jul 14 05:30:39 PM PDT 24
Finished Jul 14 05:30:41 PM PDT 24
Peak memory 208464 kb
Host smart-4478bb3d-89ee-4134-9518-e3af83703c99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430882662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3430882662
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.481343519
Short name T439
Test name
Test status
Simulation time 525988659 ps
CPU time 10.59 seconds
Started Jul 14 05:30:32 PM PDT 24
Finished Jul 14 05:30:43 PM PDT 24
Peak memory 217716 kb
Host smart-3cc2bda3-4764-43cf-8bc2-9f4fec5a0bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481343519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.481343519
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1709676477
Short name T384
Test name
Test status
Simulation time 14985742308 ps
CPU time 22.06 seconds
Started Jul 14 05:30:39 PM PDT 24
Finished Jul 14 05:31:02 PM PDT 24
Peak memory 217192 kb
Host smart-b6d23f63-7113-4bca-9ed7-40f45b3922b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709676477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1709676477
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.828434673
Short name T564
Test name
Test status
Simulation time 125169138 ps
CPU time 2.33 seconds
Started Jul 14 05:30:36 PM PDT 24
Finished Jul 14 05:30:39 PM PDT 24
Peak memory 221684 kb
Host smart-332e6b67-e54e-4f57-8591-9c0f3e40b2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828434673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.828434673
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.314082968
Short name T349
Test name
Test status
Simulation time 2155940254 ps
CPU time 17.09 seconds
Started Jul 14 05:30:38 PM PDT 24
Finished Jul 14 05:30:56 PM PDT 24
Peak memory 225560 kb
Host smart-40a16c32-b5f0-4f73-83ad-1cee00684eea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314082968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.314082968
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2075094903
Short name T527
Test name
Test status
Simulation time 675383093 ps
CPU time 8.81 seconds
Started Jul 14 05:30:36 PM PDT 24
Finished Jul 14 05:30:45 PM PDT 24
Peak memory 225396 kb
Host smart-22787b4e-8c5f-4386-b2b6-76ef98114315
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075094903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2075094903
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3999380831
Short name T466
Test name
Test status
Simulation time 292416466 ps
CPU time 8.69 seconds
Started Jul 14 05:30:40 PM PDT 24
Finished Jul 14 05:30:49 PM PDT 24
Peak memory 217528 kb
Host smart-14b72ffd-0f64-4ca3-bf2a-0ba025fad602
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999380831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3999380831
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3802404198
Short name T336
Test name
Test status
Simulation time 344042004 ps
CPU time 13.28 seconds
Started Jul 14 05:30:39 PM PDT 24
Finished Jul 14 05:30:54 PM PDT 24
Peak memory 224792 kb
Host smart-a12debeb-d710-4ce4-8f59-307cd0ccc05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802404198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3802404198
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2872481788
Short name T322
Test name
Test status
Simulation time 979973338 ps
CPU time 4.55 seconds
Started Jul 14 05:30:36 PM PDT 24
Finished Jul 14 05:30:42 PM PDT 24
Peak memory 217244 kb
Host smart-cdb947ca-71c5-40c9-8cbc-0aa3f18d898e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872481788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2872481788
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.3342514111
Short name T742
Test name
Test status
Simulation time 185691668 ps
CPU time 16.25 seconds
Started Jul 14 05:30:34 PM PDT 24
Finished Jul 14 05:30:52 PM PDT 24
Peak memory 250388 kb
Host smart-d4b5c969-2e47-4fd7-a492-40339e0aa7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342514111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3342514111
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.754636031
Short name T648
Test name
Test status
Simulation time 86734480 ps
CPU time 3.66 seconds
Started Jul 14 05:30:31 PM PDT 24
Finished Jul 14 05:30:35 PM PDT 24
Peak memory 222296 kb
Host smart-5722903a-f7b4-4e66-bd41-f82770c0d06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754636031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.754636031
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2111350667
Short name T422
Test name
Test status
Simulation time 7604646202 ps
CPU time 59.44 seconds
Started Jul 14 05:30:37 PM PDT 24
Finished Jul 14 05:31:37 PM PDT 24
Peak memory 272664 kb
Host smart-573e73b5-b4a4-4d0f-ad5e-5b2d7543d983
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111350667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2111350667
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2813450800
Short name T144
Test name
Test status
Simulation time 32430171942 ps
CPU time 6508.11 seconds
Started Jul 14 05:30:37 PM PDT 24
Finished Jul 14 07:19:07 PM PDT 24
Peak memory 676708 kb
Host smart-252ba73d-5d21-48c2-9e96-89a48c6fdce5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2813450800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.2813450800
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.4056934638
Short name T541
Test name
Test status
Simulation time 36088267 ps
CPU time 0.81 seconds
Started Jul 14 05:30:34 PM PDT 24
Finished Jul 14 05:30:36 PM PDT 24
Peak memory 208108 kb
Host smart-d8261b60-c35c-40df-8fdf-2597d2d757a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056934638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.4056934638
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.921116840
Short name T552
Test name
Test status
Simulation time 56009585 ps
CPU time 1.29 seconds
Started Jul 14 05:30:39 PM PDT 24
Finished Jul 14 05:30:41 PM PDT 24
Peak memory 208460 kb
Host smart-7e00dfde-48e2-4646-aada-493bd62b7092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921116840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.921116840
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1256798220
Short name T810
Test name
Test status
Simulation time 1714129628 ps
CPU time 8.44 seconds
Started Jul 14 05:30:39 PM PDT 24
Finished Jul 14 05:30:49 PM PDT 24
Peak memory 225508 kb
Host smart-5ae272e4-abc6-44d7-aad9-9ccb09629638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256798220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1256798220
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1770361288
Short name T823
Test name
Test status
Simulation time 385602143 ps
CPU time 9.77 seconds
Started Jul 14 05:30:38 PM PDT 24
Finished Jul 14 05:30:48 PM PDT 24
Peak memory 217132 kb
Host smart-619daa0e-586a-46f2-8bea-f0c7315b8029
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770361288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1770361288
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2835701328
Short name T780
Test name
Test status
Simulation time 96802098 ps
CPU time 3.28 seconds
Started Jul 14 05:30:37 PM PDT 24
Finished Jul 14 05:30:42 PM PDT 24
Peak memory 217696 kb
Host smart-9e2ca8f5-3324-4e72-98fd-d9288b43d232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835701328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2835701328
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3833126654
Short name T302
Test name
Test status
Simulation time 339452243 ps
CPU time 10.65 seconds
Started Jul 14 05:30:38 PM PDT 24
Finished Jul 14 05:30:49 PM PDT 24
Peak memory 217652 kb
Host smart-4cd5b856-8998-43ca-9c77-9283558e9284
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833126654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3833126654
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3672341797
Short name T279
Test name
Test status
Simulation time 246038939 ps
CPU time 9.5 seconds
Started Jul 14 05:30:38 PM PDT 24
Finished Jul 14 05:30:49 PM PDT 24
Peak memory 225440 kb
Host smart-aa039998-1516-4779-b053-a9999c2d7966
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672341797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3672341797
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2323165336
Short name T675
Test name
Test status
Simulation time 1177559733 ps
CPU time 8.3 seconds
Started Jul 14 05:30:39 PM PDT 24
Finished Jul 14 05:30:49 PM PDT 24
Peak memory 224684 kb
Host smart-0fdca6b5-6062-4e7a-b75b-5fcf5963b9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323165336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2323165336
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2393101890
Short name T72
Test name
Test status
Simulation time 767557411 ps
CPU time 4.22 seconds
Started Jul 14 05:30:36 PM PDT 24
Finished Jul 14 05:30:41 PM PDT 24
Peak memory 221836 kb
Host smart-c73249ce-b5fe-43d7-8fb7-e6eb9f74de90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393101890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2393101890
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3406888233
Short name T776
Test name
Test status
Simulation time 553888080 ps
CPU time 13.23 seconds
Started Jul 14 05:30:37 PM PDT 24
Finished Jul 14 05:30:51 PM PDT 24
Peak memory 250456 kb
Host smart-bb0601a7-94bc-44e5-8d53-74ce611c4d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406888233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3406888233
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.772144049
Short name T717
Test name
Test status
Simulation time 69283493 ps
CPU time 7.37 seconds
Started Jul 14 05:30:40 PM PDT 24
Finished Jul 14 05:30:48 PM PDT 24
Peak memory 250500 kb
Host smart-48fbe145-685a-46fb-b5f0-d1f3d9a28299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772144049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.772144049
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1926110349
Short name T830
Test name
Test status
Simulation time 76463224577 ps
CPU time 137.38 seconds
Started Jul 14 05:30:38 PM PDT 24
Finished Jul 14 05:32:57 PM PDT 24
Peak memory 250496 kb
Host smart-a1857112-ef4b-4e97-9f6f-464f5dc51be8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926110349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1926110349
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.4100312315
Short name T35
Test name
Test status
Simulation time 48481415 ps
CPU time 1.01 seconds
Started Jul 14 05:30:38 PM PDT 24
Finished Jul 14 05:30:40 PM PDT 24
Peak memory 211256 kb
Host smart-c620dd14-0ada-44ce-b752-6051cb0305f4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100312315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.4100312315
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.48640215
Short name T800
Test name
Test status
Simulation time 75011154 ps
CPU time 0.91 seconds
Started Jul 14 05:30:46 PM PDT 24
Finished Jul 14 05:30:47 PM PDT 24
Peak memory 208424 kb
Host smart-90cf2075-6d83-45a7-a26e-fe08f7b5ccf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48640215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.48640215
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2416857096
Short name T326
Test name
Test status
Simulation time 446003193 ps
CPU time 10.67 seconds
Started Jul 14 05:30:42 PM PDT 24
Finished Jul 14 05:30:54 PM PDT 24
Peak memory 217624 kb
Host smart-397a14ee-e64f-4b2d-998a-bb08957ff9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416857096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2416857096
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.724725065
Short name T751
Test name
Test status
Simulation time 3046779965 ps
CPU time 8.04 seconds
Started Jul 14 05:30:46 PM PDT 24
Finished Jul 14 05:30:55 PM PDT 24
Peak memory 217108 kb
Host smart-a521a206-3ae0-4845-84db-d38bf3478aea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724725065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.724725065
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1747902195
Short name T738
Test name
Test status
Simulation time 124684836 ps
CPU time 3.37 seconds
Started Jul 14 05:30:43 PM PDT 24
Finished Jul 14 05:30:48 PM PDT 24
Peak memory 222264 kb
Host smart-90cbd97c-0c17-49ea-87ca-0fe07e6058dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747902195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1747902195
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.572585415
Short name T506
Test name
Test status
Simulation time 1410734414 ps
CPU time 9.87 seconds
Started Jul 14 05:30:44 PM PDT 24
Finished Jul 14 05:30:54 PM PDT 24
Peak memory 218328 kb
Host smart-7149d1e3-1d0e-4dca-bb3b-a32b99b7e933
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572585415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.572585415
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2574141319
Short name T156
Test name
Test status
Simulation time 1444099868 ps
CPU time 9.33 seconds
Started Jul 14 05:30:48 PM PDT 24
Finished Jul 14 05:30:58 PM PDT 24
Peak memory 225436 kb
Host smart-3e486c6f-8926-4ffa-b563-270993504389
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574141319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2574141319
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.465449268
Short name T355
Test name
Test status
Simulation time 312840091 ps
CPU time 11.77 seconds
Started Jul 14 05:30:47 PM PDT 24
Finished Jul 14 05:31:00 PM PDT 24
Peak memory 224852 kb
Host smart-9db8ee24-f704-48bb-a4b5-eb2a8cc5386e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465449268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.465449268
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1136862616
Short name T461
Test name
Test status
Simulation time 1004406248 ps
CPU time 7.24 seconds
Started Jul 14 05:30:47 PM PDT 24
Finished Jul 14 05:30:56 PM PDT 24
Peak memory 225432 kb
Host smart-ae72d50b-c63f-4255-b8b0-03219e7fd608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136862616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1136862616
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2676834036
Short name T63
Test name
Test status
Simulation time 159376962 ps
CPU time 1.63 seconds
Started Jul 14 05:30:39 PM PDT 24
Finished Jul 14 05:30:42 PM PDT 24
Peak memory 217056 kb
Host smart-050326b3-203a-4e33-bf80-c2dbb8a1d393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676834036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2676834036
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.580434435
Short name T588
Test name
Test status
Simulation time 191638342 ps
CPU time 20.64 seconds
Started Jul 14 05:30:48 PM PDT 24
Finished Jul 14 05:31:09 PM PDT 24
Peak memory 250468 kb
Host smart-58f6be25-66c7-43cf-aa01-89172e838f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580434435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.580434435
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2641334459
Short name T584
Test name
Test status
Simulation time 62362207 ps
CPU time 6.98 seconds
Started Jul 14 05:30:49 PM PDT 24
Finished Jul 14 05:30:58 PM PDT 24
Peak memory 250452 kb
Host smart-f7381cf8-3a47-4ae6-ba9a-34b0310c3866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641334459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2641334459
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.4262947103
Short name T100
Test name
Test status
Simulation time 1488381050 ps
CPU time 53.42 seconds
Started Jul 14 05:30:45 PM PDT 24
Finished Jul 14 05:31:39 PM PDT 24
Peak memory 250472 kb
Host smart-21a90f28-cd12-4ee3-afc1-68e6d64db97c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262947103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.4262947103
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2822328263
Short name T26
Test name
Test status
Simulation time 15073615 ps
CPU time 1 seconds
Started Jul 14 05:30:45 PM PDT 24
Finished Jul 14 05:30:47 PM PDT 24
Peak memory 208320 kb
Host smart-1c9cc9fc-783a-45fe-a71a-f9565115363e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822328263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2822328263
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.114229849
Short name T610
Test name
Test status
Simulation time 33149688 ps
CPU time 0.98 seconds
Started Jul 14 05:30:47 PM PDT 24
Finished Jul 14 05:30:49 PM PDT 24
Peak memory 208344 kb
Host smart-17f760ce-5f7e-4645-8096-3c7a8ad03750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114229849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.114229849
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1708549715
Short name T601
Test name
Test status
Simulation time 1173657197 ps
CPU time 11.91 seconds
Started Jul 14 05:30:43 PM PDT 24
Finished Jul 14 05:30:55 PM PDT 24
Peak memory 217656 kb
Host smart-98e98cb8-82db-484a-a637-19349f8cad2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708549715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1708549715
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.887591538
Short name T3
Test name
Test status
Simulation time 1016367641 ps
CPU time 7.81 seconds
Started Jul 14 05:30:49 PM PDT 24
Finished Jul 14 05:30:58 PM PDT 24
Peak memory 217136 kb
Host smart-1c27f2cf-4b1a-4387-a4ee-e8b3e5bd0de7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887591538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.887591538
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1825274902
Short name T661
Test name
Test status
Simulation time 166450816 ps
CPU time 3.96 seconds
Started Jul 14 05:30:49 PM PDT 24
Finished Jul 14 05:30:53 PM PDT 24
Peak memory 222128 kb
Host smart-1a90c23f-18a7-4970-925c-98313f48532e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825274902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1825274902
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.4114208786
Short name T821
Test name
Test status
Simulation time 1465160580 ps
CPU time 10.19 seconds
Started Jul 14 05:30:51 PM PDT 24
Finished Jul 14 05:31:03 PM PDT 24
Peak memory 225460 kb
Host smart-413ea5c3-2323-4c69-af66-afb7f8aaa9b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114208786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.4114208786
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2880450759
Short name T781
Test name
Test status
Simulation time 975948518 ps
CPU time 7.35 seconds
Started Jul 14 05:30:50 PM PDT 24
Finished Jul 14 05:30:59 PM PDT 24
Peak memory 217644 kb
Host smart-3fb67d99-d385-42ea-bb16-9f31bea77e7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880450759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2880450759
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2205922426
Short name T247
Test name
Test status
Simulation time 365028391 ps
CPU time 13.68 seconds
Started Jul 14 05:30:44 PM PDT 24
Finished Jul 14 05:30:58 PM PDT 24
Peak memory 217736 kb
Host smart-d496ec00-4c06-494e-bb43-e719e90e1fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205922426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2205922426
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3830050052
Short name T430
Test name
Test status
Simulation time 82640770 ps
CPU time 2.87 seconds
Started Jul 14 05:30:44 PM PDT 24
Finished Jul 14 05:30:48 PM PDT 24
Peak memory 217136 kb
Host smart-86dc14c7-2068-4218-8487-f5b4371d8c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830050052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3830050052
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3969993751
Short name T281
Test name
Test status
Simulation time 227938620 ps
CPU time 29.61 seconds
Started Jul 14 05:30:48 PM PDT 24
Finished Jul 14 05:31:18 PM PDT 24
Peak memory 245688 kb
Host smart-ba3df30b-4ffc-4271-8050-a0c970e2bc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969993751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3969993751
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1134678710
Short name T840
Test name
Test status
Simulation time 82783710 ps
CPU time 7.64 seconds
Started Jul 14 05:30:47 PM PDT 24
Finished Jul 14 05:30:55 PM PDT 24
Peak memory 250436 kb
Host smart-fe6b1230-3c58-4b07-bcec-7f6ac3dbbb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134678710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1134678710
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.1295401339
Short name T769
Test name
Test status
Simulation time 10382272683 ps
CPU time 414.26 seconds
Started Jul 14 05:30:48 PM PDT 24
Finished Jul 14 05:37:43 PM PDT 24
Peak memory 283280 kb
Host smart-7b10cb43-fd93-4c0c-80bc-dbf9549431da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295401339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.1295401339
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3708268056
Short name T252
Test name
Test status
Simulation time 54139328 ps
CPU time 0.83 seconds
Started Jul 14 05:30:47 PM PDT 24
Finished Jul 14 05:30:48 PM PDT 24
Peak memory 211244 kb
Host smart-f9b0365f-5df3-4762-9852-9b65de2407ad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708268056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3708268056
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1636344376
Short name T558
Test name
Test status
Simulation time 40017372 ps
CPU time 0.9 seconds
Started Jul 14 05:30:51 PM PDT 24
Finished Jul 14 05:30:53 PM PDT 24
Peak memory 208336 kb
Host smart-78166ee1-2a60-4902-8ce0-2fb3f89de529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636344376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1636344376
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2598311444
Short name T454
Test name
Test status
Simulation time 453734990 ps
CPU time 19.3 seconds
Started Jul 14 05:30:49 PM PDT 24
Finished Jul 14 05:31:09 PM PDT 24
Peak memory 217640 kb
Host smart-bfd29483-dc29-4628-a6da-d336c1fc049c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598311444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2598311444
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.745415510
Short name T382
Test name
Test status
Simulation time 6206524639 ps
CPU time 4.61 seconds
Started Jul 14 05:30:51 PM PDT 24
Finished Jul 14 05:30:57 PM PDT 24
Peak memory 217160 kb
Host smart-fcfd3260-7558-414e-bdba-d0bd470b0827
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745415510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.745415510
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1520780808
Short name T635
Test name
Test status
Simulation time 75900030 ps
CPU time 2.72 seconds
Started Jul 14 05:30:50 PM PDT 24
Finished Jul 14 05:30:54 PM PDT 24
Peak memory 217700 kb
Host smart-758a4a80-65d3-4ac2-8572-bac34bb848bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520780808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1520780808
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3604277624
Short name T413
Test name
Test status
Simulation time 1241926162 ps
CPU time 10.89 seconds
Started Jul 14 05:30:54 PM PDT 24
Finished Jul 14 05:31:06 PM PDT 24
Peak memory 225320 kb
Host smart-fd62ef1a-81aa-4992-82a4-a9becbe540ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604277624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3604277624
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2476331990
Short name T414
Test name
Test status
Simulation time 267602504 ps
CPU time 8.21 seconds
Started Jul 14 05:30:50 PM PDT 24
Finished Jul 14 05:31:00 PM PDT 24
Peak memory 225448 kb
Host smart-2864c6a5-686e-4ffe-9a4d-5624b8c8b85e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476331990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2476331990
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1752472142
Short name T857
Test name
Test status
Simulation time 1424598725 ps
CPU time 8.95 seconds
Started Jul 14 05:30:53 PM PDT 24
Finished Jul 14 05:31:02 PM PDT 24
Peak memory 217628 kb
Host smart-1ac10d72-cd98-43d1-a3ea-1c1a4e4e529c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752472142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1752472142
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.228433070
Short name T47
Test name
Test status
Simulation time 341493722 ps
CPU time 9.49 seconds
Started Jul 14 05:30:51 PM PDT 24
Finished Jul 14 05:31:02 PM PDT 24
Peak memory 225444 kb
Host smart-f5836418-a5d3-49bd-9563-4d5db9e9f503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228433070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.228433070
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1782737459
Short name T543
Test name
Test status
Simulation time 77527241 ps
CPU time 1.9 seconds
Started Jul 14 05:30:49 PM PDT 24
Finished Jul 14 05:30:52 PM PDT 24
Peak memory 222616 kb
Host smart-da5e7e43-1758-41d1-8d2a-2186fdb1703d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782737459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1782737459
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1185571188
Short name T483
Test name
Test status
Simulation time 1178015136 ps
CPU time 26.01 seconds
Started Jul 14 05:30:51 PM PDT 24
Finished Jul 14 05:31:19 PM PDT 24
Peak memory 244968 kb
Host smart-fa9ad954-4c2a-4cde-bc3c-3503de1a131b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185571188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1185571188
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2781306325
Short name T521
Test name
Test status
Simulation time 600771368 ps
CPU time 8.91 seconds
Started Jul 14 05:30:50 PM PDT 24
Finished Jul 14 05:31:00 PM PDT 24
Peak memory 250456 kb
Host smart-d6d84511-9439-4875-8104-0aadaac511bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781306325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2781306325
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3703559186
Short name T437
Test name
Test status
Simulation time 9241059763 ps
CPU time 200.78 seconds
Started Jul 14 05:30:51 PM PDT 24
Finished Jul 14 05:34:13 PM PDT 24
Peak memory 266856 kb
Host smart-9ba70b3a-6efc-47a5-ab32-30da3da287aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703559186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3703559186
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3137440136
Short name T592
Test name
Test status
Simulation time 17992285 ps
CPU time 0.84 seconds
Started Jul 14 05:30:50 PM PDT 24
Finished Jul 14 05:30:52 PM PDT 24
Peak memory 208060 kb
Host smart-c59203c9-b408-4d9c-9d52-f6339082828a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137440136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.3137440136
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.323252478
Short name T642
Test name
Test status
Simulation time 28344095 ps
CPU time 1.12 seconds
Started Jul 14 05:31:19 PM PDT 24
Finished Jul 14 05:31:21 PM PDT 24
Peak memory 208452 kb
Host smart-83019a96-d5e6-4f58-a492-3c48c34c247e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323252478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.323252478
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1184488037
Short name T222
Test name
Test status
Simulation time 382699409 ps
CPU time 14.99 seconds
Started Jul 14 05:30:50 PM PDT 24
Finished Jul 14 05:31:06 PM PDT 24
Peak memory 217616 kb
Host smart-e174728c-8cf8-4225-9216-457be0cb32b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184488037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1184488037
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1283330658
Short name T712
Test name
Test status
Simulation time 1348222854 ps
CPU time 6.31 seconds
Started Jul 14 05:30:51 PM PDT 24
Finished Jul 14 05:30:59 PM PDT 24
Peak memory 216716 kb
Host smart-ef436cb6-9e76-429b-9ca7-4f6baea2d4c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283330658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1283330658
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1856113372
Short name T232
Test name
Test status
Simulation time 280440134 ps
CPU time 1.52 seconds
Started Jul 14 05:30:50 PM PDT 24
Finished Jul 14 05:30:53 PM PDT 24
Peak memory 217704 kb
Host smart-b9d62794-fb44-461e-9671-6781c4fd06c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856113372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1856113372
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.4073885039
Short name T394
Test name
Test status
Simulation time 1424159310 ps
CPU time 17.32 seconds
Started Jul 14 05:30:50 PM PDT 24
Finished Jul 14 05:31:08 PM PDT 24
Peak memory 219460 kb
Host smart-1ed70098-8fb9-4c22-b63e-e87c794720d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073885039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.4073885039
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2943413176
Short name T53
Test name
Test status
Simulation time 2466417585 ps
CPU time 18.59 seconds
Started Jul 14 05:30:53 PM PDT 24
Finished Jul 14 05:31:12 PM PDT 24
Peak memory 225500 kb
Host smart-86de4102-8838-407e-bcf3-e15887feb4ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943413176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2943413176
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1505449355
Short name T318
Test name
Test status
Simulation time 387197106 ps
CPU time 7.57 seconds
Started Jul 14 05:30:51 PM PDT 24
Finished Jul 14 05:31:00 PM PDT 24
Peak memory 217580 kb
Host smart-574e4815-1586-4488-bff6-28ca827fe416
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505449355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1505449355
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1503595911
Short name T641
Test name
Test status
Simulation time 654589974 ps
CPU time 13.15 seconds
Started Jul 14 05:30:51 PM PDT 24
Finished Jul 14 05:31:05 PM PDT 24
Peak memory 225504 kb
Host smart-c36e8f8b-2db7-4ba9-891f-d70984e4546f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503595911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1503595911
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3336956315
Short name T267
Test name
Test status
Simulation time 42090630 ps
CPU time 3.02 seconds
Started Jul 14 05:30:51 PM PDT 24
Finished Jul 14 05:30:56 PM PDT 24
Peak memory 213760 kb
Host smart-c6c66e5a-deed-4ecc-aa37-7fa1a8af3d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336956315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3336956315
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1994691421
Short name T542
Test name
Test status
Simulation time 195390465 ps
CPU time 26.05 seconds
Started Jul 14 05:30:50 PM PDT 24
Finished Jul 14 05:31:17 PM PDT 24
Peak memory 250452 kb
Host smart-e52b6861-1c64-46a1-aace-ff4a73576ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994691421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1994691421
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2622031673
Short name T234
Test name
Test status
Simulation time 627459479 ps
CPU time 7.71 seconds
Started Jul 14 05:30:50 PM PDT 24
Finished Jul 14 05:30:59 PM PDT 24
Peak memory 250456 kb
Host smart-a00f41b9-3f66-4dea-a046-cbdf8da474e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622031673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2622031673
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.907246706
Short name T614
Test name
Test status
Simulation time 14359346965 ps
CPU time 91.88 seconds
Started Jul 14 05:31:22 PM PDT 24
Finished Jul 14 05:32:56 PM PDT 24
Peak memory 274504 kb
Host smart-7ed6288c-6c68-4297-8676-578eb2532333
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907246706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.907246706
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1602357470
Short name T767
Test name
Test status
Simulation time 11489998 ps
CPU time 0.84 seconds
Started Jul 14 05:30:53 PM PDT 24
Finished Jul 14 05:30:54 PM PDT 24
Peak memory 208268 kb
Host smart-4b1dc220-579d-4373-98fb-c7cc24b0b970
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602357470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1602357470
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3845319108
Short name T638
Test name
Test status
Simulation time 18822719 ps
CPU time 0.85 seconds
Started Jul 14 05:31:20 PM PDT 24
Finished Jul 14 05:31:22 PM PDT 24
Peak memory 208300 kb
Host smart-3efbb5a2-a5b9-4216-8999-b04c3bb08f66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845319108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3845319108
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2126855505
Short name T44
Test name
Test status
Simulation time 1044626807 ps
CPU time 15.91 seconds
Started Jul 14 05:31:19 PM PDT 24
Finished Jul 14 05:31:37 PM PDT 24
Peak memory 225472 kb
Host smart-54fb386c-d9af-4e52-8f98-348cc4534f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126855505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2126855505
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.396899455
Short name T548
Test name
Test status
Simulation time 109635759 ps
CPU time 3.15 seconds
Started Jul 14 05:31:19 PM PDT 24
Finished Jul 14 05:31:23 PM PDT 24
Peak memory 216580 kb
Host smart-73edcc66-e038-4695-bef3-b410cd83323f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396899455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.396899455
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1983065159
Short name T303
Test name
Test status
Simulation time 91699395 ps
CPU time 1.81 seconds
Started Jul 14 05:31:18 PM PDT 24
Finished Jul 14 05:31:21 PM PDT 24
Peak memory 217712 kb
Host smart-c66e0f9c-1569-45c0-befa-a0f00ef12582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983065159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1983065159
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.990138621
Short name T763
Test name
Test status
Simulation time 1399334596 ps
CPU time 12.18 seconds
Started Jul 14 05:31:19 PM PDT 24
Finished Jul 14 05:31:31 PM PDT 24
Peak memory 217916 kb
Host smart-42e509ec-22a2-4658-9f5c-165be016ea74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990138621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.990138621
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.3212665035
Short name T713
Test name
Test status
Simulation time 5760090745 ps
CPU time 10.94 seconds
Started Jul 14 05:31:21 PM PDT 24
Finished Jul 14 05:31:34 PM PDT 24
Peak memory 225508 kb
Host smart-fc49e036-51bf-46aa-a886-5d3dcc24aac2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212665035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.3212665035
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1100512002
Short name T507
Test name
Test status
Simulation time 528431390 ps
CPU time 10.83 seconds
Started Jul 14 05:31:21 PM PDT 24
Finished Jul 14 05:31:34 PM PDT 24
Peak memory 217572 kb
Host smart-2a16d11a-6e1d-449a-8e67-722641fc7ec9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100512002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1100512002
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.2350009791
Short name T514
Test name
Test status
Simulation time 1163959790 ps
CPU time 5.83 seconds
Started Jul 14 05:31:17 PM PDT 24
Finished Jul 14 05:31:23 PM PDT 24
Peak memory 224156 kb
Host smart-2f991713-c589-4f41-be48-fc8e89cb0943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350009791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.2350009791
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2503489313
Short name T62
Test name
Test status
Simulation time 164218993 ps
CPU time 3 seconds
Started Jul 14 05:31:18 PM PDT 24
Finished Jul 14 05:31:21 PM PDT 24
Peak memory 222100 kb
Host smart-6130b828-9c77-46cd-ad0a-804dd3446765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503489313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2503489313
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1340506923
Short name T288
Test name
Test status
Simulation time 530346814 ps
CPU time 28.07 seconds
Started Jul 14 05:31:20 PM PDT 24
Finished Jul 14 05:31:49 PM PDT 24
Peak memory 250420 kb
Host smart-f574d060-f943-438c-938e-d12e145e0cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340506923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1340506923
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.843957421
Short name T523
Test name
Test status
Simulation time 65495803 ps
CPU time 6.85 seconds
Started Jul 14 05:31:20 PM PDT 24
Finished Jul 14 05:31:28 PM PDT 24
Peak memory 246624 kb
Host smart-578668e9-0788-42d2-a44f-e815eaae61a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843957421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.843957421
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3488326401
Short name T847
Test name
Test status
Simulation time 15807639284 ps
CPU time 482.13 seconds
Started Jul 14 05:31:21 PM PDT 24
Finished Jul 14 05:39:25 PM PDT 24
Peak memory 316040 kb
Host smart-6d85fd21-04f8-4e6c-a2da-e3bc24c9897b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488326401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3488326401
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.2748616826
Short name T102
Test name
Test status
Simulation time 43766939060 ps
CPU time 195.56 seconds
Started Jul 14 05:31:20 PM PDT 24
Finished Jul 14 05:34:37 PM PDT 24
Peak memory 278584 kb
Host smart-c298c89b-24c2-40ac-8521-59476678d099
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2748616826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.2748616826
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1124535237
Short name T373
Test name
Test status
Simulation time 22771575 ps
CPU time 0.88 seconds
Started Jul 14 05:31:19 PM PDT 24
Finished Jul 14 05:31:21 PM PDT 24
Peak memory 211276 kb
Host smart-ed6f81d5-6274-4c53-b72d-f954a171b992
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124535237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1124535237
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3195072334
Short name T315
Test name
Test status
Simulation time 74269116 ps
CPU time 0.95 seconds
Started Jul 14 05:31:20 PM PDT 24
Finished Jul 14 05:31:23 PM PDT 24
Peak memory 208384 kb
Host smart-97f48924-5421-4663-909a-17ca281267c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195072334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3195072334
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.4060090350
Short name T399
Test name
Test status
Simulation time 1215386024 ps
CPU time 15.37 seconds
Started Jul 14 05:31:18 PM PDT 24
Finished Jul 14 05:31:34 PM PDT 24
Peak memory 217712 kb
Host smart-2fdfb07b-5ba2-4907-be63-f1a34b820faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060090350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.4060090350
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.260148677
Short name T321
Test name
Test status
Simulation time 875861031 ps
CPU time 6.64 seconds
Started Jul 14 05:31:21 PM PDT 24
Finished Jul 14 05:31:30 PM PDT 24
Peak memory 216212 kb
Host smart-0d10d787-2457-45f3-81c2-74c484c09925
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260148677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.260148677
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1486791267
Short name T293
Test name
Test status
Simulation time 355843106 ps
CPU time 4.28 seconds
Started Jul 14 05:31:21 PM PDT 24
Finished Jul 14 05:31:28 PM PDT 24
Peak memory 221836 kb
Host smart-55a1bb38-ebaa-4708-9842-1270e3c9bdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486791267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1486791267
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.86079435
Short name T695
Test name
Test status
Simulation time 1484062352 ps
CPU time 11.68 seconds
Started Jul 14 05:31:21 PM PDT 24
Finished Jul 14 05:31:35 PM PDT 24
Peak memory 218372 kb
Host smart-89e77055-7520-4a2e-a6d2-ffc4957d352f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86079435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.86079435
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2114920172
Short name T703
Test name
Test status
Simulation time 1255981036 ps
CPU time 11.98 seconds
Started Jul 14 05:31:20 PM PDT 24
Finished Jul 14 05:31:33 PM PDT 24
Peak memory 225396 kb
Host smart-7ec0fd90-5ef1-4de3-9aab-87ce85f08b54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114920172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2114920172
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3188084374
Short name T158
Test name
Test status
Simulation time 1153707861 ps
CPU time 9.57 seconds
Started Jul 14 05:31:20 PM PDT 24
Finished Jul 14 05:31:32 PM PDT 24
Peak memory 225396 kb
Host smart-60a9627a-d6ef-4354-b128-b7eeaab07afa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188084374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3188084374
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2880358612
Short name T629
Test name
Test status
Simulation time 469564621 ps
CPU time 9.57 seconds
Started Jul 14 05:31:19 PM PDT 24
Finished Jul 14 05:31:29 PM PDT 24
Peak memory 224548 kb
Host smart-2f79e7b1-1650-417e-896a-4ea7050a9993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880358612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2880358612
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3905580425
Short name T490
Test name
Test status
Simulation time 760218156 ps
CPU time 1.66 seconds
Started Jul 14 05:31:21 PM PDT 24
Finished Jul 14 05:31:25 PM PDT 24
Peak memory 216344 kb
Host smart-b7eda649-9b5a-4f9e-9888-8811ef62c2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905580425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3905580425
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3247670129
Short name T368
Test name
Test status
Simulation time 1212960301 ps
CPU time 31.61 seconds
Started Jul 14 05:31:20 PM PDT 24
Finished Jul 14 05:31:53 PM PDT 24
Peak memory 250452 kb
Host smart-43b1f00c-2b66-4d29-a85f-5acf30a2e67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247670129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3247670129
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2274434610
Short name T353
Test name
Test status
Simulation time 113647314 ps
CPU time 2.59 seconds
Started Jul 14 05:31:19 PM PDT 24
Finished Jul 14 05:31:22 PM PDT 24
Peak memory 223496 kb
Host smart-7cd3b9cd-7656-45d8-877d-568b7f72d565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274434610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2274434610
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3702084268
Short name T748
Test name
Test status
Simulation time 1662975702 ps
CPU time 41.55 seconds
Started Jul 14 05:31:22 PM PDT 24
Finished Jul 14 05:32:05 PM PDT 24
Peak memory 270160 kb
Host smart-0f3fd2a9-5024-4b43-a772-6ef8180b684d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702084268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3702084268
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.4097553592
Short name T106
Test name
Test status
Simulation time 26677434712 ps
CPU time 1097.4 seconds
Started Jul 14 05:31:20 PM PDT 24
Finished Jul 14 05:49:39 PM PDT 24
Peak memory 259484 kb
Host smart-590c6f44-bcba-4853-bb9b-db8bcb4dbabb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4097553592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.4097553592
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1204923217
Short name T292
Test name
Test status
Simulation time 14191693 ps
CPU time 0.8 seconds
Started Jul 14 05:31:19 PM PDT 24
Finished Jul 14 05:31:20 PM PDT 24
Peak memory 208296 kb
Host smart-bf0b8028-0e18-4ca6-a063-0c85103539e6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204923217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.1204923217
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3976057732
Short name T611
Test name
Test status
Simulation time 14210090 ps
CPU time 0.84 seconds
Started Jul 14 05:31:23 PM PDT 24
Finished Jul 14 05:31:26 PM PDT 24
Peak memory 208280 kb
Host smart-f746dc76-865e-4b5f-9c8f-51046c94b722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976057732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3976057732
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3092859639
Short name T633
Test name
Test status
Simulation time 220736011 ps
CPU time 10.13 seconds
Started Jul 14 05:31:20 PM PDT 24
Finished Jul 14 05:31:32 PM PDT 24
Peak memory 217640 kb
Host smart-0a0d1474-2d3f-4ee9-b2ed-7ca6a7a66025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092859639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3092859639
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.835668339
Short name T25
Test name
Test status
Simulation time 2038940835 ps
CPU time 9.64 seconds
Started Jul 14 05:31:20 PM PDT 24
Finished Jul 14 05:31:32 PM PDT 24
Peak memory 217100 kb
Host smart-ef6da5e4-8d72-420b-a06c-23d7631429ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835668339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.835668339
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.881151659
Short name T663
Test name
Test status
Simulation time 231031507 ps
CPU time 3.11 seconds
Started Jul 14 05:31:21 PM PDT 24
Finished Jul 14 05:31:26 PM PDT 24
Peak memory 217712 kb
Host smart-50a05a7a-3cb6-43a4-b54f-a8e8b683e9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881151659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.881151659
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2897228974
Short name T357
Test name
Test status
Simulation time 419907481 ps
CPU time 15.64 seconds
Started Jul 14 05:31:23 PM PDT 24
Finished Jul 14 05:31:40 PM PDT 24
Peak memory 217640 kb
Host smart-1b416456-6c86-4d20-809f-afb3a2db1b19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897228974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2897228974
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2715483000
Short name T298
Test name
Test status
Simulation time 2156832796 ps
CPU time 13.33 seconds
Started Jul 14 05:31:22 PM PDT 24
Finished Jul 14 05:31:37 PM PDT 24
Peak memory 225500 kb
Host smart-693ba5c2-cdf1-4d97-9b2a-4b139de5e71f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715483000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2715483000
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.367037070
Short name T364
Test name
Test status
Simulation time 532055832 ps
CPU time 12.23 seconds
Started Jul 14 05:31:22 PM PDT 24
Finished Jul 14 05:31:36 PM PDT 24
Peak memory 217632 kb
Host smart-7ba9554d-8e2f-494a-87e9-a0916c66a08c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367037070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.367037070
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3617854412
Short name T605
Test name
Test status
Simulation time 2881592207 ps
CPU time 8.41 seconds
Started Jul 14 05:31:22 PM PDT 24
Finished Jul 14 05:31:32 PM PDT 24
Peak memory 217828 kb
Host smart-66c38fc5-3f22-4e8f-86a7-c96572a32698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617854412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3617854412
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1539111657
Short name T532
Test name
Test status
Simulation time 179106492 ps
CPU time 2.58 seconds
Started Jul 14 05:31:21 PM PDT 24
Finished Jul 14 05:31:26 PM PDT 24
Peak memory 213784 kb
Host smart-bc40b670-f1b2-46a0-a808-574e8d14bc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539111657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1539111657
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3431452836
Short name T305
Test name
Test status
Simulation time 444070449 ps
CPU time 25.36 seconds
Started Jul 14 05:31:23 PM PDT 24
Finished Jul 14 05:31:50 PM PDT 24
Peak memory 246420 kb
Host smart-867706c6-100a-4b10-85b2-5ace3df38e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431452836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3431452836
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.2843472202
Short name T757
Test name
Test status
Simulation time 383195760 ps
CPU time 8.26 seconds
Started Jul 14 05:31:19 PM PDT 24
Finished Jul 14 05:31:29 PM PDT 24
Peak memory 250460 kb
Host smart-b9e89721-a6b8-47f5-914a-e513129c00b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843472202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2843472202
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3863449346
Short name T707
Test name
Test status
Simulation time 1066624521 ps
CPU time 42.7 seconds
Started Jul 14 05:31:20 PM PDT 24
Finished Jul 14 05:32:05 PM PDT 24
Peak memory 266860 kb
Host smart-f343f9b7-406f-443f-90ae-325f5b886199
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863449346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3863449346
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2731854267
Short name T332
Test name
Test status
Simulation time 13318839 ps
CPU time 0.8 seconds
Started Jul 14 05:31:21 PM PDT 24
Finished Jul 14 05:31:23 PM PDT 24
Peak memory 208232 kb
Host smart-3f99d13b-a498-4efd-b173-494fefd2efc3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731854267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2731854267
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3214085195
Short name T297
Test name
Test status
Simulation time 43112351 ps
CPU time 1.09 seconds
Started Jul 14 05:28:02 PM PDT 24
Finished Jul 14 05:28:04 PM PDT 24
Peak memory 208440 kb
Host smart-898aadfd-cddc-415e-be65-e6d44ccf24d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214085195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3214085195
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.493233748
Short name T520
Test name
Test status
Simulation time 726203791 ps
CPU time 9.92 seconds
Started Jul 14 05:27:55 PM PDT 24
Finished Jul 14 05:28:05 PM PDT 24
Peak memory 217572 kb
Host smart-2335ed35-95fe-4679-9d1e-8f0686ded82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493233748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.493233748
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3084971871
Short name T622
Test name
Test status
Simulation time 657373223 ps
CPU time 5.91 seconds
Started Jul 14 05:27:54 PM PDT 24
Finished Jul 14 05:28:01 PM PDT 24
Peak memory 216760 kb
Host smart-0ef301ae-264d-4e66-8fa7-8a9df704e0e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084971871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3084971871
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1210452696
Short name T479
Test name
Test status
Simulation time 1869339261 ps
CPU time 58.33 seconds
Started Jul 14 05:27:54 PM PDT 24
Finished Jul 14 05:28:54 PM PDT 24
Peak memory 225436 kb
Host smart-0d6f656e-c390-4d94-8871-3ae0fb7230cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210452696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1210452696
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1821968291
Short name T497
Test name
Test status
Simulation time 2145319773 ps
CPU time 5.71 seconds
Started Jul 14 05:27:56 PM PDT 24
Finished Jul 14 05:28:03 PM PDT 24
Peak memory 217168 kb
Host smart-4ab7b8a2-7dcc-4411-a139-f2a247840042
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821968291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.1
821968291
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3159344675
Short name T2
Test name
Test status
Simulation time 423646841 ps
CPU time 7.7 seconds
Started Jul 14 05:27:55 PM PDT 24
Finished Jul 14 05:28:03 PM PDT 24
Peak memory 223724 kb
Host smart-bd35a5de-bef2-497a-956b-a337281da3fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159344675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3159344675
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2256835071
Short name T155
Test name
Test status
Simulation time 857034946 ps
CPU time 23.14 seconds
Started Jul 14 05:27:59 PM PDT 24
Finished Jul 14 05:28:23 PM PDT 24
Peak memory 217048 kb
Host smart-16180210-ff78-4cb2-b42d-e14a1447cf95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256835071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2256835071
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.185572000
Short name T262
Test name
Test status
Simulation time 67641056 ps
CPU time 1.76 seconds
Started Jul 14 05:27:55 PM PDT 24
Finished Jul 14 05:27:58 PM PDT 24
Peak memory 216976 kb
Host smart-547f532e-f9fd-4ca0-a497-b118703b882a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185572000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.185572000
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2780786030
Short name T82
Test name
Test status
Simulation time 2712149674 ps
CPU time 64.34 seconds
Started Jul 14 05:27:55 PM PDT 24
Finished Jul 14 05:29:00 PM PDT 24
Peak memory 277056 kb
Host smart-2c3c6e06-4c83-4d5a-a7b9-875de74e60f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780786030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2780786030
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.843104264
Short name T212
Test name
Test status
Simulation time 1224128001 ps
CPU time 12.51 seconds
Started Jul 14 05:27:57 PM PDT 24
Finished Jul 14 05:28:10 PM PDT 24
Peak memory 250316 kb
Host smart-f58f7022-ea1c-4554-9d45-b4c18f8ccc57
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843104264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.843104264
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.183684077
Short name T631
Test name
Test status
Simulation time 62199519 ps
CPU time 1.76 seconds
Started Jul 14 05:27:56 PM PDT 24
Finished Jul 14 05:27:59 PM PDT 24
Peak memory 221376 kb
Host smart-a039c0a0-a2c8-4801-b9ba-8749930882fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183684077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.183684077
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1358898182
Short name T390
Test name
Test status
Simulation time 191927520 ps
CPU time 10.42 seconds
Started Jul 14 05:27:53 PM PDT 24
Finished Jul 14 05:28:04 PM PDT 24
Peak memory 217072 kb
Host smart-249bff65-9495-4533-be8e-820cfde26ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358898182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1358898182
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2044662348
Short name T679
Test name
Test status
Simulation time 701950606 ps
CPU time 12.56 seconds
Started Jul 14 05:28:00 PM PDT 24
Finished Jul 14 05:28:13 PM PDT 24
Peak memory 225388 kb
Host smart-e3b5c38c-0ca0-4784-800b-0ec7bcf57215
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044662348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2044662348
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.413420106
Short name T177
Test name
Test status
Simulation time 4447763418 ps
CPU time 12.68 seconds
Started Jul 14 05:28:00 PM PDT 24
Finished Jul 14 05:28:14 PM PDT 24
Peak memory 225480 kb
Host smart-bd50b5a6-a788-42f4-871b-778fe5798fb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413420106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.413420106
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.4166444482
Short name T628
Test name
Test status
Simulation time 1550606717 ps
CPU time 12.68 seconds
Started Jul 14 05:27:56 PM PDT 24
Finished Jul 14 05:28:09 PM PDT 24
Peak memory 225448 kb
Host smart-62a1cea6-15b1-4315-b2b9-e2266f55c0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166444482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.4166444482
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1370449177
Short name T73
Test name
Test status
Simulation time 648367815 ps
CPU time 3.62 seconds
Started Jul 14 05:27:49 PM PDT 24
Finished Jul 14 05:27:53 PM PDT 24
Peak memory 217180 kb
Host smart-977dfbc5-2ae6-4b1a-948f-2f906e1a95e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370449177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1370449177
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3278269389
Short name T417
Test name
Test status
Simulation time 184926030 ps
CPU time 27.01 seconds
Started Jul 14 05:27:53 PM PDT 24
Finished Jul 14 05:28:20 PM PDT 24
Peak memory 250044 kb
Host smart-963b6eb8-2d5b-479e-b115-7058f2c3cd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278269389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3278269389
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.133656068
Short name T240
Test name
Test status
Simulation time 440272497 ps
CPU time 7.85 seconds
Started Jul 14 05:27:54 PM PDT 24
Finished Jul 14 05:28:03 PM PDT 24
Peak memory 250460 kb
Host smart-272d0f97-2774-4a0c-9cd7-9bb2596caba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133656068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.133656068
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.4285115357
Short name T444
Test name
Test status
Simulation time 10033097832 ps
CPU time 329.06 seconds
Started Jul 14 05:28:03 PM PDT 24
Finished Jul 14 05:33:32 PM PDT 24
Peak memory 283280 kb
Host smart-7ed0cea3-9db5-4b3e-a46b-a2727fd7a828
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285115357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.4285115357
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2581160609
Short name T418
Test name
Test status
Simulation time 12201528 ps
CPU time 1.13 seconds
Started Jul 14 05:27:47 PM PDT 24
Finished Jul 14 05:27:48 PM PDT 24
Peak memory 211392 kb
Host smart-c426a626-aac1-4f82-8cd0-e61f4930a3bd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581160609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2581160609
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.4120648653
Short name T666
Test name
Test status
Simulation time 31852030 ps
CPU time 0.8 seconds
Started Jul 14 05:28:06 PM PDT 24
Finished Jul 14 05:28:07 PM PDT 24
Peak memory 208448 kb
Host smart-8ee83d3e-9c62-4bbe-84a3-c8366f3f2499
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120648653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.4120648653
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.382552151
Short name T286
Test name
Test status
Simulation time 11110749 ps
CPU time 0.82 seconds
Started Jul 14 05:28:02 PM PDT 24
Finished Jul 14 05:28:04 PM PDT 24
Peak memory 208384 kb
Host smart-042b666a-c276-437e-b892-039cc69bff9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382552151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.382552151
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.707810582
Short name T834
Test name
Test status
Simulation time 1578214321 ps
CPU time 13.09 seconds
Started Jul 14 05:28:04 PM PDT 24
Finished Jul 14 05:28:17 PM PDT 24
Peak memory 217760 kb
Host smart-36a96f55-dc61-437c-9589-26bbcc828cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707810582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.707810582
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.4146500740
Short name T511
Test name
Test status
Simulation time 247933559 ps
CPU time 1.91 seconds
Started Jul 14 05:28:00 PM PDT 24
Finished Jul 14 05:28:03 PM PDT 24
Peak memory 216584 kb
Host smart-a8652b7a-2c5f-488a-a0eb-009b260f4f14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146500740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.4146500740
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2811606384
Short name T645
Test name
Test status
Simulation time 9851242975 ps
CPU time 51.55 seconds
Started Jul 14 05:27:59 PM PDT 24
Finished Jul 14 05:28:51 PM PDT 24
Peak memory 218332 kb
Host smart-dcb801a1-9c6b-4b0c-9343-58ae285273c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811606384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2811606384
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.880359084
Short name T480
Test name
Test status
Simulation time 1518980405 ps
CPU time 4.56 seconds
Started Jul 14 05:28:04 PM PDT 24
Finished Jul 14 05:28:09 PM PDT 24
Peak memory 217120 kb
Host smart-0a33029f-73e7-4f4b-8b91-d30b5dc6f453
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880359084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.880359084
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.386404916
Short name T181
Test name
Test status
Simulation time 623914876 ps
CPU time 5.82 seconds
Started Jul 14 05:28:01 PM PDT 24
Finished Jul 14 05:28:07 PM PDT 24
Peak memory 222412 kb
Host smart-69fcd425-d6a9-49c7-8622-aeaa121b96d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386404916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.386404916
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.924693641
Short name T278
Test name
Test status
Simulation time 2100626971 ps
CPU time 31.47 seconds
Started Jul 14 05:28:02 PM PDT 24
Finished Jul 14 05:28:34 PM PDT 24
Peak memory 217064 kb
Host smart-892cc945-b979-4b0f-910f-916ea8df25ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924693641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_regwen_during_op.924693641
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2781876690
Short name T225
Test name
Test status
Simulation time 834641628 ps
CPU time 10.68 seconds
Started Jul 14 05:28:06 PM PDT 24
Finished Jul 14 05:28:17 PM PDT 24
Peak memory 217080 kb
Host smart-7f2c7811-2de8-403b-8c2c-c95c8e7595d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781876690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2781876690
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3484676057
Short name T624
Test name
Test status
Simulation time 3770238763 ps
CPU time 42.77 seconds
Started Jul 14 05:28:00 PM PDT 24
Finished Jul 14 05:28:44 PM PDT 24
Peak memory 250328 kb
Host smart-44909375-873c-4b58-9e84-6948f8025e20
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484676057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3484676057
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1412579784
Short name T715
Test name
Test status
Simulation time 505589250 ps
CPU time 16.14 seconds
Started Jul 14 05:28:03 PM PDT 24
Finished Jul 14 05:28:19 PM PDT 24
Peak memory 250404 kb
Host smart-52bbe066-f7fb-4cdd-b549-0ac87fdd22fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412579784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1412579784
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.668773970
Short name T12
Test name
Test status
Simulation time 186628751 ps
CPU time 2.73 seconds
Started Jul 14 05:28:00 PM PDT 24
Finished Jul 14 05:28:03 PM PDT 24
Peak memory 217528 kb
Host smart-40bd1615-6620-44f3-88de-2649e76ed111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668773970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.668773970
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3417632411
Short name T54
Test name
Test status
Simulation time 1287381858 ps
CPU time 18.04 seconds
Started Jul 14 05:27:59 PM PDT 24
Finished Jul 14 05:28:18 PM PDT 24
Peak memory 217132 kb
Host smart-53ebd494-1262-4ea4-b07e-fb41e05d0463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417632411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3417632411
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3350999105
Short name T651
Test name
Test status
Simulation time 258443429 ps
CPU time 8.41 seconds
Started Jul 14 05:28:06 PM PDT 24
Finished Jul 14 05:28:16 PM PDT 24
Peak memory 217732 kb
Host smart-e797daf7-6d66-4974-9fd5-0645547d1147
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350999105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3350999105
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.140795114
Short name T389
Test name
Test status
Simulation time 958242699 ps
CPU time 8.89 seconds
Started Jul 14 05:28:00 PM PDT 24
Finished Jul 14 05:28:09 PM PDT 24
Peak memory 225412 kb
Host smart-ac103399-d859-452f-a11e-eb7fbd650bab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140795114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.140795114
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3199460690
Short name T165
Test name
Test status
Simulation time 235253992 ps
CPU time 6.89 seconds
Started Jul 14 05:28:02 PM PDT 24
Finished Jul 14 05:28:09 PM PDT 24
Peak memory 217668 kb
Host smart-aba39132-9dfd-43ba-a8a4-bd6103705ea4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199460690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
199460690
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1612146497
Short name T568
Test name
Test status
Simulation time 34237723 ps
CPU time 1.46 seconds
Started Jul 14 05:28:00 PM PDT 24
Finished Jul 14 05:28:03 PM PDT 24
Peak memory 213320 kb
Host smart-df7fb888-b669-4e2d-ae47-be9012362951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612146497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1612146497
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1739596017
Short name T217
Test name
Test status
Simulation time 905543500 ps
CPU time 28.91 seconds
Started Jul 14 05:28:06 PM PDT 24
Finished Jul 14 05:28:36 PM PDT 24
Peak memory 250584 kb
Host smart-4a45ca87-f7e5-47f3-84ec-81a224315d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739596017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1739596017
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3110043223
Short name T544
Test name
Test status
Simulation time 169126121 ps
CPU time 7.41 seconds
Started Jul 14 05:27:59 PM PDT 24
Finished Jul 14 05:28:07 PM PDT 24
Peak memory 225460 kb
Host smart-cdd9ae62-6ffa-43e9-91f0-03760717440a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110043223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3110043223
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.286743244
Short name T677
Test name
Test status
Simulation time 5255230422 ps
CPU time 136.45 seconds
Started Jul 14 05:28:06 PM PDT 24
Finished Jul 14 05:30:24 PM PDT 24
Peak memory 274932 kb
Host smart-77d7738b-af66-4f6a-99f1-33d73fadeae1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286743244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.286743244
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1317190741
Short name T74
Test name
Test status
Simulation time 50077734 ps
CPU time 1.04 seconds
Started Jul 14 05:28:05 PM PDT 24
Finished Jul 14 05:28:07 PM PDT 24
Peak memory 211356 kb
Host smart-98cf7605-2fc6-4c34-bbc7-8020da3714e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317190741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1317190741
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3521925494
Short name T574
Test name
Test status
Simulation time 67167654 ps
CPU time 0.82 seconds
Started Jul 14 05:28:10 PM PDT 24
Finished Jul 14 05:28:11 PM PDT 24
Peak memory 208448 kb
Host smart-79456ecc-7902-49d4-93f1-3b7cdb90cb6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521925494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3521925494
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.222498399
Short name T264
Test name
Test status
Simulation time 330903424 ps
CPU time 11.81 seconds
Started Jul 14 05:28:06 PM PDT 24
Finished Jul 14 05:28:20 PM PDT 24
Peak memory 217628 kb
Host smart-f02f2108-9e86-4c64-94b8-6321f5735ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222498399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.222498399
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.98771917
Short name T21
Test name
Test status
Simulation time 1215988212 ps
CPU time 7.33 seconds
Started Jul 14 05:28:13 PM PDT 24
Finished Jul 14 05:28:21 PM PDT 24
Peak memory 217076 kb
Host smart-1b581db2-67cf-474c-ab4d-727d72abc39f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98771917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.98771917
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.4213193223
Short name T38
Test name
Test status
Simulation time 1776187221 ps
CPU time 35.88 seconds
Started Jul 14 05:28:05 PM PDT 24
Finished Jul 14 05:28:42 PM PDT 24
Peak memory 217584 kb
Host smart-f3aa1c5c-63e0-480c-8ca0-a6f69cfc20b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213193223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.4213193223
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3766535981
Short name T419
Test name
Test status
Simulation time 458366158 ps
CPU time 2.05 seconds
Started Jul 14 05:28:13 PM PDT 24
Finished Jul 14 05:28:16 PM PDT 24
Peak memory 217124 kb
Host smart-50e70263-31a1-4391-8c4d-c9fda21c086d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766535981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
766535981
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.277159979
Short name T617
Test name
Test status
Simulation time 703713006 ps
CPU time 6.39 seconds
Started Jul 14 05:28:07 PM PDT 24
Finished Jul 14 05:28:15 PM PDT 24
Peak memory 222624 kb
Host smart-eabd5861-7d70-43ea-93fd-934240e50789
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277159979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.277159979
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.4046458334
Short name T672
Test name
Test status
Simulation time 3673406307 ps
CPU time 13.86 seconds
Started Jul 14 05:28:13 PM PDT 24
Finished Jul 14 05:28:28 PM PDT 24
Peak memory 217068 kb
Host smart-509adbc2-6ef0-4447-9a0e-b53a9bb001d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046458334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.4046458334
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3920702839
Short name T710
Test name
Test status
Simulation time 2548746021 ps
CPU time 8.52 seconds
Started Jul 14 05:28:07 PM PDT 24
Finished Jul 14 05:28:17 PM PDT 24
Peak memory 217112 kb
Host smart-eb0ed25d-fc0f-4dd6-8647-ec5a8400c222
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920702839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3920702839
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2656277797
Short name T17
Test name
Test status
Simulation time 3882448870 ps
CPU time 55.69 seconds
Started Jul 14 05:28:08 PM PDT 24
Finished Jul 14 05:29:04 PM PDT 24
Peak memory 280080 kb
Host smart-112c4e4d-942b-4d84-a080-e54bd1caeb16
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656277797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2656277797
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3819350477
Short name T4
Test name
Test status
Simulation time 328013249 ps
CPU time 17.77 seconds
Started Jul 14 05:28:06 PM PDT 24
Finished Jul 14 05:28:25 PM PDT 24
Peak memory 250360 kb
Host smart-bc5d8ffa-dd6b-4799-b6f6-f09fdd8b1ae8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819350477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3819350477
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3430095732
Short name T481
Test name
Test status
Simulation time 51160011 ps
CPU time 3.06 seconds
Started Jul 14 05:28:07 PM PDT 24
Finished Jul 14 05:28:11 PM PDT 24
Peak memory 217700 kb
Host smart-3c8bcacb-e59c-484f-b17d-a423cb1eeeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430095732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3430095732
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3955467527
Short name T397
Test name
Test status
Simulation time 1473952279 ps
CPU time 9.87 seconds
Started Jul 14 05:28:08 PM PDT 24
Finished Jul 14 05:28:19 PM PDT 24
Peak memory 217124 kb
Host smart-a2699be6-f253-40cc-b89b-84d776543955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955467527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3955467527
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2102103418
Short name T249
Test name
Test status
Simulation time 430343771 ps
CPU time 15.5 seconds
Started Jul 14 05:28:12 PM PDT 24
Finished Jul 14 05:28:29 PM PDT 24
Peak memory 225412 kb
Host smart-ec7032b2-8764-4c4b-9b2c-5a999f64aadf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102103418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2102103418
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3283731120
Short name T660
Test name
Test status
Simulation time 266179499 ps
CPU time 10.23 seconds
Started Jul 14 05:28:11 PM PDT 24
Finished Jul 14 05:28:23 PM PDT 24
Peak memory 217596 kb
Host smart-52f3c944-0163-4459-8682-c21b3b07416d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283731120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
283731120
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2165470643
Short name T846
Test name
Test status
Simulation time 565954704 ps
CPU time 6.22 seconds
Started Jul 14 05:28:06 PM PDT 24
Finished Jul 14 05:28:14 PM PDT 24
Peak memory 223584 kb
Host smart-4baff1c5-9400-44bc-9563-a9221f6a7f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165470643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2165470643
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2878836020
Short name T164
Test name
Test status
Simulation time 255779176 ps
CPU time 7.55 seconds
Started Jul 14 05:28:05 PM PDT 24
Finished Jul 14 05:28:13 PM PDT 24
Peak memory 217108 kb
Host smart-1c1c6d44-ed0e-4789-91f0-5acc97d52f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878836020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2878836020
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1131216902
Short name T500
Test name
Test status
Simulation time 189698728 ps
CPU time 21.1 seconds
Started Jul 14 05:28:05 PM PDT 24
Finished Jul 14 05:28:27 PM PDT 24
Peak memory 245580 kb
Host smart-53085603-3ae7-4fe6-a7af-7342cadfa5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131216902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1131216902
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2182532865
Short name T367
Test name
Test status
Simulation time 738538821 ps
CPU time 8.1 seconds
Started Jul 14 05:28:08 PM PDT 24
Finished Jul 14 05:28:17 PM PDT 24
Peak memory 250456 kb
Host smart-cbf55329-3520-49d5-a6e6-d3819eceafc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182532865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2182532865
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2668434890
Short name T330
Test name
Test status
Simulation time 8918016624 ps
CPU time 79.81 seconds
Started Jul 14 05:28:13 PM PDT 24
Finished Jul 14 05:29:34 PM PDT 24
Peak memory 250452 kb
Host smart-e1126857-23c2-4744-bb49-7227f3c08ae7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668434890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2668434890
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.403821694
Short name T526
Test name
Test status
Simulation time 26169521 ps
CPU time 0.99 seconds
Started Jul 14 05:28:05 PM PDT 24
Finished Jul 14 05:28:06 PM PDT 24
Peak memory 211388 kb
Host smart-ba4a2c8d-0ede-4054-a618-0e99973895c4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403821694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.403821694
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1999001471
Short name T310
Test name
Test status
Simulation time 113022514 ps
CPU time 1.32 seconds
Started Jul 14 05:28:24 PM PDT 24
Finished Jul 14 05:28:26 PM PDT 24
Peak memory 208464 kb
Host smart-7cc48bb1-31be-44f6-9dec-b14eecd3a87f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999001471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1999001471
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1736627082
Short name T207
Test name
Test status
Simulation time 35318135 ps
CPU time 0.78 seconds
Started Jul 14 05:28:18 PM PDT 24
Finished Jul 14 05:28:19 PM PDT 24
Peak memory 208444 kb
Host smart-536e2873-8da0-4653-a5f2-6d7fa3a1bf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736627082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1736627082
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.4133617463
Short name T325
Test name
Test status
Simulation time 879384373 ps
CPU time 6.42 seconds
Started Jul 14 05:28:18 PM PDT 24
Finished Jul 14 05:28:25 PM PDT 24
Peak memory 217096 kb
Host smart-d79fb022-b010-43a7-9e04-67332c4ae4ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133617463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.4133617463
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2702393316
Short name T656
Test name
Test status
Simulation time 3150745112 ps
CPU time 81.27 seconds
Started Jul 14 05:28:18 PM PDT 24
Finished Jul 14 05:29:40 PM PDT 24
Peak memory 217756 kb
Host smart-b0562fef-188f-4f95-97e7-12d707317b52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702393316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2702393316
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.376624455
Short name T420
Test name
Test status
Simulation time 1126506724 ps
CPU time 4.58 seconds
Started Jul 14 05:28:16 PM PDT 24
Finished Jul 14 05:28:20 PM PDT 24
Peak memory 217068 kb
Host smart-de33df73-293d-4b2a-8bbb-8bdba447f354
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376624455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.376624455
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2882244721
Short name T547
Test name
Test status
Simulation time 58913951 ps
CPU time 2.72 seconds
Started Jul 14 05:28:18 PM PDT 24
Finished Jul 14 05:28:21 PM PDT 24
Peak memory 217596 kb
Host smart-39e29544-61af-4930-b5ae-6c47c3e9613c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882244721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2882244721
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.956527399
Short name T623
Test name
Test status
Simulation time 4194057567 ps
CPU time 16.55 seconds
Started Jul 14 05:28:19 PM PDT 24
Finished Jul 14 05:28:36 PM PDT 24
Peak memory 217148 kb
Host smart-f18cee7b-b1fa-4a47-b289-607071c405f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956527399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.956527399
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2402342449
Short name T492
Test name
Test status
Simulation time 501936284 ps
CPU time 4.41 seconds
Started Jul 14 05:28:18 PM PDT 24
Finished Jul 14 05:28:23 PM PDT 24
Peak memory 217060 kb
Host smart-25900c3a-f5e7-4482-8349-0537a38558e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402342449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2402342449
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.530986251
Short name T256
Test name
Test status
Simulation time 2563985382 ps
CPU time 63.89 seconds
Started Jul 14 05:28:20 PM PDT 24
Finished Jul 14 05:29:24 PM PDT 24
Peak memory 275308 kb
Host smart-fe43ece7-5d4f-47b2-8478-40966c88217c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530986251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.530986251
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1090182622
Short name T269
Test name
Test status
Simulation time 20214134081 ps
CPU time 20.61 seconds
Started Jul 14 05:28:17 PM PDT 24
Finished Jul 14 05:28:38 PM PDT 24
Peak memory 250508 kb
Host smart-c430597c-8ca8-4bab-b391-868c75b6481e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090182622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1090182622
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3926329538
Short name T567
Test name
Test status
Simulation time 272013542 ps
CPU time 1.78 seconds
Started Jul 14 05:28:10 PM PDT 24
Finished Jul 14 05:28:12 PM PDT 24
Peak memory 217712 kb
Host smart-fc48da23-4566-41c5-9e65-3de631f13fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926329538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3926329538
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.124033288
Short name T71
Test name
Test status
Simulation time 213657228 ps
CPU time 7.79 seconds
Started Jul 14 05:28:19 PM PDT 24
Finished Jul 14 05:28:27 PM PDT 24
Peak memory 217096 kb
Host smart-876a8023-dbfe-41f6-98e5-5695196ef491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124033288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.124033288
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2114524603
Short name T95
Test name
Test status
Simulation time 835262303 ps
CPU time 9.18 seconds
Started Jul 14 05:28:18 PM PDT 24
Finished Jul 14 05:28:28 PM PDT 24
Peak memory 224844 kb
Host smart-5b67aae6-8ea1-4a16-bdda-8ab525e7f886
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114524603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2114524603
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3820624266
Short name T808
Test name
Test status
Simulation time 236225978 ps
CPU time 9.83 seconds
Started Jul 14 05:28:18 PM PDT 24
Finished Jul 14 05:28:28 PM PDT 24
Peak memory 217684 kb
Host smart-bbaea390-992e-49a6-ae4c-ecc3f9c4267f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820624266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
820624266
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2595633019
Short name T294
Test name
Test status
Simulation time 3359773092 ps
CPU time 7.72 seconds
Started Jul 14 05:28:13 PM PDT 24
Finished Jul 14 05:28:21 PM PDT 24
Peak memory 217796 kb
Host smart-cbadb101-2d28-41f8-9e1c-bfdd5acb13a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595633019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2595633019
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.325532090
Short name T519
Test name
Test status
Simulation time 149082910 ps
CPU time 2.4 seconds
Started Jul 14 05:28:11 PM PDT 24
Finished Jul 14 05:28:13 PM PDT 24
Peak memory 217120 kb
Host smart-2a8e329b-df32-4fef-b286-6ccfe25201d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325532090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.325532090
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.774479795
Short name T517
Test name
Test status
Simulation time 1039589619 ps
CPU time 35.27 seconds
Started Jul 14 05:28:11 PM PDT 24
Finished Jul 14 05:28:47 PM PDT 24
Peak memory 250384 kb
Host smart-0771b161-7416-4849-aad4-f4b5ea273563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774479795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.774479795
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.1889170431
Short name T180
Test name
Test status
Simulation time 217853655 ps
CPU time 6.82 seconds
Started Jul 14 05:28:11 PM PDT 24
Finished Jul 14 05:28:19 PM PDT 24
Peak memory 246712 kb
Host smart-270eea52-3dd8-444c-beef-60daceb3f7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889170431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1889170431
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2246803573
Short name T254
Test name
Test status
Simulation time 3068468670 ps
CPU time 82 seconds
Started Jul 14 05:28:19 PM PDT 24
Finished Jul 14 05:29:41 PM PDT 24
Peak memory 225552 kb
Host smart-47d05ca8-2856-4ed4-a393-8b10c8c6c3ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246803573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2246803573
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.2150554854
Short name T142
Test name
Test status
Simulation time 152175743763 ps
CPU time 864.26 seconds
Started Jul 14 05:28:22 PM PDT 24
Finished Jul 14 05:42:46 PM PDT 24
Peak memory 316240 kb
Host smart-0a32c13c-b95b-4106-994e-c3ba16218e1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2150554854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.2150554854
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1183083691
Short name T339
Test name
Test status
Simulation time 12548848 ps
CPU time 1.07 seconds
Started Jul 14 05:28:11 PM PDT 24
Finished Jul 14 05:28:13 PM PDT 24
Peak memory 211276 kb
Host smart-5f80d8fc-8510-41cd-8151-ab1992ead26a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183083691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1183083691
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.1736930025
Short name T555
Test name
Test status
Simulation time 64550663 ps
CPU time 1.18 seconds
Started Jul 14 05:28:28 PM PDT 24
Finished Jul 14 05:28:31 PM PDT 24
Peak memory 208468 kb
Host smart-05870fcb-6421-4e30-ae5a-7f38ed48460d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736930025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1736930025
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3011296971
Short name T789
Test name
Test status
Simulation time 259766320 ps
CPU time 8.63 seconds
Started Jul 14 05:28:24 PM PDT 24
Finished Jul 14 05:28:33 PM PDT 24
Peak memory 217760 kb
Host smart-6e66f98d-0571-4849-9551-0af6cd991588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011296971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3011296971
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.2905364119
Short name T460
Test name
Test status
Simulation time 2053426999 ps
CPU time 13.05 seconds
Started Jul 14 05:28:23 PM PDT 24
Finished Jul 14 05:28:36 PM PDT 24
Peak memory 217024 kb
Host smart-f323692e-48ef-4e6f-aeb8-4397ea0f3632
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905364119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2905364119
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.2666552599
Short name T445
Test name
Test status
Simulation time 1391533754 ps
CPU time 40.97 seconds
Started Jul 14 05:28:24 PM PDT 24
Finished Jul 14 05:29:06 PM PDT 24
Peak memory 217688 kb
Host smart-1f8a23f3-9005-4487-bf39-1dc097a2f3d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666552599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.2666552599
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.319334301
Short name T473
Test name
Test status
Simulation time 3824857780 ps
CPU time 4.38 seconds
Started Jul 14 05:28:24 PM PDT 24
Finished Jul 14 05:28:30 PM PDT 24
Peak memory 217148 kb
Host smart-870ddd5b-0424-46d5-91b6-d1af947c86d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319334301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.319334301
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3240971845
Short name T758
Test name
Test status
Simulation time 922526463 ps
CPU time 14.14 seconds
Started Jul 14 05:28:28 PM PDT 24
Finished Jul 14 05:28:42 PM PDT 24
Peak memory 217636 kb
Host smart-27162bf3-d986-4b4a-897b-b25d9c31ddd5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240971845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.3240971845
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.523476274
Short name T609
Test name
Test status
Simulation time 8426619955 ps
CPU time 14.24 seconds
Started Jul 14 05:28:28 PM PDT 24
Finished Jul 14 05:28:44 PM PDT 24
Peak memory 217060 kb
Host smart-f2324d86-f647-477e-9c07-c62908539a58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523476274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.523476274
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.684780266
Short name T442
Test name
Test status
Simulation time 597482690 ps
CPU time 5.12 seconds
Started Jul 14 05:28:25 PM PDT 24
Finished Jul 14 05:28:30 PM PDT 24
Peak memory 217000 kb
Host smart-3c936924-2388-4f94-9e9d-9822ebe0c30b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684780266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.684780266
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3697630251
Short name T851
Test name
Test status
Simulation time 3700773665 ps
CPU time 42.84 seconds
Started Jul 14 05:28:24 PM PDT 24
Finished Jul 14 05:29:08 PM PDT 24
Peak memory 266812 kb
Host smart-86d90543-d0c7-4dc6-afa6-0f84059c6615
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697630251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3697630251
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2172242956
Short name T392
Test name
Test status
Simulation time 1137805579 ps
CPU time 16.85 seconds
Started Jul 14 05:28:25 PM PDT 24
Finished Jul 14 05:28:43 PM PDT 24
Peak memory 223360 kb
Host smart-5d79ea61-6f2d-4dfc-99ae-1a8e29dbc666
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172242956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2172242956
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2822167829
Short name T10
Test name
Test status
Simulation time 291673104 ps
CPU time 2.83 seconds
Started Jul 14 05:28:24 PM PDT 24
Finished Jul 14 05:28:27 PM PDT 24
Peak memory 221824 kb
Host smart-10112931-e118-408d-8f00-ce3d1129848f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822167829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2822167829
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3376909474
Short name T747
Test name
Test status
Simulation time 1390351524 ps
CPU time 8.58 seconds
Started Jul 14 05:28:28 PM PDT 24
Finished Jul 14 05:28:38 PM PDT 24
Peak memory 217072 kb
Host smart-7b68cc7f-a8e4-474c-9f07-2ac99e5a30cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376909474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3376909474
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1254647749
Short name T694
Test name
Test status
Simulation time 1496935542 ps
CPU time 17.81 seconds
Started Jul 14 05:28:25 PM PDT 24
Finished Jul 14 05:28:44 PM PDT 24
Peak memory 225476 kb
Host smart-991cc1c3-f01a-4b0c-997d-8d6f19ce861d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254647749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1254647749
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2065159173
Short name T838
Test name
Test status
Simulation time 376380299 ps
CPU time 8.62 seconds
Started Jul 14 05:28:30 PM PDT 24
Finished Jul 14 05:28:39 PM PDT 24
Peak memory 225356 kb
Host smart-d898e72c-c627-4676-92c9-825a8aa74ae1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065159173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2065159173
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3759334948
Short name T618
Test name
Test status
Simulation time 319364639 ps
CPU time 11.39 seconds
Started Jul 14 05:28:28 PM PDT 24
Finished Jul 14 05:28:40 PM PDT 24
Peak memory 217896 kb
Host smart-0e21b4ac-a5f5-4229-a226-52f4f23a4eef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759334948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
759334948
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2812163729
Short name T858
Test name
Test status
Simulation time 798203533 ps
CPU time 8.72 seconds
Started Jul 14 05:28:23 PM PDT 24
Finished Jul 14 05:28:32 PM PDT 24
Peak memory 225508 kb
Host smart-c4c3d35b-b434-4cb2-8ead-b9238531f62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812163729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2812163729
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1684432876
Short name T34
Test name
Test status
Simulation time 241410320 ps
CPU time 2.75 seconds
Started Jul 14 05:28:25 PM PDT 24
Finished Jul 14 05:28:28 PM PDT 24
Peak memory 217052 kb
Host smart-257728db-fcfc-4ae2-ab19-89a2941b9f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684432876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1684432876
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3988735052
Short name T416
Test name
Test status
Simulation time 347104227 ps
CPU time 20.03 seconds
Started Jul 14 05:28:28 PM PDT 24
Finished Jul 14 05:28:49 PM PDT 24
Peak memory 250420 kb
Host smart-39f8b7f4-2d8d-489d-a83d-555ceb06c6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988735052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3988735052
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2970011809
Short name T801
Test name
Test status
Simulation time 78519739 ps
CPU time 6.83 seconds
Started Jul 14 05:28:24 PM PDT 24
Finished Jul 14 05:28:32 PM PDT 24
Peak memory 250548 kb
Host smart-5a451d43-9818-4937-a5ab-a45e471db06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970011809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2970011809
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.4077708291
Short name T739
Test name
Test status
Simulation time 2340161153 ps
CPU time 61.68 seconds
Started Jul 14 05:28:30 PM PDT 24
Finished Jul 14 05:29:32 PM PDT 24
Peak memory 270404 kb
Host smart-606cb12c-2aae-4583-98ab-cab2a1f186be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077708291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.4077708291
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.2106553530
Short name T140
Test name
Test status
Simulation time 925411720738 ps
CPU time 1608.39 seconds
Started Jul 14 05:28:29 PM PDT 24
Finished Jul 14 05:55:18 PM PDT 24
Peak memory 405180 kb
Host smart-ed713a8d-400f-4945-b251-6f0183027b53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2106553530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.2106553530
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2905505676
Short name T174
Test name
Test status
Simulation time 11476586 ps
CPU time 0.93 seconds
Started Jul 14 05:28:23 PM PDT 24
Finished Jul 14 05:28:25 PM PDT 24
Peak memory 208572 kb
Host smart-35b09a78-7170-43cd-8c47-cbc609e1d2a6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905505676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2905505676
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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