Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88680103

1

T1

4245

T2

74341

T3

24603

auto[1]

1265659

1

T4

6699

T5

392

T14

1980

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88684133

1

T1

4245

T2

74341

T3

24603

auto[1]

1261629

1

T4

6001

T5

196

T14

1683

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6506287	1			T1	901		T2	7345		T3	13787
auto[IdleSt]	20444841	1			T1	1294		T2	6957		T3	4203
auto[ClkMuxSt]	32901	1			T1	10		T2	83		T4	77
auto[CntIncrSt]	32590	1			T1	10		T2	83		T4	72
auto[CntProgSt]	1745667	1			T1	251		T2	37694		T4	2977
auto[TransCheckSt]	25491	1			T1	10		T2	83		T4	59
auto[TokenHashSt]	33059465	1			T1	184		T2	7629		T4	190996
auto[FlashRmaSt]	30739	1			T1	58		T4	54		T11	10
auto[TokenCheck0St]	11138	1			T1	10		T4	18		T11	10
auto[TokenCheck1St]	8120	1			T1	10		T4	14		T11	10
auto[TransProgSt]	391925	1			T1	204		T4	695		T11	109
auto[PostTransSt]	12267668	1			T1	1303		T2	14467		T4	10015
auto[ScrapSt]	127774	1			T3	367		T4	714		T16	1445
auto[EscalateSt]	5897286	1			T4	52945		T5	9754		T14	4742
auto[InvalidSt]	9362152	1			T3	6226		T4	165966		T5	8663

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1718	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	9362152	1			T3	6226		T4	165966		T5	8663
EscalateSt	5897286	1			T4	52945		T5	9754		T14	4742
ScrapSt	127774	1			T3	367		T4	714		T16	1445
PostTransSt	12267668	1			T1	1303		T2	14467		T4	10015
TransProgSt	391925	1			T1	204		T4	695		T11	109
TokenCheck1St	8120	1			T1	10		T4	14		T11	10
TokenCheck0St	11138	1			T1	10		T4	18		T11	10
FlashRmaSt	30739	1			T1	58		T4	54		T11	10
TokenHashSt	33059465	1			T1	184		T2	7629		T4	190996
TransCheckSt	25491	1			T1	10		T2	83		T4	59
CntProgSt	1745667	1			T1	251		T2	37694		T4	2977
CntIncrSt	32590	1			T1	10		T2	83		T4	72
ClkMuxSt	32901	1			T1	10		T2	83		T4	77
IdleSt	20444841	1			T1	1294		T2	6957		T3	4203
ResetSt	6506287	1			T1	901		T2	7345		T3	13787
arcs[ResetSt=>IdleSt]	49205	1			T1	10		T2	84		T3	121
arcs[IdleSt=>ScrapSt]	271	1			T3	7		T4	4		T16	3
arcs[IdleSt=>ClkMuxSt]	32666	1			T1	10		T2	83		T4	72
arcs[ClkMuxSt=>CntIncrSt]	32590	1			T1	10		T2	83		T4	72
arcs[CntIncrSt=>PostTransSt]	1745	1			T4	5		T15	13		T16	22
arcs[CntIncrSt=>CntProgSt]	30783	1			T1	10		T2	83		T4	67
arcs[CntProgSt=>PostTransSt]	4267	1			T4	8		T14	14		T15	11
arcs[CntProgSt=>TransCheckSt]	25491	1			T1	10		T2	83		T4	59
arcs[TransCheckSt=>PostTransSt]	3562	1			T4	6		T15	10		T16	22
arcs[TransCheckSt=>TokenHashSt]	21820	1			T1	10		T2	83		T4	53
arcs[TokenHashSt=>PostTransSt]	9839	1			T2	83		T4	35		T14	10
arcs[TokenHashSt=>FlashRmaSt]	11247	1			T1	10		T4	18		T11	10
arcs[FlashRmaSt=>TokenCheck0St]	11138	1			T1	10		T4	18		T11	10
arcs[TokenCheck0St=>PostTransSt]	2990	1			T4	4		T14	18		T15	8
arcs[TokenCheck0St=>TokenCheck1St]	8120	1			T1	10		T4	14		T11	10
arcs[TokenCheck1St=>PostTransSt]	606	1			T4	1		T16	1		T19	3
arcs[TransProgSt=>PostTransSt]	6689	1			T1	10		T4	13		T11	10
arcs[IdleSt=>EscalateSt]	177	1			T49	7		T52	12		T53	6
arcs[ClkMuxSt=>EscalateSt]	76	1			T38	2		T49	2		T50	1
arcs[CntIncrSt=>EscalateSt]	62	1			T38	2		T49	2		T51	2
arcs[CntProgSt=>EscalateSt]	1025	1			T38	7		T49	18		T51	26
arcs[TransCheckSt=>EscalateSt]	109	1			T38	6		T57	3		T56	4
arcs[TokenHashSt=>EscalateSt]	734	1			T38	30		T49	10		T51	14
arcs[FlashRmaSt=>EscalateSt]	109	1			T38	1		T49	1		T51	2
arcs[TokenCheck0St=>EscalateSt]	28	1			T50	1		T55	3		T56	2
arcs[TokenCheck1St=>EscalateSt]	129	1			T38	3		T49	2		T51	4
arcs[TransProgSt=>EscalateSt]	696	1			T38	9		T49	10		T51	19
arcs[PostTransSt=>EscalateSt]	4514	1			T4	8		T14	14		T15	11
arcs[InvalidSt=>EscalateSt]	12209	1			T4	121		T5	6		T14	23

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6506126	1			T1	901		T2	7345		T3	13787
auto[0]	auto[IdleSt]	20444721	1			T1	1294		T2	6957		T3	4203
auto[0]	auto[ClkMuxSt]	32858	1			T1	10		T2	83		T4	77
auto[0]	auto[CntIncrSt]	32548	1			T1	10		T2	83		T4	72
auto[0]	auto[CntProgSt]	1744984	1			T1	251		T2	37694		T4	2977
auto[0]	auto[TransCheckSt]	25419	1			T1	10		T2	83		T4	59
auto[0]	auto[TokenHashSt]	33058961	1			T1	184		T2	7629		T4	190996
auto[0]	auto[FlashRmaSt]	30664	1			T1	58		T4	54		T11	10
auto[0]	auto[TokenCheck0St]	11121	1			T1	10		T4	18		T11	10
auto[0]	auto[TokenCheck1St]	8045	1			T1	10		T4	14		T11	10
auto[0]	auto[TransProgSt]	391451	1			T1	204		T4	695		T11	109
auto[0]	auto[PostTransSt]	12265377	1			T1	1303		T2	14467		T4	10011
auto[0]	auto[ScrapSt]	127731	1			T3	367		T4	714		T16	1445
auto[0]	auto[EscalateSt]	4642386	1			T4	46314		T5	9366		T14	2782
auto[0]	auto[InvalidSt]	9355993	1			T3	6226		T4	165902		T5	8659
auto[1]	auto[ResetSt]	161	1			T38	4		T49	1		T51	2
auto[1]	auto[IdleSt]	120	1			T49	5		T52	10		T53	4
auto[1]	auto[ClkMuxSt]	43	1			T38	2		T49	2		T50	1
auto[1]	auto[CntIncrSt]	42	1			T38	1		T51	1		T50	2
auto[1]	auto[CntProgSt]	683	1			T38	6		T49	11		T51	12
auto[1]	auto[TransCheckSt]	72	1			T38	3		T57	2		T56	2
auto[1]	auto[TokenHashSt]	504	1			T38	21		T49	6		T51	10
auto[1]	auto[FlashRmaSt]	75	1			T49	1		T51	1		T52	1
auto[1]	auto[TokenCheck0St]	17	1			T55	1		T56	2		T202	1
auto[1]	auto[TokenCheck1St]	75	1			T38	3		T49	1		T51	1
auto[1]	auto[TransProgSt]	474	1			T38	6		T49	7		T51	16
auto[1]	auto[PostTransSt]	2291	1			T4	4		T14	8		T15	5
auto[1]	auto[ScrapSt]	43	1			T38	1		T51	2		T52	2
auto[1]	auto[EscalateSt]	1254900	1			T4	6631		T5	388		T14	1960
auto[1]	auto[InvalidSt]	6159	1			T4	64		T5	4		T14	12

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6506101	1			T1	901		T2	7345		T3	13787
auto[0]	auto[IdleSt]	20444724	1			T1	1294		T2	6957		T3	4203
auto[0]	auto[ClkMuxSt]	32846	1			T1	10		T2	83		T4	77
auto[0]	auto[CntIncrSt]	32549	1			T1	10		T2	83		T4	72
auto[0]	auto[CntProgSt]	1744985	1			T1	251		T2	37694		T4	2977
auto[0]	auto[TransCheckSt]	25412	1			T1	10		T2	83		T4	59
auto[0]	auto[TokenHashSt]	33058976	1			T1	184		T2	7629		T4	190996
auto[0]	auto[FlashRmaSt]	30665	1			T1	58		T4	54		T11	10
auto[0]	auto[TokenCheck0St]	11120	1			T1	10		T4	18		T11	10
auto[0]	auto[TokenCheck1St]	8026	1			T1	10		T4	14		T11	10
auto[0]	auto[TransProgSt]	391487	1			T1	204		T4	695		T11	109
auto[0]	auto[PostTransSt]	12265360	1			T1	1303		T2	14467		T4	10011
auto[0]	auto[ScrapSt]	127734	1			T3	367		T4	714		T16	1445
auto[0]	auto[EscalateSt]	4646328	1			T4	47005		T5	9560		T14	3076
auto[0]	auto[InvalidSt]	9356102	1			T3	6226		T4	165909		T5	8661
auto[1]	auto[ResetSt]	186	1			T38	6		T49	3		T51	6
auto[1]	auto[IdleSt]	117	1			T49	7		T52	6		T53	4
auto[1]	auto[ClkMuxSt]	55	1			T38	1		T50	1		T52	2
auto[1]	auto[CntIncrSt]	41	1			T38	2		T49	2		T51	1
auto[1]	auto[CntProgSt]	682	1			T38	4		T49	13		T51	21
auto[1]	auto[TransCheckSt]	79	1			T38	5		T57	3		T56	3
auto[1]	auto[TokenHashSt]	489	1			T38	17		T49	5		T51	7
auto[1]	auto[FlashRmaSt]	74	1			T38	1		T51	2		T55	2
auto[1]	auto[TokenCheck0St]	18	1			T50	1		T55	3		T56	1
auto[1]	auto[TokenCheck1St]	94	1			T38	1		T49	1		T51	3
auto[1]	auto[TransProgSt]	438	1			T38	6		T49	5		T51	9
auto[1]	auto[PostTransSt]	2308	1			T4	4		T14	6		T15	6
auto[1]	auto[ScrapSt]	40	1			T38	3		T51	1		T52	1
auto[1]	auto[EscalateSt]	1250958	1			T4	5940		T5	194		T14	1666
auto[1]	auto[InvalidSt]	6050	1			T4	57		T5	2		T14	11