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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.19 97.99 95.77 93.40 100.00 98.55 98.51 96.11


Total test records in report: 987
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T812 /workspace/coverage/default/13.lc_ctrl_sec_token_digest.4210724992 Jul 15 05:28:22 PM PDT 24 Jul 15 05:28:36 PM PDT 24 1417053435 ps
T813 /workspace/coverage/default/35.lc_ctrl_sec_token_mux.4145706574 Jul 15 05:30:07 PM PDT 24 Jul 15 05:30:15 PM PDT 24 234351963 ps
T814 /workspace/coverage/default/49.lc_ctrl_security_escalation.3492433589 Jul 15 05:31:08 PM PDT 24 Jul 15 05:31:17 PM PDT 24 344837073 ps
T815 /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.502902988 Jul 15 05:31:06 PM PDT 24 Jul 15 05:31:08 PM PDT 24 40897416 ps
T816 /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.740104102 Jul 15 05:27:20 PM PDT 24 Jul 15 05:27:35 PM PDT 24 516537406 ps
T817 /workspace/coverage/default/1.lc_ctrl_state_failure.2194873191 Jul 15 05:26:41 PM PDT 24 Jul 15 05:27:03 PM PDT 24 468122424 ps
T818 /workspace/coverage/default/15.lc_ctrl_sec_mubi.2429686123 Jul 15 05:28:36 PM PDT 24 Jul 15 05:28:50 PM PDT 24 5077391091 ps
T819 /workspace/coverage/default/9.lc_ctrl_alert_test.2923524298 Jul 15 05:27:59 PM PDT 24 Jul 15 05:28:01 PM PDT 24 44251166 ps
T820 /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3389923697 Jul 15 05:28:23 PM PDT 24 Jul 15 05:28:28 PM PDT 24 124390871 ps
T821 /workspace/coverage/default/31.lc_ctrl_sec_token_mux.293353674 Jul 15 05:29:50 PM PDT 24 Jul 15 05:29:59 PM PDT 24 1986213282 ps
T822 /workspace/coverage/default/27.lc_ctrl_sec_mubi.2364017360 Jul 15 05:29:33 PM PDT 24 Jul 15 05:29:43 PM PDT 24 5098984568 ps
T823 /workspace/coverage/default/30.lc_ctrl_stress_all.2921255373 Jul 15 05:29:50 PM PDT 24 Jul 15 05:30:27 PM PDT 24 1330580358 ps
T824 /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1729506951 Jul 15 05:28:09 PM PDT 24 Jul 15 05:28:41 PM PDT 24 3780264795 ps
T825 /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1344666483 Jul 15 05:27:49 PM PDT 24 Jul 15 05:27:51 PM PDT 24 43076801 ps
T826 /workspace/coverage/default/0.lc_ctrl_errors.1813699850 Jul 15 05:26:32 PM PDT 24 Jul 15 05:26:46 PM PDT 24 525202077 ps
T827 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.472340105 Jul 15 05:30:51 PM PDT 24 Jul 15 05:31:06 PM PDT 24 2739607363 ps
T828 /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.412921024 Jul 15 05:27:33 PM PDT 24 Jul 15 05:28:31 PM PDT 24 1619282112 ps
T829 /workspace/coverage/default/12.lc_ctrl_errors.183348709 Jul 15 05:28:12 PM PDT 24 Jul 15 05:28:31 PM PDT 24 1618137672 ps
T830 /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3280909306 Jul 15 05:30:20 PM PDT 24 Jul 15 05:30:22 PM PDT 24 14489426 ps
T831 /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3801360662 Jul 15 05:28:49 PM PDT 24 Jul 15 05:28:57 PM PDT 24 1579704975 ps
T832 /workspace/coverage/default/2.lc_ctrl_regwen_during_op.779098922 Jul 15 05:26:48 PM PDT 24 Jul 15 05:26:56 PM PDT 24 415249262 ps
T199 /workspace/coverage/default/8.lc_ctrl_claim_transition_if.302524100 Jul 15 05:27:42 PM PDT 24 Jul 15 05:27:44 PM PDT 24 25268276 ps
T833 /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3873944560 Jul 15 05:30:13 PM PDT 24 Jul 15 05:30:27 PM PDT 24 761230463 ps
T834 /workspace/coverage/default/19.lc_ctrl_state_failure.2231723155 Jul 15 05:28:54 PM PDT 24 Jul 15 05:29:17 PM PDT 24 156543397 ps
T835 /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3487426330 Jul 15 05:28:58 PM PDT 24 Jul 15 05:29:08 PM PDT 24 461576248 ps
T836 /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.4045477328 Jul 15 05:26:50 PM PDT 24 Jul 15 05:27:33 PM PDT 24 3121559460 ps
T837 /workspace/coverage/default/6.lc_ctrl_claim_transition_if.92880830 Jul 15 05:27:26 PM PDT 24 Jul 15 05:27:28 PM PDT 24 34124089 ps
T838 /workspace/coverage/default/40.lc_ctrl_errors.811751205 Jul 15 05:30:29 PM PDT 24 Jul 15 05:30:39 PM PDT 24 1316368732 ps
T839 /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1805444606 Jul 15 05:28:29 PM PDT 24 Jul 15 05:29:19 PM PDT 24 8617377265 ps
T840 /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.2809648757 Jul 15 05:29:59 PM PDT 24 Jul 15 05:44:49 PM PDT 24 106166210609 ps
T841 /workspace/coverage/default/7.lc_ctrl_state_post_trans.1110658953 Jul 15 05:27:35 PM PDT 24 Jul 15 05:27:44 PM PDT 24 263301136 ps
T842 /workspace/coverage/default/13.lc_ctrl_jtag_errors.244027154 Jul 15 05:28:20 PM PDT 24 Jul 15 05:29:08 PM PDT 24 2182153796 ps
T843 /workspace/coverage/default/40.lc_ctrl_state_failure.4052673926 Jul 15 05:30:30 PM PDT 24 Jul 15 05:30:59 PM PDT 24 1094217780 ps
T844 /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2305660410 Jul 15 05:29:12 PM PDT 24 Jul 15 05:29:14 PM PDT 24 15733226 ps
T845 /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.627514374 Jul 15 05:28:45 PM PDT 24 Jul 15 05:28:46 PM PDT 24 21236826 ps
T846 /workspace/coverage/default/49.lc_ctrl_jtag_access.1160591742 Jul 15 05:31:06 PM PDT 24 Jul 15 05:31:09 PM PDT 24 40105646 ps
T847 /workspace/coverage/default/25.lc_ctrl_state_failure.400567787 Jul 15 05:29:27 PM PDT 24 Jul 15 05:29:50 PM PDT 24 954322109 ps
T848 /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3201916604 Jul 15 05:27:48 PM PDT 24 Jul 15 05:29:03 PM PDT 24 3436838090 ps
T849 /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.164321105 Jul 15 05:26:32 PM PDT 24 Jul 15 05:26:47 PM PDT 24 2780599822 ps
T850 /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3518560464 Jul 15 05:30:28 PM PDT 24 Jul 15 05:30:41 PM PDT 24 2188410262 ps
T851 /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.484703760 Jul 15 05:28:59 PM PDT 24 Jul 15 05:29:00 PM PDT 24 22672424 ps
T852 /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3531647348 Jul 15 05:28:23 PM PDT 24 Jul 15 05:28:25 PM PDT 24 42275150 ps
T853 /workspace/coverage/default/1.lc_ctrl_sec_token_digest.822718626 Jul 15 05:26:39 PM PDT 24 Jul 15 05:26:52 PM PDT 24 402192903 ps
T854 /workspace/coverage/default/11.lc_ctrl_state_failure.2141306891 Jul 15 05:28:05 PM PDT 24 Jul 15 05:28:21 PM PDT 24 750870895 ps
T855 /workspace/coverage/default/32.lc_ctrl_prog_failure.1341381478 Jul 15 05:29:58 PM PDT 24 Jul 15 05:30:01 PM PDT 24 33619380 ps
T856 /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2130530014 Jul 15 05:27:18 PM PDT 24 Jul 15 05:27:28 PM PDT 24 386170594 ps
T857 /workspace/coverage/default/10.lc_ctrl_sec_mubi.3361432210 Jul 15 05:28:01 PM PDT 24 Jul 15 05:28:12 PM PDT 24 519538777 ps
T858 /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1381034616 Jul 15 05:26:58 PM PDT 24 Jul 15 05:27:14 PM PDT 24 368376731 ps
T859 /workspace/coverage/default/28.lc_ctrl_state_post_trans.3592504066 Jul 15 05:29:42 PM PDT 24 Jul 15 05:29:47 PM PDT 24 79665262 ps
T860 /workspace/coverage/default/5.lc_ctrl_prog_failure.2019376087 Jul 15 05:27:11 PM PDT 24 Jul 15 05:27:13 PM PDT 24 53177147 ps
T861 /workspace/coverage/default/21.lc_ctrl_prog_failure.2872165772 Jul 15 05:29:03 PM PDT 24 Jul 15 05:29:06 PM PDT 24 112575646 ps
T862 /workspace/coverage/default/38.lc_ctrl_state_post_trans.2284307299 Jul 15 05:30:21 PM PDT 24 Jul 15 05:30:31 PM PDT 24 105262307 ps
T102 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1239345946 Jul 15 06:14:17 PM PDT 24 Jul 15 06:14:21 PM PDT 24 266252349 ps
T114 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1414034853 Jul 15 06:14:38 PM PDT 24 Jul 15 06:14:40 PM PDT 24 103689067 ps
T115 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1585029247 Jul 15 06:14:31 PM PDT 24 Jul 15 06:14:33 PM PDT 24 296382914 ps
T110 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3541056107 Jul 15 06:14:17 PM PDT 24 Jul 15 06:14:19 PM PDT 24 47951614 ps
T198 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2364393975 Jul 15 06:14:44 PM PDT 24 Jul 15 06:14:46 PM PDT 24 25498820 ps
T103 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3593314446 Jul 15 06:14:42 PM PDT 24 Jul 15 06:14:46 PM PDT 24 41277922 ps
T111 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2776958586 Jul 15 06:14:28 PM PDT 24 Jul 15 06:14:29 PM PDT 24 31533395 ps
T138 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.427498465 Jul 15 06:14:19 PM PDT 24 Jul 15 06:14:20 PM PDT 24 25719929 ps
T147 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.22815419 Jul 15 06:14:10 PM PDT 24 Jul 15 06:14:11 PM PDT 24 107455335 ps
T193 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2597433021 Jul 15 06:14:19 PM PDT 24 Jul 15 06:14:21 PM PDT 24 24207941 ps
T112 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.327313122 Jul 15 06:14:36 PM PDT 24 Jul 15 06:14:38 PM PDT 24 100601896 ps
T104 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.710105969 Jul 15 06:14:43 PM PDT 24 Jul 15 06:14:47 PM PDT 24 201516043 ps
T107 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1516669040 Jul 15 06:14:44 PM PDT 24 Jul 15 06:14:47 PM PDT 24 448553731 ps
T179 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.961006853 Jul 15 06:14:53 PM PDT 24 Jul 15 06:14:55 PM PDT 24 44059370 ps
T148 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3681575370 Jul 15 06:14:19 PM PDT 24 Jul 15 06:14:21 PM PDT 24 188053980 ps
T194 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2794418001 Jul 15 06:14:18 PM PDT 24 Jul 15 06:14:20 PM PDT 24 40518837 ps
T108 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1449583421 Jul 15 06:14:29 PM PDT 24 Jul 15 06:14:33 PM PDT 24 98379675 ps
T109 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.4288443663 Jul 15 06:14:43 PM PDT 24 Jul 15 06:14:46 PM PDT 24 45645158 ps
T149 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.4101206419 Jul 15 06:14:52 PM PDT 24 Jul 15 06:14:54 PM PDT 24 67906690 ps
T139 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2943712291 Jul 15 06:14:31 PM PDT 24 Jul 15 06:14:34 PM PDT 24 246753011 ps
T116 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2464012870 Jul 15 06:14:29 PM PDT 24 Jul 15 06:14:32 PM PDT 24 53970615 ps
T136 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3355022189 Jul 15 06:14:20 PM PDT 24 Jul 15 06:14:23 PM PDT 24 58302977 ps
T118 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3366464496 Jul 15 06:14:38 PM PDT 24 Jul 15 06:14:42 PM PDT 24 47200175 ps
T195 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1479675190 Jul 15 06:14:38 PM PDT 24 Jul 15 06:14:40 PM PDT 24 45296281 ps
T172 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3913706398 Jul 15 06:14:42 PM PDT 24 Jul 15 06:14:45 PM PDT 24 79894351 ps
T129 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3754998750 Jul 15 06:14:28 PM PDT 24 Jul 15 06:14:32 PM PDT 24 130792631 ps
T119 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1789548025 Jul 15 06:14:20 PM PDT 24 Jul 15 06:14:26 PM PDT 24 133959100 ps
T133 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.830167202 Jul 15 06:14:38 PM PDT 24 Jul 15 06:14:42 PM PDT 24 297166877 ps
T196 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1177636973 Jul 15 06:14:40 PM PDT 24 Jul 15 06:14:42 PM PDT 24 71435073 ps
T863 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2311362798 Jul 15 06:14:39 PM PDT 24 Jul 15 06:14:42 PM PDT 24 58292712 ps
T137 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1368192090 Jul 15 06:14:18 PM PDT 24 Jul 15 06:14:21 PM PDT 24 284098883 ps
T173 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2078335170 Jul 15 06:14:41 PM PDT 24 Jul 15 06:14:43 PM PDT 24 15258394 ps
T864 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2316143575 Jul 15 06:14:32 PM PDT 24 Jul 15 06:14:34 PM PDT 24 76150292 ps
T865 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2860672716 Jul 15 06:14:39 PM PDT 24 Jul 15 06:14:43 PM PDT 24 311211971 ps
T866 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3684637167 Jul 15 06:14:25 PM PDT 24 Jul 15 06:14:27 PM PDT 24 17474885 ps
T180 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3690539191 Jul 15 06:14:42 PM PDT 24 Jul 15 06:14:43 PM PDT 24 55628295 ps
T867 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3368637589 Jul 15 06:14:24 PM PDT 24 Jul 15 06:14:26 PM PDT 24 172112384 ps
T181 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3734307480 Jul 15 06:14:26 PM PDT 24 Jul 15 06:14:28 PM PDT 24 32940706 ps
T134 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2557901237 Jul 15 06:14:11 PM PDT 24 Jul 15 06:14:15 PM PDT 24 441713070 ps
T868 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.4170546417 Jul 15 06:14:40 PM PDT 24 Jul 15 06:14:43 PM PDT 24 90641672 ps
T869 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3957020099 Jul 15 06:14:52 PM PDT 24 Jul 15 06:14:54 PM PDT 24 262373471 ps
T870 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.144713657 Jul 15 06:14:19 PM PDT 24 Jul 15 06:14:22 PM PDT 24 191963352 ps
T871 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3946116328 Jul 15 06:14:37 PM PDT 24 Jul 15 06:14:39 PM PDT 24 48336771 ps
T872 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2822613826 Jul 15 06:14:52 PM PDT 24 Jul 15 06:14:57 PM PDT 24 309587322 ps
T873 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.809115757 Jul 15 06:14:31 PM PDT 24 Jul 15 06:14:34 PM PDT 24 14544533 ps
T874 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2072617403 Jul 15 06:14:45 PM PDT 24 Jul 15 06:14:47 PM PDT 24 21376876 ps
T875 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3908587365 Jul 15 06:14:35 PM PDT 24 Jul 15 06:14:37 PM PDT 24 37592916 ps
T876 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3305952937 Jul 15 06:14:31 PM PDT 24 Jul 15 06:14:34 PM PDT 24 98637466 ps
T877 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1906746288 Jul 15 06:14:25 PM PDT 24 Jul 15 06:14:27 PM PDT 24 45520395 ps
T878 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.71301555 Jul 15 06:14:34 PM PDT 24 Jul 15 06:14:43 PM PDT 24 663269420 ps
T879 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1859851588 Jul 15 06:14:37 PM PDT 24 Jul 15 06:14:38 PM PDT 24 112060358 ps
T201 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.964125598 Jul 15 06:14:15 PM PDT 24 Jul 15 06:14:17 PM PDT 24 291041690 ps
T880 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1654201968 Jul 15 06:14:37 PM PDT 24 Jul 15 06:14:40 PM PDT 24 123980365 ps
T124 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2861461289 Jul 15 06:14:39 PM PDT 24 Jul 15 06:14:43 PM PDT 24 73054107 ps
T881 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2730511826 Jul 15 06:14:46 PM PDT 24 Jul 15 06:14:48 PM PDT 24 50176854 ps
T882 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.734695289 Jul 15 06:14:14 PM PDT 24 Jul 15 06:14:15 PM PDT 24 49297517 ps
T123 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.562275623 Jul 15 06:14:39 PM PDT 24 Jul 15 06:14:43 PM PDT 24 163688104 ps
T883 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1124186089 Jul 15 06:14:16 PM PDT 24 Jul 15 06:14:18 PM PDT 24 157975956 ps
T884 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3860397971 Jul 15 06:14:33 PM PDT 24 Jul 15 06:14:35 PM PDT 24 224457632 ps
T885 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3404583355 Jul 15 06:14:27 PM PDT 24 Jul 15 06:14:32 PM PDT 24 150758092 ps
T886 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.246323487 Jul 15 06:14:10 PM PDT 24 Jul 15 06:14:12 PM PDT 24 52793089 ps
T887 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3301568234 Jul 15 06:14:16 PM PDT 24 Jul 15 06:14:20 PM PDT 24 77908456 ps
T888 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.343135671 Jul 15 06:14:19 PM PDT 24 Jul 15 06:14:20 PM PDT 24 56930879 ps
T135 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3945359446 Jul 15 06:14:39 PM PDT 24 Jul 15 06:14:43 PM PDT 24 289086435 ps
T889 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3367103591 Jul 15 06:14:16 PM PDT 24 Jul 15 06:14:18 PM PDT 24 17483902 ps
T890 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.598923482 Jul 15 06:14:35 PM PDT 24 Jul 15 06:14:40 PM PDT 24 778085077 ps
T891 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1746276394 Jul 15 06:14:38 PM PDT 24 Jul 15 06:14:43 PM PDT 24 106351348 ps
T892 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.832450736 Jul 15 06:14:11 PM PDT 24 Jul 15 06:14:13 PM PDT 24 343504395 ps
T893 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3315971264 Jul 15 06:14:18 PM PDT 24 Jul 15 06:14:20 PM PDT 24 61662429 ps
T894 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2930097554 Jul 15 06:14:53 PM PDT 24 Jul 15 06:14:56 PM PDT 24 138906929 ps
T895 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3284472160 Jul 15 06:14:37 PM PDT 24 Jul 15 06:14:49 PM PDT 24 487973734 ps
T182 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2881599635 Jul 15 06:14:34 PM PDT 24 Jul 15 06:14:36 PM PDT 24 255657214 ps
T896 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2848345827 Jul 15 06:14:35 PM PDT 24 Jul 15 06:14:37 PM PDT 24 22589424 ps
T897 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1724099833 Jul 15 06:14:17 PM PDT 24 Jul 15 06:14:21 PM PDT 24 118757938 ps
T898 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2997020478 Jul 15 06:14:30 PM PDT 24 Jul 15 06:14:32 PM PDT 24 87482572 ps
T899 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3501271418 Jul 15 06:14:37 PM PDT 24 Jul 15 06:14:39 PM PDT 24 22045644 ps
T900 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2399536783 Jul 15 06:14:17 PM PDT 24 Jul 15 06:14:19 PM PDT 24 19001572 ps
T901 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1489054755 Jul 15 06:14:37 PM PDT 24 Jul 15 06:14:39 PM PDT 24 47116901 ps
T117 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.986753572 Jul 15 06:14:45 PM PDT 24 Jul 15 06:14:48 PM PDT 24 288943770 ps
T902 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.4062166571 Jul 15 06:14:36 PM PDT 24 Jul 15 06:14:42 PM PDT 24 489137557 ps
T132 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1829006344 Jul 15 06:14:17 PM PDT 24 Jul 15 06:14:20 PM PDT 24 113241123 ps
T903 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3154519733 Jul 15 06:14:20 PM PDT 24 Jul 15 06:14:22 PM PDT 24 47119254 ps
T904 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1513667763 Jul 15 06:14:26 PM PDT 24 Jul 15 06:14:32 PM PDT 24 830969414 ps
T905 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4109601076 Jul 15 06:14:39 PM PDT 24 Jul 15 06:14:51 PM PDT 24 2168410507 ps
T906 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1024936815 Jul 15 06:14:30 PM PDT 24 Jul 15 06:14:35 PM PDT 24 931042362 ps
T907 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.4192812023 Jul 15 06:14:24 PM PDT 24 Jul 15 06:14:26 PM PDT 24 22537504 ps
T908 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3931405977 Jul 15 06:14:43 PM PDT 24 Jul 15 06:14:45 PM PDT 24 52938175 ps
T909 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3385351741 Jul 15 06:14:40 PM PDT 24 Jul 15 06:14:45 PM PDT 24 119440183 ps
T910 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1201690019 Jul 15 06:14:30 PM PDT 24 Jul 15 06:14:32 PM PDT 24 51785476 ps
T911 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1741610090 Jul 15 06:14:18 PM PDT 24 Jul 15 06:14:20 PM PDT 24 251265434 ps
T912 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1567866822 Jul 15 06:14:39 PM PDT 24 Jul 15 06:14:43 PM PDT 24 120182008 ps
T183 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3666670482 Jul 15 06:14:23 PM PDT 24 Jul 15 06:14:24 PM PDT 24 29975688 ps
T913 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1483223490 Jul 15 06:14:21 PM PDT 24 Jul 15 06:14:24 PM PDT 24 196737139 ps
T914 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.4181044711 Jul 15 06:14:45 PM PDT 24 Jul 15 06:14:47 PM PDT 24 93736389 ps
T915 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2917556665 Jul 15 06:14:43 PM PDT 24 Jul 15 06:14:45 PM PDT 24 35430565 ps
T916 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4035605519 Jul 15 06:14:45 PM PDT 24 Jul 15 06:14:49 PM PDT 24 85578773 ps
T917 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1381468032 Jul 15 06:14:17 PM PDT 24 Jul 15 06:14:20 PM PDT 24 822784860 ps
T131 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1155583888 Jul 15 06:14:51 PM PDT 24 Jul 15 06:14:54 PM PDT 24 367896302 ps
T918 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2258780291 Jul 15 06:14:17 PM PDT 24 Jul 15 06:14:19 PM PDT 24 160278249 ps
T919 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3830032914 Jul 15 06:14:39 PM PDT 24 Jul 15 06:14:42 PM PDT 24 19485351 ps
T126 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2115080305 Jul 15 06:14:44 PM PDT 24 Jul 15 06:14:49 PM PDT 24 2044053148 ps
T920 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3404400320 Jul 15 06:14:38 PM PDT 24 Jul 15 06:14:40 PM PDT 24 38880849 ps
T130 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.572428782 Jul 15 06:14:38 PM PDT 24 Jul 15 06:14:43 PM PDT 24 107260257 ps
T921 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.356834096 Jul 15 06:14:43 PM PDT 24 Jul 15 06:14:46 PM PDT 24 68632432 ps
T922 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4032133604 Jul 15 06:14:39 PM PDT 24 Jul 15 06:14:43 PM PDT 24 609600292 ps
T923 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.718326252 Jul 15 06:14:37 PM PDT 24 Jul 15 06:14:49 PM PDT 24 5232904017 ps
T924 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.221800351 Jul 15 06:14:40 PM PDT 24 Jul 15 06:14:46 PM PDT 24 516914263 ps
T925 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.4096266458 Jul 15 06:14:46 PM PDT 24 Jul 15 06:14:47 PM PDT 24 26876886 ps
T926 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1120684077 Jul 15 06:14:39 PM PDT 24 Jul 15 06:14:41 PM PDT 24 95413878 ps
T927 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.178310525 Jul 15 06:14:19 PM PDT 24 Jul 15 06:14:23 PM PDT 24 309207366 ps
T928 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3706867892 Jul 15 06:14:42 PM PDT 24 Jul 15 06:14:58 PM PDT 24 2432930041 ps
T929 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.989319244 Jul 15 06:14:22 PM PDT 24 Jul 15 06:14:26 PM PDT 24 172630434 ps
T930 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1678570449 Jul 15 06:14:47 PM PDT 24 Jul 15 06:14:49 PM PDT 24 39008968 ps
T931 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.144036197 Jul 15 06:14:31 PM PDT 24 Jul 15 06:14:34 PM PDT 24 239859619 ps
T184 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3797997711 Jul 15 06:14:32 PM PDT 24 Jul 15 06:14:34 PM PDT 24 12153471 ps
T932 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.36421464 Jul 15 06:14:20 PM PDT 24 Jul 15 06:14:21 PM PDT 24 18034440 ps
T933 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.4107443184 Jul 15 06:14:13 PM PDT 24 Jul 15 06:14:21 PM PDT 24 1326010604 ps
T934 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.838910681 Jul 15 06:14:31 PM PDT 24 Jul 15 06:14:34 PM PDT 24 44998138 ps
T185 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1911930853 Jul 15 06:14:37 PM PDT 24 Jul 15 06:14:39 PM PDT 24 44649625 ps
T935 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.303401198 Jul 15 06:14:53 PM PDT 24 Jul 15 06:14:56 PM PDT 24 21894612 ps
T936 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3128038464 Jul 15 06:14:43 PM PDT 24 Jul 15 06:14:45 PM PDT 24 15100951 ps
T186 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.758765601 Jul 15 06:14:23 PM PDT 24 Jul 15 06:14:25 PM PDT 24 18847047 ps
T937 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2407425848 Jul 15 06:14:30 PM PDT 24 Jul 15 06:14:32 PM PDT 24 179194795 ps
T187 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3200806911 Jul 15 06:14:43 PM PDT 24 Jul 15 06:14:45 PM PDT 24 116380014 ps
T938 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2795577041 Jul 15 06:14:38 PM PDT 24 Jul 15 06:14:41 PM PDT 24 23076149 ps
T939 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4069512785 Jul 15 06:14:18 PM PDT 24 Jul 15 06:14:32 PM PDT 24 631340270 ps
T191 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.459860620 Jul 15 06:14:31 PM PDT 24 Jul 15 06:14:33 PM PDT 24 32706218 ps
T940 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.763582992 Jul 15 06:14:30 PM PDT 24 Jul 15 06:14:36 PM PDT 24 911319543 ps
T941 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.137734629 Jul 15 06:14:35 PM PDT 24 Jul 15 06:14:36 PM PDT 24 17623082 ps
T942 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1235797452 Jul 15 06:14:23 PM PDT 24 Jul 15 06:14:29 PM PDT 24 2002433325 ps
T943 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.151023545 Jul 15 06:14:30 PM PDT 24 Jul 15 06:14:37 PM PDT 24 488025871 ps
T944 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1506391988 Jul 15 06:14:38 PM PDT 24 Jul 15 06:14:41 PM PDT 24 42610048 ps
T945 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3966341854 Jul 15 06:14:45 PM PDT 24 Jul 15 06:14:47 PM PDT 24 241737328 ps
T946 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2968040134 Jul 15 06:14:39 PM PDT 24 Jul 15 06:14:42 PM PDT 24 62594806 ps
T947 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2945056325 Jul 15 06:14:31 PM PDT 24 Jul 15 06:14:34 PM PDT 24 120404226 ps
T948 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2797026354 Jul 15 06:14:31 PM PDT 24 Jul 15 06:14:33 PM PDT 24 101062748 ps
T949 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3497606897 Jul 15 06:14:37 PM PDT 24 Jul 15 06:14:41 PM PDT 24 120577689 ps
T950 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2610474178 Jul 15 06:14:37 PM PDT 24 Jul 15 06:14:41 PM PDT 24 110051690 ps
T188 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2844248807 Jul 15 06:14:16 PM PDT 24 Jul 15 06:14:19 PM PDT 24 35584322 ps
T951 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3727451870 Jul 15 06:14:17 PM PDT 24 Jul 15 06:14:19 PM PDT 24 13586507 ps
T952 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2144136560 Jul 15 06:14:16 PM PDT 24 Jul 15 06:14:48 PM PDT 24 7861206547 ps
T120 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.228352478 Jul 15 06:14:28 PM PDT 24 Jul 15 06:14:30 PM PDT 24 65079123 ps
T953 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.657682239 Jul 15 06:14:36 PM PDT 24 Jul 15 06:14:37 PM PDT 24 102258200 ps
T954 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2409411589 Jul 15 06:14:35 PM PDT 24 Jul 15 06:14:37 PM PDT 24 55092856 ps
T127 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2438834913 Jul 15 06:14:51 PM PDT 24 Jul 15 06:14:54 PM PDT 24 67259762 ps
T121 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.592106960 Jul 15 06:14:43 PM PDT 24 Jul 15 06:14:46 PM PDT 24 122189208 ps
T125 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4153470226 Jul 15 06:14:39 PM PDT 24 Jul 15 06:14:42 PM PDT 24 58719392 ps
T122 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2900289191 Jul 15 06:14:42 PM PDT 24 Jul 15 06:14:46 PM PDT 24 288607165 ps
T955 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4083909731 Jul 15 06:14:17 PM PDT 24 Jul 15 06:14:19 PM PDT 24 108940367 ps
T956 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2477175731 Jul 15 06:14:38 PM PDT 24 Jul 15 06:14:41 PM PDT 24 61138435 ps
T957 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.514294759 Jul 15 06:14:38 PM PDT 24 Jul 15 06:14:41 PM PDT 24 63765293 ps
T958 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3760003110 Jul 15 06:14:36 PM PDT 24 Jul 15 06:14:38 PM PDT 24 46190719 ps
T959 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.230479180 Jul 15 06:14:18 PM PDT 24 Jul 15 06:14:20 PM PDT 24 27413520 ps
T960 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2373660099 Jul 15 06:14:39 PM PDT 24 Jul 15 06:14:42 PM PDT 24 336275911 ps
T961 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3875025772 Jul 15 06:14:45 PM PDT 24 Jul 15 06:14:47 PM PDT 24 66448173 ps
T962 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2786192287 Jul 15 06:14:26 PM PDT 24 Jul 15 06:14:28 PM PDT 24 211696574 ps
T963 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.757682978 Jul 15 06:14:46 PM PDT 24 Jul 15 06:14:48 PM PDT 24 16031451 ps
T964 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2048436878 Jul 15 06:14:42 PM PDT 24 Jul 15 06:14:45 PM PDT 24 176008774 ps
T965 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.399040945 Jul 15 06:14:12 PM PDT 24 Jul 15 06:15:02 PM PDT 24 25460847852 ps
T966 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.969236831 Jul 15 06:14:11 PM PDT 24 Jul 15 06:14:13 PM PDT 24 20121662 ps
T967 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3092284240 Jul 15 06:14:23 PM PDT 24 Jul 15 06:14:24 PM PDT 24 494061787 ps
T968 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.79795197 Jul 15 06:14:38 PM PDT 24 Jul 15 06:14:40 PM PDT 24 16951305 ps
T192 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.265334560 Jul 15 06:14:20 PM PDT 24 Jul 15 06:14:22 PM PDT 24 52254296 ps
T969 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3222465267 Jul 15 06:14:22 PM PDT 24 Jul 15 06:14:24 PM PDT 24 36178304 ps
T128 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1656589235 Jul 15 06:14:15 PM PDT 24 Jul 15 06:14:17 PM PDT 24 222783642 ps
T970 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1869842199 Jul 15 06:14:51 PM PDT 24 Jul 15 06:14:52 PM PDT 24 111827704 ps
T971 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2016439465 Jul 15 06:14:24 PM PDT 24 Jul 15 06:14:28 PM PDT 24 824553597 ps
T189 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3877387112 Jul 15 06:14:39 PM PDT 24 Jul 15 06:14:41 PM PDT 24 12617645 ps
T972 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2916754043 Jul 15 06:14:26 PM PDT 24 Jul 15 06:14:28 PM PDT 24 60454944 ps
T973 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1617663076 Jul 15 06:14:24 PM PDT 24 Jul 15 06:14:28 PM PDT 24 377693476 ps
T974 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2551635334 Jul 15 06:14:13 PM PDT 24 Jul 15 06:14:14 PM PDT 24 32848584 ps
T975 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2240584878 Jul 15 06:14:44 PM PDT 24 Jul 15 06:14:46 PM PDT 24 68078911 ps
T976 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2521090522 Jul 15 06:14:39 PM PDT 24 Jul 15 06:14:42 PM PDT 24 21715778 ps
T977 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1654731878 Jul 15 06:14:24 PM PDT 24 Jul 15 06:14:26 PM PDT 24 156621103 ps
T978 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2557386770 Jul 15 06:14:39 PM PDT 24 Jul 15 06:14:45 PM PDT 24 368408505 ps
T979 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.227865605 Jul 15 06:14:23 PM PDT 24 Jul 15 06:14:25 PM PDT 24 63368183 ps
T980 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.9344078 Jul 15 06:14:28 PM PDT 24 Jul 15 06:15:02 PM PDT 24 3045650438 ps
T981 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4040027946 Jul 15 06:14:37 PM PDT 24 Jul 15 06:14:39 PM PDT 24 29145657 ps
T982 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1035841342 Jul 15 06:14:44 PM PDT 24 Jul 15 06:14:47 PM PDT 24 164163297 ps
T983 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3647322995 Jul 15 06:14:42 PM PDT 24 Jul 15 06:14:45 PM PDT 24 23720141 ps
T984 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3088365249 Jul 15 06:14:39 PM PDT 24 Jul 15 06:14:41 PM PDT 24 31149567 ps
T985 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1441090253 Jul 15 06:14:32 PM PDT 24 Jul 15 06:14:36 PM PDT 24 303495259 ps
T986 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2715362964 Jul 15 06:14:30 PM PDT 24 Jul 15 06:14:33 PM PDT 24 40087028 ps
T190 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2028810803 Jul 15 06:14:14 PM PDT 24 Jul 15 06:14:16 PM PDT 24 15498075 ps
T987 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3621000113 Jul 15 06:14:18 PM PDT 24 Jul 15 06:14:26 PM PDT 24 652384130 ps

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.3659243902
Short name T4
Test name
Test status
Simulation time 21897389329 ps
CPU time 137.51 seconds
Started Jul 15 05:30:38 PM PDT 24
Finished Jul 15 05:32:57 PM PDT 24
Peak memory 283184 kb
Host smart-1744d58e-15e7-43b8-90f3-4f0fa217242b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659243902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.3659243902
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.1159868634
Short name T20
Test name
Test status
Simulation time 13424863773 ps
CPU time 575.65 seconds
Started Jul 15 05:27:20 PM PDT 24
Finished Jul 15 05:36:56 PM PDT 24
Peak memory 496188 kb
Host smart-df8bbe1d-62ad-4068-acf4-c629836b1c40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1159868634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.1159868634
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2173437430
Short name T38
Test name
Test status
Simulation time 2208156136 ps
CPU time 11.15 seconds
Started Jul 15 05:28:57 PM PDT 24
Finished Jul 15 05:29:09 PM PDT 24
Peak memory 217868 kb
Host smart-ddc96a92-92ef-4660-87d8-c48d7cd64ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173437430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2173437430
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2713178648
Short name T14
Test name
Test status
Simulation time 311017214 ps
CPU time 13.14 seconds
Started Jul 15 05:28:08 PM PDT 24
Finished Jul 15 05:28:21 PM PDT 24
Peak memory 225480 kb
Host smart-928ebb45-f060-486a-b822-f0d3aa02ab73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713178648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2713178648
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.740580179
Short name T46
Test name
Test status
Simulation time 12038718941 ps
CPU time 331 seconds
Started Jul 15 05:28:24 PM PDT 24
Finished Jul 15 05:33:55 PM PDT 24
Peak memory 283304 kb
Host smart-5e91095b-e5b3-4e11-adb7-9b8f985333be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=740580179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.740580179
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3810609492
Short name T3
Test name
Test status
Simulation time 251067112 ps
CPU time 35.49 seconds
Started Jul 15 05:26:54 PM PDT 24
Finished Jul 15 05:27:30 PM PDT 24
Peak memory 269456 kb
Host smart-aaf82894-1297-4763-adf8-4db5e20bcd1f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810609492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3810609492
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2592263684
Short name T34
Test name
Test status
Simulation time 13965770 ps
CPU time 0.81 seconds
Started Jul 15 05:28:53 PM PDT 24
Finished Jul 15 05:28:54 PM PDT 24
Peak memory 208496 kb
Host smart-e6840328-8077-4d84-a426-6cc309b9ed7b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592263684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2592263684
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1990874117
Short name T202
Test name
Test status
Simulation time 638627862 ps
CPU time 9.75 seconds
Started Jul 15 05:28:10 PM PDT 24
Finished Jul 15 05:28:20 PM PDT 24
Peak memory 224324 kb
Host smart-c9c4d205-9c58-45b1-a647-ab1bbf1cb724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990874117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1990874117
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3593314446
Short name T103
Test name
Test status
Simulation time 41277922 ps
CPU time 2.86 seconds
Started Jul 15 06:14:42 PM PDT 24
Finished Jul 15 06:14:46 PM PDT 24
Peak memory 217528 kb
Host smart-b68bebfa-2aea-4ee6-8b50-aad8de71a985
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593314446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3593314446
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1516669040
Short name T107
Test name
Test status
Simulation time 448553731 ps
CPU time 3.01 seconds
Started Jul 15 06:14:44 PM PDT 24
Finished Jul 15 06:14:47 PM PDT 24
Peak memory 222436 kb
Host smart-3cc81c21-218b-4be2-90b6-7e2ed29b7368
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516669040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1516669040
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.915392212
Short name T6
Test name
Test status
Simulation time 1175132683 ps
CPU time 3.98 seconds
Started Jul 15 05:27:26 PM PDT 24
Finished Jul 15 05:27:30 PM PDT 24
Peak memory 216848 kb
Host smart-a391c91f-e98d-4422-90b1-6d9829862709
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915392212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.915392212
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.1061966872
Short name T160
Test name
Test status
Simulation time 10274608623 ps
CPU time 60.28 seconds
Started Jul 15 05:28:48 PM PDT 24
Finished Jul 15 05:29:49 PM PDT 24
Peak memory 250464 kb
Host smart-2dc8eb1f-02cd-48dd-839e-a4078cf39226
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061966872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.1061966872
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.433667114
Short name T265
Test name
Test status
Simulation time 380796471 ps
CPU time 10.77 seconds
Started Jul 15 05:26:39 PM PDT 24
Finished Jul 15 05:26:51 PM PDT 24
Peak memory 217680 kb
Host smart-f2546ce3-253a-44ae-bccd-965a3113292b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433667114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.433667114
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3608915447
Short name T10
Test name
Test status
Simulation time 19220522 ps
CPU time 1.13 seconds
Started Jul 15 05:30:04 PM PDT 24
Finished Jul 15 05:30:06 PM PDT 24
Peak memory 208492 kb
Host smart-9b9856c1-f179-485c-8401-31c527990223
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608915447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3608915447
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3690539191
Short name T180
Test name
Test status
Simulation time 55628295 ps
CPU time 0.87 seconds
Started Jul 15 06:14:42 PM PDT 24
Finished Jul 15 06:14:43 PM PDT 24
Peak memory 208944 kb
Host smart-7888fe2a-f54a-4d9d-9e09-d2ea72dd8c7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690539191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3690539191
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2557901237
Short name T134
Test name
Test status
Simulation time 441713070 ps
CPU time 3.86 seconds
Started Jul 15 06:14:11 PM PDT 24
Finished Jul 15 06:14:15 PM PDT 24
Peak memory 223440 kb
Host smart-04f8defa-4953-4a58-befa-1e3ea76318ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255790
1237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2557901237
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.562275623
Short name T123
Test name
Test status
Simulation time 163688104 ps
CPU time 2.21 seconds
Started Jul 15 06:14:39 PM PDT 24
Finished Jul 15 06:14:43 PM PDT 24
Peak memory 221828 kb
Host smart-e35b7f22-034c-42d1-80e2-55456d200aa1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562275623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_e
rr.562275623
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.253880311
Short name T96
Test name
Test status
Simulation time 13668395921 ps
CPU time 537.19 seconds
Started Jul 15 05:30:03 PM PDT 24
Finished Jul 15 05:39:01 PM PDT 24
Peak memory 283276 kb
Host smart-1f1d71a2-b981-43f3-abf8-e34e0bd7e544
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=253880311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.253880311
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.51945044
Short name T162
Test name
Test status
Simulation time 34395550311 ps
CPU time 516.93 seconds
Started Jul 15 05:26:41 PM PDT 24
Finished Jul 15 05:35:19 PM PDT 24
Peak memory 283476 kb
Host smart-e2986b13-cc8f-4877-8c3e-e5d42a2b4d24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=51945044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.51945044
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2115080305
Short name T126
Test name
Test status
Simulation time 2044053148 ps
CPU time 4.84 seconds
Started Jul 15 06:14:44 PM PDT 24
Finished Jul 15 06:14:49 PM PDT 24
Peak memory 217420 kb
Host smart-763d0502-8f10-433f-9b34-d47e8bd07dae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115080305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2115080305
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2861461289
Short name T124
Test name
Test status
Simulation time 73054107 ps
CPU time 2.8 seconds
Started Jul 15 06:14:39 PM PDT 24
Finished Jul 15 06:14:43 PM PDT 24
Peak memory 217432 kb
Host smart-045e1e6a-ee8c-4cb1-94d4-d6a2fb95b798
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861461289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2861461289
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3566540884
Short name T91
Test name
Test status
Simulation time 130157675 ps
CPU time 7 seconds
Started Jul 15 05:29:57 PM PDT 24
Finished Jul 15 05:30:05 PM PDT 24
Peak memory 250424 kb
Host smart-9f94098a-d804-4fa9-9bc7-0abe3ef89b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566540884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3566540884
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2438834913
Short name T127
Test name
Test status
Simulation time 67259762 ps
CPU time 2.89 seconds
Started Jul 15 06:14:51 PM PDT 24
Finished Jul 15 06:14:54 PM PDT 24
Peak memory 217468 kb
Host smart-d210d4fb-fc51-4580-948b-506eaff7b07d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438834913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2438834913
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3754998750
Short name T129
Test name
Test status
Simulation time 130792631 ps
CPU time 3.74 seconds
Started Jul 15 06:14:28 PM PDT 24
Finished Jul 15 06:14:32 PM PDT 24
Peak memory 217444 kb
Host smart-1d8cebd9-db54-4304-b732-5000e40ccac1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754998750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3754998750
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.22815419
Short name T147
Test name
Test status
Simulation time 107455335 ps
CPU time 1.12 seconds
Started Jul 15 06:14:10 PM PDT 24
Finished Jul 15 06:14:11 PM PDT 24
Peak memory 209196 kb
Host smart-ee0d7a68-5d92-47e5-aade-deb969acb99e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22815419 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.22815419
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.592106960
Short name T121
Test name
Test status
Simulation time 122189208 ps
CPU time 1.89 seconds
Started Jul 15 06:14:43 PM PDT 24
Finished Jul 15 06:14:46 PM PDT 24
Peak memory 222036 kb
Host smart-95423158-4d68-48d3-9e00-96543f44d685
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592106960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.592106960
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.572428782
Short name T130
Test name
Test status
Simulation time 107260257 ps
CPU time 3.96 seconds
Started Jul 15 06:14:38 PM PDT 24
Finished Jul 15 06:14:43 PM PDT 24
Peak memory 217412 kb
Host smart-0372c0dc-08e5-4593-aca3-6df33a914666
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572428782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.572428782
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.4062340472
Short name T777
Test name
Test status
Simulation time 893197321 ps
CPU time 13.95 seconds
Started Jul 15 05:26:33 PM PDT 24
Finished Jul 15 05:26:48 PM PDT 24
Peak memory 225432 kb
Host smart-e4850147-b3a9-4cf3-aa4d-81d92e8c1a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062340472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.4062340472
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.531655200
Short name T200
Test name
Test status
Simulation time 11079814 ps
CPU time 0.95 seconds
Started Jul 15 05:26:55 PM PDT 24
Finished Jul 15 05:26:57 PM PDT 24
Peak memory 208372 kb
Host smart-d0dae217-50ba-4b65-875e-e26cc26b0583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531655200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.531655200
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1684284620
Short name T73
Test name
Test status
Simulation time 15861311 ps
CPU time 0.95 seconds
Started Jul 15 05:27:04 PM PDT 24
Finished Jul 15 05:27:05 PM PDT 24
Peak memory 208332 kb
Host smart-744b1a66-9da0-4453-9b64-54ad48672226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684284620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1684284620
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.302524100
Short name T199
Test name
Test status
Simulation time 25268276 ps
CPU time 0.86 seconds
Started Jul 15 05:27:42 PM PDT 24
Finished Jul 15 05:27:44 PM PDT 24
Peak memory 208236 kb
Host smart-d0c0cbc4-8f2c-47d2-b6b3-4c87a542c39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302524100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.302524100
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1633269434
Short name T272
Test name
Test status
Simulation time 10368802966 ps
CPU time 72.94 seconds
Started Jul 15 05:27:59 PM PDT 24
Finished Jul 15 05:29:13 PM PDT 24
Peak memory 282968 kb
Host smart-b672d3be-2861-45ca-b066-ec58dbcedc60
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633269434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1633269434
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3150158448
Short name T18
Test name
Test status
Simulation time 1825846036 ps
CPU time 27.27 seconds
Started Jul 15 05:26:39 PM PDT 24
Finished Jul 15 05:27:07 PM PDT 24
Peak memory 217020 kb
Host smart-8c319cb1-2539-4f73-9efe-52f5328d208b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150158448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3150158448
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1449583421
Short name T108
Test name
Test status
Simulation time 98379675 ps
CPU time 4.07 seconds
Started Jul 15 06:14:29 PM PDT 24
Finished Jul 15 06:14:33 PM PDT 24
Peak memory 217564 kb
Host smart-7e474fd6-d522-4b1d-ab3e-cf0f6735c9e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449583421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1449583421
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.228352478
Short name T120
Test name
Test status
Simulation time 65079123 ps
CPU time 1.93 seconds
Started Jul 15 06:14:28 PM PDT 24
Finished Jul 15 06:14:30 PM PDT 24
Peak memory 221876 kb
Host smart-bd18ce62-ea31-49e2-a13b-d805ce4a2236
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228352478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.228352478
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1649507775
Short name T44
Test name
Test status
Simulation time 20976850419 ps
CPU time 457.87 seconds
Started Jul 15 05:28:00 PM PDT 24
Finished Jul 15 05:35:38 PM PDT 24
Peak memory 302712 kb
Host smart-8db40836-7655-4871-899c-b6b7c87085bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649507775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1649507775
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2461099103
Short name T5
Test name
Test status
Simulation time 1265514148 ps
CPU time 15.79 seconds
Started Jul 15 05:26:39 PM PDT 24
Finished Jul 15 05:26:56 PM PDT 24
Peak memory 250364 kb
Host smart-a16970a7-732f-4209-99bc-bc5d09c71062
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461099103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2461099103
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2844248807
Short name T188
Test name
Test status
Simulation time 35584322 ps
CPU time 1.64 seconds
Started Jul 15 06:14:16 PM PDT 24
Finished Jul 15 06:14:19 PM PDT 24
Peak memory 209228 kb
Host smart-54ea15f8-3adb-4426-8994-d65bfdd4743f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844248807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2844248807
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2551635334
Short name T974
Test name
Test status
Simulation time 32848584 ps
CPU time 1.15 seconds
Started Jul 15 06:14:13 PM PDT 24
Finished Jul 15 06:14:14 PM PDT 24
Peak memory 209128 kb
Host smart-53190403-4f33-4d3a-972d-eed1ab3278f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551635334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2551635334
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.969236831
Short name T966
Test name
Test status
Simulation time 20121662 ps
CPU time 1 seconds
Started Jul 15 06:14:11 PM PDT 24
Finished Jul 15 06:14:13 PM PDT 24
Peak memory 210304 kb
Host smart-6acd9f58-664d-42dd-b93d-5f1cf9f942a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969236831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.969236831
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.36421464
Short name T932
Test name
Test status
Simulation time 18034440 ps
CPU time 1.24 seconds
Started Jul 15 06:14:20 PM PDT 24
Finished Jul 15 06:14:21 PM PDT 24
Peak memory 217132 kb
Host smart-7ebb308f-dd92-4d91-ac45-193c608b54c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36421464 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.36421464
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2028810803
Short name T190
Test name
Test status
Simulation time 15498075 ps
CPU time 0.84 seconds
Started Jul 15 06:14:14 PM PDT 24
Finished Jul 15 06:14:16 PM PDT 24
Peak memory 209236 kb
Host smart-859d2abb-143c-4083-972c-9c2b8bb49467
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028810803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2028810803
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.832450736
Short name T892
Test name
Test status
Simulation time 343504395 ps
CPU time 1.08 seconds
Started Jul 15 06:14:11 PM PDT 24
Finished Jul 15 06:14:13 PM PDT 24
Peak memory 209108 kb
Host smart-0fc7578f-9e50-4ada-9da9-61b5ae248115
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832450736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.832450736
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.4107443184
Short name T933
Test name
Test status
Simulation time 1326010604 ps
CPU time 7.41 seconds
Started Jul 15 06:14:13 PM PDT 24
Finished Jul 15 06:14:21 PM PDT 24
Peak memory 209024 kb
Host smart-dc4dbc5c-a700-4e38-a5d5-3e1483df9bc9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107443184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.4107443184
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.399040945
Short name T965
Test name
Test status
Simulation time 25460847852 ps
CPU time 49.1 seconds
Started Jul 15 06:14:12 PM PDT 24
Finished Jul 15 06:15:02 PM PDT 24
Peak memory 217224 kb
Host smart-700a7845-fa90-4d83-8c0a-83b4699a5c9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399040945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.399040945
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.734695289
Short name T882
Test name
Test status
Simulation time 49297517 ps
CPU time 1.28 seconds
Started Jul 15 06:14:14 PM PDT 24
Finished Jul 15 06:14:15 PM PDT 24
Peak memory 210456 kb
Host smart-e22fa792-2cac-42d0-9c90-1d44b50aefd0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734695289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.734695289
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1124186089
Short name T883
Test name
Test status
Simulation time 157975956 ps
CPU time 1.53 seconds
Started Jul 15 06:14:16 PM PDT 24
Finished Jul 15 06:14:18 PM PDT 24
Peak memory 209232 kb
Host smart-c3d78a5a-fb39-475a-9fe9-7ef466866f96
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124186089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1124186089
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3315971264
Short name T893
Test name
Test status
Simulation time 61662429 ps
CPU time 0.99 seconds
Started Jul 15 06:14:18 PM PDT 24
Finished Jul 15 06:14:20 PM PDT 24
Peak memory 217480 kb
Host smart-4a476ffc-07c7-4f32-b973-5425d230f7a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315971264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3315971264
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.246323487
Short name T886
Test name
Test status
Simulation time 52793089 ps
CPU time 1.69 seconds
Started Jul 15 06:14:10 PM PDT 24
Finished Jul 15 06:14:12 PM PDT 24
Peak memory 217420 kb
Host smart-a3be965e-712a-4e1e-bbe2-4bb698563f7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246323487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.246323487
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.964125598
Short name T201
Test name
Test status
Simulation time 291041690 ps
CPU time 1.86 seconds
Started Jul 15 06:14:15 PM PDT 24
Finished Jul 15 06:14:17 PM PDT 24
Peak memory 222000 kb
Host smart-bfe41c9f-146d-47c9-999d-b161b944d165
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964125598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.964125598
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3222465267
Short name T969
Test name
Test status
Simulation time 36178304 ps
CPU time 1.49 seconds
Started Jul 15 06:14:22 PM PDT 24
Finished Jul 15 06:14:24 PM PDT 24
Peak memory 217416 kb
Host smart-a3511671-a718-4160-b0aa-4074754c559a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222465267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3222465267
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.265334560
Short name T192
Test name
Test status
Simulation time 52254296 ps
CPU time 1.64 seconds
Started Jul 15 06:14:20 PM PDT 24
Finished Jul 15 06:14:22 PM PDT 24
Peak memory 216960 kb
Host smart-7a9e4125-3c30-41a2-9885-f63838adbaea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265334560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.265334560
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4083909731
Short name T955
Test name
Test status
Simulation time 108940367 ps
CPU time 0.92 seconds
Started Jul 15 06:14:17 PM PDT 24
Finished Jul 15 06:14:19 PM PDT 24
Peak memory 209844 kb
Host smart-25b0a36e-cce7-4a23-83b0-5dcf77289dce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083909731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.4083909731
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3681575370
Short name T148
Test name
Test status
Simulation time 188053980 ps
CPU time 1.21 seconds
Started Jul 15 06:14:19 PM PDT 24
Finished Jul 15 06:14:21 PM PDT 24
Peak memory 217500 kb
Host smart-5d45bd6a-2b42-4357-9621-6111b1b93310
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681575370 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3681575370
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.230479180
Short name T959
Test name
Test status
Simulation time 27413520 ps
CPU time 1.07 seconds
Started Jul 15 06:14:18 PM PDT 24
Finished Jul 15 06:14:20 PM PDT 24
Peak memory 208932 kb
Host smart-33c1a17b-676a-4df9-9674-29854d9c1512
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230479180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.230479180
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1741610090
Short name T911
Test name
Test status
Simulation time 251265434 ps
CPU time 1.3 seconds
Started Jul 15 06:14:18 PM PDT 24
Finished Jul 15 06:14:20 PM PDT 24
Peak memory 208620 kb
Host smart-b58a55da-6c1f-4f4a-9202-a127d77da930
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741610090 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1741610090
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.144713657
Short name T870
Test name
Test status
Simulation time 191963352 ps
CPU time 2.83 seconds
Started Jul 15 06:14:19 PM PDT 24
Finished Jul 15 06:14:22 PM PDT 24
Peak memory 216876 kb
Host smart-d2fb2b63-a675-43b0-9968-28dd81f7408c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144713657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.144713657
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4069512785
Short name T939
Test name
Test status
Simulation time 631340270 ps
CPU time 13.18 seconds
Started Jul 15 06:14:18 PM PDT 24
Finished Jul 15 06:14:32 PM PDT 24
Peak memory 208860 kb
Host smart-474bf328-ab8a-4ec4-bb91-8885437e0dd7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069512785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.4069512785
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1368192090
Short name T137
Test name
Test status
Simulation time 284098883 ps
CPU time 1.89 seconds
Started Jul 15 06:14:18 PM PDT 24
Finished Jul 15 06:14:21 PM PDT 24
Peak memory 210600 kb
Host smart-ad0597a2-7a6b-4fca-a951-eac052006950
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368192090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1368192090
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1483223490
Short name T913
Test name
Test status
Simulation time 196737139 ps
CPU time 2.82 seconds
Started Jul 15 06:14:21 PM PDT 24
Finished Jul 15 06:14:24 PM PDT 24
Peak memory 223360 kb
Host smart-bb311f7a-7032-439d-8598-3cf05ba0a9df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148322
3490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1483223490
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2258780291
Short name T918
Test name
Test status
Simulation time 160278249 ps
CPU time 2.03 seconds
Started Jul 15 06:14:17 PM PDT 24
Finished Jul 15 06:14:19 PM PDT 24
Peak memory 209120 kb
Host smart-9826d482-3135-42c8-aff9-b5bad8c2846b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258780291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2258780291
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2597433021
Short name T193
Test name
Test status
Simulation time 24207941 ps
CPU time 1.06 seconds
Started Jul 15 06:14:19 PM PDT 24
Finished Jul 15 06:14:21 PM PDT 24
Peak memory 209252 kb
Host smart-38f2eec8-7f3b-43ce-8c53-348b85e2e2d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597433021 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2597433021
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.343135671
Short name T888
Test name
Test status
Simulation time 56930879 ps
CPU time 1.15 seconds
Started Jul 15 06:14:19 PM PDT 24
Finished Jul 15 06:14:20 PM PDT 24
Peak memory 209188 kb
Host smart-ee1b4a14-573c-40a6-8fe9-030861cda902
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343135671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.343135671
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1239345946
Short name T102
Test name
Test status
Simulation time 266252349 ps
CPU time 3.33 seconds
Started Jul 15 06:14:17 PM PDT 24
Finished Jul 15 06:14:21 PM PDT 24
Peak memory 217544 kb
Host smart-3d7693cc-4643-43e6-af44-c7717b8c3b79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239345946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1239345946
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1656589235
Short name T128
Test name
Test status
Simulation time 222783642 ps
CPU time 1.86 seconds
Started Jul 15 06:14:15 PM PDT 24
Finished Jul 15 06:14:17 PM PDT 24
Peak memory 221680 kb
Host smart-b479f748-4360-41a6-a251-2af47968bdba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656589235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1656589235
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1859851588
Short name T879
Test name
Test status
Simulation time 112060358 ps
CPU time 1.13 seconds
Started Jul 15 06:14:37 PM PDT 24
Finished Jul 15 06:14:38 PM PDT 24
Peak memory 218624 kb
Host smart-11a47960-e975-4da0-a2e0-c2c79459d904
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859851588 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1859851588
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.79795197
Short name T968
Test name
Test status
Simulation time 16951305 ps
CPU time 0.89 seconds
Started Jul 15 06:14:38 PM PDT 24
Finished Jul 15 06:14:40 PM PDT 24
Peak memory 209176 kb
Host smart-09b6bc27-7130-4224-b0de-f8bf4dbcbed5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79795197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.79795197
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.327313122
Short name T112
Test name
Test status
Simulation time 100601896 ps
CPU time 1.41 seconds
Started Jul 15 06:14:36 PM PDT 24
Finished Jul 15 06:14:38 PM PDT 24
Peak memory 209224 kb
Host smart-e10b4935-c9e2-4b54-8d6e-cf3c1b2c0dd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327313122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.327313122
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3913706398
Short name T172
Test name
Test status
Simulation time 79894351 ps
CPU time 1.48 seconds
Started Jul 15 06:14:42 PM PDT 24
Finished Jul 15 06:14:45 PM PDT 24
Peak memory 217872 kb
Host smart-e0290490-b041-4e93-9b57-44bb2f6c3fd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913706398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3913706398
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.4288443663
Short name T109
Test name
Test status
Simulation time 45645158 ps
CPU time 2.34 seconds
Started Jul 15 06:14:43 PM PDT 24
Finished Jul 15 06:14:46 PM PDT 24
Peak memory 221960 kb
Host smart-de0ceb39-b99b-4ff6-8660-9d354d53ec8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288443663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.4288443663
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3088365249
Short name T984
Test name
Test status
Simulation time 31149567 ps
CPU time 1.16 seconds
Started Jul 15 06:14:39 PM PDT 24
Finished Jul 15 06:14:41 PM PDT 24
Peak memory 217492 kb
Host smart-382f8f27-03a9-4e4b-a2e1-4ebde6f3a812
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088365249 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3088365249
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3501271418
Short name T899
Test name
Test status
Simulation time 22045644 ps
CPU time 0.85 seconds
Started Jul 15 06:14:37 PM PDT 24
Finished Jul 15 06:14:39 PM PDT 24
Peak memory 209108 kb
Host smart-10617b61-a62c-4a40-8632-70bf4b3566dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501271418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3501271418
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1120684077
Short name T926
Test name
Test status
Simulation time 95413878 ps
CPU time 1.11 seconds
Started Jul 15 06:14:39 PM PDT 24
Finished Jul 15 06:14:41 PM PDT 24
Peak memory 209192 kb
Host smart-8be39dbc-0aee-43d2-8e26-43636274a340
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120684077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1120684077
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2610474178
Short name T950
Test name
Test status
Simulation time 110051690 ps
CPU time 2.42 seconds
Started Jul 15 06:14:37 PM PDT 24
Finished Jul 15 06:14:41 PM PDT 24
Peak memory 217228 kb
Host smart-caa1702d-7ecb-4a61-b40c-f89225ca0063
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610474178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2610474178
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3366464496
Short name T118
Test name
Test status
Simulation time 47200175 ps
CPU time 2.2 seconds
Started Jul 15 06:14:38 PM PDT 24
Finished Jul 15 06:14:42 PM PDT 24
Peak memory 221912 kb
Host smart-460c4034-c908-4acc-9bab-617b92dfbc10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366464496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3366464496
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2968040134
Short name T946
Test name
Test status
Simulation time 62594806 ps
CPU time 1.24 seconds
Started Jul 15 06:14:39 PM PDT 24
Finished Jul 15 06:14:42 PM PDT 24
Peak memory 218700 kb
Host smart-444e5e52-f9a6-4e42-83d1-7ce77949a509
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968040134 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2968040134
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2311362798
Short name T863
Test name
Test status
Simulation time 58292712 ps
CPU time 1.12 seconds
Started Jul 15 06:14:39 PM PDT 24
Finished Jul 15 06:14:42 PM PDT 24
Peak memory 209232 kb
Host smart-88df7bfe-0bb1-45ab-9e38-2c8d3734cdd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311362798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2311362798
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1479675190
Short name T195
Test name
Test status
Simulation time 45296281 ps
CPU time 1.08 seconds
Started Jul 15 06:14:38 PM PDT 24
Finished Jul 15 06:14:40 PM PDT 24
Peak memory 209192 kb
Host smart-5b474e21-d357-43d8-9d6f-c66d0db7d124
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479675190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1479675190
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4032133604
Short name T922
Test name
Test status
Simulation time 609600292 ps
CPU time 2.91 seconds
Started Jul 15 06:14:39 PM PDT 24
Finished Jul 15 06:14:43 PM PDT 24
Peak memory 218548 kb
Host smart-adfa960a-0f64-480e-b738-b3c2e23a14b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032133604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.4032133604
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2078335170
Short name T173
Test name
Test status
Simulation time 15258394 ps
CPU time 1.12 seconds
Started Jul 15 06:14:41 PM PDT 24
Finished Jul 15 06:14:43 PM PDT 24
Peak memory 219176 kb
Host smart-76f3d1eb-94d0-4368-8aff-ae384856b5ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078335170 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2078335170
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2072617403
Short name T874
Test name
Test status
Simulation time 21376876 ps
CPU time 1.41 seconds
Started Jul 15 06:14:45 PM PDT 24
Finished Jul 15 06:14:47 PM PDT 24
Peak memory 209296 kb
Host smart-43170d11-e531-4c3e-8391-05629a0da162
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072617403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2072617403
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3647322995
Short name T983
Test name
Test status
Simulation time 23720141 ps
CPU time 1.49 seconds
Started Jul 15 06:14:42 PM PDT 24
Finished Jul 15 06:14:45 PM PDT 24
Peak memory 217492 kb
Host smart-c3d4eae0-0af7-4683-9ab7-897f589bf979
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647322995 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3647322995
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2364393975
Short name T198
Test name
Test status
Simulation time 25498820 ps
CPU time 1.02 seconds
Started Jul 15 06:14:44 PM PDT 24
Finished Jul 15 06:14:46 PM PDT 24
Peak memory 209180 kb
Host smart-696008dc-1c98-4623-a0b6-a62e92b82134
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364393975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2364393975
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.4181044711
Short name T914
Test name
Test status
Simulation time 93736389 ps
CPU time 1.45 seconds
Started Jul 15 06:14:45 PM PDT 24
Finished Jul 15 06:14:47 PM PDT 24
Peak memory 209236 kb
Host smart-cce4cabc-66c6-4d4a-ba70-1ae9f5a2d66c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181044711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.4181044711
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4035605519
Short name T916
Test name
Test status
Simulation time 85578773 ps
CPU time 2.72 seconds
Started Jul 15 06:14:45 PM PDT 24
Finished Jul 15 06:14:49 PM PDT 24
Peak memory 218620 kb
Host smart-29c631d1-e8e4-4b86-8685-00280dbaedcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035605519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.4035605519
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2900289191
Short name T122
Test name
Test status
Simulation time 288607165 ps
CPU time 3.25 seconds
Started Jul 15 06:14:42 PM PDT 24
Finished Jul 15 06:14:46 PM PDT 24
Peak memory 217436 kb
Host smart-00d8e6de-55d9-4f8b-b452-2b800398d765
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900289191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2900289191
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1678570449
Short name T930
Test name
Test status
Simulation time 39008968 ps
CPU time 1.59 seconds
Started Jul 15 06:14:47 PM PDT 24
Finished Jul 15 06:14:49 PM PDT 24
Peak memory 221420 kb
Host smart-7322c886-a80f-42d2-aba1-664fd14abd18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678570449 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1678570449
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.757682978
Short name T963
Test name
Test status
Simulation time 16031451 ps
CPU time 1.07 seconds
Started Jul 15 06:14:46 PM PDT 24
Finished Jul 15 06:14:48 PM PDT 24
Peak memory 209132 kb
Host smart-0dbd8156-f17c-4a21-9307-63ecdb47e0e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757682978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.757682978
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.4096266458
Short name T925
Test name
Test status
Simulation time 26876886 ps
CPU time 1.1 seconds
Started Jul 15 06:14:46 PM PDT 24
Finished Jul 15 06:14:47 PM PDT 24
Peak memory 209108 kb
Host smart-0f53fb66-b929-4319-adf4-29159ac14537
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096266458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.4096266458
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3966341854
Short name T945
Test name
Test status
Simulation time 241737328 ps
CPU time 1.71 seconds
Started Jul 15 06:14:45 PM PDT 24
Finished Jul 15 06:14:47 PM PDT 24
Peak memory 217488 kb
Host smart-b6a85f9c-2a55-461e-b023-03f6f7297ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966341854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3966341854
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.986753572
Short name T117
Test name
Test status
Simulation time 288943770 ps
CPU time 2 seconds
Started Jul 15 06:14:45 PM PDT 24
Finished Jul 15 06:14:48 PM PDT 24
Peak memory 221880 kb
Host smart-e53b012a-bd96-4dc9-b9e4-10cf74f05358
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986753572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_
err.986753572
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3875025772
Short name T961
Test name
Test status
Simulation time 66448173 ps
CPU time 1.03 seconds
Started Jul 15 06:14:45 PM PDT 24
Finished Jul 15 06:14:47 PM PDT 24
Peak memory 217512 kb
Host smart-e98eef39-5ec7-4f3a-9156-a1497204421c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875025772 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3875025772
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3128038464
Short name T936
Test name
Test status
Simulation time 15100951 ps
CPU time 0.91 seconds
Started Jul 15 06:14:43 PM PDT 24
Finished Jul 15 06:14:45 PM PDT 24
Peak memory 209276 kb
Host smart-2a9373a2-c698-4a44-b4cb-b55ef0b23f10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128038464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3128038464
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2917556665
Short name T915
Test name
Test status
Simulation time 35430565 ps
CPU time 1.17 seconds
Started Jul 15 06:14:43 PM PDT 24
Finished Jul 15 06:14:45 PM PDT 24
Peak memory 211296 kb
Host smart-b3e692ff-1284-4801-86e7-47c56df5ce9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917556665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2917556665
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2730511826
Short name T881
Test name
Test status
Simulation time 50176854 ps
CPU time 1.72 seconds
Started Jul 15 06:14:46 PM PDT 24
Finished Jul 15 06:14:48 PM PDT 24
Peak memory 217464 kb
Host smart-0c4e6b64-971f-400d-b6c4-1abd808c88c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730511826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2730511826
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.356834096
Short name T921
Test name
Test status
Simulation time 68632432 ps
CPU time 1.98 seconds
Started Jul 15 06:14:43 PM PDT 24
Finished Jul 15 06:14:46 PM PDT 24
Peak memory 221588 kb
Host smart-67c18877-0120-46e0-8505-92aebac34453
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356834096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.356834096
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2240584878
Short name T975
Test name
Test status
Simulation time 68078911 ps
CPU time 1.25 seconds
Started Jul 15 06:14:44 PM PDT 24
Finished Jul 15 06:14:46 PM PDT 24
Peak memory 217552 kb
Host smart-207c72ce-3bf3-4b79-9d5c-ff94b09c30a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240584878 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2240584878
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3200806911
Short name T187
Test name
Test status
Simulation time 116380014 ps
CPU time 0.97 seconds
Started Jul 15 06:14:43 PM PDT 24
Finished Jul 15 06:14:45 PM PDT 24
Peak memory 209232 kb
Host smart-99843b62-6573-45c0-a7d9-e221acbd8214
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200806911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3200806911
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3931405977
Short name T908
Test name
Test status
Simulation time 52938175 ps
CPU time 1.11 seconds
Started Jul 15 06:14:43 PM PDT 24
Finished Jul 15 06:14:45 PM PDT 24
Peak memory 209232 kb
Host smart-34f72cc1-e3f0-4c61-a2b0-9033f5cf457f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931405977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3931405977
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1035841342
Short name T982
Test name
Test status
Simulation time 164163297 ps
CPU time 3.06 seconds
Started Jul 15 06:14:44 PM PDT 24
Finished Jul 15 06:14:47 PM PDT 24
Peak memory 217580 kb
Host smart-259baf27-aab8-4470-b6c8-d829b9034a98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035841342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1035841342
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.303401198
Short name T935
Test name
Test status
Simulation time 21894612 ps
CPU time 1.35 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:14:56 PM PDT 24
Peak memory 224724 kb
Host smart-43075cb6-9836-469d-813f-e1c6675aa9b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303401198 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.303401198
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.961006853
Short name T179
Test name
Test status
Simulation time 44059370 ps
CPU time 0.82 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:14:55 PM PDT 24
Peak memory 209116 kb
Host smart-eceb2ac9-80fe-4d64-9cd2-22780af30cd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961006853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.961006853
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3957020099
Short name T869
Test name
Test status
Simulation time 262373471 ps
CPU time 1.86 seconds
Started Jul 15 06:14:52 PM PDT 24
Finished Jul 15 06:14:54 PM PDT 24
Peak memory 211228 kb
Host smart-6bd1636a-9b15-4641-8692-5abc4f433051
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957020099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3957020099
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.710105969
Short name T104
Test name
Test status
Simulation time 201516043 ps
CPU time 2.96 seconds
Started Jul 15 06:14:43 PM PDT 24
Finished Jul 15 06:14:47 PM PDT 24
Peak memory 217568 kb
Host smart-d72e9e94-976b-4f9e-a5a7-c1afe907017f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710105969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.710105969
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.4101206419
Short name T149
Test name
Test status
Simulation time 67906690 ps
CPU time 1.25 seconds
Started Jul 15 06:14:52 PM PDT 24
Finished Jul 15 06:14:54 PM PDT 24
Peak memory 217448 kb
Host smart-ceaca1c2-3c3d-4315-a242-c4c403b38ff6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101206419 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.4101206419
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2930097554
Short name T894
Test name
Test status
Simulation time 138906929 ps
CPU time 0.99 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:14:56 PM PDT 24
Peak memory 209348 kb
Host smart-9b735fd5-8545-4c7b-bec6-b5916974f3fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930097554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2930097554
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1869842199
Short name T970
Test name
Test status
Simulation time 111827704 ps
CPU time 1.06 seconds
Started Jul 15 06:14:51 PM PDT 24
Finished Jul 15 06:14:52 PM PDT 24
Peak memory 209436 kb
Host smart-b733690c-44a5-4d75-9720-fa71c841076c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869842199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1869842199
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2822613826
Short name T872
Test name
Test status
Simulation time 309587322 ps
CPU time 2.2 seconds
Started Jul 15 06:14:52 PM PDT 24
Finished Jul 15 06:14:57 PM PDT 24
Peak memory 217436 kb
Host smart-52ee0acb-8ffd-4aa8-8612-58b2363bccad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822613826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2822613826
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1155583888
Short name T131
Test name
Test status
Simulation time 367896302 ps
CPU time 3.01 seconds
Started Jul 15 06:14:51 PM PDT 24
Finished Jul 15 06:14:54 PM PDT 24
Peak memory 222276 kb
Host smart-968abbc8-1c47-4a56-a962-21b10a55a64c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155583888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1155583888
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2399536783
Short name T900
Test name
Test status
Simulation time 19001572 ps
CPU time 0.96 seconds
Started Jul 15 06:14:17 PM PDT 24
Finished Jul 15 06:14:19 PM PDT 24
Peak memory 209196 kb
Host smart-d72f6596-add2-4a4b-87cc-7249c90fd2bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399536783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2399536783
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3301568234
Short name T887
Test name
Test status
Simulation time 77908456 ps
CPU time 2.56 seconds
Started Jul 15 06:14:16 PM PDT 24
Finished Jul 15 06:14:20 PM PDT 24
Peak memory 217328 kb
Host smart-111107ff-9450-4321-93ba-951fbbb05ef4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301568234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3301568234
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3154519733
Short name T903
Test name
Test status
Simulation time 47119254 ps
CPU time 0.91 seconds
Started Jul 15 06:14:20 PM PDT 24
Finished Jul 15 06:14:22 PM PDT 24
Peak memory 209840 kb
Host smart-28a04ecb-ade3-4470-afca-0a713d6076ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154519733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3154519733
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3367103591
Short name T889
Test name
Test status
Simulation time 17483902 ps
CPU time 1.45 seconds
Started Jul 15 06:14:16 PM PDT 24
Finished Jul 15 06:14:18 PM PDT 24
Peak memory 218620 kb
Host smart-dc06e824-fa13-4206-bde3-ec5bd2cb0324
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367103591 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3367103591
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3727451870
Short name T951
Test name
Test status
Simulation time 13586507 ps
CPU time 0.89 seconds
Started Jul 15 06:14:17 PM PDT 24
Finished Jul 15 06:14:19 PM PDT 24
Peak memory 209228 kb
Host smart-7d626571-8df3-40d0-a12b-e793e1a3edab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727451870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3727451870
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.427498465
Short name T138
Test name
Test status
Simulation time 25719929 ps
CPU time 0.99 seconds
Started Jul 15 06:14:19 PM PDT 24
Finished Jul 15 06:14:20 PM PDT 24
Peak memory 209060 kb
Host smart-5f6c8b3a-39ca-4605-8ccb-2c3a60f72635
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427498465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.427498465
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3621000113
Short name T987
Test name
Test status
Simulation time 652384130 ps
CPU time 7.33 seconds
Started Jul 15 06:14:18 PM PDT 24
Finished Jul 15 06:14:26 PM PDT 24
Peak memory 216836 kb
Host smart-6715259c-5582-4c61-83d0-5cd0e4aab855
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621000113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3621000113
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2144136560
Short name T952
Test name
Test status
Simulation time 7861206547 ps
CPU time 31.87 seconds
Started Jul 15 06:14:16 PM PDT 24
Finished Jul 15 06:14:48 PM PDT 24
Peak memory 209120 kb
Host smart-c8c2a2fe-1f6a-4238-ba64-bd0aa68f26dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144136560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2144136560
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1724099833
Short name T897
Test name
Test status
Simulation time 118757938 ps
CPU time 3.21 seconds
Started Jul 15 06:14:17 PM PDT 24
Finished Jul 15 06:14:21 PM PDT 24
Peak memory 217332 kb
Host smart-2c278577-7faa-4c77-a258-725ef0a428fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724099833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1724099833
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3355022189
Short name T136
Test name
Test status
Simulation time 58302977 ps
CPU time 2.2 seconds
Started Jul 15 06:14:20 PM PDT 24
Finished Jul 15 06:14:23 PM PDT 24
Peak memory 217600 kb
Host smart-2654da20-c13d-4b56-a933-c4366c1a48f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335502
2189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3355022189
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1381468032
Short name T917
Test name
Test status
Simulation time 822784860 ps
CPU time 1.86 seconds
Started Jul 15 06:14:17 PM PDT 24
Finished Jul 15 06:14:20 PM PDT 24
Peak memory 217100 kb
Host smart-1694e472-3cbb-43fa-8baa-cbc7b6f0f086
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381468032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1381468032
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3541056107
Short name T110
Test name
Test status
Simulation time 47951614 ps
CPU time 1.04 seconds
Started Jul 15 06:14:17 PM PDT 24
Finished Jul 15 06:14:19 PM PDT 24
Peak memory 217340 kb
Host smart-6eb56438-a693-48a0-8bb6-00ab914e3750
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541056107 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3541056107
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2794418001
Short name T194
Test name
Test status
Simulation time 40518837 ps
CPU time 1.39 seconds
Started Jul 15 06:14:18 PM PDT 24
Finished Jul 15 06:14:20 PM PDT 24
Peak memory 211332 kb
Host smart-b39ef5d8-d7ec-41ad-8b56-4395729de27c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794418001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2794418001
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1789548025
Short name T119
Test name
Test status
Simulation time 133959100 ps
CPU time 4.91 seconds
Started Jul 15 06:14:20 PM PDT 24
Finished Jul 15 06:14:26 PM PDT 24
Peak memory 217424 kb
Host smart-8fa4d433-6ed8-46b3-80e8-60af1aa4c6ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789548025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1789548025
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1829006344
Short name T132
Test name
Test status
Simulation time 113241123 ps
CPU time 1.82 seconds
Started Jul 15 06:14:17 PM PDT 24
Finished Jul 15 06:14:20 PM PDT 24
Peak memory 221160 kb
Host smart-fcd8eef9-1ce7-4295-92af-3214bf04c230
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829006344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1829006344
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3734307480
Short name T181
Test name
Test status
Simulation time 32940706 ps
CPU time 1.36 seconds
Started Jul 15 06:14:26 PM PDT 24
Finished Jul 15 06:14:28 PM PDT 24
Peak memory 209236 kb
Host smart-1d8fdba1-aab5-4104-9b38-2ac14d488269
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734307480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3734307480
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1585029247
Short name T115
Test name
Test status
Simulation time 296382914 ps
CPU time 1.56 seconds
Started Jul 15 06:14:31 PM PDT 24
Finished Jul 15 06:14:33 PM PDT 24
Peak memory 216964 kb
Host smart-acad5339-d5a6-4818-b4ba-f5bf5b680466
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585029247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1585029247
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3666670482
Short name T183
Test name
Test status
Simulation time 29975688 ps
CPU time 1.01 seconds
Started Jul 15 06:14:23 PM PDT 24
Finished Jul 15 06:14:24 PM PDT 24
Peak memory 209828 kb
Host smart-22074553-c588-4ffe-90ae-cf81d552eba2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666670482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3666670482
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1906746288
Short name T877
Test name
Test status
Simulation time 45520395 ps
CPU time 1.71 seconds
Started Jul 15 06:14:25 PM PDT 24
Finished Jul 15 06:14:27 PM PDT 24
Peak memory 222328 kb
Host smart-04aadb27-83fc-4c34-8167-655e3e431d56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906746288 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1906746288
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.459860620
Short name T191
Test name
Test status
Simulation time 32706218 ps
CPU time 0.99 seconds
Started Jul 15 06:14:31 PM PDT 24
Finished Jul 15 06:14:33 PM PDT 24
Peak memory 209188 kb
Host smart-b71af4f4-f10b-4dae-8136-1d10fc88015b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459860620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.459860620
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2786192287
Short name T962
Test name
Test status
Simulation time 211696574 ps
CPU time 1.78 seconds
Started Jul 15 06:14:26 PM PDT 24
Finished Jul 15 06:14:28 PM PDT 24
Peak memory 209084 kb
Host smart-0e645910-1b5d-4213-89ac-5495a182ca13
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786192287 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2786192287
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2016439465
Short name T971
Test name
Test status
Simulation time 824553597 ps
CPU time 2.97 seconds
Started Jul 15 06:14:24 PM PDT 24
Finished Jul 15 06:14:28 PM PDT 24
Peak memory 209200 kb
Host smart-8e4e2567-1e5a-4403-8f08-6017d6f5e9aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016439465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2016439465
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.9344078
Short name T980
Test name
Test status
Simulation time 3045650438 ps
CPU time 33.59 seconds
Started Jul 15 06:14:28 PM PDT 24
Finished Jul 15 06:15:02 PM PDT 24
Peak memory 209192 kb
Host smart-0dca1ca7-835f-4ee3-8376-889508bc4717
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9344078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base
_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.lc_ctrl_jtag_csr_bit_bash.9344078
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.178310525
Short name T927
Test name
Test status
Simulation time 309207366 ps
CPU time 2.66 seconds
Started Jul 15 06:14:19 PM PDT 24
Finished Jul 15 06:14:23 PM PDT 24
Peak memory 217380 kb
Host smart-1a27d430-0b03-4d2b-b899-3c604f6b5f3b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178310525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.178310525
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.989319244
Short name T929
Test name
Test status
Simulation time 172630434 ps
CPU time 3.34 seconds
Started Jul 15 06:14:22 PM PDT 24
Finished Jul 15 06:14:26 PM PDT 24
Peak memory 217556 kb
Host smart-ec56cd0f-21d0-4341-b579-84d6429b5f23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989319
244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.989319244
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3092284240
Short name T967
Test name
Test status
Simulation time 494061787 ps
CPU time 1.17 seconds
Started Jul 15 06:14:23 PM PDT 24
Finished Jul 15 06:14:24 PM PDT 24
Peak memory 209160 kb
Host smart-2592cc98-8767-496d-8ac6-e40ed8a9f510
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092284240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3092284240
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3684637167
Short name T866
Test name
Test status
Simulation time 17474885 ps
CPU time 1.03 seconds
Started Jul 15 06:14:25 PM PDT 24
Finished Jul 15 06:14:27 PM PDT 24
Peak memory 209240 kb
Host smart-f14aa754-cb15-4443-a645-0ef82102e791
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684637167 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3684637167
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.4192812023
Short name T907
Test name
Test status
Simulation time 22537504 ps
CPU time 1.53 seconds
Started Jul 15 06:14:24 PM PDT 24
Finished Jul 15 06:14:26 PM PDT 24
Peak memory 217420 kb
Host smart-bfffd9ea-6def-4f1a-94de-fa684a33f139
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192812023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.4192812023
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.227865605
Short name T979
Test name
Test status
Simulation time 63368183 ps
CPU time 2 seconds
Started Jul 15 06:14:23 PM PDT 24
Finished Jul 15 06:14:25 PM PDT 24
Peak memory 217404 kb
Host smart-3960f065-ae92-4bc1-8e51-784a5b47151f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227865605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.227865605
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2881599635
Short name T182
Test name
Test status
Simulation time 255657214 ps
CPU time 1.64 seconds
Started Jul 15 06:14:34 PM PDT 24
Finished Jul 15 06:14:36 PM PDT 24
Peak memory 209212 kb
Host smart-d26d627a-6f0e-4d01-964d-32c7b57d215f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881599635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2881599635
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3404400320
Short name T920
Test name
Test status
Simulation time 38880849 ps
CPU time 1.34 seconds
Started Jul 15 06:14:38 PM PDT 24
Finished Jul 15 06:14:40 PM PDT 24
Peak memory 209176 kb
Host smart-bab376ac-df08-4b7d-90bc-0efd99c1936c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404400320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3404400320
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.758765601
Short name T186
Test name
Test status
Simulation time 18847047 ps
CPU time 1.18 seconds
Started Jul 15 06:14:23 PM PDT 24
Finished Jul 15 06:14:25 PM PDT 24
Peak memory 209776 kb
Host smart-e1abd0b0-f74c-4182-b886-915b8316d3ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758765601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.758765601
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1201690019
Short name T910
Test name
Test status
Simulation time 51785476 ps
CPU time 1.33 seconds
Started Jul 15 06:14:30 PM PDT 24
Finished Jul 15 06:14:32 PM PDT 24
Peak memory 217604 kb
Host smart-8f0c8c15-699a-4750-b7d8-c5200f21fa88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201690019 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1201690019
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.809115757
Short name T873
Test name
Test status
Simulation time 14544533 ps
CPU time 1.07 seconds
Started Jul 15 06:14:31 PM PDT 24
Finished Jul 15 06:14:34 PM PDT 24
Peak memory 209248 kb
Host smart-8dc0579f-70c5-431c-8338-6e701d253fc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809115757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.809115757
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1654731878
Short name T977
Test name
Test status
Simulation time 156621103 ps
CPU time 1.43 seconds
Started Jul 15 06:14:24 PM PDT 24
Finished Jul 15 06:14:26 PM PDT 24
Peak memory 208532 kb
Host smart-eb7e9638-b469-43e3-884e-27926a676a18
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654731878 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1654731878
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1235797452
Short name T942
Test name
Test status
Simulation time 2002433325 ps
CPU time 5.38 seconds
Started Jul 15 06:14:23 PM PDT 24
Finished Jul 15 06:14:29 PM PDT 24
Peak memory 209164 kb
Host smart-13b47835-b6d7-48f6-b2c3-83064c4fee29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235797452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1235797452
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1513667763
Short name T904
Test name
Test status
Simulation time 830969414 ps
CPU time 5.45 seconds
Started Jul 15 06:14:26 PM PDT 24
Finished Jul 15 06:14:32 PM PDT 24
Peak memory 208760 kb
Host smart-548c074a-9186-4008-a10b-808f8b2badb6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513667763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1513667763
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3368637589
Short name T867
Test name
Test status
Simulation time 172112384 ps
CPU time 1.29 seconds
Started Jul 15 06:14:24 PM PDT 24
Finished Jul 15 06:14:26 PM PDT 24
Peak memory 210628 kb
Host smart-098e2c62-4a54-43ed-837b-7b5372a1f8e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368637589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3368637589
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2945056325
Short name T947
Test name
Test status
Simulation time 120404226 ps
CPU time 2.41 seconds
Started Jul 15 06:14:31 PM PDT 24
Finished Jul 15 06:14:34 PM PDT 24
Peak memory 219328 kb
Host smart-87cd2281-c83d-4ab4-b229-f74388853628
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294505
6325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2945056325
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2916754043
Short name T972
Test name
Test status
Simulation time 60454944 ps
CPU time 2.14 seconds
Started Jul 15 06:14:26 PM PDT 24
Finished Jul 15 06:14:28 PM PDT 24
Peak memory 209152 kb
Host smart-d4f85c87-de80-495d-ab42-c11c67057a32
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916754043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2916754043
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3305952937
Short name T876
Test name
Test status
Simulation time 98637466 ps
CPU time 1.48 seconds
Started Jul 15 06:14:31 PM PDT 24
Finished Jul 15 06:14:34 PM PDT 24
Peak memory 211200 kb
Host smart-7278b8a9-74d7-4ce4-b79b-0cbef146d884
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305952937 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3305952937
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2797026354
Short name T948
Test name
Test status
Simulation time 101062748 ps
CPU time 1.42 seconds
Started Jul 15 06:14:31 PM PDT 24
Finished Jul 15 06:14:33 PM PDT 24
Peak memory 217424 kb
Host smart-a5567f75-60e3-4132-a884-ddb5a5b55744
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797026354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2797026354
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1617663076
Short name T973
Test name
Test status
Simulation time 377693476 ps
CPU time 3.06 seconds
Started Jul 15 06:14:24 PM PDT 24
Finished Jul 15 06:14:28 PM PDT 24
Peak memory 217480 kb
Host smart-2e9a92ed-768e-4490-a285-3fbe42dfc6b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617663076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1617663076
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2521090522
Short name T976
Test name
Test status
Simulation time 21715778 ps
CPU time 1.42 seconds
Started Jul 15 06:14:39 PM PDT 24
Finished Jul 15 06:14:42 PM PDT 24
Peak memory 217496 kb
Host smart-d87a1cfb-2e3b-47c7-ae4f-ba7783886b78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521090522 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2521090522
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3797997711
Short name T184
Test name
Test status
Simulation time 12153471 ps
CPU time 0.95 seconds
Started Jul 15 06:14:32 PM PDT 24
Finished Jul 15 06:14:34 PM PDT 24
Peak memory 209208 kb
Host smart-28d08a13-dc67-443b-a04f-fe5e0b4262b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797997711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3797997711
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2943712291
Short name T139
Test name
Test status
Simulation time 246753011 ps
CPU time 2.13 seconds
Started Jul 15 06:14:31 PM PDT 24
Finished Jul 15 06:14:34 PM PDT 24
Peak memory 208988 kb
Host smart-cb193bf0-549e-47ab-bea6-3575dbff25d6
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943712291 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2943712291
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2557386770
Short name T978
Test name
Test status
Simulation time 368408505 ps
CPU time 4.55 seconds
Started Jul 15 06:14:39 PM PDT 24
Finished Jul 15 06:14:45 PM PDT 24
Peak memory 216932 kb
Host smart-8deed366-7918-4ecb-a049-c2c9cf80eca3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557386770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2557386770
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.151023545
Short name T943
Test name
Test status
Simulation time 488025871 ps
CPU time 6.99 seconds
Started Jul 15 06:14:30 PM PDT 24
Finished Jul 15 06:14:37 PM PDT 24
Peak memory 209176 kb
Host smart-cbc79a3c-8bfd-4128-980a-604d0b8d7787
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151023545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.151023545
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.598923482
Short name T890
Test name
Test status
Simulation time 778085077 ps
CPU time 4.93 seconds
Started Jul 15 06:14:35 PM PDT 24
Finished Jul 15 06:14:40 PM PDT 24
Peak memory 217364 kb
Host smart-417484ea-f92c-4d35-8ca3-93b562178a19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598923482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.598923482
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1024936815
Short name T906
Test name
Test status
Simulation time 931042362 ps
CPU time 4.43 seconds
Started Jul 15 06:14:30 PM PDT 24
Finished Jul 15 06:14:35 PM PDT 24
Peak memory 219188 kb
Host smart-d3457e62-18cc-4765-9621-e82896ce3b7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102493
6815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1024936815
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3404583355
Short name T885
Test name
Test status
Simulation time 150758092 ps
CPU time 4.22 seconds
Started Jul 15 06:14:27 PM PDT 24
Finished Jul 15 06:14:32 PM PDT 24
Peak memory 209168 kb
Host smart-a1098cfd-b946-4ce9-9eec-cb65ab8937eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404583355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3404583355
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3946116328
Short name T871
Test name
Test status
Simulation time 48336771 ps
CPU time 1.41 seconds
Started Jul 15 06:14:37 PM PDT 24
Finished Jul 15 06:14:39 PM PDT 24
Peak memory 211184 kb
Host smart-02308f0e-89c9-49e2-91d5-52b36585467a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946116328 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3946116328
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2776958586
Short name T111
Test name
Test status
Simulation time 31533395 ps
CPU time 1.21 seconds
Started Jul 15 06:14:28 PM PDT 24
Finished Jul 15 06:14:29 PM PDT 24
Peak memory 209220 kb
Host smart-b7e0e553-5793-4744-bf6d-d34d6ba6d17a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776958586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2776958586
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2464012870
Short name T116
Test name
Test status
Simulation time 53970615 ps
CPU time 2.32 seconds
Started Jul 15 06:14:29 PM PDT 24
Finished Jul 15 06:14:32 PM PDT 24
Peak memory 217392 kb
Host smart-6302e8d8-188b-4523-b9e4-07ca2a2c0275
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464012870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2464012870
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.838910681
Short name T934
Test name
Test status
Simulation time 44998138 ps
CPU time 1.54 seconds
Started Jul 15 06:14:31 PM PDT 24
Finished Jul 15 06:14:34 PM PDT 24
Peak memory 218020 kb
Host smart-2ef36cb8-1694-41f9-9003-7c33f14b8a56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838910681 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.838910681
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1911930853
Short name T185
Test name
Test status
Simulation time 44649625 ps
CPU time 1.01 seconds
Started Jul 15 06:14:37 PM PDT 24
Finished Jul 15 06:14:39 PM PDT 24
Peak memory 209104 kb
Host smart-35da8c1e-8e42-4e20-9001-a3cf2a013dd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911930853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1911930853
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2407425848
Short name T937
Test name
Test status
Simulation time 179194795 ps
CPU time 1.05 seconds
Started Jul 15 06:14:30 PM PDT 24
Finished Jul 15 06:14:32 PM PDT 24
Peak memory 209068 kb
Host smart-e1260114-3ab1-4d6e-a644-4e9305162c2f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407425848 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2407425848
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.830167202
Short name T133
Test name
Test status
Simulation time 297166877 ps
CPU time 3.19 seconds
Started Jul 15 06:14:38 PM PDT 24
Finished Jul 15 06:14:42 PM PDT 24
Peak memory 209172 kb
Host smart-32f21841-82bb-45b8-98c6-a86ea3666cfb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830167202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.830167202
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.763582992
Short name T940
Test name
Test status
Simulation time 911319543 ps
CPU time 5.38 seconds
Started Jul 15 06:14:30 PM PDT 24
Finished Jul 15 06:14:36 PM PDT 24
Peak memory 209176 kb
Host smart-e699deeb-f389-4ae9-9c7d-2cb96cc410e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763582992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.763582992
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1441090253
Short name T985
Test name
Test status
Simulation time 303495259 ps
CPU time 2.71 seconds
Started Jul 15 06:14:32 PM PDT 24
Finished Jul 15 06:14:36 PM PDT 24
Peak memory 217344 kb
Host smart-eb9f29b7-7705-4e38-be90-59b43b8d1945
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441090253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1441090253
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.144036197
Short name T931
Test name
Test status
Simulation time 239859619 ps
CPU time 2.11 seconds
Started Jul 15 06:14:31 PM PDT 24
Finished Jul 15 06:14:34 PM PDT 24
Peak memory 217420 kb
Host smart-de3c76fa-c684-4bcb-8565-3bfab17d462f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144036
197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.144036197
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2715362964
Short name T986
Test name
Test status
Simulation time 40087028 ps
CPU time 1.53 seconds
Started Jul 15 06:14:30 PM PDT 24
Finished Jul 15 06:14:33 PM PDT 24
Peak memory 217332 kb
Host smart-a824a44f-a795-4d21-979a-1b0a82dedeaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715362964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.2715362964
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2316143575
Short name T864
Test name
Test status
Simulation time 76150292 ps
CPU time 1.22 seconds
Started Jul 15 06:14:32 PM PDT 24
Finished Jul 15 06:14:34 PM PDT 24
Peak memory 209192 kb
Host smart-0e062b85-a381-4a59-9fd7-59bbd10a461d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316143575 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2316143575
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2997020478
Short name T898
Test name
Test status
Simulation time 87482572 ps
CPU time 1.26 seconds
Started Jul 15 06:14:30 PM PDT 24
Finished Jul 15 06:14:32 PM PDT 24
Peak memory 217508 kb
Host smart-14926252-d802-44e5-9615-79482921d2a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997020478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2997020478
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2795577041
Short name T938
Test name
Test status
Simulation time 23076149 ps
CPU time 1.47 seconds
Started Jul 15 06:14:38 PM PDT 24
Finished Jul 15 06:14:41 PM PDT 24
Peak memory 218496 kb
Host smart-688531a7-b52f-4b84-86b7-41cc44e7a4b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795577041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2795577041
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3908587365
Short name T875
Test name
Test status
Simulation time 37592916 ps
CPU time 1.26 seconds
Started Jul 15 06:14:35 PM PDT 24
Finished Jul 15 06:14:37 PM PDT 24
Peak memory 217480 kb
Host smart-467b4be9-31de-4228-9151-aaa9831822da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908587365 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3908587365
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1414034853
Short name T114
Test name
Test status
Simulation time 103689067 ps
CPU time 0.99 seconds
Started Jul 15 06:14:38 PM PDT 24
Finished Jul 15 06:14:40 PM PDT 24
Peak memory 209416 kb
Host smart-f5d441d8-f43e-493d-8985-8c13195790c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414034853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1414034853
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.657682239
Short name T953
Test name
Test status
Simulation time 102258200 ps
CPU time 1.03 seconds
Started Jul 15 06:14:36 PM PDT 24
Finished Jul 15 06:14:37 PM PDT 24
Peak memory 209072 kb
Host smart-48292e58-a0ff-4a5d-9a3b-1c776ac90961
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657682239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.lc_ctrl_jtag_alert_test.657682239
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.71301555
Short name T878
Test name
Test status
Simulation time 663269420 ps
CPU time 8.03 seconds
Started Jul 15 06:14:34 PM PDT 24
Finished Jul 15 06:14:43 PM PDT 24
Peak memory 209144 kb
Host smart-486f6110-5e56-43a3-9966-19f35ae569f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71301555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.lc_ctrl_jtag_csr_aliasing.71301555
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.718326252
Short name T923
Test name
Test status
Simulation time 5232904017 ps
CPU time 11.81 seconds
Started Jul 15 06:14:37 PM PDT 24
Finished Jul 15 06:14:49 PM PDT 24
Peak memory 209300 kb
Host smart-9957512b-f4dd-4d19-ae61-360c74b5f6d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718326252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.718326252
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3945359446
Short name T135
Test name
Test status
Simulation time 289086435 ps
CPU time 1.91 seconds
Started Jul 15 06:14:39 PM PDT 24
Finished Jul 15 06:14:43 PM PDT 24
Peak memory 217376 kb
Host smart-2052e78f-e7da-43e0-991a-b23e193c6efd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945359446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3945359446
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2373660099
Short name T960
Test name
Test status
Simulation time 336275911 ps
CPU time 1.96 seconds
Started Jul 15 06:14:39 PM PDT 24
Finished Jul 15 06:14:42 PM PDT 24
Peak memory 219788 kb
Host smart-121f3316-d916-4202-88d3-8c03cff2a90f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237366
0099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2373660099
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3860397971
Short name T884
Test name
Test status
Simulation time 224457632 ps
CPU time 2.02 seconds
Started Jul 15 06:14:33 PM PDT 24
Finished Jul 15 06:14:35 PM PDT 24
Peak memory 209176 kb
Host smart-ba28e38d-021f-4d16-bda7-a9263430d854
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860397971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3860397971
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3760003110
Short name T958
Test name
Test status
Simulation time 46190719 ps
CPU time 2.05 seconds
Started Jul 15 06:14:36 PM PDT 24
Finished Jul 15 06:14:38 PM PDT 24
Peak memory 211176 kb
Host smart-8a955f30-109a-432e-aeeb-3a98515acf6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760003110 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3760003110
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1489054755
Short name T901
Test name
Test status
Simulation time 47116901 ps
CPU time 1.29 seconds
Started Jul 15 06:14:37 PM PDT 24
Finished Jul 15 06:14:39 PM PDT 24
Peak memory 209368 kb
Host smart-24720017-a538-4dae-8364-0b18c2e2deb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489054755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1489054755
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3385351741
Short name T909
Test name
Test status
Simulation time 119440183 ps
CPU time 3.34 seconds
Started Jul 15 06:14:40 PM PDT 24
Finished Jul 15 06:14:45 PM PDT 24
Peak memory 217652 kb
Host smart-7e192d48-707d-4154-b1a3-592747a9613e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385351741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3385351741
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3830032914
Short name T919
Test name
Test status
Simulation time 19485351 ps
CPU time 1.08 seconds
Started Jul 15 06:14:39 PM PDT 24
Finished Jul 15 06:14:42 PM PDT 24
Peak memory 219528 kb
Host smart-97d8a427-8728-472f-9485-9751ecb8653e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830032914 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3830032914
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1177636973
Short name T196
Test name
Test status
Simulation time 71435073 ps
CPU time 0.9 seconds
Started Jul 15 06:14:40 PM PDT 24
Finished Jul 15 06:14:42 PM PDT 24
Peak memory 208956 kb
Host smart-67233351-3622-4317-a1db-1eccb8974bf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177636973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1177636973
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1654201968
Short name T880
Test name
Test status
Simulation time 123980365 ps
CPU time 1.98 seconds
Started Jul 15 06:14:37 PM PDT 24
Finished Jul 15 06:14:40 PM PDT 24
Peak memory 208860 kb
Host smart-72f82344-bfe2-4db6-9460-707cf4e3c051
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654201968 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1654201968
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3706867892
Short name T928
Test name
Test status
Simulation time 2432930041 ps
CPU time 14.23 seconds
Started Jul 15 06:14:42 PM PDT 24
Finished Jul 15 06:14:58 PM PDT 24
Peak memory 209108 kb
Host smart-6a663dc2-a403-4ac2-864b-18b3b648039a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706867892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3706867892
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4109601076
Short name T905
Test name
Test status
Simulation time 2168410507 ps
CPU time 10.1 seconds
Started Jul 15 06:14:39 PM PDT 24
Finished Jul 15 06:14:51 PM PDT 24
Peak memory 217080 kb
Host smart-cf7a4229-3df8-4292-a128-87b6b9c4988d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109601076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.4109601076
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2860672716
Short name T865
Test name
Test status
Simulation time 311211971 ps
CPU time 2.07 seconds
Started Jul 15 06:14:39 PM PDT 24
Finished Jul 15 06:14:43 PM PDT 24
Peak memory 217468 kb
Host smart-66c5276a-c47e-43da-bf21-70c0a8c99b72
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860672716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2860672716
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1567866822
Short name T912
Test name
Test status
Simulation time 120182008 ps
CPU time 2.69 seconds
Started Jul 15 06:14:39 PM PDT 24
Finished Jul 15 06:14:43 PM PDT 24
Peak memory 217700 kb
Host smart-2cf2777a-24da-4d36-abe2-92026a350815
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156786
6822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1567866822
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2048436878
Short name T964
Test name
Test status
Simulation time 176008774 ps
CPU time 2.47 seconds
Started Jul 15 06:14:42 PM PDT 24
Finished Jul 15 06:14:45 PM PDT 24
Peak memory 209108 kb
Host smart-fabf8fcd-3c2e-449b-94b9-d8cd2199b5b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048436878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2048436878
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4040027946
Short name T981
Test name
Test status
Simulation time 29145657 ps
CPU time 1.12 seconds
Started Jul 15 06:14:37 PM PDT 24
Finished Jul 15 06:14:39 PM PDT 24
Peak memory 209200 kb
Host smart-7927f517-25d4-499a-9e8c-620134380402
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040027946 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.4040027946
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1506391988
Short name T944
Test name
Test status
Simulation time 42610048 ps
CPU time 1.05 seconds
Started Jul 15 06:14:38 PM PDT 24
Finished Jul 15 06:14:41 PM PDT 24
Peak memory 217452 kb
Host smart-eedf5120-7473-45e4-9612-f96132ccf6c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506391988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1506391988
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.221800351
Short name T924
Test name
Test status
Simulation time 516914263 ps
CPU time 4.69 seconds
Started Jul 15 06:14:40 PM PDT 24
Finished Jul 15 06:14:46 PM PDT 24
Peak memory 217396 kb
Host smart-a8faa1ef-572f-4706-9cd8-e5ae758e2d91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221800351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.221800351
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2848345827
Short name T896
Test name
Test status
Simulation time 22589424 ps
CPU time 1.43 seconds
Started Jul 15 06:14:35 PM PDT 24
Finished Jul 15 06:14:37 PM PDT 24
Peak memory 218540 kb
Host smart-4cda91ab-4ea2-45c0-92db-574297c295c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848345827 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2848345827
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3877387112
Short name T189
Test name
Test status
Simulation time 12617645 ps
CPU time 0.88 seconds
Started Jul 15 06:14:39 PM PDT 24
Finished Jul 15 06:14:41 PM PDT 24
Peak memory 209192 kb
Host smart-1b34ee66-3464-4d40-adca-f9f629aca036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877387112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3877387112
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.514294759
Short name T957
Test name
Test status
Simulation time 63765293 ps
CPU time 2.43 seconds
Started Jul 15 06:14:38 PM PDT 24
Finished Jul 15 06:14:41 PM PDT 24
Peak memory 208592 kb
Host smart-da472fb8-c4d0-45d5-a436-fcd397221e7b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514294759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.514294759
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.4062166571
Short name T902
Test name
Test status
Simulation time 489137557 ps
CPU time 6.17 seconds
Started Jul 15 06:14:36 PM PDT 24
Finished Jul 15 06:14:42 PM PDT 24
Peak memory 209188 kb
Host smart-88c5828b-1f64-43d5-a47a-8aba4cf3fa63
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062166571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.4062166571
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3284472160
Short name T895
Test name
Test status
Simulation time 487973734 ps
CPU time 11.85 seconds
Started Jul 15 06:14:37 PM PDT 24
Finished Jul 15 06:14:49 PM PDT 24
Peak memory 217060 kb
Host smart-2f183f50-945d-48df-8497-b5a3d5160925
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284472160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3284472160
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.4170546417
Short name T868
Test name
Test status
Simulation time 90641672 ps
CPU time 1.83 seconds
Started Jul 15 06:14:40 PM PDT 24
Finished Jul 15 06:14:43 PM PDT 24
Peak memory 210656 kb
Host smart-a2acd930-3ee3-4e2a-b43e-e7cf24139c1b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170546417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.4170546417
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1746276394
Short name T891
Test name
Test status
Simulation time 106351348 ps
CPU time 3.7 seconds
Started Jul 15 06:14:38 PM PDT 24
Finished Jul 15 06:14:43 PM PDT 24
Peak memory 218084 kb
Host smart-c0d6a563-ca66-4308-a8e1-b6abdd0ccc09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174627
6394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1746276394
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2477175731
Short name T956
Test name
Test status
Simulation time 61138435 ps
CPU time 1.3 seconds
Started Jul 15 06:14:38 PM PDT 24
Finished Jul 15 06:14:41 PM PDT 24
Peak memory 209184 kb
Host smart-99e2b2f1-7778-47b5-887f-60f3673b2283
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477175731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.2477175731
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.137734629
Short name T941
Test name
Test status
Simulation time 17623082 ps
CPU time 1.02 seconds
Started Jul 15 06:14:35 PM PDT 24
Finished Jul 15 06:14:36 PM PDT 24
Peak memory 209264 kb
Host smart-6ec46057-211e-4e1c-8910-c918b6180ba6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137734629 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.137734629
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2409411589
Short name T954
Test name
Test status
Simulation time 55092856 ps
CPU time 1.1 seconds
Started Jul 15 06:14:35 PM PDT 24
Finished Jul 15 06:14:37 PM PDT 24
Peak memory 209236 kb
Host smart-314650c4-3a2e-4cf1-a2b5-dc733ab47cef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409411589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2409411589
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3497606897
Short name T949
Test name
Test status
Simulation time 120577689 ps
CPU time 2.3 seconds
Started Jul 15 06:14:37 PM PDT 24
Finished Jul 15 06:14:41 PM PDT 24
Peak memory 218788 kb
Host smart-e57b67c6-9a1c-4a80-8787-8c9d02df7e8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497606897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3497606897
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4153470226
Short name T125
Test name
Test status
Simulation time 58719392 ps
CPU time 2.02 seconds
Started Jul 15 06:14:39 PM PDT 24
Finished Jul 15 06:14:42 PM PDT 24
Peak memory 221840 kb
Host smart-fa915dfc-6d79-4246-a683-860170388798
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153470226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.4153470226
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.355608915
Short name T470
Test name
Test status
Simulation time 101429333 ps
CPU time 0.97 seconds
Started Jul 15 05:26:40 PM PDT 24
Finished Jul 15 05:26:42 PM PDT 24
Peak memory 208452 kb
Host smart-06167409-2eaf-4125-a2d2-17187565d2ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355608915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.355608915
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2821653378
Short name T560
Test name
Test status
Simulation time 13929667 ps
CPU time 0.88 seconds
Started Jul 15 05:26:33 PM PDT 24
Finished Jul 15 05:26:35 PM PDT 24
Peak memory 208456 kb
Host smart-43553abb-400a-4aa1-84b7-3c832c65ab2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821653378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2821653378
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1813699850
Short name T826
Test name
Test status
Simulation time 525202077 ps
CPU time 12.71 seconds
Started Jul 15 05:26:32 PM PDT 24
Finished Jul 15 05:26:46 PM PDT 24
Peak memory 225364 kb
Host smart-89da0939-ae5f-4d7e-ab10-f3889333ebd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813699850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1813699850
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3448393458
Short name T726
Test name
Test status
Simulation time 1594293256 ps
CPU time 8.95 seconds
Started Jul 15 05:26:44 PM PDT 24
Finished Jul 15 05:26:54 PM PDT 24
Peak memory 217104 kb
Host smart-d8a46ec7-e9bd-4bdc-b73c-fa23b908b1e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448393458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3448393458
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3771848564
Short name T599
Test name
Test status
Simulation time 1437330430 ps
CPU time 25.63 seconds
Started Jul 15 05:26:35 PM PDT 24
Finished Jul 15 05:27:01 PM PDT 24
Peak memory 218196 kb
Host smart-4a3c78ef-3bc8-4dfc-adf4-da2ff190dcb9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771848564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3771848564
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2806209702
Short name T659
Test name
Test status
Simulation time 352424284 ps
CPU time 2.3 seconds
Started Jul 15 05:26:42 PM PDT 24
Finished Jul 15 05:26:46 PM PDT 24
Peak memory 217200 kb
Host smart-d9695f1c-7bdf-4750-96f2-cdb6670e5812
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806209702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.2
806209702
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1660580994
Short name T694
Test name
Test status
Simulation time 419169253 ps
CPU time 8.13 seconds
Started Jul 15 05:26:32 PM PDT 24
Finished Jul 15 05:26:41 PM PDT 24
Peak memory 217704 kb
Host smart-17a3da7e-11f6-4ed5-b945-4d0318517746
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660580994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1660580994
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3607341776
Short name T635
Test name
Test status
Simulation time 1734158570 ps
CPU time 12.02 seconds
Started Jul 15 05:26:32 PM PDT 24
Finished Jul 15 05:26:45 PM PDT 24
Peak memory 217048 kb
Host smart-04de70f2-edc2-4819-9d33-e79319027c59
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607341776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3607341776
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1002889963
Short name T464
Test name
Test status
Simulation time 1033876830 ps
CPU time 28.89 seconds
Started Jul 15 05:26:31 PM PDT 24
Finished Jul 15 05:27:01 PM PDT 24
Peak memory 250376 kb
Host smart-b6a3c60f-7274-4d18-aa00-5843ff14292f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002889963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1002889963
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.164321105
Short name T849
Test name
Test status
Simulation time 2780599822 ps
CPU time 14.54 seconds
Started Jul 15 05:26:32 PM PDT 24
Finished Jul 15 05:26:47 PM PDT 24
Peak memory 249660 kb
Host smart-54684472-d0e8-4b79-8714-894794c785b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164321105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.164321105
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2813702496
Short name T743
Test name
Test status
Simulation time 71699006 ps
CPU time 1.72 seconds
Started Jul 15 05:26:32 PM PDT 24
Finished Jul 15 05:26:35 PM PDT 24
Peak memory 217628 kb
Host smart-4890bae2-9cee-42fe-a507-c0ae6ab51d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813702496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2813702496
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1196078958
Short name T499
Test name
Test status
Simulation time 1707037379 ps
CPU time 18.8 seconds
Started Jul 15 05:26:32 PM PDT 24
Finished Jul 15 05:26:52 PM PDT 24
Peak memory 217048 kb
Host smart-0b41acdb-6336-4bdd-8542-f08c000e7133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196078958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1196078958
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3441328070
Short name T93
Test name
Test status
Simulation time 905623899 ps
CPU time 39.88 seconds
Started Jul 15 05:26:39 PM PDT 24
Finished Jul 15 05:27:20 PM PDT 24
Peak memory 269380 kb
Host smart-93885c6f-457a-487b-956e-bada381b9b0a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441328070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3441328070
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.431647132
Short name T579
Test name
Test status
Simulation time 2323316733 ps
CPU time 11.75 seconds
Started Jul 15 05:26:41 PM PDT 24
Finished Jul 15 05:26:53 PM PDT 24
Peak memory 225524 kb
Host smart-7f959d39-4611-4313-a720-2bf1b52422ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431647132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.431647132
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.135547520
Short name T314
Test name
Test status
Simulation time 316946225 ps
CPU time 13.05 seconds
Started Jul 15 05:26:41 PM PDT 24
Finished Jul 15 05:26:55 PM PDT 24
Peak memory 225364 kb
Host smart-2c38e75c-21d4-431f-9f7e-f6613919107d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135547520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig
est.135547520
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3934928737
Short name T680
Test name
Test status
Simulation time 346210089 ps
CPU time 8.82 seconds
Started Jul 15 05:26:39 PM PDT 24
Finished Jul 15 05:26:48 PM PDT 24
Peak memory 217592 kb
Host smart-9bd3fe28-50b1-4fc1-b79a-322c33d30964
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934928737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
934928737
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.467094445
Short name T606
Test name
Test status
Simulation time 54766208 ps
CPU time 2.1 seconds
Started Jul 15 05:26:30 PM PDT 24
Finished Jul 15 05:26:33 PM PDT 24
Peak memory 217096 kb
Host smart-b4df9491-a636-475d-8c0c-2f05887af955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467094445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.467094445
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2073445891
Short name T290
Test name
Test status
Simulation time 868601574 ps
CPU time 26.63 seconds
Started Jul 15 05:26:32 PM PDT 24
Finished Jul 15 05:27:00 PM PDT 24
Peak memory 245960 kb
Host smart-a2162389-9f06-4de3-8c4b-9260905106d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073445891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2073445891
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.666977627
Short name T156
Test name
Test status
Simulation time 100562212 ps
CPU time 6.02 seconds
Started Jul 15 05:26:31 PM PDT 24
Finished Jul 15 05:26:37 PM PDT 24
Peak memory 246652 kb
Host smart-bca3f2b9-043d-4db6-aa2f-103e6dbfd0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666977627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.666977627
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3720197851
Short name T319
Test name
Test status
Simulation time 1496649262 ps
CPU time 13.84 seconds
Started Jul 15 05:26:40 PM PDT 24
Finished Jul 15 05:26:55 PM PDT 24
Peak memory 225456 kb
Host smart-2cffdc71-4fe7-4f96-ae91-440ca15d424a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720197851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3720197851
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1988337434
Short name T799
Test name
Test status
Simulation time 120457878 ps
CPU time 0.77 seconds
Started Jul 15 05:26:31 PM PDT 24
Finished Jul 15 05:26:32 PM PDT 24
Peak memory 208188 kb
Host smart-8e49afff-81d0-4376-a9ba-430aeb2e7985
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988337434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1988337434
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.89604123
Short name T594
Test name
Test status
Simulation time 40821576 ps
CPU time 0.97 seconds
Started Jul 15 05:26:42 PM PDT 24
Finished Jul 15 05:26:44 PM PDT 24
Peak memory 208492 kb
Host smart-7e81b839-2e4c-45f7-a3dd-1c778a61ecfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89604123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.89604123
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1874037701
Short name T238
Test name
Test status
Simulation time 38853153 ps
CPU time 0.9 seconds
Started Jul 15 05:26:40 PM PDT 24
Finished Jul 15 05:26:42 PM PDT 24
Peak memory 208368 kb
Host smart-761a882c-b590-4324-ae45-0f8ed926147e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874037701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1874037701
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1342799192
Short name T437
Test name
Test status
Simulation time 1470445055 ps
CPU time 12.46 seconds
Started Jul 15 05:26:42 PM PDT 24
Finished Jul 15 05:26:55 PM PDT 24
Peak memory 217656 kb
Host smart-e92095b1-ba06-464b-87e2-0cb6b79c91fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342799192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1342799192
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1989327522
Short name T23
Test name
Test status
Simulation time 512837829 ps
CPU time 13.03 seconds
Started Jul 15 05:26:39 PM PDT 24
Finished Jul 15 05:26:53 PM PDT 24
Peak memory 216852 kb
Host smart-1ef2c37b-c475-4e1e-aa90-5c50a7eeca86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989327522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1989327522
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1967679141
Short name T300
Test name
Test status
Simulation time 2569097379 ps
CPU time 70.64 seconds
Started Jul 15 05:26:42 PM PDT 24
Finished Jul 15 05:27:54 PM PDT 24
Peak memory 217748 kb
Host smart-06336324-99fa-4cbf-8405-907b760dfed5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967679141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1967679141
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.4002845100
Short name T395
Test name
Test status
Simulation time 256696236 ps
CPU time 3.59 seconds
Started Jul 15 05:26:42 PM PDT 24
Finished Jul 15 05:26:46 PM PDT 24
Peak memory 217064 kb
Host smart-5b02b6c4-66a6-43d9-a581-818908e868d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002845100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.4
002845100
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1249679752
Short name T381
Test name
Test status
Simulation time 1877355998 ps
CPU time 14.58 seconds
Started Jul 15 05:26:40 PM PDT 24
Finished Jul 15 05:26:56 PM PDT 24
Peak memory 223812 kb
Host smart-274aa5d5-326d-4fba-bd86-47f50c33da21
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249679752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1249679752
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3408333073
Short name T89
Test name
Test status
Simulation time 2206738889 ps
CPU time 16.36 seconds
Started Jul 15 05:26:40 PM PDT 24
Finished Jul 15 05:26:57 PM PDT 24
Peak memory 217372 kb
Host smart-fd24799b-9f5f-4bc7-8e17-838d0e4027b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408333073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3408333073
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2716263945
Short name T622
Test name
Test status
Simulation time 201333768 ps
CPU time 5.81 seconds
Started Jul 15 05:26:40 PM PDT 24
Finished Jul 15 05:26:47 PM PDT 24
Peak memory 216996 kb
Host smart-64043510-02e1-43ef-9246-c9cb0a0901b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716263945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2716263945
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2830852499
Short name T525
Test name
Test status
Simulation time 36897012815 ps
CPU time 61.76 seconds
Started Jul 15 05:26:40 PM PDT 24
Finished Jul 15 05:27:43 PM PDT 24
Peak memory 283064 kb
Host smart-9f76694d-b24e-4b59-acd9-c72d370bf7f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830852499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2830852499
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.20755902
Short name T625
Test name
Test status
Simulation time 281534507 ps
CPU time 3.92 seconds
Started Jul 15 05:26:40 PM PDT 24
Finished Jul 15 05:26:44 PM PDT 24
Peak memory 217616 kb
Host smart-9e210764-2e24-48ce-ac55-12ad47dfc11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20755902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.20755902
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.943911593
Short name T642
Test name
Test status
Simulation time 335479824 ps
CPU time 19.55 seconds
Started Jul 15 05:26:42 PM PDT 24
Finished Jul 15 05:27:03 PM PDT 24
Peak memory 213676 kb
Host smart-9a0e2657-54e4-447a-b3fe-fad944bc4876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943911593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.943911593
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.276295994
Short name T98
Test name
Test status
Simulation time 283456808 ps
CPU time 26.23 seconds
Started Jul 15 05:26:41 PM PDT 24
Finished Jul 15 05:27:08 PM PDT 24
Peak memory 283844 kb
Host smart-7db679ef-e95f-4cf2-913a-4eb0128cacb8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276295994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.276295994
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.4053549587
Short name T645
Test name
Test status
Simulation time 2276773383 ps
CPU time 15.48 seconds
Started Jul 15 05:26:42 PM PDT 24
Finished Jul 15 05:26:59 PM PDT 24
Peak memory 225584 kb
Host smart-2704efdb-485b-4416-b89d-4bd1213d1979
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053549587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.4053549587
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.822718626
Short name T853
Test name
Test status
Simulation time 402192903 ps
CPU time 11.85 seconds
Started Jul 15 05:26:39 PM PDT 24
Finished Jul 15 05:26:52 PM PDT 24
Peak memory 225372 kb
Host smart-d83c5e7b-e6ff-4cac-aa5a-2f505a5fad1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822718626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.822718626
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3296087803
Short name T722
Test name
Test status
Simulation time 837637338 ps
CPU time 6.85 seconds
Started Jul 15 05:26:42 PM PDT 24
Finished Jul 15 05:26:50 PM PDT 24
Peak memory 225428 kb
Host smart-9de676de-03a2-43ef-a35f-2a3c21574814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296087803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3296087803
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.341264714
Short name T621
Test name
Test status
Simulation time 40407255 ps
CPU time 2.62 seconds
Started Jul 15 05:26:42 PM PDT 24
Finished Jul 15 05:26:46 PM PDT 24
Peak memory 213692 kb
Host smart-349dccb1-8eaf-490d-8d90-bb04a8bca20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341264714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.341264714
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2194873191
Short name T817
Test name
Test status
Simulation time 468122424 ps
CPU time 21.05 seconds
Started Jul 15 05:26:41 PM PDT 24
Finished Jul 15 05:27:03 PM PDT 24
Peak memory 250476 kb
Host smart-60243bf1-70e8-4278-ba08-3c8f9ca7547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194873191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2194873191
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1190154259
Short name T155
Test name
Test status
Simulation time 786134145 ps
CPU time 7.15 seconds
Started Jul 15 05:26:44 PM PDT 24
Finished Jul 15 05:26:52 PM PDT 24
Peak memory 247928 kb
Host smart-2f2d1538-3281-40f1-934c-b9a39bb14881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190154259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1190154259
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2547584498
Short name T315
Test name
Test status
Simulation time 7471485920 ps
CPU time 68.26 seconds
Started Jul 15 05:26:44 PM PDT 24
Finished Jul 15 05:27:53 PM PDT 24
Peak memory 250496 kb
Host smart-a76367f2-f5c8-410c-8fc5-9e35c5e236bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547584498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2547584498
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2977354938
Short name T252
Test name
Test status
Simulation time 38195413 ps
CPU time 0.82 seconds
Started Jul 15 05:26:40 PM PDT 24
Finished Jul 15 05:26:42 PM PDT 24
Peak memory 208332 kb
Host smart-15f77c74-54c3-403f-9783-9d32a46ed636
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977354938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2977354938
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.764263454
Short name T402
Test name
Test status
Simulation time 24967302 ps
CPU time 1.28 seconds
Started Jul 15 05:28:05 PM PDT 24
Finished Jul 15 05:28:07 PM PDT 24
Peak memory 208536 kb
Host smart-17121a73-a5e0-4efc-a3bb-790d45bdebba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764263454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.764263454
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2063751202
Short name T681
Test name
Test status
Simulation time 370102941 ps
CPU time 19.06 seconds
Started Jul 15 05:27:57 PM PDT 24
Finished Jul 15 05:28:17 PM PDT 24
Peak memory 225512 kb
Host smart-11a0ec84-456c-4a23-ac86-8aaa51953c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063751202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2063751202
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.2607136043
Short name T25
Test name
Test status
Simulation time 348702308 ps
CPU time 6.67 seconds
Started Jul 15 05:27:59 PM PDT 24
Finished Jul 15 05:28:06 PM PDT 24
Peak memory 216820 kb
Host smart-c945742c-0708-42ed-86cb-6bb1acc025cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607136043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2607136043
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.3094898943
Short name T19
Test name
Test status
Simulation time 5606758508 ps
CPU time 48.12 seconds
Started Jul 15 05:27:59 PM PDT 24
Finished Jul 15 05:28:48 PM PDT 24
Peak memory 217984 kb
Host smart-62b2a705-98d1-4aa0-9b04-c15d43ba1e30
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094898943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.3094898943
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1719955855
Short name T795
Test name
Test status
Simulation time 246397777 ps
CPU time 5.78 seconds
Started Jul 15 05:28:00 PM PDT 24
Finished Jul 15 05:28:06 PM PDT 24
Peak memory 222464 kb
Host smart-7d0ed2f4-97e7-463b-882d-9acaadf6df1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719955855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1719955855
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3950173884
Short name T242
Test name
Test status
Simulation time 733499515 ps
CPU time 8.41 seconds
Started Jul 15 05:27:57 PM PDT 24
Finished Jul 15 05:28:06 PM PDT 24
Peak memory 217172 kb
Host smart-72457085-0685-4b0f-8a87-ff10470b636a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950173884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3950173884
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1442518826
Short name T591
Test name
Test status
Simulation time 2968415072 ps
CPU time 14.95 seconds
Started Jul 15 05:27:57 PM PDT 24
Finished Jul 15 05:28:12 PM PDT 24
Peak memory 250460 kb
Host smart-0d2f1d6c-f153-4247-a739-cc2020b15465
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442518826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1442518826
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.466580581
Short name T33
Test name
Test status
Simulation time 471826299 ps
CPU time 2.05 seconds
Started Jul 15 05:28:01 PM PDT 24
Finished Jul 15 05:28:04 PM PDT 24
Peak memory 217644 kb
Host smart-943bb840-07f1-472d-959e-4d8ee369922b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466580581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.466580581
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3361432210
Short name T857
Test name
Test status
Simulation time 519538777 ps
CPU time 10.57 seconds
Started Jul 15 05:28:01 PM PDT 24
Finished Jul 15 05:28:12 PM PDT 24
Peak memory 217844 kb
Host smart-3e1c6e9c-7721-4267-9438-3e3a52af2695
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361432210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3361432210
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1314845335
Short name T277
Test name
Test status
Simulation time 226299632 ps
CPU time 9.72 seconds
Started Jul 15 05:27:58 PM PDT 24
Finished Jul 15 05:28:08 PM PDT 24
Peak memory 217676 kb
Host smart-fb86390c-429d-4aee-8eb7-b1ca7f5573a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314845335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1314845335
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.4250190227
Short name T48
Test name
Test status
Simulation time 307990067 ps
CPU time 8.88 seconds
Started Jul 15 05:27:58 PM PDT 24
Finished Jul 15 05:28:07 PM PDT 24
Peak memory 225368 kb
Host smart-1276c8b9-5c8a-4756-8cbe-f9efb7d2161d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250190227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
4250190227
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3356127586
Short name T638
Test name
Test status
Simulation time 7292873878 ps
CPU time 13.53 seconds
Started Jul 15 05:28:00 PM PDT 24
Finished Jul 15 05:28:14 PM PDT 24
Peak memory 217784 kb
Host smart-254fe11b-1ea2-4522-aacb-afaf3aacfa0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356127586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3356127586
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3219057715
Short name T208
Test name
Test status
Simulation time 204976502 ps
CPU time 3.27 seconds
Started Jul 15 05:28:01 PM PDT 24
Finished Jul 15 05:28:05 PM PDT 24
Peak memory 214400 kb
Host smart-9dcdd0f9-0299-4000-b485-b687442e3ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219057715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3219057715
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2892390037
Short name T677
Test name
Test status
Simulation time 163469505 ps
CPU time 17.98 seconds
Started Jul 15 05:28:02 PM PDT 24
Finished Jul 15 05:28:20 PM PDT 24
Peak memory 250412 kb
Host smart-f7d4a84f-8161-4095-b60e-14a3156e552e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892390037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2892390037
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3706878082
Short name T446
Test name
Test status
Simulation time 217487305 ps
CPU time 10.04 seconds
Started Jul 15 05:27:57 PM PDT 24
Finished Jul 15 05:28:08 PM PDT 24
Peak memory 250304 kb
Host smart-87f9d4f1-68b7-486d-afe7-9ca05aae94c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706878082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3706878082
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1212181377
Short name T360
Test name
Test status
Simulation time 4687815206 ps
CPU time 124.21 seconds
Started Jul 15 05:27:58 PM PDT 24
Finished Jul 15 05:30:03 PM PDT 24
Peak memory 283268 kb
Host smart-cc3eb790-d51c-46cb-b7ae-e4391653641f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212181377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1212181377
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1394973711
Short name T489
Test name
Test status
Simulation time 187954910 ps
CPU time 0.92 seconds
Started Jul 15 05:27:57 PM PDT 24
Finished Jul 15 05:27:59 PM PDT 24
Peak memory 208500 kb
Host smart-88625def-df0c-4578-9f02-a13e7e1094af
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394973711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1394973711
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3880018778
Short name T409
Test name
Test status
Simulation time 17247865 ps
CPU time 0.93 seconds
Started Jul 15 05:28:11 PM PDT 24
Finished Jul 15 05:28:12 PM PDT 24
Peak memory 208444 kb
Host smart-b3d2b8e6-32fc-4902-8d9a-2350dcd5f553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880018778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3880018778
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3256328421
Short name T483
Test name
Test status
Simulation time 477264780 ps
CPU time 19.75 seconds
Started Jul 15 05:28:04 PM PDT 24
Finished Jul 15 05:28:25 PM PDT 24
Peak memory 217600 kb
Host smart-a201693e-18c2-4c4e-8027-c5f64295abc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256328421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3256328421
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.278939200
Short name T783
Test name
Test status
Simulation time 128071282 ps
CPU time 1.64 seconds
Started Jul 15 05:28:04 PM PDT 24
Finished Jul 15 05:28:06 PM PDT 24
Peak memory 216576 kb
Host smart-a9ec15d7-76ba-46d5-b8a3-fad7c7eb6fb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278939200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.278939200
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1836644402
Short name T471
Test name
Test status
Simulation time 8696204063 ps
CPU time 58.49 seconds
Started Jul 15 05:28:09 PM PDT 24
Finished Jul 15 05:29:08 PM PDT 24
Peak memory 219284 kb
Host smart-f024066b-719a-4626-bbba-a79bcf67253a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836644402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1836644402
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1166219080
Short name T225
Test name
Test status
Simulation time 2200057611 ps
CPU time 13.4 seconds
Started Jul 15 05:28:03 PM PDT 24
Finished Jul 15 05:28:17 PM PDT 24
Peak memory 217700 kb
Host smart-0a91faa1-9b56-4fb8-95f5-42776040159f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166219080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1166219080
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3613263697
Short name T400
Test name
Test status
Simulation time 1854438628 ps
CPU time 3.55 seconds
Started Jul 15 05:28:10 PM PDT 24
Finished Jul 15 05:28:14 PM PDT 24
Peak memory 217040 kb
Host smart-6c34046e-761d-4bf8-bc60-dc72e70af38d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613263697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3613263697
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3273073823
Short name T230
Test name
Test status
Simulation time 28388418047 ps
CPU time 65.1 seconds
Started Jul 15 05:28:04 PM PDT 24
Finished Jul 15 05:29:09 PM PDT 24
Peak memory 275272 kb
Host smart-35c6eaa0-435c-4cc2-ab03-a3f1b254b662
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273073823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3273073823
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1729506951
Short name T824
Test name
Test status
Simulation time 3780264795 ps
CPU time 31.4 seconds
Started Jul 15 05:28:09 PM PDT 24
Finished Jul 15 05:28:41 PM PDT 24
Peak memory 250140 kb
Host smart-a6c446c3-035e-40df-a1d2-b89d75460e43
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729506951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1729506951
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3207823797
Short name T781
Test name
Test status
Simulation time 73956274 ps
CPU time 3.86 seconds
Started Jul 15 05:28:09 PM PDT 24
Finished Jul 15 05:28:13 PM PDT 24
Peak memory 217736 kb
Host smart-492f87c1-c1a7-42a2-a7d7-09db099b6e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207823797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3207823797
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3891642453
Short name T260
Test name
Test status
Simulation time 1917189487 ps
CPU time 16.64 seconds
Started Jul 15 05:28:04 PM PDT 24
Finished Jul 15 05:28:21 PM PDT 24
Peak memory 225384 kb
Host smart-d41ca349-5928-45f3-857c-aa5ce9a082fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891642453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3891642453
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3158971095
Short name T241
Test name
Test status
Simulation time 1303999638 ps
CPU time 9.39 seconds
Started Jul 15 05:28:05 PM PDT 24
Finished Jul 15 05:28:15 PM PDT 24
Peak memory 217668 kb
Host smart-a3a2861d-46dc-47e1-8f31-99dbdaea81d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158971095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3158971095
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.1885511321
Short name T702
Test name
Test status
Simulation time 752513551 ps
CPU time 2.13 seconds
Started Jul 15 05:28:04 PM PDT 24
Finished Jul 15 05:28:07 PM PDT 24
Peak memory 217140 kb
Host smart-cd4d2590-ffaf-4df9-a1b3-95c30b638108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885511321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1885511321
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.2141306891
Short name T854
Test name
Test status
Simulation time 750870895 ps
CPU time 15.27 seconds
Started Jul 15 05:28:05 PM PDT 24
Finished Jul 15 05:28:21 PM PDT 24
Peak memory 250468 kb
Host smart-0ea0f096-85db-4049-aa7b-b47ef29cfe92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141306891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2141306891
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.726912672
Short name T653
Test name
Test status
Simulation time 192929429 ps
CPU time 3.32 seconds
Started Jul 15 05:28:05 PM PDT 24
Finished Jul 15 05:28:09 PM PDT 24
Peak memory 221848 kb
Host smart-941833d8-5c8a-43ec-85c4-8f597b1e78af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726912672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.726912672
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1337147114
Short name T430
Test name
Test status
Simulation time 17548202140 ps
CPU time 224.56 seconds
Started Jul 15 05:28:04 PM PDT 24
Finished Jul 15 05:31:49 PM PDT 24
Peak memory 270476 kb
Host smart-7001b5cd-1cc3-4f06-bb26-3154a61ae9cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337147114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1337147114
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2484077689
Short name T608
Test name
Test status
Simulation time 156178726 ps
CPU time 0.93 seconds
Started Jul 15 05:28:03 PM PDT 24
Finished Jul 15 05:28:04 PM PDT 24
Peak memory 208448 kb
Host smart-2834fbd4-bec4-4f84-b371-a546c402707d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484077689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2484077689
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.703780772
Short name T782
Test name
Test status
Simulation time 45219348 ps
CPU time 0.96 seconds
Started Jul 15 05:28:21 PM PDT 24
Finished Jul 15 05:28:23 PM PDT 24
Peak memory 208520 kb
Host smart-63940e95-e627-41dc-b90f-efb781c7e380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703780772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.703780772
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.183348709
Short name T829
Test name
Test status
Simulation time 1618137672 ps
CPU time 17.97 seconds
Started Jul 15 05:28:12 PM PDT 24
Finished Jul 15 05:28:31 PM PDT 24
Peak memory 225432 kb
Host smart-17a32dce-e7d2-44e7-a5d9-d087a046dd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183348709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.183348709
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1156991959
Short name T778
Test name
Test status
Simulation time 4195103357 ps
CPU time 6.67 seconds
Started Jul 15 05:28:13 PM PDT 24
Finished Jul 15 05:28:20 PM PDT 24
Peak memory 217192 kb
Host smart-3d55ecf4-b046-46f1-bda4-b0cc4d971007
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156991959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1156991959
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2333851402
Short name T519
Test name
Test status
Simulation time 1155636179 ps
CPU time 37.25 seconds
Started Jul 15 05:28:14 PM PDT 24
Finished Jul 15 05:28:52 PM PDT 24
Peak memory 217640 kb
Host smart-513cd8be-e383-4d7d-880f-e2bd4c5c594d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333851402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2333851402
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.4274248898
Short name T656
Test name
Test status
Simulation time 1213363556 ps
CPU time 3.58 seconds
Started Jul 15 05:28:12 PM PDT 24
Finished Jul 15 05:28:16 PM PDT 24
Peak memory 217612 kb
Host smart-72ff655c-fc9c-4b44-bedf-d45680df60cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274248898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.4274248898
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1099278827
Short name T65
Test name
Test status
Simulation time 394487683 ps
CPU time 2.37 seconds
Started Jul 15 05:28:12 PM PDT 24
Finished Jul 15 05:28:15 PM PDT 24
Peak memory 217052 kb
Host smart-96e759e8-37a0-4eda-9595-27d752176c6b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099278827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1099278827
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1765188920
Short name T492
Test name
Test status
Simulation time 1541893770 ps
CPU time 58.71 seconds
Started Jul 15 05:28:13 PM PDT 24
Finished Jul 15 05:29:12 PM PDT 24
Peak memory 250408 kb
Host smart-feac3621-4e48-4752-b8ad-15a333d45f3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765188920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1765188920
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3500227493
Short name T301
Test name
Test status
Simulation time 502750577 ps
CPU time 9.3 seconds
Started Jul 15 05:28:15 PM PDT 24
Finished Jul 15 05:28:25 PM PDT 24
Peak memory 225752 kb
Host smart-5f5ad9b5-6432-4f4e-abd4-b8e28fa7437e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500227493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3500227493
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3152434867
Short name T289
Test name
Test status
Simulation time 56243092 ps
CPU time 3.31 seconds
Started Jul 15 05:28:12 PM PDT 24
Finished Jul 15 05:28:16 PM PDT 24
Peak memory 217688 kb
Host smart-26032f70-96a5-4f22-ad14-25e7b833d741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152434867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3152434867
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3377198224
Short name T761
Test name
Test status
Simulation time 214677184 ps
CPU time 8.44 seconds
Started Jul 15 05:28:13 PM PDT 24
Finished Jul 15 05:28:22 PM PDT 24
Peak memory 225532 kb
Host smart-91baf047-ed79-41ab-a3d5-e5fe6865bf26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377198224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3377198224
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.4202503819
Short name T802
Test name
Test status
Simulation time 201050880 ps
CPU time 7.27 seconds
Started Jul 15 05:28:13 PM PDT 24
Finished Jul 15 05:28:21 PM PDT 24
Peak memory 217676 kb
Host smart-ad9edbf2-4c38-408f-baf4-4680aeebcf7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202503819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
4202503819
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3485888514
Short name T276
Test name
Test status
Simulation time 620075430 ps
CPU time 8.24 seconds
Started Jul 15 05:28:14 PM PDT 24
Finished Jul 15 05:28:23 PM PDT 24
Peak memory 224836 kb
Host smart-0ec5ef13-351e-4040-9b1d-12b5fadcc23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485888514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3485888514
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1311945038
Short name T79
Test name
Test status
Simulation time 47863174 ps
CPU time 1.88 seconds
Started Jul 15 05:28:12 PM PDT 24
Finished Jul 15 05:28:14 PM PDT 24
Peak memory 217132 kb
Host smart-c53fe310-1771-4170-9594-93c1d521663d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311945038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1311945038
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1619803227
Short name T364
Test name
Test status
Simulation time 1144692976 ps
CPU time 26.28 seconds
Started Jul 15 05:28:12 PM PDT 24
Finished Jul 15 05:28:39 PM PDT 24
Peak memory 250428 kb
Host smart-db30129f-c5fd-4fd2-ade7-c728193071a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619803227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1619803227
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2435302726
Short name T451
Test name
Test status
Simulation time 361135020 ps
CPU time 9.02 seconds
Started Jul 15 05:28:13 PM PDT 24
Finished Jul 15 05:28:22 PM PDT 24
Peak memory 250412 kb
Host smart-1850e0fe-829e-4439-9274-85b64643dd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435302726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2435302726
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.618336297
Short name T324
Test name
Test status
Simulation time 9000305578 ps
CPU time 49.61 seconds
Started Jul 15 05:28:15 PM PDT 24
Finished Jul 15 05:29:05 PM PDT 24
Peak memory 225912 kb
Host smart-f72a3173-845a-46b0-a6ec-8289b425854a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618336297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.618336297
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.4082871109
Short name T142
Test name
Test status
Simulation time 576662404800 ps
CPU time 614.33 seconds
Started Jul 15 05:28:21 PM PDT 24
Finished Jul 15 05:38:36 PM PDT 24
Peak memory 281116 kb
Host smart-0de3e0c4-14ae-4e10-a12c-f1fe90f74969
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4082871109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.4082871109
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1129192577
Short name T708
Test name
Test status
Simulation time 28774571 ps
CPU time 1.08 seconds
Started Jul 15 05:28:11 PM PDT 24
Finished Jul 15 05:28:12 PM PDT 24
Peak memory 211364 kb
Host smart-824f9fdb-dee6-4d07-97d9-02b7ff7d0794
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129192577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1129192577
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3802551631
Short name T604
Test name
Test status
Simulation time 12629397 ps
CPU time 1.05 seconds
Started Jul 15 05:28:22 PM PDT 24
Finished Jul 15 05:28:24 PM PDT 24
Peak memory 208404 kb
Host smart-eb3fe5ad-5e7d-45a7-941a-f114ac8b5617
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802551631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3802551631
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2341794346
Short name T542
Test name
Test status
Simulation time 927988581 ps
CPU time 11.93 seconds
Started Jul 15 05:28:21 PM PDT 24
Finished Jul 15 05:28:34 PM PDT 24
Peak memory 225440 kb
Host smart-fa0cc4d3-1009-4ada-b6f3-ec372755ecb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341794346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2341794346
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3759562888
Short name T28
Test name
Test status
Simulation time 696488676 ps
CPU time 3.48 seconds
Started Jul 15 05:28:19 PM PDT 24
Finished Jul 15 05:28:24 PM PDT 24
Peak memory 216536 kb
Host smart-45b4ec6c-fef0-4b5c-b57b-6f90337ecf8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759562888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3759562888
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.244027154
Short name T842
Test name
Test status
Simulation time 2182153796 ps
CPU time 47.23 seconds
Started Jul 15 05:28:20 PM PDT 24
Finished Jul 15 05:29:08 PM PDT 24
Peak memory 217736 kb
Host smart-6fa5c49e-a0f3-4bfc-b2f0-bf2a08338b36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244027154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.244027154
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3087592242
Short name T330
Test name
Test status
Simulation time 7991702872 ps
CPU time 8.66 seconds
Started Jul 15 05:28:20 PM PDT 24
Finished Jul 15 05:28:30 PM PDT 24
Peak memory 217632 kb
Host smart-76113f37-d937-4d54-8d74-7efef0c57427
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087592242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3087592242
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3389923697
Short name T820
Test name
Test status
Simulation time 124390871 ps
CPU time 4.04 seconds
Started Jul 15 05:28:23 PM PDT 24
Finished Jul 15 05:28:28 PM PDT 24
Peak memory 216968 kb
Host smart-30a05d84-8839-4c88-873c-b7fd3c2e4ee8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389923697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3389923697
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3279600228
Short name T373
Test name
Test status
Simulation time 2372597615 ps
CPU time 91.23 seconds
Started Jul 15 05:28:20 PM PDT 24
Finished Jul 15 05:29:52 PM PDT 24
Peak memory 278932 kb
Host smart-7b705e6a-071e-45d0-8770-99e6f7ef03aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279600228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3279600228
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2112353215
Short name T452
Test name
Test status
Simulation time 6662766313 ps
CPU time 28.59 seconds
Started Jul 15 05:28:19 PM PDT 24
Finished Jul 15 05:28:49 PM PDT 24
Peak memory 250428 kb
Host smart-9ab3d267-2abc-48d9-86b5-8323092f7a3e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112353215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2112353215
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1395788048
Short name T262
Test name
Test status
Simulation time 581270486 ps
CPU time 4.14 seconds
Started Jul 15 05:28:21 PM PDT 24
Finished Jul 15 05:28:26 PM PDT 24
Peak memory 217652 kb
Host smart-9c2ca497-bc31-4c56-95c3-4bfc1aa82f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395788048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1395788048
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.180847438
Short name T735
Test name
Test status
Simulation time 801006829 ps
CPU time 18.62 seconds
Started Jul 15 05:28:21 PM PDT 24
Finished Jul 15 05:28:41 PM PDT 24
Peak memory 218336 kb
Host smart-291b5b4a-9f47-493a-8739-ec5bcd4caecb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180847438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.180847438
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.4210724992
Short name T812
Test name
Test status
Simulation time 1417053435 ps
CPU time 13.62 seconds
Started Jul 15 05:28:22 PM PDT 24
Finished Jul 15 05:28:36 PM PDT 24
Peak memory 225428 kb
Host smart-31e63e88-f6bf-4572-92e2-a855b891510a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210724992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.4210724992
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1185172046
Short name T550
Test name
Test status
Simulation time 307656407 ps
CPU time 8.44 seconds
Started Jul 15 05:28:22 PM PDT 24
Finished Jul 15 05:28:31 PM PDT 24
Peak memory 217632 kb
Host smart-81b75e07-d707-44b9-94ed-09730acd0de9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185172046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1185172046
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.610207447
Short name T411
Test name
Test status
Simulation time 279184316 ps
CPU time 8.9 seconds
Started Jul 15 05:28:19 PM PDT 24
Finished Jul 15 05:28:29 PM PDT 24
Peak memory 225476 kb
Host smart-b7e5e0f7-39f1-40a6-bf0c-bd6824795a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610207447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.610207447
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.383139437
Short name T348
Test name
Test status
Simulation time 153128737 ps
CPU time 1.91 seconds
Started Jul 15 05:28:19 PM PDT 24
Finished Jul 15 05:28:22 PM PDT 24
Peak memory 213588 kb
Host smart-aa792abc-df8a-428f-895d-62ad798946c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383139437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.383139437
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.789370389
Short name T221
Test name
Test status
Simulation time 240969363 ps
CPU time 23.07 seconds
Started Jul 15 05:28:20 PM PDT 24
Finished Jul 15 05:28:44 PM PDT 24
Peak memory 250472 kb
Host smart-993e02c4-8bb9-4773-9aa0-c9aef3f2a282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789370389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.789370389
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2532873648
Short name T738
Test name
Test status
Simulation time 643433713 ps
CPU time 7.23 seconds
Started Jul 15 05:28:19 PM PDT 24
Finished Jul 15 05:28:28 PM PDT 24
Peak memory 250312 kb
Host smart-7f811ce7-2020-4564-b609-cf57ad7f9bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532873648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2532873648
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.4018926330
Short name T17
Test name
Test status
Simulation time 59018824746 ps
CPU time 112.8 seconds
Started Jul 15 05:28:21 PM PDT 24
Finished Jul 15 05:30:14 PM PDT 24
Peak memory 268556 kb
Host smart-12a6879a-0c28-452b-a40d-b680f6b799a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018926330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.4018926330
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3531647348
Short name T852
Test name
Test status
Simulation time 42275150 ps
CPU time 0.91 seconds
Started Jul 15 05:28:23 PM PDT 24
Finished Jul 15 05:28:25 PM PDT 24
Peak memory 208364 kb
Host smart-0670264c-fcd4-4ef0-aaa5-d714537378c7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531647348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3531647348
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1083577305
Short name T691
Test name
Test status
Simulation time 50058095 ps
CPU time 1.03 seconds
Started Jul 15 05:28:28 PM PDT 24
Finished Jul 15 05:28:31 PM PDT 24
Peak memory 208720 kb
Host smart-044fd3af-6c02-48ee-b8bd-a3e2caadcc88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083577305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1083577305
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3285678408
Short name T472
Test name
Test status
Simulation time 324581504 ps
CPU time 8 seconds
Started Jul 15 05:28:25 PM PDT 24
Finished Jul 15 05:28:33 PM PDT 24
Peak memory 225480 kb
Host smart-f64e1bb8-0c82-4090-9f17-10d4bb1816c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285678408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3285678408
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.1087913636
Short name T810
Test name
Test status
Simulation time 2904261512 ps
CPU time 16.3 seconds
Started Jul 15 05:28:27 PM PDT 24
Finished Jul 15 05:28:44 PM PDT 24
Peak memory 217140 kb
Host smart-81b49f17-ee28-4c01-a875-4f5369d4a6f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087913636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1087913636
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1003583226
Short name T422
Test name
Test status
Simulation time 1649128627 ps
CPU time 26.08 seconds
Started Jul 15 05:28:29 PM PDT 24
Finished Jul 15 05:28:57 PM PDT 24
Peak memory 217588 kb
Host smart-f8838e59-0f92-4cd1-8b94-7706bda5742f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003583226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1003583226
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3396658491
Short name T363
Test name
Test status
Simulation time 77467903 ps
CPU time 2.32 seconds
Started Jul 15 05:28:29 PM PDT 24
Finished Jul 15 05:28:33 PM PDT 24
Peak memory 217568 kb
Host smart-e31dc9ef-454f-4457-aaee-2b6958d56987
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396658491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3396658491
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1560876073
Short name T574
Test name
Test status
Simulation time 929892561 ps
CPU time 7.44 seconds
Started Jul 15 05:28:31 PM PDT 24
Finished Jul 15 05:28:39 PM PDT 24
Peak memory 217056 kb
Host smart-62d0dbc1-4e71-4da8-a582-67493a036240
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560876073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1560876073
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1805444606
Short name T839
Test name
Test status
Simulation time 8617377265 ps
CPU time 47.96 seconds
Started Jul 15 05:28:29 PM PDT 24
Finished Jul 15 05:29:19 PM PDT 24
Peak memory 275732 kb
Host smart-0cdfab4a-6ae4-4dba-8d30-447e0e8c9ddf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805444606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1805444606
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.4065998358
Short name T587
Test name
Test status
Simulation time 469851597 ps
CPU time 17.92 seconds
Started Jul 15 05:28:28 PM PDT 24
Finished Jul 15 05:28:49 PM PDT 24
Peak memory 245220 kb
Host smart-4c30787b-acf8-4720-a114-9f638e053644
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065998358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.4065998358
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.179284128
Short name T426
Test name
Test status
Simulation time 381926576 ps
CPU time 2.97 seconds
Started Jul 15 05:28:23 PM PDT 24
Finished Jul 15 05:28:26 PM PDT 24
Peak memory 217704 kb
Host smart-7049ead5-1ed2-425d-a6d1-6ec9fbd1331f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179284128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.179284128
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.453328316
Short name T700
Test name
Test status
Simulation time 437756602 ps
CPU time 9.76 seconds
Started Jul 15 05:28:27 PM PDT 24
Finished Jul 15 05:28:37 PM PDT 24
Peak memory 225492 kb
Host smart-aadf71c9-7d23-4212-aa1c-4a101f4c5b3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453328316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.453328316
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3403773960
Short name T663
Test name
Test status
Simulation time 1435332705 ps
CPU time 11.13 seconds
Started Jul 15 05:28:28 PM PDT 24
Finished Jul 15 05:28:42 PM PDT 24
Peak memory 224408 kb
Host smart-fae68a3f-6535-45fd-92c5-762820c983bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403773960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3403773960
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2211336302
Short name T392
Test name
Test status
Simulation time 230268462 ps
CPU time 6.92 seconds
Started Jul 15 05:28:27 PM PDT 24
Finished Jul 15 05:28:35 PM PDT 24
Peak memory 217692 kb
Host smart-2da8f4e6-a89b-4f68-903e-621c58ddb4bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211336302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2211336302
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2561028006
Short name T51
Test name
Test status
Simulation time 272588575 ps
CPU time 7.62 seconds
Started Jul 15 05:28:29 PM PDT 24
Finished Jul 15 05:28:38 PM PDT 24
Peak memory 225504 kb
Host smart-846c1b8a-a62d-4d94-93d2-c843b1fb6cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561028006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2561028006
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1474197764
Short name T273
Test name
Test status
Simulation time 52027271 ps
CPU time 1.75 seconds
Started Jul 15 05:28:21 PM PDT 24
Finished Jul 15 05:28:24 PM PDT 24
Peak memory 213348 kb
Host smart-d74eb0e4-6dc6-4b6e-a218-dec7aa4ff052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474197764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1474197764
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.4023328051
Short name T287
Test name
Test status
Simulation time 375327286 ps
CPU time 23.8 seconds
Started Jul 15 05:28:22 PM PDT 24
Finished Jul 15 05:28:47 PM PDT 24
Peak memory 250432 kb
Host smart-26310809-f316-45ce-b5fd-39f5f935e147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023328051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.4023328051
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2582339447
Short name T407
Test name
Test status
Simulation time 342415485 ps
CPU time 7.24 seconds
Started Jul 15 05:28:24 PM PDT 24
Finished Jul 15 05:28:32 PM PDT 24
Peak memory 245772 kb
Host smart-80cd363f-e73a-4254-9354-b6dc4ceb01e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582339447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2582339447
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.322247950
Short name T439
Test name
Test status
Simulation time 1717656444 ps
CPU time 52.63 seconds
Started Jul 15 05:28:31 PM PDT 24
Finished Jul 15 05:29:24 PM PDT 24
Peak memory 268392 kb
Host smart-5c4ae836-d400-4fa2-b9e0-eab7a52e37b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322247950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.322247950
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.3555854325
Short name T106
Test name
Test status
Simulation time 109411583686 ps
CPU time 681.54 seconds
Started Jul 15 05:28:30 PM PDT 24
Finished Jul 15 05:39:53 PM PDT 24
Peak memory 529020 kb
Host smart-d560ca05-e3fb-4221-ab87-2aec3648861c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3555854325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.3555854325
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1054366080
Short name T637
Test name
Test status
Simulation time 217898951 ps
CPU time 1.07 seconds
Started Jul 15 05:28:22 PM PDT 24
Finished Jul 15 05:28:24 PM PDT 24
Peak memory 211244 kb
Host smart-e9c18cac-4db0-4575-b7c3-139de8fb79b0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054366080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1054366080
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3560851922
Short name T633
Test name
Test status
Simulation time 17627592 ps
CPU time 0.86 seconds
Started Jul 15 05:28:40 PM PDT 24
Finished Jul 15 05:28:42 PM PDT 24
Peak memory 208412 kb
Host smart-634cdc53-0c4e-4f42-a31e-86b80e6d4801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560851922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3560851922
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3456091196
Short name T750
Test name
Test status
Simulation time 1010748213 ps
CPU time 8.04 seconds
Started Jul 15 05:28:29 PM PDT 24
Finished Jul 15 05:28:39 PM PDT 24
Peak memory 225464 kb
Host smart-d019da4e-7dd6-48e0-a0e4-04878fec7c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456091196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3456091196
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3585428254
Short name T354
Test name
Test status
Simulation time 6602762991 ps
CPU time 16.57 seconds
Started Jul 15 05:28:26 PM PDT 24
Finished Jul 15 05:28:43 PM PDT 24
Peak memory 217124 kb
Host smart-a4fd209e-8e12-4fc7-9d9f-5854fe395378
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585428254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3585428254
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.444664912
Short name T462
Test name
Test status
Simulation time 14116906484 ps
CPU time 91.22 seconds
Started Jul 15 05:28:29 PM PDT 24
Finished Jul 15 05:30:02 PM PDT 24
Peak memory 219044 kb
Host smart-920e2001-05d9-4138-8384-925eaad402c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444664912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er
rors.444664912
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.4081732071
Short name T216
Test name
Test status
Simulation time 330397963 ps
CPU time 5.37 seconds
Started Jul 15 05:28:26 PM PDT 24
Finished Jul 15 05:28:32 PM PDT 24
Peak memory 217656 kb
Host smart-17053e08-c44d-447b-b5e0-0e9d943f3e47
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081732071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.4081732071
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1909895978
Short name T383
Test name
Test status
Simulation time 4090687909 ps
CPU time 5.69 seconds
Started Jul 15 05:28:30 PM PDT 24
Finished Jul 15 05:28:37 PM PDT 24
Peak memory 217076 kb
Host smart-87877f37-b418-40a2-8f7b-4d1f6c098087
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909895978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1909895978
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.123837196
Short name T338
Test name
Test status
Simulation time 5780002597 ps
CPU time 54.45 seconds
Started Jul 15 05:28:29 PM PDT 24
Finished Jul 15 05:29:25 PM PDT 24
Peak memory 275020 kb
Host smart-c3e058c9-f41b-41aa-a89b-897e036e4c24
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123837196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.123837196
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1505330081
Short name T620
Test name
Test status
Simulation time 2162393486 ps
CPU time 12.79 seconds
Started Jul 15 05:28:26 PM PDT 24
Finished Jul 15 05:28:39 PM PDT 24
Peak memory 221772 kb
Host smart-708a0960-3128-4252-80f5-0ac2f354b949
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505330081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1505330081
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2686227586
Short name T474
Test name
Test status
Simulation time 94804256 ps
CPU time 2.33 seconds
Started Jul 15 05:28:28 PM PDT 24
Finished Jul 15 05:28:33 PM PDT 24
Peak memory 217696 kb
Host smart-efc7142e-3eef-4450-a907-6e1db37530ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686227586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2686227586
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2429686123
Short name T818
Test name
Test status
Simulation time 5077391091 ps
CPU time 12.71 seconds
Started Jul 15 05:28:36 PM PDT 24
Finished Jul 15 05:28:50 PM PDT 24
Peak memory 225600 kb
Host smart-b2c4632b-e0f5-4fc8-a7e3-2573d7bbd3e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429686123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2429686123
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.902884027
Short name T322
Test name
Test status
Simulation time 347892333 ps
CPU time 12.25 seconds
Started Jul 15 05:28:38 PM PDT 24
Finished Jul 15 05:28:51 PM PDT 24
Peak memory 225360 kb
Host smart-aff2408c-3c7c-4357-a9f5-18dd00f04f96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902884027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.902884027
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.4230112492
Short name T578
Test name
Test status
Simulation time 678504103 ps
CPU time 12.81 seconds
Started Jul 15 05:28:36 PM PDT 24
Finished Jul 15 05:28:49 PM PDT 24
Peak memory 225360 kb
Host smart-2f8fb894-3b62-4fd2-932b-7cd3d29855dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230112492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
4230112492
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.940834825
Short name T371
Test name
Test status
Simulation time 384414173 ps
CPU time 14.07 seconds
Started Jul 15 05:28:30 PM PDT 24
Finished Jul 15 05:28:45 PM PDT 24
Peak memory 225496 kb
Host smart-f107dad5-1b9a-4f5e-acb6-f8a511ae4113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940834825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.940834825
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.649484484
Short name T685
Test name
Test status
Simulation time 41956254 ps
CPU time 1.54 seconds
Started Jul 15 05:28:29 PM PDT 24
Finished Jul 15 05:28:32 PM PDT 24
Peak memory 213312 kb
Host smart-422cedd9-f285-46a1-a1cf-d41b5a100862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649484484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.649484484
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2376262566
Short name T420
Test name
Test status
Simulation time 360890021 ps
CPU time 16.3 seconds
Started Jul 15 05:28:28 PM PDT 24
Finished Jul 15 05:28:47 PM PDT 24
Peak memory 250488 kb
Host smart-69879126-f1ec-4d15-919c-847b9d0c198e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376262566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2376262566
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.141549027
Short name T154
Test name
Test status
Simulation time 87476373 ps
CPU time 7.14 seconds
Started Jul 15 05:28:27 PM PDT 24
Finished Jul 15 05:28:34 PM PDT 24
Peak memory 246180 kb
Host smart-74ddcba9-fe9b-4c1e-90ca-031cb1773e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141549027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.141549027
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1100321013
Short name T161
Test name
Test status
Simulation time 36868433720 ps
CPU time 294.4 seconds
Started Jul 15 05:28:35 PM PDT 24
Finished Jul 15 05:33:30 PM PDT 24
Peak memory 274376 kb
Host smart-35729263-ccfd-433b-87e4-d8dcf2772e2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100321013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1100321013
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2989383033
Short name T39
Test name
Test status
Simulation time 31481907 ps
CPU time 0.98 seconds
Started Jul 15 05:28:27 PM PDT 24
Finished Jul 15 05:28:29 PM PDT 24
Peak memory 208340 kb
Host smart-7ed7bc80-ea88-4324-adfe-d60070d07c8a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989383033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2989383033
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1333987842
Short name T331
Test name
Test status
Simulation time 20282223 ps
CPU time 1.29 seconds
Started Jul 15 05:28:35 PM PDT 24
Finished Jul 15 05:28:37 PM PDT 24
Peak memory 208396 kb
Host smart-4a438900-8f2e-4b5a-8e7f-dcfbfc9e9551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333987842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1333987842
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1469106800
Short name T213
Test name
Test status
Simulation time 1601364660 ps
CPU time 14.93 seconds
Started Jul 15 05:28:36 PM PDT 24
Finished Jul 15 05:28:51 PM PDT 24
Peak memory 217648 kb
Host smart-540d2efe-74ef-4d7f-adca-0a0a6024f5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469106800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1469106800
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.178326424
Short name T544
Test name
Test status
Simulation time 1584050502 ps
CPU time 11.49 seconds
Started Jul 15 05:28:36 PM PDT 24
Finished Jul 15 05:28:48 PM PDT 24
Peak memory 217048 kb
Host smart-81d987cb-afef-4bf8-8108-5fbc8f1ec24b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178326424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.178326424
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.820786489
Short name T323
Test name
Test status
Simulation time 8427928471 ps
CPU time 40.23 seconds
Started Jul 15 05:28:34 PM PDT 24
Finished Jul 15 05:29:15 PM PDT 24
Peak memory 217660 kb
Host smart-1b7bb275-7b69-4f37-baf5-4e01aa9f113e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820786489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.820786489
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1450922606
Short name T434
Test name
Test status
Simulation time 505715510 ps
CPU time 7.88 seconds
Started Jul 15 05:28:35 PM PDT 24
Finished Jul 15 05:28:44 PM PDT 24
Peak memory 217596 kb
Host smart-8a3f3815-ae74-4f1b-b7dc-0c2a23f32546
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450922606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1450922606
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.610560784
Short name T751
Test name
Test status
Simulation time 950440362 ps
CPU time 4.43 seconds
Started Jul 15 05:28:35 PM PDT 24
Finished Jul 15 05:28:41 PM PDT 24
Peak memory 217080 kb
Host smart-dab82a48-f422-48c9-b2a2-f32498664ff8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610560784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
610560784
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3031373695
Short name T215
Test name
Test status
Simulation time 3511233940 ps
CPU time 36.54 seconds
Started Jul 15 05:28:35 PM PDT 24
Finished Jul 15 05:29:12 PM PDT 24
Peak memory 275004 kb
Host smart-7b8e1bee-dbf9-4287-9013-4a816d333282
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031373695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3031373695
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1943226630
Short name T444
Test name
Test status
Simulation time 656558984 ps
CPU time 23.24 seconds
Started Jul 15 05:28:37 PM PDT 24
Finished Jul 15 05:29:01 PM PDT 24
Peak memory 247068 kb
Host smart-6b971ade-7c1a-40aa-9b93-570941eff9a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943226630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.1943226630
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2986772945
Short name T205
Test name
Test status
Simulation time 973020997 ps
CPU time 3.77 seconds
Started Jul 15 05:28:36 PM PDT 24
Finished Jul 15 05:28:41 PM PDT 24
Peak memory 221872 kb
Host smart-c7c947b9-9fcf-4c1c-9c34-d41a617ebd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986772945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2986772945
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.3557298484
Short name T577
Test name
Test status
Simulation time 2641314947 ps
CPU time 16.3 seconds
Started Jul 15 05:28:37 PM PDT 24
Finished Jul 15 05:28:54 PM PDT 24
Peak memory 225448 kb
Host smart-9a00453f-e7d2-4faf-89fd-53d048c5ed14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557298484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.3557298484
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1863238885
Short name T672
Test name
Test status
Simulation time 5802183724 ps
CPU time 9.27 seconds
Started Jul 15 05:28:41 PM PDT 24
Finished Jul 15 05:28:51 PM PDT 24
Peak memory 217672 kb
Host smart-cbe09a3b-683a-46f1-88e7-2a5cfc7033b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863238885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
1863238885
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3023145053
Short name T285
Test name
Test status
Simulation time 303943693 ps
CPU time 12.24 seconds
Started Jul 15 05:28:36 PM PDT 24
Finished Jul 15 05:28:49 PM PDT 24
Peak memory 224992 kb
Host smart-a120953c-8964-485f-bbbc-d3d8be3df4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023145053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3023145053
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3915858762
Short name T350
Test name
Test status
Simulation time 262119992 ps
CPU time 6.1 seconds
Started Jul 15 05:28:38 PM PDT 24
Finished Jul 15 05:28:45 PM PDT 24
Peak memory 217044 kb
Host smart-e5ac45ed-1bd6-4d45-9bec-5b301fb6dcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915858762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3915858762
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3709384624
Short name T712
Test name
Test status
Simulation time 456716120 ps
CPU time 24.51 seconds
Started Jul 15 05:28:41 PM PDT 24
Finished Jul 15 05:29:06 PM PDT 24
Peak memory 250420 kb
Host smart-da6c4b26-a3c7-4499-a669-70df0a65b21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709384624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3709384624
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3975423243
Short name T763
Test name
Test status
Simulation time 45540493 ps
CPU time 6.46 seconds
Started Jul 15 05:28:35 PM PDT 24
Finished Jul 15 05:28:42 PM PDT 24
Peak memory 249824 kb
Host smart-8dcb7ef9-de6f-44e2-a50d-be68b5527822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975423243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3975423243
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1695092430
Short name T345
Test name
Test status
Simulation time 1151014082 ps
CPU time 8.59 seconds
Started Jul 15 05:28:36 PM PDT 24
Finished Jul 15 05:28:46 PM PDT 24
Peak memory 225916 kb
Host smart-8eb42388-e899-4194-b358-33c0d0c5d4b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695092430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1695092430
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3688474743
Short name T69
Test name
Test status
Simulation time 17336871 ps
CPU time 1.13 seconds
Started Jul 15 05:28:37 PM PDT 24
Finished Jul 15 05:28:39 PM PDT 24
Peak memory 217100 kb
Host smart-ace69231-6132-440c-a080-790bdb571258
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688474743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3688474743
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.323237442
Short name T619
Test name
Test status
Simulation time 19434960 ps
CPU time 1.15 seconds
Started Jul 15 05:28:44 PM PDT 24
Finished Jul 15 05:28:46 PM PDT 24
Peak memory 208396 kb
Host smart-60a24798-6b99-46fc-949a-3e07d5d9b67e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323237442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.323237442
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.690992242
Short name T43
Test name
Test status
Simulation time 1311417611 ps
CPU time 14.08 seconds
Started Jul 15 05:28:43 PM PDT 24
Finished Jul 15 05:28:58 PM PDT 24
Peak memory 217752 kb
Host smart-108c50d8-1222-427d-9954-e006de990265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690992242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.690992242
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3630913318
Short name T480
Test name
Test status
Simulation time 4769131948 ps
CPU time 6.69 seconds
Started Jul 15 05:28:48 PM PDT 24
Finished Jul 15 05:28:55 PM PDT 24
Peak memory 217220 kb
Host smart-0bdea1b9-71fc-4861-98f9-23c8370814b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630913318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3630913318
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.4151003284
Short name T365
Test name
Test status
Simulation time 4286492096 ps
CPU time 40.64 seconds
Started Jul 15 05:28:42 PM PDT 24
Finished Jul 15 05:29:23 PM PDT 24
Peak memory 218264 kb
Host smart-7be45523-5aac-4c82-84bf-f0546ef9a6eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151003284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.4151003284
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.816048638
Short name T399
Test name
Test status
Simulation time 169892868 ps
CPU time 5.36 seconds
Started Jul 15 05:28:44 PM PDT 24
Finished Jul 15 05:28:50 PM PDT 24
Peak memory 217632 kb
Host smart-98b36dcf-4c76-4168-b01c-2dd7e55f23ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816048638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.816048638
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.125140601
Short name T547
Test name
Test status
Simulation time 87535099 ps
CPU time 2.97 seconds
Started Jul 15 05:28:43 PM PDT 24
Finished Jul 15 05:28:47 PM PDT 24
Peak memory 217084 kb
Host smart-19d15f81-8854-488d-a297-bfcf0e18d90a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125140601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
125140601
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.265576540
Short name T144
Test name
Test status
Simulation time 7048956988 ps
CPU time 36.34 seconds
Started Jul 15 05:28:44 PM PDT 24
Finished Jul 15 05:29:21 PM PDT 24
Peak memory 250420 kb
Host smart-996c807d-7c15-4483-894c-1f8a69233138
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265576540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.265576540
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1230665735
Short name T526
Test name
Test status
Simulation time 604405347 ps
CPU time 14.43 seconds
Started Jul 15 05:28:44 PM PDT 24
Finished Jul 15 05:28:59 PM PDT 24
Peak memory 248892 kb
Host smart-5470ce6d-a563-472b-b20b-9f295ee83440
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230665735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1230665735
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1281621574
Short name T698
Test name
Test status
Simulation time 195611235 ps
CPU time 2.28 seconds
Started Jul 15 05:28:42 PM PDT 24
Finished Jul 15 05:28:46 PM PDT 24
Peak memory 217628 kb
Host smart-1b23ceb0-7e39-4a90-b21b-1c9129f61db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281621574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1281621574
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.40555152
Short name T408
Test name
Test status
Simulation time 2530955367 ps
CPU time 11.02 seconds
Started Jul 15 05:28:47 PM PDT 24
Finished Jul 15 05:28:59 PM PDT 24
Peak memory 225536 kb
Host smart-a287e7e2-88a3-4c55-9061-c5964f85fadc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40555152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.40555152
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2140701354
Short name T757
Test name
Test status
Simulation time 244838389 ps
CPU time 9.3 seconds
Started Jul 15 05:28:44 PM PDT 24
Finished Jul 15 05:28:54 PM PDT 24
Peak memory 225480 kb
Host smart-5dcbd3bd-ea90-4568-afc1-fb1e84f5c822
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140701354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2140701354
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.315252963
Short name T520
Test name
Test status
Simulation time 1315236951 ps
CPU time 13.51 seconds
Started Jul 15 05:28:42 PM PDT 24
Finished Jul 15 05:28:57 PM PDT 24
Peak memory 225380 kb
Host smart-9ed5657d-036b-4716-88bf-1d6e69cd296d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315252963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.315252963
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.774948850
Short name T164
Test name
Test status
Simulation time 1649926141 ps
CPU time 14.86 seconds
Started Jul 15 05:28:44 PM PDT 24
Finished Jul 15 05:28:59 PM PDT 24
Peak memory 224484 kb
Host smart-c5f47da5-8a08-4313-b5f1-831155e0169a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774948850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.774948850
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3837974962
Short name T283
Test name
Test status
Simulation time 230426712 ps
CPU time 2.72 seconds
Started Jul 15 05:28:45 PM PDT 24
Finished Jul 15 05:28:49 PM PDT 24
Peak memory 214184 kb
Host smart-44c7ad2a-e90c-46cb-9df4-679fc56d36e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837974962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3837974962
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.236151171
Short name T676
Test name
Test status
Simulation time 491111356 ps
CPU time 24.67 seconds
Started Jul 15 05:28:43 PM PDT 24
Finished Jul 15 05:29:08 PM PDT 24
Peak memory 250464 kb
Host smart-55fd2133-fcfb-4678-935a-ea18cb1747c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236151171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.236151171
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.559086698
Short name T769
Test name
Test status
Simulation time 481764509 ps
CPU time 6.36 seconds
Started Jul 15 05:28:46 PM PDT 24
Finished Jul 15 05:28:53 PM PDT 24
Peak memory 250348 kb
Host smart-5cee553a-54bc-4a78-8d31-de727929b4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559086698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.559086698
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2816249062
Short name T305
Test name
Test status
Simulation time 31882649574 ps
CPU time 66.17 seconds
Started Jul 15 05:28:46 PM PDT 24
Finished Jul 15 05:29:52 PM PDT 24
Peak memory 250512 kb
Host smart-f91d6b9c-ee21-4f2f-b89b-1bb06cf9e184
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816249062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2816249062
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.1390944129
Short name T143
Test name
Test status
Simulation time 38255403843 ps
CPU time 1199.46 seconds
Started Jul 15 05:28:42 PM PDT 24
Finished Jul 15 05:48:42 PM PDT 24
Peak memory 643740 kb
Host smart-7bf3601d-4495-444f-af83-15f16e9f767e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1390944129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.1390944129
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.627514374
Short name T845
Test name
Test status
Simulation time 21236826 ps
CPU time 0.9 seconds
Started Jul 15 05:28:45 PM PDT 24
Finished Jul 15 05:28:46 PM PDT 24
Peak memory 208536 kb
Host smart-fb969ddd-d109-4756-be6b-d893eab6538d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627514374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.627514374
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.96968737
Short name T271
Test name
Test status
Simulation time 18953057 ps
CPU time 0.94 seconds
Started Jul 15 05:28:50 PM PDT 24
Finished Jul 15 05:28:52 PM PDT 24
Peak memory 208404 kb
Host smart-73ee2f81-853c-4386-930d-419c3ef6b8e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96968737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.96968737
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3929736085
Short name T515
Test name
Test status
Simulation time 1497638325 ps
CPU time 8.5 seconds
Started Jul 15 05:28:55 PM PDT 24
Finished Jul 15 05:29:04 PM PDT 24
Peak memory 217660 kb
Host smart-bb77ec6d-8051-4328-94dd-ba4ce4d5736d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929736085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3929736085
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.84034021
Short name T8
Test name
Test status
Simulation time 12464724485 ps
CPU time 13.08 seconds
Started Jul 15 05:28:48 PM PDT 24
Finished Jul 15 05:29:02 PM PDT 24
Peak memory 217044 kb
Host smart-c7ace1de-3432-4342-a2e6-197cbe6d4074
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84034021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.84034021
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2320388719
Short name T513
Test name
Test status
Simulation time 13419617045 ps
CPU time 33.85 seconds
Started Jul 15 05:29:09 PM PDT 24
Finished Jul 15 05:29:43 PM PDT 24
Peak memory 217724 kb
Host smart-28e7528b-ebdf-4375-b508-8477e47e9b1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320388719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2320388719
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3801360662
Short name T831
Test name
Test status
Simulation time 1579704975 ps
CPU time 7.19 seconds
Started Jul 15 05:28:49 PM PDT 24
Finished Jul 15 05:28:57 PM PDT 24
Peak memory 217608 kb
Host smart-67b5aa91-c683-4bb7-a53d-0d73d7dd27c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801360662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3801360662
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2991834745
Short name T21
Test name
Test status
Simulation time 128034305 ps
CPU time 3.33 seconds
Started Jul 15 05:28:49 PM PDT 24
Finished Jul 15 05:28:54 PM PDT 24
Peak memory 217072 kb
Host smart-50892d25-b5fa-4ef6-b7ba-e9350e144190
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991834745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2991834745
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.637775058
Short name T380
Test name
Test status
Simulation time 5435921591 ps
CPU time 38.22 seconds
Started Jul 15 05:28:49 PM PDT 24
Finished Jul 15 05:29:28 PM PDT 24
Peak memory 250976 kb
Host smart-25b0955a-33c2-4fae-aded-5c61c9a8414d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637775058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.637775058
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3502676085
Short name T334
Test name
Test status
Simulation time 382644480 ps
CPU time 11.21 seconds
Started Jul 15 05:28:50 PM PDT 24
Finished Jul 15 05:29:02 PM PDT 24
Peak memory 250140 kb
Host smart-dde4a138-04e0-4e8d-a251-2a52680776f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502676085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3502676085
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3403954138
Short name T764
Test name
Test status
Simulation time 365200833 ps
CPU time 2.66 seconds
Started Jul 15 05:28:49 PM PDT 24
Finished Jul 15 05:28:52 PM PDT 24
Peak memory 217760 kb
Host smart-659affdb-7e15-46db-92ed-d9e0f661e165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403954138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3403954138
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2856326698
Short name T346
Test name
Test status
Simulation time 173539017 ps
CPU time 9.4 seconds
Started Jul 15 05:28:54 PM PDT 24
Finished Jul 15 05:29:05 PM PDT 24
Peak memory 225448 kb
Host smart-22036f23-6d6f-45f6-b8c5-f5a5c764776c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856326698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2856326698
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1709130779
Short name T699
Test name
Test status
Simulation time 1320044831 ps
CPU time 13.47 seconds
Started Jul 15 05:28:49 PM PDT 24
Finished Jul 15 05:29:03 PM PDT 24
Peak memory 217556 kb
Host smart-22b5b356-298e-4169-9fd2-2cb1c636aea6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709130779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1709130779
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2206379854
Short name T774
Test name
Test status
Simulation time 1462487209 ps
CPU time 8.79 seconds
Started Jul 15 05:28:49 PM PDT 24
Finished Jul 15 05:28:59 PM PDT 24
Peak memory 217624 kb
Host smart-06c63761-9a2b-4b8f-b933-9222dc88e8a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206379854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2206379854
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1893375327
Short name T696
Test name
Test status
Simulation time 1461987344 ps
CPU time 7.8 seconds
Started Jul 15 05:28:53 PM PDT 24
Finished Jul 15 05:29:02 PM PDT 24
Peak memory 224192 kb
Host smart-3f8c69ef-f27f-44db-9197-4ff35145bce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893375327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1893375327
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1995280557
Short name T510
Test name
Test status
Simulation time 154301894 ps
CPU time 3.2 seconds
Started Jul 15 05:28:41 PM PDT 24
Finished Jul 15 05:28:45 PM PDT 24
Peak memory 214152 kb
Host smart-2df4a908-c3a1-4294-a0cc-88125bcea74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995280557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1995280557
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.630433631
Short name T279
Test name
Test status
Simulation time 203802171 ps
CPU time 19.42 seconds
Started Jul 15 05:28:43 PM PDT 24
Finished Jul 15 05:29:03 PM PDT 24
Peak memory 250476 kb
Host smart-58868bad-61a7-46cf-b2e6-55455faf9cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630433631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.630433631
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3412566713
Short name T410
Test name
Test status
Simulation time 152355969 ps
CPU time 6.84 seconds
Started Jul 15 05:28:50 PM PDT 24
Finished Jul 15 05:28:57 PM PDT 24
Peak memory 249856 kb
Host smart-285e047f-e7cb-45bf-b66e-e1819c700b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412566713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3412566713
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1570625737
Short name T487
Test name
Test status
Simulation time 22733351 ps
CPU time 0.93 seconds
Started Jul 15 05:28:42 PM PDT 24
Finished Jul 15 05:28:43 PM PDT 24
Peak memory 208528 kb
Host smart-9548352a-7500-4ffa-95d5-762568386fb9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570625737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.1570625737
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1244321844
Short name T706
Test name
Test status
Simulation time 69760629 ps
CPU time 1.19 seconds
Started Jul 15 05:28:58 PM PDT 24
Finished Jul 15 05:29:00 PM PDT 24
Peak memory 208544 kb
Host smart-423ebcf7-9303-4320-ac11-f2d25183df68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244321844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1244321844
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2752270480
Short name T800
Test name
Test status
Simulation time 238602358 ps
CPU time 10.8 seconds
Started Jul 15 05:28:57 PM PDT 24
Finished Jul 15 05:29:09 PM PDT 24
Peak memory 225544 kb
Host smart-c38b86fa-26ab-4e2d-93fe-ae200274fe8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752270480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2752270480
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3574733429
Short name T724
Test name
Test status
Simulation time 2791971729 ps
CPU time 6.62 seconds
Started Jul 15 05:28:57 PM PDT 24
Finished Jul 15 05:29:05 PM PDT 24
Peak memory 217200 kb
Host smart-019046ef-c713-422b-9618-c92538331568
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574733429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3574733429
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.4123419541
Short name T41
Test name
Test status
Simulation time 1258421387 ps
CPU time 37.81 seconds
Started Jul 15 05:28:55 PM PDT 24
Finished Jul 15 05:29:34 PM PDT 24
Peak memory 218232 kb
Host smart-ba281fc8-790e-4414-a131-5556aec58ae3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123419541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.4123419541
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3061939704
Short name T707
Test name
Test status
Simulation time 632176911 ps
CPU time 19.01 seconds
Started Jul 15 05:28:56 PM PDT 24
Finished Jul 15 05:29:16 PM PDT 24
Peak memory 223928 kb
Host smart-4834c8d3-882a-4fe9-a374-37878a576b7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061939704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.3061939704
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3712208156
Short name T435
Test name
Test status
Simulation time 1183392537 ps
CPU time 5.8 seconds
Started Jul 15 05:29:01 PM PDT 24
Finished Jul 15 05:29:07 PM PDT 24
Peak memory 217052 kb
Host smart-245d4199-b7cc-4352-b9d9-4a6c4f71fc4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712208156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3712208156
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1005409596
Short name T326
Test name
Test status
Simulation time 8295420265 ps
CPU time 37.88 seconds
Started Jul 15 05:28:55 PM PDT 24
Finished Jul 15 05:29:34 PM PDT 24
Peak memory 267180 kb
Host smart-4cabc63e-d66c-4041-b230-ad3316ec7b0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005409596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1005409596
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.4090584853
Short name T479
Test name
Test status
Simulation time 4206733705 ps
CPU time 13.57 seconds
Started Jul 15 05:28:57 PM PDT 24
Finished Jul 15 05:29:12 PM PDT 24
Peak memory 250420 kb
Host smart-8681aaf5-a3e6-4234-9597-e3816652ed5f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090584853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.4090584853
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3230437658
Short name T729
Test name
Test status
Simulation time 30263160 ps
CPU time 1.82 seconds
Started Jul 15 05:28:58 PM PDT 24
Finished Jul 15 05:29:01 PM PDT 24
Peak memory 217724 kb
Host smart-eecd2ac3-1751-44af-a732-7d0c915ef7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230437658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3230437658
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3215796979
Short name T705
Test name
Test status
Simulation time 549920816 ps
CPU time 10.96 seconds
Started Jul 15 05:28:56 PM PDT 24
Finished Jul 15 05:29:08 PM PDT 24
Peak memory 225456 kb
Host smart-cde13f02-957f-48f6-b5b8-149f9d134dff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215796979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3215796979
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2892940872
Short name T541
Test name
Test status
Simulation time 1041015750 ps
CPU time 12.21 seconds
Started Jul 15 05:28:57 PM PDT 24
Finished Jul 15 05:29:09 PM PDT 24
Peak memory 225444 kb
Host smart-a2612b00-36e2-4b24-ac69-8956bc9ed221
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892940872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2892940872
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3487426330
Short name T835
Test name
Test status
Simulation time 461576248 ps
CPU time 9.48 seconds
Started Jul 15 05:28:58 PM PDT 24
Finished Jul 15 05:29:08 PM PDT 24
Peak memory 217660 kb
Host smart-df294b14-541a-4a71-9801-dabe2970b66b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487426330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
3487426330
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2831648914
Short name T82
Test name
Test status
Simulation time 351374368 ps
CPU time 3.18 seconds
Started Jul 15 05:28:50 PM PDT 24
Finished Jul 15 05:28:54 PM PDT 24
Peak memory 223592 kb
Host smart-93a19331-7d08-4aa0-a0a4-c7f11ee5f03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831648914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2831648914
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2231723155
Short name T834
Test name
Test status
Simulation time 156543397 ps
CPU time 21.77 seconds
Started Jul 15 05:28:54 PM PDT 24
Finished Jul 15 05:29:17 PM PDT 24
Peak memory 250476 kb
Host smart-6f40e73c-585e-4cb1-a106-a4dc5e62d6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231723155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2231723155
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3430044940
Short name T805
Test name
Test status
Simulation time 391410333 ps
CPU time 8.29 seconds
Started Jul 15 05:28:50 PM PDT 24
Finished Jul 15 05:28:59 PM PDT 24
Peak memory 250488 kb
Host smart-5bc51484-eb93-4a5b-abab-c6df416ab654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430044940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3430044940
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1941694550
Short name T549
Test name
Test status
Simulation time 13653989431 ps
CPU time 67.48 seconds
Started Jul 15 05:28:59 PM PDT 24
Finished Jul 15 05:30:07 PM PDT 24
Peak memory 250608 kb
Host smart-ad16c98b-abd0-439b-a613-636a907fd391
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941694550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1941694550
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.90110665
Short name T321
Test name
Test status
Simulation time 94024983 ps
CPU time 1.03 seconds
Started Jul 15 05:26:55 PM PDT 24
Finished Jul 15 05:26:57 PM PDT 24
Peak memory 208344 kb
Host smart-a7e5952b-1e82-443a-b47d-7a33eb4c87fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90110665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.90110665
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3469390218
Short name T31
Test name
Test status
Simulation time 28616594 ps
CPU time 0.82 seconds
Started Jul 15 05:26:46 PM PDT 24
Finished Jul 15 05:26:48 PM PDT 24
Peak memory 208452 kb
Host smart-447d25f0-2771-4e49-85f3-88305d0eae63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469390218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3469390218
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2667724933
Short name T251
Test name
Test status
Simulation time 1725983181 ps
CPU time 11.95 seconds
Started Jul 15 05:26:50 PM PDT 24
Finished Jul 15 05:27:02 PM PDT 24
Peak memory 217632 kb
Host smart-6474a8d4-8799-475c-8c64-08bafcdc3e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667724933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2667724933
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.804011727
Short name T163
Test name
Test status
Simulation time 171023474 ps
CPU time 1.84 seconds
Started Jul 15 05:26:47 PM PDT 24
Finished Jul 15 05:26:50 PM PDT 24
Peak memory 216496 kb
Host smart-5fba6bba-71df-48ee-ad4c-e42a40606031
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804011727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.804011727
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.4210607802
Short name T217
Test name
Test status
Simulation time 1589995699 ps
CPU time 50.04 seconds
Started Jul 15 05:26:46 PM PDT 24
Finished Jul 15 05:27:37 PM PDT 24
Peak memory 217584 kb
Host smart-c9cd9bd5-9327-450e-abd5-44482063b84e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210607802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.4210607802
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.326377001
Short name T343
Test name
Test status
Simulation time 809197329 ps
CPU time 4.94 seconds
Started Jul 15 05:26:47 PM PDT 24
Finished Jul 15 05:26:53 PM PDT 24
Peak memory 217072 kb
Host smart-e22ca134-d2dd-4d5e-bd57-ab383d24eb63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326377001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.326377001
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1244596489
Short name T665
Test name
Test status
Simulation time 1878332890 ps
CPU time 7.65 seconds
Started Jul 15 05:26:48 PM PDT 24
Finished Jul 15 05:26:56 PM PDT 24
Peak memory 217564 kb
Host smart-f5aabc24-5537-45cf-9f04-69104ebefd8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244596489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.1244596489
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2092010500
Short name T715
Test name
Test status
Simulation time 10038623886 ps
CPU time 36.43 seconds
Started Jul 15 05:26:47 PM PDT 24
Finished Jul 15 05:27:24 PM PDT 24
Peak memory 217120 kb
Host smart-1509207d-817b-4732-b30c-e53798cfa02f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092010500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2092010500
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.795861317
Short name T72
Test name
Test status
Simulation time 220092124 ps
CPU time 3.33 seconds
Started Jul 15 05:26:46 PM PDT 24
Finished Jul 15 05:26:49 PM PDT 24
Peak memory 217016 kb
Host smart-d181d4f2-7a84-4471-b77b-e26c5fe320a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795861317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.795861317
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.4045477328
Short name T836
Test name
Test status
Simulation time 3121559460 ps
CPU time 42.75 seconds
Started Jul 15 05:26:50 PM PDT 24
Finished Jul 15 05:27:33 PM PDT 24
Peak memory 274944 kb
Host smart-1b49c6a1-5e74-4bac-b1fa-b76fe215c19d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045477328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.4045477328
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.875281827
Short name T581
Test name
Test status
Simulation time 4355484777 ps
CPU time 41.39 seconds
Started Jul 15 05:26:47 PM PDT 24
Finished Jul 15 05:27:30 PM PDT 24
Peak memory 250344 kb
Host smart-9457ba49-614e-465c-a5d2-3f03f9c3ab1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875281827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.875281827
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2942490201
Short name T168
Test name
Test status
Simulation time 164442835 ps
CPU time 2.38 seconds
Started Jul 15 05:26:47 PM PDT 24
Finished Jul 15 05:26:50 PM PDT 24
Peak memory 217740 kb
Host smart-25546105-f969-41ca-ab7f-e7b48fb981d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942490201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2942490201
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.779098922
Short name T832
Test name
Test status
Simulation time 415249262 ps
CPU time 7.7 seconds
Started Jul 15 05:26:48 PM PDT 24
Finished Jul 15 05:26:56 PM PDT 24
Peak memory 216984 kb
Host smart-355b6071-5de1-48e9-93ec-92d230cc5a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779098922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.779098922
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1089022209
Short name T508
Test name
Test status
Simulation time 220445614 ps
CPU time 9.08 seconds
Started Jul 15 05:26:47 PM PDT 24
Finished Jul 15 05:26:56 PM PDT 24
Peak memory 218312 kb
Host smart-d6d2fc7a-0c76-4052-9ca8-766f8faf0a4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089022209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1089022209
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1381034616
Short name T858
Test name
Test status
Simulation time 368376731 ps
CPU time 15.89 seconds
Started Jul 15 05:26:58 PM PDT 24
Finished Jul 15 05:27:14 PM PDT 24
Peak memory 225364 kb
Host smart-9ca2294a-ce1a-4db5-982f-c8db70274085
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381034616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1381034616
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.4107355919
Short name T551
Test name
Test status
Simulation time 570044617 ps
CPU time 11.29 seconds
Started Jul 15 05:26:47 PM PDT 24
Finished Jul 15 05:26:59 PM PDT 24
Peak memory 217592 kb
Host smart-a212b780-7e6f-4c24-bce1-5392386c30ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107355919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.4
107355919
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3605293425
Short name T649
Test name
Test status
Simulation time 1241210534 ps
CPU time 9.34 seconds
Started Jul 15 05:26:46 PM PDT 24
Finished Jul 15 05:26:56 PM PDT 24
Peak memory 217760 kb
Host smart-8efb1034-ec6d-418a-b41b-801b8516a13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605293425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3605293425
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3342764873
Short name T214
Test name
Test status
Simulation time 367484514 ps
CPU time 1.78 seconds
Started Jul 15 05:26:42 PM PDT 24
Finished Jul 15 05:26:44 PM PDT 24
Peak memory 217144 kb
Host smart-c0706a72-44e5-4698-8c4b-a2b9876fc46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342764873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3342764873
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.59733488
Short name T614
Test name
Test status
Simulation time 331033869 ps
CPU time 35.36 seconds
Started Jul 15 05:26:42 PM PDT 24
Finished Jul 15 05:27:18 PM PDT 24
Peak memory 250544 kb
Host smart-ddcf60df-d347-4291-ad0a-1fcc73b5627d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59733488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.59733488
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3314119529
Short name T247
Test name
Test status
Simulation time 74775459 ps
CPU time 7.53 seconds
Started Jul 15 05:26:40 PM PDT 24
Finished Jul 15 05:26:49 PM PDT 24
Peak memory 250364 kb
Host smart-261005cd-23e0-4ee5-9411-a74fa36d9345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314119529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3314119529
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.3530999198
Short name T270
Test name
Test status
Simulation time 14914503636 ps
CPU time 436.24 seconds
Started Jul 15 05:26:55 PM PDT 24
Finished Jul 15 05:34:12 PM PDT 24
Peak memory 258796 kb
Host smart-8ee8ddc3-16c4-4cd7-b507-677dfb220e27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530999198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.3530999198
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.958538669
Short name T141
Test name
Test status
Simulation time 35469436123 ps
CPU time 1222.01 seconds
Started Jul 15 05:26:54 PM PDT 24
Finished Jul 15 05:47:17 PM PDT 24
Peak memory 438048 kb
Host smart-a6c340e7-1682-448c-b880-c2f0df63c756
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=958538669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.958538669
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1901839327
Short name T704
Test name
Test status
Simulation time 13930090 ps
CPU time 0.98 seconds
Started Jul 15 05:26:42 PM PDT 24
Finished Jul 15 05:26:44 PM PDT 24
Peak memory 208400 kb
Host smart-88562990-1bb7-4ab1-a9e9-19380e3b7813
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901839327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1901839327
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3574334247
Short name T583
Test name
Test status
Simulation time 54459983 ps
CPU time 1.1 seconds
Started Jul 15 05:29:03 PM PDT 24
Finished Jul 15 05:29:05 PM PDT 24
Peak memory 208588 kb
Host smart-a8524b8e-0a7b-4a06-ab70-61c7e224bbea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574334247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3574334247
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1763234879
Short name T220
Test name
Test status
Simulation time 358824446 ps
CPU time 15.08 seconds
Started Jul 15 05:29:07 PM PDT 24
Finished Jul 15 05:29:22 PM PDT 24
Peak memory 217732 kb
Host smart-e3a2e2f2-4034-4298-957f-7e7154628476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763234879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1763234879
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2198507269
Short name T535
Test name
Test status
Simulation time 730234866 ps
CPU time 6.42 seconds
Started Jul 15 05:29:03 PM PDT 24
Finished Jul 15 05:29:10 PM PDT 24
Peak memory 217152 kb
Host smart-57fe7ac0-4e93-4b95-88d6-c1c0cf672bc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198507269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2198507269
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.3869072153
Short name T291
Test name
Test status
Simulation time 192566555 ps
CPU time 4.24 seconds
Started Jul 15 05:29:06 PM PDT 24
Finished Jul 15 05:29:11 PM PDT 24
Peak memory 217636 kb
Host smart-c8c85b33-c21e-45ec-b514-287334cde909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869072153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3869072153
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2715996695
Short name T794
Test name
Test status
Simulation time 625260377 ps
CPU time 17.13 seconds
Started Jul 15 05:29:03 PM PDT 24
Finished Jul 15 05:29:21 PM PDT 24
Peak memory 219388 kb
Host smart-e274090f-2c9d-42ab-8162-9d48e3c306a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715996695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2715996695
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1811317302
Short name T385
Test name
Test status
Simulation time 1102265664 ps
CPU time 19.81 seconds
Started Jul 15 05:29:05 PM PDT 24
Finished Jul 15 05:29:25 PM PDT 24
Peak memory 225376 kb
Host smart-2e490933-3030-42df-9258-f58f78388da8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811317302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.1811317302
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2158147133
Short name T803
Test name
Test status
Simulation time 188705359 ps
CPU time 6.35 seconds
Started Jul 15 05:29:03 PM PDT 24
Finished Jul 15 05:29:11 PM PDT 24
Peak memory 225400 kb
Host smart-1194ee34-31b2-45b7-8937-fa4db7cbd105
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158147133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2158147133
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2143438564
Short name T570
Test name
Test status
Simulation time 289813623 ps
CPU time 11.2 seconds
Started Jul 15 05:29:04 PM PDT 24
Finished Jul 15 05:29:16 PM PDT 24
Peak memory 225424 kb
Host smart-a203ca90-4c0e-4643-b3fd-86bfedbcda09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143438564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2143438564
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3551992229
Short name T469
Test name
Test status
Simulation time 192553102 ps
CPU time 3.13 seconds
Started Jul 15 05:29:01 PM PDT 24
Finished Jul 15 05:29:05 PM PDT 24
Peak memory 217184 kb
Host smart-5fb088a3-c709-474c-81b1-7adc66c533c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551992229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3551992229
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3108227827
Short name T288
Test name
Test status
Simulation time 1432970371 ps
CPU time 30.14 seconds
Started Jul 15 05:28:56 PM PDT 24
Finished Jul 15 05:29:27 PM PDT 24
Peak memory 250456 kb
Host smart-3bb61c73-20b8-4690-8c43-b848095d3cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108227827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3108227827
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1594401192
Short name T431
Test name
Test status
Simulation time 273250530 ps
CPU time 4.12 seconds
Started Jul 15 05:29:04 PM PDT 24
Finished Jul 15 05:29:09 PM PDT 24
Peak memory 221860 kb
Host smart-135c06ce-b04d-4c2d-a390-97ffc73f3eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594401192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1594401192
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2862614531
Short name T767
Test name
Test status
Simulation time 13152142442 ps
CPU time 53.24 seconds
Started Jul 15 05:29:03 PM PDT 24
Finished Jul 15 05:29:57 PM PDT 24
Peak memory 250384 kb
Host smart-831aead2-8302-405a-b3fa-2181058b8707
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862614531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2862614531
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.2727200095
Short name T145
Test name
Test status
Simulation time 111523756013 ps
CPU time 1002.42 seconds
Started Jul 15 05:29:03 PM PDT 24
Finished Jul 15 05:45:47 PM PDT 24
Peak memory 496388 kb
Host smart-d6ee9cda-25f8-42b5-a44a-dc2633d7e0e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2727200095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.2727200095
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.484703760
Short name T851
Test name
Test status
Simulation time 22672424 ps
CPU time 0.78 seconds
Started Jul 15 05:28:59 PM PDT 24
Finished Jul 15 05:29:00 PM PDT 24
Peak memory 208312 kb
Host smart-2aa0701b-081c-404e-92c9-8e3e1b7cee9a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484703760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.484703760
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2744462943
Short name T166
Test name
Test status
Simulation time 23342904 ps
CPU time 0.97 seconds
Started Jul 15 05:29:11 PM PDT 24
Finished Jul 15 05:29:12 PM PDT 24
Peak memory 208460 kb
Host smart-831df5c7-1c92-4ec9-a841-9de339fc2dd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744462943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2744462943
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.2002365601
Short name T329
Test name
Test status
Simulation time 2156729861 ps
CPU time 8.09 seconds
Started Jul 15 05:29:03 PM PDT 24
Finished Jul 15 05:29:12 PM PDT 24
Peak memory 225576 kb
Host smart-c0c79e0e-95f2-47bd-8636-f1b89127cc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002365601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2002365601
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1698997057
Short name T529
Test name
Test status
Simulation time 799782456 ps
CPU time 18.15 seconds
Started Jul 15 05:29:03 PM PDT 24
Finished Jul 15 05:29:22 PM PDT 24
Peak memory 217068 kb
Host smart-05e23204-75ae-4fb7-b940-04aa558c3ab7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698997057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1698997057
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2872165772
Short name T861
Test name
Test status
Simulation time 112575646 ps
CPU time 2.21 seconds
Started Jul 15 05:29:03 PM PDT 24
Finished Jul 15 05:29:06 PM PDT 24
Peak memory 217644 kb
Host smart-c9024d15-0721-4aa6-a726-a8ccfc520196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872165772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2872165772
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3218911220
Short name T772
Test name
Test status
Simulation time 723577651 ps
CPU time 12.39 seconds
Started Jul 15 05:29:13 PM PDT 24
Finished Jul 15 05:29:26 PM PDT 24
Peak memory 218328 kb
Host smart-ce054718-83d4-4994-9731-42a335d85c1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218911220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3218911220
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3729246725
Short name T718
Test name
Test status
Simulation time 2846371625 ps
CPU time 9.76 seconds
Started Jul 15 05:29:12 PM PDT 24
Finished Jul 15 05:29:23 PM PDT 24
Peak memory 225448 kb
Host smart-1697fee4-effd-4edb-99e5-130460205cea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729246725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3729246725
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3449821275
Short name T585
Test name
Test status
Simulation time 186832152 ps
CPU time 8.39 seconds
Started Jul 15 05:29:12 PM PDT 24
Finished Jul 15 05:29:21 PM PDT 24
Peak memory 217628 kb
Host smart-ef25ce9e-5efc-4efc-84fe-3fd491e08fb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449821275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3449821275
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2613121953
Short name T533
Test name
Test status
Simulation time 220863685 ps
CPU time 5.9 seconds
Started Jul 15 05:29:03 PM PDT 24
Finished Jul 15 05:29:10 PM PDT 24
Peak memory 217748 kb
Host smart-e566752c-5a10-4d79-86fc-b51b6c751108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613121953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2613121953
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3678236195
Short name T477
Test name
Test status
Simulation time 95332766 ps
CPU time 2.23 seconds
Started Jul 15 05:29:02 PM PDT 24
Finished Jul 15 05:29:04 PM PDT 24
Peak memory 217160 kb
Host smart-dd9b6e66-5616-4d62-a440-82bca157559b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678236195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3678236195
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3889389976
Short name T643
Test name
Test status
Simulation time 1037053523 ps
CPU time 27.56 seconds
Started Jul 15 05:29:04 PM PDT 24
Finished Jul 15 05:29:33 PM PDT 24
Peak memory 250416 kb
Host smart-327ae4d9-b6a9-41fb-93af-bdda3011f3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889389976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3889389976
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3378498119
Short name T339
Test name
Test status
Simulation time 271515842 ps
CPU time 5.85 seconds
Started Jul 15 05:29:05 PM PDT 24
Finished Jul 15 05:29:11 PM PDT 24
Peak memory 246368 kb
Host smart-982d2d87-f1c3-48c7-ac74-d7ea2fde792a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378498119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3378498119
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3362070745
Short name T308
Test name
Test status
Simulation time 9110902668 ps
CPU time 111.38 seconds
Started Jul 15 05:29:11 PM PDT 24
Finished Jul 15 05:31:03 PM PDT 24
Peak memory 276492 kb
Host smart-e0e39d39-ea79-4ab8-8e18-8b00e4d84f02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362070745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3362070745
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.304779904
Short name T235
Test name
Test status
Simulation time 26325908 ps
CPU time 1.01 seconds
Started Jul 15 05:29:06 PM PDT 24
Finished Jul 15 05:29:07 PM PDT 24
Peak memory 212220 kb
Host smart-ae1b312a-7980-4723-860f-a504f0b41b93
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304779904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.304779904
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2736602035
Short name T491
Test name
Test status
Simulation time 47392188 ps
CPU time 0.94 seconds
Started Jul 15 05:29:12 PM PDT 24
Finished Jul 15 05:29:14 PM PDT 24
Peak memory 208360 kb
Host smart-147c70db-cb88-48bb-b37a-1bbfd96af6ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736602035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2736602035
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2089553517
Short name T486
Test name
Test status
Simulation time 1017798559 ps
CPU time 13.59 seconds
Started Jul 15 05:29:13 PM PDT 24
Finished Jul 15 05:29:27 PM PDT 24
Peak memory 217640 kb
Host smart-8cf8dbf7-0b45-4f42-bde5-bd163a83efe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089553517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2089553517
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.494130699
Short name T29
Test name
Test status
Simulation time 198583242 ps
CPU time 4.97 seconds
Started Jul 15 05:29:09 PM PDT 24
Finished Jul 15 05:29:15 PM PDT 24
Peak memory 217072 kb
Host smart-0b85ec5d-72bf-497b-88e0-1937a09a6f80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494130699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.494130699
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.266041625
Short name T375
Test name
Test status
Simulation time 127981728 ps
CPU time 3.26 seconds
Started Jul 15 05:29:14 PM PDT 24
Finished Jul 15 05:29:18 PM PDT 24
Peak memory 217660 kb
Host smart-1cb8199b-0a67-4590-9c79-3e249de1b5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266041625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.266041625
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3758582906
Short name T756
Test name
Test status
Simulation time 610750439 ps
CPU time 13.25 seconds
Started Jul 15 05:29:13 PM PDT 24
Finished Jul 15 05:29:26 PM PDT 24
Peak memory 225376 kb
Host smart-3d1a8734-2e2a-49d0-9d87-b48fcd75b88b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758582906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3758582906
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2295593101
Short name T720
Test name
Test status
Simulation time 2365304987 ps
CPU time 12.34 seconds
Started Jul 15 05:29:12 PM PDT 24
Finished Jul 15 05:29:25 PM PDT 24
Peak memory 217912 kb
Host smart-535c40fa-dde0-4fdb-a3c2-cb7d4bffaf1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295593101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2295593101
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1003793919
Short name T517
Test name
Test status
Simulation time 232478968 ps
CPU time 10.35 seconds
Started Jul 15 05:29:12 PM PDT 24
Finished Jul 15 05:29:24 PM PDT 24
Peak memory 225568 kb
Host smart-a0296416-0627-4adc-ae73-d438ad9255e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003793919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1003793919
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1475687419
Short name T440
Test name
Test status
Simulation time 92162103 ps
CPU time 1.89 seconds
Started Jul 15 05:29:12 PM PDT 24
Finished Jul 15 05:29:14 PM PDT 24
Peak memory 217104 kb
Host smart-3d069845-0d4d-4af1-b720-e1c88d4bb5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475687419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1475687419
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.2053959959
Short name T274
Test name
Test status
Simulation time 163068978 ps
CPU time 23.11 seconds
Started Jul 15 05:29:10 PM PDT 24
Finished Jul 15 05:29:34 PM PDT 24
Peak memory 250384 kb
Host smart-0166156c-a898-4d2f-9a6a-acbc642e9d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053959959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2053959959
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3359890885
Short name T797
Test name
Test status
Simulation time 139440963 ps
CPU time 7.23 seconds
Started Jul 15 05:29:11 PM PDT 24
Finished Jul 15 05:29:18 PM PDT 24
Peak memory 250440 kb
Host smart-71d53efc-5ff9-49c3-8cd0-e4417de1ed57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359890885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3359890885
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2533157592
Short name T159
Test name
Test status
Simulation time 7486895564 ps
CPU time 50.59 seconds
Started Jul 15 05:29:11 PM PDT 24
Finished Jul 15 05:30:02 PM PDT 24
Peak memory 250456 kb
Host smart-2fac91e5-a5b9-498c-8ef1-793560fd5c1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533157592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2533157592
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2305660410
Short name T844
Test name
Test status
Simulation time 15733226 ps
CPU time 1.02 seconds
Started Jul 15 05:29:12 PM PDT 24
Finished Jul 15 05:29:14 PM PDT 24
Peak memory 217328 kb
Host smart-86a285d6-28d0-4bd9-b33d-25d811263711
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305660410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2305660410
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3747163732
Short name T504
Test name
Test status
Simulation time 52531056 ps
CPU time 0.96 seconds
Started Jul 15 05:29:19 PM PDT 24
Finished Jul 15 05:29:21 PM PDT 24
Peak memory 208468 kb
Host smart-a820fb12-1578-4817-beb2-a47f446fd6e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747163732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3747163732
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.528443326
Short name T728
Test name
Test status
Simulation time 1260269811 ps
CPU time 13.87 seconds
Started Jul 15 05:29:20 PM PDT 24
Finished Jul 15 05:29:34 PM PDT 24
Peak memory 217632 kb
Host smart-b2c28b06-3b5e-499b-a1dc-17761600a02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528443326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.528443326
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2714198666
Short name T719
Test name
Test status
Simulation time 3126186974 ps
CPU time 4.71 seconds
Started Jul 15 05:29:19 PM PDT 24
Finished Jul 15 05:29:25 PM PDT 24
Peak memory 217160 kb
Host smart-e4816f91-3a2a-42c6-b807-9508c04d2d86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714198666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2714198666
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1237796536
Short name T349
Test name
Test status
Simulation time 132106217 ps
CPU time 1.89 seconds
Started Jul 15 05:29:19 PM PDT 24
Finished Jul 15 05:29:22 PM PDT 24
Peak memory 217664 kb
Host smart-f90d6323-d27b-49e9-980f-b556d4c02bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237796536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1237796536
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1991849223
Short name T615
Test name
Test status
Simulation time 2062371154 ps
CPU time 16.56 seconds
Started Jul 15 05:29:25 PM PDT 24
Finished Jul 15 05:29:42 PM PDT 24
Peak memory 218300 kb
Host smart-bee0122c-55de-4c62-a391-316240666386
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991849223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1991849223
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3766704106
Short name T561
Test name
Test status
Simulation time 297087478 ps
CPU time 8.15 seconds
Started Jul 15 05:29:19 PM PDT 24
Finished Jul 15 05:29:29 PM PDT 24
Peak memory 225416 kb
Host smart-a8a2b26a-835e-46f5-858d-40701a3dce0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766704106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3766704106
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.4059072175
Short name T425
Test name
Test status
Simulation time 2223353562 ps
CPU time 12.11 seconds
Started Jul 15 05:29:19 PM PDT 24
Finished Jul 15 05:29:32 PM PDT 24
Peak memory 225484 kb
Host smart-18b4534c-8b81-4102-b9f3-f3b5ddbfef82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059072175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
4059072175
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3490747793
Short name T312
Test name
Test status
Simulation time 210104305 ps
CPU time 9.36 seconds
Started Jul 15 05:29:19 PM PDT 24
Finished Jul 15 05:29:29 PM PDT 24
Peak memory 217804 kb
Host smart-0e652be4-7392-4fdc-92ee-18e49ce46ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490747793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3490747793
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.3092269823
Short name T597
Test name
Test status
Simulation time 71323846 ps
CPU time 2.71 seconds
Started Jul 15 05:29:14 PM PDT 24
Finished Jul 15 05:29:18 PM PDT 24
Peak memory 217144 kb
Host smart-5f9f7ad3-e4b7-4257-b535-734ccd7dc9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092269823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3092269823
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1161456404
Short name T524
Test name
Test status
Simulation time 219391359 ps
CPU time 22.85 seconds
Started Jul 15 05:29:18 PM PDT 24
Finished Jul 15 05:29:42 PM PDT 24
Peak memory 250448 kb
Host smart-62c373c6-c36d-4c1c-82ca-b5fd006dc418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161456404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1161456404
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3846395626
Short name T488
Test name
Test status
Simulation time 79906544 ps
CPU time 7.68 seconds
Started Jul 15 05:29:18 PM PDT 24
Finished Jul 15 05:29:27 PM PDT 24
Peak memory 250396 kb
Host smart-b8c8fd6a-fc60-42fd-a153-4e9f5f02e191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846395626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3846395626
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.709027837
Short name T286
Test name
Test status
Simulation time 5252992682 ps
CPU time 66.4 seconds
Started Jul 15 05:29:18 PM PDT 24
Finished Jul 15 05:30:25 PM PDT 24
Peak memory 248496 kb
Host smart-b1d4ac25-ab4c-4441-bc6b-839242cdb4c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709027837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.709027837
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2549106566
Short name T528
Test name
Test status
Simulation time 40088181 ps
CPU time 0.9 seconds
Started Jul 15 05:29:12 PM PDT 24
Finished Jul 15 05:29:14 PM PDT 24
Peak memory 208504 kb
Host smart-ed22c572-030f-4f5e-8326-33883dd8694b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549106566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2549106566
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1922258128
Short name T71
Test name
Test status
Simulation time 13005483 ps
CPU time 0.99 seconds
Started Jul 15 05:29:25 PM PDT 24
Finished Jul 15 05:29:27 PM PDT 24
Peak memory 208436 kb
Host smart-28970fc2-10ba-4183-8a51-fe0ff76beadc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922258128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1922258128
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2511931530
Short name T255
Test name
Test status
Simulation time 1911052382 ps
CPU time 10.47 seconds
Started Jul 15 05:29:18 PM PDT 24
Finished Jul 15 05:29:29 PM PDT 24
Peak memory 225444 kb
Host smart-f7b3e2b6-501d-41fc-b647-6056865dfe8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511931530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2511931530
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3735477998
Short name T602
Test name
Test status
Simulation time 274800094 ps
CPU time 4.25 seconds
Started Jul 15 05:29:19 PM PDT 24
Finished Jul 15 05:29:24 PM PDT 24
Peak memory 217112 kb
Host smart-8034a980-b084-4037-9904-1c4ceec5d88e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735477998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3735477998
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.822865984
Short name T686
Test name
Test status
Simulation time 148326360 ps
CPU time 1.41 seconds
Started Jul 15 05:29:19 PM PDT 24
Finished Jul 15 05:29:21 PM PDT 24
Peak memory 217696 kb
Host smart-86394df5-3f40-473a-8d01-e08b40c25191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822865984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.822865984
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.645180428
Short name T532
Test name
Test status
Simulation time 550472969 ps
CPU time 15.88 seconds
Started Jul 15 05:29:27 PM PDT 24
Finished Jul 15 05:29:44 PM PDT 24
Peak memory 225380 kb
Host smart-489d3277-9679-4de4-b9a4-7094d37434f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645180428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.645180428
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3833034532
Short name T224
Test name
Test status
Simulation time 1462655411 ps
CPU time 9.32 seconds
Started Jul 15 05:29:18 PM PDT 24
Finished Jul 15 05:29:27 PM PDT 24
Peak memory 217572 kb
Host smart-3feceddc-9a72-43e7-9756-376a1bb4766b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833034532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3833034532
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1029551391
Short name T55
Test name
Test status
Simulation time 1047147673 ps
CPU time 14.9 seconds
Started Jul 15 05:29:19 PM PDT 24
Finished Jul 15 05:29:34 PM PDT 24
Peak memory 225504 kb
Host smart-6ecd2d85-e1db-473a-8cbe-c2d82b3887e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029551391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1029551391
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2699425012
Short name T563
Test name
Test status
Simulation time 505358910 ps
CPU time 3.1 seconds
Started Jul 15 05:29:20 PM PDT 24
Finished Jul 15 05:29:24 PM PDT 24
Peak memory 214396 kb
Host smart-2c3684c8-6758-42b0-a72e-445bf7aadecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699425012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2699425012
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2794643003
Short name T259
Test name
Test status
Simulation time 320240056 ps
CPU time 25.96 seconds
Started Jul 15 05:29:18 PM PDT 24
Finished Jul 15 05:29:45 PM PDT 24
Peak memory 250448 kb
Host smart-bbed6717-a72e-4d2c-8d4d-dbba92728f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794643003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2794643003
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.4234144428
Short name T150
Test name
Test status
Simulation time 723814007 ps
CPU time 6.96 seconds
Started Jul 15 05:29:19 PM PDT 24
Finished Jul 15 05:29:27 PM PDT 24
Peak memory 249972 kb
Host smart-152e4e69-f011-43f8-8439-c626e3e06459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234144428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.4234144428
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2732297371
Short name T511
Test name
Test status
Simulation time 9843861520 ps
CPU time 95.17 seconds
Started Jul 15 05:29:27 PM PDT 24
Finished Jul 15 05:31:03 PM PDT 24
Peak memory 272948 kb
Host smart-928206b3-5047-4d0a-bd62-ff2f824b25ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732297371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2732297371
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1635231263
Short name T356
Test name
Test status
Simulation time 34278224 ps
CPU time 1.13 seconds
Started Jul 15 05:29:18 PM PDT 24
Finished Jul 15 05:29:20 PM PDT 24
Peak memory 211312 kb
Host smart-0f35b50c-3936-4b38-8988-3daca00229c6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635231263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1635231263
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2653054736
Short name T94
Test name
Test status
Simulation time 245010521 ps
CPU time 0.9 seconds
Started Jul 15 05:29:28 PM PDT 24
Finished Jul 15 05:29:30 PM PDT 24
Peak memory 208464 kb
Host smart-f5495682-f7dd-46d5-80f7-767a7cd58b4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653054736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2653054736
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1937106537
Short name T295
Test name
Test status
Simulation time 206285209 ps
CPU time 9.61 seconds
Started Jul 15 05:29:27 PM PDT 24
Finished Jul 15 05:29:38 PM PDT 24
Peak memory 217736 kb
Host smart-23c191b0-2e98-4d2a-b540-dffcaf3dff09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937106537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1937106537
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2597665264
Short name T733
Test name
Test status
Simulation time 143439680 ps
CPU time 1.2 seconds
Started Jul 15 05:29:25 PM PDT 24
Finished Jul 15 05:29:27 PM PDT 24
Peak memory 216524 kb
Host smart-d2e710fc-2ee3-4261-b38e-2bb36c686d60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597665264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2597665264
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.4103885741
Short name T424
Test name
Test status
Simulation time 35931594 ps
CPU time 2.17 seconds
Started Jul 15 05:29:26 PM PDT 24
Finished Jul 15 05:29:29 PM PDT 24
Peak memory 217680 kb
Host smart-fc5b74e5-6422-451f-8d04-1e28a447f347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103885741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.4103885741
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2974542265
Short name T204
Test name
Test status
Simulation time 981181989 ps
CPU time 13.47 seconds
Started Jul 15 05:29:27 PM PDT 24
Finished Jul 15 05:29:42 PM PDT 24
Peak memory 218348 kb
Host smart-17ee60a1-595c-47e6-a01e-28be606f4465
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974542265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2974542265
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1958908979
Short name T2
Test name
Test status
Simulation time 2973661204 ps
CPU time 17.65 seconds
Started Jul 15 05:29:27 PM PDT 24
Finished Jul 15 05:29:46 PM PDT 24
Peak memory 225492 kb
Host smart-f2a1fc04-8030-4bf9-8b58-386e1667b876
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958908979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1958908979
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1393113823
Short name T165
Test name
Test status
Simulation time 744263542 ps
CPU time 9.37 seconds
Started Jul 15 05:29:25 PM PDT 24
Finished Jul 15 05:29:36 PM PDT 24
Peak memory 225396 kb
Host smart-20f86a92-7506-4fb3-a59c-6ec806461742
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393113823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1393113823
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1131547339
Short name T671
Test name
Test status
Simulation time 212200770 ps
CPU time 7.09 seconds
Started Jul 15 05:29:27 PM PDT 24
Finished Jul 15 05:29:35 PM PDT 24
Peak memory 224368 kb
Host smart-d304922b-86d6-49a9-a3c6-52dd99a9b4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131547339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1131547339
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2909234351
Short name T85
Test name
Test status
Simulation time 174077845 ps
CPU time 3.24 seconds
Started Jul 15 05:29:27 PM PDT 24
Finished Jul 15 05:29:32 PM PDT 24
Peak memory 217144 kb
Host smart-1a947b86-ad07-4315-bb1e-8b934fdb9095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909234351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2909234351
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.400567787
Short name T847
Test name
Test status
Simulation time 954322109 ps
CPU time 21.42 seconds
Started Jul 15 05:29:27 PM PDT 24
Finished Jul 15 05:29:50 PM PDT 24
Peak memory 250404 kb
Host smart-7f63baea-4ea8-4bb7-9dcf-448d5d5b9423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400567787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.400567787
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3580161809
Short name T232
Test name
Test status
Simulation time 428475139 ps
CPU time 8.33 seconds
Started Jul 15 05:29:28 PM PDT 24
Finished Jul 15 05:29:37 PM PDT 24
Peak memory 250384 kb
Host smart-c78e3cf8-15a7-4dd7-a071-962a05c753b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580161809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3580161809
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1907014319
Short name T152
Test name
Test status
Simulation time 39654616394 ps
CPU time 106.6 seconds
Started Jul 15 05:29:26 PM PDT 24
Finished Jul 15 05:31:13 PM PDT 24
Peak memory 258760 kb
Host smart-abeee116-9577-4934-8f59-fb4f492121f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907014319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1907014319
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2247701385
Short name T714
Test name
Test status
Simulation time 28376356 ps
CPU time 1.13 seconds
Started Jul 15 05:29:25 PM PDT 24
Finished Jul 15 05:29:27 PM PDT 24
Peak memory 211256 kb
Host smart-857bdcd2-3854-4470-9cb9-c7443e05f6bb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247701385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2247701385
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2818691013
Short name T167
Test name
Test status
Simulation time 39404412 ps
CPU time 1.15 seconds
Started Jul 15 05:29:35 PM PDT 24
Finished Jul 15 05:29:36 PM PDT 24
Peak memory 208464 kb
Host smart-35917033-640e-435b-a32d-6c51195cb194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818691013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2818691013
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1479424102
Short name T684
Test name
Test status
Simulation time 361018634 ps
CPU time 13.53 seconds
Started Jul 15 05:29:28 PM PDT 24
Finished Jul 15 05:29:43 PM PDT 24
Peak memory 217512 kb
Host smart-2b9f3fc2-042b-4529-99bc-b62d3f9afebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479424102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1479424102
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3236418602
Short name T9
Test name
Test status
Simulation time 1475976285 ps
CPU time 10.33 seconds
Started Jul 15 05:29:27 PM PDT 24
Finished Jul 15 05:29:39 PM PDT 24
Peak memory 217040 kb
Host smart-634132fb-b04f-49b0-947b-b30c31758278
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236418602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3236418602
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3727994358
Short name T394
Test name
Test status
Simulation time 266898347 ps
CPU time 3.05 seconds
Started Jul 15 05:29:27 PM PDT 24
Finished Jul 15 05:29:31 PM PDT 24
Peak memory 217704 kb
Host smart-a96ea4ee-03cb-4185-a497-fe65f40fdd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727994358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3727994358
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1867655730
Short name T765
Test name
Test status
Simulation time 3334908166 ps
CPU time 20.54 seconds
Started Jul 15 05:29:34 PM PDT 24
Finished Jul 15 05:29:55 PM PDT 24
Peak memory 225516 kb
Host smart-f5b6a252-90a8-4da8-9fcd-86ef2f06850b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867655730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1867655730
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.4201087513
Short name T310
Test name
Test status
Simulation time 318567054 ps
CPU time 12.71 seconds
Started Jul 15 05:29:25 PM PDT 24
Finished Jul 15 05:29:39 PM PDT 24
Peak memory 217736 kb
Host smart-3f012820-e887-4fcc-b24a-62022e6029fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201087513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
4201087513
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3198369470
Short name T49
Test name
Test status
Simulation time 442751635 ps
CPU time 9.07 seconds
Started Jul 15 05:29:25 PM PDT 24
Finished Jul 15 05:29:35 PM PDT 24
Peak memory 224460 kb
Host smart-e3e3e140-66c5-401f-937c-58ae73d50d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198369470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3198369470
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2429312454
Short name T484
Test name
Test status
Simulation time 80117354 ps
CPU time 2.27 seconds
Started Jul 15 05:29:28 PM PDT 24
Finished Jul 15 05:29:31 PM PDT 24
Peak memory 216996 kb
Host smart-fe4a4be2-8e0c-4a6e-afc5-872391df7c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429312454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2429312454
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.713840921
Short name T566
Test name
Test status
Simulation time 1677978120 ps
CPU time 30.65 seconds
Started Jul 15 05:29:25 PM PDT 24
Finished Jul 15 05:29:57 PM PDT 24
Peak memory 250404 kb
Host smart-fa38b2d2-bb88-4f3a-bd35-07ddf178567b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713840921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.713840921
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2950442618
Short name T445
Test name
Test status
Simulation time 71297292 ps
CPU time 2.93 seconds
Started Jul 15 05:29:27 PM PDT 24
Finished Jul 15 05:29:31 PM PDT 24
Peak memory 221860 kb
Host smart-9b744424-a075-4249-b1e2-070b793b4cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950442618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2950442618
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.3495246351
Short name T309
Test name
Test status
Simulation time 15578957706 ps
CPU time 445.23 seconds
Started Jul 15 05:29:34 PM PDT 24
Finished Jul 15 05:37:00 PM PDT 24
Peak memory 266840 kb
Host smart-1132fce3-c676-4268-85e1-4626f558746f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495246351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.3495246351
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2270629218
Short name T736
Test name
Test status
Simulation time 12164310 ps
CPU time 0.98 seconds
Started Jul 15 05:29:29 PM PDT 24
Finished Jul 15 05:29:31 PM PDT 24
Peak memory 208364 kb
Host smart-ba7a01d0-7ce6-4cd2-b3c9-96a3e3faa9ea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270629218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2270629218
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.157244632
Short name T268
Test name
Test status
Simulation time 62845686 ps
CPU time 0.89 seconds
Started Jul 15 05:29:36 PM PDT 24
Finished Jul 15 05:29:37 PM PDT 24
Peak memory 208420 kb
Host smart-1de270cc-06e5-4c80-94dc-dc369cf39d44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157244632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.157244632
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.202761460
Short name T701
Test name
Test status
Simulation time 389342277 ps
CPU time 16.35 seconds
Started Jul 15 05:29:34 PM PDT 24
Finished Jul 15 05:29:51 PM PDT 24
Peak memory 217688 kb
Host smart-140e728b-4700-4e8a-b055-07568b610718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202761460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.202761460
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2046143061
Short name T7
Test name
Test status
Simulation time 177427400 ps
CPU time 2.84 seconds
Started Jul 15 05:29:36 PM PDT 24
Finished Jul 15 05:29:40 PM PDT 24
Peak memory 217060 kb
Host smart-7fb00892-8fd9-4856-b341-27c4c2785714
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046143061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2046143061
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3236054592
Short name T269
Test name
Test status
Simulation time 281626009 ps
CPU time 4.25 seconds
Started Jul 15 05:29:33 PM PDT 24
Finished Jul 15 05:29:38 PM PDT 24
Peak memory 222292 kb
Host smart-64d0f35c-48c6-407a-874b-f587a2feb961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236054592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3236054592
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2364017360
Short name T822
Test name
Test status
Simulation time 5098984568 ps
CPU time 9.1 seconds
Started Jul 15 05:29:33 PM PDT 24
Finished Jul 15 05:29:43 PM PDT 24
Peak memory 225492 kb
Host smart-1218b8e2-d1e7-4eca-b001-04414bb3e91e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364017360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2364017360
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2874330811
Short name T211
Test name
Test status
Simulation time 563547626 ps
CPU time 11.64 seconds
Started Jul 15 05:29:35 PM PDT 24
Finished Jul 15 05:29:47 PM PDT 24
Peak memory 225432 kb
Host smart-ef6a1daf-54d5-49b3-b785-45a5767fdc0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874330811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2874330811
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2874520737
Short name T58
Test name
Test status
Simulation time 291810600 ps
CPU time 10.65 seconds
Started Jul 15 05:29:33 PM PDT 24
Finished Jul 15 05:29:45 PM PDT 24
Peak memory 217644 kb
Host smart-c01b0e4a-90dc-4852-ba70-cdb06d5692ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874520737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2874520737
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.4178201427
Short name T57
Test name
Test status
Simulation time 776941557 ps
CPU time 6.05 seconds
Started Jul 15 05:29:36 PM PDT 24
Finished Jul 15 05:29:43 PM PDT 24
Peak memory 224208 kb
Host smart-c4bd33b5-2a55-4b2a-bebe-7bbdb2cc835e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178201427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.4178201427
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1317126804
Short name T11
Test name
Test status
Simulation time 39531520 ps
CPU time 2.49 seconds
Started Jul 15 05:29:35 PM PDT 24
Finished Jul 15 05:29:38 PM PDT 24
Peak memory 217072 kb
Host smart-05c53b9a-28f5-44a6-a582-266476e8c646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317126804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1317126804
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2706162588
Short name T503
Test name
Test status
Simulation time 466022826 ps
CPU time 22.46 seconds
Started Jul 15 05:29:36 PM PDT 24
Finished Jul 15 05:29:59 PM PDT 24
Peak memory 250396 kb
Host smart-2d3bd821-af47-469b-9b48-059134e13a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706162588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2706162588
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.847750508
Short name T382
Test name
Test status
Simulation time 66103041 ps
CPU time 6.26 seconds
Started Jul 15 05:29:35 PM PDT 24
Finished Jul 15 05:29:41 PM PDT 24
Peak memory 246320 kb
Host smart-2ace20c2-1a08-49a9-934c-c134cfc65b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847750508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.847750508
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3393921924
Short name T695
Test name
Test status
Simulation time 6016333506 ps
CPU time 137.57 seconds
Started Jul 15 05:29:35 PM PDT 24
Finished Jul 15 05:31:53 PM PDT 24
Peak memory 226904 kb
Host smart-2043d821-623f-48e3-8629-b07930324855
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393921924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3393921924
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3076924102
Short name T13
Test name
Test status
Simulation time 37173636 ps
CPU time 0.95 seconds
Started Jul 15 05:29:37 PM PDT 24
Finished Jul 15 05:29:39 PM PDT 24
Peak memory 211360 kb
Host smart-bf845c97-b369-46e8-96b6-4e0d323e3964
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076924102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3076924102
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3299027820
Short name T441
Test name
Test status
Simulation time 56872839 ps
CPU time 1.03 seconds
Started Jul 15 05:29:42 PM PDT 24
Finished Jul 15 05:29:43 PM PDT 24
Peak memory 208560 kb
Host smart-444e18b0-563b-475b-8c66-50a4632d6a1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299027820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3299027820
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.1345900702
Short name T683
Test name
Test status
Simulation time 1295631335 ps
CPU time 15.14 seconds
Started Jul 15 05:29:42 PM PDT 24
Finished Jul 15 05:29:58 PM PDT 24
Peak memory 217652 kb
Host smart-fa21692d-b587-476e-8880-243fedf753c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345900702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.1345900702
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.383093746
Short name T498
Test name
Test status
Simulation time 315210548 ps
CPU time 8.03 seconds
Started Jul 15 05:29:43 PM PDT 24
Finished Jul 15 05:29:52 PM PDT 24
Peak memory 217048 kb
Host smart-c92fbf0c-98f0-402e-947f-cb574c68560a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383093746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.383093746
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2903073591
Short name T207
Test name
Test status
Simulation time 69863478 ps
CPU time 3.77 seconds
Started Jul 15 05:29:42 PM PDT 24
Finished Jul 15 05:29:46 PM PDT 24
Peak memory 217652 kb
Host smart-e1d3e33a-9ae3-42f0-9e8d-543b46752464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903073591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2903073591
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.856030748
Short name T257
Test name
Test status
Simulation time 196646810 ps
CPU time 8.7 seconds
Started Jul 15 05:29:42 PM PDT 24
Finished Jul 15 05:29:51 PM PDT 24
Peak memory 217660 kb
Host smart-4d067af5-9a1e-484c-949e-74b66be8c8c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856030748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.856030748
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.4132770995
Short name T609
Test name
Test status
Simulation time 3219092453 ps
CPU time 16.24 seconds
Started Jul 15 05:29:43 PM PDT 24
Finished Jul 15 05:30:00 PM PDT 24
Peak memory 225448 kb
Host smart-3f88279c-04db-4d6f-8083-09fb44b38ece
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132770995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.4132770995
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3067283548
Short name T506
Test name
Test status
Simulation time 1433549341 ps
CPU time 9.63 seconds
Started Jul 15 05:29:42 PM PDT 24
Finished Jul 15 05:29:53 PM PDT 24
Peak memory 225476 kb
Host smart-b8eeb9d6-74dc-4982-bbff-e05fc97b048f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067283548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3067283548
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.346937806
Short name T806
Test name
Test status
Simulation time 1463655722 ps
CPU time 9.21 seconds
Started Jul 15 05:29:40 PM PDT 24
Finished Jul 15 05:29:50 PM PDT 24
Peak memory 224652 kb
Host smart-87fdb69e-68b8-4dbc-bbcf-14e9141dcbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346937806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.346937806
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3197763089
Short name T78
Test name
Test status
Simulation time 24846032 ps
CPU time 1.75 seconds
Started Jul 15 05:29:37 PM PDT 24
Finished Jul 15 05:29:40 PM PDT 24
Peak memory 217132 kb
Host smart-be8f2647-3f66-4f73-8618-0aa25759b596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197763089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3197763089
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.606377938
Short name T438
Test name
Test status
Simulation time 192979210 ps
CPU time 26.35 seconds
Started Jul 15 05:29:41 PM PDT 24
Finished Jul 15 05:30:08 PM PDT 24
Peak memory 250452 kb
Host smart-5a03b2cf-454e-4b02-bca6-f127107ec3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606377938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.606377938
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3592504066
Short name T859
Test name
Test status
Simulation time 79665262 ps
CPU time 4.33 seconds
Started Jul 15 05:29:42 PM PDT 24
Finished Jul 15 05:29:47 PM PDT 24
Peak memory 222212 kb
Host smart-ab4e2c83-be60-4b95-9c2a-5c2f8341b3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592504066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3592504066
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3625041817
Short name T514
Test name
Test status
Simulation time 10257798558 ps
CPU time 194.23 seconds
Started Jul 15 05:29:42 PM PDT 24
Finished Jul 15 05:32:57 PM PDT 24
Peak memory 250508 kb
Host smart-67b129ca-5ff5-422b-ae2f-3f4867af68bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625041817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3625041817
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2283984407
Short name T266
Test name
Test status
Simulation time 49062333 ps
CPU time 0.89 seconds
Started Jul 15 05:29:36 PM PDT 24
Finished Jul 15 05:29:38 PM PDT 24
Peak memory 208284 kb
Host smart-b09110fb-7bd2-4178-8f78-17f8e080299d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283984407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2283984407
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.72597863
Short name T545
Test name
Test status
Simulation time 60449024 ps
CPU time 1.14 seconds
Started Jul 15 05:29:41 PM PDT 24
Finished Jul 15 05:29:43 PM PDT 24
Peak memory 208580 kb
Host smart-5317cec1-ee9e-4358-8794-aa3daecd5780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72597863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.72597863
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.450960350
Short name T15
Test name
Test status
Simulation time 509543722 ps
CPU time 19.66 seconds
Started Jul 15 05:29:44 PM PDT 24
Finished Jul 15 05:30:05 PM PDT 24
Peak memory 217748 kb
Host smart-99166b79-5946-4adf-9569-d17f13cfda10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450960350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.450960350
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.41088439
Short name T27
Test name
Test status
Simulation time 468824303 ps
CPU time 6.92 seconds
Started Jul 15 05:29:44 PM PDT 24
Finished Jul 15 05:29:51 PM PDT 24
Peak memory 217136 kb
Host smart-3e843a65-b9ca-4091-a115-8fd112378b5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41088439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.41088439
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1174901055
Short name T415
Test name
Test status
Simulation time 526296776 ps
CPU time 2.94 seconds
Started Jul 15 05:29:44 PM PDT 24
Finished Jul 15 05:29:48 PM PDT 24
Peak memory 217740 kb
Host smart-4cee49ed-bbdb-45c9-80c3-6f0054fa5498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174901055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1174901055
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.995876565
Short name T243
Test name
Test status
Simulation time 483376928 ps
CPU time 12.12 seconds
Started Jul 15 05:29:41 PM PDT 24
Finished Jul 15 05:29:53 PM PDT 24
Peak memory 225452 kb
Host smart-5791e61d-df45-47cf-b7f8-84725769f898
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995876565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.995876565
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1672141916
Short name T47
Test name
Test status
Simulation time 1162150087 ps
CPU time 10.14 seconds
Started Jul 15 05:29:44 PM PDT 24
Finished Jul 15 05:29:55 PM PDT 24
Peak memory 225456 kb
Host smart-44f1df83-e346-4337-be63-4a20945e0293
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672141916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1672141916
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3528090897
Short name T261
Test name
Test status
Simulation time 440462154 ps
CPU time 10.1 seconds
Started Jul 15 05:29:42 PM PDT 24
Finished Jul 15 05:29:53 PM PDT 24
Peak memory 217720 kb
Host smart-d4c1bb49-b98b-414a-b89e-7f9c0a61b5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528090897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3528090897
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2261185419
Short name T404
Test name
Test status
Simulation time 456742551 ps
CPU time 5.45 seconds
Started Jul 15 05:29:44 PM PDT 24
Finished Jul 15 05:29:50 PM PDT 24
Peak memory 217144 kb
Host smart-3dc4a951-2d47-4b6e-89e8-a32feef44f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261185419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2261185419
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1668362536
Short name T657
Test name
Test status
Simulation time 1708296352 ps
CPU time 32.65 seconds
Started Jul 15 05:29:44 PM PDT 24
Finished Jul 15 05:30:17 PM PDT 24
Peak memory 250444 kb
Host smart-d6c9c0e3-6e91-4139-a182-c2f93e73658d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668362536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1668362536
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.1564802115
Short name T521
Test name
Test status
Simulation time 86754314 ps
CPU time 7.78 seconds
Started Jul 15 05:29:43 PM PDT 24
Finished Jul 15 05:29:51 PM PDT 24
Peak memory 250444 kb
Host smart-2bc3335b-0222-41e5-b141-fcbf1578147b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564802115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1564802115
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2202377707
Short name T752
Test name
Test status
Simulation time 14157044656 ps
CPU time 139.73 seconds
Started Jul 15 05:29:43 PM PDT 24
Finished Jul 15 05:32:04 PM PDT 24
Peak memory 276624 kb
Host smart-7b1f05b0-d754-4006-af3c-6c42715aed71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202377707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2202377707
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2057606233
Short name T389
Test name
Test status
Simulation time 14859097 ps
CPU time 0.89 seconds
Started Jul 15 05:29:43 PM PDT 24
Finished Jul 15 05:29:45 PM PDT 24
Peak memory 208256 kb
Host smart-7570ed2f-d511-4707-a63d-b7917e60ee54
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057606233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2057606233
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1667809657
Short name T554
Test name
Test status
Simulation time 20538556 ps
CPU time 1.21 seconds
Started Jul 15 05:27:04 PM PDT 24
Finished Jul 15 05:27:06 PM PDT 24
Peak memory 208380 kb
Host smart-e98b8622-dd22-4e0e-b921-856b7c1d507c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667809657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1667809657
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3520474319
Short name T226
Test name
Test status
Simulation time 3602125557 ps
CPU time 21.48 seconds
Started Jul 15 05:26:54 PM PDT 24
Finished Jul 15 05:27:16 PM PDT 24
Peak memory 218500 kb
Host smart-1de7e072-38ff-4278-9b73-c066b1a97686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520474319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3520474319
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2695572109
Short name T703
Test name
Test status
Simulation time 260226003 ps
CPU time 3.25 seconds
Started Jul 15 05:26:55 PM PDT 24
Finished Jul 15 05:26:59 PM PDT 24
Peak memory 217116 kb
Host smart-5d604a07-1fff-4a3c-bb82-77b0069fb48e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695572109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2695572109
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2780068044
Short name T460
Test name
Test status
Simulation time 14693541341 ps
CPU time 71.85 seconds
Started Jul 15 05:26:54 PM PDT 24
Finished Jul 15 05:28:06 PM PDT 24
Peak memory 218388 kb
Host smart-a667f719-045c-454f-974a-0b538a9b41de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780068044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2780068044
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3803962527
Short name T176
Test name
Test status
Simulation time 13415293509 ps
CPU time 78.62 seconds
Started Jul 15 05:26:56 PM PDT 24
Finished Jul 15 05:28:15 PM PDT 24
Peak memory 217232 kb
Host smart-ba847b10-f463-4c49-bfad-58c6e420f55a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803962527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
803962527
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3681110685
Short name T644
Test name
Test status
Simulation time 1191345333 ps
CPU time 14.43 seconds
Started Jul 15 05:26:58 PM PDT 24
Finished Jul 15 05:27:13 PM PDT 24
Peak memory 223852 kb
Host smart-93666a8c-73a9-4434-a64f-a04cc74b197f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681110685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3681110685
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2124936716
Short name T598
Test name
Test status
Simulation time 3894983972 ps
CPU time 15.1 seconds
Started Jul 15 05:26:55 PM PDT 24
Finished Jul 15 05:27:11 PM PDT 24
Peak memory 217128 kb
Host smart-a53c8c05-c2ea-4904-8838-c1b73c12a1e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124936716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2124936716
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.4242235525
Short name T77
Test name
Test status
Simulation time 3172389579 ps
CPU time 4.95 seconds
Started Jul 15 05:26:54 PM PDT 24
Finished Jul 15 05:27:00 PM PDT 24
Peak memory 217068 kb
Host smart-f3773e6c-1396-48ef-84d4-bad6994148e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242235525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
4242235525
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2905449736
Short name T605
Test name
Test status
Simulation time 6148161189 ps
CPU time 64.89 seconds
Started Jul 15 05:26:54 PM PDT 24
Finished Jul 15 05:28:00 PM PDT 24
Peak memory 274988 kb
Host smart-1cbb68c1-9bbc-48bb-8e58-810c29bced1a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905449736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2905449736
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2341994688
Short name T304
Test name
Test status
Simulation time 424469849 ps
CPU time 12 seconds
Started Jul 15 05:26:55 PM PDT 24
Finished Jul 15 05:27:08 PM PDT 24
Peak memory 249760 kb
Host smart-1a81090c-5a46-43b1-b270-b1c14ae1a6fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341994688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2341994688
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.265979895
Short name T648
Test name
Test status
Simulation time 96539538 ps
CPU time 1.79 seconds
Started Jul 15 05:26:53 PM PDT 24
Finished Jul 15 05:26:55 PM PDT 24
Peak memory 217628 kb
Host smart-29b33756-0224-4578-8666-defb758a3bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265979895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.265979895
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2726033105
Short name T177
Test name
Test status
Simulation time 211081707 ps
CPU time 8.44 seconds
Started Jul 15 05:26:55 PM PDT 24
Finished Jul 15 05:27:04 PM PDT 24
Peak memory 213824 kb
Host smart-2d074eba-fbe9-4097-83e9-2d7da8951af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726033105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2726033105
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2989819352
Short name T92
Test name
Test status
Simulation time 1010888796 ps
CPU time 27.92 seconds
Started Jul 15 05:27:02 PM PDT 24
Finished Jul 15 05:27:31 PM PDT 24
Peak memory 269348 kb
Host smart-e3ff1aef-3726-4a0b-9ef3-23896d3707a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989819352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2989819352
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.621231660
Short name T723
Test name
Test status
Simulation time 453935385 ps
CPU time 20.21 seconds
Started Jul 15 05:26:55 PM PDT 24
Finished Jul 15 05:27:15 PM PDT 24
Peak memory 225460 kb
Host smart-b5175e94-6255-475c-a2e5-1c13ef98acfc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621231660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.621231660
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.223271132
Short name T423
Test name
Test status
Simulation time 512887906 ps
CPU time 12.38 seconds
Started Jul 15 05:26:53 PM PDT 24
Finished Jul 15 05:27:06 PM PDT 24
Peak memory 225444 kb
Host smart-f935c6a8-a55d-4f2b-b331-d26fb8fad2d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223271132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig
est.223271132
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2124828267
Short name T61
Test name
Test status
Simulation time 1007229692 ps
CPU time 9.57 seconds
Started Jul 15 05:26:56 PM PDT 24
Finished Jul 15 05:27:06 PM PDT 24
Peak memory 225100 kb
Host smart-851ba8e2-317f-4b53-8996-2bd7616e00dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124828267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
124828267
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3666908781
Short name T297
Test name
Test status
Simulation time 1526475361 ps
CPU time 15.52 seconds
Started Jul 15 05:26:54 PM PDT 24
Finished Jul 15 05:27:10 PM PDT 24
Peak memory 225444 kb
Host smart-1d2555b0-b96a-4884-a7eb-9ac8a189475d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666908781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3666908781
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1847641447
Short name T335
Test name
Test status
Simulation time 27704657 ps
CPU time 2.1 seconds
Started Jul 15 05:26:56 PM PDT 24
Finished Jul 15 05:26:58 PM PDT 24
Peak memory 213868 kb
Host smart-b98b8c20-4a83-401c-b60b-bd7f1371af65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847641447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1847641447
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1348680965
Short name T171
Test name
Test status
Simulation time 1032402660 ps
CPU time 24 seconds
Started Jul 15 05:26:57 PM PDT 24
Finished Jul 15 05:27:22 PM PDT 24
Peak memory 250264 kb
Host smart-a5369a43-dc40-479b-8c06-86d316f2bc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348680965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1348680965
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.692159019
Short name T618
Test name
Test status
Simulation time 90000834 ps
CPU time 11.23 seconds
Started Jul 15 05:26:58 PM PDT 24
Finished Jul 15 05:27:10 PM PDT 24
Peak memory 250412 kb
Host smart-a31ee1ea-610c-4929-940c-9494ac120d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692159019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.692159019
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3989581643
Short name T466
Test name
Test status
Simulation time 4899042390 ps
CPU time 66.16 seconds
Started Jul 15 05:26:58 PM PDT 24
Finished Jul 15 05:28:05 PM PDT 24
Peak memory 275724 kb
Host smart-a7ae6109-8e42-494a-9bf0-6c56159c0c3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989581643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3989581643
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2254072478
Short name T454
Test name
Test status
Simulation time 71856933 ps
CPU time 0.89 seconds
Started Jul 15 05:26:53 PM PDT 24
Finished Jul 15 05:26:54 PM PDT 24
Peak memory 211240 kb
Host smart-d7a1eaf5-9cad-4a99-ab71-d773a5fcba9b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254072478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2254072478
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2402160951
Short name T357
Test name
Test status
Simulation time 82638211 ps
CPU time 0.99 seconds
Started Jul 15 05:29:50 PM PDT 24
Finished Jul 15 05:29:51 PM PDT 24
Peak memory 208560 kb
Host smart-20534498-4a09-4b90-b7c8-833e9c836ba4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402160951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2402160951
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2006540886
Short name T482
Test name
Test status
Simulation time 399365026 ps
CPU time 13.61 seconds
Started Jul 15 05:29:49 PM PDT 24
Finished Jul 15 05:30:03 PM PDT 24
Peak memory 225492 kb
Host smart-33ed7526-97a5-4563-8c3b-d9a4e0d86bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006540886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2006540886
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1590621201
Short name T543
Test name
Test status
Simulation time 871589429 ps
CPU time 2.92 seconds
Started Jul 15 05:29:48 PM PDT 24
Finished Jul 15 05:29:51 PM PDT 24
Peak memory 217056 kb
Host smart-e895b536-4703-433d-9293-b58b9403aa8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590621201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1590621201
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3142525702
Short name T565
Test name
Test status
Simulation time 19112919 ps
CPU time 1.5 seconds
Started Jul 15 05:29:50 PM PDT 24
Finished Jul 15 05:29:52 PM PDT 24
Peak memory 217740 kb
Host smart-0d6fae15-c0f2-4872-b6bb-7b3a1c45c6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142525702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3142525702
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.2344278156
Short name T690
Test name
Test status
Simulation time 3861121816 ps
CPU time 12.93 seconds
Started Jul 15 05:29:49 PM PDT 24
Finished Jul 15 05:30:03 PM PDT 24
Peak memory 225584 kb
Host smart-763386f7-308f-4078-8c85-a693c18bbdf6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344278156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.2344278156
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.109913200
Short name T233
Test name
Test status
Simulation time 1285536211 ps
CPU time 12.34 seconds
Started Jul 15 05:29:48 PM PDT 24
Finished Jul 15 05:30:01 PM PDT 24
Peak memory 225440 kb
Host smart-f39560aa-5a7f-476b-80de-67ad49f85d29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109913200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.109913200
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3017350742
Short name T660
Test name
Test status
Simulation time 1238452217 ps
CPU time 11.36 seconds
Started Jul 15 05:29:48 PM PDT 24
Finished Jul 15 05:30:00 PM PDT 24
Peak memory 217780 kb
Host smart-ee3366e6-a50d-4de1-9936-2127b2df57be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017350742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3017350742
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1118636177
Short name T740
Test name
Test status
Simulation time 503559302 ps
CPU time 7.11 seconds
Started Jul 15 05:29:50 PM PDT 24
Finished Jul 15 05:29:58 PM PDT 24
Peak memory 225508 kb
Host smart-a88ceac7-fb45-4e2f-b39e-0a43df858d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118636177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1118636177
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2906065048
Short name T64
Test name
Test status
Simulation time 415658364 ps
CPU time 3.31 seconds
Started Jul 15 05:29:48 PM PDT 24
Finished Jul 15 05:29:53 PM PDT 24
Peak memory 217072 kb
Host smart-ff065157-95a8-4746-a68d-293b30a17188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906065048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2906065048
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1057387401
Short name T246
Test name
Test status
Simulation time 354894945 ps
CPU time 31.88 seconds
Started Jul 15 05:29:48 PM PDT 24
Finished Jul 15 05:30:21 PM PDT 24
Peak memory 250492 kb
Host smart-85458473-2287-44ad-9259-edaaec0fb276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057387401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1057387401
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1918971336
Short name T590
Test name
Test status
Simulation time 339101627 ps
CPU time 8.39 seconds
Started Jul 15 05:29:48 PM PDT 24
Finished Jul 15 05:29:57 PM PDT 24
Peak memory 250408 kb
Host smart-39239bfe-148d-42cd-a144-cc15d464210c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918971336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1918971336
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2921255373
Short name T823
Test name
Test status
Simulation time 1330580358 ps
CPU time 36.16 seconds
Started Jul 15 05:29:50 PM PDT 24
Finished Jul 15 05:30:27 PM PDT 24
Peak memory 245912 kb
Host smart-3eeddbbc-e8f2-4b03-a649-c0cdd44189f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921255373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2921255373
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3684418219
Short name T333
Test name
Test status
Simulation time 21320819 ps
CPU time 1.03 seconds
Started Jul 15 05:29:48 PM PDT 24
Finished Jul 15 05:29:50 PM PDT 24
Peak memory 211236 kb
Host smart-18c604ef-5700-48e7-9010-0d89e2e4840c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684418219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3684418219
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3345178786
Short name T332
Test name
Test status
Simulation time 90438146 ps
CPU time 1.08 seconds
Started Jul 15 05:30:00 PM PDT 24
Finished Jul 15 05:30:01 PM PDT 24
Peak memory 208464 kb
Host smart-509ef970-0ec8-4251-aea0-368a93208546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345178786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3345178786
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.4130824552
Short name T237
Test name
Test status
Simulation time 1538646674 ps
CPU time 11.09 seconds
Started Jul 15 05:29:51 PM PDT 24
Finished Jul 15 05:30:03 PM PDT 24
Peak memory 217684 kb
Host smart-7ad3308c-d38e-43d3-9dd0-201c71f5893d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130824552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.4130824552
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1909491165
Short name T26
Test name
Test status
Simulation time 797809811 ps
CPU time 6.17 seconds
Started Jul 15 05:29:51 PM PDT 24
Finished Jul 15 05:29:58 PM PDT 24
Peak memory 216644 kb
Host smart-9f0c0d48-e819-4f6f-b7cd-0cbf93614069
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909491165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1909491165
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3021252417
Short name T250
Test name
Test status
Simulation time 153682607 ps
CPU time 3.74 seconds
Started Jul 15 05:29:51 PM PDT 24
Finished Jul 15 05:29:55 PM PDT 24
Peak memory 217676 kb
Host smart-5468f8ef-e387-488d-9a2e-c88b2acd8666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021252417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3021252417
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.4132788166
Short name T280
Test name
Test status
Simulation time 394723066 ps
CPU time 11.57 seconds
Started Jul 15 05:29:51 PM PDT 24
Finished Jul 15 05:30:03 PM PDT 24
Peak memory 218400 kb
Host smart-d5bb1890-209f-4e06-893c-11568097852e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132788166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.4132788166
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2713365438
Short name T327
Test name
Test status
Simulation time 334889670 ps
CPU time 13.62 seconds
Started Jul 15 05:29:49 PM PDT 24
Finished Jul 15 05:30:03 PM PDT 24
Peak memory 225420 kb
Host smart-001e26d4-c071-4c74-8439-4edfe8e1b99f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713365438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2713365438
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.293353674
Short name T821
Test name
Test status
Simulation time 1986213282 ps
CPU time 7.84 seconds
Started Jul 15 05:29:50 PM PDT 24
Finished Jul 15 05:29:59 PM PDT 24
Peak memory 225468 kb
Host smart-e0eeb497-3a19-4345-a708-e23de20d6d58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293353674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.293353674
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.196032764
Short name T254
Test name
Test status
Simulation time 2100324706 ps
CPU time 14.06 seconds
Started Jul 15 05:29:49 PM PDT 24
Finished Jul 15 05:30:04 PM PDT 24
Peak memory 225480 kb
Host smart-f73bf5a3-1ca8-44ac-bd3e-18ff241dd82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196032764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.196032764
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.531697934
Short name T75
Test name
Test status
Simulation time 2340603761 ps
CPU time 5.39 seconds
Started Jul 15 05:29:49 PM PDT 24
Finished Jul 15 05:29:55 PM PDT 24
Peak memory 217116 kb
Host smart-b7913462-3b09-4edb-9ea4-e0008f7c4baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531697934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.531697934
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1593331443
Short name T443
Test name
Test status
Simulation time 281493361 ps
CPU time 27.29 seconds
Started Jul 15 05:29:49 PM PDT 24
Finished Jul 15 05:30:17 PM PDT 24
Peak memory 250496 kb
Host smart-6dd8655d-8167-41c2-b00c-c2543de0074c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593331443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1593331443
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3107025484
Short name T302
Test name
Test status
Simulation time 47682615 ps
CPU time 6.96 seconds
Started Jul 15 05:29:51 PM PDT 24
Finished Jul 15 05:29:58 PM PDT 24
Peak memory 250428 kb
Host smart-3fdd0423-0568-4597-a469-e18a8f9c55fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107025484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3107025484
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.996402031
Short name T478
Test name
Test status
Simulation time 2059342594 ps
CPU time 50.4 seconds
Started Jul 15 05:29:52 PM PDT 24
Finished Jul 15 05:30:43 PM PDT 24
Peak memory 270904 kb
Host smart-d29f6ce7-9169-4653-bf84-447538e531fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996402031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.996402031
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.2809648757
Short name T840
Test name
Test status
Simulation time 106166210609 ps
CPU time 889.46 seconds
Started Jul 15 05:29:59 PM PDT 24
Finished Jul 15 05:44:49 PM PDT 24
Peak memory 283440 kb
Host smart-c4185ff1-697c-49ed-bc0b-374832ea1b68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2809648757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.2809648757
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1060038851
Short name T311
Test name
Test status
Simulation time 17332411 ps
CPU time 0.91 seconds
Started Jul 15 05:29:48 PM PDT 24
Finished Jul 15 05:29:50 PM PDT 24
Peak memory 208308 kb
Host smart-9401c64d-825f-4391-9bde-3478ab9a0a5e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060038851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1060038851
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.2226084994
Short name T249
Test name
Test status
Simulation time 21784230 ps
CPU time 1.25 seconds
Started Jul 15 05:29:57 PM PDT 24
Finished Jul 15 05:29:59 PM PDT 24
Peak memory 208444 kb
Host smart-4d6fe4e9-1782-421f-b8b2-c74fd7372acf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226084994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2226084994
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2965524068
Short name T475
Test name
Test status
Simulation time 353000635 ps
CPU time 12.63 seconds
Started Jul 15 05:29:56 PM PDT 24
Finished Jul 15 05:30:09 PM PDT 24
Peak memory 217676 kb
Host smart-dc8cfa7e-1391-4b48-b570-45e44bf93a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965524068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2965524068
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.604858858
Short name T294
Test name
Test status
Simulation time 448251984 ps
CPU time 1.44 seconds
Started Jul 15 05:29:57 PM PDT 24
Finished Jul 15 05:30:00 PM PDT 24
Peak memory 216600 kb
Host smart-ab9b2840-c8f3-4127-a093-f309d81ea240
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604858858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.604858858
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1341381478
Short name T855
Test name
Test status
Simulation time 33619380 ps
CPU time 1.62 seconds
Started Jul 15 05:29:58 PM PDT 24
Finished Jul 15 05:30:01 PM PDT 24
Peak memory 221132 kb
Host smart-eedee6c7-7d22-4076-96a2-305bd2167e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341381478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1341381478
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1245544832
Short name T569
Test name
Test status
Simulation time 994849160 ps
CPU time 10.9 seconds
Started Jul 15 05:29:57 PM PDT 24
Finished Jul 15 05:30:08 PM PDT 24
Peak memory 225288 kb
Host smart-537256c4-e2ac-4978-b82a-e9608e4c05bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245544832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1245544832
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2559010273
Short name T600
Test name
Test status
Simulation time 261295122 ps
CPU time 6.9 seconds
Started Jul 15 05:29:57 PM PDT 24
Finished Jul 15 05:30:05 PM PDT 24
Peak memory 217680 kb
Host smart-7a2ac859-1eab-4d76-b7fa-724f3d46594b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559010273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2559010273
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.235206224
Short name T328
Test name
Test status
Simulation time 1337557580 ps
CPU time 10.17 seconds
Started Jul 15 05:29:55 PM PDT 24
Finished Jul 15 05:30:06 PM PDT 24
Peak memory 224508 kb
Host smart-3b38bf12-c6b3-425f-b0a0-19887fa41659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235206224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.235206224
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2257981156
Short name T74
Test name
Test status
Simulation time 1072368368 ps
CPU time 4.83 seconds
Started Jul 15 05:29:58 PM PDT 24
Finished Jul 15 05:30:04 PM PDT 24
Peak memory 217044 kb
Host smart-4885c7d8-54ad-4a89-8f9f-450dc1ca367e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257981156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2257981156
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2367209234
Short name T679
Test name
Test status
Simulation time 938095849 ps
CPU time 22.48 seconds
Started Jul 15 05:29:55 PM PDT 24
Finished Jul 15 05:30:18 PM PDT 24
Peak memory 250456 kb
Host smart-e8e0532f-f133-4637-a16b-c090464ee217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367209234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2367209234
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.4069319089
Short name T90
Test name
Test status
Simulation time 70792499 ps
CPU time 8.39 seconds
Started Jul 15 05:29:57 PM PDT 24
Finished Jul 15 05:30:07 PM PDT 24
Peak memory 250432 kb
Host smart-f3b0c614-a216-4c1f-80bb-3418ba053ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069319089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.4069319089
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2030660907
Short name T203
Test name
Test status
Simulation time 75922438963 ps
CPU time 149.12 seconds
Started Jul 15 05:30:00 PM PDT 24
Finished Jul 15 05:32:29 PM PDT 24
Peak memory 225516 kb
Host smart-67b4a5c9-afea-49b3-b8b4-a1dc16ebd326
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030660907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2030660907
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2111151783
Short name T101
Test name
Test status
Simulation time 13265927704 ps
CPU time 235.05 seconds
Started Jul 15 05:29:58 PM PDT 24
Finished Jul 15 05:33:54 PM PDT 24
Peak memory 271168 kb
Host smart-0b55d534-3d56-4500-ad27-5254cd39baef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2111151783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.2111151783
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.852497534
Short name T465
Test name
Test status
Simulation time 17676582 ps
CPU time 1.06 seconds
Started Jul 15 05:30:01 PM PDT 24
Finished Jul 15 05:30:02 PM PDT 24
Peak memory 217128 kb
Host smart-02c244f1-d6f3-4ce9-9fee-8b7985c4576d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852497534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.852497534
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3620529150
Short name T45
Test name
Test status
Simulation time 1294606689 ps
CPU time 20.81 seconds
Started Jul 15 05:29:58 PM PDT 24
Finished Jul 15 05:30:20 PM PDT 24
Peak memory 217644 kb
Host smart-fbb6ae56-c84c-4495-930e-8ab6bc383f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620529150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3620529150
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3224249974
Short name T646
Test name
Test status
Simulation time 357618931 ps
CPU time 4.22 seconds
Started Jul 15 05:29:58 PM PDT 24
Finished Jul 15 05:30:03 PM PDT 24
Peak memory 217048 kb
Host smart-71c9ba7a-d8e3-492c-88b5-c9f8bd3f7505
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224249974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3224249974
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3257439424
Short name T623
Test name
Test status
Simulation time 241368109 ps
CPU time 2.72 seconds
Started Jul 15 05:30:01 PM PDT 24
Finished Jul 15 05:30:04 PM PDT 24
Peak memory 217788 kb
Host smart-755d7786-7427-42ef-9e25-bb898645de97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257439424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3257439424
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2188642636
Short name T158
Test name
Test status
Simulation time 645118064 ps
CPU time 15.72 seconds
Started Jul 15 05:29:57 PM PDT 24
Finished Jul 15 05:30:13 PM PDT 24
Peak memory 225428 kb
Host smart-a8f039fd-7062-4df5-9233-57f2b6c1b0ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188642636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2188642636
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2986484648
Short name T398
Test name
Test status
Simulation time 237078429 ps
CPU time 8.99 seconds
Started Jul 15 05:30:04 PM PDT 24
Finished Jul 15 05:30:14 PM PDT 24
Peak memory 225444 kb
Host smart-650fdbc5-6186-4ee9-a0b5-fb78472181c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986484648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2986484648
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2116658279
Short name T459
Test name
Test status
Simulation time 5694292547 ps
CPU time 9.27 seconds
Started Jul 15 05:30:03 PM PDT 24
Finished Jul 15 05:30:13 PM PDT 24
Peak memory 225524 kb
Host smart-971aa34d-7db6-437e-aa8d-3ca1c580b345
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116658279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2116658279
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3367906482
Short name T347
Test name
Test status
Simulation time 3124999823 ps
CPU time 8.58 seconds
Started Jul 15 05:29:57 PM PDT 24
Finished Jul 15 05:30:06 PM PDT 24
Peak memory 225556 kb
Host smart-9cf16ec3-d3b7-4229-a622-8550383b5bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367906482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3367906482
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1443277866
Short name T414
Test name
Test status
Simulation time 191000036 ps
CPU time 1.83 seconds
Started Jul 15 05:29:59 PM PDT 24
Finished Jul 15 05:30:01 PM PDT 24
Peak memory 213516 kb
Host smart-939221aa-42c9-4fed-b9ec-91eb8ca5ea5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443277866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1443277866
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.374613361
Short name T626
Test name
Test status
Simulation time 466259973 ps
CPU time 32.39 seconds
Started Jul 15 05:29:57 PM PDT 24
Finished Jul 15 05:30:30 PM PDT 24
Peak memory 250536 kb
Host smart-3f8d69e3-b13e-45d2-a2cc-5226aecbfd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374613361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.374613361
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.843052926
Short name T178
Test name
Test status
Simulation time 8346353080 ps
CPU time 153.89 seconds
Started Jul 15 05:30:05 PM PDT 24
Finished Jul 15 05:32:40 PM PDT 24
Peak memory 281044 kb
Host smart-da72eedd-c1d0-41fb-b107-05952d976d6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843052926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.843052926
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3198789841
Short name T70
Test name
Test status
Simulation time 17666372 ps
CPU time 1.27 seconds
Started Jul 15 05:29:57 PM PDT 24
Finished Jul 15 05:29:59 PM PDT 24
Peak memory 217064 kb
Host smart-d02429fc-3a11-4080-acae-e659d199eab9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198789841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.3198789841
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2193131774
Short name T610
Test name
Test status
Simulation time 48970839 ps
CPU time 0.85 seconds
Started Jul 15 05:30:05 PM PDT 24
Finished Jul 15 05:30:07 PM PDT 24
Peak memory 208260 kb
Host smart-108bc6e4-22fa-45b3-a2a9-1e5ee828c295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193131774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2193131774
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2285490920
Short name T113
Test name
Test status
Simulation time 478898715 ps
CPU time 14.84 seconds
Started Jul 15 05:30:02 PM PDT 24
Finished Jul 15 05:30:17 PM PDT 24
Peak memory 225428 kb
Host smart-0b5c7c19-a7bf-4365-86d6-51d07f50c575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285490920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2285490920
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3129271328
Short name T512
Test name
Test status
Simulation time 242241323 ps
CPU time 2.05 seconds
Started Jul 15 05:30:04 PM PDT 24
Finished Jul 15 05:30:07 PM PDT 24
Peak memory 217148 kb
Host smart-bfd2f877-6f58-496f-83d2-2a8ccba6dfc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129271328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3129271328
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3320792204
Short name T318
Test name
Test status
Simulation time 62498183 ps
CPU time 1.81 seconds
Started Jul 15 05:30:04 PM PDT 24
Finished Jul 15 05:30:06 PM PDT 24
Peak memory 217660 kb
Host smart-7a8e1a6e-2da7-4275-b8fe-59a2ba806abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320792204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3320792204
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3991694433
Short name T419
Test name
Test status
Simulation time 440890516 ps
CPU time 15.08 seconds
Started Jul 15 05:30:05 PM PDT 24
Finished Jul 15 05:30:22 PM PDT 24
Peak memory 218292 kb
Host smart-25b19df7-067f-4839-8956-fe4c3bb60919
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991694433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3991694433
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2494867695
Short name T442
Test name
Test status
Simulation time 1534370593 ps
CPU time 8.87 seconds
Started Jul 15 05:30:05 PM PDT 24
Finished Jul 15 05:30:16 PM PDT 24
Peak memory 225424 kb
Host smart-ac6c60b4-68f8-4b10-8b03-ae87b7729000
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494867695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2494867695
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3906725622
Short name T501
Test name
Test status
Simulation time 5129978649 ps
CPU time 12.24 seconds
Started Jul 15 05:30:04 PM PDT 24
Finished Jul 15 05:30:18 PM PDT 24
Peak memory 217672 kb
Host smart-eeea0e76-e70c-43cc-a033-421a99881382
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906725622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3906725622
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.888122428
Short name T595
Test name
Test status
Simulation time 810517162 ps
CPU time 7.11 seconds
Started Jul 15 05:30:06 PM PDT 24
Finished Jul 15 05:30:14 PM PDT 24
Peak memory 224640 kb
Host smart-2a2f553f-6891-4b13-8076-d7597cf8c3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888122428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.888122428
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.781583394
Short name T264
Test name
Test status
Simulation time 56520868 ps
CPU time 2.08 seconds
Started Jul 15 05:30:06 PM PDT 24
Finished Jul 15 05:30:09 PM PDT 24
Peak memory 217132 kb
Host smart-ca1fe179-a1fd-4c2d-ae8a-33af0249c061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781583394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.781583394
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2116258907
Short name T768
Test name
Test status
Simulation time 1312728061 ps
CPU time 27.99 seconds
Started Jul 15 05:30:06 PM PDT 24
Finished Jul 15 05:30:35 PM PDT 24
Peak memory 250380 kb
Host smart-62f80714-0db9-4fc5-a460-e58d81f624ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116258907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2116258907
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2944896902
Short name T771
Test name
Test status
Simulation time 100741758 ps
CPU time 8.54 seconds
Started Jul 15 05:30:07 PM PDT 24
Finished Jul 15 05:30:16 PM PDT 24
Peak memory 250432 kb
Host smart-19326706-c164-46e3-89a7-1fc4a42ebf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944896902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2944896902
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3754138597
Short name T641
Test name
Test status
Simulation time 1373687282 ps
CPU time 37.67 seconds
Started Jul 15 05:30:04 PM PDT 24
Finished Jul 15 05:30:43 PM PDT 24
Peak memory 258688 kb
Host smart-0e09390f-a373-4ea8-8d95-28dcadccfbc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754138597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3754138597
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2313240149
Short name T456
Test name
Test status
Simulation time 45021912 ps
CPU time 0.94 seconds
Started Jul 15 05:30:04 PM PDT 24
Finished Jul 15 05:30:06 PM PDT 24
Peak memory 211344 kb
Host smart-e092782b-3424-4a1d-9c27-98908af980cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313240149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2313240149
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.937096574
Short name T406
Test name
Test status
Simulation time 32584064 ps
CPU time 1.42 seconds
Started Jul 15 05:30:19 PM PDT 24
Finished Jul 15 05:30:21 PM PDT 24
Peak memory 208424 kb
Host smart-bb81fb40-6492-42e4-9b2e-a59de8a45d43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937096574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.937096574
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3816363871
Short name T790
Test name
Test status
Simulation time 236100973 ps
CPU time 8.66 seconds
Started Jul 15 05:30:07 PM PDT 24
Finished Jul 15 05:30:16 PM PDT 24
Peak memory 217612 kb
Host smart-02bfe717-1fb1-476d-b9fe-d09553594c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816363871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3816363871
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.158263134
Short name T379
Test name
Test status
Simulation time 1057449424 ps
CPU time 7.45 seconds
Started Jul 15 05:30:03 PM PDT 24
Finished Jul 15 05:30:11 PM PDT 24
Peak memory 217028 kb
Host smart-595a8980-ab2f-49db-808a-8fd1ac3816a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158263134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.158263134
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3960230389
Short name T298
Test name
Test status
Simulation time 229678389 ps
CPU time 3.6 seconds
Started Jul 15 05:30:05 PM PDT 24
Finished Jul 15 05:30:10 PM PDT 24
Peak memory 222028 kb
Host smart-af605919-8ce5-49da-b96b-ff594f159b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960230389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3960230389
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1145104072
Short name T534
Test name
Test status
Simulation time 361498944 ps
CPU time 17.96 seconds
Started Jul 15 05:30:06 PM PDT 24
Finished Jul 15 05:30:25 PM PDT 24
Peak memory 225472 kb
Host smart-5cfe65ff-884c-4d06-ab5f-9be6cd43a2b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145104072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1145104072
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.4159555125
Short name T388
Test name
Test status
Simulation time 518898238 ps
CPU time 13.83 seconds
Started Jul 15 05:30:07 PM PDT 24
Finished Jul 15 05:30:22 PM PDT 24
Peak memory 225412 kb
Host smart-9b7157ff-bd5a-4c9e-8958-e82becb66b35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159555125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.4159555125
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.4145706574
Short name T813
Test name
Test status
Simulation time 234351963 ps
CPU time 6.81 seconds
Started Jul 15 05:30:07 PM PDT 24
Finished Jul 15 05:30:15 PM PDT 24
Peak memory 225076 kb
Host smart-063fd277-6c84-49ec-a13b-e5a7352e8d33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145706574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
4145706574
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.636310838
Short name T436
Test name
Test status
Simulation time 170810142 ps
CPU time 6.51 seconds
Started Jul 15 05:30:05 PM PDT 24
Finished Jul 15 05:30:13 PM PDT 24
Peak memory 224040 kb
Host smart-3c95b266-473c-4b87-8f4f-347ad292798a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636310838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.636310838
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2016549696
Short name T84
Test name
Test status
Simulation time 505667493 ps
CPU time 2.67 seconds
Started Jul 15 05:30:05 PM PDT 24
Finished Jul 15 05:30:09 PM PDT 24
Peak memory 213932 kb
Host smart-b476af53-4ef9-4ce8-9f07-9b8e731a289d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016549696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2016549696
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.4236048241
Short name T169
Test name
Test status
Simulation time 1780048050 ps
CPU time 22.24 seconds
Started Jul 15 05:30:06 PM PDT 24
Finished Jul 15 05:30:30 PM PDT 24
Peak memory 250456 kb
Host smart-7894bbc5-6a2f-4f01-bef6-ef98c566741f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236048241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.4236048241
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1713168256
Short name T366
Test name
Test status
Simulation time 208577374 ps
CPU time 6.86 seconds
Started Jul 15 05:30:06 PM PDT 24
Finished Jul 15 05:30:15 PM PDT 24
Peak memory 249976 kb
Host smart-0e7c55fb-0237-41f6-b56d-4a64f42b714e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713168256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1713168256
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.533628111
Short name T405
Test name
Test status
Simulation time 42453703059 ps
CPU time 191.25 seconds
Started Jul 15 05:30:07 PM PDT 24
Finished Jul 15 05:33:19 PM PDT 24
Peak memory 315996 kb
Host smart-b5823ee9-5d5b-407a-a50c-81a0877a8ac4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533628111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.533628111
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.992066883
Short name T336
Test name
Test status
Simulation time 14946046 ps
CPU time 0.96 seconds
Started Jul 15 05:30:04 PM PDT 24
Finished Jul 15 05:30:06 PM PDT 24
Peak memory 208584 kb
Host smart-8e90b983-4a3d-4adc-adaf-19caa34f899f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992066883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct
rl_volatile_unlock_smoke.992066883
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.6125664
Short name T256
Test name
Test status
Simulation time 16588660 ps
CPU time 1.15 seconds
Started Jul 15 05:30:12 PM PDT 24
Finished Jul 15 05:30:14 PM PDT 24
Peak memory 208492 kb
Host smart-34a23856-88ec-4109-b21c-462d5e7506bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6125664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.6125664
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3917957995
Short name T467
Test name
Test status
Simulation time 520521011 ps
CPU time 14.65 seconds
Started Jul 15 05:30:12 PM PDT 24
Finished Jul 15 05:30:27 PM PDT 24
Peak memory 225512 kb
Host smart-64b226ca-04e6-468b-8ae7-d5ce75ce7200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917957995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3917957995
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2302336979
Short name T582
Test name
Test status
Simulation time 457647870 ps
CPU time 5.53 seconds
Started Jul 15 05:30:12 PM PDT 24
Finished Jul 15 05:30:18 PM PDT 24
Peak memory 216672 kb
Host smart-ab63b090-1dc7-4511-ab68-4aaf9c898ec7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302336979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2302336979
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.318147451
Short name T531
Test name
Test status
Simulation time 133235212 ps
CPU time 3.34 seconds
Started Jul 15 05:30:12 PM PDT 24
Finished Jul 15 05:30:16 PM PDT 24
Peak memory 217652 kb
Host smart-74f17cb0-7ca8-4692-8c50-c4a7e93fe08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318147451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.318147451
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1658650924
Short name T759
Test name
Test status
Simulation time 607790450 ps
CPU time 14.59 seconds
Started Jul 15 05:30:13 PM PDT 24
Finished Jul 15 05:30:28 PM PDT 24
Peak memory 219408 kb
Host smart-21654e71-502b-46d1-9dba-da8c7237c4ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658650924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1658650924
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3873944560
Short name T833
Test name
Test status
Simulation time 761230463 ps
CPU time 13.07 seconds
Started Jul 15 05:30:13 PM PDT 24
Finished Jul 15 05:30:27 PM PDT 24
Peak memory 225476 kb
Host smart-de4c8930-6a30-444f-846b-9e780196b1c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873944560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3873944560
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3289607658
Short name T785
Test name
Test status
Simulation time 567347705 ps
CPU time 8.72 seconds
Started Jul 15 05:30:18 PM PDT 24
Finished Jul 15 05:30:28 PM PDT 24
Peak memory 217628 kb
Host smart-27ff1c99-6ff9-435c-89b2-fcf6a7aeaafe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289607658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3289607658
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.776527813
Short name T362
Test name
Test status
Simulation time 930239088 ps
CPU time 7.74 seconds
Started Jul 15 05:30:11 PM PDT 24
Finished Jul 15 05:30:19 PM PDT 24
Peak memory 224712 kb
Host smart-643e4cee-6742-493a-87b5-bb1a69ecae28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776527813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.776527813
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3059120442
Short name T88
Test name
Test status
Simulation time 438913401 ps
CPU time 7.45 seconds
Started Jul 15 05:30:12 PM PDT 24
Finished Jul 15 05:30:20 PM PDT 24
Peak memory 217128 kb
Host smart-2d21c112-8091-40a9-92dd-08b295d4ea4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059120442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3059120442
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2656500674
Short name T742
Test name
Test status
Simulation time 706034685 ps
CPU time 25.4 seconds
Started Jul 15 05:30:12 PM PDT 24
Finished Jul 15 05:30:37 PM PDT 24
Peak memory 250400 kb
Host smart-46fb28ef-4ba6-4de0-b1e2-cc436c8896fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656500674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2656500674
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.226552054
Short name T559
Test name
Test status
Simulation time 48949150 ps
CPU time 7.44 seconds
Started Jul 15 05:30:17 PM PDT 24
Finished Jul 15 05:30:25 PM PDT 24
Peak memory 250408 kb
Host smart-27165ec2-1b98-471f-a858-abd8208f1190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226552054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.226552054
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.84530956
Short name T16
Test name
Test status
Simulation time 28084024649 ps
CPU time 614.98 seconds
Started Jul 15 05:30:18 PM PDT 24
Finished Jul 15 05:40:33 PM PDT 24
Peak memory 267000 kb
Host smart-b144a46f-f35b-4f65-8e24-bd95c124a061
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84530956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.lc_ctrl_stress_all.84530956
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.916076770
Short name T97
Test name
Test status
Simulation time 4110826952 ps
CPU time 102.9 seconds
Started Jul 15 05:30:11 PM PDT 24
Finished Jul 15 05:31:55 PM PDT 24
Peak memory 316208 kb
Host smart-103a5fb3-1689-4aba-ba35-9cd5ecadbb68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=916076770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.916076770
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.152670503
Short name T523
Test name
Test status
Simulation time 135994091 ps
CPU time 0.81 seconds
Started Jul 15 05:30:12 PM PDT 24
Finished Jul 15 05:30:13 PM PDT 24
Peak memory 208352 kb
Host smart-84cbd1db-a4d0-4ebd-8256-71b7b702de61
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152670503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.152670503
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2710406884
Short name T80
Test name
Test status
Simulation time 22017365 ps
CPU time 0.94 seconds
Started Jul 15 05:30:20 PM PDT 24
Finished Jul 15 05:30:23 PM PDT 24
Peak memory 208368 kb
Host smart-f14cd6d3-6950-4811-b92a-189e4d3a3686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710406884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2710406884
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2692525242
Short name T555
Test name
Test status
Simulation time 231540039 ps
CPU time 11.75 seconds
Started Jul 15 05:30:11 PM PDT 24
Finished Jul 15 05:30:24 PM PDT 24
Peak memory 217580 kb
Host smart-ba7f3eb7-d15e-41f6-8ab7-b295ac536303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692525242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2692525242
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.815900241
Short name T734
Test name
Test status
Simulation time 9624410331 ps
CPU time 14.42 seconds
Started Jul 15 05:30:21 PM PDT 24
Finished Jul 15 05:30:36 PM PDT 24
Peak memory 217196 kb
Host smart-5d82ab94-92c9-442b-9f5b-912fc4a35beb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815900241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.815900241
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2072783165
Short name T358
Test name
Test status
Simulation time 63220853 ps
CPU time 1.61 seconds
Started Jul 15 05:30:14 PM PDT 24
Finished Jul 15 05:30:16 PM PDT 24
Peak memory 217628 kb
Host smart-6dd543c8-faf9-4db0-bf0a-bf30a8f2817b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072783165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2072783165
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1620467596
Short name T639
Test name
Test status
Simulation time 336253139 ps
CPU time 13.34 seconds
Started Jul 15 05:30:21 PM PDT 24
Finished Jul 15 05:30:35 PM PDT 24
Peak memory 225452 kb
Host smart-ba624485-6bb7-4074-abde-c8f8cdd9a22d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620467596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1620467596
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.660959144
Short name T316
Test name
Test status
Simulation time 1505768797 ps
CPU time 11.18 seconds
Started Jul 15 05:30:18 PM PDT 24
Finished Jul 15 05:30:30 PM PDT 24
Peak memory 225380 kb
Host smart-05a59e34-26ae-48b6-861e-6830e85946ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660959144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.660959144
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3420917195
Short name T391
Test name
Test status
Simulation time 277580754 ps
CPU time 9.83 seconds
Started Jul 15 05:30:19 PM PDT 24
Finished Jul 15 05:30:30 PM PDT 24
Peak memory 217688 kb
Host smart-77b1ee8e-b03f-4819-bade-8c6458077ead
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420917195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3420917195
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.139178580
Short name T629
Test name
Test status
Simulation time 533840279 ps
CPU time 13.64 seconds
Started Jul 15 05:30:15 PM PDT 24
Finished Jul 15 05:30:29 PM PDT 24
Peak memory 217732 kb
Host smart-5389f2b1-9db2-4463-b577-54341885e484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139178580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.139178580
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2365413131
Short name T568
Test name
Test status
Simulation time 2597625434 ps
CPU time 5.2 seconds
Started Jul 15 05:30:14 PM PDT 24
Finished Jul 15 05:30:20 PM PDT 24
Peak memory 217144 kb
Host smart-c047c7d3-a0e8-46de-a2dc-aa97bdb9fcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365413131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2365413131
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3057024800
Short name T303
Test name
Test status
Simulation time 876863443 ps
CPU time 23.2 seconds
Started Jul 15 05:30:17 PM PDT 24
Finished Jul 15 05:30:41 PM PDT 24
Peak memory 250424 kb
Host smart-96fe720c-96b6-4861-8a5a-9e3ee8d3f180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057024800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3057024800
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.4189902913
Short name T448
Test name
Test status
Simulation time 426106871 ps
CPU time 7.91 seconds
Started Jul 15 05:30:14 PM PDT 24
Finished Jul 15 05:30:23 PM PDT 24
Peak memory 250488 kb
Host smart-b60fc94b-1970-420d-84b9-a3e40be271c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189902913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.4189902913
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.922590390
Short name T175
Test name
Test status
Simulation time 21967309849 ps
CPU time 75.8 seconds
Started Jul 15 05:30:21 PM PDT 24
Finished Jul 15 05:31:38 PM PDT 24
Peak memory 250436 kb
Host smart-99c5ab77-da6a-45b4-b0d7-5fff02d40a4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922590390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.922590390
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2790691573
Short name T35
Test name
Test status
Simulation time 23010227 ps
CPU time 0.82 seconds
Started Jul 15 05:30:14 PM PDT 24
Finished Jul 15 05:30:15 PM PDT 24
Peak memory 208432 kb
Host smart-bf2b2b23-aa40-4972-b249-9431822aebf6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790691573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.2790691573
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2741214840
Short name T661
Test name
Test status
Simulation time 21695223 ps
CPU time 1.17 seconds
Started Jul 15 05:30:21 PM PDT 24
Finished Jul 15 05:30:23 PM PDT 24
Peak memory 208412 kb
Host smart-ff962a26-ea30-427c-bfa3-acb750f4a3b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741214840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2741214840
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2654798306
Short name T453
Test name
Test status
Simulation time 504245237 ps
CPU time 18.36 seconds
Started Jul 15 05:30:20 PM PDT 24
Finished Jul 15 05:30:39 PM PDT 24
Peak memory 217600 kb
Host smart-96967f75-c255-4bdb-828a-0ad7a7e4e9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654798306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2654798306
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.668615662
Short name T631
Test name
Test status
Simulation time 1487290434 ps
CPU time 14.31 seconds
Started Jul 15 05:30:20 PM PDT 24
Finished Jul 15 05:30:36 PM PDT 24
Peak memory 217048 kb
Host smart-f5dc7e4b-27c0-4db7-a505-424bb043894c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668615662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.668615662
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2239657694
Short name T557
Test name
Test status
Simulation time 18269071 ps
CPU time 1.49 seconds
Started Jul 15 05:30:21 PM PDT 24
Finished Jul 15 05:30:23 PM PDT 24
Peak memory 221204 kb
Host smart-fa78b673-90c0-4604-afcb-f1986775951e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239657694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2239657694
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1026638587
Short name T390
Test name
Test status
Simulation time 1745014194 ps
CPU time 18.41 seconds
Started Jul 15 05:30:19 PM PDT 24
Finished Jul 15 05:30:38 PM PDT 24
Peak memory 225112 kb
Host smart-ab05c784-19a6-42d0-b93a-c75d7c2d10c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026638587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1026638587
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.711777308
Short name T811
Test name
Test status
Simulation time 1358323324 ps
CPU time 13.28 seconds
Started Jul 15 05:30:18 PM PDT 24
Finished Jul 15 05:30:32 PM PDT 24
Peak memory 225400 kb
Host smart-663fa8ca-9f84-4be0-b089-a45f8bc09fef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711777308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_di
gest.711777308
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1885601016
Short name T387
Test name
Test status
Simulation time 2574018717 ps
CPU time 8.52 seconds
Started Jul 15 05:30:18 PM PDT 24
Finished Jul 15 05:30:28 PM PDT 24
Peak memory 217660 kb
Host smart-019e7b92-dfdb-4a1b-8095-c8e2c3eeaad9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885601016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1885601016
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3829024125
Short name T522
Test name
Test status
Simulation time 486734890 ps
CPU time 6.26 seconds
Started Jul 15 05:30:18 PM PDT 24
Finished Jul 15 05:30:25 PM PDT 24
Peak memory 217688 kb
Host smart-c8267512-a64f-4667-8bdb-57df3f669356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829024125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3829024125
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3895378889
Short name T12
Test name
Test status
Simulation time 114290622 ps
CPU time 1.13 seconds
Started Jul 15 05:30:20 PM PDT 24
Finished Jul 15 05:30:21 PM PDT 24
Peak memory 211652 kb
Host smart-d0a654c5-22d3-4c5e-b88f-237929c8f9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895378889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3895378889
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1311593884
Short name T428
Test name
Test status
Simulation time 179852693 ps
CPU time 18.23 seconds
Started Jul 15 05:30:20 PM PDT 24
Finished Jul 15 05:30:40 PM PDT 24
Peak memory 250468 kb
Host smart-04b46027-7cbe-4add-a72c-0db4870bcdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311593884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1311593884
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2284307299
Short name T862
Test name
Test status
Simulation time 105262307 ps
CPU time 8.87 seconds
Started Jul 15 05:30:21 PM PDT 24
Finished Jul 15 05:30:31 PM PDT 24
Peak memory 250364 kb
Host smart-7c5e5f30-aa95-49e4-8ca2-9588a3d2d26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284307299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2284307299
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1558754787
Short name T68
Test name
Test status
Simulation time 1726509201 ps
CPU time 61.48 seconds
Started Jul 15 05:30:18 PM PDT 24
Finished Jul 15 05:31:21 PM PDT 24
Peak memory 266900 kb
Host smart-f557e08e-e7e7-4636-b5da-2ed6a42bfb96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558754787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1558754787
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3280909306
Short name T830
Test name
Test status
Simulation time 14489426 ps
CPU time 0.81 seconds
Started Jul 15 05:30:20 PM PDT 24
Finished Jul 15 05:30:22 PM PDT 24
Peak memory 208280 kb
Host smart-10847a14-25e4-4133-b5b7-07d12f236119
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280909306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3280909306
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.7444573
Short name T796
Test name
Test status
Simulation time 17136045 ps
CPU time 1.13 seconds
Started Jul 15 05:30:29 PM PDT 24
Finished Jul 15 05:30:30 PM PDT 24
Peak memory 208452 kb
Host smart-77eddc66-33f6-4d76-9ef3-16cda46d7895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7444573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.7444573
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1897233073
Short name T540
Test name
Test status
Simulation time 374543395 ps
CPU time 12.66 seconds
Started Jul 15 05:30:27 PM PDT 24
Finished Jul 15 05:30:41 PM PDT 24
Peak memory 217656 kb
Host smart-01a3301d-a226-4a6e-8ae3-9b16bf938fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897233073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1897233073
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3618423753
Short name T153
Test name
Test status
Simulation time 908835527 ps
CPU time 2.3 seconds
Started Jul 15 05:30:30 PM PDT 24
Finished Jul 15 05:30:33 PM PDT 24
Peak memory 217068 kb
Host smart-bc078df7-d56c-4481-bc4c-7153633fece7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618423753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3618423753
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3983374991
Short name T481
Test name
Test status
Simulation time 71801890 ps
CPU time 2.8 seconds
Started Jul 15 05:30:27 PM PDT 24
Finished Jul 15 05:30:31 PM PDT 24
Peak memory 217848 kb
Host smart-21fef3f1-fb20-441c-bc45-7fea81c2d100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983374991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3983374991
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.4052989623
Short name T789
Test name
Test status
Simulation time 1467081244 ps
CPU time 24.87 seconds
Started Jul 15 05:30:30 PM PDT 24
Finished Jul 15 05:30:56 PM PDT 24
Peak memory 218332 kb
Host smart-11f5dad6-8464-4f14-b69c-96e0c1f97041
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052989623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.4052989623
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3518560464
Short name T850
Test name
Test status
Simulation time 2188410262 ps
CPU time 12.09 seconds
Started Jul 15 05:30:28 PM PDT 24
Finished Jul 15 05:30:41 PM PDT 24
Peak memory 225452 kb
Host smart-416d2fc2-977b-4345-a8fc-c8317a89295c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518560464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3518560464
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3111235410
Short name T632
Test name
Test status
Simulation time 3939486540 ps
CPU time 9.24 seconds
Started Jul 15 05:30:28 PM PDT 24
Finished Jul 15 05:30:38 PM PDT 24
Peak memory 225444 kb
Host smart-119de286-15ce-4ac7-b6bf-ebdaf0ea1256
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111235410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3111235410
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3739322966
Short name T766
Test name
Test status
Simulation time 206618842 ps
CPU time 8.48 seconds
Started Jul 15 05:30:28 PM PDT 24
Finished Jul 15 05:30:38 PM PDT 24
Peak memory 224148 kb
Host smart-eb3a332d-b589-4e2d-b832-7fc6cd52b900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739322966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3739322966
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.375598268
Short name T307
Test name
Test status
Simulation time 31410883 ps
CPU time 1.67 seconds
Started Jul 15 05:30:19 PM PDT 24
Finished Jul 15 05:30:21 PM PDT 24
Peak memory 213144 kb
Host smart-a11ef1cc-57c2-463a-8f84-4476d2dcea0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375598268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.375598268
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3145525842
Short name T658
Test name
Test status
Simulation time 318250960 ps
CPU time 21.78 seconds
Started Jul 15 05:30:20 PM PDT 24
Finished Jul 15 05:30:43 PM PDT 24
Peak memory 250468 kb
Host smart-4bd6baab-599d-439e-afc7-19e3bcdf2789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145525842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3145525842
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2370040717
Short name T427
Test name
Test status
Simulation time 390110594 ps
CPU time 6.74 seconds
Started Jul 15 05:30:20 PM PDT 24
Finished Jul 15 05:30:27 PM PDT 24
Peak memory 246008 kb
Host smart-486713d7-127f-4a3b-b60c-de54780b9d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370040717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2370040717
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1546591391
Short name T236
Test name
Test status
Simulation time 16269970896 ps
CPU time 136.4 seconds
Started Jul 15 05:30:28 PM PDT 24
Finished Jul 15 05:32:45 PM PDT 24
Peak memory 266796 kb
Host smart-51b80189-3bb6-4dc7-be99-86d2bd20e4e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546591391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1546591391
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3570817077
Short name T234
Test name
Test status
Simulation time 26935476 ps
CPU time 0.83 seconds
Started Jul 15 05:30:20 PM PDT 24
Finished Jul 15 05:30:21 PM PDT 24
Peak memory 208176 kb
Host smart-943a20ff-6414-4a83-a481-f804ca80b647
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570817077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3570817077
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.821749437
Short name T209
Test name
Test status
Simulation time 21338924 ps
CPU time 1 seconds
Started Jul 15 05:27:10 PM PDT 24
Finished Jul 15 05:27:12 PM PDT 24
Peak memory 208456 kb
Host smart-25f58ea9-ec15-4c97-be89-86b1510a41c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821749437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.821749437
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1732281705
Short name T463
Test name
Test status
Simulation time 687147094 ps
CPU time 12.79 seconds
Started Jul 15 05:27:04 PM PDT 24
Finished Jul 15 05:27:18 PM PDT 24
Peak memory 217676 kb
Host smart-314da0af-c5b4-44d1-ad4b-783ae2e6b9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732281705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1732281705
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3320635679
Short name T355
Test name
Test status
Simulation time 4788309309 ps
CPU time 10.55 seconds
Started Jul 15 05:27:02 PM PDT 24
Finished Jul 15 05:27:13 PM PDT 24
Peak memory 217124 kb
Host smart-d502cd08-96ca-4830-bc4d-fed77d8a1f7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320635679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3320635679
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3395316823
Short name T495
Test name
Test status
Simulation time 3399594647 ps
CPU time 43.14 seconds
Started Jul 15 05:27:03 PM PDT 24
Finished Jul 15 05:27:47 PM PDT 24
Peak memory 218380 kb
Host smart-1713e250-c975-433c-9d3e-0202c403b14c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395316823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3395316823
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1990456349
Short name T263
Test name
Test status
Simulation time 474062098 ps
CPU time 5.61 seconds
Started Jul 15 05:27:03 PM PDT 24
Finished Jul 15 05:27:09 PM PDT 24
Peak memory 217124 kb
Host smart-61ff0aee-ddbf-463f-9d37-207bba43458a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990456349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
990456349
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.521196101
Short name T556
Test name
Test status
Simulation time 1050971575 ps
CPU time 16.65 seconds
Started Jul 15 05:27:02 PM PDT 24
Finished Jul 15 05:27:19 PM PDT 24
Peak memory 217636 kb
Host smart-2c776ee7-a639-47f8-80f1-89c270638bbb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521196101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.521196101
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3735372345
Short name T413
Test name
Test status
Simulation time 5471486948 ps
CPU time 20.28 seconds
Started Jul 15 05:27:02 PM PDT 24
Finished Jul 15 05:27:23 PM PDT 24
Peak memory 217052 kb
Host smart-f61960d5-4e59-4b1e-82bf-3e2c9c556ebc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735372345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3735372345
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.569956600
Short name T567
Test name
Test status
Simulation time 835082922 ps
CPU time 5.68 seconds
Started Jul 15 05:27:03 PM PDT 24
Finished Jul 15 05:27:09 PM PDT 24
Peak memory 216996 kb
Host smart-f760ce75-e7bf-454c-9fa6-be26a0a61f3b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569956600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.569956600
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1178291632
Short name T370
Test name
Test status
Simulation time 1165790315 ps
CPU time 38.05 seconds
Started Jul 15 05:27:03 PM PDT 24
Finished Jul 15 05:27:41 PM PDT 24
Peak memory 266772 kb
Host smart-15f5ff55-d2bd-4e67-8480-d8d50e49cd68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178291632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1178291632
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3985332615
Short name T592
Test name
Test status
Simulation time 608696789 ps
CPU time 23.43 seconds
Started Jul 15 05:27:02 PM PDT 24
Finished Jul 15 05:27:26 PM PDT 24
Peak memory 250340 kb
Host smart-0dab120f-be69-4318-875c-4ae0bdd2dfaf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985332615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.3985332615
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.4137923632
Short name T275
Test name
Test status
Simulation time 44952662 ps
CPU time 2.3 seconds
Started Jul 15 05:27:03 PM PDT 24
Finished Jul 15 05:27:06 PM PDT 24
Peak memory 217632 kb
Host smart-e0fbb6f5-8ab2-46f2-af1c-994dc095f100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137923632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.4137923632
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.592963334
Short name T593
Test name
Test status
Simulation time 997617686 ps
CPU time 6.39 seconds
Started Jul 15 05:27:04 PM PDT 24
Finished Jul 15 05:27:11 PM PDT 24
Peak memory 217104 kb
Host smart-57ea7c2c-6026-4d43-bbc5-df63c4bea258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592963334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.592963334
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1422963165
Short name T54
Test name
Test status
Simulation time 2751006671 ps
CPU time 36.46 seconds
Started Jul 15 05:27:15 PM PDT 24
Finished Jul 15 05:27:51 PM PDT 24
Peak memory 282248 kb
Host smart-4a142001-b63b-4759-8295-e202bceb3de7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422963165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1422963165
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2733899010
Short name T627
Test name
Test status
Simulation time 340113392 ps
CPU time 10.31 seconds
Started Jul 15 05:27:03 PM PDT 24
Finished Jul 15 05:27:14 PM PDT 24
Peak memory 218304 kb
Host smart-7f771651-7fc3-4a44-af18-7f08052c91ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733899010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2733899010
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1724896385
Short name T292
Test name
Test status
Simulation time 651464860 ps
CPU time 9.79 seconds
Started Jul 15 05:27:13 PM PDT 24
Finished Jul 15 05:27:23 PM PDT 24
Peak memory 225424 kb
Host smart-7c9afc58-b9c0-4554-b87b-d7fed55c0622
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724896385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1724896385
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.118391695
Short name T417
Test name
Test status
Simulation time 296218276 ps
CPU time 6.69 seconds
Started Jul 15 05:27:11 PM PDT 24
Finished Jul 15 05:27:18 PM PDT 24
Peak memory 217616 kb
Host smart-70890ad9-f18a-46f9-bf83-00520d847f24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118391695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.118391695
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3332812590
Short name T664
Test name
Test status
Simulation time 514062159 ps
CPU time 13.52 seconds
Started Jul 15 05:27:02 PM PDT 24
Finished Jul 15 05:27:17 PM PDT 24
Peak memory 224500 kb
Host smart-d34c8015-6535-4a03-9121-02cc66f3a8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332812590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3332812590
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.583941306
Short name T386
Test name
Test status
Simulation time 279758421 ps
CPU time 2.47 seconds
Started Jul 15 05:27:02 PM PDT 24
Finished Jul 15 05:27:05 PM PDT 24
Peak memory 217120 kb
Host smart-bfb0ff09-3b32-4557-81ec-59d714075563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583941306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.583941306
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1522051188
Short name T100
Test name
Test status
Simulation time 661908363 ps
CPU time 34.14 seconds
Started Jul 15 05:27:02 PM PDT 24
Finished Jul 15 05:27:37 PM PDT 24
Peak memory 250472 kb
Host smart-6823d217-6727-44f4-8095-879d78d8b3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522051188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1522051188
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2881182015
Short name T30
Test name
Test status
Simulation time 612064191 ps
CPU time 6.87 seconds
Started Jul 15 05:27:03 PM PDT 24
Finished Jul 15 05:27:10 PM PDT 24
Peak memory 246492 kb
Host smart-b12d7d05-d570-4bb9-af8f-00ce16f170cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881182015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2881182015
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3353070782
Short name T760
Test name
Test status
Simulation time 5936362782 ps
CPU time 52.23 seconds
Started Jul 15 05:27:12 PM PDT 24
Finished Jul 15 05:28:05 PM PDT 24
Peak memory 276628 kb
Host smart-c4b863f8-f223-4138-8e7b-fa7eb96dbfcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353070782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3353070782
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1203057438
Short name T36
Test name
Test status
Simulation time 19000072 ps
CPU time 0.83 seconds
Started Jul 15 05:27:03 PM PDT 24
Finished Jul 15 05:27:05 PM PDT 24
Peak memory 208332 kb
Host smart-5f3b0526-b201-4dd5-b9c3-2569ec9490a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203057438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1203057438
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.2382415751
Short name T673
Test name
Test status
Simulation time 12276087 ps
CPU time 0.81 seconds
Started Jul 15 05:30:38 PM PDT 24
Finished Jul 15 05:30:40 PM PDT 24
Peak memory 208256 kb
Host smart-59aa430f-2ac7-4255-b56c-025bfe553c2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382415751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2382415751
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.811751205
Short name T838
Test name
Test status
Simulation time 1316368732 ps
CPU time 9.85 seconds
Started Jul 15 05:30:29 PM PDT 24
Finished Jul 15 05:30:39 PM PDT 24
Peak memory 225520 kb
Host smart-17bcc71b-8049-4855-8b5c-931fcb36dfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811751205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.811751205
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2919752393
Short name T377
Test name
Test status
Simulation time 2007124492 ps
CPU time 4.9 seconds
Started Jul 15 05:30:28 PM PDT 24
Finished Jul 15 05:30:34 PM PDT 24
Peak memory 217076 kb
Host smart-6d3a108f-6541-4d5b-b66e-5e4b7afc0cf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919752393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2919752393
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2578652186
Short name T306
Test name
Test status
Simulation time 24707365 ps
CPU time 1.88 seconds
Started Jul 15 05:30:29 PM PDT 24
Finished Jul 15 05:30:31 PM PDT 24
Peak memory 217704 kb
Host smart-fa29b24e-eca8-481f-93e9-559cf0c94d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578652186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2578652186
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1553827526
Short name T670
Test name
Test status
Simulation time 352250078 ps
CPU time 10.9 seconds
Started Jul 15 05:30:27 PM PDT 24
Finished Jul 15 05:30:39 PM PDT 24
Peak memory 225436 kb
Host smart-31d5aba6-3f63-4847-bba4-a0f96a575023
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553827526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1553827526
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1956361077
Short name T418
Test name
Test status
Simulation time 266006816 ps
CPU time 8.39 seconds
Started Jul 15 05:30:28 PM PDT 24
Finished Jul 15 05:30:37 PM PDT 24
Peak memory 225480 kb
Host smart-5298edd0-4350-44cb-9d64-20ffa56d4c5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956361077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1956361077
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3926624669
Short name T564
Test name
Test status
Simulation time 4833376646 ps
CPU time 12.85 seconds
Started Jul 15 05:30:30 PM PDT 24
Finished Jul 15 05:30:43 PM PDT 24
Peak memory 217772 kb
Host smart-b3a5f99f-c013-49a4-83c0-4ecfefebaff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926624669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3926624669
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.89272256
Short name T575
Test name
Test status
Simulation time 93526796 ps
CPU time 2.22 seconds
Started Jul 15 05:30:32 PM PDT 24
Finished Jul 15 05:30:34 PM PDT 24
Peak memory 217108 kb
Host smart-29604a8a-e505-4350-bf65-c0cd8ffcb98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89272256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.89272256
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.4052673926
Short name T843
Test name
Test status
Simulation time 1094217780 ps
CPU time 28.93 seconds
Started Jul 15 05:30:30 PM PDT 24
Finished Jul 15 05:30:59 PM PDT 24
Peak memory 250404 kb
Host smart-a4700f5b-bd58-46aa-98c4-8cbfe501dc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052673926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.4052673926
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.501412769
Short name T378
Test name
Test status
Simulation time 137112808 ps
CPU time 7.92 seconds
Started Jul 15 05:30:29 PM PDT 24
Finished Jul 15 05:30:37 PM PDT 24
Peak memory 250452 kb
Host smart-383d3437-4651-4d94-ac30-fd37f1b041a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501412769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.501412769
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3329654529
Short name T361
Test name
Test status
Simulation time 15094344956 ps
CPU time 254.83 seconds
Started Jul 15 05:30:27 PM PDT 24
Finished Jul 15 05:34:43 PM PDT 24
Peak memory 267428 kb
Host smart-bf2001e1-b9d7-41b8-8842-0053a547c360
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329654529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3329654529
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1633154280
Short name T711
Test name
Test status
Simulation time 16481358 ps
CPU time 1.25 seconds
Started Jul 15 05:30:31 PM PDT 24
Finished Jul 15 05:30:33 PM PDT 24
Peak memory 217084 kb
Host smart-8c7817f2-b349-492b-94d5-adefa809a670
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633154280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1633154280
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3773559937
Short name T687
Test name
Test status
Simulation time 98741531 ps
CPU time 0.88 seconds
Started Jul 15 05:30:38 PM PDT 24
Finished Jul 15 05:30:40 PM PDT 24
Peak memory 208320 kb
Host smart-5b27dc2e-f4b2-4f6c-a127-d36784836499
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773559937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3773559937
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.722873583
Short name T730
Test name
Test status
Simulation time 4822512257 ps
CPU time 17.96 seconds
Started Jul 15 05:30:54 PM PDT 24
Finished Jul 15 05:31:12 PM PDT 24
Peak memory 218452 kb
Host smart-d17a8650-a738-4cf6-ae79-c30b2c59075c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722873583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.722873583
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.102014431
Short name T775
Test name
Test status
Simulation time 489830464 ps
CPU time 2.49 seconds
Started Jul 15 05:30:39 PM PDT 24
Finished Jul 15 05:30:43 PM PDT 24
Peak memory 216548 kb
Host smart-427238d7-d46b-4892-86d5-6fc22292db83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102014431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.102014431
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3071733528
Short name T342
Test name
Test status
Simulation time 184455541 ps
CPU time 4.33 seconds
Started Jul 15 05:30:39 PM PDT 24
Finished Jul 15 05:30:45 PM PDT 24
Peak memory 217684 kb
Host smart-99050c31-30b6-4647-91a5-4d6ea2000e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071733528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3071733528
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2520009965
Short name T32
Test name
Test status
Simulation time 3480217744 ps
CPU time 12.54 seconds
Started Jul 15 05:30:39 PM PDT 24
Finished Jul 15 05:30:53 PM PDT 24
Peak memory 225408 kb
Host smart-ba854dfd-2ab1-43bc-9290-fe6ade8827be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520009965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2520009965
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.195336080
Short name T773
Test name
Test status
Simulation time 1972971020 ps
CPU time 11.5 seconds
Started Jul 15 05:30:38 PM PDT 24
Finished Jul 15 05:30:51 PM PDT 24
Peak memory 217668 kb
Host smart-c3ee78c4-a490-49cd-8932-a80c5ddb5320
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195336080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.195336080
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.4108171684
Short name T52
Test name
Test status
Simulation time 1723017837 ps
CPU time 14.75 seconds
Started Jul 15 05:30:37 PM PDT 24
Finished Jul 15 05:30:53 PM PDT 24
Peak memory 225440 kb
Host smart-1ebdc318-91dc-413d-bd76-3014dc1ce633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108171684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.4108171684
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1963361551
Short name T83
Test name
Test status
Simulation time 147366317 ps
CPU time 2.99 seconds
Started Jul 15 05:30:40 PM PDT 24
Finished Jul 15 05:30:44 PM PDT 24
Peak memory 214300 kb
Host smart-1ac7a7b2-a34e-4504-9156-dd02df481c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963361551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1963361551
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.589031497
Short name T809
Test name
Test status
Simulation time 397930225 ps
CPU time 16.51 seconds
Started Jul 15 05:30:38 PM PDT 24
Finished Jul 15 05:30:56 PM PDT 24
Peak memory 250484 kb
Host smart-c09476a8-eef0-41c5-984c-fbefd265550c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589031497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.589031497
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.4198747910
Short name T739
Test name
Test status
Simulation time 55198300 ps
CPU time 8.75 seconds
Started Jul 15 05:30:39 PM PDT 24
Finished Jul 15 05:30:49 PM PDT 24
Peak memory 250432 kb
Host smart-74a70035-ac32-436d-b4e9-81fdeea202f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198747910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.4198747910
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.4266530083
Short name T67
Test name
Test status
Simulation time 91222943 ps
CPU time 1.35 seconds
Started Jul 15 05:30:39 PM PDT 24
Finished Jul 15 05:30:41 PM PDT 24
Peak memory 217184 kb
Host smart-3fa2feb6-0d18-484e-985f-f1b6b440593b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266530083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.4266530083
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.422779150
Short name T669
Test name
Test status
Simulation time 38468751 ps
CPU time 1.04 seconds
Started Jul 15 05:30:38 PM PDT 24
Finished Jul 15 05:30:40 PM PDT 24
Peak memory 208576 kb
Host smart-a1c6562e-c5f2-401a-99a6-0ab9e52e795d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422779150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.422779150
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.311472765
Short name T500
Test name
Test status
Simulation time 1081027484 ps
CPU time 13.95 seconds
Started Jul 15 05:30:38 PM PDT 24
Finished Jul 15 05:30:54 PM PDT 24
Peak memory 217724 kb
Host smart-50c280a9-4a02-46bd-b700-f942ca104f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311472765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.311472765
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.340853606
Short name T655
Test name
Test status
Simulation time 3478632268 ps
CPU time 20.78 seconds
Started Jul 15 05:30:38 PM PDT 24
Finished Jul 15 05:31:00 PM PDT 24
Peak memory 217116 kb
Host smart-e7de0e21-5f7f-44cb-994b-f8bb4d6d6c58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340853606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.340853606
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3106831618
Short name T219
Test name
Test status
Simulation time 101802598 ps
CPU time 3.63 seconds
Started Jul 15 05:30:39 PM PDT 24
Finished Jul 15 05:30:44 PM PDT 24
Peak memory 222232 kb
Host smart-33ccc118-23d3-419c-8356-0f5b7aae64f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106831618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3106831618
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1675248216
Short name T384
Test name
Test status
Simulation time 695143545 ps
CPU time 15.42 seconds
Started Jul 15 05:30:38 PM PDT 24
Finished Jul 15 05:30:54 PM PDT 24
Peak memory 225448 kb
Host smart-569677d7-7cb1-4a78-9f65-9f2f5abf649e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675248216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1675248216
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2442583992
Short name T624
Test name
Test status
Simulation time 255643948 ps
CPU time 8.76 seconds
Started Jul 15 05:30:41 PM PDT 24
Finished Jul 15 05:30:51 PM PDT 24
Peak memory 225460 kb
Host smart-62283f0f-b5fa-4c7a-bb84-8e97049ace44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442583992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2442583992
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2231974730
Short name T313
Test name
Test status
Simulation time 321276981 ps
CPU time 10.08 seconds
Started Jul 15 05:30:37 PM PDT 24
Finished Jul 15 05:30:48 PM PDT 24
Peak memory 217624 kb
Host smart-1e8b2cdd-4cb5-4975-b474-f4b3cb754221
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231974730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2231974730
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3188653106
Short name T53
Test name
Test status
Simulation time 493444801 ps
CPU time 9.53 seconds
Started Jul 15 05:30:42 PM PDT 24
Finished Jul 15 05:30:52 PM PDT 24
Peak memory 225504 kb
Host smart-01685664-9d52-491f-a0fb-80f7eb25667f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188653106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3188653106
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3269469370
Short name T450
Test name
Test status
Simulation time 16149586 ps
CPU time 1.18 seconds
Started Jul 15 05:30:38 PM PDT 24
Finished Jul 15 05:30:40 PM PDT 24
Peak memory 217144 kb
Host smart-ec6b719e-ccdb-4752-9e95-7867c0d9f65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269469370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3269469370
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.160257180
Short name T518
Test name
Test status
Simulation time 1471848263 ps
CPU time 37.77 seconds
Started Jul 15 05:30:38 PM PDT 24
Finished Jul 15 05:31:17 PM PDT 24
Peak memory 250392 kb
Host smart-696c47a9-4ce5-4e24-bad3-feb2cc32291e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160257180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.160257180
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3885071328
Short name T713
Test name
Test status
Simulation time 203327035 ps
CPU time 8.04 seconds
Started Jul 15 05:30:40 PM PDT 24
Finished Jul 15 05:30:49 PM PDT 24
Peak memory 250348 kb
Host smart-8b3422b5-0ba8-4e39-b60f-1fc268035719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885071328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3885071328
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.345829549
Short name T784
Test name
Test status
Simulation time 45162668052 ps
CPU time 124.37 seconds
Started Jul 15 05:30:40 PM PDT 24
Finished Jul 15 05:32:46 PM PDT 24
Peak memory 282268 kb
Host smart-2f2aba9c-5e37-4e8d-a779-c61c5d348cbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345829549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.345829549
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2103225069
Short name T539
Test name
Test status
Simulation time 70879590 ps
CPU time 0.85 seconds
Started Jul 15 05:30:39 PM PDT 24
Finished Jul 15 05:30:41 PM PDT 24
Peak memory 211384 kb
Host smart-202520e7-cecc-479f-aa2d-dcd900ac5377
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103225069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2103225069
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1938975693
Short name T634
Test name
Test status
Simulation time 77688627 ps
CPU time 1.08 seconds
Started Jul 15 05:30:50 PM PDT 24
Finished Jul 15 05:30:52 PM PDT 24
Peak memory 208452 kb
Host smart-d55390fc-9764-48ab-a85c-3ad74940c695
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938975693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1938975693
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3988912801
Short name T801
Test name
Test status
Simulation time 288658911 ps
CPU time 12.98 seconds
Started Jul 15 05:30:41 PM PDT 24
Finished Jul 15 05:30:55 PM PDT 24
Peak memory 217648 kb
Host smart-0d77a666-8021-4d08-b2f7-03be100e3dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988912801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3988912801
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3169560867
Short name T787
Test name
Test status
Simulation time 1172009918 ps
CPU time 27.8 seconds
Started Jul 15 05:30:50 PM PDT 24
Finished Jul 15 05:31:19 PM PDT 24
Peak memory 217128 kb
Host smart-2a44d730-7776-452d-a2c0-f1c11275deda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169560867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3169560867
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3611515903
Short name T320
Test name
Test status
Simulation time 58426657 ps
CPU time 2.63 seconds
Started Jul 15 05:30:38 PM PDT 24
Finished Jul 15 05:30:42 PM PDT 24
Peak memory 217572 kb
Host smart-28d845ed-1d15-4816-91ba-ada0404211db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611515903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3611515903
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.4104069346
Short name T258
Test name
Test status
Simulation time 6349204879 ps
CPU time 19.24 seconds
Started Jul 15 05:30:52 PM PDT 24
Finished Jul 15 05:31:12 PM PDT 24
Peak memory 225524 kb
Host smart-935ca55a-e066-476f-8dc2-5d5d47835d60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104069346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.4104069346
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1967661994
Short name T60
Test name
Test status
Simulation time 1328236538 ps
CPU time 14.06 seconds
Started Jul 15 05:31:03 PM PDT 24
Finished Jul 15 05:31:18 PM PDT 24
Peak memory 225372 kb
Host smart-780ad69c-7f1f-47e6-b17c-f93e8001fb44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967661994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1967661994
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1914579063
Short name T344
Test name
Test status
Simulation time 3908611049 ps
CPU time 10.13 seconds
Started Jul 15 05:30:49 PM PDT 24
Finished Jul 15 05:31:00 PM PDT 24
Peak memory 217692 kb
Host smart-014294d5-f0f5-4d39-8ed1-b95bd6a76b55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914579063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1914579063
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.777257263
Short name T721
Test name
Test status
Simulation time 628967100 ps
CPU time 8.49 seconds
Started Jul 15 05:30:40 PM PDT 24
Finished Jul 15 05:30:50 PM PDT 24
Peak memory 224240 kb
Host smart-2d73f083-e541-4dd0-b0a6-2a7ef843e494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777257263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.777257263
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1442070639
Short name T87
Test name
Test status
Simulation time 27274504 ps
CPU time 1.23 seconds
Started Jul 15 05:30:40 PM PDT 24
Finished Jul 15 05:30:42 PM PDT 24
Peak memory 217084 kb
Host smart-e4a6d98e-eb2b-4b80-a7de-b4b29f787b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442070639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1442070639
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.4005690567
Short name T553
Test name
Test status
Simulation time 744776469 ps
CPU time 33.36 seconds
Started Jul 15 05:30:38 PM PDT 24
Finished Jul 15 05:31:12 PM PDT 24
Peak memory 250464 kb
Host smart-fb1ebfd8-e427-46d6-bc90-f547b6c4d649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005690567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.4005690567
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3975929055
Short name T716
Test name
Test status
Simulation time 153133973 ps
CPU time 7.15 seconds
Started Jul 15 05:30:39 PM PDT 24
Finished Jul 15 05:30:47 PM PDT 24
Peak memory 246280 kb
Host smart-1989c222-babb-4c61-9b45-48f55d7b937b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975929055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3975929055
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2102289741
Short name T473
Test name
Test status
Simulation time 3519778947 ps
CPU time 20.9 seconds
Started Jul 15 05:30:51 PM PDT 24
Finished Jul 15 05:31:12 PM PDT 24
Peak memory 250268 kb
Host smart-4c8af82a-6715-4112-827f-5778d92b8651
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102289741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2102289741
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.4043226047
Short name T689
Test name
Test status
Simulation time 32770741307 ps
CPU time 644.77 seconds
Started Jul 15 05:30:48 PM PDT 24
Finished Jul 15 05:41:34 PM PDT 24
Peak memory 267060 kb
Host smart-8059608e-41cb-4fbc-9db3-cb228a24f7f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4043226047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.4043226047
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1315442133
Short name T293
Test name
Test status
Simulation time 37904994 ps
CPU time 0.85 seconds
Started Jul 15 05:30:40 PM PDT 24
Finished Jul 15 05:30:42 PM PDT 24
Peak memory 211300 kb
Host smart-b7039e92-e784-4caf-bba5-4e67f2cea047
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315442133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1315442133
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3211892142
Short name T725
Test name
Test status
Simulation time 25747646 ps
CPU time 0.92 seconds
Started Jul 15 05:30:49 PM PDT 24
Finished Jul 15 05:30:50 PM PDT 24
Peak memory 208424 kb
Host smart-18fe529e-3bb4-447c-9bb3-41a9d676ad30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211892142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3211892142
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1718755482
Short name T502
Test name
Test status
Simulation time 252659530 ps
CPU time 8.22 seconds
Started Jul 15 05:30:49 PM PDT 24
Finished Jul 15 05:30:58 PM PDT 24
Peak memory 225376 kb
Host smart-96752a0c-5138-4b11-9d21-c6d3b0a9bed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718755482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1718755482
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.493239691
Short name T675
Test name
Test status
Simulation time 1785729274 ps
CPU time 7.69 seconds
Started Jul 15 05:30:50 PM PDT 24
Finished Jul 15 05:30:59 PM PDT 24
Peak memory 217088 kb
Host smart-43ec59f2-7d1f-41d4-8268-8aa7b4fd1005
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493239691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.493239691
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2565178087
Short name T421
Test name
Test status
Simulation time 42461102 ps
CPU time 2.25 seconds
Started Jul 15 05:30:49 PM PDT 24
Finished Jul 15 05:30:53 PM PDT 24
Peak memory 217632 kb
Host smart-afbca92f-f3b5-49f1-9660-373caf060f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565178087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2565178087
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1712488866
Short name T63
Test name
Test status
Simulation time 1664286062 ps
CPU time 15.03 seconds
Started Jul 15 05:30:51 PM PDT 24
Finished Jul 15 05:31:07 PM PDT 24
Peak memory 225452 kb
Host smart-2052ce16-7c05-431d-9eb7-58d306ccee22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712488866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1712488866
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.268133744
Short name T749
Test name
Test status
Simulation time 248129037 ps
CPU time 12.24 seconds
Started Jul 15 05:30:48 PM PDT 24
Finished Jul 15 05:31:01 PM PDT 24
Peak memory 225428 kb
Host smart-8f99954b-5328-4464-9cf7-bcfbdfe08a73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268133744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.268133744
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2828396333
Short name T509
Test name
Test status
Simulation time 2958078121 ps
CPU time 6.43 seconds
Started Jul 15 05:30:52 PM PDT 24
Finished Jul 15 05:30:59 PM PDT 24
Peak memory 225524 kb
Host smart-345fc281-0861-41a9-922d-062e96ce8b63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828396333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2828396333
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1113953041
Short name T401
Test name
Test status
Simulation time 373249103 ps
CPU time 8.81 seconds
Started Jul 15 05:30:48 PM PDT 24
Finished Jul 15 05:30:57 PM PDT 24
Peak memory 225484 kb
Host smart-78bbef06-9ba3-479f-8a6b-99138e79665a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113953041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1113953041
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2482872810
Short name T780
Test name
Test status
Simulation time 150036788 ps
CPU time 2.99 seconds
Started Jul 15 05:30:50 PM PDT 24
Finished Jul 15 05:30:54 PM PDT 24
Peak memory 213836 kb
Host smart-831ebd80-0c91-4610-b248-b7ca8ec909a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482872810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2482872810
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.4219813032
Short name T537
Test name
Test status
Simulation time 672260827 ps
CPU time 32.99 seconds
Started Jul 15 05:30:47 PM PDT 24
Finished Jul 15 05:31:21 PM PDT 24
Peak memory 250440 kb
Host smart-d5b9feeb-7bd8-4d7d-be6e-556c0c052e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219813032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.4219813032
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3032173137
Short name T240
Test name
Test status
Simulation time 46004591 ps
CPU time 6.4 seconds
Started Jul 15 05:30:49 PM PDT 24
Finished Jul 15 05:30:56 PM PDT 24
Peak memory 249768 kb
Host smart-6b5e084c-1b24-4d3a-851c-2e1bd42f34e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032173137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3032173137
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.651696032
Short name T662
Test name
Test status
Simulation time 4072215040 ps
CPU time 143.18 seconds
Started Jul 15 05:30:52 PM PDT 24
Finished Jul 15 05:33:15 PM PDT 24
Peak memory 275568 kb
Host smart-77c93536-89fe-47e3-b696-f837fcaa5c8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651696032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.651696032
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2352887992
Short name T86
Test name
Test status
Simulation time 14082481 ps
CPU time 1.02 seconds
Started Jul 15 05:30:48 PM PDT 24
Finished Jul 15 05:30:50 PM PDT 24
Peak memory 211176 kb
Host smart-27a21049-52f5-4fc8-9573-0c7426a37b01
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352887992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2352887992
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3995750196
Short name T299
Test name
Test status
Simulation time 20765388 ps
CPU time 1.2 seconds
Started Jul 15 05:30:51 PM PDT 24
Finished Jul 15 05:30:53 PM PDT 24
Peak memory 208576 kb
Host smart-283a0162-a7bb-4e97-94cd-789c2e98b850
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995750196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3995750196
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3846744277
Short name T636
Test name
Test status
Simulation time 561640522 ps
CPU time 14 seconds
Started Jul 15 05:30:50 PM PDT 24
Finished Jul 15 05:31:05 PM PDT 24
Peak memory 217720 kb
Host smart-83857560-787b-448f-8c82-32bb4474dc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846744277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3846744277
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.861999511
Short name T693
Test name
Test status
Simulation time 1179058999 ps
CPU time 25.15 seconds
Started Jul 15 05:30:50 PM PDT 24
Finished Jul 15 05:31:16 PM PDT 24
Peak memory 217128 kb
Host smart-09fe2ea7-9758-4176-ac3d-aae36d9d7f14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861999511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.861999511
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.556299140
Short name T589
Test name
Test status
Simulation time 79258168 ps
CPU time 3.99 seconds
Started Jul 15 05:30:49 PM PDT 24
Finished Jul 15 05:30:54 PM PDT 24
Peak memory 222048 kb
Host smart-48de3963-346b-4d1f-8bcc-e59663798bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556299140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.556299140
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.731458056
Short name T461
Test name
Test status
Simulation time 232663067 ps
CPU time 8.78 seconds
Started Jul 15 05:30:49 PM PDT 24
Finished Jul 15 05:30:59 PM PDT 24
Peak memory 225444 kb
Host smart-4e45baaa-19b3-4f2f-b55c-f45458c46146
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731458056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.731458056
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2820779529
Short name T793
Test name
Test status
Simulation time 929255700 ps
CPU time 16.9 seconds
Started Jul 15 05:30:50 PM PDT 24
Finished Jul 15 05:31:07 PM PDT 24
Peak memory 225420 kb
Host smart-3dc79b5d-dace-4be8-9db9-a20900748305
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820779529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2820779529
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.472340105
Short name T827
Test name
Test status
Simulation time 2739607363 ps
CPU time 14.77 seconds
Started Jul 15 05:30:51 PM PDT 24
Finished Jul 15 05:31:06 PM PDT 24
Peak memory 225436 kb
Host smart-4e11e23d-bd65-45c9-bfef-0b254ce0f81a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472340105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.472340105
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2217245337
Short name T804
Test name
Test status
Simulation time 722846160 ps
CPU time 14.56 seconds
Started Jul 15 05:30:49 PM PDT 24
Finished Jul 15 05:31:05 PM PDT 24
Peak memory 225516 kb
Host smart-89de6648-af85-4897-b21c-b85f6c5b7c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217245337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2217245337
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2197550223
Short name T1
Test name
Test status
Simulation time 43781466 ps
CPU time 2.22 seconds
Started Jul 15 05:30:51 PM PDT 24
Finished Jul 15 05:30:54 PM PDT 24
Peak memory 217132 kb
Host smart-f34616cd-e205-4a08-add3-c5d997028514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197550223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2197550223
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1673796373
Short name T99
Test name
Test status
Simulation time 796357181 ps
CPU time 27.41 seconds
Started Jul 15 05:30:50 PM PDT 24
Finished Jul 15 05:31:19 PM PDT 24
Peak memory 250420 kb
Host smart-81843576-bd16-4219-8d92-bc763e7cfe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673796373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1673796373
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.1395346614
Short name T507
Test name
Test status
Simulation time 289483325 ps
CPU time 7 seconds
Started Jul 15 05:30:48 PM PDT 24
Finished Jul 15 05:30:56 PM PDT 24
Peak memory 250460 kb
Host smart-4b417f37-f61e-4d64-b40b-094a04cd32fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395346614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.1395346614
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.809183651
Short name T792
Test name
Test status
Simulation time 3624488287 ps
CPU time 141.25 seconds
Started Jul 15 05:30:53 PM PDT 24
Finished Jul 15 05:33:15 PM PDT 24
Peak memory 283292 kb
Host smart-40a1d34b-6536-42f9-90ee-cbb1ee31a05d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809183651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.809183651
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.4272089480
Short name T146
Test name
Test status
Simulation time 151524522493 ps
CPU time 604.52 seconds
Started Jul 15 05:30:50 PM PDT 24
Finished Jul 15 05:40:56 PM PDT 24
Peak memory 316128 kb
Host smart-67b8aec5-10c6-4db3-9339-bdff31ff01eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4272089480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.4272089480
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.4080580743
Short name T688
Test name
Test status
Simulation time 14643188 ps
CPU time 0.86 seconds
Started Jul 15 05:30:52 PM PDT 24
Finished Jul 15 05:30:53 PM PDT 24
Peak memory 208508 kb
Host smart-1805fe82-238d-4ce1-a8c2-026ebebc3fd9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080580743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.4080580743
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2928687656
Short name T727
Test name
Test status
Simulation time 19955211 ps
CPU time 0.99 seconds
Started Jul 15 05:30:59 PM PDT 24
Finished Jul 15 05:31:01 PM PDT 24
Peak memory 208396 kb
Host smart-9935a929-275b-490a-ac22-f15dfe66ec83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928687656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2928687656
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.568301349
Short name T746
Test name
Test status
Simulation time 267283229 ps
CPU time 11.23 seconds
Started Jul 15 05:30:52 PM PDT 24
Finished Jul 15 05:31:04 PM PDT 24
Peak memory 217712 kb
Host smart-a48c267c-2523-490a-8033-fa40252bcb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568301349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.568301349
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.66937610
Short name T667
Test name
Test status
Simulation time 412667090 ps
CPU time 1.61 seconds
Started Jul 15 05:30:59 PM PDT 24
Finished Jul 15 05:31:02 PM PDT 24
Peak memory 217124 kb
Host smart-d1e05206-d5e6-4079-86d7-b0389f2759ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66937610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.66937610
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.4125780997
Short name T223
Test name
Test status
Simulation time 432237133 ps
CPU time 2.35 seconds
Started Jul 15 05:30:52 PM PDT 24
Finished Jul 15 05:30:55 PM PDT 24
Peak memory 217720 kb
Host smart-ce5540a4-19ab-49fe-8149-ab223fe888bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125780997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.4125780997
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2037033876
Short name T776
Test name
Test status
Simulation time 434036145 ps
CPU time 13.49 seconds
Started Jul 15 05:30:59 PM PDT 24
Finished Jul 15 05:31:13 PM PDT 24
Peak memory 218296 kb
Host smart-b883810e-4d5d-410c-add9-9b6d2b15f7b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037033876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2037033876
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.452006869
Short name T651
Test name
Test status
Simulation time 648146346 ps
CPU time 11.74 seconds
Started Jul 15 05:30:56 PM PDT 24
Finished Jul 15 05:31:08 PM PDT 24
Peak memory 225360 kb
Host smart-429b27a9-b32f-4d59-b3de-6f6f16460ddd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452006869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di
gest.452006869
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3649899957
Short name T368
Test name
Test status
Simulation time 2066270967 ps
CPU time 11.87 seconds
Started Jul 15 05:30:59 PM PDT 24
Finished Jul 15 05:31:12 PM PDT 24
Peak memory 225444 kb
Host smart-1b72b84e-0b0b-4afd-8045-ad9a1591e2c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649899957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3649899957
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1243106865
Short name T674
Test name
Test status
Simulation time 2987568000 ps
CPU time 13.12 seconds
Started Jul 15 05:30:48 PM PDT 24
Finished Jul 15 05:31:02 PM PDT 24
Peak memory 225544 kb
Host smart-6b86cafa-a804-4416-96ff-9ed70ca7d89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243106865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1243106865
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.344034016
Short name T748
Test name
Test status
Simulation time 188771904 ps
CPU time 12.98 seconds
Started Jul 15 05:30:50 PM PDT 24
Finished Jul 15 05:31:04 PM PDT 24
Peak memory 217176 kb
Host smart-527d1c7d-cf07-4524-a8df-31449a663536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344034016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.344034016
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1235225206
Short name T755
Test name
Test status
Simulation time 248556392 ps
CPU time 28.71 seconds
Started Jul 15 05:30:50 PM PDT 24
Finished Jul 15 05:31:20 PM PDT 24
Peak memory 250472 kb
Host smart-b02b5e0a-cee2-4ad1-a2dd-c7f6d7b40b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235225206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1235225206
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1088399742
Short name T596
Test name
Test status
Simulation time 50307221 ps
CPU time 6.73 seconds
Started Jul 15 05:30:48 PM PDT 24
Finished Jul 15 05:30:55 PM PDT 24
Peak memory 250412 kb
Host smart-e8e4eba0-1b35-4c5e-9854-67a764250431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088399742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1088399742
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2155118508
Short name T278
Test name
Test status
Simulation time 2502656176 ps
CPU time 94.08 seconds
Started Jul 15 05:30:58 PM PDT 24
Finished Jul 15 05:32:33 PM PDT 24
Peak memory 266868 kb
Host smart-9f1a65f3-23e0-433f-8174-0d5fa027ca5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155118508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2155118508
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.2669024259
Short name T807
Test name
Test status
Simulation time 7621379482 ps
CPU time 191.71 seconds
Started Jul 15 05:30:57 PM PDT 24
Finished Jul 15 05:34:09 PM PDT 24
Peak memory 274596 kb
Host smart-b1764350-300f-4d4d-95bd-4bbed8cf9e6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2669024259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.2669024259
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2707701426
Short name T245
Test name
Test status
Simulation time 47001649 ps
CPU time 0.93 seconds
Started Jul 15 05:30:49 PM PDT 24
Finished Jul 15 05:30:51 PM PDT 24
Peak memory 211240 kb
Host smart-b55f3db2-fb95-4a3b-8aaa-c726e8798ac7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707701426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2707701426
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3330361310
Short name T571
Test name
Test status
Simulation time 33481784 ps
CPU time 0.99 seconds
Started Jul 15 05:31:00 PM PDT 24
Finished Jul 15 05:31:02 PM PDT 24
Peak memory 208400 kb
Host smart-8812abe7-e41e-4257-a833-3aaba690be03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330361310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3330361310
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.880458197
Short name T717
Test name
Test status
Simulation time 438047121 ps
CPU time 13.35 seconds
Started Jul 15 05:31:00 PM PDT 24
Finished Jul 15 05:31:15 PM PDT 24
Peak memory 217748 kb
Host smart-70f9b43f-d367-4d99-a071-08cb775c8d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880458197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.880458197
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3928296096
Short name T580
Test name
Test status
Simulation time 3873568145 ps
CPU time 15.86 seconds
Started Jul 15 05:31:00 PM PDT 24
Finished Jul 15 05:31:17 PM PDT 24
Peak memory 217164 kb
Host smart-339bcfbc-2bbf-4505-a2dc-499d9bfe35bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928296096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3928296096
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.3567700204
Short name T359
Test name
Test status
Simulation time 33762686 ps
CPU time 1.92 seconds
Started Jul 15 05:30:59 PM PDT 24
Finished Jul 15 05:31:01 PM PDT 24
Peak memory 217684 kb
Host smart-7bf6328f-5270-489e-9fe2-bb30af642c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567700204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3567700204
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.4144541882
Short name T527
Test name
Test status
Simulation time 854996988 ps
CPU time 13.65 seconds
Started Jul 15 05:30:59 PM PDT 24
Finished Jul 15 05:31:14 PM PDT 24
Peak memory 217732 kb
Host smart-546297f2-747d-48e3-9df4-5219ec5de8da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144541882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.4144541882
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.809362150
Short name T548
Test name
Test status
Simulation time 1652400611 ps
CPU time 15.53 seconds
Started Jul 15 05:31:00 PM PDT 24
Finished Jul 15 05:31:17 PM PDT 24
Peak memory 225412 kb
Host smart-d0d62d4b-0afb-4aa6-bb38-95ce2621f0b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809362150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.809362150
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3554717400
Short name T281
Test name
Test status
Simulation time 908014364 ps
CPU time 8.57 seconds
Started Jul 15 05:30:58 PM PDT 24
Finished Jul 15 05:31:08 PM PDT 24
Peak memory 217660 kb
Host smart-4c119f3e-61fe-4b9d-8d9e-ff6dc8da6330
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554717400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3554717400
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.17442627
Short name T458
Test name
Test status
Simulation time 1101953498 ps
CPU time 8.58 seconds
Started Jul 15 05:31:00 PM PDT 24
Finished Jul 15 05:31:10 PM PDT 24
Peak memory 225520 kb
Host smart-007fe589-4d5b-4c88-8c12-aeb992c17a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17442627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.17442627
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1132221397
Short name T76
Test name
Test status
Simulation time 15932255 ps
CPU time 1.08 seconds
Started Jul 15 05:30:57 PM PDT 24
Finished Jul 15 05:30:59 PM PDT 24
Peak memory 217120 kb
Host smart-58aaa8dd-b35a-4409-908d-feb0a2e839ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132221397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1132221397
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1851458330
Short name T218
Test name
Test status
Simulation time 1002322747 ps
CPU time 22.33 seconds
Started Jul 15 05:30:58 PM PDT 24
Finished Jul 15 05:31:21 PM PDT 24
Peak memory 250408 kb
Host smart-893239b8-8ee1-4dbe-8f68-813d737d24e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851458330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1851458330
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2649181524
Short name T692
Test name
Test status
Simulation time 910103647 ps
CPU time 4.49 seconds
Started Jul 15 05:30:58 PM PDT 24
Finished Jul 15 05:31:03 PM PDT 24
Peak memory 225884 kb
Host smart-8170b4b2-095d-49d7-bf91-1b7085aca571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649181524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2649181524
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.4223640662
Short name T607
Test name
Test status
Simulation time 5761523900 ps
CPU time 241.84 seconds
Started Jul 15 05:30:57 PM PDT 24
Finished Jul 15 05:35:00 PM PDT 24
Peak memory 421516 kb
Host smart-ffe3baf8-2d42-4178-b929-a58b6c62c2f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223640662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.4223640662
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.237438512
Short name T282
Test name
Test status
Simulation time 31853070 ps
CPU time 0.78 seconds
Started Jul 15 05:30:57 PM PDT 24
Finished Jul 15 05:30:58 PM PDT 24
Peak memory 208352 kb
Host smart-7aeaf0dd-b792-49db-8256-16823b53736d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237438512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.237438512
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1057568705
Short name T95
Test name
Test status
Simulation time 135647080 ps
CPU time 1.13 seconds
Started Jul 15 05:31:08 PM PDT 24
Finished Jul 15 05:31:10 PM PDT 24
Peak memory 208400 kb
Host smart-80c38b12-b220-4ff8-b358-7ac1250ac7a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057568705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1057568705
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.606637385
Short name T284
Test name
Test status
Simulation time 1599387711 ps
CPU time 16.99 seconds
Started Jul 15 05:31:00 PM PDT 24
Finished Jul 15 05:31:18 PM PDT 24
Peak memory 217740 kb
Host smart-f1b80291-03c1-4375-b3fe-8c87bd50165c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606637385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.606637385
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3706453512
Short name T630
Test name
Test status
Simulation time 654503146 ps
CPU time 4.49 seconds
Started Jul 15 05:30:59 PM PDT 24
Finished Jul 15 05:31:05 PM PDT 24
Peak memory 216596 kb
Host smart-2b4c00e2-92f5-4967-aec8-831737967ee6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706453512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.3706453512
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.4100358513
Short name T747
Test name
Test status
Simulation time 312606754 ps
CPU time 2.77 seconds
Started Jul 15 05:31:00 PM PDT 24
Finished Jul 15 05:31:04 PM PDT 24
Peak memory 221728 kb
Host smart-ee20a850-9f1a-49b7-8961-dae12690b86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100358513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.4100358513
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3761943985
Short name T222
Test name
Test status
Simulation time 264522375 ps
CPU time 12.15 seconds
Started Jul 15 05:31:00 PM PDT 24
Finished Jul 15 05:31:14 PM PDT 24
Peak memory 225308 kb
Host smart-48df110f-1b73-41b4-85fa-39c5cb290f14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761943985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3761943985
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3091286859
Short name T770
Test name
Test status
Simulation time 788062544 ps
CPU time 9.43 seconds
Started Jul 15 05:31:00 PM PDT 24
Finished Jul 15 05:31:11 PM PDT 24
Peak memory 217584 kb
Host smart-f23d4973-d97e-4f33-a0fc-faec3e3048c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091286859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3091286859
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.199966589
Short name T325
Test name
Test status
Simulation time 806361335 ps
CPU time 11.26 seconds
Started Jul 15 05:31:00 PM PDT 24
Finished Jul 15 05:31:13 PM PDT 24
Peak memory 225492 kb
Host smart-7a6c83c5-73dd-4b87-91f5-ad45bf562045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199966589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.199966589
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3119468741
Short name T374
Test name
Test status
Simulation time 730722438 ps
CPU time 4.25 seconds
Started Jul 15 05:30:59 PM PDT 24
Finished Jul 15 05:31:04 PM PDT 24
Peak memory 217060 kb
Host smart-ef7b55a3-70e7-4f5c-9741-a838e72af949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119468741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3119468741
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3463362176
Short name T612
Test name
Test status
Simulation time 865272868 ps
CPU time 24.1 seconds
Started Jul 15 05:30:59 PM PDT 24
Finished Jul 15 05:31:25 PM PDT 24
Peak memory 250436 kb
Host smart-4c623040-68b2-40cc-ad02-25d69beb2172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463362176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3463362176
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1612885149
Short name T353
Test name
Test status
Simulation time 43651302 ps
CPU time 5.97 seconds
Started Jul 15 05:31:00 PM PDT 24
Finished Jul 15 05:31:08 PM PDT 24
Peak memory 242188 kb
Host smart-6d166d8f-4b79-47b7-a22e-fc59cd352004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612885149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1612885149
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1909754906
Short name T586
Test name
Test status
Simulation time 10838157142 ps
CPU time 84.1 seconds
Started Jul 15 05:30:59 PM PDT 24
Finished Jul 15 05:32:25 PM PDT 24
Peak memory 277416 kb
Host smart-b7428e5b-bd1d-427e-ab22-379e110e5052
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909754906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1909754906
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.19128817
Short name T105
Test name
Test status
Simulation time 81750776446 ps
CPU time 647.42 seconds
Started Jul 15 05:31:00 PM PDT 24
Finished Jul 15 05:41:49 PM PDT 24
Peak memory 283380 kb
Host smart-b2ce4bdf-28e1-493e-9035-970402ccfcea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=19128817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.19128817
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.299849944
Short name T412
Test name
Test status
Simulation time 29995508 ps
CPU time 0.91 seconds
Started Jul 15 05:31:00 PM PDT 24
Finished Jul 15 05:31:02 PM PDT 24
Peak memory 208352 kb
Host smart-4f180794-f31b-4242-aefc-6e9466e635d1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299849944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct
rl_volatile_unlock_smoke.299849944
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2243408262
Short name T516
Test name
Test status
Simulation time 39034141 ps
CPU time 0.92 seconds
Started Jul 15 05:31:07 PM PDT 24
Finished Jul 15 05:31:09 PM PDT 24
Peak memory 208560 kb
Host smart-7c440adf-7717-4d61-b3c2-15e3be4f55f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243408262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2243408262
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3009274149
Short name T798
Test name
Test status
Simulation time 265788350 ps
CPU time 11.42 seconds
Started Jul 15 05:31:05 PM PDT 24
Finished Jul 15 05:31:18 PM PDT 24
Peak memory 217632 kb
Host smart-1a8c0d04-19cb-4dfd-b0bd-cb3425064dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009274149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3009274149
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1160591742
Short name T846
Test name
Test status
Simulation time 40105646 ps
CPU time 1.72 seconds
Started Jul 15 05:31:06 PM PDT 24
Finished Jul 15 05:31:09 PM PDT 24
Peak memory 216532 kb
Host smart-cdffd324-69db-4aa2-877e-23b60e19698d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160591742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1160591742
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.917408121
Short name T573
Test name
Test status
Simulation time 62694588 ps
CPU time 3.55 seconds
Started Jul 15 05:31:07 PM PDT 24
Finished Jul 15 05:31:12 PM PDT 24
Peak memory 221924 kb
Host smart-5885b315-112b-4a95-8235-88c0a7677d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917408121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.917408121
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.246825762
Short name T758
Test name
Test status
Simulation time 1076409697 ps
CPU time 11.17 seconds
Started Jul 15 05:31:08 PM PDT 24
Finished Jul 15 05:31:20 PM PDT 24
Peak memory 225440 kb
Host smart-5076fd1e-b172-4236-9747-624d3afeb504
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246825762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.246825762
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1879538168
Short name T455
Test name
Test status
Simulation time 822940689 ps
CPU time 11.04 seconds
Started Jul 15 05:31:06 PM PDT 24
Finished Jul 15 05:31:19 PM PDT 24
Peak memory 225164 kb
Host smart-1461e83e-fc55-44b7-b079-48531b0a0d8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879538168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1879538168
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2539775627
Short name T552
Test name
Test status
Simulation time 4671586216 ps
CPU time 26.99 seconds
Started Jul 15 05:31:06 PM PDT 24
Finished Jul 15 05:31:34 PM PDT 24
Peak memory 218312 kb
Host smart-fffdaa4c-1265-46b0-80cb-d04c9babe7db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539775627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2539775627
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3492433589
Short name T814
Test name
Test status
Simulation time 344837073 ps
CPU time 7.86 seconds
Started Jul 15 05:31:08 PM PDT 24
Finished Jul 15 05:31:17 PM PDT 24
Peak memory 224308 kb
Host smart-a5f4f7d1-de05-4fb9-b021-3a19ba505292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492433589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3492433589
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2268879692
Short name T786
Test name
Test status
Simulation time 149440981 ps
CPU time 4.9 seconds
Started Jul 15 05:31:06 PM PDT 24
Finished Jul 15 05:31:12 PM PDT 24
Peak memory 217068 kb
Host smart-866a7f2f-a76f-4dd2-967f-60b390e8d687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268879692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2268879692
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.2390284487
Short name T779
Test name
Test status
Simulation time 394583908 ps
CPU time 25.01 seconds
Started Jul 15 05:31:05 PM PDT 24
Finished Jul 15 05:31:31 PM PDT 24
Peak memory 250392 kb
Host smart-15fed262-3485-47a0-89c3-20d4c3258592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390284487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2390284487
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.2161597381
Short name T588
Test name
Test status
Simulation time 466534441 ps
CPU time 7.35 seconds
Started Jul 15 05:31:07 PM PDT 24
Finished Jul 15 05:31:15 PM PDT 24
Peak memory 249828 kb
Host smart-375c4d13-74b0-40e5-a449-48260f6d1aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161597381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2161597381
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.1763488801
Short name T376
Test name
Test status
Simulation time 7282040586 ps
CPU time 241.99 seconds
Started Jul 15 05:31:11 PM PDT 24
Finished Jul 15 05:35:13 PM PDT 24
Peak memory 283984 kb
Host smart-9a36f741-b66b-496e-b061-b69f11e028a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763488801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.1763488801
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.2687539195
Short name T762
Test name
Test status
Simulation time 54611184985 ps
CPU time 469.3 seconds
Started Jul 15 05:31:11 PM PDT 24
Finished Jul 15 05:39:02 PM PDT 24
Peak memory 316172 kb
Host smart-88eed065-e649-4ed3-908f-cdbbbe6609bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2687539195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.2687539195
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.502902988
Short name T815
Test name
Test status
Simulation time 40897416 ps
CPU time 0.8 seconds
Started Jul 15 05:31:06 PM PDT 24
Finished Jul 15 05:31:08 PM PDT 24
Peak memory 208288 kb
Host smart-58d5b832-524c-4c5f-adef-af745c44f67d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502902988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.502902988
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.515543045
Short name T340
Test name
Test status
Simulation time 113572888 ps
CPU time 1.04 seconds
Started Jul 15 05:27:18 PM PDT 24
Finished Jul 15 05:27:20 PM PDT 24
Peak memory 208508 kb
Host smart-3e84b15e-9ca7-4a21-99e7-be4b239aacc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515543045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.515543045
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1719615233
Short name T788
Test name
Test status
Simulation time 17247294 ps
CPU time 0.91 seconds
Started Jul 15 05:27:13 PM PDT 24
Finished Jul 15 05:27:14 PM PDT 24
Peak memory 208592 kb
Host smart-2cc9e17e-3fb0-4967-a87a-5547fcf9f49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719615233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1719615233
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2856369742
Short name T603
Test name
Test status
Simulation time 1774170093 ps
CPU time 15.82 seconds
Started Jul 15 05:27:11 PM PDT 24
Finished Jul 15 05:27:27 PM PDT 24
Peak memory 217704 kb
Host smart-81ed0fe6-dd31-4ea5-a457-71aa1ce67ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856369742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2856369742
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3862973136
Short name T24
Test name
Test status
Simulation time 242865251 ps
CPU time 3.43 seconds
Started Jul 15 05:27:20 PM PDT 24
Finished Jul 15 05:27:24 PM PDT 24
Peak memory 216908 kb
Host smart-767043f5-6d53-4d49-9900-1b8d5548d8da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862973136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3862973136
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2218903095
Short name T42
Test name
Test status
Simulation time 3655155899 ps
CPU time 88.55 seconds
Started Jul 15 05:27:20 PM PDT 24
Finished Jul 15 05:28:49 PM PDT 24
Peak memory 219284 kb
Host smart-e084efda-bbd9-49b4-80be-bc50dc56ec72
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218903095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2218903095
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3448970198
Short name T709
Test name
Test status
Simulation time 4050939721 ps
CPU time 8.81 seconds
Started Jul 15 05:27:16 PM PDT 24
Finished Jul 15 05:27:25 PM PDT 24
Peak memory 217168 kb
Host smart-1f90a806-c82c-4b43-a248-0dda94154ab7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448970198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
448970198
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2287517617
Short name T351
Test name
Test status
Simulation time 927091809 ps
CPU time 6.19 seconds
Started Jul 15 05:27:20 PM PDT 24
Finished Jul 15 05:27:27 PM PDT 24
Peak memory 217556 kb
Host smart-9c11b5ed-9070-4f61-a7e1-02861d3d6095
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287517617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2287517617
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.703563176
Short name T433
Test name
Test status
Simulation time 3822430408 ps
CPU time 21.66 seconds
Started Jul 15 05:27:18 PM PDT 24
Finished Jul 15 05:27:40 PM PDT 24
Peak memory 217144 kb
Host smart-ee929096-83fc-4780-86a4-1adc8d84c14e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703563176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.703563176
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.2697691867
Short name T81
Test name
Test status
Simulation time 230751650 ps
CPU time 2.62 seconds
Started Jul 15 05:27:13 PM PDT 24
Finished Jul 15 05:27:17 PM PDT 24
Peak memory 217016 kb
Host smart-81816fc8-44a3-42df-93e9-4d0def0ec0ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697691867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
2697691867
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.99627404
Short name T372
Test name
Test status
Simulation time 1048863377 ps
CPU time 41.12 seconds
Started Jul 15 05:27:11 PM PDT 24
Finished Jul 15 05:27:53 PM PDT 24
Peak memory 250328 kb
Host smart-20e40e49-7309-4665-a3f4-7efa2f9b0d22
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99627404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
state_failure.99627404
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.740104102
Short name T816
Test name
Test status
Simulation time 516537406 ps
CPU time 14.47 seconds
Started Jul 15 05:27:20 PM PDT 24
Finished Jul 15 05:27:35 PM PDT 24
Peak memory 250360 kb
Host smart-71d169e4-9df4-4f54-88f8-9ce63df83baf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740104102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.740104102
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.2019376087
Short name T860
Test name
Test status
Simulation time 53177147 ps
CPU time 1.49 seconds
Started Jul 15 05:27:11 PM PDT 24
Finished Jul 15 05:27:13 PM PDT 24
Peak memory 217620 kb
Host smart-a7ff9cdd-b113-4fbb-ad41-4bd12f262e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019376087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2019376087
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3090555603
Short name T66
Test name
Test status
Simulation time 635133937 ps
CPU time 17.67 seconds
Started Jul 15 05:27:11 PM PDT 24
Finished Jul 15 05:27:29 PM PDT 24
Peak memory 214204 kb
Host smart-e86af1d3-19ce-4cc4-bf8e-4f7a171c9052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090555603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3090555603
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2130530014
Short name T856
Test name
Test status
Simulation time 386170594 ps
CPU time 9.5 seconds
Started Jul 15 05:27:18 PM PDT 24
Finished Jul 15 05:27:28 PM PDT 24
Peak memory 225380 kb
Host smart-8121a476-b4b1-4880-ae07-356bd3179328
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130530014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2130530014
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3175269220
Short name T396
Test name
Test status
Simulation time 685348881 ps
CPU time 6.45 seconds
Started Jul 15 05:27:18 PM PDT 24
Finished Jul 15 05:27:25 PM PDT 24
Peak memory 217596 kb
Host smart-f5d7d434-a641-4876-808c-f24619276d73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175269220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
175269220
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.86469318
Short name T56
Test name
Test status
Simulation time 830806068 ps
CPU time 7.82 seconds
Started Jul 15 05:27:13 PM PDT 24
Finished Jul 15 05:27:21 PM PDT 24
Peak memory 224380 kb
Host smart-d67a5664-1bb0-478a-9304-7d58685d5df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86469318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.86469318
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3329952135
Short name T791
Test name
Test status
Simulation time 41039176 ps
CPU time 1.17 seconds
Started Jul 15 05:27:45 PM PDT 24
Finished Jul 15 05:27:47 PM PDT 24
Peak memory 217260 kb
Host smart-55bb214b-c082-4861-b6ae-01a161769c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329952135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3329952135
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3806652714
Short name T710
Test name
Test status
Simulation time 529528675 ps
CPU time 26.05 seconds
Started Jul 15 05:27:11 PM PDT 24
Finished Jul 15 05:27:38 PM PDT 24
Peak memory 250384 kb
Host smart-ae3e9b98-b00e-473b-8f64-ab750bc56f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806652714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3806652714
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.379849175
Short name T652
Test name
Test status
Simulation time 1470317436 ps
CPU time 8.06 seconds
Started Jul 15 05:27:11 PM PDT 24
Finished Jul 15 05:27:20 PM PDT 24
Peak memory 247064 kb
Host smart-0331fb33-1dac-4f06-ada7-9efaa3d258d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379849175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.379849175
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.4151069047
Short name T494
Test name
Test status
Simulation time 3153046956 ps
CPU time 23.87 seconds
Started Jul 15 05:27:18 PM PDT 24
Finished Jul 15 05:27:42 PM PDT 24
Peak memory 250512 kb
Host smart-946f644c-c2ec-4f30-9527-5afa0fe21bc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151069047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.4151069047
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.4230654288
Short name T40
Test name
Test status
Simulation time 20318959 ps
CPU time 1.07 seconds
Started Jul 15 05:27:14 PM PDT 24
Finished Jul 15 05:27:15 PM PDT 24
Peak memory 211276 kb
Host smart-8802207f-0457-425c-a4bb-58d1285b7913
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230654288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.4230654288
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1560510630
Short name T429
Test name
Test status
Simulation time 77473561 ps
CPU time 0.99 seconds
Started Jul 15 05:27:28 PM PDT 24
Finished Jul 15 05:27:30 PM PDT 24
Peak memory 208520 kb
Host smart-2f74e172-f756-4dd9-a71b-8f78538728bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560510630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1560510630
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.92880830
Short name T837
Test name
Test status
Simulation time 34124089 ps
CPU time 0.93 seconds
Started Jul 15 05:27:26 PM PDT 24
Finished Jul 15 05:27:28 PM PDT 24
Peak memory 208640 kb
Host smart-e9d1da60-4c7a-44e4-854f-017e29c2891f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92880830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.92880830
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3681594603
Short name T745
Test name
Test status
Simulation time 360590379 ps
CPU time 13.27 seconds
Started Jul 15 05:27:26 PM PDT 24
Finished Jul 15 05:27:40 PM PDT 24
Peak memory 217628 kb
Host smart-a7bd2200-10fb-47d6-a3e9-d109b83700fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681594603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3681594603
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2330778946
Short name T530
Test name
Test status
Simulation time 1923811168 ps
CPU time 62.64 seconds
Started Jul 15 05:27:26 PM PDT 24
Finished Jul 15 05:28:29 PM PDT 24
Peak memory 217640 kb
Host smart-63319b80-0757-4561-bc24-f7f980f4a6c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330778946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2330778946
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1961376042
Short name T341
Test name
Test status
Simulation time 251224178 ps
CPU time 3.45 seconds
Started Jul 15 05:27:28 PM PDT 24
Finished Jul 15 05:27:32 PM PDT 24
Peak memory 217104 kb
Host smart-d8b1a59c-431e-470d-8734-e64048863a8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961376042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
961376042
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.894696586
Short name T228
Test name
Test status
Simulation time 802193141 ps
CPU time 4.82 seconds
Started Jul 15 05:27:24 PM PDT 24
Finished Jul 15 05:27:30 PM PDT 24
Peak memory 221232 kb
Host smart-d2ec02d3-bf7a-4a18-9a9b-c2b2f5d2f8c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894696586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.894696586
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3269238151
Short name T468
Test name
Test status
Simulation time 3094532925 ps
CPU time 21.02 seconds
Started Jul 15 05:27:27 PM PDT 24
Finished Jul 15 05:27:48 PM PDT 24
Peak memory 217172 kb
Host smart-41aad556-b654-44cc-b3d4-ea947e6b2431
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269238151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3269238151
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3870385837
Short name T546
Test name
Test status
Simulation time 1620024431 ps
CPU time 5.18 seconds
Started Jul 15 05:27:28 PM PDT 24
Finished Jul 15 05:27:34 PM PDT 24
Peak memory 217056 kb
Host smart-221cdfc0-b437-4edf-bd39-273f89bbc74c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870385837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3870385837
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1227386602
Short name T493
Test name
Test status
Simulation time 14354451963 ps
CPU time 112.91 seconds
Started Jul 15 05:27:25 PM PDT 24
Finished Jul 15 05:29:19 PM PDT 24
Peak memory 283132 kb
Host smart-1d72a042-3961-4f70-b2dc-8bfab7285722
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227386602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1227386602
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1379255488
Short name T367
Test name
Test status
Simulation time 10535079224 ps
CPU time 16.74 seconds
Started Jul 15 05:27:26 PM PDT 24
Finished Jul 15 05:27:43 PM PDT 24
Peak memory 217752 kb
Host smart-f7ec4661-de3e-4ae7-b787-7dc72addfa57
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379255488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1379255488
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.917657822
Short name T697
Test name
Test status
Simulation time 474357275 ps
CPU time 2.91 seconds
Started Jul 15 05:27:28 PM PDT 24
Finished Jul 15 05:27:31 PM PDT 24
Peak memory 217652 kb
Host smart-7d54c057-c5cd-4250-90e5-71915659403b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917657822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.917657822
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3590127027
Short name T174
Test name
Test status
Simulation time 794214460 ps
CPU time 10.52 seconds
Started Jul 15 05:27:27 PM PDT 24
Finished Jul 15 05:27:38 PM PDT 24
Peak memory 213832 kb
Host smart-1016cc73-1cad-487b-8b9c-b2f83c23e0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590127027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3590127027
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.521344011
Short name T59
Test name
Test status
Simulation time 318582209 ps
CPU time 12.47 seconds
Started Jul 15 05:27:28 PM PDT 24
Finished Jul 15 05:27:41 PM PDT 24
Peak memory 218344 kb
Host smart-f444c1ac-2c35-47d8-978d-bb0ad403a439
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521344011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.521344011
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1439460673
Short name T449
Test name
Test status
Simulation time 1344293232 ps
CPU time 12.78 seconds
Started Jul 15 05:27:25 PM PDT 24
Finished Jul 15 05:27:38 PM PDT 24
Peak memory 225444 kb
Host smart-23393efd-4e0a-4440-842f-1cc0394157d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439460673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1439460673
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2503969067
Short name T476
Test name
Test status
Simulation time 257129268 ps
CPU time 9.48 seconds
Started Jul 15 05:27:27 PM PDT 24
Finished Jul 15 05:27:37 PM PDT 24
Peak memory 225420 kb
Host smart-b454f8e7-60da-4531-ad79-17d43acbf232
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503969067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
503969067
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3456711975
Short name T403
Test name
Test status
Simulation time 1406164000 ps
CPU time 7.97 seconds
Started Jul 15 05:27:28 PM PDT 24
Finished Jul 15 05:27:36 PM PDT 24
Peak memory 217700 kb
Host smart-d770fef1-30a8-4569-89de-219b2dc137e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456711975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3456711975
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.4237677248
Short name T737
Test name
Test status
Simulation time 219943522 ps
CPU time 1.36 seconds
Started Jul 15 05:27:18 PM PDT 24
Finished Jul 15 05:27:20 PM PDT 24
Peak memory 213204 kb
Host smart-ae37efc8-d97f-4feb-8ad9-3cb582037785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237677248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.4237677248
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.549151592
Short name T267
Test name
Test status
Simulation time 1200964393 ps
CPU time 35.67 seconds
Started Jul 15 05:27:20 PM PDT 24
Finished Jul 15 05:27:56 PM PDT 24
Peak memory 250304 kb
Host smart-38bd010d-f258-4fc5-b0b2-60184a1c3b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549151592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.549151592
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.1026545494
Short name T170
Test name
Test status
Simulation time 109859855 ps
CPU time 7.96 seconds
Started Jul 15 05:27:28 PM PDT 24
Finished Jul 15 05:27:36 PM PDT 24
Peak memory 250436 kb
Host smart-1fd3eead-c00c-483c-9f25-f94c1013b2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026545494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1026545494
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.3444292688
Short name T808
Test name
Test status
Simulation time 3142048769 ps
CPU time 48.94 seconds
Started Jul 15 05:27:26 PM PDT 24
Finished Jul 15 05:28:15 PM PDT 24
Peak memory 250576 kb
Host smart-9e22d54e-da5d-42a4-a0ce-fb020b8f6800
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444292688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.3444292688
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1034351450
Short name T584
Test name
Test status
Simulation time 14020473 ps
CPU time 0.83 seconds
Started Jul 15 05:27:18 PM PDT 24
Finished Jul 15 05:27:19 PM PDT 24
Peak memory 208308 kb
Host smart-0e02e0a3-df6d-4e01-aba8-3c74a1444687
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034351450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1034351450
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1472944471
Short name T732
Test name
Test status
Simulation time 14854329 ps
CPU time 1.09 seconds
Started Jul 15 05:27:34 PM PDT 24
Finished Jul 15 05:27:35 PM PDT 24
Peak memory 208400 kb
Host smart-1ba3d730-d422-4449-ab52-1844132a00e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472944471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1472944471
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1811409230
Short name T210
Test name
Test status
Simulation time 36733214 ps
CPU time 0.85 seconds
Started Jul 15 05:27:34 PM PDT 24
Finished Jul 15 05:27:35 PM PDT 24
Peak memory 208236 kb
Host smart-4cb02c55-3332-4a89-9fb6-0b45dc11a4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811409230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1811409230
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.4045859044
Short name T668
Test name
Test status
Simulation time 1142939858 ps
CPU time 12.48 seconds
Started Jul 15 05:27:33 PM PDT 24
Finished Jul 15 05:27:47 PM PDT 24
Peak memory 225432 kb
Host smart-0c29530b-c5c4-449d-8668-846f135f6540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045859044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.4045859044
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1256184449
Short name T432
Test name
Test status
Simulation time 134809823 ps
CPU time 2.48 seconds
Started Jul 15 05:27:33 PM PDT 24
Finished Jul 15 05:27:36 PM PDT 24
Peak memory 216556 kb
Host smart-21e9589a-66f1-453d-b2b3-24596392185a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256184449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1256184449
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.640859547
Short name T753
Test name
Test status
Simulation time 3815514205 ps
CPU time 24.16 seconds
Started Jul 15 05:27:36 PM PDT 24
Finished Jul 15 05:28:01 PM PDT 24
Peak memory 217664 kb
Host smart-7f6b199e-64c4-4144-9791-69dfe8e9f984
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640859547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_err
ors.640859547
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1960522545
Short name T253
Test name
Test status
Simulation time 742571649 ps
CPU time 4.81 seconds
Started Jul 15 05:27:35 PM PDT 24
Finished Jul 15 05:27:41 PM PDT 24
Peak memory 217004 kb
Host smart-dbf6fa22-1268-470a-83d2-b55b5e73e124
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960522545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
960522545
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2737907373
Short name T248
Test name
Test status
Simulation time 807697922 ps
CPU time 4.36 seconds
Started Jul 15 05:27:33 PM PDT 24
Finished Jul 15 05:27:39 PM PDT 24
Peak memory 217616 kb
Host smart-dcbf04d8-c82e-45fa-96a7-85c2b732a68a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737907373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2737907373
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.4006812873
Short name T611
Test name
Test status
Simulation time 3717065088 ps
CPU time 13.71 seconds
Started Jul 15 05:27:33 PM PDT 24
Finished Jul 15 05:27:48 PM PDT 24
Peak memory 217068 kb
Host smart-4000e867-046c-4dd1-956b-46cb61736498
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006812873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.4006812873
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3228912751
Short name T496
Test name
Test status
Simulation time 263442111 ps
CPU time 4.7 seconds
Started Jul 15 05:27:34 PM PDT 24
Finished Jul 15 05:27:40 PM PDT 24
Peak memory 217044 kb
Host smart-b9c5801a-56d7-48d6-849c-d86215d7b201
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228912751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3228912751
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.412921024
Short name T828
Test name
Test status
Simulation time 1619282112 ps
CPU time 57.26 seconds
Started Jul 15 05:27:33 PM PDT 24
Finished Jul 15 05:28:31 PM PDT 24
Peak memory 283068 kb
Host smart-1a4a7c94-e4a6-4825-99e1-105d8e26d1ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412921024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.412921024
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.226669369
Short name T231
Test name
Test status
Simulation time 5809658901 ps
CPU time 21.56 seconds
Started Jul 15 05:27:34 PM PDT 24
Finished Jul 15 05:27:56 PM PDT 24
Peak memory 250440 kb
Host smart-7da8837b-95b4-48e9-a9c1-8a4645fac25f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226669369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.226669369
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.192644427
Short name T754
Test name
Test status
Simulation time 44234061 ps
CPU time 2.27 seconds
Started Jul 15 05:27:34 PM PDT 24
Finished Jul 15 05:27:37 PM PDT 24
Peak memory 221652 kb
Host smart-d13a17ee-ce49-458e-bc70-100f0e5aa6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192644427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.192644427
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.467890154
Short name T197
Test name
Test status
Simulation time 201858272 ps
CPU time 12.65 seconds
Started Jul 15 05:27:35 PM PDT 24
Finished Jul 15 05:27:48 PM PDT 24
Peak memory 213936 kb
Host smart-d651f42e-f875-4493-82e4-e204a83dbad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467890154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.467890154
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3505363374
Short name T682
Test name
Test status
Simulation time 464883767 ps
CPU time 18.69 seconds
Started Jul 15 05:27:33 PM PDT 24
Finished Jul 15 05:27:52 PM PDT 24
Peak memory 225372 kb
Host smart-66e4881f-90fb-4bd5-af76-ec1bce7664cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505363374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3505363374
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2469923245
Short name T572
Test name
Test status
Simulation time 1014461059 ps
CPU time 12.92 seconds
Started Jul 15 05:27:35 PM PDT 24
Finished Jul 15 05:27:49 PM PDT 24
Peak memory 225404 kb
Host smart-faf0e125-3d92-4e60-a09a-281f08421fe5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469923245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2469923245
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2972788697
Short name T505
Test name
Test status
Simulation time 879368091 ps
CPU time 7.13 seconds
Started Jul 15 05:27:33 PM PDT 24
Finished Jul 15 05:27:40 PM PDT 24
Peak memory 217588 kb
Host smart-d273358a-080f-4ca5-92be-03f9807f31f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972788697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
972788697
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.172813886
Short name T731
Test name
Test status
Simulation time 1025020074 ps
CPU time 6.11 seconds
Started Jul 15 05:27:33 PM PDT 24
Finished Jul 15 05:27:40 PM PDT 24
Peak memory 223964 kb
Host smart-07527776-3a37-46bb-853a-7a6096f95080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172813886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.172813886
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.3913285483
Short name T317
Test name
Test status
Simulation time 142498742 ps
CPU time 2.46 seconds
Started Jul 15 05:27:35 PM PDT 24
Finished Jul 15 05:27:38 PM PDT 24
Peak memory 213876 kb
Host smart-fc8b6ff1-706f-4e38-98f7-0aab87c5f4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913285483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3913285483
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3986854357
Short name T244
Test name
Test status
Simulation time 832635631 ps
CPU time 25.45 seconds
Started Jul 15 05:27:35 PM PDT 24
Finished Jul 15 05:28:01 PM PDT 24
Peak memory 250384 kb
Host smart-c3d7d778-e00d-4d24-8404-418aead3c80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986854357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3986854357
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1110658953
Short name T841
Test name
Test status
Simulation time 263301136 ps
CPU time 8.3 seconds
Started Jul 15 05:27:35 PM PDT 24
Finished Jul 15 05:27:44 PM PDT 24
Peak memory 250404 kb
Host smart-44c69bcb-2172-4706-9ee5-da029dd39d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110658953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1110658953
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3324441548
Short name T647
Test name
Test status
Simulation time 11038473781 ps
CPU time 343.09 seconds
Started Jul 15 05:27:36 PM PDT 24
Finished Jul 15 05:33:20 PM PDT 24
Peak memory 283244 kb
Host smart-14fd0102-e89a-4c19-a11d-3a3c6665db7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324441548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3324441548
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.934837751
Short name T741
Test name
Test status
Simulation time 18263145 ps
CPU time 0.84 seconds
Started Jul 15 05:27:40 PM PDT 24
Finished Jul 15 05:27:41 PM PDT 24
Peak memory 208356 kb
Host smart-fa8c0cb3-6292-42f7-894f-cb5c0de7075e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934837751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.934837751
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.54748337
Short name T490
Test name
Test status
Simulation time 30548314 ps
CPU time 0.89 seconds
Started Jul 15 05:27:48 PM PDT 24
Finished Jul 15 05:27:49 PM PDT 24
Peak memory 208272 kb
Host smart-cc6193a3-6bea-4ce2-816b-e3f3a1f2dff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54748337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.54748337
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.2812166467
Short name T206
Test name
Test status
Simulation time 389152395 ps
CPU time 12.46 seconds
Started Jul 15 05:27:34 PM PDT 24
Finished Jul 15 05:27:47 PM PDT 24
Peak memory 217708 kb
Host smart-46ea7538-4012-4f53-9218-3083d9fde12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812166467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2812166467
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.780177652
Short name T562
Test name
Test status
Simulation time 68507091 ps
CPU time 1.52 seconds
Started Jul 15 05:27:42 PM PDT 24
Finished Jul 15 05:27:44 PM PDT 24
Peak memory 216632 kb
Host smart-068e82b2-1ecf-44e0-b8b0-41c8cf7524da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780177652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.780177652
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.80945902
Short name T239
Test name
Test status
Simulation time 4467800829 ps
CPU time 24.2 seconds
Started Jul 15 05:27:43 PM PDT 24
Finished Jul 15 05:28:08 PM PDT 24
Peak memory 218272 kb
Host smart-941ebbf9-ff11-450b-b7ff-04434b305582
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80945902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_erro
rs.80945902
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1624836545
Short name T678
Test name
Test status
Simulation time 427285253 ps
CPU time 5.82 seconds
Started Jul 15 05:27:40 PM PDT 24
Finished Jul 15 05:27:47 PM PDT 24
Peak memory 217240 kb
Host smart-2367140e-243a-43f3-966b-48b96c99df20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624836545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
624836545
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1120520162
Short name T393
Test name
Test status
Simulation time 1998593903 ps
CPU time 15.09 seconds
Started Jul 15 05:27:40 PM PDT 24
Finished Jul 15 05:27:56 PM PDT 24
Peak memory 218284 kb
Host smart-f0aff662-0930-4adb-921b-b1aa388c9386
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120520162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.1120520162
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2915100637
Short name T22
Test name
Test status
Simulation time 1878135726 ps
CPU time 27.85 seconds
Started Jul 15 05:27:42 PM PDT 24
Finished Jul 15 05:28:10 PM PDT 24
Peak memory 217108 kb
Host smart-337c09c7-2c5e-42c6-9ccc-70a199f41eaf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915100637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2915100637
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2865436736
Short name T654
Test name
Test status
Simulation time 264004749 ps
CPU time 3.43 seconds
Started Jul 15 05:27:43 PM PDT 24
Finished Jul 15 05:27:47 PM PDT 24
Peak memory 217372 kb
Host smart-60711083-c74a-415a-922a-9f06bc6b90ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865436736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2865436736
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2200405740
Short name T352
Test name
Test status
Simulation time 848509911 ps
CPU time 30.8 seconds
Started Jul 15 05:27:43 PM PDT 24
Finished Jul 15 05:28:15 PM PDT 24
Peak memory 250416 kb
Host smart-e5db769d-6311-4f2f-a234-989efbf8635b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200405740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2200405740
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1215245530
Short name T151
Test name
Test status
Simulation time 2659604341 ps
CPU time 15.21 seconds
Started Jul 15 05:27:44 PM PDT 24
Finished Jul 15 05:28:00 PM PDT 24
Peak memory 250108 kb
Host smart-9382e6c4-2fd1-461f-bbd3-cc72ece0c11f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215245530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1215245530
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1604289095
Short name T558
Test name
Test status
Simulation time 80984051 ps
CPU time 3.73 seconds
Started Jul 15 05:27:32 PM PDT 24
Finished Jul 15 05:27:37 PM PDT 24
Peak memory 221748 kb
Host smart-241b8e70-82df-454b-a3a1-55de9664371f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604289095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1604289095
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3525755413
Short name T576
Test name
Test status
Simulation time 476491290 ps
CPU time 16 seconds
Started Jul 15 05:27:41 PM PDT 24
Finished Jul 15 05:27:58 PM PDT 24
Peak memory 214020 kb
Host smart-f2718c24-64e0-45fd-9fb9-8bd4e600718f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525755413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3525755413
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3419503480
Short name T616
Test name
Test status
Simulation time 1173870862 ps
CPU time 12.66 seconds
Started Jul 15 05:27:42 PM PDT 24
Finished Jul 15 05:27:55 PM PDT 24
Peak memory 218392 kb
Host smart-fc9bda26-1436-412d-960b-1dad371fd4aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419503480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3419503480
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1940321780
Short name T536
Test name
Test status
Simulation time 1146402248 ps
CPU time 13.4 seconds
Started Jul 15 05:27:40 PM PDT 24
Finished Jul 15 05:27:54 PM PDT 24
Peak memory 225416 kb
Host smart-9ac00e24-f031-4e27-ad53-16ce8b8f0151
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940321780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1940321780
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3399272786
Short name T650
Test name
Test status
Simulation time 279434484 ps
CPU time 9.79 seconds
Started Jul 15 05:27:42 PM PDT 24
Finished Jul 15 05:27:52 PM PDT 24
Peak memory 217632 kb
Host smart-1610735f-84c3-4451-babf-8ffbe7524502
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399272786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
399272786
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.672645678
Short name T497
Test name
Test status
Simulation time 228911722 ps
CPU time 6.98 seconds
Started Jul 15 05:27:52 PM PDT 24
Finished Jul 15 05:27:59 PM PDT 24
Peak memory 225448 kb
Host smart-97ddd1b1-f18d-4e9e-978b-d5fdcade996d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672645678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.672645678
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.102396300
Short name T628
Test name
Test status
Simulation time 81792089 ps
CPU time 1.47 seconds
Started Jul 15 05:27:36 PM PDT 24
Finished Jul 15 05:27:38 PM PDT 24
Peak memory 213204 kb
Host smart-7dc6f91b-65ab-428a-92b2-9e11493aaf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102396300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.102396300
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.678069693
Short name T601
Test name
Test status
Simulation time 202643524 ps
CPU time 21.13 seconds
Started Jul 15 05:27:34 PM PDT 24
Finished Jul 15 05:27:56 PM PDT 24
Peak memory 250384 kb
Host smart-18e4a2e2-5c1a-42f3-a13a-f7d6cce79ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678069693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.678069693
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.1645720816
Short name T397
Test name
Test status
Simulation time 85358469 ps
CPU time 7.68 seconds
Started Jul 15 05:27:36 PM PDT 24
Finished Jul 15 05:27:44 PM PDT 24
Peak memory 250428 kb
Host smart-9a2a0d24-fae2-4ee3-afd5-9f32566d623f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645720816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1645720816
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3637030243
Short name T538
Test name
Test status
Simulation time 25025803504 ps
CPU time 204.95 seconds
Started Jul 15 05:27:43 PM PDT 24
Finished Jul 15 05:31:09 PM PDT 24
Peak memory 267176 kb
Host smart-36f742b0-6280-4128-a7b8-29b11ef730ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637030243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3637030243
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.4234184383
Short name T140
Test name
Test status
Simulation time 16210732529 ps
CPU time 378.79 seconds
Started Jul 15 05:27:40 PM PDT 24
Finished Jul 15 05:34:00 PM PDT 24
Peak memory 332536 kb
Host smart-c4ca698b-f704-4850-a20f-4b8e925329d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4234184383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.4234184383
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1254636719
Short name T613
Test name
Test status
Simulation time 39131692 ps
CPU time 0.94 seconds
Started Jul 15 05:27:34 PM PDT 24
Finished Jul 15 05:27:35 PM PDT 24
Peak memory 211304 kb
Host smart-d0b87bee-0b3b-4108-9fda-69248a384224
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254636719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1254636719
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2923524298
Short name T819
Test name
Test status
Simulation time 44251166 ps
CPU time 0.84 seconds
Started Jul 15 05:27:59 PM PDT 24
Finished Jul 15 05:28:01 PM PDT 24
Peak memory 208280 kb
Host smart-d2591d21-3781-4a2c-9ab9-c14e13e8e07b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923524298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2923524298
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1344666483
Short name T825
Test name
Test status
Simulation time 43076801 ps
CPU time 0.82 seconds
Started Jul 15 05:27:49 PM PDT 24
Finished Jul 15 05:27:51 PM PDT 24
Peak memory 208456 kb
Host smart-e40fcbf9-24df-4d8c-b97b-6d78c652e463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344666483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1344666483
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1128847511
Short name T37
Test name
Test status
Simulation time 676262823 ps
CPU time 10.23 seconds
Started Jul 15 05:27:48 PM PDT 24
Finished Jul 15 05:27:59 PM PDT 24
Peak memory 225496 kb
Host smart-971d31c2-03e9-4ac6-9981-a793db3c6286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128847511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1128847511
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.2372010203
Short name T157
Test name
Test status
Simulation time 704621488 ps
CPU time 1.7 seconds
Started Jul 15 05:27:47 PM PDT 24
Finished Jul 15 05:27:50 PM PDT 24
Peak memory 217140 kb
Host smart-d9aaee63-f36a-44da-ab8b-9444a6b3033d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372010203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2372010203
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3909216940
Short name T416
Test name
Test status
Simulation time 2224602352 ps
CPU time 59.63 seconds
Started Jul 15 05:27:49 PM PDT 24
Finished Jul 15 05:28:50 PM PDT 24
Peak memory 217748 kb
Host smart-e5cc3882-e47f-4cfb-99b0-4d316e114d84
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909216940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3909216940
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3909003190
Short name T337
Test name
Test status
Simulation time 4855988988 ps
CPU time 19.97 seconds
Started Jul 15 05:27:49 PM PDT 24
Finished Jul 15 05:28:10 PM PDT 24
Peak memory 217232 kb
Host smart-e030fad8-d602-4378-b4f9-10be1b7dc8f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909003190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
909003190
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1884841939
Short name T212
Test name
Test status
Simulation time 5309740051 ps
CPU time 5.42 seconds
Started Jul 15 05:27:48 PM PDT 24
Finished Jul 15 05:27:54 PM PDT 24
Peak memory 217644 kb
Host smart-692f225d-e744-4e76-8eff-7de40c7a83f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884841939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1884841939
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3502914664
Short name T744
Test name
Test status
Simulation time 1484526704 ps
CPU time 34.61 seconds
Started Jul 15 05:27:48 PM PDT 24
Finished Jul 15 05:28:23 PM PDT 24
Peak memory 217024 kb
Host smart-50c82ad6-ef66-4d56-ba06-a3794b1ade7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502914664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3502914664
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1695069402
Short name T229
Test name
Test status
Simulation time 461788063 ps
CPU time 5.24 seconds
Started Jul 15 05:27:47 PM PDT 24
Finished Jul 15 05:27:53 PM PDT 24
Peak memory 217076 kb
Host smart-52e8e97c-ec76-473a-bd6a-39935b44381e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695069402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1695069402
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3201916604
Short name T848
Test name
Test status
Simulation time 3436838090 ps
CPU time 73.84 seconds
Started Jul 15 05:27:48 PM PDT 24
Finished Jul 15 05:29:03 PM PDT 24
Peak memory 283140 kb
Host smart-a7790f32-c9b6-4739-84e9-7eaf9a64f0c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201916604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3201916604
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2330975326
Short name T640
Test name
Test status
Simulation time 581998011 ps
CPU time 9.24 seconds
Started Jul 15 05:27:49 PM PDT 24
Finished Jul 15 05:27:59 PM PDT 24
Peak memory 224540 kb
Host smart-bcb862c2-921e-4579-bea9-9fc4bd231548
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330975326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2330975326
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.4006800545
Short name T666
Test name
Test status
Simulation time 241042931 ps
CPU time 3.02 seconds
Started Jul 15 05:27:49 PM PDT 24
Finished Jul 15 05:27:53 PM PDT 24
Peak memory 217684 kb
Host smart-7d1ed0e4-151a-428d-b4c9-08f4abc52677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006800545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.4006800545
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.4290480193
Short name T447
Test name
Test status
Simulation time 1495059474 ps
CPU time 13.21 seconds
Started Jul 15 05:27:51 PM PDT 24
Finished Jul 15 05:28:05 PM PDT 24
Peak memory 217124 kb
Host smart-aaba89e0-8e8c-45ec-8576-4821cae5f2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290480193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.4290480193
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.250114866
Short name T62
Test name
Test status
Simulation time 764646010 ps
CPU time 8.58 seconds
Started Jul 15 05:27:49 PM PDT 24
Finished Jul 15 05:27:58 PM PDT 24
Peak memory 218388 kb
Host smart-62f8ae64-70e2-42a5-b438-f4fdb99c4972
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250114866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.250114866
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.358486987
Short name T369
Test name
Test status
Simulation time 211942532 ps
CPU time 7.63 seconds
Started Jul 15 05:28:00 PM PDT 24
Finished Jul 15 05:28:08 PM PDT 24
Peak memory 225396 kb
Host smart-5f114fb8-c665-4ace-83ba-93d4104cea29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358486987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.358486987
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1187141615
Short name T485
Test name
Test status
Simulation time 2403300309 ps
CPU time 11.6 seconds
Started Jul 15 05:27:58 PM PDT 24
Finished Jul 15 05:28:10 PM PDT 24
Peak memory 217728 kb
Host smart-d8e80955-61df-4bf5-a79b-24fa52ada9e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187141615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
187141615
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2693802778
Short name T50
Test name
Test status
Simulation time 1296234135 ps
CPU time 13.8 seconds
Started Jul 15 05:27:48 PM PDT 24
Finished Jul 15 05:28:03 PM PDT 24
Peak memory 225456 kb
Host smart-e3164064-5762-48e9-bb4f-c6cd01ee6b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693802778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2693802778
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1150387187
Short name T617
Test name
Test status
Simulation time 78876281 ps
CPU time 3.89 seconds
Started Jul 15 05:27:49 PM PDT 24
Finished Jul 15 05:27:53 PM PDT 24
Peak memory 217068 kb
Host smart-3387852f-193e-4169-a161-bb5b913a08aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150387187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1150387187
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3048456362
Short name T227
Test name
Test status
Simulation time 300260689 ps
CPU time 23.76 seconds
Started Jul 15 05:27:47 PM PDT 24
Finished Jul 15 05:28:12 PM PDT 24
Peak memory 250428 kb
Host smart-ecdf7091-288d-4ce5-a418-ca20afd458e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048456362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3048456362
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1061479723
Short name T457
Test name
Test status
Simulation time 960667489 ps
CPU time 8.42 seconds
Started Jul 15 05:27:49 PM PDT 24
Finished Jul 15 05:27:58 PM PDT 24
Peak memory 249968 kb
Host smart-04655f99-b893-4f59-83ef-b6eb2ea1b180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061479723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1061479723
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2989534344
Short name T296
Test name
Test status
Simulation time 38371181 ps
CPU time 0.9 seconds
Started Jul 15 05:27:48 PM PDT 24
Finished Jul 15 05:27:50 PM PDT 24
Peak memory 208536 kb
Host smart-f02a43d6-c50a-43a5-963e-faf00ac8742c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989534344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2989534344
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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