Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100084413

1

T1

325935

T2

701612

T3

29167

auto[1]

1272406

1

T1

792

T2

4847

T4

1584

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100103504

1

T1

326628

T2

701709

T3

29167

auto[1]

1253315

1

T1

99

T2

4750

T4

1881

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6596583	1			T1	6840		T2	30451		T3	103
auto[IdleSt]	22944199	1			T1	167578		T2	141681		T3	29064
auto[ClkMuxSt]	33860	1			T1	78		T2	221		T4	35
auto[CntIncrSt]	33560	1			T1	78		T2	221		T4	35
auto[CntProgSt]	1668758	1			T1	10652		T2	23717		T4	1100
auto[TransCheckSt]	26186	1			T1	61		T2	178		T8	1
auto[TokenHashSt]	40029733	1			T1	570		T2	353778		T8	66
auto[FlashRmaSt]	32017	1			T1	16		T2	175		T8	1
auto[TokenCheck0St]	11527	1			T1	16		T2	81		T8	1
auto[TokenCheck1St]	8458	1			T1	9		T2	66		T8	1
auto[TransProgSt]	370450	1			T1	1537		T2	7753		T8	66
auto[PostTransSt]	13274919	1			T1	132489		T2	101366		T4	2813
auto[ScrapSt]	135848	1			T2	779		T16	8		T34	12
auto[EscalateSt]	6044879	1			T1	6803		T2	24036		T4	4988
auto[InvalidSt]	10144170	1			T2	21948		T9	4841		T12	217

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1672	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10144170	1			T2	21948		T9	4841		T12	217
EscalateSt	6044879	1			T1	6803		T2	24036		T4	4988
ScrapSt	135848	1			T2	779		T16	8		T34	12
PostTransSt	13274919	1			T1	132489		T2	101366		T4	2813
TransProgSt	370450	1			T1	1537		T2	7753		T8	66
TokenCheck1St	8458	1			T1	9		T2	66		T8	1
TokenCheck0St	11527	1			T1	16		T2	81		T8	1
FlashRmaSt	32017	1			T1	16		T2	175		T8	1
TokenHashSt	40029733	1			T1	570		T2	353778		T8	66
TransCheckSt	26186	1			T1	61		T2	178		T8	1
CntProgSt	1668758	1			T1	10652		T2	23717		T4	1100
CntIncrSt	33560	1			T1	78		T2	221		T4	35
ClkMuxSt	33860	1			T1	78		T2	221		T4	35
IdleSt	22944199	1			T1	167578		T2	141681		T3	29064
ResetSt	6596583	1			T1	6840		T2	30451		T3	103
arcs[ResetSt=>IdleSt]	49572	1			T1	79		T2	312		T3	1
arcs[IdleSt=>ScrapSt]	265	1			T2	1		T16	1		T34	1
arcs[IdleSt=>ClkMuxSt]	33610	1			T1	78		T2	221		T4	35
arcs[ClkMuxSt=>CntIncrSt]	33560	1			T1	78		T2	221		T4	35
arcs[CntIncrSt=>PostTransSt]	1841	1			T1	8		T2	23		T32	6
arcs[CntIncrSt=>CntProgSt]	31655	1			T1	70		T2	198		T4	35
arcs[CntProgSt=>PostTransSt]	4395	1			T1	9		T2	20		T4	35
arcs[CntProgSt=>TransCheckSt]	26186	1			T1	61		T2	178		T8	1
arcs[TransCheckSt=>PostTransSt]	3698	1			T1	10		T2	21		T13	50
arcs[TransCheckSt=>TokenHashSt]	22355	1			T1	51		T2	157		T8	1
arcs[TokenHashSt=>PostTransSt]	10040	1			T1	35		T2	76		T10	71
arcs[TokenHashSt=>FlashRmaSt]	11621	1			T1	16		T2	81		T8	1
arcs[FlashRmaSt=>TokenCheck0St]	11527	1			T1	16		T2	81		T8	1
arcs[TokenCheck0St=>PostTransSt]	3031	1			T1	7		T2	15		T13	26
arcs[TokenCheck0St=>TokenCheck1St]	8458	1			T1	9		T2	66		T8	1
arcs[TokenCheck1St=>PostTransSt]	623	1			T2	2		T13	13		T17	5
arcs[TransProgSt=>PostTransSt]	6970	1			T1	9		T2	64		T8	1
arcs[IdleSt=>EscalateSt]	187	1			T48	7		T33	3		T51	3
arcs[ClkMuxSt=>EscalateSt]	50	1			T48	1		T49	1		T50	1
arcs[CntIncrSt=>EscalateSt]	64	1			T33	1		T51	1		T50	1
arcs[CntProgSt=>EscalateSt]	1074	1			T48	8		T49	7		T33	14
arcs[TransCheckSt=>EscalateSt]	133	1			T48	2		T49	6		T33	5
arcs[TokenHashSt=>EscalateSt]	693	1			T18	1		T48	13		T49	12
arcs[FlashRmaSt=>EscalateSt]	94	1			T48	2		T49	3		T33	3
arcs[TokenCheck0St=>EscalateSt]	38	1			T48	1		T33	1		T51	2
arcs[TokenCheck1St=>EscalateSt]	154	1			T48	5		T49	1		T33	2
arcs[TransProgSt=>EscalateSt]	711	1			T48	4		T49	10		T33	13
arcs[PostTransSt=>EscalateSt]	4661	1			T1	9		T2	20		T4	35
arcs[InvalidSt=>EscalateSt]	11842	1			T2	77		T9	67		T12	3

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6596394	1			T1	6840		T2	30451		T3	103
auto[0]	auto[IdleSt]	22944070	1			T1	167578		T2	141681		T3	29064
auto[0]	auto[ClkMuxSt]	33825	1			T1	78		T2	221		T4	35
auto[0]	auto[CntIncrSt]	33516	1			T1	78		T2	221		T4	35
auto[0]	auto[CntProgSt]	1668063	1			T1	10652		T2	23717		T4	1100
auto[0]	auto[TransCheckSt]	26099	1			T1	61		T2	178		T8	1
auto[0]	auto[TokenHashSt]	40029278	1			T1	570		T2	353778		T8	66
auto[0]	auto[FlashRmaSt]	31954	1			T1	16		T2	175		T8	1
auto[0]	auto[TokenCheck0St]	11508	1			T1	16		T2	81		T8	1
auto[0]	auto[TokenCheck1St]	8355	1			T1	9		T2	66		T8	1
auto[0]	auto[TransProgSt]	369981	1			T1	1537		T2	7753		T8	66
auto[0]	auto[PostTransSt]	13272564	1			T1	132481		T2	101357		T4	2797
auto[0]	auto[ScrapSt]	135806	1			T2	779		T16	8		T34	12
auto[0]	auto[EscalateSt]	4783177	1			T1	6019		T2	19238		T4	3420
auto[0]	auto[InvalidSt]	10138151	1			T2	21908		T9	4802		T12	215
auto[1]	auto[ResetSt]	189	1			T48	3		T49	4		T33	3
auto[1]	auto[IdleSt]	129	1			T48	5		T33	2		T51	2
auto[1]	auto[ClkMuxSt]	35	1			T48	1		T49	1		T50	1
auto[1]	auto[CntIncrSt]	44	1			T33	1		T51	1		T50	1
auto[1]	auto[CntProgSt]	695	1			T48	6		T49	5		T33	8
auto[1]	auto[TransCheckSt]	87	1			T48	1		T49	5		T33	2
auto[1]	auto[TokenHashSt]	455	1			T48	4		T49	8		T33	14
auto[1]	auto[FlashRmaSt]	63	1			T48	1		T49	3		T33	1
auto[1]	auto[TokenCheck0St]	19	1			T51	1		T52	1		T50	1
auto[1]	auto[TokenCheck1St]	103	1			T48	3		T49	1		T33	1
auto[1]	auto[TransProgSt]	469	1			T48	1		T49	6		T33	9
auto[1]	auto[PostTransSt]	2355	1			T1	8		T2	9		T4	16
auto[1]	auto[ScrapSt]	42	1			T51	1		T52	1		T50	1
auto[1]	auto[EscalateSt]	1261702	1			T1	784		T2	4798		T4	1568
auto[1]	auto[InvalidSt]	6019	1			T2	40		T9	39		T12	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6596414	1			T1	6840		T2	30451		T3	103
auto[0]	auto[IdleSt]	22944077	1			T1	167578		T2	141681		T3	29064
auto[0]	auto[ClkMuxSt]	33832	1			T1	78		T2	221		T4	35
auto[0]	auto[CntIncrSt]	33519	1			T1	78		T2	221		T4	35
auto[0]	auto[CntProgSt]	1668047	1			T1	10652		T2	23717		T4	1100
auto[0]	auto[TransCheckSt]	26096	1			T1	61		T2	178		T8	1
auto[0]	auto[TokenHashSt]	40029277	1			T1	570		T2	353778		T8	66
auto[0]	auto[FlashRmaSt]	31949	1			T1	16		T2	175		T8	1
auto[0]	auto[TokenCheck0St]	11499	1			T1	16		T2	81		T8	1
auto[0]	auto[TokenCheck1St]	8362	1			T1	9		T2	66		T8	1
auto[0]	auto[TransProgSt]	369967	1			T1	1537		T2	7753		T8	66
auto[0]	auto[PostTransSt]	13272531	1			T1	132488		T2	101355		T4	2794
auto[0]	auto[ScrapSt]	135810	1			T2	779		T16	8		T34	12
auto[0]	auto[EscalateSt]	4802105	1			T1	6705		T2	19334		T4	3126
auto[0]	auto[InvalidSt]	10138347	1			T2	21911		T9	4813		T12	216
auto[1]	auto[ResetSt]	169	1			T48	2		T49	3		T33	2
auto[1]	auto[IdleSt]	122	1			T48	5		T33	1		T51	3
auto[1]	auto[ClkMuxSt]	28	1			T48	1		T93	1		T192	2
auto[1]	auto[CntIncrSt]	41	1			T51	1		T93	1		T192	1
auto[1]	auto[CntProgSt]	711	1			T48	7		T49	6		T33	8
auto[1]	auto[TransCheckSt]	90	1			T48	1		T49	4		T33	4
auto[1]	auto[TokenHashSt]	456	1			T18	1		T48	9		T49	7
auto[1]	auto[FlashRmaSt]	68	1			T48	1		T49	1		T33	3
auto[1]	auto[TokenCheck0St]	28	1			T48	1		T33	1		T51	2
auto[1]	auto[TokenCheck1St]	96	1			T48	2		T33	2		T51	2
auto[1]	auto[TransProgSt]	483	1			T48	3		T49	8		T33	9
auto[1]	auto[PostTransSt]	2388	1			T1	1		T2	11		T4	19
auto[1]	auto[ScrapSt]	38	1			T51	1		T93	1		T192	1
auto[1]	auto[EscalateSt]	1242774	1			T1	98		T2	4702		T4	1862
auto[1]	auto[InvalidSt]	5823	1			T2	37		T9	28		T12	1