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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.96 97.99 96.13 93.40 97.67 98.55 98.51 96.47


Total test records in report: 982
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T817 /workspace/coverage/default/5.lc_ctrl_errors.1882766839 Jul 16 05:04:14 PM PDT 24 Jul 16 05:04:25 PM PDT 24 195154799 ps
T818 /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3513699768 Jul 16 05:06:08 PM PDT 24 Jul 16 05:06:11 PM PDT 24 15868011 ps
T819 /workspace/coverage/default/28.lc_ctrl_state_post_trans.2663253192 Jul 16 05:05:35 PM PDT 24 Jul 16 05:05:49 PM PDT 24 111516154 ps
T45 /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.1107510327 Jul 16 05:05:51 PM PDT 24 Jul 16 05:15:03 PM PDT 24 16498549734 ps
T820 /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.4139387630 Jul 16 05:03:46 PM PDT 24 Jul 16 05:03:52 PM PDT 24 1533975566 ps
T821 /workspace/coverage/default/25.lc_ctrl_security_escalation.974099708 Jul 16 05:05:29 PM PDT 24 Jul 16 05:05:43 PM PDT 24 666796678 ps
T822 /workspace/coverage/default/44.lc_ctrl_jtag_access.238310814 Jul 16 05:06:17 PM PDT 24 Jul 16 05:06:25 PM PDT 24 527771261 ps
T823 /workspace/coverage/default/34.lc_ctrl_smoke.1488074260 Jul 16 05:06:02 PM PDT 24 Jul 16 05:06:06 PM PDT 24 221370004 ps
T824 /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1991635162 Jul 16 05:04:25 PM PDT 24 Jul 16 05:04:28 PM PDT 24 80569809 ps
T825 /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.634931960 Jul 16 05:04:38 PM PDT 24 Jul 16 05:04:42 PM PDT 24 21037174 ps
T826 /workspace/coverage/default/4.lc_ctrl_errors.1276687927 Jul 16 05:03:50 PM PDT 24 Jul 16 05:04:06 PM PDT 24 574110486 ps
T827 /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1037150460 Jul 16 05:05:32 PM PDT 24 Jul 16 05:05:36 PM PDT 24 12864384 ps
T828 /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.152907867 Jul 16 05:04:09 PM PDT 24 Jul 16 05:04:37 PM PDT 24 788524825 ps
T829 /workspace/coverage/default/31.lc_ctrl_errors.1784295900 Jul 16 05:05:50 PM PDT 24 Jul 16 05:06:04 PM PDT 24 303519398 ps
T830 /workspace/coverage/default/24.lc_ctrl_prog_failure.3583896470 Jul 16 05:05:33 PM PDT 24 Jul 16 05:05:41 PM PDT 24 70931066 ps
T831 /workspace/coverage/default/42.lc_ctrl_sec_mubi.3433644105 Jul 16 05:06:17 PM PDT 24 Jul 16 05:06:31 PM PDT 24 278885505 ps
T832 /workspace/coverage/default/27.lc_ctrl_sec_token_mux.3131625486 Jul 16 05:05:35 PM PDT 24 Jul 16 05:05:58 PM PDT 24 3185222214 ps
T833 /workspace/coverage/default/1.lc_ctrl_stress_all.1902224969 Jul 16 05:03:36 PM PDT 24 Jul 16 05:06:57 PM PDT 24 21680707243 ps
T145 /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.411719817 Jul 16 05:05:03 PM PDT 24 Jul 16 05:11:55 PM PDT 24 12493893250 ps
T834 /workspace/coverage/default/14.lc_ctrl_state_post_trans.4122964292 Jul 16 05:04:52 PM PDT 24 Jul 16 05:04:56 PM PDT 24 255494634 ps
T835 /workspace/coverage/default/41.lc_ctrl_errors.3231852793 Jul 16 05:06:05 PM PDT 24 Jul 16 05:06:33 PM PDT 24 2914737684 ps
T836 /workspace/coverage/default/3.lc_ctrl_security_escalation.716947924 Jul 16 05:03:49 PM PDT 24 Jul 16 05:03:58 PM PDT 24 171954002 ps
T837 /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2552615653 Jul 16 05:06:16 PM PDT 24 Jul 16 05:06:27 PM PDT 24 758641893 ps
T838 /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2436466771 Jul 16 05:03:31 PM PDT 24 Jul 16 05:04:41 PM PDT 24 2995057836 ps
T839 /workspace/coverage/default/15.lc_ctrl_security_escalation.3808191102 Jul 16 05:04:49 PM PDT 24 Jul 16 05:05:02 PM PDT 24 627984432 ps
T840 /workspace/coverage/default/7.lc_ctrl_regwen_during_op.4290841116 Jul 16 05:04:09 PM PDT 24 Jul 16 05:04:20 PM PDT 24 257478131 ps
T841 /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2903596335 Jul 16 05:05:10 PM PDT 24 Jul 16 05:05:23 PM PDT 24 667260896 ps
T842 /workspace/coverage/default/35.lc_ctrl_sec_token_digest.44042118 Jul 16 05:05:59 PM PDT 24 Jul 16 05:06:13 PM PDT 24 1118410421 ps
T843 /workspace/coverage/default/10.lc_ctrl_state_post_trans.1007183153 Jul 16 05:04:35 PM PDT 24 Jul 16 05:04:43 PM PDT 24 249284994 ps
T844 /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2297735834 Jul 16 05:05:00 PM PDT 24 Jul 16 05:05:14 PM PDT 24 1435722589 ps
T845 /workspace/coverage/default/43.lc_ctrl_prog_failure.4268740556 Jul 16 05:06:21 PM PDT 24 Jul 16 05:06:25 PM PDT 24 94570162 ps
T846 /workspace/coverage/default/29.lc_ctrl_state_post_trans.3572770962 Jul 16 05:05:42 PM PDT 24 Jul 16 05:05:57 PM PDT 24 157913725 ps
T847 /workspace/coverage/default/8.lc_ctrl_jtag_errors.3478962592 Jul 16 05:04:23 PM PDT 24 Jul 16 05:06:00 PM PDT 24 17749240359 ps
T848 /workspace/coverage/default/15.lc_ctrl_stress_all.602943073 Jul 16 05:04:47 PM PDT 24 Jul 16 05:05:51 PM PDT 24 10383925006 ps
T849 /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.716659142 Jul 16 05:03:37 PM PDT 24 Jul 16 05:04:52 PM PDT 24 5816582514 ps
T850 /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3618567371 Jul 16 05:04:29 PM PDT 24 Jul 16 05:04:30 PM PDT 24 23493784 ps
T851 /workspace/coverage/default/49.lc_ctrl_alert_test.2159067421 Jul 16 05:06:42 PM PDT 24 Jul 16 05:06:44 PM PDT 24 26163217 ps
T852 /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3697131416 Jul 16 05:04:54 PM PDT 24 Jul 16 05:05:43 PM PDT 24 4328750373 ps
T853 /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1822362135 Jul 16 05:04:59 PM PDT 24 Jul 16 05:05:05 PM PDT 24 137608040 ps
T854 /workspace/coverage/default/0.lc_ctrl_security_escalation.2783200356 Jul 16 05:03:30 PM PDT 24 Jul 16 05:03:40 PM PDT 24 246408845 ps
T855 /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3547270576 Jul 16 05:05:57 PM PDT 24 Jul 16 05:06:19 PM PDT 24 1236378574 ps
T856 /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3552495944 Jul 16 05:06:19 PM PDT 24 Jul 16 05:06:37 PM PDT 24 751335834 ps
T857 /workspace/coverage/default/17.lc_ctrl_sec_mubi.910252654 Jul 16 05:05:04 PM PDT 24 Jul 16 05:05:20 PM PDT 24 1048040580 ps
T858 /workspace/coverage/default/31.lc_ctrl_security_escalation.2556872545 Jul 16 05:05:49 PM PDT 24 Jul 16 05:06:03 PM PDT 24 644765614 ps
T859 /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2341888615 Jul 16 05:04:10 PM PDT 24 Jul 16 05:04:34 PM PDT 24 843348638 ps
T860 /workspace/coverage/default/43.lc_ctrl_smoke.3903809012 Jul 16 05:06:25 PM PDT 24 Jul 16 05:06:28 PM PDT 24 85463735 ps
T861 /workspace/coverage/default/13.lc_ctrl_jtag_errors.331919245 Jul 16 05:04:49 PM PDT 24 Jul 16 05:06:01 PM PDT 24 4988850424 ps
T105 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3057283907 Jul 16 04:54:49 PM PDT 24 Jul 16 04:54:52 PM PDT 24 415565315 ps
T135 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.549374345 Jul 16 04:54:35 PM PDT 24 Jul 16 04:54:37 PM PDT 24 16807949 ps
T116 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2218071503 Jul 16 04:54:43 PM PDT 24 Jul 16 04:54:49 PM PDT 24 372420303 ps
T106 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3510691420 Jul 16 04:54:42 PM PDT 24 Jul 16 04:54:44 PM PDT 24 44720043 ps
T136 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1885523789 Jul 16 04:54:11 PM PDT 24 Jul 16 04:54:42 PM PDT 24 2745828183 ps
T134 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.31247177 Jul 16 04:54:26 PM PDT 24 Jul 16 04:54:33 PM PDT 24 561063315 ps
T138 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3250322331 Jul 16 04:54:28 PM PDT 24 Jul 16 04:54:30 PM PDT 24 84558095 ps
T139 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4072219936 Jul 16 04:54:14 PM PDT 24 Jul 16 04:54:18 PM PDT 24 135358361 ps
T862 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2630927091 Jul 16 04:54:17 PM PDT 24 Jul 16 04:54:20 PM PDT 24 63649885 ps
T107 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.255502049 Jul 16 04:54:32 PM PDT 24 Jul 16 04:54:34 PM PDT 24 54685709 ps
T137 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1886250807 Jul 16 04:54:19 PM PDT 24 Jul 16 04:54:20 PM PDT 24 54129018 ps
T863 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.178580512 Jul 16 04:54:41 PM PDT 24 Jul 16 04:54:43 PM PDT 24 222579128 ps
T146 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2613608211 Jul 16 04:54:12 PM PDT 24 Jul 16 04:54:16 PM PDT 24 50389669 ps
T169 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3245239503 Jul 16 04:54:45 PM PDT 24 Jul 16 04:54:47 PM PDT 24 41418502 ps
T98 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2399072774 Jul 16 04:55:00 PM PDT 24 Jul 16 04:55:08 PM PDT 24 258579427 ps
T101 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2189169269 Jul 16 04:54:14 PM PDT 24 Jul 16 04:54:17 PM PDT 24 96772948 ps
T132 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2943526232 Jul 16 04:54:17 PM PDT 24 Jul 16 04:54:20 PM PDT 24 34641953 ps
T182 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3465543453 Jul 16 04:54:30 PM PDT 24 Jul 16 04:54:31 PM PDT 24 88053972 ps
T183 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.662557406 Jul 16 04:54:16 PM PDT 24 Jul 16 04:54:19 PM PDT 24 128990861 ps
T99 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1804189699 Jul 16 04:54:12 PM PDT 24 Jul 16 04:54:18 PM PDT 24 936781459 ps
T147 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3759322944 Jul 16 04:54:58 PM PDT 24 Jul 16 04:55:04 PM PDT 24 40799923 ps
T864 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2777119925 Jul 16 04:54:25 PM PDT 24 Jul 16 04:54:26 PM PDT 24 19521594 ps
T100 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3202222098 Jul 16 04:54:45 PM PDT 24 Jul 16 04:54:48 PM PDT 24 46826137 ps
T133 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3961775861 Jul 16 04:54:31 PM PDT 24 Jul 16 04:54:35 PM PDT 24 818508633 ps
T108 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3960063720 Jul 16 04:54:44 PM PDT 24 Jul 16 04:54:46 PM PDT 24 35086375 ps
T102 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3991494214 Jul 16 04:54:25 PM PDT 24 Jul 16 04:54:28 PM PDT 24 77732919 ps
T148 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.281052581 Jul 16 04:54:13 PM PDT 24 Jul 16 04:54:16 PM PDT 24 15861717 ps
T184 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1486688465 Jul 16 04:54:21 PM PDT 24 Jul 16 04:54:23 PM PDT 24 84142009 ps
T865 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3780536224 Jul 16 04:54:37 PM PDT 24 Jul 16 04:54:39 PM PDT 24 36208429 ps
T866 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.114948285 Jul 16 04:54:16 PM PDT 24 Jul 16 04:54:24 PM PDT 24 665461006 ps
T170 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1597552961 Jul 16 04:54:40 PM PDT 24 Jul 16 04:54:42 PM PDT 24 16385833 ps
T104 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.876756361 Jul 16 04:54:15 PM PDT 24 Jul 16 04:54:22 PM PDT 24 177642877 ps
T126 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.24991068 Jul 16 04:54:39 PM PDT 24 Jul 16 04:54:41 PM PDT 24 38582842 ps
T166 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4062737717 Jul 16 04:54:50 PM PDT 24 Jul 16 04:54:53 PM PDT 24 1222336744 ps
T185 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3129797985 Jul 16 04:54:31 PM PDT 24 Jul 16 04:54:33 PM PDT 24 16549572 ps
T186 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.772007937 Jul 16 04:54:34 PM PDT 24 Jul 16 04:54:36 PM PDT 24 28824331 ps
T103 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3837263227 Jul 16 04:54:31 PM PDT 24 Jul 16 04:54:34 PM PDT 24 82473590 ps
T113 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3383940390 Jul 16 04:54:25 PM PDT 24 Jul 16 04:54:29 PM PDT 24 212383315 ps
T171 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4113889744 Jul 16 04:54:12 PM PDT 24 Jul 16 04:54:14 PM PDT 24 19619352 ps
T109 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4171589933 Jul 16 04:54:24 PM PDT 24 Jul 16 04:54:28 PM PDT 24 497268821 ps
T118 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2721375219 Jul 16 04:54:24 PM PDT 24 Jul 16 04:54:28 PM PDT 24 490371552 ps
T867 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3719984689 Jul 16 04:54:38 PM PDT 24 Jul 16 04:54:41 PM PDT 24 42311125 ps
T110 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2445306747 Jul 16 04:54:25 PM PDT 24 Jul 16 04:54:28 PM PDT 24 108622326 ps
T868 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2257228976 Jul 16 04:54:38 PM PDT 24 Jul 16 04:54:42 PM PDT 24 307892111 ps
T172 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2783494236 Jul 16 04:54:16 PM PDT 24 Jul 16 04:54:19 PM PDT 24 41039333 ps
T869 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3948620349 Jul 16 04:54:15 PM PDT 24 Jul 16 04:54:18 PM PDT 24 59368530 ps
T173 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2660421012 Jul 16 04:54:16 PM PDT 24 Jul 16 04:54:19 PM PDT 24 92068468 ps
T174 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1670593054 Jul 16 04:54:16 PM PDT 24 Jul 16 04:54:19 PM PDT 24 68375334 ps
T870 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2529358849 Jul 16 04:54:34 PM PDT 24 Jul 16 04:54:36 PM PDT 24 23033087 ps
T117 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2809565496 Jul 16 04:54:14 PM PDT 24 Jul 16 04:54:18 PM PDT 24 1328709381 ps
T175 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1506345687 Jul 16 04:54:34 PM PDT 24 Jul 16 04:54:36 PM PDT 24 58903309 ps
T871 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1587919302 Jul 16 04:54:26 PM PDT 24 Jul 16 04:54:51 PM PDT 24 4820040480 ps
T114 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1958431648 Jul 16 04:54:20 PM PDT 24 Jul 16 04:54:24 PM PDT 24 539811579 ps
T872 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4177394628 Jul 16 04:54:32 PM PDT 24 Jul 16 04:54:34 PM PDT 24 27461683 ps
T123 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3720940649 Jul 16 04:54:44 PM PDT 24 Jul 16 04:54:48 PM PDT 24 287605465 ps
T127 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2025230769 Jul 16 04:54:38 PM PDT 24 Jul 16 04:54:47 PM PDT 24 283396456 ps
T873 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3382616067 Jul 16 04:54:25 PM PDT 24 Jul 16 04:54:28 PM PDT 24 404635470 ps
T874 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3163709848 Jul 16 04:54:41 PM PDT 24 Jul 16 04:54:43 PM PDT 24 51560474 ps
T875 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1642668365 Jul 16 04:54:34 PM PDT 24 Jul 16 04:54:41 PM PDT 24 62999192 ps
T876 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1005441881 Jul 16 04:55:02 PM PDT 24 Jul 16 04:55:07 PM PDT 24 60783704 ps
T877 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2783824393 Jul 16 04:54:53 PM PDT 24 Jul 16 04:54:57 PM PDT 24 230696177 ps
T878 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2876772960 Jul 16 04:54:37 PM PDT 24 Jul 16 04:54:40 PM PDT 24 90686599 ps
T879 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4051929311 Jul 16 04:54:23 PM PDT 24 Jul 16 04:54:38 PM PDT 24 2585666767 ps
T115 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3294766665 Jul 16 04:54:16 PM PDT 24 Jul 16 04:54:21 PM PDT 24 41717340 ps
T130 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3885550435 Jul 16 04:54:41 PM PDT 24 Jul 16 04:54:45 PM PDT 24 448826142 ps
T880 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2104347340 Jul 16 04:54:37 PM PDT 24 Jul 16 04:54:39 PM PDT 24 95564357 ps
T881 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2376288156 Jul 16 04:54:17 PM PDT 24 Jul 16 04:54:20 PM PDT 24 243503821 ps
T882 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.760648203 Jul 16 04:54:25 PM PDT 24 Jul 16 04:54:34 PM PDT 24 341135806 ps
T119 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1295251286 Jul 16 04:54:27 PM PDT 24 Jul 16 04:54:31 PM PDT 24 146119129 ps
T111 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3905357369 Jul 16 04:54:30 PM PDT 24 Jul 16 04:54:33 PM PDT 24 553055266 ps
T883 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3172231392 Jul 16 04:54:42 PM PDT 24 Jul 16 04:54:44 PM PDT 24 22816942 ps
T884 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2901349195 Jul 16 04:54:39 PM PDT 24 Jul 16 04:54:43 PM PDT 24 1022732952 ps
T885 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4284751211 Jul 16 04:54:14 PM PDT 24 Jul 16 04:54:19 PM PDT 24 187253848 ps
T886 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2976777324 Jul 16 04:54:58 PM PDT 24 Jul 16 04:55:04 PM PDT 24 36425824 ps
T887 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.322727332 Jul 16 04:54:21 PM PDT 24 Jul 16 04:54:26 PM PDT 24 703690815 ps
T888 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.4293968797 Jul 16 04:54:34 PM PDT 24 Jul 16 04:54:36 PM PDT 24 98158172 ps
T889 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.37596793 Jul 16 04:54:25 PM PDT 24 Jul 16 04:54:28 PM PDT 24 111641166 ps
T890 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3712335035 Jul 16 04:54:15 PM PDT 24 Jul 16 04:54:38 PM PDT 24 1915627781 ps
T891 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4116777644 Jul 16 04:54:42 PM PDT 24 Jul 16 04:54:45 PM PDT 24 25990771 ps
T892 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1230411832 Jul 16 04:54:25 PM PDT 24 Jul 16 04:54:26 PM PDT 24 70836496 ps
T893 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1390675967 Jul 16 04:54:14 PM PDT 24 Jul 16 04:54:20 PM PDT 24 670938097 ps
T176 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1971218160 Jul 16 04:54:32 PM PDT 24 Jul 16 04:54:34 PM PDT 24 14167051 ps
T124 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1728773419 Jul 16 04:54:35 PM PDT 24 Jul 16 04:54:37 PM PDT 24 59580455 ps
T121 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1620174148 Jul 16 04:54:49 PM PDT 24 Jul 16 04:54:53 PM PDT 24 106023575 ps
T894 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1865939898 Jul 16 04:54:15 PM PDT 24 Jul 16 04:54:19 PM PDT 24 480070116 ps
T895 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2593480819 Jul 16 04:54:13 PM PDT 24 Jul 16 04:54:16 PM PDT 24 120607661 ps
T896 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4120432687 Jul 16 04:54:25 PM PDT 24 Jul 16 04:54:27 PM PDT 24 114535557 ps
T897 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2750709754 Jul 16 04:54:14 PM PDT 24 Jul 16 04:54:20 PM PDT 24 125394854 ps
T898 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2829263281 Jul 16 04:54:16 PM PDT 24 Jul 16 04:54:19 PM PDT 24 41727520 ps
T899 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2384394314 Jul 16 04:54:37 PM PDT 24 Jul 16 04:54:39 PM PDT 24 36486293 ps
T179 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3748910479 Jul 16 04:54:33 PM PDT 24 Jul 16 04:54:35 PM PDT 24 18427814 ps
T900 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.767904995 Jul 16 04:54:16 PM PDT 24 Jul 16 04:54:19 PM PDT 24 14121522 ps
T901 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.503709864 Jul 16 04:54:26 PM PDT 24 Jul 16 04:54:30 PM PDT 24 118977987 ps
T131 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.469032562 Jul 16 04:54:35 PM PDT 24 Jul 16 04:54:39 PM PDT 24 61342936 ps
T902 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1266963032 Jul 16 04:54:41 PM PDT 24 Jul 16 04:54:43 PM PDT 24 125039802 ps
T903 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.53268301 Jul 16 04:54:33 PM PDT 24 Jul 16 04:55:01 PM PDT 24 1796430552 ps
T180 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3430619894 Jul 16 04:54:36 PM PDT 24 Jul 16 04:54:38 PM PDT 24 12401671 ps
T904 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3164058760 Jul 16 04:54:16 PM PDT 24 Jul 16 04:54:21 PM PDT 24 60344635 ps
T905 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.966395243 Jul 16 04:54:32 PM PDT 24 Jul 16 04:54:34 PM PDT 24 88308154 ps
T906 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3537944589 Jul 16 04:54:43 PM PDT 24 Jul 16 04:54:46 PM PDT 24 93675394 ps
T907 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3762062647 Jul 16 04:54:25 PM PDT 24 Jul 16 04:54:28 PM PDT 24 60066643 ps
T908 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.337569928 Jul 16 04:54:34 PM PDT 24 Jul 16 04:54:36 PM PDT 24 22666581 ps
T909 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.478007157 Jul 16 04:54:38 PM PDT 24 Jul 16 04:55:03 PM PDT 24 973262328 ps
T910 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3141408637 Jul 16 04:54:43 PM PDT 24 Jul 16 04:54:47 PM PDT 24 56869311 ps
T177 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2158586670 Jul 16 04:54:32 PM PDT 24 Jul 16 04:54:34 PM PDT 24 23127035 ps
T911 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3772519679 Jul 16 04:54:15 PM PDT 24 Jul 16 04:54:24 PM PDT 24 2337179244 ps
T912 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.231603254 Jul 16 04:54:25 PM PDT 24 Jul 16 04:54:36 PM PDT 24 478744642 ps
T913 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3499267001 Jul 16 04:54:26 PM PDT 24 Jul 16 04:54:29 PM PDT 24 65379800 ps
T914 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.73561327 Jul 16 04:54:39 PM PDT 24 Jul 16 04:54:41 PM PDT 24 12136881 ps
T915 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2307046747 Jul 16 04:54:33 PM PDT 24 Jul 16 04:54:36 PM PDT 24 418617717 ps
T916 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.163386842 Jul 16 04:54:40 PM PDT 24 Jul 16 04:54:42 PM PDT 24 58711597 ps
T917 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3780206678 Jul 16 04:54:43 PM PDT 24 Jul 16 04:54:56 PM PDT 24 300334333 ps
T918 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.78820423 Jul 16 04:54:16 PM PDT 24 Jul 16 04:54:19 PM PDT 24 53036243 ps
T919 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3076526736 Jul 16 04:54:13 PM PDT 24 Jul 16 04:54:16 PM PDT 24 46488242 ps
T920 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1034308356 Jul 16 04:54:17 PM PDT 24 Jul 16 04:54:20 PM PDT 24 18529934 ps
T921 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2333681201 Jul 16 04:54:31 PM PDT 24 Jul 16 04:54:32 PM PDT 24 27527383 ps
T922 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2696955133 Jul 16 04:54:16 PM PDT 24 Jul 16 04:54:19 PM PDT 24 364415542 ps
T923 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.790814466 Jul 16 04:54:44 PM PDT 24 Jul 16 04:54:47 PM PDT 24 85506614 ps
T178 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3215695822 Jul 16 04:54:18 PM PDT 24 Jul 16 04:54:20 PM PDT 24 19010185 ps
T924 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3506003360 Jul 16 04:54:38 PM PDT 24 Jul 16 04:54:40 PM PDT 24 251104834 ps
T925 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.152425125 Jul 16 04:54:14 PM PDT 24 Jul 16 04:54:16 PM PDT 24 52689958 ps
T926 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1530438244 Jul 16 04:54:26 PM PDT 24 Jul 16 04:54:27 PM PDT 24 34479076 ps
T927 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.4144495699 Jul 16 04:54:31 PM PDT 24 Jul 16 04:54:36 PM PDT 24 203565964 ps
T928 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2824955643 Jul 16 04:54:46 PM PDT 24 Jul 16 04:54:48 PM PDT 24 27584212 ps
T929 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3214370654 Jul 16 04:54:32 PM PDT 24 Jul 16 04:54:34 PM PDT 24 70447139 ps
T930 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1847538634 Jul 16 04:54:17 PM PDT 24 Jul 16 04:54:20 PM PDT 24 65296608 ps
T931 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2612132064 Jul 16 04:54:14 PM PDT 24 Jul 16 04:54:17 PM PDT 24 22973262 ps
T122 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.378244406 Jul 16 04:54:12 PM PDT 24 Jul 16 04:54:16 PM PDT 24 213870091 ps
T932 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.884234115 Jul 16 04:54:57 PM PDT 24 Jul 16 04:55:03 PM PDT 24 465314984 ps
T933 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2215933442 Jul 16 04:54:44 PM PDT 24 Jul 16 04:54:47 PM PDT 24 93700927 ps
T934 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1195081199 Jul 16 04:54:47 PM PDT 24 Jul 16 04:54:49 PM PDT 24 32175753 ps
T935 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1430014143 Jul 16 04:54:52 PM PDT 24 Jul 16 04:54:55 PM PDT 24 112777236 ps
T936 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1674789187 Jul 16 04:54:36 PM PDT 24 Jul 16 04:54:41 PM PDT 24 385845020 ps
T937 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.240046441 Jul 16 04:54:27 PM PDT 24 Jul 16 04:54:29 PM PDT 24 16223272 ps
T938 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3227999446 Jul 16 04:54:45 PM PDT 24 Jul 16 04:54:47 PM PDT 24 35242597 ps
T939 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.931562484 Jul 16 04:54:44 PM PDT 24 Jul 16 04:54:47 PM PDT 24 239632855 ps
T940 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1699887255 Jul 16 04:54:30 PM PDT 24 Jul 16 04:54:31 PM PDT 24 298314658 ps
T941 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.71492657 Jul 16 04:54:36 PM PDT 24 Jul 16 04:54:38 PM PDT 24 88360897 ps
T129 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.632827328 Jul 16 04:54:22 PM PDT 24 Jul 16 04:54:26 PM PDT 24 225486825 ps
T942 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.4173341551 Jul 16 04:54:16 PM PDT 24 Jul 16 04:54:19 PM PDT 24 16090433 ps
T943 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3400334548 Jul 16 04:54:16 PM PDT 24 Jul 16 04:55:14 PM PDT 24 10523084839 ps
T125 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.323959789 Jul 16 04:54:48 PM PDT 24 Jul 16 04:54:51 PM PDT 24 480430224 ps
T944 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1538466287 Jul 16 04:54:47 PM PDT 24 Jul 16 04:54:50 PM PDT 24 177431832 ps
T945 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.64415005 Jul 16 04:54:36 PM PDT 24 Jul 16 04:54:41 PM PDT 24 122659931 ps
T946 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1589499661 Jul 16 04:54:36 PM PDT 24 Jul 16 04:54:40 PM PDT 24 88619286 ps
T947 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3934746000 Jul 16 04:54:49 PM PDT 24 Jul 16 04:54:53 PM PDT 24 380453185 ps
T948 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3641269668 Jul 16 04:54:14 PM PDT 24 Jul 16 04:54:20 PM PDT 24 2415034681 ps
T949 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3321199526 Jul 16 04:54:30 PM PDT 24 Jul 16 04:54:32 PM PDT 24 95289339 ps
T950 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2336333012 Jul 16 04:54:35 PM PDT 24 Jul 16 04:54:38 PM PDT 24 28191620 ps
T951 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1559955940 Jul 16 04:54:44 PM PDT 24 Jul 16 04:54:48 PM PDT 24 138108364 ps
T952 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3202362428 Jul 16 04:54:34 PM PDT 24 Jul 16 04:54:36 PM PDT 24 46799353 ps
T953 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1809999452 Jul 16 04:54:52 PM PDT 24 Jul 16 04:54:55 PM PDT 24 129488089 ps
T954 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2691103966 Jul 16 04:54:24 PM PDT 24 Jul 16 04:54:27 PM PDT 24 93668220 ps
T955 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3753828220 Jul 16 04:54:22 PM PDT 24 Jul 16 04:54:23 PM PDT 24 30830566 ps
T956 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3262178666 Jul 16 04:54:35 PM PDT 24 Jul 16 04:54:38 PM PDT 24 87885095 ps
T957 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2092992193 Jul 16 04:54:38 PM PDT 24 Jul 16 04:54:40 PM PDT 24 443974486 ps
T958 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2453174077 Jul 16 04:54:30 PM PDT 24 Jul 16 04:54:33 PM PDT 24 103292147 ps
T959 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3399179133 Jul 16 04:54:52 PM PDT 24 Jul 16 04:54:57 PM PDT 24 624046372 ps
T960 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3241265647 Jul 16 04:54:43 PM PDT 24 Jul 16 04:54:45 PM PDT 24 47687305 ps
T961 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.955916933 Jul 16 04:54:37 PM PDT 24 Jul 16 04:54:54 PM PDT 24 6460494225 ps
T962 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1700584197 Jul 16 04:54:37 PM PDT 24 Jul 16 04:54:39 PM PDT 24 24892098 ps
T963 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1970452572 Jul 16 04:54:14 PM PDT 24 Jul 16 04:54:18 PM PDT 24 151637636 ps
T964 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.417666479 Jul 16 04:54:16 PM PDT 24 Jul 16 04:54:21 PM PDT 24 314280528 ps
T181 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3739544785 Jul 16 04:54:48 PM PDT 24 Jul 16 04:54:50 PM PDT 24 96502731 ps
T965 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.844918632 Jul 16 04:54:39 PM PDT 24 Jul 16 04:54:43 PM PDT 24 187821582 ps
T966 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1160894527 Jul 16 04:54:49 PM PDT 24 Jul 16 04:54:51 PM PDT 24 68676754 ps
T967 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.608671441 Jul 16 04:54:45 PM PDT 24 Jul 16 04:54:48 PM PDT 24 97622142 ps
T968 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4114149461 Jul 16 04:54:15 PM PDT 24 Jul 16 04:54:18 PM PDT 24 45381507 ps
T969 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.4022567875 Jul 16 04:54:35 PM PDT 24 Jul 16 04:54:37 PM PDT 24 18404286 ps
T970 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.4143526711 Jul 16 04:54:26 PM PDT 24 Jul 16 04:54:39 PM PDT 24 12343931941 ps
T971 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.4285502924 Jul 16 04:54:22 PM PDT 24 Jul 16 04:54:24 PM PDT 24 60035337 ps
T972 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2663807625 Jul 16 04:54:17 PM PDT 24 Jul 16 04:54:20 PM PDT 24 52324842 ps
T973 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.4162041047 Jul 16 04:54:42 PM PDT 24 Jul 16 04:54:47 PM PDT 24 111695488 ps
T128 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3874174614 Jul 16 04:54:32 PM PDT 24 Jul 16 04:54:35 PM PDT 24 226728328 ps
T974 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4046661315 Jul 16 04:54:35 PM PDT 24 Jul 16 04:54:37 PM PDT 24 44049266 ps
T975 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4069124135 Jul 16 04:54:32 PM PDT 24 Jul 16 04:54:46 PM PDT 24 6783078404 ps
T120 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3044085312 Jul 16 04:54:35 PM PDT 24 Jul 16 04:54:39 PM PDT 24 145562229 ps
T976 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1731027167 Jul 16 04:54:24 PM PDT 24 Jul 16 04:54:28 PM PDT 24 107137844 ps
T112 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1548091555 Jul 16 04:54:40 PM PDT 24 Jul 16 04:54:44 PM PDT 24 149543276 ps
T977 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.295732662 Jul 16 04:54:16 PM PDT 24 Jul 16 04:54:20 PM PDT 24 89601839 ps
T978 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3124802839 Jul 16 04:54:40 PM PDT 24 Jul 16 04:54:43 PM PDT 24 45584005 ps
T979 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.487685112 Jul 16 04:54:30 PM PDT 24 Jul 16 04:54:54 PM PDT 24 1242948907 ps
T980 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.940424585 Jul 16 04:54:39 PM PDT 24 Jul 16 04:54:43 PM PDT 24 240453742 ps
T981 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2283406254 Jul 16 04:54:52 PM PDT 24 Jul 16 04:54:54 PM PDT 24 22726402 ps
T982 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1924558587 Jul 16 04:54:15 PM PDT 24 Jul 16 04:54:19 PM PDT 24 424560611 ps

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.460055985
Short name T2
Test name
Test status
Simulation time 7359209212 ps
CPU time 237.75 seconds
Started Jul 16 05:05:46 PM PDT 24
Finished Jul 16 05:09:48 PM PDT 24
Peak memory 276652 kb
Host smart-ee444545-0445-4c96-9d63-2ded4af1df38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460055985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.460055985
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3692072430
Short name T33
Test name
Test status
Simulation time 325367311 ps
CPU time 8.27 seconds
Started Jul 16 05:05:46 PM PDT 24
Finished Jul 16 05:05:59 PM PDT 24
Peak memory 224720 kb
Host smart-489f5d75-17f6-46e8-8dc4-3a1c06ab165d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692072430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3692072430
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3169675561
Short name T17
Test name
Test status
Simulation time 235808621124 ps
CPU time 2855.26 seconds
Started Jul 16 05:05:15 PM PDT 24
Finished Jul 16 05:52:53 PM PDT 24
Peak memory 1552508 kb
Host smart-48ff0e38-5053-4024-bcfb-26501b2f8fa5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3169675561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.3169675561
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.3021839408
Short name T40
Test name
Test status
Simulation time 375358256 ps
CPU time 11.12 seconds
Started Jul 16 05:05:46 PM PDT 24
Finished Jul 16 05:06:02 PM PDT 24
Peak memory 218276 kb
Host smart-8424fe79-4b38-43f3-86a1-54145399fdb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021839408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.3021839408
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1172249950
Short name T30
Test name
Test status
Simulation time 50690680 ps
CPU time 0.76 seconds
Started Jul 16 05:04:37 PM PDT 24
Finished Jul 16 05:04:41 PM PDT 24
Peak memory 208212 kb
Host smart-919a8f13-baf1-4528-a07b-c17cb254b671
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172249950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.1172249950
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3069342887
Short name T93
Test name
Test status
Simulation time 983707649 ps
CPU time 12.04 seconds
Started Jul 16 05:05:33 PM PDT 24
Finished Jul 16 05:05:50 PM PDT 24
Peak memory 217788 kb
Host smart-b91e7ba4-b2c0-463c-a503-a9f2d3e184a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069342887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3069342887
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1556482983
Short name T53
Test name
Test status
Simulation time 219555296 ps
CPU time 36.02 seconds
Started Jul 16 05:03:50 PM PDT 24
Finished Jul 16 05:04:27 PM PDT 24
Peak memory 269432 kb
Host smart-949062fd-1315-478f-9913-26816ae8f2ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556482983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1556482983
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1701796653
Short name T18
Test name
Test status
Simulation time 103134204298 ps
CPU time 675.68 seconds
Started Jul 16 05:05:41 PM PDT 24
Finished Jul 16 05:17:03 PM PDT 24
Peak memory 261472 kb
Host smart-7984ce48-9245-48e3-b695-6ec323ebee82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701796653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1701796653
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1804189699
Short name T99
Test name
Test status
Simulation time 936781459 ps
CPU time 3.96 seconds
Started Jul 16 04:54:12 PM PDT 24
Finished Jul 16 04:54:18 PM PDT 24
Peak memory 217340 kb
Host smart-8f836e02-d17b-4a93-9b18-89af4c1e8fcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804189699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1804189699
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.940813792
Short name T13
Test name
Test status
Simulation time 1582190263 ps
CPU time 13.19 seconds
Started Jul 16 05:06:08 PM PDT 24
Finished Jul 16 05:06:23 PM PDT 24
Peak memory 217636 kb
Host smart-3c300da3-e95e-4f25-b54a-67cfbaaf5a3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940813792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.940813792
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.763023168
Short name T11
Test name
Test status
Simulation time 32907972 ps
CPU time 0.98 seconds
Started Jul 16 05:05:14 PM PDT 24
Finished Jul 16 05:05:17 PM PDT 24
Peak memory 208508 kb
Host smart-3a5a723d-eed2-4275-abfc-832eb8e28b53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763023168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.763023168
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.876756361
Short name T104
Test name
Test status
Simulation time 177642877 ps
CPU time 4.97 seconds
Started Jul 16 04:54:15 PM PDT 24
Finished Jul 16 04:54:22 PM PDT 24
Peak memory 222400 kb
Host smart-930c86a8-a05d-4714-a68d-af23d40d258c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876756
361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.876756361
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.430384604
Short name T3
Test name
Test status
Simulation time 1535164658 ps
CPU time 8.67 seconds
Started Jul 16 05:05:15 PM PDT 24
Finished Jul 16 05:05:26 PM PDT 24
Peak memory 216896 kb
Host smart-2a16abaf-e0a0-4d4b-9f30-ff31dc3381d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430384604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.430384604
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3245239503
Short name T169
Test name
Test status
Simulation time 41418502 ps
CPU time 1.01 seconds
Started Jul 16 04:54:45 PM PDT 24
Finished Jul 16 04:54:47 PM PDT 24
Peak memory 209248 kb
Host smart-4d236ac0-b1aa-4ebd-86b8-84706f387df0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245239503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3245239503
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4113889744
Short name T171
Test name
Test status
Simulation time 19619352 ps
CPU time 0.91 seconds
Started Jul 16 04:54:12 PM PDT 24
Finished Jul 16 04:54:14 PM PDT 24
Peak memory 209100 kb
Host smart-eddac0f0-03be-44e4-989b-9b46810525a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113889744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.4113889744
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3294766665
Short name T115
Test name
Test status
Simulation time 41717340 ps
CPU time 2.93 seconds
Started Jul 16 04:54:16 PM PDT 24
Finished Jul 16 04:54:21 PM PDT 24
Peak memory 218704 kb
Host smart-04d6c7bc-fdc7-433f-be8a-8985191cdb4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294766665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3294766665
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.472856561
Short name T62
Test name
Test status
Simulation time 1078255062 ps
CPU time 21.44 seconds
Started Jul 16 05:06:05 PM PDT 24
Finished Jul 16 05:06:28 PM PDT 24
Peak memory 250452 kb
Host smart-211cfc10-2ff8-4ffc-9aed-c1c547123d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472856561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.472856561
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1620174148
Short name T121
Test name
Test status
Simulation time 106023575 ps
CPU time 3.07 seconds
Started Jul 16 04:54:49 PM PDT 24
Finished Jul 16 04:54:53 PM PDT 24
Peak memory 222336 kb
Host smart-048b8dec-34b5-4236-9351-3344d4616f9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620174148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1620174148
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1548091555
Short name T112
Test name
Test status
Simulation time 149543276 ps
CPU time 2.83 seconds
Started Jul 16 04:54:40 PM PDT 24
Finished Jul 16 04:54:44 PM PDT 24
Peak memory 217336 kb
Host smart-9e8b339b-06bd-4b30-8d20-84616eb8abc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548091555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1548091555
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.632827328
Short name T129
Test name
Test status
Simulation time 225486825 ps
CPU time 2.85 seconds
Started Jul 16 04:54:22 PM PDT 24
Finished Jul 16 04:54:26 PM PDT 24
Peak memory 222344 kb
Host smart-782f0c48-f33b-48c6-98f1-a72ef452230a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632827328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e
rr.632827328
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.4289178019
Short name T37
Test name
Test status
Simulation time 531847713 ps
CPU time 10.98 seconds
Started Jul 16 05:04:37 PM PDT 24
Finished Jul 16 05:04:50 PM PDT 24
Peak memory 217680 kb
Host smart-0f6d457a-669f-4511-a60d-7f39c5e6de25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289178019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.4289178019
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.1107510327
Short name T45
Test name
Test status
Simulation time 16498549734 ps
CPU time 550.32 seconds
Started Jul 16 05:05:51 PM PDT 24
Finished Jul 16 05:15:03 PM PDT 24
Peak memory 315180 kb
Host smart-2654bd03-dfe0-4923-a3c3-19285fab12ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1107510327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.1107510327
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2025230769
Short name T127
Test name
Test status
Simulation time 283396456 ps
CPU time 3.49 seconds
Started Jul 16 04:54:38 PM PDT 24
Finished Jul 16 04:54:47 PM PDT 24
Peak memory 222336 kb
Host smart-305ccc6b-9080-4a1c-b65b-2a8935786d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025230769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2025230769
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3837263227
Short name T103
Test name
Test status
Simulation time 82473590 ps
CPU time 2.74 seconds
Started Jul 16 04:54:31 PM PDT 24
Finished Jul 16 04:54:34 PM PDT 24
Peak memory 217300 kb
Host smart-300fb566-9f59-4502-ac4e-ee32ff92669c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837263227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3837263227
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1295251286
Short name T119
Test name
Test status
Simulation time 146119129 ps
CPU time 2.49 seconds
Started Jul 16 04:54:27 PM PDT 24
Finished Jul 16 04:54:31 PM PDT 24
Peak memory 221820 kb
Host smart-a3ddfee0-e2f4-4023-a3d9-a0a25805ec7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295251286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1295251286
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.937045212
Short name T188
Test name
Test status
Simulation time 38135029 ps
CPU time 0.84 seconds
Started Jul 16 05:03:31 PM PDT 24
Finished Jul 16 05:03:33 PM PDT 24
Peak memory 208348 kb
Host smart-a11ef72f-e88d-4c99-ab68-4edfb37a7f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937045212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.937045212
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1539407070
Short name T340
Test name
Test status
Simulation time 545828629 ps
CPU time 7.91 seconds
Started Jul 16 05:04:37 PM PDT 24
Finished Jul 16 05:04:48 PM PDT 24
Peak memory 225488 kb
Host smart-c7ac40a1-10f7-4263-bf08-ae7660d3997f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539407070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1539407070
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2110885187
Short name T189
Test name
Test status
Simulation time 11258202 ps
CPU time 0.8 seconds
Started Jul 16 05:03:47 PM PDT 24
Finished Jul 16 05:03:49 PM PDT 24
Peak memory 208040 kb
Host smart-e06aa333-1004-40e8-b8d3-7839c5542385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110885187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2110885187
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2516290563
Short name T158
Test name
Test status
Simulation time 30271447 ps
CPU time 0.81 seconds
Started Jul 16 05:03:49 PM PDT 24
Finished Jul 16 05:03:52 PM PDT 24
Peak memory 208372 kb
Host smart-e349b07c-b6ce-4dd9-a9d2-68843d9b9cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516290563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2516290563
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3828682297
Short name T190
Test name
Test status
Simulation time 29940234 ps
CPU time 0.88 seconds
Started Jul 16 05:04:09 PM PDT 24
Finished Jul 16 05:04:11 PM PDT 24
Peak memory 208252 kb
Host smart-b5e3355d-78ad-4d3c-aa80-ddf68e752a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828682297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3828682297
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3785116778
Short name T191
Test name
Test status
Simulation time 44568951 ps
CPU time 0.89 seconds
Started Jul 16 05:04:21 PM PDT 24
Finished Jul 16 05:04:22 PM PDT 24
Peak memory 208256 kb
Host smart-f6bf3f76-63f8-4d77-b02e-1738beeb11a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785116778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3785116778
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.3018806361
Short name T19
Test name
Test status
Simulation time 1719277533 ps
CPU time 50.36 seconds
Started Jul 16 05:04:59 PM PDT 24
Finished Jul 16 05:05:51 PM PDT 24
Peak memory 217684 kb
Host smart-2dc9d3b4-886b-4b96-850d-d5a1c357e053
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018806361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.3018806361
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.114948285
Short name T866
Test name
Test status
Simulation time 665461006 ps
CPU time 5.65 seconds
Started Jul 16 04:54:16 PM PDT 24
Finished Jul 16 04:54:24 PM PDT 24
Peak memory 208908 kb
Host smart-2f4df7b8-1a0b-45ff-8780-9cb42b7204ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114948285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.114948285
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.378244406
Short name T122
Test name
Test status
Simulation time 213870091 ps
CPU time 2.44 seconds
Started Jul 16 04:54:12 PM PDT 24
Finished Jul 16 04:54:16 PM PDT 24
Peak memory 217356 kb
Host smart-7ba7069e-cb40-4d9e-9654-3d0f3ac644ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378244406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.378244406
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1958431648
Short name T114
Test name
Test status
Simulation time 539811579 ps
CPU time 2.8 seconds
Started Jul 16 04:54:20 PM PDT 24
Finished Jul 16 04:54:24 PM PDT 24
Peak memory 217312 kb
Host smart-11f13f8c-624e-4b0e-b381-bfbc131a6d5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958431648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1958431648
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3044085312
Short name T120
Test name
Test status
Simulation time 145562229 ps
CPU time 3.3 seconds
Started Jul 16 04:54:35 PM PDT 24
Finished Jul 16 04:54:39 PM PDT 24
Peak memory 222236 kb
Host smart-f5787f10-c5db-4e20-9942-68a34ee19728
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044085312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3044085312
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3885550435
Short name T130
Test name
Test status
Simulation time 448826142 ps
CPU time 3.05 seconds
Started Jul 16 04:54:41 PM PDT 24
Finished Jul 16 04:54:45 PM PDT 24
Peak memory 222312 kb
Host smart-280bc253-7327-4992-870d-74a7c97eb824
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885550435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3885550435
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2721375219
Short name T118
Test name
Test status
Simulation time 490371552 ps
CPU time 3.1 seconds
Started Jul 16 04:54:24 PM PDT 24
Finished Jul 16 04:54:28 PM PDT 24
Peak memory 217340 kb
Host smart-fab724b7-52de-491c-b1bc-01a26fe39ec7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721375219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2721375219
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3720940649
Short name T123
Test name
Test status
Simulation time 287605465 ps
CPU time 2.78 seconds
Started Jul 16 04:54:44 PM PDT 24
Finished Jul 16 04:54:48 PM PDT 24
Peak memory 222088 kb
Host smart-b47637bd-625b-4fe3-9b98-1116b5822e40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720940649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3720940649
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1785736439
Short name T15
Test name
Test status
Simulation time 139829995 ps
CPU time 2.96 seconds
Started Jul 16 05:04:34 PM PDT 24
Finished Jul 16 05:04:38 PM PDT 24
Peak memory 217656 kb
Host smart-cc56c63e-189e-4738-aa5f-8156b9917348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785736439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1785736439
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2783494236
Short name T172
Test name
Test status
Simulation time 41039333 ps
CPU time 1.13 seconds
Started Jul 16 04:54:16 PM PDT 24
Finished Jul 16 04:54:19 PM PDT 24
Peak memory 209016 kb
Host smart-59a272f3-0a5c-4aaf-a9f6-0cf8a95bbc54
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783494236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2783494236
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2630927091
Short name T862
Test name
Test status
Simulation time 63649885 ps
CPU time 1.26 seconds
Started Jul 16 04:54:17 PM PDT 24
Finished Jul 16 04:54:20 PM PDT 24
Peak memory 208980 kb
Host smart-dbc447d9-3416-46da-8876-c5c64ddc652e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630927091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2630927091
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2158586670
Short name T177
Test name
Test status
Simulation time 23127035 ps
CPU time 1.07 seconds
Started Jul 16 04:54:32 PM PDT 24
Finished Jul 16 04:54:34 PM PDT 24
Peak memory 211248 kb
Host smart-bffdb955-311c-40cd-af3b-c90920bf6d9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158586670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2158586670
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2612132064
Short name T931
Test name
Test status
Simulation time 22973262 ps
CPU time 1.24 seconds
Started Jul 16 04:54:14 PM PDT 24
Finished Jul 16 04:54:17 PM PDT 24
Peak memory 217568 kb
Host smart-7a432b83-2d3e-4ad6-a46f-b02dd8e46531
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612132064 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2612132064
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.281052581
Short name T148
Test name
Test status
Simulation time 15861717 ps
CPU time 0.87 seconds
Started Jul 16 04:54:13 PM PDT 24
Finished Jul 16 04:54:16 PM PDT 24
Peak memory 209136 kb
Host smart-7ce892d4-af3d-455c-bfe7-579c80cea38b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281052581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.281052581
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3076526736
Short name T919
Test name
Test status
Simulation time 46488242 ps
CPU time 1.23 seconds
Started Jul 16 04:54:13 PM PDT 24
Finished Jul 16 04:54:16 PM PDT 24
Peak memory 208980 kb
Host smart-d1419e0a-a8ff-4716-87e2-5b8bcf6cb907
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076526736 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3076526736
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1885523789
Short name T136
Test name
Test status
Simulation time 2745828183 ps
CPU time 30.46 seconds
Started Jul 16 04:54:11 PM PDT 24
Finished Jul 16 04:54:42 PM PDT 24
Peak memory 209164 kb
Host smart-ed5d9f2a-1a89-4d73-a3b3-074851efc5da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885523789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1885523789
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3382616067
Short name T873
Test name
Test status
Simulation time 404635470 ps
CPU time 1.94 seconds
Started Jul 16 04:54:25 PM PDT 24
Finished Jul 16 04:54:28 PM PDT 24
Peak memory 210700 kb
Host smart-dabb5bcc-0108-4e72-bc81-bd98c3ba1ae0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382616067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3382616067
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1390675967
Short name T893
Test name
Test status
Simulation time 670938097 ps
CPU time 3.29 seconds
Started Jul 16 04:54:14 PM PDT 24
Finished Jul 16 04:54:20 PM PDT 24
Peak memory 217400 kb
Host smart-fba81750-2dfb-48ec-bc18-5f633cbf459a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139067
5967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1390675967
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2593480819
Short name T895
Test name
Test status
Simulation time 120607661 ps
CPU time 2.14 seconds
Started Jul 16 04:54:13 PM PDT 24
Finished Jul 16 04:54:16 PM PDT 24
Peak memory 209060 kb
Host smart-b29e5b78-e5f0-4f4c-87d2-f79a35c262e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593480819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2593480819
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1486688465
Short name T184
Test name
Test status
Simulation time 84142009 ps
CPU time 1.04 seconds
Started Jul 16 04:54:21 PM PDT 24
Finished Jul 16 04:54:23 PM PDT 24
Peak memory 209124 kb
Host smart-45120d58-a622-4e38-82b2-c48fdacf9a26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486688465 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1486688465
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.662557406
Short name T183
Test name
Test status
Simulation time 128990861 ps
CPU time 1.06 seconds
Started Jul 16 04:54:16 PM PDT 24
Finished Jul 16 04:54:19 PM PDT 24
Peak memory 209032 kb
Host smart-cc6f55c3-f7c3-436e-a8f1-e73be873c8fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662557406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
same_csr_outstanding.662557406
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2660421012
Short name T173
Test name
Test status
Simulation time 92068468 ps
CPU time 1.04 seconds
Started Jul 16 04:54:16 PM PDT 24
Finished Jul 16 04:54:19 PM PDT 24
Peak memory 209112 kb
Host smart-9f0bfa2e-a8a4-43c8-b3ad-c890a3203f6a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660421012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.2660421012
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.417666479
Short name T964
Test name
Test status
Simulation time 314280528 ps
CPU time 2.93 seconds
Started Jul 16 04:54:16 PM PDT 24
Finished Jul 16 04:54:21 PM PDT 24
Peak memory 209056 kb
Host smart-3b6ed822-5427-4df4-a4cb-b8a1d6775e3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417666479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.417666479
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.767904995
Short name T900
Test name
Test status
Simulation time 14121522 ps
CPU time 0.91 seconds
Started Jul 16 04:54:16 PM PDT 24
Finished Jul 16 04:54:19 PM PDT 24
Peak memory 209736 kb
Host smart-727194d1-cacb-436e-ad05-f67d7a195740
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767904995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.767904995
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2189169269
Short name T101
Test name
Test status
Simulation time 96772948 ps
CPU time 1.44 seconds
Started Jul 16 04:54:14 PM PDT 24
Finished Jul 16 04:54:17 PM PDT 24
Peak memory 224284 kb
Host smart-15490651-e79d-423f-a6d6-61b9d9513cf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189169269 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2189169269
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.152425125
Short name T925
Test name
Test status
Simulation time 52689958 ps
CPU time 1 seconds
Started Jul 16 04:54:14 PM PDT 24
Finished Jul 16 04:54:16 PM PDT 24
Peak memory 209116 kb
Host smart-ab98da08-9ad6-450b-88e5-2124d14927cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152425125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.152425125
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3948620349
Short name T869
Test name
Test status
Simulation time 59368530 ps
CPU time 1.2 seconds
Started Jul 16 04:54:15 PM PDT 24
Finished Jul 16 04:54:18 PM PDT 24
Peak memory 208936 kb
Host smart-7721e868-e50f-42c4-837f-e1ad20a27b1b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948620349 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.3948620349
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4051929311
Short name T879
Test name
Test status
Simulation time 2585666767 ps
CPU time 15.16 seconds
Started Jul 16 04:54:23 PM PDT 24
Finished Jul 16 04:54:38 PM PDT 24
Peak memory 209180 kb
Host smart-e5bbdc12-53a5-428e-8d0d-17ce56e412e8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051929311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.4051929311
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3400334548
Short name T943
Test name
Test status
Simulation time 10523084839 ps
CPU time 56.88 seconds
Started Jul 16 04:54:16 PM PDT 24
Finished Jul 16 04:55:14 PM PDT 24
Peak memory 209084 kb
Host smart-1bffd308-24cd-4936-a950-6d2502152635
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400334548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3400334548
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2750709754
Short name T897
Test name
Test status
Simulation time 125394854 ps
CPU time 3.79 seconds
Started Jul 16 04:54:14 PM PDT 24
Finished Jul 16 04:54:20 PM PDT 24
Peak memory 210848 kb
Host smart-2838a0fd-671c-4d16-8909-4ffeb7b56c25
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750709754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2750709754
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2696955133
Short name T922
Test name
Test status
Simulation time 364415542 ps
CPU time 1.8 seconds
Started Jul 16 04:54:16 PM PDT 24
Finished Jul 16 04:54:19 PM PDT 24
Peak memory 220188 kb
Host smart-e9f814fd-a94a-43ea-ab2a-d510758ca6b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269695
5133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2696955133
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2691103966
Short name T954
Test name
Test status
Simulation time 93668220 ps
CPU time 2.65 seconds
Started Jul 16 04:54:24 PM PDT 24
Finished Jul 16 04:54:27 PM PDT 24
Peak memory 208976 kb
Host smart-0619e3cb-9661-4c8f-9cd7-08f4e44bcd79
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691103966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2691103966
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3250322331
Short name T138
Test name
Test status
Simulation time 84558095 ps
CPU time 1.02 seconds
Started Jul 16 04:54:28 PM PDT 24
Finished Jul 16 04:54:30 PM PDT 24
Peak memory 209068 kb
Host smart-f891866a-1e77-4a95-9367-936426bdcd56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250322331 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3250322331
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2613608211
Short name T146
Test name
Test status
Simulation time 50389669 ps
CPU time 1.94 seconds
Started Jul 16 04:54:12 PM PDT 24
Finished Jul 16 04:54:16 PM PDT 24
Peak memory 211344 kb
Host smart-80a97ea0-de67-4acb-b048-3a2ba26d553e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613608211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2613608211
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1700584197
Short name T962
Test name
Test status
Simulation time 24892098 ps
CPU time 1.14 seconds
Started Jul 16 04:54:37 PM PDT 24
Finished Jul 16 04:54:39 PM PDT 24
Peak memory 217468 kb
Host smart-187b638d-6e64-4c26-a340-d3acee4085f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700584197 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1700584197
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.4022567875
Short name T969
Test name
Test status
Simulation time 18404286 ps
CPU time 1.21 seconds
Started Jul 16 04:54:35 PM PDT 24
Finished Jul 16 04:54:37 PM PDT 24
Peak memory 208932 kb
Host smart-f3569c14-aef8-4558-b811-96930cba8d0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022567875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.4022567875
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2783824393
Short name T877
Test name
Test status
Simulation time 230696177 ps
CPU time 1.66 seconds
Started Jul 16 04:54:53 PM PDT 24
Finished Jul 16 04:54:57 PM PDT 24
Peak memory 211304 kb
Host smart-b315bb75-4ae7-4be6-80d6-24b5c3c77223
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783824393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2783824393
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1731027167
Short name T976
Test name
Test status
Simulation time 107137844 ps
CPU time 3.1 seconds
Started Jul 16 04:54:24 PM PDT 24
Finished Jul 16 04:54:28 PM PDT 24
Peak memory 217404 kb
Host smart-7061acaa-2e2f-4894-b920-e4a8981c2a95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731027167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1731027167
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.323959789
Short name T125
Test name
Test status
Simulation time 480430224 ps
CPU time 1.88 seconds
Started Jul 16 04:54:48 PM PDT 24
Finished Jul 16 04:54:51 PM PDT 24
Peak memory 222072 kb
Host smart-b06629a5-e496-4762-9830-2cf37d426230
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323959789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.323959789
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1195081199
Short name T934
Test name
Test status
Simulation time 32175753 ps
CPU time 1.77 seconds
Started Jul 16 04:54:47 PM PDT 24
Finished Jul 16 04:54:49 PM PDT 24
Peak memory 217456 kb
Host smart-97eeea8c-77f2-4e55-a7bf-32ef7be20eaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195081199 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1195081199
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2824955643
Short name T928
Test name
Test status
Simulation time 27584212 ps
CPU time 0.94 seconds
Started Jul 16 04:54:46 PM PDT 24
Finished Jul 16 04:54:48 PM PDT 24
Peak memory 208696 kb
Host smart-833cc3fb-c51c-49e3-a8af-8b636f778b8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824955643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2824955643
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1005441881
Short name T876
Test name
Test status
Simulation time 60783704 ps
CPU time 1.14 seconds
Started Jul 16 04:55:02 PM PDT 24
Finished Jul 16 04:55:07 PM PDT 24
Peak memory 209252 kb
Host smart-3c17ba8c-daaa-4469-9451-27a99a9321ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005441881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1005441881
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1559955940
Short name T951
Test name
Test status
Simulation time 138108364 ps
CPU time 2.37 seconds
Started Jul 16 04:54:44 PM PDT 24
Finished Jul 16 04:54:48 PM PDT 24
Peak memory 217352 kb
Host smart-242f8071-8eb0-4f67-9ea4-d67bb8c4627b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559955940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1559955940
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3905357369
Short name T111
Test name
Test status
Simulation time 553055266 ps
CPU time 2.04 seconds
Started Jul 16 04:54:30 PM PDT 24
Finished Jul 16 04:54:33 PM PDT 24
Peak memory 221884 kb
Host smart-a9715ec9-de33-43cc-b3d5-c325697e1e5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905357369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3905357369
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3241265647
Short name T960
Test name
Test status
Simulation time 47687305 ps
CPU time 1.23 seconds
Started Jul 16 04:54:43 PM PDT 24
Finished Jul 16 04:54:45 PM PDT 24
Peak memory 217520 kb
Host smart-1b58bd73-935a-4183-80a8-24ea9c005297
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241265647 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3241265647
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.73561327
Short name T914
Test name
Test status
Simulation time 12136881 ps
CPU time 0.81 seconds
Started Jul 16 04:54:39 PM PDT 24
Finished Jul 16 04:54:41 PM PDT 24
Peak memory 209020 kb
Host smart-80750e65-c7a0-4bff-afcf-e59968512660
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73561327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.73561327
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3227999446
Short name T938
Test name
Test status
Simulation time 35242597 ps
CPU time 1.18 seconds
Started Jul 16 04:54:45 PM PDT 24
Finished Jul 16 04:54:47 PM PDT 24
Peak memory 209248 kb
Host smart-f635382e-e84f-49c3-883c-0a489cb851a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227999446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3227999446
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3383940390
Short name T113
Test name
Test status
Simulation time 212383315 ps
CPU time 3.42 seconds
Started Jul 16 04:54:25 PM PDT 24
Finished Jul 16 04:54:29 PM PDT 24
Peak memory 217572 kb
Host smart-c9f4c6b9-8ee9-41c5-86f3-6376baaa8381
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383940390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3383940390
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2283406254
Short name T981
Test name
Test status
Simulation time 22726402 ps
CPU time 1.11 seconds
Started Jul 16 04:54:52 PM PDT 24
Finished Jul 16 04:54:54 PM PDT 24
Peak memory 218428 kb
Host smart-916f74e8-beac-4ba9-8557-8b978b597afc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283406254 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2283406254
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.790814466
Short name T923
Test name
Test status
Simulation time 85506614 ps
CPU time 1.39 seconds
Started Jul 16 04:54:44 PM PDT 24
Finished Jul 16 04:54:47 PM PDT 24
Peak memory 209248 kb
Host smart-7e6e579a-1a77-4148-9827-4acd32cfefc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790814466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.790814466
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3934746000
Short name T947
Test name
Test status
Simulation time 380453185 ps
CPU time 3.77 seconds
Started Jul 16 04:54:49 PM PDT 24
Finished Jul 16 04:54:53 PM PDT 24
Peak memory 217364 kb
Host smart-6b844d2a-abd7-41b7-a0c4-0e414dd724a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934746000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3934746000
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3991494214
Short name T102
Test name
Test status
Simulation time 77732919 ps
CPU time 2.07 seconds
Started Jul 16 04:54:25 PM PDT 24
Finished Jul 16 04:54:28 PM PDT 24
Peak memory 221788 kb
Host smart-9c6b1cbd-0105-460c-906f-9e002d12bc44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991494214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3991494214
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1160894527
Short name T966
Test name
Test status
Simulation time 68676754 ps
CPU time 1.25 seconds
Started Jul 16 04:54:49 PM PDT 24
Finished Jul 16 04:54:51 PM PDT 24
Peak memory 219020 kb
Host smart-1d574659-52f8-4829-8c64-592df82a4c3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160894527 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1160894527
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3759322944
Short name T147
Test name
Test status
Simulation time 40799923 ps
CPU time 0.87 seconds
Started Jul 16 04:54:58 PM PDT 24
Finished Jul 16 04:55:04 PM PDT 24
Peak memory 209108 kb
Host smart-04399174-2f67-410f-9b9f-4833278ce2d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759322944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3759322944
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1538466287
Short name T944
Test name
Test status
Simulation time 177431832 ps
CPU time 2.09 seconds
Started Jul 16 04:54:47 PM PDT 24
Finished Jul 16 04:54:50 PM PDT 24
Peak memory 211076 kb
Host smart-c84eab4d-e82c-40eb-8b91-0453a323b652
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538466287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.1538466287
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2399072774
Short name T98
Test name
Test status
Simulation time 258579427 ps
CPU time 2.95 seconds
Started Jul 16 04:55:00 PM PDT 24
Finished Jul 16 04:55:08 PM PDT 24
Peak memory 217372 kb
Host smart-f1692329-96be-4afa-bd5a-8ffaf64e83d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399072774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2399072774
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2976777324
Short name T886
Test name
Test status
Simulation time 36425824 ps
CPU time 1.79 seconds
Started Jul 16 04:54:58 PM PDT 24
Finished Jul 16 04:55:04 PM PDT 24
Peak memory 219012 kb
Host smart-70b04d6c-2753-459e-9068-fcf5c0cef515
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976777324 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2976777324
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3430619894
Short name T180
Test name
Test status
Simulation time 12401671 ps
CPU time 1.02 seconds
Started Jul 16 04:54:36 PM PDT 24
Finished Jul 16 04:54:38 PM PDT 24
Peak memory 209136 kb
Host smart-0dd46ff0-d5f5-44cf-8fb2-cff28c2a2b8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430619894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3430619894
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1699887255
Short name T940
Test name
Test status
Simulation time 298314658 ps
CPU time 1.29 seconds
Started Jul 16 04:54:30 PM PDT 24
Finished Jul 16 04:54:31 PM PDT 24
Peak memory 209136 kb
Host smart-8d28f4fc-c0d6-4ba9-b70c-b83c927e539b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699887255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1699887255
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1674789187
Short name T936
Test name
Test status
Simulation time 385845020 ps
CPU time 3.94 seconds
Started Jul 16 04:54:36 PM PDT 24
Finished Jul 16 04:54:41 PM PDT 24
Peak memory 217348 kb
Host smart-a9d36e9b-4845-44c3-aff8-7fd6fc69356c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674789187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1674789187
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1642668365
Short name T875
Test name
Test status
Simulation time 62999192 ps
CPU time 1.18 seconds
Started Jul 16 04:54:34 PM PDT 24
Finished Jul 16 04:54:41 PM PDT 24
Peak memory 217328 kb
Host smart-4a63d62a-4796-4b1c-8274-83a46ecdd74a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642668365 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1642668365
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1530438244
Short name T926
Test name
Test status
Simulation time 34479076 ps
CPU time 0.84 seconds
Started Jul 16 04:54:26 PM PDT 24
Finished Jul 16 04:54:27 PM PDT 24
Peak memory 209092 kb
Host smart-f296d1df-eff8-4cfd-9cbf-16661f7084df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530438244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1530438244
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2336333012
Short name T950
Test name
Test status
Simulation time 28191620 ps
CPU time 1.49 seconds
Started Jul 16 04:54:35 PM PDT 24
Finished Jul 16 04:54:38 PM PDT 24
Peak memory 209156 kb
Host smart-efcb2129-5aba-4894-99da-657185b2055f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336333012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2336333012
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.931562484
Short name T939
Test name
Test status
Simulation time 239632855 ps
CPU time 2.57 seconds
Started Jul 16 04:54:44 PM PDT 24
Finished Jul 16 04:54:47 PM PDT 24
Peak memory 217564 kb
Host smart-68fbf279-db50-4815-87bf-e628524589b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931562484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.931562484
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2901349195
Short name T884
Test name
Test status
Simulation time 1022732952 ps
CPU time 2.58 seconds
Started Jul 16 04:54:39 PM PDT 24
Finished Jul 16 04:54:43 PM PDT 24
Peak memory 217240 kb
Host smart-4b39df7e-7b01-48a0-8581-fa1bc58193dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901349195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2901349195
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2215933442
Short name T933
Test name
Test status
Simulation time 93700927 ps
CPU time 1.8 seconds
Started Jul 16 04:54:44 PM PDT 24
Finished Jul 16 04:54:47 PM PDT 24
Peak memory 218892 kb
Host smart-aa2330e4-d371-49ad-a39a-475d22c28125
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215933442 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2215933442
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3202362428
Short name T952
Test name
Test status
Simulation time 46799353 ps
CPU time 0.91 seconds
Started Jul 16 04:54:34 PM PDT 24
Finished Jul 16 04:54:36 PM PDT 24
Peak memory 208948 kb
Host smart-5c94e45e-9b37-42f6-a460-9cadd9119f2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202362428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3202362428
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.4293968797
Short name T888
Test name
Test status
Simulation time 98158172 ps
CPU time 1.1 seconds
Started Jul 16 04:54:34 PM PDT 24
Finished Jul 16 04:54:36 PM PDT 24
Peak memory 209252 kb
Host smart-a0d40a08-1bb8-4bab-ba03-fe36a2e92f11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293968797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.4293968797
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4116777644
Short name T891
Test name
Test status
Simulation time 25990771 ps
CPU time 1.77 seconds
Started Jul 16 04:54:42 PM PDT 24
Finished Jul 16 04:54:45 PM PDT 24
Peak memory 217392 kb
Host smart-0bf39fd8-a85d-4be8-860e-34703c39b5e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116777644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.4116777644
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3874174614
Short name T128
Test name
Test status
Simulation time 226728328 ps
CPU time 1.91 seconds
Started Jul 16 04:54:32 PM PDT 24
Finished Jul 16 04:54:35 PM PDT 24
Peak memory 221540 kb
Host smart-2b5dc7ea-73b5-4d61-9a94-e9e593cad486
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874174614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3874174614
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.337569928
Short name T908
Test name
Test status
Simulation time 22666581 ps
CPU time 1.1 seconds
Started Jul 16 04:54:34 PM PDT 24
Finished Jul 16 04:54:36 PM PDT 24
Peak memory 220200 kb
Host smart-6be6af4b-ce0c-4e30-8f45-f648b27754f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337569928 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.337569928
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1971218160
Short name T176
Test name
Test status
Simulation time 14167051 ps
CPU time 0.84 seconds
Started Jul 16 04:54:32 PM PDT 24
Finished Jul 16 04:54:34 PM PDT 24
Peak memory 208800 kb
Host smart-dbe58781-ef03-41cb-b434-1f5512829ef0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971218160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1971218160
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.772007937
Short name T186
Test name
Test status
Simulation time 28824331 ps
CPU time 1.42 seconds
Started Jul 16 04:54:34 PM PDT 24
Finished Jul 16 04:54:36 PM PDT 24
Peak memory 209124 kb
Host smart-b82d613e-9c26-437b-9dd9-fd9ff22d0e53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772007937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.772007937
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3141408637
Short name T910
Test name
Test status
Simulation time 56869311 ps
CPU time 2.46 seconds
Started Jul 16 04:54:43 PM PDT 24
Finished Jul 16 04:54:47 PM PDT 24
Peak memory 217340 kb
Host smart-05b2232e-68fb-48d4-a19f-fcd67a68e312
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141408637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3141408637
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2529358849
Short name T870
Test name
Test status
Simulation time 23033087 ps
CPU time 1.54 seconds
Started Jul 16 04:54:34 PM PDT 24
Finished Jul 16 04:54:36 PM PDT 24
Peak memory 221580 kb
Host smart-5d4a6cc0-6586-4c3e-8ede-6ebee3c7c775
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529358849 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2529358849
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.240046441
Short name T937
Test name
Test status
Simulation time 16223272 ps
CPU time 0.86 seconds
Started Jul 16 04:54:27 PM PDT 24
Finished Jul 16 04:54:29 PM PDT 24
Peak memory 209152 kb
Host smart-30fb9cfe-a4d2-465b-b5f4-de3a66f9f066
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240046441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.240046441
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3537944589
Short name T906
Test name
Test status
Simulation time 93675394 ps
CPU time 1.39 seconds
Started Jul 16 04:54:43 PM PDT 24
Finished Jul 16 04:54:46 PM PDT 24
Peak memory 209140 kb
Host smart-b369ab43-fafa-4076-8446-8b9ca30a5a46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537944589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3537944589
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3202222098
Short name T100
Test name
Test status
Simulation time 46826137 ps
CPU time 2.05 seconds
Started Jul 16 04:54:45 PM PDT 24
Finished Jul 16 04:54:48 PM PDT 24
Peak memory 217776 kb
Host smart-ddc3c4f7-0609-4304-8dba-2e9f82a88b4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202222098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3202222098
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1728773419
Short name T124
Test name
Test status
Simulation time 59580455 ps
CPU time 1.9 seconds
Started Jul 16 04:54:35 PM PDT 24
Finished Jul 16 04:54:37 PM PDT 24
Peak memory 221428 kb
Host smart-d9fc088c-b957-44dc-8c7e-77d1bf24ea90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728773419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1728773419
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3215695822
Short name T178
Test name
Test status
Simulation time 19010185 ps
CPU time 1.43 seconds
Started Jul 16 04:54:18 PM PDT 24
Finished Jul 16 04:54:20 PM PDT 24
Peak memory 209164 kb
Host smart-a688a2aa-452f-45f6-b659-96104ff5b472
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215695822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3215695822
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4072219936
Short name T139
Test name
Test status
Simulation time 135358361 ps
CPU time 1.81 seconds
Started Jul 16 04:54:14 PM PDT 24
Finished Jul 16 04:54:18 PM PDT 24
Peak memory 209192 kb
Host smart-198713d6-2191-40f3-ac6f-2601288795a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072219936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.4072219936
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1670593054
Short name T174
Test name
Test status
Simulation time 68375334 ps
CPU time 0.86 seconds
Started Jul 16 04:54:16 PM PDT 24
Finished Jul 16 04:54:19 PM PDT 24
Peak memory 209748 kb
Host smart-36d05041-fc9d-4761-9321-ec5093c3d78d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670593054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1670593054
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1847538634
Short name T930
Test name
Test status
Simulation time 65296608 ps
CPU time 1.29 seconds
Started Jul 16 04:54:17 PM PDT 24
Finished Jul 16 04:54:20 PM PDT 24
Peak memory 217436 kb
Host smart-085c65a1-b3f0-4b12-8181-27a65f5e1cae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847538634 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1847538634
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.4173341551
Short name T942
Test name
Test status
Simulation time 16090433 ps
CPU time 1.06 seconds
Started Jul 16 04:54:16 PM PDT 24
Finished Jul 16 04:54:19 PM PDT 24
Peak memory 208868 kb
Host smart-9094c5c1-8545-44eb-bd25-aea6a802f23e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173341551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.4173341551
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.549374345
Short name T135
Test name
Test status
Simulation time 16807949 ps
CPU time 1.08 seconds
Started Jul 16 04:54:35 PM PDT 24
Finished Jul 16 04:54:37 PM PDT 24
Peak memory 208972 kb
Host smart-1053a8e8-e648-4105-bb48-32d3589dfdd3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549374345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.549374345
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4284751211
Short name T885
Test name
Test status
Simulation time 187253848 ps
CPU time 2.99 seconds
Started Jul 16 04:54:14 PM PDT 24
Finished Jul 16 04:54:19 PM PDT 24
Peak memory 208864 kb
Host smart-de2516a1-5ce8-4235-aae6-e9c14c8bd2d8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284751211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.4284751211
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.322727332
Short name T887
Test name
Test status
Simulation time 703690815 ps
CPU time 4.74 seconds
Started Jul 16 04:54:21 PM PDT 24
Finished Jul 16 04:54:26 PM PDT 24
Peak memory 208864 kb
Host smart-ab429e29-b8c3-4215-8720-49c8a985f394
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322727332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.322727332
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.760648203
Short name T882
Test name
Test status
Simulation time 341135806 ps
CPU time 2.82 seconds
Started Jul 16 04:54:25 PM PDT 24
Finished Jul 16 04:54:34 PM PDT 24
Peak memory 210740 kb
Host smart-b5eb4508-49b8-48d3-b7af-36fed29ecea7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760648203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.760648203
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2663807625
Short name T972
Test name
Test status
Simulation time 52324842 ps
CPU time 1.24 seconds
Started Jul 16 04:54:17 PM PDT 24
Finished Jul 16 04:54:20 PM PDT 24
Peak memory 209008 kb
Host smart-32b88ddb-954e-4e98-95ed-705e83869431
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663807625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2663807625
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4114149461
Short name T968
Test name
Test status
Simulation time 45381507 ps
CPU time 1.51 seconds
Started Jul 16 04:54:15 PM PDT 24
Finished Jul 16 04:54:18 PM PDT 24
Peak memory 211276 kb
Host smart-0068f0ca-a573-4cee-8221-4f2d57356587
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114149461 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.4114149461
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3163709848
Short name T874
Test name
Test status
Simulation time 51560474 ps
CPU time 0.99 seconds
Started Jul 16 04:54:41 PM PDT 24
Finished Jul 16 04:54:43 PM PDT 24
Peak memory 209196 kb
Host smart-4c83b353-ac56-43af-b8fd-f0abbb1b2c38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163709848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3163709848
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1970452572
Short name T963
Test name
Test status
Simulation time 151637636 ps
CPU time 2.55 seconds
Started Jul 16 04:54:14 PM PDT 24
Finished Jul 16 04:54:18 PM PDT 24
Peak memory 218376 kb
Host smart-dd5cdcd9-b732-4bf5-a055-66ab4701174b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970452572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1970452572
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1034308356
Short name T920
Test name
Test status
Simulation time 18529934 ps
CPU time 1.2 seconds
Started Jul 16 04:54:17 PM PDT 24
Finished Jul 16 04:54:20 PM PDT 24
Peak memory 209128 kb
Host smart-475ce910-d99d-4372-93b5-7e36ebf20204
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034308356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1034308356
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2829263281
Short name T898
Test name
Test status
Simulation time 41727520 ps
CPU time 1.33 seconds
Started Jul 16 04:54:16 PM PDT 24
Finished Jul 16 04:54:19 PM PDT 24
Peak memory 208160 kb
Host smart-28aa44ff-9659-475b-81df-b7d63b6e802d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829263281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2829263281
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3753828220
Short name T955
Test name
Test status
Simulation time 30830566 ps
CPU time 1.18 seconds
Started Jul 16 04:54:22 PM PDT 24
Finished Jul 16 04:54:23 PM PDT 24
Peak memory 211440 kb
Host smart-d83506c6-9871-46c2-acdb-c024f52c0b57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753828220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3753828220
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.78820423
Short name T918
Test name
Test status
Simulation time 53036243 ps
CPU time 1.24 seconds
Started Jul 16 04:54:16 PM PDT 24
Finished Jul 16 04:54:19 PM PDT 24
Peak memory 217416 kb
Host smart-f5b68767-120b-4d2a-8db9-37f2881bc962
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78820423 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.78820423
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.295732662
Short name T977
Test name
Test status
Simulation time 89601839 ps
CPU time 1.79 seconds
Started Jul 16 04:54:16 PM PDT 24
Finished Jul 16 04:54:20 PM PDT 24
Peak memory 207700 kb
Host smart-949688fd-95f3-45dc-ac94-eaaa3347faf2
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295732662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.295732662
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3772519679
Short name T911
Test name
Test status
Simulation time 2337179244 ps
CPU time 7.02 seconds
Started Jul 16 04:54:15 PM PDT 24
Finished Jul 16 04:54:24 PM PDT 24
Peak memory 208956 kb
Host smart-d1b8c1da-1602-423f-9d77-2549bfb07af2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772519679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3772519679
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3712335035
Short name T890
Test name
Test status
Simulation time 1915627781 ps
CPU time 21.21 seconds
Started Jul 16 04:54:15 PM PDT 24
Finished Jul 16 04:54:38 PM PDT 24
Peak memory 208912 kb
Host smart-599ae1c1-518a-47f2-8cd4-4035a8c51f43
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712335035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3712335035
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3641269668
Short name T948
Test name
Test status
Simulation time 2415034681 ps
CPU time 4 seconds
Started Jul 16 04:54:14 PM PDT 24
Finished Jul 16 04:54:20 PM PDT 24
Peak memory 210852 kb
Host smart-cccf3ecb-e189-4e54-8cfe-d7e532fdda77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641269668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3641269668
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1865939898
Short name T894
Test name
Test status
Simulation time 480070116 ps
CPU time 1.98 seconds
Started Jul 16 04:54:15 PM PDT 24
Finished Jul 16 04:54:19 PM PDT 24
Peak memory 218492 kb
Host smart-109c5ea8-e352-463d-9038-91ed10eeda06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186593
9898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1865939898
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1924558587
Short name T982
Test name
Test status
Simulation time 424560611 ps
CPU time 1.73 seconds
Started Jul 16 04:54:15 PM PDT 24
Finished Jul 16 04:54:19 PM PDT 24
Peak memory 208192 kb
Host smart-47097a53-d24f-443d-a6d4-be76c7277a06
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924558587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1924558587
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1886250807
Short name T137
Test name
Test status
Simulation time 54129018 ps
CPU time 0.97 seconds
Started Jul 16 04:54:19 PM PDT 24
Finished Jul 16 04:54:20 PM PDT 24
Peak memory 209224 kb
Host smart-8db2d580-2a63-4c2c-b544-573220988c3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886250807 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1886250807
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.4285502924
Short name T971
Test name
Test status
Simulation time 60035337 ps
CPU time 1.13 seconds
Started Jul 16 04:54:22 PM PDT 24
Finished Jul 16 04:54:24 PM PDT 24
Peak memory 209140 kb
Host smart-cd429bfd-1843-40cd-8231-42bf99dad3b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285502924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.4285502924
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2809565496
Short name T117
Test name
Test status
Simulation time 1328709381 ps
CPU time 2.82 seconds
Started Jul 16 04:54:14 PM PDT 24
Finished Jul 16 04:54:18 PM PDT 24
Peak memory 217376 kb
Host smart-d63c8b6b-3e4b-46ec-a865-e339f14188b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809565496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2809565496
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3164058760
Short name T904
Test name
Test status
Simulation time 60344635 ps
CPU time 2.53 seconds
Started Jul 16 04:54:16 PM PDT 24
Finished Jul 16 04:54:21 PM PDT 24
Peak memory 217556 kb
Host smart-be9261ae-38e2-4f78-a848-f3b411e47d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164058760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3164058760
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1809999452
Short name T953
Test name
Test status
Simulation time 129488089 ps
CPU time 1.71 seconds
Started Jul 16 04:54:52 PM PDT 24
Finished Jul 16 04:54:55 PM PDT 24
Peak memory 209140 kb
Host smart-cdc2eaa9-6a67-428d-bcce-409286e2e96c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809999452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1809999452
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4120432687
Short name T896
Test name
Test status
Simulation time 114535557 ps
CPU time 1.7 seconds
Started Jul 16 04:54:25 PM PDT 24
Finished Jul 16 04:54:27 PM PDT 24
Peak memory 209064 kb
Host smart-f9fdf836-83a0-4644-a59a-26eb58c835a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120432687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.4120432687
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1506345687
Short name T175
Test name
Test status
Simulation time 58903309 ps
CPU time 1.05 seconds
Started Jul 16 04:54:34 PM PDT 24
Finished Jul 16 04:54:36 PM PDT 24
Peak memory 210288 kb
Host smart-162c5a64-82ae-4f5b-b376-cfefc37064a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506345687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1506345687
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.24991068
Short name T126
Test name
Test status
Simulation time 38582842 ps
CPU time 1 seconds
Started Jul 16 04:54:39 PM PDT 24
Finished Jul 16 04:54:41 PM PDT 24
Peak memory 218368 kb
Host smart-17db03b4-6634-4dd3-8770-5cab03be0a46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24991068 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.24991068
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3780536224
Short name T865
Test name
Test status
Simulation time 36208429 ps
CPU time 0.94 seconds
Started Jul 16 04:54:37 PM PDT 24
Finished Jul 16 04:54:39 PM PDT 24
Peak memory 209160 kb
Host smart-ca87e08a-3c35-4325-ac6e-74ee120d3d1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780536224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3780536224
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3506003360
Short name T924
Test name
Test status
Simulation time 251104834 ps
CPU time 1.14 seconds
Started Jul 16 04:54:38 PM PDT 24
Finished Jul 16 04:54:40 PM PDT 24
Peak memory 208980 kb
Host smart-8cd5c769-2d94-4759-b259-f436ff1f2a85
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506003360 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3506003360
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2307046747
Short name T915
Test name
Test status
Simulation time 418617717 ps
CPU time 2.88 seconds
Started Jul 16 04:54:33 PM PDT 24
Finished Jul 16 04:54:36 PM PDT 24
Peak memory 208892 kb
Host smart-724a9bca-39c1-4196-9a9f-684fbd1b1594
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307046747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2307046747
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.478007157
Short name T909
Test name
Test status
Simulation time 973262328 ps
CPU time 23.72 seconds
Started Jul 16 04:54:38 PM PDT 24
Finished Jul 16 04:55:03 PM PDT 24
Peak memory 209132 kb
Host smart-9742939b-d350-4aa8-afa4-90dad809ba9d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478007157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.478007157
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2376288156
Short name T881
Test name
Test status
Simulation time 243503821 ps
CPU time 1.9 seconds
Started Jul 16 04:54:17 PM PDT 24
Finished Jul 16 04:54:20 PM PDT 24
Peak memory 210480 kb
Host smart-44ca606b-a680-498b-b938-fc87e7ffc5b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376288156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2376288156
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4062737717
Short name T166
Test name
Test status
Simulation time 1222336744 ps
CPU time 2.83 seconds
Started Jul 16 04:54:50 PM PDT 24
Finished Jul 16 04:54:53 PM PDT 24
Peak memory 217492 kb
Host smart-b7888f73-c9b1-42d6-b528-8367ea3bc8bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406273
7717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4062737717
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2943526232
Short name T132
Test name
Test status
Simulation time 34641953 ps
CPU time 1.21 seconds
Started Jul 16 04:54:17 PM PDT 24
Finished Jul 16 04:54:20 PM PDT 24
Peak memory 209176 kb
Host smart-71df312b-1dca-4d58-8680-21333af3d7d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943526232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2943526232
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3510691420
Short name T106
Test name
Test status
Simulation time 44720043 ps
CPU time 1.36 seconds
Started Jul 16 04:54:42 PM PDT 24
Finished Jul 16 04:54:44 PM PDT 24
Peak memory 209164 kb
Host smart-2188c25f-b983-4f03-aa81-88ca23f289c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510691420 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3510691420
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3129797985
Short name T185
Test name
Test status
Simulation time 16549572 ps
CPU time 1.02 seconds
Started Jul 16 04:54:31 PM PDT 24
Finished Jul 16 04:54:33 PM PDT 24
Peak memory 209172 kb
Host smart-66e216c2-03fd-4a85-bdf1-c4b506eae27d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129797985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3129797985
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3762062647
Short name T907
Test name
Test status
Simulation time 60066643 ps
CPU time 2.29 seconds
Started Jul 16 04:54:25 PM PDT 24
Finished Jul 16 04:54:28 PM PDT 24
Peak memory 217576 kb
Host smart-bf30820c-0582-441b-a89f-45e9551fd0fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762062647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3762062647
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2445306747
Short name T110
Test name
Test status
Simulation time 108622326 ps
CPU time 2.16 seconds
Started Jul 16 04:54:25 PM PDT 24
Finished Jul 16 04:54:28 PM PDT 24
Peak memory 219532 kb
Host smart-4009473c-d429-4052-b7c1-4155364aa7b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445306747 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2445306747
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.255502049
Short name T107
Test name
Test status
Simulation time 54685709 ps
CPU time 1.04 seconds
Started Jul 16 04:54:32 PM PDT 24
Finished Jul 16 04:54:34 PM PDT 24
Peak memory 209152 kb
Host smart-d7386e83-7696-41c1-87e7-28cbf54f21bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255502049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.255502049
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1430014143
Short name T935
Test name
Test status
Simulation time 112777236 ps
CPU time 1.13 seconds
Started Jul 16 04:54:52 PM PDT 24
Finished Jul 16 04:54:55 PM PDT 24
Peak memory 209120 kb
Host smart-a2488f76-82b9-4514-b668-1a8859b35b60
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430014143 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1430014143
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.487685112
Short name T979
Test name
Test status
Simulation time 1242948907 ps
CPU time 23.46 seconds
Started Jul 16 04:54:30 PM PDT 24
Finished Jul 16 04:54:54 PM PDT 24
Peak memory 208948 kb
Host smart-ac9bcefb-766c-4c13-9f9a-136bb3ddc821
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487685112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.487685112
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4069124135
Short name T975
Test name
Test status
Simulation time 6783078404 ps
CPU time 13.6 seconds
Started Jul 16 04:54:32 PM PDT 24
Finished Jul 16 04:54:46 PM PDT 24
Peak memory 209188 kb
Host smart-47858006-d0e9-4b17-9a44-fcc6a8289840
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069124135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.4069124135
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.64415005
Short name T945
Test name
Test status
Simulation time 122659931 ps
CPU time 3.58 seconds
Started Jul 16 04:54:36 PM PDT 24
Finished Jul 16 04:54:41 PM PDT 24
Peak memory 210820 kb
Host smart-64fc812c-05e3-4ccd-b1f8-8d5d4506b443
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64415005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.64415005
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2876772960
Short name T878
Test name
Test status
Simulation time 90686599 ps
CPU time 3.06 seconds
Started Jul 16 04:54:37 PM PDT 24
Finished Jul 16 04:54:40 PM PDT 24
Peak memory 217400 kb
Host smart-2e35cfd2-3e04-4bc4-b7cb-ff6bde5b971f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287677
2960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2876772960
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3499267001
Short name T913
Test name
Test status
Simulation time 65379800 ps
CPU time 2.07 seconds
Started Jul 16 04:54:26 PM PDT 24
Finished Jul 16 04:54:29 PM PDT 24
Peak memory 208364 kb
Host smart-e70691cc-7fe3-404c-abf1-cf9650fa5ad1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499267001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3499267001
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.608671441
Short name T967
Test name
Test status
Simulation time 97622142 ps
CPU time 1.43 seconds
Started Jul 16 04:54:45 PM PDT 24
Finished Jul 16 04:54:48 PM PDT 24
Peak memory 209152 kb
Host smart-4249d4e1-1247-4eee-bfa2-f2843e788dc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608671441 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.608671441
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2384394314
Short name T899
Test name
Test status
Simulation time 36486293 ps
CPU time 1.52 seconds
Started Jul 16 04:54:37 PM PDT 24
Finished Jul 16 04:54:39 PM PDT 24
Peak memory 211184 kb
Host smart-a2615e7d-de8e-4839-a980-1c6b1573f06e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384394314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2384394314
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2453174077
Short name T958
Test name
Test status
Simulation time 103292147 ps
CPU time 2.63 seconds
Started Jul 16 04:54:30 PM PDT 24
Finished Jul 16 04:54:33 PM PDT 24
Peak memory 217260 kb
Host smart-74be7b67-42f1-4c98-9f29-58718eb86905
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453174077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2453174077
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.469032562
Short name T131
Test name
Test status
Simulation time 61342936 ps
CPU time 2.12 seconds
Started Jul 16 04:54:35 PM PDT 24
Finished Jul 16 04:54:39 PM PDT 24
Peak memory 221776 kb
Host smart-f6095185-dd4e-4ace-92b0-696aec2925b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469032562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.469032562
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1266963032
Short name T902
Test name
Test status
Simulation time 125039802 ps
CPU time 1.43 seconds
Started Jul 16 04:54:41 PM PDT 24
Finished Jul 16 04:54:43 PM PDT 24
Peak memory 218384 kb
Host smart-e4a41c60-7d28-4d24-a3c1-2672a6821e01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266963032 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1266963032
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3739544785
Short name T181
Test name
Test status
Simulation time 96502731 ps
CPU time 1.05 seconds
Started Jul 16 04:54:48 PM PDT 24
Finished Jul 16 04:54:50 PM PDT 24
Peak memory 208976 kb
Host smart-1c93bc5d-b798-4b00-b3da-32e462ebbde7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739544785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3739544785
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3172231392
Short name T883
Test name
Test status
Simulation time 22816942 ps
CPU time 0.9 seconds
Started Jul 16 04:54:42 PM PDT 24
Finished Jul 16 04:54:44 PM PDT 24
Peak memory 208952 kb
Host smart-6ac1d342-7f6e-496f-b1a8-8e6c3afa3b69
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172231392 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3172231392
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.231603254
Short name T912
Test name
Test status
Simulation time 478744642 ps
CPU time 10.73 seconds
Started Jul 16 04:54:25 PM PDT 24
Finished Jul 16 04:54:36 PM PDT 24
Peak memory 207596 kb
Host smart-2856ba8e-e566-4b0c-a196-4f86a408e8a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231603254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.231603254
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.53268301
Short name T903
Test name
Test status
Simulation time 1796430552 ps
CPU time 27.29 seconds
Started Jul 16 04:54:33 PM PDT 24
Finished Jul 16 04:55:01 PM PDT 24
Peak memory 209012 kb
Host smart-755c2a8f-38d2-4144-8dd3-ba24bc28b96e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53268301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.53268301
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3961775861
Short name T133
Test name
Test status
Simulation time 818508633 ps
CPU time 3 seconds
Started Jul 16 04:54:31 PM PDT 24
Finished Jul 16 04:54:35 PM PDT 24
Peak memory 210728 kb
Host smart-d5793b4e-f826-4f77-8ebd-445382a4cbba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961775861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.3961775861
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3399179133
Short name T959
Test name
Test status
Simulation time 624046372 ps
CPU time 2.9 seconds
Started Jul 16 04:54:52 PM PDT 24
Finished Jul 16 04:54:57 PM PDT 24
Peak memory 217552 kb
Host smart-2a9fafbf-516c-4d78-943e-6c1df37b04cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339917
9133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3399179133
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.503709864
Short name T901
Test name
Test status
Simulation time 118977987 ps
CPU time 3.36 seconds
Started Jul 16 04:54:26 PM PDT 24
Finished Jul 16 04:54:30 PM PDT 24
Peak memory 209016 kb
Host smart-2a7269d6-412b-482c-aaf3-79af338f0ee4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503709864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.503709864
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4177394628
Short name T872
Test name
Test status
Simulation time 27461683 ps
CPU time 1.04 seconds
Started Jul 16 04:54:32 PM PDT 24
Finished Jul 16 04:54:34 PM PDT 24
Peak memory 209176 kb
Host smart-56d68f18-4375-4b66-bd26-6b7f6f2cb6f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177394628 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.4177394628
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2333681201
Short name T921
Test name
Test status
Simulation time 27527383 ps
CPU time 1.03 seconds
Started Jul 16 04:54:31 PM PDT 24
Finished Jul 16 04:54:32 PM PDT 24
Peak memory 209192 kb
Host smart-080d70f9-6314-4117-9f5e-e2367d990c6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333681201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2333681201
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.4162041047
Short name T973
Test name
Test status
Simulation time 111695488 ps
CPU time 4.75 seconds
Started Jul 16 04:54:42 PM PDT 24
Finished Jul 16 04:54:47 PM PDT 24
Peak memory 217416 kb
Host smart-d1921bc7-99a6-4e2d-a29f-81588dffc7dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162041047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.4162041047
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1230411832
Short name T892
Test name
Test status
Simulation time 70836496 ps
CPU time 1.19 seconds
Started Jul 16 04:54:25 PM PDT 24
Finished Jul 16 04:54:26 PM PDT 24
Peak memory 217632 kb
Host smart-416f874a-bc41-4f23-86f1-60ef368888f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230411832 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1230411832
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.163386842
Short name T916
Test name
Test status
Simulation time 58711597 ps
CPU time 0.87 seconds
Started Jul 16 04:54:40 PM PDT 24
Finished Jul 16 04:54:42 PM PDT 24
Peak memory 209108 kb
Host smart-d1163e06-3adb-48db-b151-9b934cc7a837
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163386842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.163386842
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.178580512
Short name T863
Test name
Test status
Simulation time 222579128 ps
CPU time 1.2 seconds
Started Jul 16 04:54:41 PM PDT 24
Finished Jul 16 04:54:43 PM PDT 24
Peak memory 208972 kb
Host smart-6f0bc252-f064-48fa-8465-e6c72e60a629
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178580512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.lc_ctrl_jtag_alert_test.178580512
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2218071503
Short name T116
Test name
Test status
Simulation time 372420303 ps
CPU time 5.23 seconds
Started Jul 16 04:54:43 PM PDT 24
Finished Jul 16 04:54:49 PM PDT 24
Peak memory 208896 kb
Host smart-df0e29eb-875e-47c5-80f3-b370a929b5d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218071503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2218071503
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.4143526711
Short name T970
Test name
Test status
Simulation time 12343931941 ps
CPU time 12.39 seconds
Started Jul 16 04:54:26 PM PDT 24
Finished Jul 16 04:54:39 PM PDT 24
Peak memory 208544 kb
Host smart-0c089f7c-6fbc-4a61-a61a-0b543b2f65be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143526711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.4143526711
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3057283907
Short name T105
Test name
Test status
Simulation time 415565315 ps
CPU time 1.73 seconds
Started Jul 16 04:54:49 PM PDT 24
Finished Jul 16 04:54:52 PM PDT 24
Peak memory 210816 kb
Host smart-ed01df24-9d18-4c85-bc6b-782149e67b2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057283907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3057283907
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1589499661
Short name T946
Test name
Test status
Simulation time 88619286 ps
CPU time 3.56 seconds
Started Jul 16 04:54:36 PM PDT 24
Finished Jul 16 04:54:40 PM PDT 24
Peak memory 217428 kb
Host smart-92ec398b-80e3-4689-adb4-bd592d846c62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158949
9661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1589499661
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.844918632
Short name T965
Test name
Test status
Simulation time 187821582 ps
CPU time 2.28 seconds
Started Jul 16 04:54:39 PM PDT 24
Finished Jul 16 04:54:43 PM PDT 24
Peak memory 208332 kb
Host smart-9a42762e-3924-4297-89f7-c4b8126b013c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844918632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.844918632
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4046661315
Short name T974
Test name
Test status
Simulation time 44049266 ps
CPU time 1.1 seconds
Started Jul 16 04:54:35 PM PDT 24
Finished Jul 16 04:54:37 PM PDT 24
Peak memory 209164 kb
Host smart-8eb48270-976b-4ccb-8335-781766d51e68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046661315 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.4046661315
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3465543453
Short name T182
Test name
Test status
Simulation time 88053972 ps
CPU time 1.09 seconds
Started Jul 16 04:54:30 PM PDT 24
Finished Jul 16 04:54:31 PM PDT 24
Peak memory 209088 kb
Host smart-7109fcbc-91b5-4161-b392-191f189a1e52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465543453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3465543453
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4171589933
Short name T109
Test name
Test status
Simulation time 497268821 ps
CPU time 3.12 seconds
Started Jul 16 04:54:24 PM PDT 24
Finished Jul 16 04:54:28 PM PDT 24
Peak memory 217300 kb
Host smart-ae0ed820-6b6e-4200-9a77-61b64bdac6f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171589933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.4171589933
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3214370654
Short name T929
Test name
Test status
Simulation time 70447139 ps
CPU time 1.49 seconds
Started Jul 16 04:54:32 PM PDT 24
Finished Jul 16 04:54:34 PM PDT 24
Peak memory 217380 kb
Host smart-81a51b48-5694-47ba-b4c9-75853f56964a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214370654 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3214370654
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3748910479
Short name T179
Test name
Test status
Simulation time 18427814 ps
CPU time 1.13 seconds
Started Jul 16 04:54:33 PM PDT 24
Finished Jul 16 04:54:35 PM PDT 24
Peak memory 209032 kb
Host smart-cac16d1c-a71a-419a-b1db-1622fd047839
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748910479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3748910479
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2777119925
Short name T864
Test name
Test status
Simulation time 19521594 ps
CPU time 0.91 seconds
Started Jul 16 04:54:25 PM PDT 24
Finished Jul 16 04:54:26 PM PDT 24
Peak memory 207736 kb
Host smart-42c68e12-4d3a-4a0c-9b87-9acbb69d4b63
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777119925 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2777119925
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.31247177
Short name T134
Test name
Test status
Simulation time 561063315 ps
CPU time 6.18 seconds
Started Jul 16 04:54:26 PM PDT 24
Finished Jul 16 04:54:33 PM PDT 24
Peak memory 209008 kb
Host smart-fc8fe181-ae51-47a3-b553-1ef8fa7e6aa0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31247177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.lc_ctrl_jtag_csr_aliasing.31247177
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1587919302
Short name T871
Test name
Test status
Simulation time 4820040480 ps
CPU time 24.96 seconds
Started Jul 16 04:54:26 PM PDT 24
Finished Jul 16 04:54:51 PM PDT 24
Peak memory 209176 kb
Host smart-12dec4a0-abb4-44a9-b5d9-cb770db5afc8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587919302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1587919302
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.37596793
Short name T889
Test name
Test status
Simulation time 111641166 ps
CPU time 1.91 seconds
Started Jul 16 04:54:25 PM PDT 24
Finished Jul 16 04:54:28 PM PDT 24
Peak memory 210796 kb
Host smart-24261a02-a72d-43b1-b007-13ab7daa1d97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37596793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.37596793
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3262178666
Short name T956
Test name
Test status
Simulation time 87885095 ps
CPU time 2.87 seconds
Started Jul 16 04:54:35 PM PDT 24
Finished Jul 16 04:54:38 PM PDT 24
Peak memory 217360 kb
Host smart-9b445c98-7f90-4fd1-b8ef-5352ce4e478c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326217
8666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3262178666
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.71492657
Short name T941
Test name
Test status
Simulation time 88360897 ps
CPU time 1.22 seconds
Started Jul 16 04:54:36 PM PDT 24
Finished Jul 16 04:54:38 PM PDT 24
Peak memory 209204 kb
Host smart-9c4d3d25-4e50-4c37-9774-6d4c714e6b5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71492657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 8.lc_ctrl_jtag_csr_rw.71492657
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3124802839
Short name T978
Test name
Test status
Simulation time 45584005 ps
CPU time 1.28 seconds
Started Jul 16 04:54:40 PM PDT 24
Finished Jul 16 04:54:43 PM PDT 24
Peak memory 209160 kb
Host smart-cd069bec-6afa-4fa2-970b-cd8478100841
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124802839 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3124802839
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3719984689
Short name T867
Test name
Test status
Simulation time 42311125 ps
CPU time 1.28 seconds
Started Jul 16 04:54:38 PM PDT 24
Finished Jul 16 04:54:41 PM PDT 24
Peak memory 211152 kb
Host smart-36cf3527-9740-44fb-bf8f-b045198bfdda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719984689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3719984689
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.4144495699
Short name T927
Test name
Test status
Simulation time 203565964 ps
CPU time 3.95 seconds
Started Jul 16 04:54:31 PM PDT 24
Finished Jul 16 04:54:36 PM PDT 24
Peak memory 217356 kb
Host smart-96e886cc-e49d-48d2-8cd2-82c925291f21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144495699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.4144495699
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3960063720
Short name T108
Test name
Test status
Simulation time 35086375 ps
CPU time 1.51 seconds
Started Jul 16 04:54:44 PM PDT 24
Finished Jul 16 04:54:46 PM PDT 24
Peak memory 224600 kb
Host smart-e921c0f3-309b-4660-a5c6-43c04f380084
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960063720 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3960063720
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1597552961
Short name T170
Test name
Test status
Simulation time 16385833 ps
CPU time 0.87 seconds
Started Jul 16 04:54:40 PM PDT 24
Finished Jul 16 04:54:42 PM PDT 24
Peak memory 209152 kb
Host smart-97cd40f8-2c4f-44d2-9e98-f92e8b4b23ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597552961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1597552961
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2104347340
Short name T880
Test name
Test status
Simulation time 95564357 ps
CPU time 1.07 seconds
Started Jul 16 04:54:37 PM PDT 24
Finished Jul 16 04:54:39 PM PDT 24
Peak memory 208936 kb
Host smart-6632f036-2a9b-42e9-ab25-fa77a44d914c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104347340 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2104347340
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3780206678
Short name T917
Test name
Test status
Simulation time 300334333 ps
CPU time 7.66 seconds
Started Jul 16 04:54:43 PM PDT 24
Finished Jul 16 04:54:56 PM PDT 24
Peak memory 208788 kb
Host smart-b98b3d8f-5204-43b5-9c29-f40012c8e8e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780206678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3780206678
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.955916933
Short name T961
Test name
Test status
Simulation time 6460494225 ps
CPU time 15.16 seconds
Started Jul 16 04:54:37 PM PDT 24
Finished Jul 16 04:54:54 PM PDT 24
Peak memory 208460 kb
Host smart-c67f3114-d91d-4738-979b-46de20e7ff8b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955916933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.955916933
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.884234115
Short name T932
Test name
Test status
Simulation time 465314984 ps
CPU time 1.92 seconds
Started Jul 16 04:54:57 PM PDT 24
Finished Jul 16 04:55:03 PM PDT 24
Peak memory 210620 kb
Host smart-43bbd27f-76d5-482d-ae0d-76b6deefcc60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884234115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.884234115
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2257228976
Short name T868
Test name
Test status
Simulation time 307892111 ps
CPU time 2.69 seconds
Started Jul 16 04:54:38 PM PDT 24
Finished Jul 16 04:54:42 PM PDT 24
Peak memory 217476 kb
Host smart-0b0859db-304d-48f1-804d-7333cf140613
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225722
8976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2257228976
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2092992193
Short name T957
Test name
Test status
Simulation time 443974486 ps
CPU time 1.33 seconds
Started Jul 16 04:54:38 PM PDT 24
Finished Jul 16 04:54:40 PM PDT 24
Peak memory 209076 kb
Host smart-ffd0d2be-24ee-40c4-adc8-09110214825d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092992193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.2092992193
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3321199526
Short name T949
Test name
Test status
Simulation time 95289339 ps
CPU time 1.38 seconds
Started Jul 16 04:54:30 PM PDT 24
Finished Jul 16 04:54:32 PM PDT 24
Peak memory 209188 kb
Host smart-5209dc1a-5ca1-42ff-b136-d1aa0ab5fb16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321199526 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3321199526
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.966395243
Short name T905
Test name
Test status
Simulation time 88308154 ps
CPU time 1.1 seconds
Started Jul 16 04:54:32 PM PDT 24
Finished Jul 16 04:54:34 PM PDT 24
Peak memory 209124 kb
Host smart-cde29457-0bf7-4a3b-be56-52ef5cb1b9c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966395243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.966395243
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.940424585
Short name T980
Test name
Test status
Simulation time 240453742 ps
CPU time 3.22 seconds
Started Jul 16 04:54:39 PM PDT 24
Finished Jul 16 04:54:43 PM PDT 24
Peak memory 217344 kb
Host smart-115dcbd8-7b24-41b9-a731-7fa0172a97d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940424585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.940424585
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3642243219
Short name T529
Test name
Test status
Simulation time 165848246 ps
CPU time 0.94 seconds
Started Jul 16 05:03:36 PM PDT 24
Finished Jul 16 05:03:37 PM PDT 24
Peak memory 208228 kb
Host smart-c7e98bb2-3c60-4ae5-8dfd-a600317738cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642243219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3642243219
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1296464431
Short name T432
Test name
Test status
Simulation time 4002827393 ps
CPU time 15.66 seconds
Started Jul 16 05:03:31 PM PDT 24
Finished Jul 16 05:03:48 PM PDT 24
Peak memory 225484 kb
Host smart-c4a5098e-0608-40f4-8504-62ecb68766ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296464431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1296464431
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2544507546
Short name T688
Test name
Test status
Simulation time 522199704 ps
CPU time 5.65 seconds
Started Jul 16 05:03:39 PM PDT 24
Finished Jul 16 05:03:46 PM PDT 24
Peak memory 216680 kb
Host smart-717d01a8-0113-4153-bb9f-b3e5d60ef679
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544507546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2544507546
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1827359301
Short name T299
Test name
Test status
Simulation time 5147987714 ps
CPU time 21.61 seconds
Started Jul 16 05:03:36 PM PDT 24
Finished Jul 16 05:03:58 PM PDT 24
Peak memory 217564 kb
Host smart-89b67af4-0c1a-4e84-ad3e-2729d5428a40
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827359301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1827359301
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.39408694
Short name T359
Test name
Test status
Simulation time 3196462103 ps
CPU time 13.8 seconds
Started Jul 16 05:03:37 PM PDT 24
Finished Jul 16 05:03:51 PM PDT 24
Peak memory 217512 kb
Host smart-874d5d21-60a6-4cae-b604-f04eaefb7b89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39408694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.39408694
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1800943181
Short name T450
Test name
Test status
Simulation time 660941680 ps
CPU time 18.61 seconds
Started Jul 16 05:03:39 PM PDT 24
Finished Jul 16 05:03:59 PM PDT 24
Peak memory 217540 kb
Host smart-42cf222c-151c-49fd-b583-56672c7ae019
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800943181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1800943181
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.4029621780
Short name T489
Test name
Test status
Simulation time 4046095123 ps
CPU time 31.58 seconds
Started Jul 16 05:03:37 PM PDT 24
Finished Jul 16 05:04:09 PM PDT 24
Peak memory 217188 kb
Host smart-d3738122-3d73-4446-85a3-cac01ccc9c27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029621780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.4029621780
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3198848530
Short name T668
Test name
Test status
Simulation time 335485985 ps
CPU time 5.35 seconds
Started Jul 16 05:03:32 PM PDT 24
Finished Jul 16 05:03:38 PM PDT 24
Peak memory 217000 kb
Host smart-39453123-2f2f-4b01-a12f-9603f22b36cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198848530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3198848530
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2436466771
Short name T838
Test name
Test status
Simulation time 2995057836 ps
CPU time 68.03 seconds
Started Jul 16 05:03:31 PM PDT 24
Finished Jul 16 05:04:41 PM PDT 24
Peak memory 283100 kb
Host smart-8386bd06-0c3e-4b94-98a9-28593ae73307
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436466771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.2436466771
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.307516797
Short name T680
Test name
Test status
Simulation time 475013362 ps
CPU time 17.79 seconds
Started Jul 16 05:03:48 PM PDT 24
Finished Jul 16 05:04:07 PM PDT 24
Peak memory 249548 kb
Host smart-9c0c192a-ec58-468f-a47a-bc2b52157983
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307516797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.307516797
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3572333049
Short name T812
Test name
Test status
Simulation time 16925160 ps
CPU time 1.63 seconds
Started Jul 16 05:03:26 PM PDT 24
Finished Jul 16 05:03:28 PM PDT 24
Peak memory 221400 kb
Host smart-f45003b3-02f2-410c-8b35-6833407d2db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572333049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3572333049
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2925882090
Short name T249
Test name
Test status
Simulation time 230959919 ps
CPU time 15.36 seconds
Started Jul 16 05:03:30 PM PDT 24
Finished Jul 16 05:03:47 PM PDT 24
Peak memory 217024 kb
Host smart-8268c5e3-d072-4b4b-9092-a1ed1e292de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925882090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2925882090
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1619216031
Short name T83
Test name
Test status
Simulation time 409493762 ps
CPU time 24.87 seconds
Started Jul 16 05:03:38 PM PDT 24
Finished Jul 16 05:04:03 PM PDT 24
Peak memory 282168 kb
Host smart-ec4ac933-27c0-41da-a932-f2371ce33420
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619216031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1619216031
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.78299623
Short name T741
Test name
Test status
Simulation time 325131058 ps
CPU time 13.02 seconds
Started Jul 16 05:03:44 PM PDT 24
Finished Jul 16 05:03:58 PM PDT 24
Peak memory 218428 kb
Host smart-5ad45c75-cdc1-4bec-87c2-c69e0dde1e02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78299623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.78299623
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2128493228
Short name T689
Test name
Test status
Simulation time 281060086 ps
CPU time 8.85 seconds
Started Jul 16 05:03:40 PM PDT 24
Finished Jul 16 05:03:50 PM PDT 24
Peak memory 225416 kb
Host smart-1d7c9356-7a98-4a9f-a5dd-1d12815347ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128493228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2128493228
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1105748588
Short name T687
Test name
Test status
Simulation time 1074560839 ps
CPU time 9.46 seconds
Started Jul 16 05:03:41 PM PDT 24
Finished Jul 16 05:03:51 PM PDT 24
Peak memory 217604 kb
Host smart-d3ef0646-1875-4074-8940-ae281f5a8f70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105748588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
105748588
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2783200356
Short name T854
Test name
Test status
Simulation time 246408845 ps
CPU time 9.79 seconds
Started Jul 16 05:03:30 PM PDT 24
Finished Jul 16 05:03:40 PM PDT 24
Peak memory 225412 kb
Host smart-55ab0b7e-9bcd-4a92-9278-9c3cb1b50e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783200356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2783200356
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3593127399
Short name T363
Test name
Test status
Simulation time 37796308 ps
CPU time 1.92 seconds
Started Jul 16 05:03:30 PM PDT 24
Finished Jul 16 05:03:33 PM PDT 24
Peak memory 213844 kb
Host smart-6f391db0-f9b7-4f17-9882-6e8bf3293661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593127399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3593127399
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.540258217
Short name T517
Test name
Test status
Simulation time 393367336 ps
CPU time 20.22 seconds
Started Jul 16 05:03:30 PM PDT 24
Finished Jul 16 05:03:52 PM PDT 24
Peak memory 250340 kb
Host smart-35fde776-da64-4b29-a2cf-4f0737563ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540258217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.540258217
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3836584278
Short name T379
Test name
Test status
Simulation time 59517465 ps
CPU time 6.31 seconds
Started Jul 16 05:03:31 PM PDT 24
Finished Jul 16 05:03:39 PM PDT 24
Peak memory 245772 kb
Host smart-8b9be3fd-519c-4bbb-8c03-009d90b8b6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836584278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3836584278
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2958612352
Short name T329
Test name
Test status
Simulation time 11920041179 ps
CPU time 95.12 seconds
Started Jul 16 05:03:35 PM PDT 24
Finished Jul 16 05:05:11 PM PDT 24
Peak memory 279144 kb
Host smart-178cbedb-8115-476c-ad31-d3ea08b5cc31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958612352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2958612352
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2760948343
Short name T281
Test name
Test status
Simulation time 42790319 ps
CPU time 0.94 seconds
Started Jul 16 05:03:31 PM PDT 24
Finished Jul 16 05:03:33 PM PDT 24
Peak memory 208248 kb
Host smart-e69fb650-8321-4a4a-9783-c6c62d3a5c63
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760948343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2760948343
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.834375491
Short name T78
Test name
Test status
Simulation time 19044151 ps
CPU time 0.91 seconds
Started Jul 16 05:03:38 PM PDT 24
Finished Jul 16 05:03:40 PM PDT 24
Peak memory 208264 kb
Host smart-33a4d562-1c83-46a4-a2d2-f789c8362e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834375491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.834375491
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.404622734
Short name T276
Test name
Test status
Simulation time 32107577 ps
CPU time 0.81 seconds
Started Jul 16 05:03:41 PM PDT 24
Finished Jul 16 05:03:43 PM PDT 24
Peak memory 208316 kb
Host smart-b89ce6cb-8e5c-4f7a-b67e-e806a72effef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404622734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.404622734
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.4227836653
Short name T296
Test name
Test status
Simulation time 1297812933 ps
CPU time 13.36 seconds
Started Jul 16 05:03:36 PM PDT 24
Finished Jul 16 05:03:50 PM PDT 24
Peak memory 225412 kb
Host smart-f95a41c5-794c-4aca-8d7e-23b4432cf5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227836653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.4227836653
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.622428481
Short name T504
Test name
Test status
Simulation time 344908894 ps
CPU time 9.84 seconds
Started Jul 16 05:03:36 PM PDT 24
Finished Jul 16 05:03:47 PM PDT 24
Peak memory 217096 kb
Host smart-b19a0b8e-6ee0-4170-b482-1ce1b7bc35ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622428481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.622428481
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.579127880
Short name T408
Test name
Test status
Simulation time 4109628091 ps
CPU time 22.95 seconds
Started Jul 16 05:03:36 PM PDT 24
Finished Jul 16 05:04:00 PM PDT 24
Peak memory 218340 kb
Host smart-1c294c25-b895-4550-b2f6-9a30b6372df8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579127880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.579127880
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.829141800
Short name T503
Test name
Test status
Simulation time 314349734 ps
CPU time 8.94 seconds
Started Jul 16 05:03:35 PM PDT 24
Finished Jul 16 05:03:44 PM PDT 24
Peak memory 217048 kb
Host smart-a7b4c015-8601-40f5-be14-93168ac15ef4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829141800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.829141800
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3237601669
Short name T225
Test name
Test status
Simulation time 328413373 ps
CPU time 2.47 seconds
Started Jul 16 05:03:35 PM PDT 24
Finished Jul 16 05:03:38 PM PDT 24
Peak memory 217576 kb
Host smart-cadf04f7-5c1f-43d3-8d6f-b9c4bf6afd00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237601669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3237601669
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1771634361
Short name T796
Test name
Test status
Simulation time 1676954519 ps
CPU time 43.14 seconds
Started Jul 16 05:03:39 PM PDT 24
Finished Jul 16 05:04:24 PM PDT 24
Peak memory 217024 kb
Host smart-53bf0f87-f880-4a9e-8a85-3ac0c73f38be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771634361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1771634361
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.4146773947
Short name T519
Test name
Test status
Simulation time 1200748689 ps
CPU time 4.9 seconds
Started Jul 16 05:03:38 PM PDT 24
Finished Jul 16 05:03:43 PM PDT 24
Peak memory 217048 kb
Host smart-98d7dd42-9b7a-4c1a-a8da-3e54ae7c8f9b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146773947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
4146773947
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.716659142
Short name T849
Test name
Test status
Simulation time 5816582514 ps
CPU time 74.45 seconds
Started Jul 16 05:03:37 PM PDT 24
Finished Jul 16 05:04:52 PM PDT 24
Peak memory 281592 kb
Host smart-2d93e837-9151-4318-bbf5-dde0722247aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716659142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.716659142
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1629107260
Short name T530
Test name
Test status
Simulation time 704745307 ps
CPU time 23.67 seconds
Started Jul 16 05:03:44 PM PDT 24
Finished Jul 16 05:04:08 PM PDT 24
Peak memory 249788 kb
Host smart-9107ecf0-191f-4b02-93a3-78a2696887e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629107260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1629107260
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2579829699
Short name T305
Test name
Test status
Simulation time 93708206 ps
CPU time 3.14 seconds
Started Jul 16 05:03:41 PM PDT 24
Finished Jul 16 05:03:45 PM PDT 24
Peak memory 217716 kb
Host smart-aa63d59e-8844-4762-8a14-cb947ad62181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579829699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2579829699
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.1506159259
Short name T502
Test name
Test status
Simulation time 918175282 ps
CPU time 11.83 seconds
Started Jul 16 05:03:39 PM PDT 24
Finished Jul 16 05:03:52 PM PDT 24
Peak memory 217056 kb
Host smart-d1faa0bf-4473-4cc6-b459-99e4298a1424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506159259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1506159259
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3621021213
Short name T76
Test name
Test status
Simulation time 121053341 ps
CPU time 23.36 seconds
Started Jul 16 05:03:43 PM PDT 24
Finished Jul 16 05:04:07 PM PDT 24
Peak memory 281180 kb
Host smart-b7331f0e-212b-4c92-ab4d-36eb23849312
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621021213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3621021213
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.774621267
Short name T603
Test name
Test status
Simulation time 1424079165 ps
CPU time 16.04 seconds
Started Jul 16 05:03:43 PM PDT 24
Finished Jul 16 05:03:59 PM PDT 24
Peak memory 218276 kb
Host smart-ffe6aa2e-ca65-401e-9c00-22141357086b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774621267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.774621267
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1508417214
Short name T801
Test name
Test status
Simulation time 342605793 ps
CPU time 13 seconds
Started Jul 16 05:03:39 PM PDT 24
Finished Jul 16 05:03:53 PM PDT 24
Peak memory 225372 kb
Host smart-88a5bc09-37df-4b42-bbe7-a41742f934e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508417214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1508417214
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2102208612
Short name T373
Test name
Test status
Simulation time 588661573 ps
CPU time 11.3 seconds
Started Jul 16 05:03:44 PM PDT 24
Finished Jul 16 05:03:56 PM PDT 24
Peak memory 217568 kb
Host smart-e430fc73-4f0b-417b-8d1c-db844452806d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102208612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
102208612
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.210514010
Short name T699
Test name
Test status
Simulation time 734691463 ps
CPU time 10.08 seconds
Started Jul 16 05:03:41 PM PDT 24
Finished Jul 16 05:03:52 PM PDT 24
Peak memory 225452 kb
Host smart-31d4806d-dd32-4903-bb6e-2d482724925a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210514010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.210514010
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.53805331
Short name T799
Test name
Test status
Simulation time 72478546 ps
CPU time 1.07 seconds
Started Jul 16 05:03:42 PM PDT 24
Finished Jul 16 05:03:44 PM PDT 24
Peak memory 217108 kb
Host smart-e4aa76e4-a14d-4043-ae40-b500d455d91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53805331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.53805331
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3446377731
Short name T770
Test name
Test status
Simulation time 549005729 ps
CPU time 18.12 seconds
Started Jul 16 05:03:39 PM PDT 24
Finished Jul 16 05:03:58 PM PDT 24
Peak memory 250404 kb
Host smart-79fec33f-05f8-4c89-afd7-291cfc9bc7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446377731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3446377731
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.459176702
Short name T540
Test name
Test status
Simulation time 279835290 ps
CPU time 6.92 seconds
Started Jul 16 05:03:36 PM PDT 24
Finished Jul 16 05:03:44 PM PDT 24
Peak memory 242228 kb
Host smart-0a4bfc4e-73f3-4b1d-91fc-549d6b8b222a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459176702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.459176702
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.1902224969
Short name T833
Test name
Test status
Simulation time 21680707243 ps
CPU time 200.67 seconds
Started Jul 16 05:03:36 PM PDT 24
Finished Jul 16 05:06:57 PM PDT 24
Peak memory 283296 kb
Host smart-ff1e5c12-1e15-4908-a9fe-0a291114b6ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902224969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.1902224969
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1248394116
Short name T388
Test name
Test status
Simulation time 12946781 ps
CPU time 0.92 seconds
Started Jul 16 05:03:38 PM PDT 24
Finished Jul 16 05:03:40 PM PDT 24
Peak memory 208400 kb
Host smart-7ef12203-f1db-47f5-9f1c-2506704c7e04
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248394116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1248394116
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3079717902
Short name T520
Test name
Test status
Simulation time 32919912 ps
CPU time 0.94 seconds
Started Jul 16 05:04:34 PM PDT 24
Finished Jul 16 05:04:35 PM PDT 24
Peak memory 208544 kb
Host smart-7a908360-a450-481b-a724-ff4a32748f1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079717902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3079717902
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3973901673
Short name T760
Test name
Test status
Simulation time 1155537752 ps
CPU time 12.3 seconds
Started Jul 16 05:04:36 PM PDT 24
Finished Jul 16 05:04:50 PM PDT 24
Peak memory 217608 kb
Host smart-4b76cb24-0fc3-4203-be5a-e452e0725aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973901673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3973901673
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3918385028
Short name T461
Test name
Test status
Simulation time 602948818 ps
CPU time 6.29 seconds
Started Jul 16 05:04:37 PM PDT 24
Finished Jul 16 05:04:45 PM PDT 24
Peak memory 216336 kb
Host smart-17f3b17f-bd79-4153-8c91-edbba5f4049a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918385028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3918385028
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.3224554722
Short name T259
Test name
Test status
Simulation time 4612249861 ps
CPU time 36.61 seconds
Started Jul 16 05:04:36 PM PDT 24
Finished Jul 16 05:05:14 PM PDT 24
Peak memory 218360 kb
Host smart-9134e4d8-bbd8-46e4-bd9e-93cd76b883dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224554722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.3224554722
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2167325980
Short name T454
Test name
Test status
Simulation time 647121007 ps
CPU time 8.89 seconds
Started Jul 16 05:04:36 PM PDT 24
Finished Jul 16 05:04:47 PM PDT 24
Peak memory 217652 kb
Host smart-fe1cc0b9-1dad-4374-966e-3fd08cdcff6e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167325980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2167325980
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2070668396
Short name T223
Test name
Test status
Simulation time 89481247 ps
CPU time 1.96 seconds
Started Jul 16 05:04:37 PM PDT 24
Finished Jul 16 05:04:41 PM PDT 24
Peak memory 217076 kb
Host smart-db01cce4-ee35-42ef-b74f-e29049940c89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070668396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2070668396
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2808800537
Short name T394
Test name
Test status
Simulation time 3604478671 ps
CPU time 64.65 seconds
Started Jul 16 05:04:36 PM PDT 24
Finished Jul 16 05:05:43 PM PDT 24
Peak memory 266916 kb
Host smart-53bae502-55f1-4b5b-9d79-dbb2f048cbed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808800537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2808800537
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1392538404
Short name T653
Test name
Test status
Simulation time 1111336780 ps
CPU time 23.03 seconds
Started Jul 16 05:04:37 PM PDT 24
Finished Jul 16 05:05:02 PM PDT 24
Peak memory 250384 kb
Host smart-2e22aad6-5de4-4ff7-930c-70c8194dcd13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392538404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1392538404
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.712214138
Short name T324
Test name
Test status
Simulation time 181491534 ps
CPU time 2.13 seconds
Started Jul 16 05:04:35 PM PDT 24
Finished Jul 16 05:04:38 PM PDT 24
Peak memory 217700 kb
Host smart-bab06aa9-40d2-4a01-828d-26e666eb2fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712214138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.712214138
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1323365380
Short name T460
Test name
Test status
Simulation time 1510923733 ps
CPU time 12.33 seconds
Started Jul 16 05:04:38 PM PDT 24
Finished Jul 16 05:04:53 PM PDT 24
Peak memory 219348 kb
Host smart-62fcfad8-0ca2-4eb7-a915-889f23e35f65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323365380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1323365380
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.4073797292
Short name T10
Test name
Test status
Simulation time 294535370 ps
CPU time 9.03 seconds
Started Jul 16 05:04:37 PM PDT 24
Finished Jul 16 05:04:49 PM PDT 24
Peak memory 225324 kb
Host smart-6a7cf7f8-ee12-4531-bc0f-2c323d8ad9f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073797292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.4073797292
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.31638007
Short name T815
Test name
Test status
Simulation time 1228930968 ps
CPU time 9.6 seconds
Started Jul 16 05:04:38 PM PDT 24
Finished Jul 16 05:04:50 PM PDT 24
Peak memory 217652 kb
Host smart-5881d32c-e565-43d9-aff1-e3e1d2ada77f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31638007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.31638007
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1652225117
Short name T452
Test name
Test status
Simulation time 97515893 ps
CPU time 3.77 seconds
Started Jul 16 05:04:34 PM PDT 24
Finished Jul 16 05:04:39 PM PDT 24
Peak memory 214616 kb
Host smart-f56e5904-7c80-4a80-993b-d6394ba9afc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652225117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1652225117
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2277594284
Short name T201
Test name
Test status
Simulation time 343503518 ps
CPU time 18.69 seconds
Started Jul 16 05:04:34 PM PDT 24
Finished Jul 16 05:04:54 PM PDT 24
Peak memory 250436 kb
Host smart-4c858bde-8d96-445b-930d-86f58e8cf990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277594284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2277594284
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1007183153
Short name T843
Test name
Test status
Simulation time 249284994 ps
CPU time 6.89 seconds
Started Jul 16 05:04:35 PM PDT 24
Finished Jul 16 05:04:43 PM PDT 24
Peak memory 246516 kb
Host smart-ea00ef35-fc5f-4b26-9880-fbb564675842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007183153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1007183153
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1925089386
Short name T4
Test name
Test status
Simulation time 806711638 ps
CPU time 7.48 seconds
Started Jul 16 05:04:37 PM PDT 24
Finished Jul 16 05:04:46 PM PDT 24
Peak memory 223152 kb
Host smart-95fdbdfa-8813-4a65-9e2a-749be7abfeab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925089386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1925089386
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.634931960
Short name T825
Test name
Test status
Simulation time 21037174 ps
CPU time 0.78 seconds
Started Jul 16 05:04:38 PM PDT 24
Finished Jul 16 05:04:42 PM PDT 24
Peak memory 208332 kb
Host smart-0bb2eb57-8500-44d2-9720-b68fe574a987
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634931960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.634931960
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2514292495
Short name T245
Test name
Test status
Simulation time 202015031 ps
CPU time 1.05 seconds
Started Jul 16 05:04:35 PM PDT 24
Finished Jul 16 05:04:38 PM PDT 24
Peak memory 208392 kb
Host smart-383bddc6-44ca-4652-8685-b04a9c05f092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514292495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2514292495
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.1751256166
Short name T765
Test name
Test status
Simulation time 2560576839 ps
CPU time 18.99 seconds
Started Jul 16 05:04:39 PM PDT 24
Finished Jul 16 05:05:01 PM PDT 24
Peak memory 218320 kb
Host smart-2c73379b-56f1-4fe5-8a7a-6c0d4d71e044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751256166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1751256166
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3064283704
Short name T522
Test name
Test status
Simulation time 547230260 ps
CPU time 13.53 seconds
Started Jul 16 05:04:34 PM PDT 24
Finished Jul 16 05:04:49 PM PDT 24
Peak memory 216788 kb
Host smart-df35ad03-805e-4b62-8c2e-4371a1c2d1a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064283704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3064283704
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2599980852
Short name T285
Test name
Test status
Simulation time 2565716491 ps
CPU time 71.15 seconds
Started Jul 16 05:04:38 PM PDT 24
Finished Jul 16 05:05:52 PM PDT 24
Peak memory 217680 kb
Host smart-6f328366-5ca8-4363-9de6-16d41d742bb1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599980852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2599980852
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1822965907
Short name T332
Test name
Test status
Simulation time 127130626 ps
CPU time 2.44 seconds
Started Jul 16 05:04:38 PM PDT 24
Finished Jul 16 05:04:43 PM PDT 24
Peak memory 220796 kb
Host smart-905c1416-3664-41f0-af59-de9f9476b94c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822965907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1822965907
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3554385372
Short name T651
Test name
Test status
Simulation time 1939683587 ps
CPU time 6.54 seconds
Started Jul 16 05:04:35 PM PDT 24
Finished Jul 16 05:04:43 PM PDT 24
Peak memory 216984 kb
Host smart-337a89af-0d12-46d3-a3ff-369e2577e14c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554385372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3554385372
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3696872771
Short name T735
Test name
Test status
Simulation time 1662490631 ps
CPU time 67.19 seconds
Started Jul 16 05:04:33 PM PDT 24
Finished Jul 16 05:05:41 PM PDT 24
Peak memory 250240 kb
Host smart-1dbc4e2e-0061-4029-a2b0-f1d221211d46
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696872771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3696872771
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3741779751
Short name T614
Test name
Test status
Simulation time 833200328 ps
CPU time 19.57 seconds
Started Jul 16 05:04:34 PM PDT 24
Finished Jul 16 05:04:55 PM PDT 24
Peak memory 250368 kb
Host smart-d054d41a-c5d1-4e8d-9876-7fafa54d3996
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741779751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3741779751
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2976000241
Short name T757
Test name
Test status
Simulation time 32041278 ps
CPU time 2.2 seconds
Started Jul 16 05:04:35 PM PDT 24
Finished Jul 16 05:04:39 PM PDT 24
Peak memory 217752 kb
Host smart-4f0b4406-3efe-4e42-b9b2-d6d4084cd3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976000241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2976000241
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.1982520781
Short name T163
Test name
Test status
Simulation time 892723158 ps
CPU time 12.45 seconds
Started Jul 16 05:04:35 PM PDT 24
Finished Jul 16 05:04:49 PM PDT 24
Peak memory 225144 kb
Host smart-c61d0175-0511-4415-b8e1-8097778b6604
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982520781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.1982520781
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2602457798
Short name T491
Test name
Test status
Simulation time 2083778549 ps
CPU time 11.9 seconds
Started Jul 16 05:04:38 PM PDT 24
Finished Jul 16 05:04:54 PM PDT 24
Peak memory 225368 kb
Host smart-947daa34-6888-4e8d-a0a9-5f996d6adda3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602457798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2602457798
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2188254803
Short name T198
Test name
Test status
Simulation time 566507323 ps
CPU time 10.79 seconds
Started Jul 16 05:04:38 PM PDT 24
Finished Jul 16 05:04:51 PM PDT 24
Peak memory 217576 kb
Host smart-a51f9723-c2ed-473f-bbb7-9bf9b2fe4771
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188254803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2188254803
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2945358888
Short name T295
Test name
Test status
Simulation time 1702931125 ps
CPU time 9.64 seconds
Started Jul 16 05:04:37 PM PDT 24
Finished Jul 16 05:04:50 PM PDT 24
Peak memory 224560 kb
Host smart-fc93b356-be95-4f1e-b635-62290c217e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945358888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2945358888
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.231044492
Short name T60
Test name
Test status
Simulation time 77140013 ps
CPU time 2.81 seconds
Started Jul 16 05:04:37 PM PDT 24
Finished Jul 16 05:04:42 PM PDT 24
Peak memory 217140 kb
Host smart-5457952c-87e5-44da-a21b-ef52bc3aa58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231044492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.231044492
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1160994121
Short name T218
Test name
Test status
Simulation time 263992798 ps
CPU time 21.18 seconds
Started Jul 16 05:04:37 PM PDT 24
Finished Jul 16 05:05:00 PM PDT 24
Peak memory 250428 kb
Host smart-d14c7179-c1b5-4973-b517-54c4658e6c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160994121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1160994121
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3609092134
Short name T437
Test name
Test status
Simulation time 136280229 ps
CPU time 3.83 seconds
Started Jul 16 05:04:38 PM PDT 24
Finished Jul 16 05:04:45 PM PDT 24
Peak memory 225888 kb
Host smart-61d1db8c-97f2-4149-825d-fd89d9c11f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609092134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3609092134
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1439788577
Short name T268
Test name
Test status
Simulation time 27847691460 ps
CPU time 185.96 seconds
Started Jul 16 05:04:38 PM PDT 24
Finished Jul 16 05:07:48 PM PDT 24
Peak memory 280832 kb
Host smart-62d06cec-7718-4063-9e84-96964b7a73d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439788577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1439788577
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2922380149
Short name T415
Test name
Test status
Simulation time 15744178 ps
CPU time 1.02 seconds
Started Jul 16 05:04:39 PM PDT 24
Finished Jul 16 05:04:43 PM PDT 24
Peak memory 211112 kb
Host smart-b262f0bf-d358-4832-8f37-65a7806ee459
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922380149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2922380149
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.2679195565
Short name T683
Test name
Test status
Simulation time 66453259 ps
CPU time 1.08 seconds
Started Jul 16 05:04:40 PM PDT 24
Finished Jul 16 05:04:43 PM PDT 24
Peak memory 208412 kb
Host smart-46d3a077-3428-4b6f-a6be-cebb850c5cd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679195565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2679195565
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.90530216
Short name T244
Test name
Test status
Simulation time 283937709 ps
CPU time 9.85 seconds
Started Jul 16 05:04:40 PM PDT 24
Finished Jul 16 05:04:52 PM PDT 24
Peak memory 225524 kb
Host smart-1c70ca0b-8f05-4a23-b89f-e5c641177cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90530216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.90530216
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.4069321971
Short name T758
Test name
Test status
Simulation time 2043214140 ps
CPU time 13.68 seconds
Started Jul 16 05:04:38 PM PDT 24
Finished Jul 16 05:04:55 PM PDT 24
Peak memory 217044 kb
Host smart-1e8af042-5086-4530-9290-7cc09500d502
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069321971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.4069321971
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2826184336
Short name T531
Test name
Test status
Simulation time 3618164045 ps
CPU time 47.67 seconds
Started Jul 16 05:04:38 PM PDT 24
Finished Jul 16 05:05:29 PM PDT 24
Peak memory 219320 kb
Host smart-9d7d1e72-913c-47bc-b530-4be68b3ac1f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826184336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2826184336
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1759719651
Short name T743
Test name
Test status
Simulation time 640168074 ps
CPU time 9.21 seconds
Started Jul 16 05:04:38 PM PDT 24
Finished Jul 16 05:04:51 PM PDT 24
Peak memory 222388 kb
Host smart-0a62f12f-6f08-4ac8-9ab8-f5869c19f96b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759719651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1759719651
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1721067138
Short name T333
Test name
Test status
Simulation time 2138424662 ps
CPU time 7.04 seconds
Started Jul 16 05:04:36 PM PDT 24
Finished Jul 16 05:04:45 PM PDT 24
Peak memory 217096 kb
Host smart-3eb977e7-6572-4aaf-8e11-9a0d93e0054f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721067138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1721067138
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2757361033
Short name T512
Test name
Test status
Simulation time 2088371485 ps
CPU time 54.81 seconds
Started Jul 16 05:04:37 PM PDT 24
Finished Jul 16 05:05:35 PM PDT 24
Peak memory 275980 kb
Host smart-a37cb6b5-7cb4-431f-968b-f247ab6e584d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757361033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2757361033
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1122083991
Short name T358
Test name
Test status
Simulation time 238976004 ps
CPU time 14.25 seconds
Started Jul 16 05:04:40 PM PDT 24
Finished Jul 16 05:04:57 PM PDT 24
Peak memory 250388 kb
Host smart-40e1e057-2171-442f-a5bd-da3a4653f858
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122083991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1122083991
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2527753483
Short name T558
Test name
Test status
Simulation time 1338108116 ps
CPU time 11.25 seconds
Started Jul 16 05:04:39 PM PDT 24
Finished Jul 16 05:04:53 PM PDT 24
Peak memory 225148 kb
Host smart-f9ee1e55-9241-4073-86f1-51e1819f0735
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527753483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2527753483
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3186579564
Short name T217
Test name
Test status
Simulation time 1014216501 ps
CPU time 19.6 seconds
Started Jul 16 05:04:36 PM PDT 24
Finished Jul 16 05:04:57 PM PDT 24
Peak memory 217604 kb
Host smart-261fd910-f40a-470e-a5ac-c2e2a601f6f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186579564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3186579564
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.214465487
Short name T677
Test name
Test status
Simulation time 534477320 ps
CPU time 10.14 seconds
Started Jul 16 05:04:40 PM PDT 24
Finished Jul 16 05:04:52 PM PDT 24
Peak memory 225040 kb
Host smart-fb8ea06d-ea53-4bf7-9b79-b4e7a06e29ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214465487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.214465487
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2950891555
Short name T63
Test name
Test status
Simulation time 15387762 ps
CPU time 0.89 seconds
Started Jul 16 05:04:38 PM PDT 24
Finished Jul 16 05:04:42 PM PDT 24
Peak memory 208208 kb
Host smart-5043bde7-2833-4495-850a-7eb49e044ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950891555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2950891555
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.577089658
Short name T600
Test name
Test status
Simulation time 672492030 ps
CPU time 22.56 seconds
Started Jul 16 05:04:38 PM PDT 24
Finished Jul 16 05:05:03 PM PDT 24
Peak memory 250384 kb
Host smart-ea6b5089-39c6-4e41-bde2-9d0376f5b8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577089658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.577089658
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1601671480
Short name T302
Test name
Test status
Simulation time 301019553 ps
CPU time 3.08 seconds
Started Jul 16 05:04:38 PM PDT 24
Finished Jul 16 05:04:45 PM PDT 24
Peak memory 221916 kb
Host smart-80f15140-b8ce-4cd7-887c-70f822845001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601671480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1601671480
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.3690209390
Short name T679
Test name
Test status
Simulation time 25719261661 ps
CPU time 443.7 seconds
Started Jul 16 05:04:37 PM PDT 24
Finished Jul 16 05:12:03 PM PDT 24
Peak memory 259396 kb
Host smart-a7838933-30c1-430e-a641-7d7f0ba96b81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690209390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.3690209390
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.935700873
Short name T623
Test name
Test status
Simulation time 12522361 ps
CPU time 0.79 seconds
Started Jul 16 05:04:38 PM PDT 24
Finished Jul 16 05:04:42 PM PDT 24
Peak memory 208332 kb
Host smart-087218b3-3ce4-4f8a-9c55-70b6ac372a80
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935700873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct
rl_volatile_unlock_smoke.935700873
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2217827530
Short name T315
Test name
Test status
Simulation time 19780006 ps
CPU time 0.87 seconds
Started Jul 16 05:04:51 PM PDT 24
Finished Jul 16 05:04:52 PM PDT 24
Peak memory 208208 kb
Host smart-e2300b17-34ca-4a9f-b6f3-8349bb281ad6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217827530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2217827530
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3166923569
Short name T321
Test name
Test status
Simulation time 698800612 ps
CPU time 6.77 seconds
Started Jul 16 05:04:56 PM PDT 24
Finished Jul 16 05:05:04 PM PDT 24
Peak memory 217044 kb
Host smart-255c61a1-7e13-47b3-9822-8db87d0b631f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166923569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3166923569
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.331919245
Short name T861
Test name
Test status
Simulation time 4988850424 ps
CPU time 70.38 seconds
Started Jul 16 05:04:49 PM PDT 24
Finished Jul 16 05:06:01 PM PDT 24
Peak memory 219344 kb
Host smart-b753a685-ee96-4cce-bebb-16218b317f57
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331919245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.331919245
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2535831993
Short name T196
Test name
Test status
Simulation time 365023800 ps
CPU time 6.3 seconds
Started Jul 16 05:04:49 PM PDT 24
Finished Jul 16 05:04:57 PM PDT 24
Peak memory 217888 kb
Host smart-e5f6fe18-4c40-476a-90dd-424ba3a8026e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535831993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2535831993
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3942325457
Short name T323
Test name
Test status
Simulation time 135205625 ps
CPU time 4.68 seconds
Started Jul 16 05:04:53 PM PDT 24
Finished Jul 16 05:04:59 PM PDT 24
Peak memory 217076 kb
Host smart-3111c7f1-11e9-4c22-87ba-19308665f754
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942325457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3942325457
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3686381136
Short name T413
Test name
Test status
Simulation time 2869642083 ps
CPU time 88.71 seconds
Started Jul 16 05:04:49 PM PDT 24
Finished Jul 16 05:06:19 PM PDT 24
Peak memory 277992 kb
Host smart-aedb2234-c94f-46ed-badc-be8c58960298
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686381136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3686381136
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.357321756
Short name T387
Test name
Test status
Simulation time 634366539 ps
CPU time 13.64 seconds
Started Jul 16 05:04:47 PM PDT 24
Finished Jul 16 05:05:02 PM PDT 24
Peak memory 250372 kb
Host smart-a7c8ab6a-7482-42ac-a008-6d6778e473c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357321756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.357321756
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1518989644
Short name T417
Test name
Test status
Simulation time 50363218 ps
CPU time 3.02 seconds
Started Jul 16 05:04:38 PM PDT 24
Finished Jul 16 05:04:44 PM PDT 24
Peak memory 217636 kb
Host smart-97f3d8d8-571f-4008-b19a-91dc0e6d453d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518989644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1518989644
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.464126493
Short name T693
Test name
Test status
Simulation time 1251779802 ps
CPU time 19.29 seconds
Started Jul 16 05:04:56 PM PDT 24
Finished Jul 16 05:05:16 PM PDT 24
Peak memory 225424 kb
Host smart-11d9cb54-6f50-4124-9da0-ca6877777876
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464126493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.464126493
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2903596335
Short name T841
Test name
Test status
Simulation time 667260896 ps
CPU time 11.54 seconds
Started Jul 16 05:05:10 PM PDT 24
Finished Jul 16 05:05:23 PM PDT 24
Peak memory 225424 kb
Host smart-0c0d47c9-c67e-4738-80c3-2321617765ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903596335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2903596335
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2997394355
Short name T371
Test name
Test status
Simulation time 6806635267 ps
CPU time 17.58 seconds
Started Jul 16 05:04:49 PM PDT 24
Finished Jul 16 05:05:08 PM PDT 24
Peak memory 217720 kb
Host smart-220e71c8-f641-45d9-ab58-21f85177c18f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997394355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2997394355
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.214851517
Short name T641
Test name
Test status
Simulation time 300584972 ps
CPU time 10.94 seconds
Started Jul 16 05:04:39 PM PDT 24
Finished Jul 16 05:04:53 PM PDT 24
Peak memory 217784 kb
Host smart-db08bb3c-531d-441e-9799-d71243c02bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214851517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.214851517
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.4174290955
Short name T649
Test name
Test status
Simulation time 66879516 ps
CPU time 2.33 seconds
Started Jul 16 05:04:37 PM PDT 24
Finished Jul 16 05:04:42 PM PDT 24
Peak memory 213704 kb
Host smart-633e999d-eab4-4aeb-84c0-dbc647e43197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174290955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.4174290955
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.3597439243
Short name T346
Test name
Test status
Simulation time 608875482 ps
CPU time 32.83 seconds
Started Jul 16 05:04:37 PM PDT 24
Finished Jul 16 05:05:13 PM PDT 24
Peak memory 246296 kb
Host smart-0cc77e21-2ce0-4657-af8e-a6a94392a09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597439243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.3597439243
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1365306073
Short name T786
Test name
Test status
Simulation time 115771639 ps
CPU time 2.79 seconds
Started Jul 16 05:04:40 PM PDT 24
Finished Jul 16 05:04:45 PM PDT 24
Peak memory 217724 kb
Host smart-59e969aa-8360-4281-9a4f-31c5542cc3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365306073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1365306073
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.920896415
Short name T73
Test name
Test status
Simulation time 2674495058 ps
CPU time 51.24 seconds
Started Jul 16 05:04:48 PM PDT 24
Finished Jul 16 05:05:41 PM PDT 24
Peak memory 249916 kb
Host smart-fde8d813-423d-4225-ba4c-71a3f98dfcb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920896415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.920896415
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.1623237938
Short name T748
Test name
Test status
Simulation time 29954368041 ps
CPU time 948.46 seconds
Started Jul 16 05:04:50 PM PDT 24
Finished Jul 16 05:20:40 PM PDT 24
Peak memory 277148 kb
Host smart-957759cf-6c96-4b08-8781-93200e4be2fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1623237938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.1623237938
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.962148389
Short name T287
Test name
Test status
Simulation time 58194593 ps
CPU time 0.9 seconds
Started Jul 16 05:04:52 PM PDT 24
Finished Jul 16 05:04:54 PM PDT 24
Peak memory 208204 kb
Host smart-922efb7d-dd4f-406a-aaf7-4a479119f3a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962148389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.962148389
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1190893488
Short name T200
Test name
Test status
Simulation time 1280547132 ps
CPU time 9.27 seconds
Started Jul 16 05:04:49 PM PDT 24
Finished Jul 16 05:04:59 PM PDT 24
Peak memory 217720 kb
Host smart-2011a18b-4350-4ce0-9fdf-5084e411d12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190893488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1190893488
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.733238762
Short name T25
Test name
Test status
Simulation time 934292877 ps
CPU time 9.49 seconds
Started Jul 16 05:04:49 PM PDT 24
Finished Jul 16 05:05:00 PM PDT 24
Peak memory 216656 kb
Host smart-67763a05-b734-4b4b-af25-78d6a6c091b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733238762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.733238762
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1491658326
Short name T682
Test name
Test status
Simulation time 9607498079 ps
CPU time 66.46 seconds
Started Jul 16 05:04:47 PM PDT 24
Finished Jul 16 05:05:55 PM PDT 24
Peak memory 218344 kb
Host smart-256502f8-cd70-47da-a3ce-f2c9ed7887c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491658326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1491658326
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2730061244
Short name T484
Test name
Test status
Simulation time 4007413107 ps
CPU time 13.11 seconds
Started Jul 16 05:04:48 PM PDT 24
Finished Jul 16 05:05:03 PM PDT 24
Peak memory 218372 kb
Host smart-50b3f22f-144e-49b7-b4eb-daf05e7c2f5e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730061244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2730061244
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1474224980
Short name T69
Test name
Test status
Simulation time 326561633 ps
CPU time 2.13 seconds
Started Jul 16 05:04:48 PM PDT 24
Finished Jul 16 05:04:51 PM PDT 24
Peak memory 217052 kb
Host smart-dc486a83-2f7c-42a6-8809-aac2ee9656ff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474224980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1474224980
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3125444648
Short name T220
Test name
Test status
Simulation time 2146329319 ps
CPU time 81.33 seconds
Started Jul 16 05:04:52 PM PDT 24
Finished Jul 16 05:06:14 PM PDT 24
Peak memory 273448 kb
Host smart-203326cf-d8a7-4a42-addf-6bc6fc3a6bc4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125444648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3125444648
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1833323937
Short name T278
Test name
Test status
Simulation time 4164259885 ps
CPU time 23.38 seconds
Started Jul 16 05:04:48 PM PDT 24
Finished Jul 16 05:05:13 PM PDT 24
Peak memory 250376 kb
Host smart-73986847-f62d-40b3-b2a2-9dbb360d45c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833323937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1833323937
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.1122107356
Short name T587
Test name
Test status
Simulation time 68452930 ps
CPU time 3.63 seconds
Started Jul 16 05:04:47 PM PDT 24
Finished Jul 16 05:04:53 PM PDT 24
Peak memory 217644 kb
Host smart-02e46f3b-fc90-4a20-8e7e-f46ce8bcb32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122107356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1122107356
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.907172888
Short name T615
Test name
Test status
Simulation time 1849173272 ps
CPU time 9.51 seconds
Started Jul 16 05:04:49 PM PDT 24
Finished Jul 16 05:05:00 PM PDT 24
Peak memory 225484 kb
Host smart-afabc8a5-3ee3-477c-983d-1509221a331c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907172888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.907172888
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3221334193
Short name T241
Test name
Test status
Simulation time 2122917179 ps
CPU time 10.04 seconds
Started Jul 16 05:04:51 PM PDT 24
Finished Jul 16 05:05:02 PM PDT 24
Peak memory 225340 kb
Host smart-45c7a076-df6b-4053-8181-8a96c50c1570
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221334193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3221334193
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.4112793811
Short name T476
Test name
Test status
Simulation time 404746067 ps
CPU time 8.27 seconds
Started Jul 16 05:04:47 PM PDT 24
Finished Jul 16 05:04:56 PM PDT 24
Peak memory 217516 kb
Host smart-baff7eca-f7d3-43e6-9a2c-953704a62e60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112793811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
4112793811
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3976620553
Short name T400
Test name
Test status
Simulation time 408033899 ps
CPU time 13.69 seconds
Started Jul 16 05:04:48 PM PDT 24
Finished Jul 16 05:05:03 PM PDT 24
Peak memory 225460 kb
Host smart-7c013190-8be8-4e0e-8bc0-14e795d7cdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976620553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3976620553
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.496843627
Short name T385
Test name
Test status
Simulation time 117421462 ps
CPU time 4.97 seconds
Started Jul 16 05:04:56 PM PDT 24
Finished Jul 16 05:05:02 PM PDT 24
Peak memory 217048 kb
Host smart-bb1abe36-1eef-4db7-8841-f26db5e98f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496843627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.496843627
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.263594399
Short name T590
Test name
Test status
Simulation time 235380211 ps
CPU time 20.92 seconds
Started Jul 16 05:04:47 PM PDT 24
Finished Jul 16 05:05:10 PM PDT 24
Peak memory 250440 kb
Host smart-42b3c773-1185-4160-810f-eb13919510dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263594399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.263594399
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.4122964292
Short name T834
Test name
Test status
Simulation time 255494634 ps
CPU time 3.55 seconds
Started Jul 16 05:04:52 PM PDT 24
Finished Jul 16 05:04:56 PM PDT 24
Peak memory 217584 kb
Host smart-b04c7b76-0367-4b38-a923-f862673eefd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122964292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.4122964292
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1105235043
Short name T622
Test name
Test status
Simulation time 110691622018 ps
CPU time 430.39 seconds
Started Jul 16 05:04:47 PM PDT 24
Finished Jul 16 05:11:58 PM PDT 24
Peak memory 250500 kb
Host smart-cf4a7465-34a7-425e-afbc-8f137f19038b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105235043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1105235043
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.751046077
Short name T141
Test name
Test status
Simulation time 158044373317 ps
CPU time 1191.13 seconds
Started Jul 16 05:04:47 PM PDT 24
Finished Jul 16 05:24:40 PM PDT 24
Peak memory 369884 kb
Host smart-2243ed63-c489-4d06-bee5-810b13cc82db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=751046077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.751046077
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1065008216
Short name T523
Test name
Test status
Simulation time 24406952 ps
CPU time 1.12 seconds
Started Jul 16 05:04:46 PM PDT 24
Finished Jul 16 05:04:47 PM PDT 24
Peak memory 211244 kb
Host smart-4205ff33-5778-4169-a40e-869652bf70cd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065008216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1065008216
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.97917212
Short name T382
Test name
Test status
Simulation time 23823672 ps
CPU time 0.88 seconds
Started Jul 16 05:04:50 PM PDT 24
Finished Jul 16 05:04:52 PM PDT 24
Peak memory 208012 kb
Host smart-419c6dff-1f83-41a6-8fa3-ea65b4ca316d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97917212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.97917212
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2411917990
Short name T262
Test name
Test status
Simulation time 753302372 ps
CPU time 9.55 seconds
Started Jul 16 05:04:47 PM PDT 24
Finished Jul 16 05:04:57 PM PDT 24
Peak memory 225484 kb
Host smart-8392a765-6d88-4575-9ee1-b07966793580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411917990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2411917990
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2128614088
Short name T753
Test name
Test status
Simulation time 679387921 ps
CPU time 2.67 seconds
Started Jul 16 05:04:52 PM PDT 24
Finished Jul 16 05:04:55 PM PDT 24
Peak memory 216520 kb
Host smart-61aeb789-735b-4c7e-9bfe-9fa087f795c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128614088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2128614088
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.3616010321
Short name T782
Test name
Test status
Simulation time 7133269033 ps
CPU time 97.22 seconds
Started Jul 16 05:04:57 PM PDT 24
Finished Jul 16 05:06:34 PM PDT 24
Peak memory 219376 kb
Host smart-eae42a02-c975-46d4-8160-f6d1aa9ad08b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616010321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.3616010321
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1815350458
Short name T273
Test name
Test status
Simulation time 460830708 ps
CPU time 12.56 seconds
Started Jul 16 05:04:52 PM PDT 24
Finished Jul 16 05:05:06 PM PDT 24
Peak memory 217564 kb
Host smart-06339a02-f40c-4724-82df-d1d8a9dead0f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815350458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.1815350458
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.287453811
Short name T791
Test name
Test status
Simulation time 109574332 ps
CPU time 3.9 seconds
Started Jul 16 05:04:46 PM PDT 24
Finished Jul 16 05:04:50 PM PDT 24
Peak memory 216992 kb
Host smart-bcebc952-e1c6-4dbd-8cbc-ce612bc297e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287453811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.
287453811
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1239531435
Short name T479
Test name
Test status
Simulation time 2152583078 ps
CPU time 40.08 seconds
Started Jul 16 05:04:47 PM PDT 24
Finished Jul 16 05:05:29 PM PDT 24
Peak memory 268200 kb
Host smart-3b7bc9d5-bf77-4252-b2dd-65d394a6b0d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239531435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1239531435
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2182112886
Short name T577
Test name
Test status
Simulation time 1486798214 ps
CPU time 19.31 seconds
Started Jul 16 05:04:53 PM PDT 24
Finished Jul 16 05:05:13 PM PDT 24
Peak memory 250268 kb
Host smart-7b50cbae-aaf0-495d-8315-d0e4518e6093
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182112886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2182112886
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.409844429
Short name T231
Test name
Test status
Simulation time 150425452 ps
CPU time 3.97 seconds
Started Jul 16 05:04:53 PM PDT 24
Finished Jul 16 05:04:58 PM PDT 24
Peak memory 217652 kb
Host smart-1b605823-120d-47d5-a4f7-ec614148558e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409844429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.409844429
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1796092163
Short name T711
Test name
Test status
Simulation time 682939302 ps
CPU time 13.48 seconds
Started Jul 16 05:04:49 PM PDT 24
Finished Jul 16 05:05:04 PM PDT 24
Peak memory 225428 kb
Host smart-9269bd28-fbb3-433c-84b7-c31153456e30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796092163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.1796092163
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1680622051
Short name T535
Test name
Test status
Simulation time 255663714 ps
CPU time 7.18 seconds
Started Jul 16 05:04:48 PM PDT 24
Finished Jul 16 05:04:57 PM PDT 24
Peak memory 217628 kb
Host smart-18603480-69c3-42ce-8aa9-be78ecb7c4b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680622051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1680622051
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3808191102
Short name T839
Test name
Test status
Simulation time 627984432 ps
CPU time 11.35 seconds
Started Jul 16 05:04:49 PM PDT 24
Finished Jul 16 05:05:02 PM PDT 24
Peak memory 225516 kb
Host smart-df9cbffe-78bc-4d9d-9527-145fb4c0dad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808191102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3808191102
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.3391844101
Short name T783
Test name
Test status
Simulation time 90156658 ps
CPU time 3.02 seconds
Started Jul 16 05:04:54 PM PDT 24
Finished Jul 16 05:04:58 PM PDT 24
Peak memory 223348 kb
Host smart-aebbaca0-4a67-4869-b600-681e0d505264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391844101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3391844101
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3223534981
Short name T310
Test name
Test status
Simulation time 568369199 ps
CPU time 30.41 seconds
Started Jul 16 05:04:48 PM PDT 24
Finished Jul 16 05:05:20 PM PDT 24
Peak memory 250460 kb
Host smart-31eda588-8705-42c6-aa26-9696ed30ba2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223534981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3223534981
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3519235801
Short name T297
Test name
Test status
Simulation time 337420425 ps
CPU time 6.48 seconds
Started Jul 16 05:04:48 PM PDT 24
Finished Jul 16 05:04:56 PM PDT 24
Peak memory 246836 kb
Host smart-7d478267-75ed-45eb-8973-ce45b6b5dc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519235801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3519235801
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.602943073
Short name T848
Test name
Test status
Simulation time 10383925006 ps
CPU time 63.55 seconds
Started Jul 16 05:04:47 PM PDT 24
Finished Jul 16 05:05:51 PM PDT 24
Peak memory 268868 kb
Host smart-c71490d8-efa2-4b4b-a329-366c82ef5f7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602943073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.602943073
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.788317057
Short name T414
Test name
Test status
Simulation time 37053631 ps
CPU time 0.96 seconds
Started Jul 16 05:04:53 PM PDT 24
Finished Jul 16 05:04:55 PM PDT 24
Peak memory 212120 kb
Host smart-06f5288c-89c5-49d5-96f6-76402b8caf7c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788317057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.788317057
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2016740100
Short name T253
Test name
Test status
Simulation time 128685410 ps
CPU time 0.93 seconds
Started Jul 16 05:05:03 PM PDT 24
Finished Jul 16 05:05:06 PM PDT 24
Peak memory 208240 kb
Host smart-09b48b01-cedd-48e8-956c-a5bbc068634b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016740100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2016740100
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.132397673
Short name T425
Test name
Test status
Simulation time 520272356 ps
CPU time 12.36 seconds
Started Jul 16 05:04:53 PM PDT 24
Finished Jul 16 05:05:06 PM PDT 24
Peak memory 217700 kb
Host smart-d8a4ec7c-b77b-4740-9288-80b6700ed439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132397673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.132397673
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2726143497
Short name T349
Test name
Test status
Simulation time 531926564 ps
CPU time 1.93 seconds
Started Jul 16 05:04:53 PM PDT 24
Finished Jul 16 05:04:56 PM PDT 24
Peak memory 217132 kb
Host smart-aaf2d2c2-e5e4-4ea0-9dd6-0e3258a40d4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726143497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2726143497
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1845678506
Short name T203
Test name
Test status
Simulation time 6614183100 ps
CPU time 54.25 seconds
Started Jul 16 05:04:52 PM PDT 24
Finished Jul 16 05:05:48 PM PDT 24
Peak memory 218976 kb
Host smart-f9add583-408d-43db-ad57-7748b7766009
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845678506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1845678506
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1755834580
Short name T736
Test name
Test status
Simulation time 1042110712 ps
CPU time 14.8 seconds
Started Jul 16 05:04:57 PM PDT 24
Finished Jul 16 05:05:12 PM PDT 24
Peak memory 217576 kb
Host smart-f11a7efd-e630-461f-a958-f97ac9ce3021
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755834580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1755834580
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1843229963
Short name T66
Test name
Test status
Simulation time 1122420148 ps
CPU time 6.29 seconds
Started Jul 16 05:04:53 PM PDT 24
Finished Jul 16 05:05:00 PM PDT 24
Peak memory 217000 kb
Host smart-facbfee5-8a50-467a-a84b-64d7c8366091
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843229963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.1843229963
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3697131416
Short name T852
Test name
Test status
Simulation time 4328750373 ps
CPU time 48.26 seconds
Started Jul 16 05:04:54 PM PDT 24
Finished Jul 16 05:05:43 PM PDT 24
Peak memory 251928 kb
Host smart-9238210f-f3b3-4403-84e6-3ee88ed39852
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697131416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3697131416
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.14178097
Short name T526
Test name
Test status
Simulation time 2400136884 ps
CPU time 21.59 seconds
Started Jul 16 05:04:48 PM PDT 24
Finished Jul 16 05:05:12 PM PDT 24
Peak memory 249084 kb
Host smart-c36b3196-3fe5-43c4-9cc4-d77e0016ea9b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14178097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_j
tag_state_post_trans.14178097
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1260034980
Short name T769
Test name
Test status
Simulation time 100888658 ps
CPU time 3.32 seconds
Started Jul 16 05:04:55 PM PDT 24
Finished Jul 16 05:04:59 PM PDT 24
Peak memory 217712 kb
Host smart-b95eb477-4d35-426a-9504-d7cd1faacedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260034980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1260034980
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.2878804359
Short name T470
Test name
Test status
Simulation time 258789028 ps
CPU time 12.48 seconds
Started Jul 16 05:04:56 PM PDT 24
Finished Jul 16 05:05:09 PM PDT 24
Peak memory 217636 kb
Host smart-e1792059-1c55-4c45-88d9-011cbdb95342
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878804359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2878804359
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1390603995
Short name T441
Test name
Test status
Simulation time 529247118 ps
CPU time 13.22 seconds
Started Jul 16 05:04:53 PM PDT 24
Finished Jul 16 05:05:07 PM PDT 24
Peak memory 225184 kb
Host smart-f93b57c8-a999-4a57-9852-3937eec0f496
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390603995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1390603995
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.694249478
Short name T327
Test name
Test status
Simulation time 807328969 ps
CPU time 9.02 seconds
Started Jul 16 05:04:53 PM PDT 24
Finished Jul 16 05:05:03 PM PDT 24
Peak memory 225432 kb
Host smart-8d5d32ed-7f05-4d78-833f-ce4d718add41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694249478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.694249478
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2736453590
Short name T90
Test name
Test status
Simulation time 912250078 ps
CPU time 11.08 seconds
Started Jul 16 05:04:51 PM PDT 24
Finished Jul 16 05:05:03 PM PDT 24
Peak memory 217720 kb
Host smart-c6a748cf-9e1f-43b3-99bd-3a7b63c87508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736453590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2736453590
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.313336793
Short name T492
Test name
Test status
Simulation time 146243919 ps
CPU time 2.25 seconds
Started Jul 16 05:04:53 PM PDT 24
Finished Jul 16 05:04:56 PM PDT 24
Peak memory 213824 kb
Host smart-c2180a9b-e8ee-46b9-baff-8f9684ba0621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313336793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.313336793
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.4064802845
Short name T463
Test name
Test status
Simulation time 601067475 ps
CPU time 25.34 seconds
Started Jul 16 05:04:47 PM PDT 24
Finished Jul 16 05:05:14 PM PDT 24
Peak memory 250248 kb
Host smart-40430689-a9b5-4f9d-9ff1-25e9bc9555c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064802845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.4064802845
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.1625739650
Short name T501
Test name
Test status
Simulation time 105132369 ps
CPU time 9.91 seconds
Started Jul 16 05:04:51 PM PDT 24
Finished Jul 16 05:05:02 PM PDT 24
Peak memory 250400 kb
Host smart-a637d82e-b2dc-4e0c-879b-54c3be0cbbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625739650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1625739650
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.3365446753
Short name T234
Test name
Test status
Simulation time 4266454095 ps
CPU time 85.29 seconds
Started Jul 16 05:05:03 PM PDT 24
Finished Jul 16 05:06:30 PM PDT 24
Peak memory 258928 kb
Host smart-6482858a-b03c-4a04-b107-137b806db417
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365446753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.3365446753
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.507225132
Short name T257
Test name
Test status
Simulation time 79814883 ps
CPU time 0.91 seconds
Started Jul 16 05:04:53 PM PDT 24
Finished Jul 16 05:04:55 PM PDT 24
Peak memory 217108 kb
Host smart-6ea7adce-ae05-4144-abf6-e53f118e3937
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507225132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.507225132
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1513944441
Short name T342
Test name
Test status
Simulation time 22502527 ps
CPU time 1.01 seconds
Started Jul 16 05:04:59 PM PDT 24
Finished Jul 16 05:05:00 PM PDT 24
Peak memory 208272 kb
Host smart-460a9a77-3594-46c3-957c-f938660b358c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513944441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1513944441
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2487924277
Short name T789
Test name
Test status
Simulation time 2103801063 ps
CPU time 11.02 seconds
Started Jul 16 05:05:03 PM PDT 24
Finished Jul 16 05:05:16 PM PDT 24
Peak memory 225420 kb
Host smart-8079cc25-28c8-4ba5-bbb4-e1c5e5764ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487924277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2487924277
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2836327505
Short name T355
Test name
Test status
Simulation time 159496622 ps
CPU time 4.65 seconds
Started Jul 16 05:05:08 PM PDT 24
Finished Jul 16 05:05:14 PM PDT 24
Peak memory 217108 kb
Host smart-21d505c7-19ab-4610-953a-1c54f0dab64e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836327505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2836327505
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3504631813
Short name T397
Test name
Test status
Simulation time 3705347360 ps
CPU time 29.22 seconds
Started Jul 16 05:05:02 PM PDT 24
Finished Jul 16 05:05:33 PM PDT 24
Peak memory 217912 kb
Host smart-38e8d880-089d-454f-9680-9a74ac5f398e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504631813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3504631813
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3668791067
Short name T806
Test name
Test status
Simulation time 1063672380 ps
CPU time 8.98 seconds
Started Jul 16 05:05:00 PM PDT 24
Finished Jul 16 05:05:10 PM PDT 24
Peak memory 217584 kb
Host smart-940af4da-4cd8-4888-8edb-5d2d1de25595
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668791067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3668791067
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.940809374
Short name T742
Test name
Test status
Simulation time 3803270311 ps
CPU time 6.93 seconds
Started Jul 16 05:04:59 PM PDT 24
Finished Jul 16 05:05:07 PM PDT 24
Peak memory 217060 kb
Host smart-8d0f9430-b463-4cf6-825c-478e5e96054d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940809374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
940809374
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1056851693
Short name T444
Test name
Test status
Simulation time 1832722106 ps
CPU time 68.32 seconds
Started Jul 16 05:04:59 PM PDT 24
Finished Jul 16 05:06:09 PM PDT 24
Peak memory 274984 kb
Host smart-d794d1f9-2823-4339-bdda-ab8edf3a2b88
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056851693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1056851693
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1491177149
Short name T568
Test name
Test status
Simulation time 1108080046 ps
CPU time 12.95 seconds
Started Jul 16 05:04:59 PM PDT 24
Finished Jul 16 05:05:14 PM PDT 24
Peak memory 246876 kb
Host smart-79ff1eb0-662d-44ae-b366-677f331950ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491177149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1491177149
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3747012426
Short name T764
Test name
Test status
Simulation time 182759150 ps
CPU time 2.33 seconds
Started Jul 16 05:05:08 PM PDT 24
Finished Jul 16 05:05:11 PM PDT 24
Peak memory 217632 kb
Host smart-e32c87a7-acde-4f9b-b18b-506868e4aaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747012426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3747012426
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.910252654
Short name T857
Test name
Test status
Simulation time 1048040580 ps
CPU time 13.74 seconds
Started Jul 16 05:05:04 PM PDT 24
Finished Jul 16 05:05:20 PM PDT 24
Peak memory 225204 kb
Host smart-ce1bb797-ff66-4c53-8231-1ac3e68bf0cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910252654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.910252654
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3977378735
Short name T591
Test name
Test status
Simulation time 282592311 ps
CPU time 8.54 seconds
Started Jul 16 05:05:04 PM PDT 24
Finished Jul 16 05:05:15 PM PDT 24
Peak memory 225456 kb
Host smart-57585910-8f2a-43bb-8297-c01c75892806
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977378735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3977378735
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3858825501
Short name T787
Test name
Test status
Simulation time 313942497 ps
CPU time 11.44 seconds
Started Jul 16 05:05:04 PM PDT 24
Finished Jul 16 05:05:18 PM PDT 24
Peak memory 217668 kb
Host smart-e8bf036e-ebfd-4add-8cd4-cfc48b0f5052
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858825501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3858825501
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.94520290
Short name T471
Test name
Test status
Simulation time 2136948796 ps
CPU time 10.55 seconds
Started Jul 16 05:05:02 PM PDT 24
Finished Jul 16 05:05:15 PM PDT 24
Peak memory 217768 kb
Host smart-93d5804e-c3a4-4066-9c89-d128971c609e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94520290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.94520290
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2331536502
Short name T599
Test name
Test status
Simulation time 526242151 ps
CPU time 4.02 seconds
Started Jul 16 05:05:08 PM PDT 24
Finished Jul 16 05:05:13 PM PDT 24
Peak memory 217124 kb
Host smart-cd764af6-d903-426a-9549-3e391b6bf74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331536502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2331536502
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3071833249
Short name T9
Test name
Test status
Simulation time 231959086 ps
CPU time 25.77 seconds
Started Jul 16 05:04:59 PM PDT 24
Finished Jul 16 05:05:26 PM PDT 24
Peak memory 250512 kb
Host smart-dbf9f916-10b1-4a6e-87a5-32989b801d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071833249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3071833249
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.1500179041
Short name T555
Test name
Test status
Simulation time 107981434 ps
CPU time 7.98 seconds
Started Jul 16 05:05:02 PM PDT 24
Finished Jul 16 05:05:13 PM PDT 24
Peak memory 250460 kb
Host smart-df6eb42d-4f2e-427b-87e4-ebfb05d17287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500179041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1500179041
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2662788759
Short name T556
Test name
Test status
Simulation time 10295063236 ps
CPU time 113.41 seconds
Started Jul 16 05:04:59 PM PDT 24
Finished Jul 16 05:06:55 PM PDT 24
Peak memory 275240 kb
Host smart-61e15b63-f741-4741-aac8-bc91b49b5f40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662788759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2662788759
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3491076163
Short name T744
Test name
Test status
Simulation time 20090000 ps
CPU time 0.79 seconds
Started Jul 16 05:05:03 PM PDT 24
Finished Jul 16 05:05:06 PM PDT 24
Peak memory 208172 kb
Host smart-b34397ed-b2d0-4a3f-94ef-e9d67ca40eb2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491076163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3491076163
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1034586081
Short name T494
Test name
Test status
Simulation time 17973301 ps
CPU time 1.24 seconds
Started Jul 16 05:05:04 PM PDT 24
Finished Jul 16 05:05:07 PM PDT 24
Peak memory 208288 kb
Host smart-1aa40c2e-26a0-4641-9347-cfe3c1fe3ddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034586081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1034586081
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2662929310
Short name T516
Test name
Test status
Simulation time 368067677 ps
CPU time 10.73 seconds
Started Jul 16 05:05:02 PM PDT 24
Finished Jul 16 05:05:15 PM PDT 24
Peak memory 225512 kb
Host smart-fc0c0d9b-2871-49f0-9ccd-4708f8ebce6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662929310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2662929310
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.791947684
Short name T640
Test name
Test status
Simulation time 92810099 ps
CPU time 1.95 seconds
Started Jul 16 05:05:01 PM PDT 24
Finished Jul 16 05:05:05 PM PDT 24
Peak memory 216144 kb
Host smart-51065940-dffc-40c3-ac9a-942e6129661f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791947684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.791947684
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2540733550
Short name T473
Test name
Test status
Simulation time 2029757410 ps
CPU time 12.79 seconds
Started Jul 16 05:05:03 PM PDT 24
Finished Jul 16 05:05:18 PM PDT 24
Peak memory 217620 kb
Host smart-931875e3-62b5-4419-8c20-6ab7f001f7ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540733550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2540733550
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1822362135
Short name T853
Test name
Test status
Simulation time 137608040 ps
CPU time 4.68 seconds
Started Jul 16 05:04:59 PM PDT 24
Finished Jul 16 05:05:05 PM PDT 24
Peak memory 217048 kb
Host smart-9dea629f-de0a-4612-9012-05a089405f24
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822362135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1822362135
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.498401153
Short name T161
Test name
Test status
Simulation time 1424538520 ps
CPU time 33.01 seconds
Started Jul 16 05:05:00 PM PDT 24
Finished Jul 16 05:05:34 PM PDT 24
Peak memory 275232 kb
Host smart-3e96d10a-6a8b-4fda-abf4-c946c4f1ebc1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498401153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.498401153
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3799395873
Short name T311
Test name
Test status
Simulation time 392846548 ps
CPU time 13.59 seconds
Started Jul 16 05:05:03 PM PDT 24
Finished Jul 16 05:05:19 PM PDT 24
Peak memory 250368 kb
Host smart-f527dd74-27cd-4218-b4d1-7c507c3f939e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799395873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3799395873
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2413629281
Short name T704
Test name
Test status
Simulation time 174938329 ps
CPU time 2.61 seconds
Started Jul 16 05:05:00 PM PDT 24
Finished Jul 16 05:05:04 PM PDT 24
Peak memory 217924 kb
Host smart-c0def811-fd30-468d-b8b5-c731c20ddfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413629281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2413629281
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.533809223
Short name T524
Test name
Test status
Simulation time 1875730877 ps
CPU time 13.92 seconds
Started Jul 16 05:05:09 PM PDT 24
Finished Jul 16 05:05:24 PM PDT 24
Peak memory 225496 kb
Host smart-ce0f5bc7-1fda-40fd-8424-52ae17e07206
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533809223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.533809223
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1614446283
Short name T595
Test name
Test status
Simulation time 734437745 ps
CPU time 19.24 seconds
Started Jul 16 05:05:08 PM PDT 24
Finished Jul 16 05:05:28 PM PDT 24
Peak memory 225428 kb
Host smart-e286fd94-33ee-4049-9fc7-0658573a428f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614446283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1614446283
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2297735834
Short name T844
Test name
Test status
Simulation time 1435722589 ps
CPU time 12.04 seconds
Started Jul 16 05:05:00 PM PDT 24
Finished Jul 16 05:05:14 PM PDT 24
Peak memory 217648 kb
Host smart-114b60d7-dd4c-4aec-8376-664b55ffb2bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297735834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2297735834
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3464244174
Short name T565
Test name
Test status
Simulation time 2817035885 ps
CPU time 7.71 seconds
Started Jul 16 05:05:02 PM PDT 24
Finished Jul 16 05:05:12 PM PDT 24
Peak memory 225496 kb
Host smart-ba8435eb-6171-4d31-971c-a5dc2b5957a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464244174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3464244174
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1098170770
Short name T549
Test name
Test status
Simulation time 827008294 ps
CPU time 6.13 seconds
Started Jul 16 05:05:02 PM PDT 24
Finished Jul 16 05:05:11 PM PDT 24
Peak memory 216956 kb
Host smart-a14808a7-11ef-4793-b174-fc84cfbbf997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098170770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1098170770
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2423895850
Short name T472
Test name
Test status
Simulation time 742344643 ps
CPU time 31.95 seconds
Started Jul 16 05:05:02 PM PDT 24
Finished Jul 16 05:05:37 PM PDT 24
Peak memory 250400 kb
Host smart-24fbb208-cfff-4fde-8ad6-af90b49e3d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423895850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2423895850
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3664554634
Short name T528
Test name
Test status
Simulation time 78166905 ps
CPU time 9.73 seconds
Started Jul 16 05:05:00 PM PDT 24
Finished Jul 16 05:05:11 PM PDT 24
Peak memory 250408 kb
Host smart-b4ee55ad-d256-49f7-abdd-16ff6263b555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664554634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3664554634
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3617769570
Short name T236
Test name
Test status
Simulation time 86206521812 ps
CPU time 218.32 seconds
Started Jul 16 05:05:02 PM PDT 24
Finished Jul 16 05:08:43 PM PDT 24
Peak memory 404608 kb
Host smart-ff587d25-b89c-45f6-8ea5-2cadf37cc9f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617769570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3617769570
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.411719817
Short name T145
Test name
Test status
Simulation time 12493893250 ps
CPU time 409.4 seconds
Started Jul 16 05:05:03 PM PDT 24
Finished Jul 16 05:11:55 PM PDT 24
Peak memory 278112 kb
Host smart-5bfc9109-fd91-4de4-890c-26cc61a4d29d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=411719817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.411719817
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.38775753
Short name T341
Test name
Test status
Simulation time 31038378 ps
CPU time 0.76 seconds
Started Jul 16 05:04:59 PM PDT 24
Finished Jul 16 05:05:01 PM PDT 24
Peak memory 208372 kb
Host smart-78f5c572-1cf8-444b-bca2-e1eb41623c04
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38775753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_volatile_unlock_smoke.38775753
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3010621317
Short name T32
Test name
Test status
Simulation time 219802839 ps
CPU time 7.87 seconds
Started Jul 16 05:05:01 PM PDT 24
Finished Jul 16 05:05:11 PM PDT 24
Peak memory 217772 kb
Host smart-12507c54-b338-4963-8c6a-1bab4cbc9d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010621317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3010621317
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.739586884
Short name T26
Test name
Test status
Simulation time 2326223960 ps
CPU time 6.32 seconds
Started Jul 16 05:05:16 PM PDT 24
Finished Jul 16 05:05:24 PM PDT 24
Peak memory 217176 kb
Host smart-9ab94d77-3c09-4d26-84e2-aafaa09bd9f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739586884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.739586884
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1565962290
Short name T391
Test name
Test status
Simulation time 4840118642 ps
CPU time 73.62 seconds
Started Jul 16 05:05:01 PM PDT 24
Finished Jul 16 05:06:16 PM PDT 24
Peak memory 218320 kb
Host smart-3074e46f-2151-4497-890a-9ffdbf9a4483
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565962290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1565962290
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3200698379
Short name T746
Test name
Test status
Simulation time 511586401 ps
CPU time 7.61 seconds
Started Jul 16 05:05:03 PM PDT 24
Finished Jul 16 05:05:13 PM PDT 24
Peak memory 223400 kb
Host smart-9cbd365e-6830-4228-90db-199f5faddbec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200698379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.3200698379
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1251169965
Short name T20
Test name
Test status
Simulation time 856087735 ps
CPU time 3.88 seconds
Started Jul 16 05:05:02 PM PDT 24
Finished Jul 16 05:05:08 PM PDT 24
Peak memory 217028 kb
Host smart-b3fbd45a-f4ac-42e3-80bc-bdba73fc6711
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251169965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1251169965
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3862362087
Short name T208
Test name
Test status
Simulation time 2980235567 ps
CPU time 39.25 seconds
Started Jul 16 05:05:01 PM PDT 24
Finished Jul 16 05:05:43 PM PDT 24
Peak memory 275672 kb
Host smart-fdb68de3-8a84-4dd8-8837-8f1c50c8bf5e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862362087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3862362087
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3144480825
Short name T194
Test name
Test status
Simulation time 886504534 ps
CPU time 15.22 seconds
Started Jul 16 05:05:09 PM PDT 24
Finished Jul 16 05:05:25 PM PDT 24
Peak memory 225872 kb
Host smart-a71668f7-6a0c-4cae-8b2b-ac5d3c1fb2ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144480825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.3144480825
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2022966231
Short name T500
Test name
Test status
Simulation time 223035340 ps
CPU time 3.13 seconds
Started Jul 16 05:05:03 PM PDT 24
Finished Jul 16 05:05:08 PM PDT 24
Peak memory 217636 kb
Host smart-53f9a0af-bb18-48d1-a0a3-c11328936f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022966231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2022966231
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1599997888
Short name T752
Test name
Test status
Simulation time 681271970 ps
CPU time 10.37 seconds
Started Jul 16 05:05:15 PM PDT 24
Finished Jul 16 05:05:28 PM PDT 24
Peak memory 218280 kb
Host smart-821f59a7-3af9-446c-a24a-e789d5734944
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599997888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1599997888
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.521617898
Short name T228
Test name
Test status
Simulation time 1115684035 ps
CPU time 21.67 seconds
Started Jul 16 05:05:16 PM PDT 24
Finished Jul 16 05:05:40 PM PDT 24
Peak memory 225428 kb
Host smart-96f014cc-df67-4706-b748-6fff4759ca51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521617898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_di
gest.521617898
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2068080947
Short name T338
Test name
Test status
Simulation time 483994832 ps
CPU time 15.24 seconds
Started Jul 16 05:05:19 PM PDT 24
Finished Jul 16 05:05:36 PM PDT 24
Peak memory 217504 kb
Host smart-1a408c48-9c01-483e-9ee3-c1c5bd5bcc67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068080947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2068080947
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2658481650
Short name T650
Test name
Test status
Simulation time 289372704 ps
CPU time 7.07 seconds
Started Jul 16 05:05:09 PM PDT 24
Finished Jul 16 05:05:17 PM PDT 24
Peak memory 224164 kb
Host smart-4a9e00eb-0f53-4a89-bb1a-daf591b753a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658481650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2658481650
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3650810318
Short name T326
Test name
Test status
Simulation time 337987792 ps
CPU time 3.2 seconds
Started Jul 16 05:05:01 PM PDT 24
Finished Jul 16 05:05:06 PM PDT 24
Peak memory 217124 kb
Host smart-4ecace39-3d3b-4ce1-af51-b8bb3f0bed0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650810318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3650810318
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1293958304
Short name T541
Test name
Test status
Simulation time 477431002 ps
CPU time 25.93 seconds
Started Jul 16 05:05:01 PM PDT 24
Finished Jul 16 05:05:29 PM PDT 24
Peak memory 249964 kb
Host smart-0d838e8d-856a-43dc-bd3a-ae231292afb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293958304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1293958304
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1309722816
Short name T406
Test name
Test status
Simulation time 87914387 ps
CPU time 6.57 seconds
Started Jul 16 05:05:01 PM PDT 24
Finished Jul 16 05:05:09 PM PDT 24
Peak memory 249852 kb
Host smart-372517a7-f7f5-4e1a-ad12-f8975c146bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309722816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1309722816
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1223312696
Short name T270
Test name
Test status
Simulation time 49209213131 ps
CPU time 423.7 seconds
Started Jul 16 05:05:20 PM PDT 24
Finished Jul 16 05:12:25 PM PDT 24
Peak memory 221184 kb
Host smart-f6b715cd-2e58-4d4d-b193-3fae5ef64c62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223312696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1223312696
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1875429262
Short name T293
Test name
Test status
Simulation time 48216574 ps
CPU time 0.92 seconds
Started Jul 16 05:05:00 PM PDT 24
Finished Jul 16 05:05:02 PM PDT 24
Peak memory 212280 kb
Host smart-14969d45-3d33-47a8-9492-2491a84a82c6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875429262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.1875429262
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2903624115
Short name T482
Test name
Test status
Simulation time 55372679 ps
CPU time 0.85 seconds
Started Jul 16 05:03:51 PM PDT 24
Finished Jul 16 05:03:53 PM PDT 24
Peak memory 208076 kb
Host smart-6fe70acd-1f8e-4958-b181-4e4ddfcc44ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903624115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2903624115
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3122275974
Short name T446
Test name
Test status
Simulation time 12194288 ps
CPU time 0.97 seconds
Started Jul 16 05:03:48 PM PDT 24
Finished Jul 16 05:03:50 PM PDT 24
Peak memory 208164 kb
Host smart-047b1fbe-d966-4fdb-9460-1aad3a3aeefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122275974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3122275974
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1743818192
Short name T467
Test name
Test status
Simulation time 1012683667 ps
CPU time 14.12 seconds
Started Jul 16 05:03:48 PM PDT 24
Finished Jul 16 05:04:03 PM PDT 24
Peak memory 217640 kb
Host smart-3315e3c7-7954-4fc7-a172-e8f9b71c8d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743818192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1743818192
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.487344286
Short name T694
Test name
Test status
Simulation time 179623169 ps
CPU time 2.72 seconds
Started Jul 16 05:03:41 PM PDT 24
Finished Jul 16 05:03:45 PM PDT 24
Peak memory 217164 kb
Host smart-ac83352f-6847-4196-a1f2-32ff111df527
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487344286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.487344286
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.4124715297
Short name T692
Test name
Test status
Simulation time 1938264063 ps
CPU time 56.2 seconds
Started Jul 16 05:03:41 PM PDT 24
Finished Jul 16 05:04:38 PM PDT 24
Peak memory 218400 kb
Host smart-b19b0550-e2ea-4dc0-abf5-c84d69502736
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124715297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.4124715297
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2494198445
Short name T665
Test name
Test status
Simulation time 2970344943 ps
CPU time 11.96 seconds
Started Jul 16 05:03:37 PM PDT 24
Finished Jul 16 05:03:50 PM PDT 24
Peak memory 217176 kb
Host smart-76a1da79-3701-4a7d-96ca-886d05cb2f2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494198445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
494198445
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.119094741
Short name T375
Test name
Test status
Simulation time 340309676 ps
CPU time 6.24 seconds
Started Jul 16 05:03:41 PM PDT 24
Finished Jul 16 05:03:48 PM PDT 24
Peak memory 217668 kb
Host smart-1cd0a6c4-b5af-41f4-8d27-a3c0f93a945b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119094741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
prog_failure.119094741
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2287361780
Short name T768
Test name
Test status
Simulation time 8140248501 ps
CPU time 28.98 seconds
Started Jul 16 05:03:48 PM PDT 24
Finished Jul 16 05:04:18 PM PDT 24
Peak memory 217164 kb
Host smart-58507d4f-8d3c-4033-9de4-349f78b7d54f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287361780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2287361780
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1251440370
Short name T356
Test name
Test status
Simulation time 277163494 ps
CPU time 2.71 seconds
Started Jul 16 05:03:36 PM PDT 24
Finished Jul 16 05:03:39 PM PDT 24
Peak memory 217036 kb
Host smart-fbd2f20a-6fbc-4817-b3da-60d67207bbb3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251440370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1251440370
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1245783273
Short name T282
Test name
Test status
Simulation time 9428492213 ps
CPU time 66.53 seconds
Started Jul 16 05:03:48 PM PDT 24
Finished Jul 16 05:04:55 PM PDT 24
Peak memory 266704 kb
Host smart-c9aeb6fc-9ce0-4b35-9cd9-82fd12e164b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245783273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1245783273
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2514465670
Short name T564
Test name
Test status
Simulation time 3324338009 ps
CPU time 15.47 seconds
Started Jul 16 05:03:48 PM PDT 24
Finished Jul 16 05:04:04 PM PDT 24
Peak memory 250356 kb
Host smart-0589a121-3892-4d5a-bf20-aa67da524502
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514465670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2514465670
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.4127297594
Short name T427
Test name
Test status
Simulation time 87165972 ps
CPU time 2.08 seconds
Started Jul 16 05:03:41 PM PDT 24
Finished Jul 16 05:03:44 PM PDT 24
Peak memory 221652 kb
Host smart-bf8477b0-665c-421c-a9c9-e24c8c004c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127297594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.4127297594
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3868007312
Short name T723
Test name
Test status
Simulation time 1288287054 ps
CPU time 7.17 seconds
Started Jul 16 05:03:48 PM PDT 24
Finished Jul 16 05:03:56 PM PDT 24
Peak memory 217032 kb
Host smart-c0a071a5-391a-47d9-ba25-70bed92886fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868007312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3868007312
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2643055530
Short name T159
Test name
Test status
Simulation time 245885753 ps
CPU time 11.02 seconds
Started Jul 16 05:03:48 PM PDT 24
Finished Jul 16 05:04:01 PM PDT 24
Peak memory 225512 kb
Host smart-2acb0182-9a6c-4971-a99b-ededbfec6a2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643055530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2643055530
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3177020313
Short name T548
Test name
Test status
Simulation time 674376755 ps
CPU time 10.31 seconds
Started Jul 16 05:03:46 PM PDT 24
Finished Jul 16 05:03:57 PM PDT 24
Peak memory 225388 kb
Host smart-c5a9d548-8b15-474b-ab59-bccdaf717b2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177020313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3177020313
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3646423758
Short name T423
Test name
Test status
Simulation time 347358598 ps
CPU time 12.21 seconds
Started Jul 16 05:03:52 PM PDT 24
Finished Jul 16 05:04:06 PM PDT 24
Peak memory 217624 kb
Host smart-34f7a61d-c4e4-49cf-841f-da547d17c524
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646423758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
646423758
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3452565455
Short name T629
Test name
Test status
Simulation time 1478467579 ps
CPU time 12.38 seconds
Started Jul 16 05:03:48 PM PDT 24
Finished Jul 16 05:04:02 PM PDT 24
Peak memory 225428 kb
Host smart-0d02d4b3-b269-4733-b5db-65d55811f002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452565455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3452565455
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3274690908
Short name T224
Test name
Test status
Simulation time 22140230 ps
CPU time 1.71 seconds
Started Jul 16 05:03:37 PM PDT 24
Finished Jul 16 05:03:40 PM PDT 24
Peak memory 213356 kb
Host smart-00115359-2dfe-4737-9547-51f66b251fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274690908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3274690908
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1878658157
Short name T370
Test name
Test status
Simulation time 608705528 ps
CPU time 21.04 seconds
Started Jul 16 05:03:44 PM PDT 24
Finished Jul 16 05:04:06 PM PDT 24
Peak memory 250440 kb
Host smart-5799e1b2-c73e-42e3-9a74-cdb2cc29a4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878658157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1878658157
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2964027496
Short name T308
Test name
Test status
Simulation time 81207101 ps
CPU time 6.33 seconds
Started Jul 16 05:03:38 PM PDT 24
Finished Jul 16 05:03:45 PM PDT 24
Peak memory 246504 kb
Host smart-b123c227-01bb-408b-862a-038df41fcd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964027496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2964027496
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2503780075
Short name T722
Test name
Test status
Simulation time 11443530492 ps
CPU time 193.45 seconds
Started Jul 16 05:03:52 PM PDT 24
Finished Jul 16 05:07:07 PM PDT 24
Peak memory 222808 kb
Host smart-7e86c73f-4477-49c3-bcb4-4875dcb2c116
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503780075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2503780075
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.253264425
Short name T204
Test name
Test status
Simulation time 21089099 ps
CPU time 1.39 seconds
Started Jul 16 05:03:44 PM PDT 24
Finished Jul 16 05:03:46 PM PDT 24
Peak memory 217268 kb
Host smart-4c426e42-452b-42d1-9304-3a76936464c2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253264425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.253264425
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3022008764
Short name T365
Test name
Test status
Simulation time 58191726 ps
CPU time 1.05 seconds
Started Jul 16 05:05:14 PM PDT 24
Finished Jul 16 05:05:17 PM PDT 24
Peak memory 208304 kb
Host smart-c07cb8b8-8ea6-4886-916b-effafb49f7f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022008764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3022008764
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.755983919
Short name T703
Test name
Test status
Simulation time 59714947 ps
CPU time 2.77 seconds
Started Jul 16 05:05:13 PM PDT 24
Finished Jul 16 05:05:16 PM PDT 24
Peak memory 217716 kb
Host smart-82762f92-250a-4d62-9ee0-979ce8143d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755983919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.755983919
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2734932765
Short name T631
Test name
Test status
Simulation time 557945850 ps
CPU time 9.16 seconds
Started Jul 16 05:05:14 PM PDT 24
Finished Jul 16 05:05:26 PM PDT 24
Peak memory 225336 kb
Host smart-6a3210b8-4c0e-4357-a4d3-f7191e57ec2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734932765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2734932765
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.4150348960
Short name T498
Test name
Test status
Simulation time 263270790 ps
CPU time 7.95 seconds
Started Jul 16 05:05:17 PM PDT 24
Finished Jul 16 05:05:27 PM PDT 24
Peak memory 217588 kb
Host smart-090a5634-62a4-48be-86fc-a1015d8d895d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150348960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
4150348960
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3060118136
Short name T607
Test name
Test status
Simulation time 751018680 ps
CPU time 10.48 seconds
Started Jul 16 05:05:18 PM PDT 24
Finished Jul 16 05:05:30 PM PDT 24
Peak memory 224320 kb
Host smart-e6deaf46-b4c1-46fb-995f-b5a8dd7a269f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060118136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3060118136
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2461672661
Short name T766
Test name
Test status
Simulation time 146921883 ps
CPU time 4.4 seconds
Started Jul 16 05:05:14 PM PDT 24
Finished Jul 16 05:05:19 PM PDT 24
Peak memory 217108 kb
Host smart-d251662c-88c8-452b-9b5e-75c091b70de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461672661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2461672661
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1775746797
Short name T632
Test name
Test status
Simulation time 395602039 ps
CPU time 33.52 seconds
Started Jul 16 05:05:17 PM PDT 24
Finished Jul 16 05:05:53 PM PDT 24
Peak memory 250288 kb
Host smart-eefb16f1-66db-458d-a322-3d5f243af02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775746797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1775746797
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2118742172
Short name T510
Test name
Test status
Simulation time 277510323 ps
CPU time 8.61 seconds
Started Jul 16 05:05:15 PM PDT 24
Finished Jul 16 05:05:26 PM PDT 24
Peak memory 250392 kb
Host smart-aa0db5cc-a5e5-480b-813c-839989794540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118742172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2118742172
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1957222008
Short name T39
Test name
Test status
Simulation time 6044813266 ps
CPU time 53.16 seconds
Started Jul 16 05:05:17 PM PDT 24
Finished Jul 16 05:06:13 PM PDT 24
Peak memory 226412 kb
Host smart-56532a4e-a362-49e2-9708-56abb4fffe2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957222008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1957222008
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3518315948
Short name T681
Test name
Test status
Simulation time 43042079 ps
CPU time 1.01 seconds
Started Jul 16 05:05:15 PM PDT 24
Finished Jul 16 05:05:17 PM PDT 24
Peak memory 208308 kb
Host smart-278152dd-7ba1-4192-bc23-1e8b16d9ca21
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518315948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.3518315948
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3485126587
Short name T303
Test name
Test status
Simulation time 103699433 ps
CPU time 0.81 seconds
Started Jul 16 05:05:17 PM PDT 24
Finished Jul 16 05:05:20 PM PDT 24
Peak memory 208500 kb
Host smart-a0694fb1-03c7-4d47-b49b-eb27eae825a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485126587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3485126587
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.2591280707
Short name T165
Test name
Test status
Simulation time 226955557 ps
CPU time 11.57 seconds
Started Jul 16 05:05:13 PM PDT 24
Finished Jul 16 05:05:26 PM PDT 24
Peak memory 217636 kb
Host smart-aeed8d47-380f-4d3a-b9ce-dc7596a09b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591280707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2591280707
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.4176530075
Short name T733
Test name
Test status
Simulation time 386785721 ps
CPU time 1.47 seconds
Started Jul 16 05:05:15 PM PDT 24
Finished Jul 16 05:05:19 PM PDT 24
Peak memory 216540 kb
Host smart-a440497f-4e45-4c09-87df-da6939388aa7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176530075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.4176530075
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3332435397
Short name T567
Test name
Test status
Simulation time 287016974 ps
CPU time 3.43 seconds
Started Jul 16 05:05:15 PM PDT 24
Finished Jul 16 05:05:21 PM PDT 24
Peak memory 217704 kb
Host smart-e18cbab2-6d4b-4860-9853-227a066da1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332435397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3332435397
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2144571066
Short name T275
Test name
Test status
Simulation time 318305616 ps
CPU time 11.01 seconds
Started Jul 16 05:05:16 PM PDT 24
Finished Jul 16 05:05:30 PM PDT 24
Peak memory 218300 kb
Host smart-f3c7f177-db14-4a65-8e05-b1a6f2ad0504
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144571066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2144571066
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2102057949
Short name T219
Test name
Test status
Simulation time 516384459 ps
CPU time 19.68 seconds
Started Jul 16 05:05:17 PM PDT 24
Finished Jul 16 05:05:39 PM PDT 24
Peak memory 225456 kb
Host smart-98b32cf2-781c-4e23-b387-75ce09b5e507
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102057949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2102057949
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.177755580
Short name T618
Test name
Test status
Simulation time 586426797 ps
CPU time 11.02 seconds
Started Jul 16 05:05:15 PM PDT 24
Finished Jul 16 05:05:29 PM PDT 24
Peak memory 217640 kb
Host smart-8df89f9b-343d-4339-901a-4c4e17717a68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177755580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.177755580
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3896726167
Short name T51
Test name
Test status
Simulation time 1122410084 ps
CPU time 12.87 seconds
Started Jul 16 05:05:18 PM PDT 24
Finished Jul 16 05:05:33 PM PDT 24
Peak memory 225516 kb
Host smart-d5cbb75f-9fba-4b66-9d67-fe677056fcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896726167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3896726167
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1374539560
Short name T34
Test name
Test status
Simulation time 134459355 ps
CPU time 2.75 seconds
Started Jul 16 05:05:20 PM PDT 24
Finished Jul 16 05:05:24 PM PDT 24
Peak memory 222960 kb
Host smart-d9f5d869-00d6-46e8-8d7e-81d09f3513fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374539560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1374539560
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3204748750
Short name T92
Test name
Test status
Simulation time 2493056225 ps
CPU time 20.69 seconds
Started Jul 16 05:05:16 PM PDT 24
Finished Jul 16 05:05:39 PM PDT 24
Peak memory 250528 kb
Host smart-9eefc50e-4e3e-447a-9825-0281e2607be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204748750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3204748750
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2501321130
Short name T661
Test name
Test status
Simulation time 241644904 ps
CPU time 8.65 seconds
Started Jul 16 05:05:17 PM PDT 24
Finished Jul 16 05:05:28 PM PDT 24
Peak memory 246828 kb
Host smart-769937d6-5c2a-42b0-8f11-4a9648e7263d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501321130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2501321130
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1531136733
Short name T372
Test name
Test status
Simulation time 19877956305 ps
CPU time 37.59 seconds
Started Jul 16 05:05:17 PM PDT 24
Finished Jul 16 05:05:57 PM PDT 24
Peak memory 234748 kb
Host smart-365747da-0086-4332-b0df-01112e7c22c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531136733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1531136733
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1728531576
Short name T800
Test name
Test status
Simulation time 26660223 ps
CPU time 1.85 seconds
Started Jul 16 05:05:14 PM PDT 24
Finished Jul 16 05:05:18 PM PDT 24
Peak memory 217196 kb
Host smart-97406509-0b51-4983-803f-3a210fd9ccd9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728531576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1728531576
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.4048558801
Short name T448
Test name
Test status
Simulation time 22678254 ps
CPU time 0.91 seconds
Started Jul 16 05:05:28 PM PDT 24
Finished Jul 16 05:05:31 PM PDT 24
Peak memory 208268 kb
Host smart-65fd4cce-94c9-4fc4-a1a3-39e56d1a4914
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048558801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.4048558801
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2614656617
Short name T390
Test name
Test status
Simulation time 1862153034 ps
CPU time 21.33 seconds
Started Jul 16 05:05:17 PM PDT 24
Finished Jul 16 05:05:41 PM PDT 24
Peak memory 217684 kb
Host smart-df8fe1b5-c3f4-4f26-b801-73b655a7e3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614656617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2614656617
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1761953852
Short name T545
Test name
Test status
Simulation time 522267412 ps
CPU time 3.5 seconds
Started Jul 16 05:05:16 PM PDT 24
Finished Jul 16 05:05:22 PM PDT 24
Peak memory 217016 kb
Host smart-5d454a05-cfa5-4bb4-a6a7-22ab60cc674c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761953852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1761953852
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2342988633
Short name T421
Test name
Test status
Simulation time 284100114 ps
CPU time 3.14 seconds
Started Jul 16 05:05:18 PM PDT 24
Finished Jul 16 05:05:23 PM PDT 24
Peak memory 217716 kb
Host smart-f3728051-4a68-48e7-97e3-37de049ce8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342988633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2342988633
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.4256228181
Short name T763
Test name
Test status
Simulation time 1408922781 ps
CPU time 15.01 seconds
Started Jul 16 05:05:14 PM PDT 24
Finished Jul 16 05:05:31 PM PDT 24
Peak memory 218296 kb
Host smart-0edd3511-1584-4497-8c78-32568a7cf322
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256228181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.4256228181
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.688022972
Short name T235
Test name
Test status
Simulation time 660632499 ps
CPU time 9.57 seconds
Started Jul 16 05:05:16 PM PDT 24
Finished Jul 16 05:05:28 PM PDT 24
Peak memory 225384 kb
Host smart-7a5b5092-de41-48d8-907f-b872ef67e838
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688022972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di
gest.688022972
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.120272862
Short name T55
Test name
Test status
Simulation time 1216386478 ps
CPU time 7.18 seconds
Started Jul 16 05:05:28 PM PDT 24
Finished Jul 16 05:05:37 PM PDT 24
Peak memory 217640 kb
Host smart-3daf5333-178d-44ae-a087-9b860d11ce18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120272862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.120272862
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.61664920
Short name T420
Test name
Test status
Simulation time 594166741 ps
CPU time 11.03 seconds
Started Jul 16 05:05:18 PM PDT 24
Finished Jul 16 05:05:31 PM PDT 24
Peak memory 217756 kb
Host smart-b0072631-bcc6-46fb-8e2b-ae70e0a9b711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61664920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.61664920
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1221541902
Short name T71
Test name
Test status
Simulation time 283897793 ps
CPU time 2.03 seconds
Started Jul 16 05:05:20 PM PDT 24
Finished Jul 16 05:05:23 PM PDT 24
Peak memory 217212 kb
Host smart-b8ef797d-8e3a-4815-b832-cdce77871ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221541902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1221541902
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.988304220
Short name T286
Test name
Test status
Simulation time 340819903 ps
CPU time 26.98 seconds
Started Jul 16 05:05:15 PM PDT 24
Finished Jul 16 05:05:44 PM PDT 24
Peak memory 250468 kb
Host smart-dd99fb33-c5d8-4616-b753-d92addf6e727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988304220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.988304220
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3591496700
Short name T247
Test name
Test status
Simulation time 68076537 ps
CPU time 6.19 seconds
Started Jul 16 05:05:17 PM PDT 24
Finished Jul 16 05:05:26 PM PDT 24
Peak memory 249912 kb
Host smart-a64de649-bfba-4cae-9cc8-2df4bb2a33b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591496700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3591496700
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2509805235
Short name T248
Test name
Test status
Simulation time 1339120783 ps
CPU time 39.14 seconds
Started Jul 16 05:05:15 PM PDT 24
Finished Jul 16 05:05:56 PM PDT 24
Peak memory 250412 kb
Host smart-177024ba-db5b-440f-abe0-e50b3b2a17fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509805235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2509805235
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1790939481
Short name T35
Test name
Test status
Simulation time 16705875 ps
CPU time 0.98 seconds
Started Jul 16 05:05:17 PM PDT 24
Finished Jul 16 05:05:21 PM PDT 24
Peak memory 211192 kb
Host smart-2054766f-db59-4d50-a851-24cbeea7f31f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790939481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.1790939481
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.210429324
Short name T702
Test name
Test status
Simulation time 95935756 ps
CPU time 0.93 seconds
Started Jul 16 05:05:28 PM PDT 24
Finished Jul 16 05:05:31 PM PDT 24
Peak memory 208228 kb
Host smart-45e2f2a6-0c91-4ebf-b28e-07cfe2f3654d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210429324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.210429324
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.220954547
Short name T537
Test name
Test status
Simulation time 237463357 ps
CPU time 10.79 seconds
Started Jul 16 05:05:31 PM PDT 24
Finished Jul 16 05:05:45 PM PDT 24
Peak memory 217692 kb
Host smart-691d9132-c5be-4dda-987d-c2fcf6a5987d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220954547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.220954547
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3325087722
Short name T335
Test name
Test status
Simulation time 1333236660 ps
CPU time 8.04 seconds
Started Jul 16 05:05:29 PM PDT 24
Finished Jul 16 05:05:40 PM PDT 24
Peak memory 217228 kb
Host smart-a1ea523d-ec56-4a87-8b8f-dbd9fcd994cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325087722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3325087722
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1184515567
Short name T376
Test name
Test status
Simulation time 270832976 ps
CPU time 3.08 seconds
Started Jul 16 05:05:35 PM PDT 24
Finished Jul 16 05:05:43 PM PDT 24
Peak memory 217620 kb
Host smart-2f7d7945-9f2c-4d39-bc68-88c2a4ec0227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184515567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1184515567
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1416165064
Short name T727
Test name
Test status
Simulation time 606358578 ps
CPU time 12.8 seconds
Started Jul 16 05:05:38 PM PDT 24
Finished Jul 16 05:05:58 PM PDT 24
Peak memory 217868 kb
Host smart-75068738-be4a-4570-90cb-33aca0e7dff5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416165064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1416165064
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.755384975
Short name T493
Test name
Test status
Simulation time 526250600 ps
CPU time 11.45 seconds
Started Jul 16 05:05:31 PM PDT 24
Finished Jul 16 05:05:45 PM PDT 24
Peak memory 225428 kb
Host smart-fc3e93a9-5bfc-4f92-b00c-2897183054a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755384975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.755384975
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2419610248
Short name T594
Test name
Test status
Simulation time 636608730 ps
CPU time 10.1 seconds
Started Jul 16 05:05:29 PM PDT 24
Finished Jul 16 05:05:41 PM PDT 24
Peak memory 217652 kb
Host smart-8fd367c4-d174-438a-9f9e-7e0b7c0c52a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419610248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2419610248
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.153949897
Short name T389
Test name
Test status
Simulation time 409182137 ps
CPU time 13.28 seconds
Started Jul 16 05:05:35 PM PDT 24
Finished Jul 16 05:05:53 PM PDT 24
Peak memory 225440 kb
Host smart-e31f3108-9f44-49b4-8d8e-ba60011abb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153949897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.153949897
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2426177092
Short name T637
Test name
Test status
Simulation time 47259186 ps
CPU time 3.23 seconds
Started Jul 16 05:05:15 PM PDT 24
Finished Jul 16 05:05:20 PM PDT 24
Peak memory 213860 kb
Host smart-cef02563-07f4-40a8-ba00-a7f89baa8fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426177092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2426177092
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1800373940
Short name T624
Test name
Test status
Simulation time 448097632 ps
CPU time 27.12 seconds
Started Jul 16 05:05:28 PM PDT 24
Finished Jul 16 05:05:58 PM PDT 24
Peak memory 250444 kb
Host smart-130c93ab-9b5d-4f51-888f-dd865799cd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800373940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1800373940
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.5681351
Short name T343
Test name
Test status
Simulation time 98724554 ps
CPU time 6.71 seconds
Started Jul 16 05:05:28 PM PDT 24
Finished Jul 16 05:05:37 PM PDT 24
Peak memory 250016 kb
Host smart-8f4a8ae9-ec71-4369-b3a7-1a8909936712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5681351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.5681351
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1138989709
Short name T451
Test name
Test status
Simulation time 12211101017 ps
CPU time 436.02 seconds
Started Jul 16 05:05:34 PM PDT 24
Finished Jul 16 05:12:55 PM PDT 24
Peak memory 272940 kb
Host smart-1ed0d005-9e34-469a-a384-c6248686a70b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138989709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1138989709
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.4172142536
Short name T94
Test name
Test status
Simulation time 21443741631 ps
CPU time 661.59 seconds
Started Jul 16 05:05:28 PM PDT 24
Finished Jul 16 05:16:32 PM PDT 24
Peak memory 332568 kb
Host smart-25dcfe47-16f7-44d0-9fde-14158b1ce0e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4172142536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.4172142536
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2968510250
Short name T578
Test name
Test status
Simulation time 135228213 ps
CPU time 0.8 seconds
Started Jul 16 05:05:27 PM PDT 24
Finished Jul 16 05:05:29 PM PDT 24
Peak memory 208288 kb
Host smart-0ea14a7d-839a-4462-9d07-bb8aad5b11fa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968510250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2968510250
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.2444540387
Short name T750
Test name
Test status
Simulation time 16345296 ps
CPU time 0.91 seconds
Started Jul 16 05:05:33 PM PDT 24
Finished Jul 16 05:05:38 PM PDT 24
Peak memory 208196 kb
Host smart-e181386b-ec3e-4951-a44d-1fbfddaa1104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444540387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.2444540387
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1815961460
Short name T331
Test name
Test status
Simulation time 1356549926 ps
CPU time 16.64 seconds
Started Jul 16 05:05:33 PM PDT 24
Finished Jul 16 05:05:53 PM PDT 24
Peak memory 225460 kb
Host smart-fd81b81b-5923-4ef2-917e-b0fc5f9d7982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815961460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1815961460
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.707577668
Short name T187
Test name
Test status
Simulation time 155939482 ps
CPU time 1.33 seconds
Started Jul 16 05:05:27 PM PDT 24
Finished Jul 16 05:05:30 PM PDT 24
Peak memory 217096 kb
Host smart-d583a9db-c430-46a7-aa5e-b0874ea797ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707577668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.707577668
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3583896470
Short name T830
Test name
Test status
Simulation time 70931066 ps
CPU time 3.76 seconds
Started Jul 16 05:05:33 PM PDT 24
Finished Jul 16 05:05:41 PM PDT 24
Peak memory 221992 kb
Host smart-92e2c27f-3dcb-4574-bb08-b699855879a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583896470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3583896470
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1736327655
Short name T666
Test name
Test status
Simulation time 1060209183 ps
CPU time 10.64 seconds
Started Jul 16 05:05:34 PM PDT 24
Finished Jul 16 05:05:49 PM PDT 24
Peak memory 217532 kb
Host smart-c0a2fe8b-8882-4dda-be54-173365810e52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736327655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1736327655
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3548427174
Short name T474
Test name
Test status
Simulation time 1190986207 ps
CPU time 9.99 seconds
Started Jul 16 05:05:28 PM PDT 24
Finished Jul 16 05:05:41 PM PDT 24
Peak memory 225396 kb
Host smart-c469f8fd-c7f9-4cff-99f2-889450cf1365
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548427174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3548427174
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1061172853
Short name T542
Test name
Test status
Simulation time 437826913 ps
CPU time 9.6 seconds
Started Jul 16 05:05:34 PM PDT 24
Finished Jul 16 05:05:48 PM PDT 24
Peak memory 225428 kb
Host smart-251429e2-e23f-4b41-9686-3984457fc493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061172853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1061172853
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1170668803
Short name T322
Test name
Test status
Simulation time 58379070 ps
CPU time 2.73 seconds
Started Jul 16 05:05:31 PM PDT 24
Finished Jul 16 05:05:36 PM PDT 24
Peak memory 214020 kb
Host smart-6404e3c0-3ce5-4b0b-a202-bd62e96319ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170668803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1170668803
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2712683498
Short name T617
Test name
Test status
Simulation time 235089303 ps
CPU time 25.64 seconds
Started Jul 16 05:05:32 PM PDT 24
Finished Jul 16 05:06:01 PM PDT 24
Peak memory 250428 kb
Host smart-dcf80f28-ada6-43ef-92c4-785d08a804f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712683498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2712683498
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.497658622
Short name T759
Test name
Test status
Simulation time 372952898 ps
CPU time 2.8 seconds
Started Jul 16 05:05:28 PM PDT 24
Finished Jul 16 05:05:32 PM PDT 24
Peak memory 217640 kb
Host smart-02977e37-9acf-497e-bb17-3014dbd0056b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497658622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.497658622
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.1729721039
Short name T74
Test name
Test status
Simulation time 9268566269 ps
CPU time 66.71 seconds
Started Jul 16 05:05:34 PM PDT 24
Finished Jul 16 05:06:46 PM PDT 24
Peak memory 250376 kb
Host smart-463ac45c-b551-4e3c-91ee-4eddb4cbe4bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729721039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.1729721039
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1982440322
Short name T767
Test name
Test status
Simulation time 14465309 ps
CPU time 0.94 seconds
Started Jul 16 05:05:33 PM PDT 24
Finished Jul 16 05:05:38 PM PDT 24
Peak memory 211172 kb
Host smart-f0ce72f8-33b8-4a8a-973f-3d29c4514575
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982440322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1982440322
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2697007575
Short name T64
Test name
Test status
Simulation time 22168331 ps
CPU time 1.02 seconds
Started Jul 16 05:05:29 PM PDT 24
Finished Jul 16 05:05:33 PM PDT 24
Peak memory 208292 kb
Host smart-f6460b56-a655-4cc3-a267-a85d2420d443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697007575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2697007575
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2598084898
Short name T412
Test name
Test status
Simulation time 431217707 ps
CPU time 8.83 seconds
Started Jul 16 05:05:29 PM PDT 24
Finished Jul 16 05:05:40 PM PDT 24
Peak memory 225408 kb
Host smart-0c233edc-c567-4ada-a65b-354e6f25585b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598084898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2598084898
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.4291279673
Short name T6
Test name
Test status
Simulation time 6412307246 ps
CPU time 27.83 seconds
Started Jul 16 05:05:32 PM PDT 24
Finished Jul 16 05:06:03 PM PDT 24
Peak memory 217204 kb
Host smart-b665f8e2-ac29-4cf6-816b-5e39006570a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291279673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.4291279673
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.532115558
Short name T312
Test name
Test status
Simulation time 113625138 ps
CPU time 1.86 seconds
Started Jul 16 05:05:30 PM PDT 24
Finished Jul 16 05:05:34 PM PDT 24
Peak memory 221580 kb
Host smart-d64d02f7-1958-4989-8a50-557709ab2bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532115558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.532115558
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1561876256
Short name T798
Test name
Test status
Simulation time 882591688 ps
CPU time 8.85 seconds
Started Jul 16 05:05:32 PM PDT 24
Finished Jul 16 05:05:45 PM PDT 24
Peak memory 218336 kb
Host smart-9e9a25b6-33cd-4c58-a9ef-dcc9a266af02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561876256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1561876256
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2817670390
Short name T14
Test name
Test status
Simulation time 1617284696 ps
CPU time 10.68 seconds
Started Jul 16 05:05:29 PM PDT 24
Finished Jul 16 05:05:43 PM PDT 24
Peak memory 225428 kb
Host smart-47392bc5-281e-46e4-a207-c2d9bc40e5f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817670390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2817670390
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.4139154182
Short name T784
Test name
Test status
Simulation time 471699566 ps
CPU time 10.96 seconds
Started Jul 16 05:05:29 PM PDT 24
Finished Jul 16 05:05:42 PM PDT 24
Peak memory 217608 kb
Host smart-b8f98312-9354-490b-80ec-96810e0dc7d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139154182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
4139154182
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.974099708
Short name T821
Test name
Test status
Simulation time 666796678 ps
CPU time 12.02 seconds
Started Jul 16 05:05:29 PM PDT 24
Finished Jul 16 05:05:43 PM PDT 24
Peak memory 225372 kb
Host smart-beb85dc9-953d-4fbe-b3d1-237076cb7fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974099708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.974099708
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3144681884
Short name T316
Test name
Test status
Simulation time 19827295 ps
CPU time 1.62 seconds
Started Jul 16 05:05:32 PM PDT 24
Finished Jul 16 05:05:37 PM PDT 24
Peak memory 213340 kb
Host smart-8ee7de03-3609-41a3-9081-fb6d2fc3f734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144681884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3144681884
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.4272192703
Short name T793
Test name
Test status
Simulation time 211436740 ps
CPU time 18.45 seconds
Started Jul 16 05:05:35 PM PDT 24
Finished Jul 16 05:05:59 PM PDT 24
Peak memory 250308 kb
Host smart-bc78e0b0-0d86-4b1a-b1ce-5716ccb159a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272192703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.4272192703
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3416224872
Short name T195
Test name
Test status
Simulation time 217241087 ps
CPU time 7.11 seconds
Started Jul 16 05:05:35 PM PDT 24
Finished Jul 16 05:05:47 PM PDT 24
Peak memory 250188 kb
Host smart-2ee22489-5261-4153-a709-ee466033c401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416224872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3416224872
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1306420991
Short name T398
Test name
Test status
Simulation time 15745014195 ps
CPU time 143.1 seconds
Started Jul 16 05:05:34 PM PDT 24
Finished Jul 16 05:08:01 PM PDT 24
Peak memory 282456 kb
Host smart-9f0180bf-d6b3-45d4-bff9-67931585ce94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306420991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1306420991
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.831923255
Short name T708
Test name
Test status
Simulation time 9353819230 ps
CPU time 383 seconds
Started Jul 16 05:05:28 PM PDT 24
Finished Jul 16 05:11:52 PM PDT 24
Peak memory 438332 kb
Host smart-953572b9-ed97-4662-8084-fa795b00e7cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=831923255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.831923255
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1037150460
Short name T827
Test name
Test status
Simulation time 12864384 ps
CPU time 0.91 seconds
Started Jul 16 05:05:32 PM PDT 24
Finished Jul 16 05:05:36 PM PDT 24
Peak memory 211296 kb
Host smart-448806d7-6594-444b-a0c5-8a7502e046c6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037150460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1037150460
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.314895958
Short name T712
Test name
Test status
Simulation time 15318139 ps
CPU time 1.02 seconds
Started Jul 16 05:05:33 PM PDT 24
Finished Jul 16 05:05:38 PM PDT 24
Peak memory 208328 kb
Host smart-5d7a2f20-7a39-45db-b69d-f2478e89f310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314895958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.314895958
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3060039633
Short name T664
Test name
Test status
Simulation time 1846240236 ps
CPU time 14.39 seconds
Started Jul 16 05:05:33 PM PDT 24
Finished Jul 16 05:05:52 PM PDT 24
Peak memory 217596 kb
Host smart-b684fb90-9080-4cdf-a110-b5719bae7339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060039633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3060039633
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1305040489
Short name T747
Test name
Test status
Simulation time 400479155 ps
CPU time 4.79 seconds
Started Jul 16 05:05:38 PM PDT 24
Finished Jul 16 05:05:50 PM PDT 24
Peak memory 217144 kb
Host smart-c89de5cd-5372-4d36-ada2-3677f2f305d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305040489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1305040489
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.476577539
Short name T330
Test name
Test status
Simulation time 34096541 ps
CPU time 1.85 seconds
Started Jul 16 05:06:31 PM PDT 24
Finished Jul 16 05:06:35 PM PDT 24
Peak memory 217692 kb
Host smart-33b4f2b0-95d3-4107-a14c-180c66d53bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476577539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.476577539
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.3128674280
Short name T263
Test name
Test status
Simulation time 2675667174 ps
CPU time 14.74 seconds
Started Jul 16 05:05:29 PM PDT 24
Finished Jul 16 05:05:46 PM PDT 24
Peak memory 225496 kb
Host smart-c4522a04-be11-4fe7-b25e-a6bf83d7c3cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128674280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3128674280
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.232348788
Short name T378
Test name
Test status
Simulation time 6780088594 ps
CPU time 13.11 seconds
Started Jul 16 05:05:31 PM PDT 24
Finished Jul 16 05:05:47 PM PDT 24
Peak memory 225452 kb
Host smart-0504c490-07fb-4bf8-88c4-b7aafc92caae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232348788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.232348788
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.218473979
Short name T351
Test name
Test status
Simulation time 3224815357 ps
CPU time 10.54 seconds
Started Jul 16 05:05:29 PM PDT 24
Finished Jul 16 05:05:42 PM PDT 24
Peak memory 225560 kb
Host smart-b985c8f7-a01b-4ce4-b885-b3c553b3ac9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218473979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.218473979
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1547486351
Short name T50
Test name
Test status
Simulation time 1491216042 ps
CPU time 9.49 seconds
Started Jul 16 05:05:29 PM PDT 24
Finished Jul 16 05:05:41 PM PDT 24
Peak memory 225224 kb
Host smart-8ec755bc-54fb-4d4d-b724-abf23fe36b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547486351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1547486351
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2185137969
Short name T429
Test name
Test status
Simulation time 58125348 ps
CPU time 1.88 seconds
Started Jul 16 05:05:31 PM PDT 24
Finished Jul 16 05:05:35 PM PDT 24
Peak memory 217124 kb
Host smart-bc7dc440-005f-44f6-a6eb-36f560fd8882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185137969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2185137969
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.173239839
Short name T75
Test name
Test status
Simulation time 707898343 ps
CPU time 30.5 seconds
Started Jul 16 05:05:33 PM PDT 24
Finished Jul 16 05:06:08 PM PDT 24
Peak memory 250476 kb
Host smart-64fed48d-d48a-4793-8574-bb8cc3801e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173239839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.173239839
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1160437053
Short name T369
Test name
Test status
Simulation time 457202435 ps
CPU time 3.75 seconds
Started Jul 16 05:05:33 PM PDT 24
Finished Jul 16 05:05:42 PM PDT 24
Peak memory 225332 kb
Host smart-5b25d45b-a26e-4b0d-ad9e-e41e36d572bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160437053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1160437053
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.527360438
Short name T404
Test name
Test status
Simulation time 5756765552 ps
CPU time 120.56 seconds
Started Jul 16 05:05:31 PM PDT 24
Finished Jul 16 05:07:34 PM PDT 24
Peak memory 278012 kb
Host smart-42973351-c742-46a6-b8b1-69878ec860ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527360438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.527360438
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.2255752615
Short name T79
Test name
Test status
Simulation time 55491125727 ps
CPU time 405.43 seconds
Started Jul 16 05:05:33 PM PDT 24
Finished Jul 16 05:12:22 PM PDT 24
Peak memory 280388 kb
Host smart-ab4c92f4-f20d-48a7-9a93-962909a34b79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2255752615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.2255752615
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.4156619104
Short name T160
Test name
Test status
Simulation time 11585412 ps
CPU time 1.03 seconds
Started Jul 16 05:05:30 PM PDT 24
Finished Jul 16 05:05:34 PM PDT 24
Peak memory 211276 kb
Host smart-a99bd3f0-0748-4a25-887a-924e7cb62dea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156619104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.4156619104
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2999312706
Short name T719
Test name
Test status
Simulation time 64966603 ps
CPU time 1.24 seconds
Started Jul 16 05:05:33 PM PDT 24
Finished Jul 16 05:05:39 PM PDT 24
Peak memory 208440 kb
Host smart-7b1b9717-aa3c-4d32-96b3-a86e28afe0ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999312706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2999312706
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.102895424
Short name T288
Test name
Test status
Simulation time 1024299705 ps
CPU time 11.2 seconds
Started Jul 16 05:05:31 PM PDT 24
Finished Jul 16 05:05:44 PM PDT 24
Peak memory 217720 kb
Host smart-9c4f8c7f-0ff1-4b74-8fed-fd8827515bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102895424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.102895424
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.3187978288
Short name T28
Test name
Test status
Simulation time 211652946 ps
CPU time 3.53 seconds
Started Jul 16 05:05:32 PM PDT 24
Finished Jul 16 05:05:38 PM PDT 24
Peak memory 216708 kb
Host smart-727dd119-616c-4543-81ce-d352fc2a1519
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187978288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.3187978288
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3068778163
Short name T221
Test name
Test status
Simulation time 43694093 ps
CPU time 2.34 seconds
Started Jul 16 05:05:31 PM PDT 24
Finished Jul 16 05:05:36 PM PDT 24
Peak memory 217636 kb
Host smart-f1241e85-9445-4524-bbc2-613b012de734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068778163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3068778163
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2831146297
Short name T222
Test name
Test status
Simulation time 1041020846 ps
CPU time 11.53 seconds
Started Jul 16 05:05:35 PM PDT 24
Finished Jul 16 05:05:52 PM PDT 24
Peak memory 225396 kb
Host smart-830692e6-0b79-469f-9ed1-65adb5af5998
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831146297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2831146297
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.3131625486
Short name T832
Test name
Test status
Simulation time 3185222214 ps
CPU time 16.72 seconds
Started Jul 16 05:05:35 PM PDT 24
Finished Jul 16 05:05:58 PM PDT 24
Peak memory 225460 kb
Host smart-26538323-2459-4e29-bd96-bc3f84fc64a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131625486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
3131625486
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2121628886
Short name T685
Test name
Test status
Simulation time 687694020 ps
CPU time 5.59 seconds
Started Jul 16 05:05:32 PM PDT 24
Finished Jul 16 05:05:40 PM PDT 24
Peak memory 224264 kb
Host smart-369d0ce2-10b6-4355-bfe0-9d3a75e215d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121628886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2121628886
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3759777680
Short name T58
Test name
Test status
Simulation time 38084861 ps
CPU time 2.63 seconds
Started Jul 16 05:05:41 PM PDT 24
Finished Jul 16 05:05:50 PM PDT 24
Peak memory 214112 kb
Host smart-594df61a-c394-4484-a6f5-929c77ea3a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759777680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3759777680
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.4151278587
Short name T593
Test name
Test status
Simulation time 943968168 ps
CPU time 26.31 seconds
Started Jul 16 05:05:32 PM PDT 24
Finished Jul 16 05:06:01 PM PDT 24
Peak memory 250440 kb
Host smart-ab2882f1-3852-4ac9-839a-0758f348dc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151278587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.4151278587
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1312128965
Short name T654
Test name
Test status
Simulation time 185911195 ps
CPU time 7.41 seconds
Started Jul 16 05:05:31 PM PDT 24
Finished Jul 16 05:05:41 PM PDT 24
Peak memory 250460 kb
Host smart-9084de84-7eef-4e59-9e7a-1d5dabac4b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312128965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1312128965
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.3244822916
Short name T140
Test name
Test status
Simulation time 93552284206 ps
CPU time 448.76 seconds
Started Jul 16 05:05:41 PM PDT 24
Finished Jul 16 05:13:16 PM PDT 24
Peak memory 529160 kb
Host smart-8f978be0-2dc8-4224-8c41-d57104db7d6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3244822916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.3244822916
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3328546304
Short name T656
Test name
Test status
Simulation time 12962970 ps
CPU time 1.12 seconds
Started Jul 16 05:05:35 PM PDT 24
Finished Jul 16 05:05:41 PM PDT 24
Peak memory 211336 kb
Host smart-dd4ab4ea-0748-4b46-b232-36dd0dd52e48
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328546304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3328546304
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.208678478
Short name T609
Test name
Test status
Simulation time 17544102 ps
CPU time 1.1 seconds
Started Jul 16 05:05:42 PM PDT 24
Finished Jul 16 05:05:49 PM PDT 24
Peak memory 208372 kb
Host smart-db034d5e-fc52-41b3-9f4a-87e87d6adee3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208678478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.208678478
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3317881801
Short name T457
Test name
Test status
Simulation time 1078012324 ps
CPU time 13.6 seconds
Started Jul 16 05:05:34 PM PDT 24
Finished Jul 16 05:05:52 PM PDT 24
Peak memory 217660 kb
Host smart-0a2b9c97-36e2-4d3b-9174-6d592b5f0c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317881801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3317881801
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.4222597745
Short name T325
Test name
Test status
Simulation time 1112783798 ps
CPU time 24.81 seconds
Started Jul 16 05:05:41 PM PDT 24
Finished Jul 16 05:06:11 PM PDT 24
Peak memory 217076 kb
Host smart-ab948cde-b636-459e-a6a3-6bd14d55d91a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222597745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.4222597745
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2478740341
Short name T813
Test name
Test status
Simulation time 17327851 ps
CPU time 1.63 seconds
Started Jul 16 05:05:31 PM PDT 24
Finished Jul 16 05:05:35 PM PDT 24
Peak memory 217668 kb
Host smart-a5b4142f-83cf-46f5-a845-dc4f08fb9c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478740341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2478740341
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.695027718
Short name T290
Test name
Test status
Simulation time 1781258047 ps
CPU time 16.42 seconds
Started Jul 16 05:05:41 PM PDT 24
Finished Jul 16 05:06:04 PM PDT 24
Peak memory 225496 kb
Host smart-5516af62-dc94-4023-9c98-9586cd98d2e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695027718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_di
gest.695027718
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.315958070
Short name T797
Test name
Test status
Simulation time 320019519 ps
CPU time 7.07 seconds
Started Jul 16 05:05:41 PM PDT 24
Finished Jul 16 05:05:54 PM PDT 24
Peak memory 217508 kb
Host smart-23af5f88-c682-47a7-a287-c6a9e769b1d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315958070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.315958070
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2695160047
Short name T70
Test name
Test status
Simulation time 47186170 ps
CPU time 1.41 seconds
Started Jul 16 05:05:35 PM PDT 24
Finished Jul 16 05:05:42 PM PDT 24
Peak memory 213048 kb
Host smart-67e8ec44-09de-48ba-99a5-9859238269fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695160047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2695160047
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.1546369257
Short name T642
Test name
Test status
Simulation time 348279824 ps
CPU time 27.17 seconds
Started Jul 16 05:05:35 PM PDT 24
Finished Jul 16 05:06:09 PM PDT 24
Peak memory 250380 kb
Host smart-816d56ef-6191-42b2-a54e-4770c5a35891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546369257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1546369257
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2663253192
Short name T819
Test name
Test status
Simulation time 111516154 ps
CPU time 8.85 seconds
Started Jul 16 05:05:35 PM PDT 24
Finished Jul 16 05:05:49 PM PDT 24
Peak memory 250444 kb
Host smart-72ab0939-84ee-41cf-8962-978859801e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663253192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2663253192
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2719940645
Short name T151
Test name
Test status
Simulation time 43015415617 ps
CPU time 679.44 seconds
Started Jul 16 05:05:46 PM PDT 24
Finished Jul 16 05:17:10 PM PDT 24
Peak memory 267228 kb
Host smart-828a8f9f-eb8f-4022-a204-fce3b647d79e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719940645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2719940645
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.452624082
Short name T266
Test name
Test status
Simulation time 14289933 ps
CPU time 0.93 seconds
Started Jul 16 05:05:35 PM PDT 24
Finished Jul 16 05:05:42 PM PDT 24
Peak memory 211240 kb
Host smart-815218c7-9f55-49b1-866c-3ace39b08ae1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452624082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ct
rl_volatile_unlock_smoke.452624082
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1841566042
Short name T386
Test name
Test status
Simulation time 54863252 ps
CPU time 0.9 seconds
Started Jul 16 05:05:42 PM PDT 24
Finished Jul 16 05:05:49 PM PDT 24
Peak memory 208332 kb
Host smart-8703e3f9-27ae-4749-9a93-749b74b1f0d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841566042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1841566042
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2834102562
Short name T490
Test name
Test status
Simulation time 1256131948 ps
CPU time 9.38 seconds
Started Jul 16 05:05:41 PM PDT 24
Finished Jul 16 05:05:57 PM PDT 24
Peak memory 225516 kb
Host smart-e80d2e41-b7be-4d09-8607-064e5a57d7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834102562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2834102562
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2459692485
Short name T367
Test name
Test status
Simulation time 4515820017 ps
CPU time 10.54 seconds
Started Jul 16 05:05:42 PM PDT 24
Finished Jul 16 05:05:58 PM PDT 24
Peak memory 217204 kb
Host smart-891e584d-c985-486d-a3d1-b87c9bff1328
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459692485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2459692485
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1691933078
Short name T344
Test name
Test status
Simulation time 195684880 ps
CPU time 3.4 seconds
Started Jul 16 05:05:41 PM PDT 24
Finished Jul 16 05:05:51 PM PDT 24
Peak memory 217768 kb
Host smart-4243381a-268b-4fb9-8966-49e58eac3f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691933078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1691933078
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.752169807
Short name T690
Test name
Test status
Simulation time 220604025 ps
CPU time 9.09 seconds
Started Jul 16 05:05:49 PM PDT 24
Finished Jul 16 05:06:01 PM PDT 24
Peak memory 225460 kb
Host smart-fd17ed17-1927-4fe1-a089-c984d0c434e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752169807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.752169807
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2116932142
Short name T256
Test name
Test status
Simulation time 1194100861 ps
CPU time 8.56 seconds
Started Jul 16 05:05:51 PM PDT 24
Finished Jul 16 05:06:01 PM PDT 24
Peak memory 217648 kb
Host smart-10c4a7f6-f0ea-4ef2-a00c-37cd4e742ccb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116932142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2116932142
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2060894924
Short name T426
Test name
Test status
Simulation time 1257471701 ps
CPU time 10.99 seconds
Started Jul 16 05:05:43 PM PDT 24
Finished Jul 16 05:05:59 PM PDT 24
Peak memory 225448 kb
Host smart-bb9a4424-34c6-4d9c-8c1a-e42f3c1df2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060894924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2060894924
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1694052638
Short name T246
Test name
Test status
Simulation time 26242028 ps
CPU time 1.08 seconds
Started Jul 16 05:05:41 PM PDT 24
Finished Jul 16 05:05:48 PM PDT 24
Peak memory 212940 kb
Host smart-2e073912-5147-46eb-a514-d2e2253880dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694052638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1694052638
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3272785702
Short name T592
Test name
Test status
Simulation time 1127175150 ps
CPU time 31.2 seconds
Started Jul 16 05:05:40 PM PDT 24
Finished Jul 16 05:06:17 PM PDT 24
Peak memory 245780 kb
Host smart-37f3f68c-a48b-4238-b1cb-83d0181fb876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272785702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3272785702
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3572770962
Short name T846
Test name
Test status
Simulation time 157913725 ps
CPU time 8.98 seconds
Started Jul 16 05:05:42 PM PDT 24
Finished Jul 16 05:05:57 PM PDT 24
Peak memory 243696 kb
Host smart-2e8acf7f-331a-4f95-969b-9b762d0ff207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572770962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3572770962
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3923999406
Short name T468
Test name
Test status
Simulation time 24021251513 ps
CPU time 95.06 seconds
Started Jul 16 05:05:40 PM PDT 24
Finished Jul 16 05:07:22 PM PDT 24
Peak memory 244336 kb
Host smart-a62ef9b2-8dbd-45e6-b1ff-b31d9aa9bce9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923999406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3923999406
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1917703695
Short name T720
Test name
Test status
Simulation time 13942702 ps
CPU time 1 seconds
Started Jul 16 05:05:46 PM PDT 24
Finished Jul 16 05:05:52 PM PDT 24
Peak memory 211264 kb
Host smart-75a56df5-5b81-4496-b8ec-911c29a23be9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917703695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1917703695
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3442010203
Short name T487
Test name
Test status
Simulation time 11263728 ps
CPU time 1.01 seconds
Started Jul 16 05:03:52 PM PDT 24
Finished Jul 16 05:03:55 PM PDT 24
Peak memory 208176 kb
Host smart-b01c8646-a4da-4972-a405-a07d4e11e8d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442010203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3442010203
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.944855031
Short name T572
Test name
Test status
Simulation time 837290805 ps
CPU time 17.46 seconds
Started Jul 16 05:03:49 PM PDT 24
Finished Jul 16 05:04:08 PM PDT 24
Peak memory 217588 kb
Host smart-b37d38fd-506c-4e47-8ea8-e3608bf0fd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944855031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.944855031
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3773307079
Short name T721
Test name
Test status
Simulation time 1121624148 ps
CPU time 4.58 seconds
Started Jul 16 05:03:50 PM PDT 24
Finished Jul 16 05:03:56 PM PDT 24
Peak memory 217064 kb
Host smart-7b9c6df1-ad54-499e-ac40-53f1decaad23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773307079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3773307079
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.58994816
Short name T575
Test name
Test status
Simulation time 13207613206 ps
CPU time 52.78 seconds
Started Jul 16 05:03:48 PM PDT 24
Finished Jul 16 05:04:42 PM PDT 24
Peak memory 218196 kb
Host smart-9481d4d3-e662-402d-a9b8-f675802c0fa7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58994816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_erro
rs.58994816
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1907074859
Short name T402
Test name
Test status
Simulation time 1302318977 ps
CPU time 2.1 seconds
Started Jul 16 05:03:52 PM PDT 24
Finished Jul 16 05:03:55 PM PDT 24
Peak memory 217176 kb
Host smart-81b461d5-942a-48cc-a728-2645604d9b5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907074859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1
907074859
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.4139387630
Short name T820
Test name
Test status
Simulation time 1533975566 ps
CPU time 5.42 seconds
Started Jul 16 05:03:46 PM PDT 24
Finished Jul 16 05:03:52 PM PDT 24
Peak memory 221208 kb
Host smart-b344f640-6171-4911-8629-a776e895f62f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139387630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.4139387630
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3445259695
Short name T620
Test name
Test status
Simulation time 3639789896 ps
CPU time 24.5 seconds
Started Jul 16 05:03:49 PM PDT 24
Finished Jul 16 05:04:15 PM PDT 24
Peak memory 217008 kb
Host smart-3f0d7b0c-7815-40fa-a575-0d7874d35f76
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445259695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3445259695
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2203523670
Short name T543
Test name
Test status
Simulation time 128104070 ps
CPU time 3.22 seconds
Started Jul 16 05:03:47 PM PDT 24
Finished Jul 16 05:03:51 PM PDT 24
Peak memory 216972 kb
Host smart-704b51d6-13bb-4cc3-a5af-a285b4cde517
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203523670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2203523670
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.4214810051
Short name T294
Test name
Test status
Simulation time 13856874885 ps
CPU time 55.05 seconds
Started Jul 16 05:03:51 PM PDT 24
Finished Jul 16 05:04:47 PM PDT 24
Peak memory 266732 kb
Host smart-00f00e71-878a-452b-8e96-f841e04aa51a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214810051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.4214810051
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2792259850
Short name T774
Test name
Test status
Simulation time 690046437 ps
CPU time 10.8 seconds
Started Jul 16 05:03:49 PM PDT 24
Finished Jul 16 05:04:01 PM PDT 24
Peak memory 223456 kb
Host smart-d50438f5-250f-4fc7-8239-3dcc9485a2eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792259850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2792259850
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3926152801
Short name T671
Test name
Test status
Simulation time 33550530 ps
CPU time 2.27 seconds
Started Jul 16 05:03:52 PM PDT 24
Finished Jul 16 05:03:55 PM PDT 24
Peak memory 217620 kb
Host smart-3232783b-a61d-41d8-a7f9-eb2a394a5b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926152801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3926152801
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3619872081
Short name T72
Test name
Test status
Simulation time 278551913 ps
CPU time 6.71 seconds
Started Jul 16 05:03:47 PM PDT 24
Finished Jul 16 05:03:54 PM PDT 24
Peak memory 217040 kb
Host smart-fe67647b-34e6-4302-a1ff-c1ba30ed3cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619872081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3619872081
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.4182812300
Short name T82
Test name
Test status
Simulation time 106980590 ps
CPU time 23.93 seconds
Started Jul 16 05:03:47 PM PDT 24
Finished Jul 16 05:04:12 PM PDT 24
Peak memory 281792 kb
Host smart-097901eb-e9de-4a1b-95ff-af6d20624e10
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182812300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.4182812300
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3371100455
Short name T443
Test name
Test status
Simulation time 963041858 ps
CPU time 9.16 seconds
Started Jul 16 05:03:48 PM PDT 24
Finished Jul 16 05:03:58 PM PDT 24
Peak memory 225348 kb
Host smart-890773e7-da0e-4257-9b31-ee1c434da527
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371100455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3371100455
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1543333910
Short name T710
Test name
Test status
Simulation time 644353691 ps
CPU time 12.42 seconds
Started Jul 16 05:03:50 PM PDT 24
Finished Jul 16 05:04:04 PM PDT 24
Peak memory 217584 kb
Host smart-54229401-d2b8-4d8f-ba3a-41f995980f3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543333910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
543333910
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.716947924
Short name T836
Test name
Test status
Simulation time 171954002 ps
CPU time 7.37 seconds
Started Jul 16 05:03:49 PM PDT 24
Finished Jul 16 05:03:58 PM PDT 24
Peak memory 224056 kb
Host smart-e790b1aa-5e60-47e7-b6b8-868d6a5bb12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716947924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.716947924
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.165269399
Short name T625
Test name
Test status
Simulation time 308474158 ps
CPU time 2.66 seconds
Started Jul 16 05:03:49 PM PDT 24
Finished Jul 16 05:03:53 PM PDT 24
Peak memory 214232 kb
Host smart-c7029f23-9207-412b-a97a-c2f4b2d339f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165269399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.165269399
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2892671658
Short name T714
Test name
Test status
Simulation time 233298502 ps
CPU time 29.64 seconds
Started Jul 16 05:03:49 PM PDT 24
Finished Jul 16 05:04:20 PM PDT 24
Peak memory 250516 kb
Host smart-cd15e00b-ad2e-42a3-935d-4c1bee148e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892671658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2892671658
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3547574386
Short name T453
Test name
Test status
Simulation time 343807237 ps
CPU time 7.74 seconds
Started Jul 16 05:03:49 PM PDT 24
Finished Jul 16 05:03:58 PM PDT 24
Peak memory 250116 kb
Host smart-de08836a-4ca3-4d15-9030-ac377fc818ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547574386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3547574386
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1928199916
Short name T348
Test name
Test status
Simulation time 18116128439 ps
CPU time 441.63 seconds
Started Jul 16 05:03:46 PM PDT 24
Finished Jul 16 05:11:08 PM PDT 24
Peak memory 283160 kb
Host smart-c80f351c-0fcd-4bd5-bfa1-af6cefe485b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928199916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1928199916
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2664414209
Short name T229
Test name
Test status
Simulation time 18316902 ps
CPU time 0.9 seconds
Started Jul 16 05:03:54 PM PDT 24
Finished Jul 16 05:03:56 PM PDT 24
Peak memory 208264 kb
Host smart-761a0cbd-e6d7-4823-9772-1729275dfc5e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664414209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2664414209
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.425021633
Short name T635
Test name
Test status
Simulation time 361877122 ps
CPU time 1.91 seconds
Started Jul 16 05:05:46 PM PDT 24
Finished Jul 16 05:05:52 PM PDT 24
Peak memory 208556 kb
Host smart-60abaf6e-e0ae-478e-98ee-6e637e423e00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425021633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.425021633
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3189541919
Short name T319
Test name
Test status
Simulation time 581123478 ps
CPU time 14.71 seconds
Started Jul 16 05:05:43 PM PDT 24
Finished Jul 16 05:06:03 PM PDT 24
Peak memory 225468 kb
Host smart-03201cb4-8f0c-4fd2-9755-ea157f84fef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189541919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3189541919
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.3688386782
Short name T569
Test name
Test status
Simulation time 3344092571 ps
CPU time 19.94 seconds
Started Jul 16 05:05:55 PM PDT 24
Finished Jul 16 05:06:17 PM PDT 24
Peak memory 217132 kb
Host smart-6793c762-0e56-4a22-ae55-d05d7a6afca9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688386782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3688386782
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2376984284
Short name T155
Test name
Test status
Simulation time 66421462 ps
CPU time 2.64 seconds
Started Jul 16 05:05:43 PM PDT 24
Finished Jul 16 05:05:51 PM PDT 24
Peak memory 221812 kb
Host smart-6b8e5af1-ec71-4e49-9552-ab088ed9eafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376984284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2376984284
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.2201864931
Short name T197
Test name
Test status
Simulation time 1629475253 ps
CPU time 17.11 seconds
Started Jul 16 05:05:43 PM PDT 24
Finished Jul 16 05:06:06 PM PDT 24
Peak memory 218368 kb
Host smart-c683f7c7-d932-4957-a649-e4d77f54c6ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201864931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.2201864931
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2761521693
Short name T643
Test name
Test status
Simulation time 732181932 ps
CPU time 14.34 seconds
Started Jul 16 05:05:46 PM PDT 24
Finished Jul 16 05:06:05 PM PDT 24
Peak memory 225436 kb
Host smart-8a4270b5-95fe-4659-9164-77b149c8a7e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761521693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2761521693
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1923285859
Short name T392
Test name
Test status
Simulation time 2478465278 ps
CPU time 7.46 seconds
Started Jul 16 05:05:44 PM PDT 24
Finished Jul 16 05:05:57 PM PDT 24
Peak memory 217732 kb
Host smart-2e67e5a7-5256-40f6-a139-09bafc2d0ee9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923285859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1923285859
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.4250961040
Short name T602
Test name
Test status
Simulation time 400665700 ps
CPU time 9.05 seconds
Started Jul 16 05:05:40 PM PDT 24
Finished Jul 16 05:05:55 PM PDT 24
Peak memory 225492 kb
Host smart-76eb2a81-e6ba-4929-b060-0f45de852f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250961040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.4250961040
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2515222197
Short name T292
Test name
Test status
Simulation time 66659484 ps
CPU time 3.16 seconds
Started Jul 16 05:05:39 PM PDT 24
Finished Jul 16 05:05:49 PM PDT 24
Peak memory 217140 kb
Host smart-fc5800f0-d292-460d-a82b-57e7dad4e769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515222197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2515222197
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.17980066
Short name T732
Test name
Test status
Simulation time 190367066 ps
CPU time 16.29 seconds
Started Jul 16 05:05:41 PM PDT 24
Finished Jul 16 05:06:03 PM PDT 24
Peak memory 250388 kb
Host smart-5ac4a962-6aca-41b6-b3c9-1e8a02ed2447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17980066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.17980066
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1348815268
Short name T436
Test name
Test status
Simulation time 313028726 ps
CPU time 8.85 seconds
Started Jul 16 05:05:43 PM PDT 24
Finished Jul 16 05:05:57 PM PDT 24
Peak memory 250356 kb
Host smart-7d7ec987-cfe7-40bb-ad9f-cc69bd06b982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348815268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1348815268
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3113247388
Short name T570
Test name
Test status
Simulation time 39382700 ps
CPU time 0.81 seconds
Started Jul 16 05:05:49 PM PDT 24
Finished Jul 16 05:05:52 PM PDT 24
Peak memory 207624 kb
Host smart-865261bc-9ab0-47da-a120-d451fe91b42c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113247388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3113247388
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3989128530
Short name T586
Test name
Test status
Simulation time 12840956 ps
CPU time 0.84 seconds
Started Jul 16 05:05:41 PM PDT 24
Finished Jul 16 05:05:48 PM PDT 24
Peak memory 208112 kb
Host smart-0067f447-0337-4cd1-88ba-97bf7b537104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989128530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3989128530
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1784295900
Short name T829
Test name
Test status
Simulation time 303519398 ps
CPU time 12.15 seconds
Started Jul 16 05:05:50 PM PDT 24
Finished Jul 16 05:06:04 PM PDT 24
Peak memory 217732 kb
Host smart-2d70b4fa-bc2c-432f-ae36-1fa5573aa8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784295900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1784295900
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.820429145
Short name T701
Test name
Test status
Simulation time 1472854070 ps
CPU time 6.33 seconds
Started Jul 16 05:05:55 PM PDT 24
Finished Jul 16 05:06:04 PM PDT 24
Peak memory 217064 kb
Host smart-727caf7c-298b-4eca-be10-5cfb9f9ff68e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820429145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.820429145
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3464486754
Short name T279
Test name
Test status
Simulation time 126452960 ps
CPU time 2.52 seconds
Started Jul 16 05:05:44 PM PDT 24
Finished Jul 16 05:05:52 PM PDT 24
Peak memory 217716 kb
Host smart-b8c88e72-965b-484c-89ce-c4b4084d6940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464486754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3464486754
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1401963394
Short name T626
Test name
Test status
Simulation time 239107822 ps
CPU time 8.43 seconds
Started Jul 16 05:05:43 PM PDT 24
Finished Jul 16 05:05:57 PM PDT 24
Peak memory 225408 kb
Host smart-bfb950de-b223-4ca4-9f1f-54e0ef313f47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401963394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1401963394
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3584873061
Short name T533
Test name
Test status
Simulation time 274715720 ps
CPU time 8.38 seconds
Started Jul 16 05:05:41 PM PDT 24
Finished Jul 16 05:05:55 PM PDT 24
Peak memory 225420 kb
Host smart-6600b499-c2e7-4530-acfb-936a9842b2aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584873061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3584873061
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2556872545
Short name T858
Test name
Test status
Simulation time 644765614 ps
CPU time 11.85 seconds
Started Jul 16 05:05:49 PM PDT 24
Finished Jul 16 05:06:03 PM PDT 24
Peak memory 224724 kb
Host smart-6a5a9751-7294-4f2a-855a-204a41a25db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556872545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2556872545
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2679236379
Short name T579
Test name
Test status
Simulation time 50258922 ps
CPU time 3.19 seconds
Started Jul 16 05:05:44 PM PDT 24
Finished Jul 16 05:05:52 PM PDT 24
Peak memory 217044 kb
Host smart-bcb8b8fd-daed-46b9-bfe0-8106ff9d8848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679236379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2679236379
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.274847217
Short name T511
Test name
Test status
Simulation time 220069089 ps
CPU time 21.79 seconds
Started Jul 16 05:05:45 PM PDT 24
Finished Jul 16 05:06:11 PM PDT 24
Peak memory 250380 kb
Host smart-95405c03-566d-4262-8e79-8e4519e26903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274847217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.274847217
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1354753947
Short name T352
Test name
Test status
Simulation time 183073068 ps
CPU time 9.5 seconds
Started Jul 16 05:05:42 PM PDT 24
Finished Jul 16 05:05:58 PM PDT 24
Peak memory 250468 kb
Host smart-907a9521-6f77-4236-b1dd-375d75e65bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354753947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1354753947
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2889868979
Short name T361
Test name
Test status
Simulation time 2092904600 ps
CPU time 56.21 seconds
Started Jul 16 05:05:45 PM PDT 24
Finished Jul 16 05:06:46 PM PDT 24
Peak memory 250412 kb
Host smart-d04f7f88-bd51-4dfb-b579-f8da8c8ece79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889868979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2889868979
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.2875044694
Short name T143
Test name
Test status
Simulation time 66446015508 ps
CPU time 482.59 seconds
Started Jul 16 05:05:40 PM PDT 24
Finished Jul 16 05:13:49 PM PDT 24
Peak memory 479828 kb
Host smart-e9ba936d-d756-4c2d-8178-e954f0e8ce8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2875044694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.2875044694
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1945780420
Short name T298
Test name
Test status
Simulation time 26451523 ps
CPU time 0.95 seconds
Started Jul 16 05:05:47 PM PDT 24
Finished Jul 16 05:05:52 PM PDT 24
Peak memory 208516 kb
Host smart-8171e592-bf83-464e-96ae-539e5024f779
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945780420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1945780420
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1645591270
Short name T496
Test name
Test status
Simulation time 128298995 ps
CPU time 1.19 seconds
Started Jul 16 05:05:44 PM PDT 24
Finished Jul 16 05:05:50 PM PDT 24
Peak memory 208340 kb
Host smart-028d9b96-1b50-438d-9c86-8c594c39f52f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645591270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1645591270
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1846625837
Short name T380
Test name
Test status
Simulation time 801535020 ps
CPU time 19.71 seconds
Started Jul 16 05:05:41 PM PDT 24
Finished Jul 16 05:06:07 PM PDT 24
Peak memory 217640 kb
Host smart-3aa3d074-2151-4243-ba20-6603358c10d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846625837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1846625837
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1528688228
Short name T334
Test name
Test status
Simulation time 1073918357 ps
CPU time 11.16 seconds
Started Jul 16 05:05:42 PM PDT 24
Finished Jul 16 05:05:59 PM PDT 24
Peak memory 217072 kb
Host smart-d674d02b-c52d-4082-80a1-4a500cb2eba6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528688228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1528688228
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3835683385
Short name T700
Test name
Test status
Simulation time 147872117 ps
CPU time 2.26 seconds
Started Jul 16 05:05:55 PM PDT 24
Finished Jul 16 05:06:00 PM PDT 24
Peak memory 217640 kb
Host smart-f3f9b4ae-20a4-4e2b-a2ff-df881a8ce764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835683385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3835683385
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.4220479882
Short name T696
Test name
Test status
Simulation time 491115537 ps
CPU time 11.16 seconds
Started Jul 16 05:05:45 PM PDT 24
Finished Jul 16 05:06:01 PM PDT 24
Peak memory 225448 kb
Host smart-8fb82c37-c1d6-4586-a2c7-74afe9be25f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220479882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.4220479882
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2129694059
Short name T251
Test name
Test status
Simulation time 224318764 ps
CPU time 10.17 seconds
Started Jul 16 05:05:45 PM PDT 24
Finished Jul 16 05:06:00 PM PDT 24
Peak memory 225384 kb
Host smart-970d2093-40a6-4804-8c56-19dced9511c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129694059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2129694059
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1806189810
Short name T434
Test name
Test status
Simulation time 835868611 ps
CPU time 9.35 seconds
Started Jul 16 05:05:44 PM PDT 24
Finished Jul 16 05:05:58 PM PDT 24
Peak memory 225460 kb
Host smart-c9ef946c-2807-43ad-9e4c-282e58fa3cc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806189810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1806189810
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3088610829
Short name T445
Test name
Test status
Simulation time 112111589 ps
CPU time 3.43 seconds
Started Jul 16 05:05:55 PM PDT 24
Finished Jul 16 05:06:02 PM PDT 24
Peak memory 217064 kb
Host smart-14313fa5-e467-44e6-97ce-fcfc8e1e20a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088610829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3088610829
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3188689253
Short name T309
Test name
Test status
Simulation time 286861838 ps
CPU time 18.63 seconds
Started Jul 16 05:05:41 PM PDT 24
Finished Jul 16 05:06:06 PM PDT 24
Peak memory 244780 kb
Host smart-e7981c94-685a-4c63-a812-d85241d4284d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188689253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3188689253
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.4136836475
Short name T418
Test name
Test status
Simulation time 1152023189 ps
CPU time 6.12 seconds
Started Jul 16 05:05:50 PM PDT 24
Finished Jul 16 05:05:58 PM PDT 24
Peak memory 242076 kb
Host smart-6164a618-11bf-4285-9542-d42a2a4a0e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136836475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.4136836475
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2095637711
Short name T634
Test name
Test status
Simulation time 6576185652 ps
CPU time 132.96 seconds
Started Jul 16 05:05:42 PM PDT 24
Finished Jul 16 05:08:01 PM PDT 24
Peak memory 283292 kb
Host smart-53375580-e5f7-4dab-bf1f-24b505a38887
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095637711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2095637711
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.211685757
Short name T44
Test name
Test status
Simulation time 39133643480 ps
CPU time 814.99 seconds
Started Jul 16 05:05:44 PM PDT 24
Finished Jul 16 05:19:24 PM PDT 24
Peak memory 356012 kb
Host smart-a2c269a2-c71e-429e-855c-a80d35683254
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=211685757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.211685757
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3252195602
Short name T731
Test name
Test status
Simulation time 29106440 ps
CPU time 0.74 seconds
Started Jul 16 05:05:43 PM PDT 24
Finished Jul 16 05:05:49 PM PDT 24
Peak memory 206840 kb
Host smart-96a16bf1-cfaf-4b50-aecc-884ff16217cc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252195602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3252195602
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3655959056
Short name T553
Test name
Test status
Simulation time 57605916 ps
CPU time 0.93 seconds
Started Jul 16 05:05:54 PM PDT 24
Finished Jul 16 05:05:58 PM PDT 24
Peak memory 208248 kb
Host smart-f2bebe70-ff5a-485d-8acc-8c766f53895a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655959056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3655959056
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3399926127
Short name T608
Test name
Test status
Simulation time 736196344 ps
CPU time 15.01 seconds
Started Jul 16 05:05:42 PM PDT 24
Finished Jul 16 05:06:03 PM PDT 24
Peak memory 225524 kb
Host smart-7bcde42a-45c5-42a5-914d-e862f3a313db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399926127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3399926127
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1749057738
Short name T328
Test name
Test status
Simulation time 907033043 ps
CPU time 12.38 seconds
Started Jul 16 05:05:59 PM PDT 24
Finished Jul 16 05:06:14 PM PDT 24
Peak memory 217040 kb
Host smart-101699be-2cea-4911-916e-08bc636f18b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749057738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1749057738
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.4099470495
Short name T628
Test name
Test status
Simulation time 125130034 ps
CPU time 3.92 seconds
Started Jul 16 05:05:42 PM PDT 24
Finished Jul 16 05:05:52 PM PDT 24
Peak memory 217716 kb
Host smart-141a7587-f632-4882-b4af-91f27276a24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099470495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.4099470495
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.3466343305
Short name T306
Test name
Test status
Simulation time 3216780322 ps
CPU time 25.65 seconds
Started Jul 16 05:05:59 PM PDT 24
Finished Jul 16 05:06:26 PM PDT 24
Peak memory 218524 kb
Host smart-d8439e0a-68c2-4de8-8ad3-7e4b3a9fade2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466343305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.3466343305
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3283825506
Short name T89
Test name
Test status
Simulation time 168397457 ps
CPU time 8.46 seconds
Started Jul 16 05:06:06 PM PDT 24
Finished Jul 16 05:06:16 PM PDT 24
Peak memory 225396 kb
Host smart-60775ae0-5a54-4447-93fa-d4958e82b237
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283825506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3283825506
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2320696387
Short name T313
Test name
Test status
Simulation time 993893629 ps
CPU time 10.48 seconds
Started Jul 16 05:05:55 PM PDT 24
Finished Jul 16 05:06:09 PM PDT 24
Peak memory 225360 kb
Host smart-040c783a-5136-40c9-ba03-ff96c640bb49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320696387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2320696387
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2366246041
Short name T547
Test name
Test status
Simulation time 288540015 ps
CPU time 11.67 seconds
Started Jul 16 05:05:58 PM PDT 24
Finished Jul 16 05:06:12 PM PDT 24
Peak memory 225428 kb
Host smart-380c8478-fb3f-4536-b283-911a77bb7221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366246041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2366246041
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1946082295
Short name T84
Test name
Test status
Simulation time 13072106 ps
CPU time 1.04 seconds
Started Jul 16 05:05:55 PM PDT 24
Finished Jul 16 05:05:59 PM PDT 24
Peak memory 211536 kb
Host smart-8d13a8e8-12e0-44f7-a662-ca82ee98219e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946082295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1946082295
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.73417806
Short name T80
Test name
Test status
Simulation time 430047788 ps
CPU time 21.18 seconds
Started Jul 16 05:05:55 PM PDT 24
Finished Jul 16 05:06:19 PM PDT 24
Peak memory 245996 kb
Host smart-baa5b039-2ac4-4287-b75d-58cfac238158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73417806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.73417806
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3863673054
Short name T395
Test name
Test status
Simulation time 321464937 ps
CPU time 8.76 seconds
Started Jul 16 05:05:56 PM PDT 24
Finished Jul 16 05:06:08 PM PDT 24
Peak memory 250384 kb
Host smart-cb6576b0-99ac-4335-8919-702c02ae9c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863673054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3863673054
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2749330942
Short name T810
Test name
Test status
Simulation time 5761256941 ps
CPU time 90.36 seconds
Started Jul 16 05:05:55 PM PDT 24
Finished Jul 16 05:07:28 PM PDT 24
Peak memory 278052 kb
Host smart-a6c91976-d823-4298-b17e-f94b7b8d4f5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749330942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2749330942
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.4272625044
Short name T152
Test name
Test status
Simulation time 21938458 ps
CPU time 1.01 seconds
Started Jul 16 05:05:54 PM PDT 24
Finished Jul 16 05:05:58 PM PDT 24
Peak memory 211240 kb
Host smart-6d2e4a9c-7531-47b6-b029-d48358f6714c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272625044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.4272625044
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2177826519
Short name T574
Test name
Test status
Simulation time 14939989 ps
CPU time 1.09 seconds
Started Jul 16 05:05:59 PM PDT 24
Finished Jul 16 05:06:02 PM PDT 24
Peak memory 208340 kb
Host smart-f0895780-274b-4d47-81ee-4f99aed4bf10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177826519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2177826519
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.3299760342
Short name T803
Test name
Test status
Simulation time 886151251 ps
CPU time 12.75 seconds
Started Jul 16 05:05:53 PM PDT 24
Finished Jul 16 05:06:07 PM PDT 24
Peak memory 217636 kb
Host smart-87b131fa-00d3-48f2-80fd-5cd4cafdb33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299760342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3299760342
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3007279762
Short name T525
Test name
Test status
Simulation time 1637980231 ps
CPU time 4.06 seconds
Started Jul 16 05:05:53 PM PDT 24
Finished Jul 16 05:05:58 PM PDT 24
Peak memory 217028 kb
Host smart-d9a8ffef-b773-40a3-a880-80a15eaded24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007279762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3007279762
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.472819508
Short name T354
Test name
Test status
Simulation time 24474050 ps
CPU time 1.85 seconds
Started Jul 16 05:05:59 PM PDT 24
Finished Jul 16 05:06:02 PM PDT 24
Peak memory 217720 kb
Host smart-8e74bb40-efbe-41ca-860a-e9b6fac8d9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472819508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.472819508
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.4048379159
Short name T585
Test name
Test status
Simulation time 392983501 ps
CPU time 11.01 seconds
Started Jul 16 05:05:58 PM PDT 24
Finished Jul 16 05:06:11 PM PDT 24
Peak memory 225384 kb
Host smart-e3375b30-87b8-48be-a409-20c62e23664c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048379159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.4048379159
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1793081555
Short name T686
Test name
Test status
Simulation time 788940723 ps
CPU time 15.15 seconds
Started Jul 16 05:05:56 PM PDT 24
Finished Jul 16 05:06:14 PM PDT 24
Peak memory 217652 kb
Host smart-133ad4e9-11ae-4b60-9481-591d423ad93c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793081555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
1793081555
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.583116824
Short name T505
Test name
Test status
Simulation time 516645082 ps
CPU time 12.15 seconds
Started Jul 16 05:05:54 PM PDT 24
Finished Jul 16 05:06:08 PM PDT 24
Peak memory 225160 kb
Host smart-b2321b28-d693-40f7-b9ae-278696752437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583116824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.583116824
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1488074260
Short name T823
Test name
Test status
Simulation time 221370004 ps
CPU time 2.81 seconds
Started Jul 16 05:06:02 PM PDT 24
Finished Jul 16 05:06:06 PM PDT 24
Peak memory 213920 kb
Host smart-e13ec454-7980-47ae-8d94-e9500495eef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488074260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1488074260
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.3211179686
Short name T419
Test name
Test status
Simulation time 1552411972 ps
CPU time 34.28 seconds
Started Jul 16 05:06:06 PM PDT 24
Finished Jul 16 05:06:42 PM PDT 24
Peak memory 247136 kb
Host smart-41f32647-00b8-4fa3-a713-6cbe92583e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211179686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3211179686
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1210071199
Short name T676
Test name
Test status
Simulation time 102939391 ps
CPU time 6.32 seconds
Started Jul 16 05:05:54 PM PDT 24
Finished Jul 16 05:06:03 PM PDT 24
Peak memory 246760 kb
Host smart-dfdac1d3-2802-4676-9158-1bd2ae908608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210071199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1210071199
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.216328756
Short name T469
Test name
Test status
Simulation time 21301302496 ps
CPU time 109.61 seconds
Started Jul 16 05:05:54 PM PDT 24
Finished Jul 16 05:07:46 PM PDT 24
Peak memory 277092 kb
Host smart-dd325ce8-0c69-4220-a7d1-ee5232e8473f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216328756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.216328756
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.374896843
Short name T95
Test name
Test status
Simulation time 10255787919 ps
CPU time 273.29 seconds
Started Jul 16 05:05:52 PM PDT 24
Finished Jul 16 05:10:27 PM PDT 24
Peak memory 332588 kb
Host smart-bd1705b7-a683-4d2e-892b-ff9c85e15fc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=374896843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.374896843
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1833214580
Short name T716
Test name
Test status
Simulation time 12359885 ps
CPU time 1.1 seconds
Started Jul 16 05:06:01 PM PDT 24
Finished Jul 16 05:06:03 PM PDT 24
Peak memory 211340 kb
Host smart-359857ee-b59a-4260-8996-4bc81c062241
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833214580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1833214580
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1696410728
Short name T254
Test name
Test status
Simulation time 66615971 ps
CPU time 1.26 seconds
Started Jul 16 05:06:00 PM PDT 24
Finished Jul 16 05:06:03 PM PDT 24
Peak memory 208392 kb
Host smart-a27467b8-1bb4-40fa-899f-2fb95b1175de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696410728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1696410728
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3242566963
Short name T802
Test name
Test status
Simulation time 715908404 ps
CPU time 8.46 seconds
Started Jul 16 05:05:54 PM PDT 24
Finished Jul 16 05:06:04 PM PDT 24
Peak memory 225432 kb
Host smart-36774fbe-9dc2-4f13-b3a5-e35bca827ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242566963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3242566963
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.1858889573
Short name T808
Test name
Test status
Simulation time 1639073314 ps
CPU time 6.12 seconds
Started Jul 16 05:05:55 PM PDT 24
Finished Jul 16 05:06:04 PM PDT 24
Peak memory 216936 kb
Host smart-8b333b45-b071-49d1-8aab-a061c19ae764
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858889573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.1858889573
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1030297017
Short name T210
Test name
Test status
Simulation time 302067401 ps
CPU time 3.64 seconds
Started Jul 16 05:05:54 PM PDT 24
Finished Jul 16 05:06:00 PM PDT 24
Peak memory 217624 kb
Host smart-33437b46-240d-4d7a-a276-ac9cc8ab2f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030297017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1030297017
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1372767981
Short name T215
Test name
Test status
Simulation time 495569106 ps
CPU time 18.55 seconds
Started Jul 16 05:06:06 PM PDT 24
Finished Jul 16 05:06:27 PM PDT 24
Peak memory 225336 kb
Host smart-94c64e8c-bd23-48bb-97b0-735fd3917820
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372767981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1372767981
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.44042118
Short name T842
Test name
Test status
Simulation time 1118410421 ps
CPU time 12.12 seconds
Started Jul 16 05:05:59 PM PDT 24
Finished Jul 16 05:06:13 PM PDT 24
Peak memory 225372 kb
Host smart-cdd5f80f-92f7-4d69-bbca-ad78474c3b98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44042118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_dig
est.44042118
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2939403089
Short name T657
Test name
Test status
Simulation time 3464058357 ps
CPU time 8.29 seconds
Started Jul 16 05:05:55 PM PDT 24
Finished Jul 16 05:06:06 PM PDT 24
Peak memory 225520 kb
Host smart-02fe8334-2346-4688-8081-e89fde490c17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939403089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2939403089
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3005051319
Short name T713
Test name
Test status
Simulation time 333457940 ps
CPU time 8.12 seconds
Started Jul 16 05:05:53 PM PDT 24
Finished Jul 16 05:06:03 PM PDT 24
Peak memory 224568 kb
Host smart-059c00ed-7deb-47fd-9503-5b76b08dfe71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005051319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3005051319
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3735768078
Short name T794
Test name
Test status
Simulation time 46682007 ps
CPU time 1.09 seconds
Started Jul 16 05:05:52 PM PDT 24
Finished Jul 16 05:05:55 PM PDT 24
Peak memory 213020 kb
Host smart-3fd742cb-a409-4237-833b-4ce2a123f9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735768078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3735768078
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.721009543
Short name T737
Test name
Test status
Simulation time 265491990 ps
CPU time 25.82 seconds
Started Jul 16 05:06:07 PM PDT 24
Finished Jul 16 05:06:35 PM PDT 24
Peak memory 250412 kb
Host smart-fdd5c036-cf2c-47dc-9ee5-e08fc89714de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721009543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.721009543
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1206510496
Short name T232
Test name
Test status
Simulation time 70122726 ps
CPU time 7.29 seconds
Started Jul 16 05:05:58 PM PDT 24
Finished Jul 16 05:06:07 PM PDT 24
Peak memory 242584 kb
Host smart-30163c19-cf73-4956-80b1-154275f1479c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206510496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1206510496
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2376208433
Short name T16
Test name
Test status
Simulation time 4654901445 ps
CPU time 145.87 seconds
Started Jul 16 05:05:53 PM PDT 24
Finished Jul 16 05:08:20 PM PDT 24
Peak memory 250484 kb
Host smart-a834ddad-6aec-4add-a37c-d596315768be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376208433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2376208433
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3934615508
Short name T31
Test name
Test status
Simulation time 120216994 ps
CPU time 0.9 seconds
Started Jul 16 05:05:59 PM PDT 24
Finished Jul 16 05:06:02 PM PDT 24
Peak memory 208268 kb
Host smart-537930da-20f5-4810-a12c-d2d34c85bea6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934615508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3934615508
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.1337946093
Short name T638
Test name
Test status
Simulation time 99029233 ps
CPU time 1.13 seconds
Started Jul 16 05:05:54 PM PDT 24
Finished Jul 16 05:05:58 PM PDT 24
Peak memory 208164 kb
Host smart-87f6bd51-1ba5-4300-a9d3-284a660b014d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337946093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1337946093
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3894653907
Short name T604
Test name
Test status
Simulation time 756209484 ps
CPU time 18.64 seconds
Started Jul 16 05:06:06 PM PDT 24
Finished Jul 16 05:06:27 PM PDT 24
Peak memory 216980 kb
Host smart-12f64191-8b90-49b8-96fb-e39f23a7df2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894653907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3894653907
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2198238802
Short name T318
Test name
Test status
Simulation time 360945889 ps
CPU time 4.49 seconds
Started Jul 16 05:05:54 PM PDT 24
Finished Jul 16 05:06:01 PM PDT 24
Peak memory 217684 kb
Host smart-4d8e3a8c-b357-42d8-aad8-7668cbd745b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198238802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2198238802
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1412974833
Short name T440
Test name
Test status
Simulation time 424236150 ps
CPU time 13.14 seconds
Started Jul 16 05:06:06 PM PDT 24
Finished Jul 16 05:06:21 PM PDT 24
Peak memory 218312 kb
Host smart-aba7df1c-0950-446e-8170-b9fb5cdc60c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412974833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1412974833
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3573347010
Short name T513
Test name
Test status
Simulation time 346978286 ps
CPU time 9.8 seconds
Started Jul 16 05:05:53 PM PDT 24
Finished Jul 16 05:06:05 PM PDT 24
Peak memory 225496 kb
Host smart-ace83558-88d6-41cf-b2dc-bb843a0f99ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573347010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3573347010
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3547270576
Short name T855
Test name
Test status
Simulation time 1236378574 ps
CPU time 19.96 seconds
Started Jul 16 05:05:57 PM PDT 24
Finished Jul 16 05:06:19 PM PDT 24
Peak memory 217596 kb
Host smart-4338c1c1-a537-461d-8d7f-4198e5622ed7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547270576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3547270576
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.2092901977
Short name T546
Test name
Test status
Simulation time 301414087 ps
CPU time 11.9 seconds
Started Jul 16 05:06:02 PM PDT 24
Finished Jul 16 05:06:15 PM PDT 24
Peak memory 217772 kb
Host smart-12e0fdd5-0063-40de-b5cb-4aacfe31a163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092901977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2092901977
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2594854375
Short name T206
Test name
Test status
Simulation time 22396148 ps
CPU time 1.17 seconds
Started Jul 16 05:06:02 PM PDT 24
Finished Jul 16 05:06:04 PM PDT 24
Peak memory 212960 kb
Host smart-df9f5658-d88c-480a-91b8-bc9ac8337c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594854375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2594854375
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2678219063
Short name T478
Test name
Test status
Simulation time 4662696682 ps
CPU time 18.45 seconds
Started Jul 16 05:05:57 PM PDT 24
Finished Jul 16 05:06:18 PM PDT 24
Peak memory 245412 kb
Host smart-517c49f6-92fd-4b88-9744-87500ed8fa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678219063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2678219063
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3603502336
Short name T207
Test name
Test status
Simulation time 251595675 ps
CPU time 5.9 seconds
Started Jul 16 05:05:55 PM PDT 24
Finished Jul 16 05:06:04 PM PDT 24
Peak memory 246084 kb
Host smart-7d76d13f-b5c5-4058-ad68-966317d7b3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603502336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3603502336
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.451792947
Short name T775
Test name
Test status
Simulation time 22804559929 ps
CPU time 173.32 seconds
Started Jul 16 05:05:54 PM PDT 24
Finished Jul 16 05:08:50 PM PDT 24
Peak memory 283224 kb
Host smart-732b5463-dfa1-4b08-87d3-2079a686d687
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451792947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.451792947
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3410519545
Short name T655
Test name
Test status
Simulation time 10371109 ps
CPU time 0.87 seconds
Started Jul 16 05:05:53 PM PDT 24
Finished Jul 16 05:05:56 PM PDT 24
Peak memory 207696 kb
Host smart-1f5cd990-1f9c-4b63-8db6-a41435142586
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410519545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3410519545
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2453815029
Short name T156
Test name
Test status
Simulation time 85224152 ps
CPU time 0.87 seconds
Started Jul 16 05:06:05 PM PDT 24
Finished Jul 16 05:06:07 PM PDT 24
Peak memory 208232 kb
Host smart-2ccdcbf3-b1e6-4e3a-aa5e-5c9961efc5da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453815029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2453815029
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.677304812
Short name T755
Test name
Test status
Simulation time 2218324486 ps
CPU time 25.95 seconds
Started Jul 16 05:05:55 PM PDT 24
Finished Jul 16 05:06:24 PM PDT 24
Peak memory 217768 kb
Host smart-056f8baa-9b9b-4a39-9ded-fb921eb68ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677304812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.677304812
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3317049626
Short name T616
Test name
Test status
Simulation time 860335809 ps
CPU time 21.39 seconds
Started Jul 16 05:06:02 PM PDT 24
Finished Jul 16 05:06:24 PM PDT 24
Peak memory 217108 kb
Host smart-d74200e1-3a63-4a7a-b5d6-34d5518c91cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317049626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3317049626
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.15273686
Short name T539
Test name
Test status
Simulation time 371203095 ps
CPU time 3.67 seconds
Started Jul 16 05:05:59 PM PDT 24
Finished Jul 16 05:06:04 PM PDT 24
Peak memory 222132 kb
Host smart-5369ff4d-0574-43f8-b92c-6c7f4ef8c082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15273686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.15273686
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3531663462
Short name T729
Test name
Test status
Simulation time 373981471 ps
CPU time 10.24 seconds
Started Jul 16 05:05:57 PM PDT 24
Finished Jul 16 05:06:10 PM PDT 24
Peak memory 225384 kb
Host smart-643ec4e0-2d5f-48bf-9567-a5c7419fdb18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531663462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3531663462
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1887476301
Short name T202
Test name
Test status
Simulation time 173741225 ps
CPU time 7.6 seconds
Started Jul 16 05:05:56 PM PDT 24
Finished Jul 16 05:06:06 PM PDT 24
Peak memory 217656 kb
Host smart-ceabe8de-db5e-41b6-ae3e-f9b3a38fab77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887476301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1887476301
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1769440956
Short name T627
Test name
Test status
Simulation time 1975536985 ps
CPU time 11.96 seconds
Started Jul 16 05:05:53 PM PDT 24
Finished Jul 16 05:06:07 PM PDT 24
Peak memory 217780 kb
Host smart-15dc0913-b694-48c5-93a6-18b711227cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769440956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1769440956
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.282040254
Short name T216
Test name
Test status
Simulation time 378347532 ps
CPU time 2.09 seconds
Started Jul 16 05:05:52 PM PDT 24
Finished Jul 16 05:05:56 PM PDT 24
Peak memory 217080 kb
Host smart-4cac8fa0-baf4-47b2-a371-f0d36b1ec9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282040254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.282040254
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3572661647
Short name T405
Test name
Test status
Simulation time 466986022 ps
CPU time 22.43 seconds
Started Jul 16 05:06:07 PM PDT 24
Finished Jul 16 05:06:32 PM PDT 24
Peak memory 250332 kb
Host smart-ea51d307-719b-4ccc-b1ea-2b06af911fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572661647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3572661647
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2180379502
Short name T403
Test name
Test status
Simulation time 267541087 ps
CPU time 2.61 seconds
Started Jul 16 05:05:53 PM PDT 24
Finished Jul 16 05:05:57 PM PDT 24
Peak memory 221992 kb
Host smart-ff99f98e-b301-4b5c-8d03-2eab0f97b7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180379502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2180379502
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.86287334
Short name T518
Test name
Test status
Simulation time 3447040669 ps
CPU time 57.84 seconds
Started Jul 16 05:06:05 PM PDT 24
Finished Jul 16 05:07:04 PM PDT 24
Peak memory 250472 kb
Host smart-92ce6af2-0ffc-4576-b1aa-1c946746dc3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86287334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.lc_ctrl_stress_all.86287334
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3264587547
Short name T260
Test name
Test status
Simulation time 16369074 ps
CPU time 0.79 seconds
Started Jul 16 05:05:59 PM PDT 24
Finished Jul 16 05:06:02 PM PDT 24
Peak memory 208116 kb
Host smart-5461315c-4a7e-448b-a359-31b6753aa294
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264587547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3264587547
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3233061004
Short name T561
Test name
Test status
Simulation time 90066288 ps
CPU time 1.25 seconds
Started Jul 16 05:06:07 PM PDT 24
Finished Jul 16 05:06:11 PM PDT 24
Peak memory 208492 kb
Host smart-cf3ec951-d7e9-47f0-810d-b69a46c1e70e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233061004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3233061004
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2269295887
Short name T562
Test name
Test status
Simulation time 256295488 ps
CPU time 10.77 seconds
Started Jul 16 05:06:08 PM PDT 24
Finished Jul 16 05:06:21 PM PDT 24
Peak memory 225448 kb
Host smart-ec3de34c-1480-41bc-9b3e-ba633dc7ec41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269295887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2269295887
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1202505121
Short name T150
Test name
Test status
Simulation time 625971575 ps
CPU time 6.12 seconds
Started Jul 16 05:06:04 PM PDT 24
Finished Jul 16 05:06:11 PM PDT 24
Peak memory 217360 kb
Host smart-68bf615d-c850-48d5-b38d-db95c32fd9a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202505121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1202505121
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3688345037
Short name T149
Test name
Test status
Simulation time 114375776 ps
CPU time 2.24 seconds
Started Jul 16 05:06:05 PM PDT 24
Finished Jul 16 05:06:08 PM PDT 24
Peak memory 221780 kb
Host smart-c70ea3b2-06dc-4ae5-a1b0-b3fecfb28567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688345037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3688345037
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.4167547623
Short name T462
Test name
Test status
Simulation time 1088873069 ps
CPU time 15.37 seconds
Started Jul 16 05:06:02 PM PDT 24
Finished Jul 16 05:06:19 PM PDT 24
Peak memory 225368 kb
Host smart-756a2f59-1627-49d6-b849-9f768ffb243a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167547623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.4167547623
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1426763726
Short name T534
Test name
Test status
Simulation time 482134668 ps
CPU time 8.73 seconds
Started Jul 16 05:06:04 PM PDT 24
Finished Jul 16 05:06:14 PM PDT 24
Peak memory 217728 kb
Host smart-2bc8941b-23fc-4211-8c7d-47ce598e505e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426763726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1426763726
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3723568493
Short name T304
Test name
Test status
Simulation time 685137371 ps
CPU time 9.11 seconds
Started Jul 16 05:06:08 PM PDT 24
Finished Jul 16 05:06:19 PM PDT 24
Peak memory 217788 kb
Host smart-effce05d-b08e-44cb-a61b-793a15c570db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723568493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3723568493
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.1948388407
Short name T610
Test name
Test status
Simulation time 313806102 ps
CPU time 4.89 seconds
Started Jul 16 05:06:10 PM PDT 24
Finished Jul 16 05:06:16 PM PDT 24
Peak memory 217116 kb
Host smart-3ff68e82-1146-4921-a57f-166b8cbf56c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948388407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1948388407
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2290411317
Short name T544
Test name
Test status
Simulation time 1970951441 ps
CPU time 21.07 seconds
Started Jul 16 05:06:04 PM PDT 24
Finished Jul 16 05:06:27 PM PDT 24
Peak memory 250252 kb
Host smart-60cdbf80-57d7-467e-8718-70744683ed0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290411317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2290411317
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2656275150
Short name T734
Test name
Test status
Simulation time 289171444 ps
CPU time 6.89 seconds
Started Jul 16 05:06:11 PM PDT 24
Finished Jul 16 05:06:19 PM PDT 24
Peak memory 242176 kb
Host smart-cd7a4fbb-bbfa-4158-a546-ff8dd7db2bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656275150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2656275150
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.4186067124
Short name T554
Test name
Test status
Simulation time 6114047934 ps
CPU time 107.08 seconds
Started Jul 16 05:06:05 PM PDT 24
Finished Jul 16 05:07:54 PM PDT 24
Peak memory 404892 kb
Host smart-56d244f4-b8fc-482a-8692-22172ad7021e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186067124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.4186067124
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2168931528
Short name T779
Test name
Test status
Simulation time 22814447 ps
CPU time 0.77 seconds
Started Jul 16 05:06:07 PM PDT 24
Finished Jul 16 05:06:09 PM PDT 24
Peak memory 208436 kb
Host smart-7f212d1d-a930-4e4d-8ca1-40d22026bee9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168931528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2168931528
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1705866053
Short name T718
Test name
Test status
Simulation time 87073315 ps
CPU time 0.98 seconds
Started Jul 16 05:06:05 PM PDT 24
Finished Jul 16 05:06:08 PM PDT 24
Peak memory 208404 kb
Host smart-6593ba6f-edbe-420f-979e-aa09c1581f6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705866053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1705866053
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3929306902
Short name T337
Test name
Test status
Simulation time 756608018 ps
CPU time 16.54 seconds
Started Jul 16 05:06:07 PM PDT 24
Finished Jul 16 05:06:25 PM PDT 24
Peak memory 217564 kb
Host smart-1abdc3de-dbea-4cc3-9f95-7b9bd9715304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929306902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3929306902
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3894253691
Short name T255
Test name
Test status
Simulation time 62189616 ps
CPU time 2.21 seconds
Started Jul 16 05:06:06 PM PDT 24
Finished Jul 16 05:06:09 PM PDT 24
Peak memory 217092 kb
Host smart-f064d7fc-8db9-4808-826a-e43d9455af6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894253691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3894253691
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.4235342542
Short name T596
Test name
Test status
Simulation time 63881311 ps
CPU time 2.72 seconds
Started Jul 16 05:06:07 PM PDT 24
Finished Jul 16 05:06:11 PM PDT 24
Peak memory 217552 kb
Host smart-abd49c1c-f9be-45eb-80b5-f7aa6d6c71de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235342542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.4235342542
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.590252228
Short name T466
Test name
Test status
Simulation time 958179770 ps
CPU time 14.25 seconds
Started Jul 16 05:06:08 PM PDT 24
Finished Jul 16 05:06:24 PM PDT 24
Peak memory 225280 kb
Host smart-b81132e2-fe5b-422b-a549-f3b09eb0c5bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590252228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.590252228
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1891514068
Short name T532
Test name
Test status
Simulation time 3018353472 ps
CPU time 16.87 seconds
Started Jul 16 05:06:08 PM PDT 24
Finished Jul 16 05:06:27 PM PDT 24
Peak memory 225480 kb
Host smart-48255f3e-cc51-48fd-8195-d703d0f6d80b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891514068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.1891514068
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.662913433
Short name T728
Test name
Test status
Simulation time 1103362417 ps
CPU time 9.51 seconds
Started Jul 16 05:06:15 PM PDT 24
Finished Jul 16 05:06:26 PM PDT 24
Peak memory 224764 kb
Host smart-993510d3-e76f-44fc-8617-ad41094a80f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662913433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.662913433
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.17966232
Short name T606
Test name
Test status
Simulation time 133345358 ps
CPU time 3.03 seconds
Started Jul 16 05:06:10 PM PDT 24
Finished Jul 16 05:06:14 PM PDT 24
Peak memory 214012 kb
Host smart-b0d96ada-2e45-42ba-8d5f-3e67a1aeeb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17966232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.17966232
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2496973333
Short name T283
Test name
Test status
Simulation time 268102059 ps
CPU time 19.07 seconds
Started Jul 16 05:06:05 PM PDT 24
Finished Jul 16 05:06:25 PM PDT 24
Peak memory 250588 kb
Host smart-1dda7a17-ce2d-4955-8d72-43f57020abef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496973333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2496973333
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3399145835
Short name T230
Test name
Test status
Simulation time 165646685 ps
CPU time 3.01 seconds
Started Jul 16 05:06:03 PM PDT 24
Finished Jul 16 05:06:08 PM PDT 24
Peak memory 225820 kb
Host smart-24470edb-9a88-4901-9660-5c44e773d757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399145835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3399145835
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1809430688
Short name T739
Test name
Test status
Simulation time 117472402933 ps
CPU time 210.02 seconds
Started Jul 16 05:06:07 PM PDT 24
Finished Jul 16 05:09:40 PM PDT 24
Peak memory 266848 kb
Host smart-1ec9e9f0-510c-4da5-83da-1fa62d283428
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809430688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1809430688
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2149796881
Short name T347
Test name
Test status
Simulation time 43057379 ps
CPU time 0.91 seconds
Started Jul 16 05:06:07 PM PDT 24
Finished Jul 16 05:06:09 PM PDT 24
Peak memory 211276 kb
Host smart-7aab360c-b6da-4fe0-90b0-ff75af803c54
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149796881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2149796881
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.854951710
Short name T211
Test name
Test status
Simulation time 28862785 ps
CPU time 0.9 seconds
Started Jul 16 05:04:02 PM PDT 24
Finished Jul 16 05:04:04 PM PDT 24
Peak memory 208216 kb
Host smart-d697a06a-78cf-458f-aa06-584af0b88338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854951710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.854951710
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1276687927
Short name T826
Test name
Test status
Simulation time 574110486 ps
CPU time 14.79 seconds
Started Jul 16 05:03:50 PM PDT 24
Finished Jul 16 05:04:06 PM PDT 24
Peak memory 217656 kb
Host smart-afe32a9f-c05a-4c14-8617-8b1cba563413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276687927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1276687927
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1132410473
Short name T22
Test name
Test status
Simulation time 446527834 ps
CPU time 4.85 seconds
Started Jul 16 05:03:46 PM PDT 24
Finished Jul 16 05:03:51 PM PDT 24
Peak memory 217076 kb
Host smart-8a45f8df-0d34-4097-a9f3-c4c5fcfcc004
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132410473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1132410473
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3343746731
Short name T630
Test name
Test status
Simulation time 16531773069 ps
CPU time 35.97 seconds
Started Jul 16 05:03:49 PM PDT 24
Finished Jul 16 05:04:27 PM PDT 24
Peak memory 217704 kb
Host smart-30fb1412-0184-44c1-85f2-375c119857b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343746731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3343746731
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3362830120
Short name T61
Test name
Test status
Simulation time 313977247 ps
CPU time 8.19 seconds
Started Jul 16 05:04:14 PM PDT 24
Finished Jul 16 05:04:24 PM PDT 24
Peak memory 217108 kb
Host smart-652fb43e-4cb1-47dd-b1a0-e42c756bc728
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362830120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.3
362830120
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1032912994
Short name T559
Test name
Test status
Simulation time 673435077 ps
CPU time 3.08 seconds
Started Jul 16 05:03:50 PM PDT 24
Finished Jul 16 05:03:55 PM PDT 24
Peak memory 217708 kb
Host smart-ce0d1a91-d26a-4832-af15-8bff49e49067
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032912994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1032912994
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1496577676
Short name T239
Test name
Test status
Simulation time 3581849549 ps
CPU time 15.29 seconds
Started Jul 16 05:03:59 PM PDT 24
Finished Jul 16 05:04:16 PM PDT 24
Peak memory 217104 kb
Host smart-35e84e46-9655-4ebd-85f0-c68d7d236408
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496577676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1496577676
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2552720357
Short name T762
Test name
Test status
Simulation time 224422363 ps
CPU time 6.75 seconds
Started Jul 16 05:03:50 PM PDT 24
Finished Jul 16 05:03:58 PM PDT 24
Peak memory 217120 kb
Host smart-aaf5c044-6110-4aa7-b3e5-f033a30e6c60
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552720357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2552720357
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2540450604
Short name T300
Test name
Test status
Simulation time 5421464092 ps
CPU time 48.97 seconds
Started Jul 16 05:03:49 PM PDT 24
Finished Jul 16 05:04:40 PM PDT 24
Peak memory 267952 kb
Host smart-8835a8a8-6af4-442e-9f0e-9ff632080cc3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540450604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2540450604
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3004475390
Short name T237
Test name
Test status
Simulation time 643806154 ps
CPU time 22.02 seconds
Started Jul 16 05:03:50 PM PDT 24
Finished Jul 16 05:04:13 PM PDT 24
Peak memory 248280 kb
Host smart-035a0b14-4f83-4a05-b3e4-3e7817c2a1f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004475390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.3004475390
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3310349021
Short name T514
Test name
Test status
Simulation time 37004552 ps
CPU time 1.98 seconds
Started Jul 16 05:03:46 PM PDT 24
Finished Jul 16 05:03:49 PM PDT 24
Peak memory 217712 kb
Host smart-eb51eb22-df33-41f7-8bcc-7a36e8f5c69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310349021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3310349021
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.354782506
Short name T167
Test name
Test status
Simulation time 1542915185 ps
CPU time 20.17 seconds
Started Jul 16 05:03:52 PM PDT 24
Finished Jul 16 05:04:13 PM PDT 24
Peak memory 213516 kb
Host smart-c4fac958-18c7-42df-89c2-3ed805d04a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354782506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.354782506
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1602770549
Short name T54
Test name
Test status
Simulation time 206358944 ps
CPU time 35.56 seconds
Started Jul 16 05:04:00 PM PDT 24
Finished Jul 16 05:04:37 PM PDT 24
Peak memory 284056 kb
Host smart-00298bb1-38f1-4304-af24-497c282cbe76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602770549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1602770549
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.3684635122
Short name T675
Test name
Test status
Simulation time 5338127969 ps
CPU time 14.68 seconds
Started Jul 16 05:04:00 PM PDT 24
Finished Jul 16 05:04:17 PM PDT 24
Peak memory 218988 kb
Host smart-2ae4e44a-a1ff-462c-a666-51f7c3d3fa2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684635122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.3684635122
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.565838861
Short name T409
Test name
Test status
Simulation time 1286486696 ps
CPU time 29.87 seconds
Started Jul 16 05:04:00 PM PDT 24
Finished Jul 16 05:04:32 PM PDT 24
Peak memory 225336 kb
Host smart-7cbe70f0-7998-4c17-8795-cfd3ff953295
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565838861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dig
est.565838861
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1083794248
Short name T725
Test name
Test status
Simulation time 260545870 ps
CPU time 8.6 seconds
Started Jul 16 05:04:00 PM PDT 24
Finished Jul 16 05:04:10 PM PDT 24
Peak memory 217476 kb
Host smart-86acc443-5863-4a6c-8c2c-23ee2ded17ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083794248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
083794248
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1249072967
Short name T360
Test name
Test status
Simulation time 953009812 ps
CPU time 9.87 seconds
Started Jul 16 05:03:54 PM PDT 24
Finished Jul 16 05:04:04 PM PDT 24
Peak memory 225436 kb
Host smart-666cd811-2fde-4188-ba70-54bd3d894444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249072967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1249072967
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.2048170080
Short name T162
Test name
Test status
Simulation time 144137329 ps
CPU time 8.19 seconds
Started Jul 16 05:03:48 PM PDT 24
Finished Jul 16 05:03:57 PM PDT 24
Peak memory 217076 kb
Host smart-24c4436f-1cac-40e4-93c1-70e6fa38634d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048170080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.2048170080
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.2032558858
Short name T499
Test name
Test status
Simulation time 1740718807 ps
CPU time 27.37 seconds
Started Jul 16 05:03:52 PM PDT 24
Finished Jul 16 05:04:20 PM PDT 24
Peak memory 250404 kb
Host smart-65fd4abe-3148-4aa3-8e85-a9b764cadd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032558858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2032558858
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3451990362
Short name T193
Test name
Test status
Simulation time 97719817 ps
CPU time 8.11 seconds
Started Jul 16 05:03:48 PM PDT 24
Finished Jul 16 05:03:57 PM PDT 24
Peak memory 250460 kb
Host smart-17166d44-24c3-4ac6-9c87-bf2710868056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451990362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3451990362
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3401543855
Short name T515
Test name
Test status
Simulation time 10557593797 ps
CPU time 66.11 seconds
Started Jul 16 05:04:00 PM PDT 24
Finished Jul 16 05:05:07 PM PDT 24
Peak memory 249420 kb
Host smart-6c75cd16-b4c2-49b5-aaf5-c5d7c1192ca8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401543855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3401543855
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.666370476
Short name T477
Test name
Test status
Simulation time 98282479 ps
CPU time 0.88 seconds
Started Jul 16 05:03:51 PM PDT 24
Finished Jul 16 05:03:53 PM PDT 24
Peak memory 211272 kb
Host smart-70f05e0b-70ce-4af4-842f-9e9c157f6fc2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666370476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.666370476
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3364312905
Short name T435
Test name
Test status
Simulation time 19898103 ps
CPU time 1.15 seconds
Started Jul 16 05:06:09 PM PDT 24
Finished Jul 16 05:06:12 PM PDT 24
Peak memory 208424 kb
Host smart-00c9852b-3f9c-450e-99d8-443966d86f35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364312905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3364312905
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2424142693
Short name T506
Test name
Test status
Simulation time 396338273 ps
CPU time 9.24 seconds
Started Jul 16 05:06:07 PM PDT 24
Finished Jul 16 05:06:18 PM PDT 24
Peak memory 225472 kb
Host smart-c9a6047f-ce4f-42f3-a1e4-38c9ae2c8487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424142693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2424142693
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.260167384
Short name T788
Test name
Test status
Simulation time 211813896 ps
CPU time 3.49 seconds
Started Jul 16 05:06:27 PM PDT 24
Finished Jul 16 05:06:32 PM PDT 24
Peak memory 216836 kb
Host smart-b85057c6-b980-49df-ab8a-44cf2bb8dd51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260167384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.260167384
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3384772585
Short name T410
Test name
Test status
Simulation time 46696777 ps
CPU time 2.19 seconds
Started Jul 16 05:06:10 PM PDT 24
Finished Jul 16 05:06:13 PM PDT 24
Peak memory 217720 kb
Host smart-f1f25d1c-d4ff-40a9-a3f6-24fda9bd957a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384772585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3384772585
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.3471496238
Short name T57
Test name
Test status
Simulation time 709486824 ps
CPU time 17.94 seconds
Started Jul 16 05:06:06 PM PDT 24
Finished Jul 16 05:06:26 PM PDT 24
Peak memory 218344 kb
Host smart-9c973a13-a0fe-421a-8c0e-e0280cae90ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471496238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3471496238
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3828325929
Short name T411
Test name
Test status
Simulation time 317769154 ps
CPU time 8.88 seconds
Started Jul 16 05:06:08 PM PDT 24
Finished Jul 16 05:06:19 PM PDT 24
Peak memory 225456 kb
Host smart-86d899b4-4fb6-44da-ab93-12e79d787dc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828325929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3828325929
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1811293174
Short name T816
Test name
Test status
Simulation time 608081834 ps
CPU time 10.87 seconds
Started Jul 16 05:06:08 PM PDT 24
Finished Jul 16 05:06:21 PM PDT 24
Peak memory 217664 kb
Host smart-1b67f4de-1729-46c7-92d7-2cc07825fc13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811293174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1811293174
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.363158098
Short name T424
Test name
Test status
Simulation time 280862117 ps
CPU time 11.59 seconds
Started Jul 16 05:06:10 PM PDT 24
Finished Jul 16 05:06:23 PM PDT 24
Peak memory 225516 kb
Host smart-4fd0278a-380f-4f5a-91e9-ac1c4c7cf8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363158098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.363158098
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1284322462
Short name T449
Test name
Test status
Simulation time 161403067 ps
CPU time 3.14 seconds
Started Jul 16 05:06:08 PM PDT 24
Finished Jul 16 05:06:13 PM PDT 24
Peak memory 217068 kb
Host smart-6c2d35f0-093a-4ca9-9c10-df55856b0243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284322462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1284322462
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.936408728
Short name T274
Test name
Test status
Simulation time 108384117 ps
CPU time 3.89 seconds
Started Jul 16 05:06:11 PM PDT 24
Finished Jul 16 05:06:16 PM PDT 24
Peak memory 225796 kb
Host smart-cbb6d9d2-ec3d-45a8-a163-d3ce3a0d4ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936408728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.936408728
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.644604179
Short name T86
Test name
Test status
Simulation time 7509976630 ps
CPU time 61.2 seconds
Started Jul 16 05:06:08 PM PDT 24
Finished Jul 16 05:07:12 PM PDT 24
Peak memory 250468 kb
Host smart-2fdd2129-034a-40f5-a1eb-47f523b1ceda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644604179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.644604179
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3317073216
Short name T381
Test name
Test status
Simulation time 11861063 ps
CPU time 0.83 seconds
Started Jul 16 05:06:08 PM PDT 24
Finished Jul 16 05:06:11 PM PDT 24
Peak memory 208452 kb
Host smart-c53ac9cb-84db-4c52-8012-a8372b56291b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317073216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3317073216
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3659899294
Short name T336
Test name
Test status
Simulation time 23966440 ps
CPU time 0.96 seconds
Started Jul 16 05:06:16 PM PDT 24
Finished Jul 16 05:06:18 PM PDT 24
Peak memory 208132 kb
Host smart-3c5ddd19-d5e1-4966-a733-663d8988db45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659899294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3659899294
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3231852793
Short name T835
Test name
Test status
Simulation time 2914737684 ps
CPU time 26.66 seconds
Started Jul 16 05:06:05 PM PDT 24
Finished Jul 16 05:06:33 PM PDT 24
Peak memory 225512 kb
Host smart-0d96c77e-a1e4-4991-8209-f8ea25fc03fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231852793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3231852793
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1303490648
Short name T636
Test name
Test status
Simulation time 398489569 ps
CPU time 10.77 seconds
Started Jul 16 05:06:27 PM PDT 24
Finished Jul 16 05:06:39 PM PDT 24
Peak memory 216332 kb
Host smart-62b29734-eb60-48c1-b94e-bfded59c18dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303490648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1303490648
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3577880993
Short name T566
Test name
Test status
Simulation time 39409299 ps
CPU time 1.62 seconds
Started Jul 16 05:06:06 PM PDT 24
Finished Jul 16 05:06:09 PM PDT 24
Peak memory 221312 kb
Host smart-7427c137-3aec-4a44-9357-7e63ebb609c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577880993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3577880993
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3794311970
Short name T227
Test name
Test status
Simulation time 293541814 ps
CPU time 8.53 seconds
Started Jul 16 05:06:08 PM PDT 24
Finished Jul 16 05:06:19 PM PDT 24
Peak memory 225428 kb
Host smart-464e6384-7dfb-4ca5-b298-eaa20b954ac9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794311970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.3794311970
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1268241873
Short name T697
Test name
Test status
Simulation time 380699978 ps
CPU time 10.01 seconds
Started Jul 16 05:06:03 PM PDT 24
Finished Jul 16 05:06:15 PM PDT 24
Peak memory 225396 kb
Host smart-2448f1af-aef5-4f51-af08-91a1cf2e75ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268241873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1268241873
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3437139735
Short name T317
Test name
Test status
Simulation time 939760833 ps
CPU time 14.62 seconds
Started Jul 16 05:06:06 PM PDT 24
Finished Jul 16 05:06:22 PM PDT 24
Peak memory 217780 kb
Host smart-33b2d6c2-f9b1-43c5-b3f5-5dd2ee80793b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437139735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3437139735
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3479544323
Short name T662
Test name
Test status
Simulation time 810212160 ps
CPU time 2.99 seconds
Started Jul 16 05:06:08 PM PDT 24
Finished Jul 16 05:06:13 PM PDT 24
Peak memory 214192 kb
Host smart-a98a1c90-9e77-4049-ba2b-a011d3118585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479544323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3479544323
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.4262488593
Short name T645
Test name
Test status
Simulation time 240319310 ps
CPU time 25.3 seconds
Started Jul 16 05:06:11 PM PDT 24
Finished Jul 16 05:06:37 PM PDT 24
Peak memory 250456 kb
Host smart-b125a686-fcd6-4f47-83c1-b7ae8137976f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262488593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.4262488593
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.25656623
Short name T674
Test name
Test status
Simulation time 129069317 ps
CPU time 8.62 seconds
Started Jul 16 05:06:08 PM PDT 24
Finished Jul 16 05:06:18 PM PDT 24
Peak memory 250424 kb
Host smart-bf9ba1a8-a4b5-400d-99bb-701b03a5c10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25656623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.25656623
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2239750874
Short name T781
Test name
Test status
Simulation time 20972695297 ps
CPU time 341.88 seconds
Started Jul 16 05:06:20 PM PDT 24
Finished Jul 16 05:12:04 PM PDT 24
Peak memory 265820 kb
Host smart-1e018082-1477-46e4-8346-d5937aa68663
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239750874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2239750874
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2622234677
Short name T144
Test name
Test status
Simulation time 43588394553 ps
CPU time 201.45 seconds
Started Jul 16 05:06:18 PM PDT 24
Finished Jul 16 05:09:42 PM PDT 24
Peak memory 250652 kb
Host smart-904e4b7d-9579-4872-9f81-9cca26879ecd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2622234677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.2622234677
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3513699768
Short name T818
Test name
Test status
Simulation time 15868011 ps
CPU time 1.22 seconds
Started Jul 16 05:06:08 PM PDT 24
Finished Jul 16 05:06:11 PM PDT 24
Peak memory 211372 kb
Host smart-08560198-9594-4d14-8ef6-1128be2618b6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513699768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3513699768
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.197770866
Short name T357
Test name
Test status
Simulation time 37535935 ps
CPU time 1.12 seconds
Started Jul 16 05:06:18 PM PDT 24
Finished Jul 16 05:06:21 PM PDT 24
Peak memory 208428 kb
Host smart-e6c827d3-ca41-4304-8267-e8ea07682abc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197770866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.197770866
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1380523901
Short name T612
Test name
Test status
Simulation time 201569723 ps
CPU time 8.06 seconds
Started Jul 16 05:06:21 PM PDT 24
Finished Jul 16 05:06:30 PM PDT 24
Peak memory 225468 kb
Host smart-e0e08a7c-64cb-4d0a-931d-b587d81d53af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380523901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1380523901
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3188464885
Short name T24
Test name
Test status
Simulation time 1507896854 ps
CPU time 3.98 seconds
Started Jul 16 05:06:17 PM PDT 24
Finished Jul 16 05:06:23 PM PDT 24
Peak memory 216944 kb
Host smart-df998cf9-dfba-4b5b-9060-1d9b27461a52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188464885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3188464885
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2632271541
Short name T678
Test name
Test status
Simulation time 59592674 ps
CPU time 2.54 seconds
Started Jul 16 05:06:17 PM PDT 24
Finished Jul 16 05:06:22 PM PDT 24
Peak memory 221832 kb
Host smart-a067977c-7313-49e4-8160-37141be9e099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632271541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2632271541
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3433644105
Short name T831
Test name
Test status
Simulation time 278885505 ps
CPU time 10.96 seconds
Started Jul 16 05:06:17 PM PDT 24
Finished Jul 16 05:06:31 PM PDT 24
Peak memory 218336 kb
Host smart-c4f3104e-b233-4024-838f-0004586b477d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433644105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3433644105
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2772309524
Short name T205
Test name
Test status
Simulation time 5745316608 ps
CPU time 10.4 seconds
Started Jul 16 05:06:23 PM PDT 24
Finished Jul 16 05:06:35 PM PDT 24
Peak memory 225516 kb
Host smart-c0c4c9b9-bcf7-40a2-afde-df2c0783ea0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772309524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2772309524
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2552615653
Short name T837
Test name
Test status
Simulation time 758641893 ps
CPU time 10.16 seconds
Started Jul 16 05:06:16 PM PDT 24
Finished Jul 16 05:06:27 PM PDT 24
Peak memory 225456 kb
Host smart-6cca3d74-6297-4b3e-aa0e-f90d1d851b33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552615653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2552615653
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1633969842
Short name T455
Test name
Test status
Simulation time 741204090 ps
CPU time 6.82 seconds
Started Jul 16 05:06:15 PM PDT 24
Finished Jul 16 05:06:23 PM PDT 24
Peak memory 224300 kb
Host smart-6673cb6a-ba98-4ebe-88cc-f55b6fe71469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633969842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1633969842
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1720415211
Short name T480
Test name
Test status
Simulation time 26429917 ps
CPU time 1.47 seconds
Started Jul 16 05:06:15 PM PDT 24
Finished Jul 16 05:06:18 PM PDT 24
Peak memory 213564 kb
Host smart-cc15df52-5182-442b-8c28-db8cae219ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720415211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1720415211
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.4236406734
Short name T619
Test name
Test status
Simulation time 1863154316 ps
CPU time 24.08 seconds
Started Jul 16 05:06:19 PM PDT 24
Finished Jul 16 05:06:45 PM PDT 24
Peak memory 250408 kb
Host smart-71990a55-0030-4aaa-8c19-1bdf67a991e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236406734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.4236406734
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2869168257
Short name T157
Test name
Test status
Simulation time 128586709 ps
CPU time 8.45 seconds
Started Jul 16 05:06:17 PM PDT 24
Finished Jul 16 05:06:28 PM PDT 24
Peak memory 250352 kb
Host smart-ba7a54a8-0a5d-431e-851a-b2cc2c4bb4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869168257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2869168257
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3862962389
Short name T284
Test name
Test status
Simulation time 3183378259 ps
CPU time 42.41 seconds
Started Jul 16 05:06:16 PM PDT 24
Finished Jul 16 05:07:01 PM PDT 24
Peak memory 225876 kb
Host smart-067b7e1e-189e-4a04-880d-882da1e17db9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862962389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3862962389
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3102511309
Short name T726
Test name
Test status
Simulation time 108481294707 ps
CPU time 308.89 seconds
Started Jul 16 05:06:17 PM PDT 24
Finished Jul 16 05:11:28 PM PDT 24
Peak memory 479952 kb
Host smart-d9e4e752-0979-4042-ae1f-40af135ce560
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3102511309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.3102511309
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1347108868
Short name T36
Test name
Test status
Simulation time 18592650 ps
CPU time 0.99 seconds
Started Jul 16 05:06:19 PM PDT 24
Finished Jul 16 05:06:22 PM PDT 24
Peak memory 217292 kb
Host smart-084ce82f-5dfd-4572-9acb-ecb821dc16a9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347108868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1347108868
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1074997128
Short name T280
Test name
Test status
Simulation time 32803224 ps
CPU time 1.14 seconds
Started Jul 16 05:06:22 PM PDT 24
Finished Jul 16 05:06:24 PM PDT 24
Peak memory 208368 kb
Host smart-b010aaea-ed5b-4230-9382-839622d6a55a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074997128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1074997128
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1896084349
Short name T672
Test name
Test status
Simulation time 233100503 ps
CPU time 9.71 seconds
Started Jul 16 05:06:22 PM PDT 24
Finished Jul 16 05:06:33 PM PDT 24
Peak memory 217660 kb
Host smart-04d709a1-f57b-46a7-b2f0-93a9b64b1f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896084349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1896084349
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2801614792
Short name T613
Test name
Test status
Simulation time 1461256452 ps
CPU time 18.55 seconds
Started Jul 16 05:06:16 PM PDT 24
Finished Jul 16 05:06:35 PM PDT 24
Peak memory 217068 kb
Host smart-967e6f86-741f-4cd7-84df-372fb45fa6d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801614792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2801614792
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.4268740556
Short name T845
Test name
Test status
Simulation time 94570162 ps
CPU time 3.04 seconds
Started Jul 16 05:06:21 PM PDT 24
Finished Jul 16 05:06:25 PM PDT 24
Peak memory 217592 kb
Host smart-e0206693-8389-4497-94a1-2dd35ec70b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268740556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.4268740556
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3995928715
Short name T660
Test name
Test status
Simulation time 405984083 ps
CPU time 8.55 seconds
Started Jul 16 05:06:19 PM PDT 24
Finished Jul 16 05:06:30 PM PDT 24
Peak memory 224984 kb
Host smart-e690da57-186a-4cf8-ba23-e2c017d93b3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995928715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3995928715
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.803864156
Short name T199
Test name
Test status
Simulation time 255797833 ps
CPU time 9.37 seconds
Started Jul 16 05:06:18 PM PDT 24
Finished Jul 16 05:06:29 PM PDT 24
Peak memory 225436 kb
Host smart-e5cc3c69-c3cc-46d3-97da-7dfe535b235b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803864156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_di
gest.803864156
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2891883497
Short name T695
Test name
Test status
Simulation time 1687536436 ps
CPU time 13.35 seconds
Started Jul 16 05:06:18 PM PDT 24
Finished Jul 16 05:06:34 PM PDT 24
Peak memory 225376 kb
Host smart-cb94a189-0a7f-43a0-af3e-833c1a6f441b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891883497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2891883497
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2095921978
Short name T383
Test name
Test status
Simulation time 349806893 ps
CPU time 11.92 seconds
Started Jul 16 05:06:24 PM PDT 24
Finished Jul 16 05:06:37 PM PDT 24
Peak memory 225520 kb
Host smart-a8d0b873-2534-47bb-9f4e-3d1e50720a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095921978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2095921978
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3903809012
Short name T860
Test name
Test status
Simulation time 85463735 ps
CPU time 1.63 seconds
Started Jul 16 05:06:25 PM PDT 24
Finished Jul 16 05:06:28 PM PDT 24
Peak memory 217136 kb
Host smart-6b316384-e2c9-44f3-bf09-702585182c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903809012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3903809012
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3087966716
Short name T646
Test name
Test status
Simulation time 1359541143 ps
CPU time 28.25 seconds
Started Jul 16 05:06:17 PM PDT 24
Finished Jul 16 05:06:48 PM PDT 24
Peak memory 250440 kb
Host smart-89fffdce-1961-460c-bef4-11ae21135804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087966716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3087966716
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3831102805
Short name T621
Test name
Test status
Simulation time 200845448 ps
CPU time 7.48 seconds
Started Jul 16 05:06:17 PM PDT 24
Finished Jul 16 05:06:27 PM PDT 24
Peak memory 250468 kb
Host smart-7594996f-9375-4fc4-bd42-da8b52372c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831102805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3831102805
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.3418077779
Short name T377
Test name
Test status
Simulation time 1644844474 ps
CPU time 49.56 seconds
Started Jul 16 05:06:17 PM PDT 24
Finished Jul 16 05:07:09 PM PDT 24
Peak memory 267220 kb
Host smart-fe3aef54-dd90-43f6-96fe-1f90a0bee5bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418077779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.3418077779
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.3675905681
Short name T96
Test name
Test status
Simulation time 21264919285 ps
CPU time 832.32 seconds
Started Jul 16 05:06:22 PM PDT 24
Finished Jul 16 05:20:16 PM PDT 24
Peak memory 267040 kb
Host smart-2d7f3caf-7eb9-451f-8c27-04740d185133
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3675905681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.3675905681
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1539031425
Short name T85
Test name
Test status
Simulation time 11907360 ps
CPU time 0.84 seconds
Started Jul 16 05:06:17 PM PDT 24
Finished Jul 16 05:06:20 PM PDT 24
Peak memory 208464 kb
Host smart-5c443822-eace-4b1d-b5de-81c13cefd87a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539031425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1539031425
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3885609625
Short name T65
Test name
Test status
Simulation time 18674134 ps
CPU time 0.89 seconds
Started Jul 16 05:06:19 PM PDT 24
Finished Jul 16 05:06:22 PM PDT 24
Peak memory 208160 kb
Host smart-0d5202d6-4cbe-492f-9e75-69e2a522f27a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885609625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3885609625
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.3610349898
Short name T698
Test name
Test status
Simulation time 1443719355 ps
CPU time 12.3 seconds
Started Jul 16 05:06:22 PM PDT 24
Finished Jul 16 05:06:36 PM PDT 24
Peak memory 217708 kb
Host smart-2db03d4f-e630-4408-addf-ca813d016484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610349898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3610349898
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.238310814
Short name T822
Test name
Test status
Simulation time 527771261 ps
CPU time 5.17 seconds
Started Jul 16 05:06:17 PM PDT 24
Finished Jul 16 05:06:25 PM PDT 24
Peak memory 217084 kb
Host smart-1546626c-a6bc-41c3-8dec-8be7faa74164
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238310814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.238310814
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2571719649
Short name T238
Test name
Test status
Simulation time 36691124 ps
CPU time 1.52 seconds
Started Jul 16 05:06:24 PM PDT 24
Finished Jul 16 05:06:27 PM PDT 24
Peak memory 217724 kb
Host smart-ac57e5ca-0256-4dab-81e5-10b537a13b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571719649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2571719649
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2050015661
Short name T307
Test name
Test status
Simulation time 807446141 ps
CPU time 13.9 seconds
Started Jul 16 05:06:22 PM PDT 24
Finished Jul 16 05:06:37 PM PDT 24
Peak memory 225612 kb
Host smart-30cbbf81-b831-4133-ad2f-b749420a1866
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050015661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2050015661
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1000590453
Short name T465
Test name
Test status
Simulation time 823410114 ps
CPU time 11.69 seconds
Started Jul 16 05:06:19 PM PDT 24
Finished Jul 16 05:06:33 PM PDT 24
Peak memory 225420 kb
Host smart-e18b1712-03d7-478f-9343-7fb87386362c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000590453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1000590453
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3552495944
Short name T856
Test name
Test status
Simulation time 751335834 ps
CPU time 16.13 seconds
Started Jul 16 05:06:19 PM PDT 24
Finished Jul 16 05:06:37 PM PDT 24
Peak memory 217508 kb
Host smart-aa5e09be-8821-49d3-bbba-d1ff28f1b298
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552495944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
3552495944
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.3278170982
Short name T751
Test name
Test status
Simulation time 1896625967 ps
CPU time 10.41 seconds
Started Jul 16 05:06:18 PM PDT 24
Finished Jul 16 05:06:30 PM PDT 24
Peak memory 224476 kb
Host smart-6cdd48f0-bf5e-45ea-a221-5cd51019e4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278170982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3278170982
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.72858263
Short name T776
Test name
Test status
Simulation time 80503883 ps
CPU time 1.46 seconds
Started Jul 16 05:06:17 PM PDT 24
Finished Jul 16 05:06:21 PM PDT 24
Peak memory 216980 kb
Host smart-635c3080-829d-42c5-85a8-bce8b9ba2102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72858263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.72858263
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1935675682
Short name T46
Test name
Test status
Simulation time 301053701 ps
CPU time 29.95 seconds
Started Jul 16 05:06:21 PM PDT 24
Finished Jul 16 05:06:52 PM PDT 24
Peak memory 250440 kb
Host smart-2ca3a9b0-5bae-44be-8cf4-b1beac42d0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935675682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1935675682
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.208456902
Short name T258
Test name
Test status
Simulation time 466411323 ps
CPU time 7.29 seconds
Started Jul 16 05:06:23 PM PDT 24
Finished Jul 16 05:06:31 PM PDT 24
Peak memory 250072 kb
Host smart-62d62566-a05b-4773-8adc-74b63086d3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208456902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.208456902
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.595944082
Short name T488
Test name
Test status
Simulation time 9554979575 ps
CPU time 295.81 seconds
Started Jul 16 05:06:22 PM PDT 24
Finished Jul 16 05:11:19 PM PDT 24
Peak memory 266868 kb
Host smart-7a710d8c-8032-4e84-a5d4-0b63962689a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595944082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.595944082
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.987822542
Short name T29
Test name
Test status
Simulation time 41547684 ps
CPU time 0.93 seconds
Started Jul 16 05:06:18 PM PDT 24
Finished Jul 16 05:06:22 PM PDT 24
Peak memory 208356 kb
Host smart-43d34136-44fc-4acc-bcd6-7cce7c4b2222
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987822542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.987822542
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2700794699
Short name T240
Test name
Test status
Simulation time 17156074 ps
CPU time 1.18 seconds
Started Jul 16 05:06:38 PM PDT 24
Finished Jul 16 05:06:40 PM PDT 24
Peak memory 208316 kb
Host smart-c40c7274-6d4c-4928-a561-74af274d8b60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700794699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2700794699
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2556251969
Short name T226
Test name
Test status
Simulation time 661600428 ps
CPU time 19.8 seconds
Started Jul 16 05:06:28 PM PDT 24
Finished Jul 16 05:06:49 PM PDT 24
Peak memory 217936 kb
Host smart-d0829b55-8b67-44d8-9628-c39702849755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556251969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2556251969
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1820266795
Short name T23
Test name
Test status
Simulation time 859777328 ps
CPU time 7.25 seconds
Started Jul 16 05:06:34 PM PDT 24
Finished Jul 16 05:06:42 PM PDT 24
Peak memory 217120 kb
Host smart-69836945-0760-4bda-b4e3-4d7e0cdecaae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820266795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1820266795
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.3405966881
Short name T709
Test name
Test status
Simulation time 40870162 ps
CPU time 2.59 seconds
Started Jul 16 05:06:22 PM PDT 24
Finished Jul 16 05:06:26 PM PDT 24
Peak memory 221820 kb
Host smart-0d93f796-d4f9-44e3-87d2-57247bd9245e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405966881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3405966881
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1293529575
Short name T497
Test name
Test status
Simulation time 692129386 ps
CPU time 11.25 seconds
Started Jul 16 05:06:30 PM PDT 24
Finished Jul 16 05:06:44 PM PDT 24
Peak memory 225040 kb
Host smart-32e7037b-c59c-4d49-b5d9-d5da1a0b6e9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293529575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1293529575
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1374498889
Short name T724
Test name
Test status
Simulation time 1211844077 ps
CPU time 7.57 seconds
Started Jul 16 05:06:30 PM PDT 24
Finished Jul 16 05:06:40 PM PDT 24
Peak memory 217660 kb
Host smart-238260c0-8a28-42b1-b808-eab1ead5b992
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374498889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1374498889
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1768143532
Short name T49
Test name
Test status
Simulation time 636884535 ps
CPU time 6.27 seconds
Started Jul 16 05:06:28 PM PDT 24
Finished Jul 16 05:06:35 PM PDT 24
Peak memory 225620 kb
Host smart-43923700-bcc3-4b74-a284-a5926f305f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768143532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1768143532
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3554356958
Short name T250
Test name
Test status
Simulation time 46710612 ps
CPU time 2.75 seconds
Started Jul 16 05:06:20 PM PDT 24
Finished Jul 16 05:06:24 PM PDT 24
Peak memory 217112 kb
Host smart-20fa064d-7954-4ebe-8d1e-01e7073502f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554356958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3554356958
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1319778827
Short name T730
Test name
Test status
Simulation time 696814114 ps
CPU time 15.77 seconds
Started Jul 16 05:06:22 PM PDT 24
Finished Jul 16 05:06:39 PM PDT 24
Peak memory 250464 kb
Host smart-0914dfbc-1e48-4cc7-8eec-844e15bc74b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319778827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1319778827
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2993876088
Short name T521
Test name
Test status
Simulation time 112719098 ps
CPU time 6.81 seconds
Started Jul 16 05:06:23 PM PDT 24
Finished Jul 16 05:06:31 PM PDT 24
Peak memory 246612 kb
Host smart-0309c908-0286-4b0f-95e7-b12af4799ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993876088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2993876088
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1688618289
Short name T42
Test name
Test status
Simulation time 34236404264 ps
CPU time 282.16 seconds
Started Jul 16 05:06:38 PM PDT 24
Finished Jul 16 05:11:21 PM PDT 24
Peak memory 250428 kb
Host smart-b5725acf-4237-46af-b9ac-f7120059f481
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688618289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1688618289
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.1211112208
Short name T41
Test name
Test status
Simulation time 19819736095 ps
CPU time 652.5 seconds
Started Jul 16 05:06:29 PM PDT 24
Finished Jul 16 05:17:24 PM PDT 24
Peak memory 272124 kb
Host smart-16002430-63fb-4027-8eaa-0c4efef283d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1211112208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.1211112208
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.5436754
Short name T68
Test name
Test status
Simulation time 23677463 ps
CPU time 0.89 seconds
Started Jul 16 05:06:21 PM PDT 24
Finished Jul 16 05:06:23 PM PDT 24
Peak memory 211268 kb
Host smart-20e16c3c-5261-4c52-8ef4-b72d4d2dbfd1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5436754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vola
tile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl
_volatile_unlock_smoke.5436754
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3668421747
Short name T77
Test name
Test status
Simulation time 69224396 ps
CPU time 0.89 seconds
Started Jul 16 05:06:38 PM PDT 24
Finished Jul 16 05:06:40 PM PDT 24
Peak memory 208244 kb
Host smart-3890109d-40ad-493a-9990-43459de9cf2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668421747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3668421747
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.4115436002
Short name T265
Test name
Test status
Simulation time 512874451 ps
CPU time 21.41 seconds
Started Jul 16 05:06:33 PM PDT 24
Finished Jul 16 05:06:55 PM PDT 24
Peak memory 225492 kb
Host smart-b67b7142-6a59-42fa-baf0-0c94e0f3ae93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115436002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.4115436002
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.37232963
Short name T430
Test name
Test status
Simulation time 10792091561 ps
CPU time 8.06 seconds
Started Jul 16 05:06:31 PM PDT 24
Finished Jul 16 05:06:41 PM PDT 24
Peak memory 217208 kb
Host smart-087901b6-9e22-4ed2-9ec1-b6dd2179109c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37232963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.37232963
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1745943271
Short name T364
Test name
Test status
Simulation time 1558701399 ps
CPU time 4.65 seconds
Started Jul 16 05:06:38 PM PDT 24
Finished Jul 16 05:06:43 PM PDT 24
Peak memory 217696 kb
Host smart-29655881-3b6f-4b6b-a1e9-4da3907ff378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745943271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1745943271
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.81630994
Short name T291
Test name
Test status
Simulation time 603502378 ps
CPU time 12.56 seconds
Started Jul 16 05:06:31 PM PDT 24
Finished Jul 16 05:06:45 PM PDT 24
Peak memory 219384 kb
Host smart-391db7b8-7a5e-4a48-87b5-25a70e9c32b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81630994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.81630994
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3958539017
Short name T447
Test name
Test status
Simulation time 756592628 ps
CPU time 10.54 seconds
Started Jul 16 05:06:41 PM PDT 24
Finished Jul 16 05:06:52 PM PDT 24
Peak memory 225372 kb
Host smart-195baf5a-d435-4eed-b4d9-de899769ffb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958539017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3958539017
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3391261155
Short name T350
Test name
Test status
Simulation time 2080758583 ps
CPU time 6.22 seconds
Started Jul 16 05:06:30 PM PDT 24
Finished Jul 16 05:06:39 PM PDT 24
Peak memory 217608 kb
Host smart-4b410d59-0e01-4f16-b482-81c14efc3f88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391261155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3391261155
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2107414411
Short name T777
Test name
Test status
Simulation time 236430265 ps
CPU time 9.44 seconds
Started Jul 16 05:06:34 PM PDT 24
Finished Jul 16 05:06:44 PM PDT 24
Peak memory 217792 kb
Host smart-78de6eaf-1cc9-4f62-9909-c03b699eca87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107414411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2107414411
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2701289758
Short name T43
Test name
Test status
Simulation time 52761974 ps
CPU time 0.97 seconds
Started Jul 16 05:06:31 PM PDT 24
Finished Jul 16 05:06:34 PM PDT 24
Peak memory 211652 kb
Host smart-10300c38-ff31-4b41-9bc0-44be4e71c0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701289758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2701289758
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.35866980
Short name T81
Test name
Test status
Simulation time 365673910 ps
CPU time 25.71 seconds
Started Jul 16 05:06:32 PM PDT 24
Finished Jul 16 05:06:59 PM PDT 24
Peak memory 250292 kb
Host smart-d4fff2db-134a-45c4-af22-3f12cbceebf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35866980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.35866980
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3424038919
Short name T154
Test name
Test status
Simulation time 348375382 ps
CPU time 10.05 seconds
Started Jul 16 05:06:31 PM PDT 24
Finished Jul 16 05:06:43 PM PDT 24
Peak memory 250404 kb
Host smart-b02da735-ac2c-46a2-91ae-2238494599b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424038919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3424038919
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1955832404
Short name T573
Test name
Test status
Simulation time 54047242397 ps
CPU time 150.83 seconds
Started Jul 16 05:06:30 PM PDT 24
Finished Jul 16 05:09:03 PM PDT 24
Peak memory 242340 kb
Host smart-00a9826f-5a1b-4925-888c-514c35fa4283
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955832404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1955832404
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3546781461
Short name T97
Test name
Test status
Simulation time 128507753456 ps
CPU time 519.42 seconds
Started Jul 16 05:06:33 PM PDT 24
Finished Jul 16 05:15:13 PM PDT 24
Peak memory 528968 kb
Host smart-70972aae-dccb-457d-95ba-d05f8ececf0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3546781461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.3546781461
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1566506581
Short name T527
Test name
Test status
Simulation time 35212932 ps
CPU time 0.74 seconds
Started Jul 16 05:06:35 PM PDT 24
Finished Jul 16 05:06:37 PM PDT 24
Peak memory 206940 kb
Host smart-87c161f8-6526-4df8-b5c8-1fe03a207356
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566506581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1566506581
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1768550595
Short name T91
Test name
Test status
Simulation time 30477148 ps
CPU time 0.89 seconds
Started Jul 16 05:06:29 PM PDT 24
Finished Jul 16 05:06:31 PM PDT 24
Peak memory 208252 kb
Host smart-7b23590a-741f-4527-a89a-b98fac203619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768550595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1768550595
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.966726546
Short name T560
Test name
Test status
Simulation time 433842503 ps
CPU time 11.87 seconds
Started Jul 16 05:06:31 PM PDT 24
Finished Jul 16 05:06:45 PM PDT 24
Peak memory 217724 kb
Host smart-7dc7e13f-d31d-4842-88c2-6da6966a1fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966726546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.966726546
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1800119737
Short name T5
Test name
Test status
Simulation time 827446338 ps
CPU time 19.75 seconds
Started Jul 16 05:06:28 PM PDT 24
Finished Jul 16 05:06:49 PM PDT 24
Peak memory 216788 kb
Host smart-bfd94e91-e6e2-4d68-a372-366f462088ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800119737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.1800119737
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.827038858
Short name T785
Test name
Test status
Simulation time 89076790 ps
CPU time 3.1 seconds
Started Jul 16 05:06:29 PM PDT 24
Finished Jul 16 05:06:33 PM PDT 24
Peak memory 217716 kb
Host smart-8bb92a2e-9434-483a-a04e-d52005249eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827038858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.827038858
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3953465233
Short name T422
Test name
Test status
Simulation time 1096908103 ps
CPU time 14.45 seconds
Started Jul 16 05:06:46 PM PDT 24
Finished Jul 16 05:07:01 PM PDT 24
Peak memory 217616 kb
Host smart-d05976ce-7f6b-4af8-8ca4-1393a5dd3e9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953465233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3953465233
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.3215627328
Short name T407
Test name
Test status
Simulation time 2047001086 ps
CPU time 8.88 seconds
Started Jul 16 05:06:40 PM PDT 24
Finished Jul 16 05:06:49 PM PDT 24
Peak memory 225348 kb
Host smart-473e91fb-01ef-40b9-8662-32b6638aa970
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215627328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.3215627328
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.139409127
Short name T47
Test name
Test status
Simulation time 308424292 ps
CPU time 6.93 seconds
Started Jul 16 05:06:29 PM PDT 24
Finished Jul 16 05:06:38 PM PDT 24
Peak memory 217596 kb
Host smart-c02b7d60-2e1f-4745-b198-ee1dffec60c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139409127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.139409127
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3448341974
Short name T52
Test name
Test status
Simulation time 226251815 ps
CPU time 7.56 seconds
Started Jul 16 05:06:33 PM PDT 24
Finished Jul 16 05:06:42 PM PDT 24
Peak memory 217728 kb
Host smart-58502d6c-0d12-4f9c-9f24-c8587ee907dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448341974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3448341974
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.907005941
Short name T507
Test name
Test status
Simulation time 173391520 ps
CPU time 3.25 seconds
Started Jul 16 05:06:37 PM PDT 24
Finished Jul 16 05:06:41 PM PDT 24
Peak memory 214324 kb
Host smart-cc094c01-4669-42a6-8f27-305768fe0228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907005941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.907005941
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2701879070
Short name T272
Test name
Test status
Simulation time 394362424 ps
CPU time 21.17 seconds
Started Jul 16 05:06:31 PM PDT 24
Finished Jul 16 05:06:54 PM PDT 24
Peak memory 250452 kb
Host smart-e116e6f7-17a0-4a59-8edc-2313d7fa6a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701879070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2701879070
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.606126911
Short name T267
Test name
Test status
Simulation time 87086011 ps
CPU time 6.53 seconds
Started Jul 16 05:06:29 PM PDT 24
Finished Jul 16 05:06:38 PM PDT 24
Peak memory 249876 kb
Host smart-d1eb458f-eed5-434d-bafe-112588222510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606126911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.606126911
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1205308532
Short name T393
Test name
Test status
Simulation time 2312687656 ps
CPU time 43.06 seconds
Started Jul 16 05:06:28 PM PDT 24
Finished Jul 16 05:07:12 PM PDT 24
Peak memory 242272 kb
Host smart-2ec59c9d-5a55-498c-827e-709c0445e540
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205308532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1205308532
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.2503356426
Short name T669
Test name
Test status
Simulation time 75591873700 ps
CPU time 633.98 seconds
Started Jul 16 05:06:44 PM PDT 24
Finished Jul 16 05:17:19 PM PDT 24
Peak memory 278956 kb
Host smart-acc81554-1b64-4f20-8e31-556b647f6b03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2503356426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.2503356426
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.213742678
Short name T647
Test name
Test status
Simulation time 40507518 ps
CPU time 1.04 seconds
Started Jul 16 05:06:38 PM PDT 24
Finished Jul 16 05:06:40 PM PDT 24
Peak memory 211224 kb
Host smart-b4be643a-1c46-4224-b8a6-385cdb9902ef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213742678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.213742678
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.382809530
Short name T771
Test name
Test status
Simulation time 25878141 ps
CPU time 1.13 seconds
Started Jul 16 05:06:33 PM PDT 24
Finished Jul 16 05:06:35 PM PDT 24
Peak memory 208488 kb
Host smart-a537c431-8f8b-4ae3-8b1a-0503917a322f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382809530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.382809530
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1164082010
Short name T772
Test name
Test status
Simulation time 5054833597 ps
CPU time 11.13 seconds
Started Jul 16 05:06:46 PM PDT 24
Finished Jul 16 05:06:57 PM PDT 24
Peak memory 217912 kb
Host smart-b5f13a58-b799-44dd-ab90-c864336f6095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164082010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1164082010
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1129263972
Short name T27
Test name
Test status
Simulation time 1689660074 ps
CPU time 11.08 seconds
Started Jul 16 05:06:31 PM PDT 24
Finished Jul 16 05:06:44 PM PDT 24
Peak memory 217028 kb
Host smart-b467f8ef-96d5-4739-899f-e71f835e6b1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129263972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1129263972
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.708872917
Short name T7
Test name
Test status
Simulation time 75851139 ps
CPU time 2.61 seconds
Started Jul 16 05:06:28 PM PDT 24
Finished Jul 16 05:06:32 PM PDT 24
Peak memory 217640 kb
Host smart-8a3ce27d-2ab6-4b04-b2bb-abe240d52b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708872917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.708872917
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1686465158
Short name T483
Test name
Test status
Simulation time 252698844 ps
CPU time 11.09 seconds
Started Jul 16 05:06:41 PM PDT 24
Finished Jul 16 05:06:53 PM PDT 24
Peak memory 217720 kb
Host smart-9b9a9763-c7be-4c8c-ad60-ce48d9773ce6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686465158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1686465158
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2416286360
Short name T366
Test name
Test status
Simulation time 251195269 ps
CPU time 10.6 seconds
Started Jul 16 05:06:30 PM PDT 24
Finished Jul 16 05:06:43 PM PDT 24
Peak memory 225428 kb
Host smart-2b611e0c-52a5-4422-8a1c-2425fdcebd12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416286360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2416286360
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.212781873
Short name T790
Test name
Test status
Simulation time 1461934128 ps
CPU time 9.19 seconds
Started Jul 16 05:06:37 PM PDT 24
Finished Jul 16 05:06:47 PM PDT 24
Peak memory 217592 kb
Host smart-4ab5c611-a63f-432a-bf63-525438e1cbef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212781873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.212781873
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1041958476
Short name T192
Test name
Test status
Simulation time 419516828 ps
CPU time 14.7 seconds
Started Jul 16 05:06:32 PM PDT 24
Finished Jul 16 05:06:48 PM PDT 24
Peak memory 225492 kb
Host smart-86c0450d-12ff-4e4c-bc45-93cf10a1f737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041958476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1041958476
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3995380577
Short name T59
Test name
Test status
Simulation time 485828683 ps
CPU time 3.8 seconds
Started Jul 16 05:06:29 PM PDT 24
Finished Jul 16 05:06:35 PM PDT 24
Peak memory 217144 kb
Host smart-18c5b8b7-e009-4396-9b69-d3763efcccbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995380577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3995380577
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.207708102
Short name T658
Test name
Test status
Simulation time 1030687811 ps
CPU time 22.06 seconds
Started Jul 16 05:06:30 PM PDT 24
Finished Jul 16 05:06:54 PM PDT 24
Peak memory 250440 kb
Host smart-de4f0dee-4e47-49ad-bdea-8483dbde37d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207708102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.207708102
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3424716267
Short name T88
Test name
Test status
Simulation time 239688648 ps
CPU time 6.41 seconds
Started Jul 16 05:06:31 PM PDT 24
Finished Jul 16 05:06:39 PM PDT 24
Peak memory 249996 kb
Host smart-1b84dba2-6e7b-4bac-8206-a08ba8ac320d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424716267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3424716267
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3955909920
Short name T401
Test name
Test status
Simulation time 2161140740 ps
CPU time 53.29 seconds
Started Jul 16 05:06:35 PM PDT 24
Finished Jul 16 05:07:29 PM PDT 24
Peak memory 267268 kb
Host smart-56814b5a-d4d8-43a6-bde6-b064df9f6f47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955909920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3955909920
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1591884091
Short name T8
Test name
Test status
Simulation time 71136480 ps
CPU time 0.91 seconds
Started Jul 16 05:06:30 PM PDT 24
Finished Jul 16 05:06:33 PM PDT 24
Peak memory 211156 kb
Host smart-d5a03b5d-347e-481f-b100-9c8057babe68
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591884091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.1591884091
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2159067421
Short name T851
Test name
Test status
Simulation time 26163217 ps
CPU time 1.06 seconds
Started Jul 16 05:06:42 PM PDT 24
Finished Jul 16 05:06:44 PM PDT 24
Peak memory 208332 kb
Host smart-f28592dd-1424-4899-bf9b-3271ad581edf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159067421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2159067421
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.125576000
Short name T639
Test name
Test status
Simulation time 4772914434 ps
CPU time 10.96 seconds
Started Jul 16 05:06:30 PM PDT 24
Finished Jul 16 05:06:43 PM PDT 24
Peak memory 217716 kb
Host smart-faaec51e-32e0-44e6-a16b-5f8abfd7dee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125576000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.125576000
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.3336507498
Short name T271
Test name
Test status
Simulation time 491664272 ps
CPU time 3.11 seconds
Started Jul 16 05:06:46 PM PDT 24
Finished Jul 16 05:06:49 PM PDT 24
Peak memory 217024 kb
Host smart-ea79dc3a-8f8f-43a2-a6bc-dd67c575395a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336507498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3336507498
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.927149833
Short name T153
Test name
Test status
Simulation time 54699130 ps
CPU time 3.21 seconds
Started Jul 16 05:06:40 PM PDT 24
Finished Jul 16 05:06:43 PM PDT 24
Peak memory 217624 kb
Host smart-a9308086-3231-4f0a-8981-cac7fb5ed5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927149833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.927149833
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.4179826968
Short name T756
Test name
Test status
Simulation time 966684758 ps
CPU time 10.46 seconds
Started Jul 16 05:06:33 PM PDT 24
Finished Jul 16 05:06:45 PM PDT 24
Peak memory 217912 kb
Host smart-c79935b9-ba40-4d51-ab4c-53374d46db71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179826968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.4179826968
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1358153625
Short name T740
Test name
Test status
Simulation time 602939812 ps
CPU time 13.52 seconds
Started Jul 16 05:06:29 PM PDT 24
Finished Jul 16 05:06:44 PM PDT 24
Peak memory 225428 kb
Host smart-c4776067-7e57-468f-8503-476ac309ebbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358153625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1358153625
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.869150865
Short name T814
Test name
Test status
Simulation time 714774789 ps
CPU time 16.44 seconds
Started Jul 16 05:06:27 PM PDT 24
Finished Jul 16 05:06:45 PM PDT 24
Peak memory 225368 kb
Host smart-7f66e92a-9be1-4e6a-8683-3c4866b47308
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869150865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.869150865
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3629241659
Short name T48
Test name
Test status
Simulation time 1077791263 ps
CPU time 7.08 seconds
Started Jul 16 05:06:37 PM PDT 24
Finished Jul 16 05:06:45 PM PDT 24
Peak memory 217760 kb
Host smart-a08984e3-7053-4901-92cc-734c9572c867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629241659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3629241659
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3976082519
Short name T684
Test name
Test status
Simulation time 2120428323 ps
CPU time 5.39 seconds
Started Jul 16 05:06:28 PM PDT 24
Finished Jul 16 05:06:35 PM PDT 24
Peak memory 217180 kb
Host smart-9f89f603-5d95-4af7-99de-727e68c06d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976082519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3976082519
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.248352945
Short name T538
Test name
Test status
Simulation time 841203665 ps
CPU time 26.4 seconds
Started Jul 16 05:06:37 PM PDT 24
Finished Jul 16 05:07:04 PM PDT 24
Peak memory 250316 kb
Host smart-4e846ecf-ad58-482a-b2e9-239f5932728b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248352945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.248352945
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1513206524
Short name T581
Test name
Test status
Simulation time 63853935 ps
CPU time 2.94 seconds
Started Jul 16 05:06:37 PM PDT 24
Finished Jul 16 05:06:41 PM PDT 24
Peak memory 222064 kb
Host smart-22f5f9ef-ea66-439e-a90b-01be8591c36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513206524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1513206524
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.854164234
Short name T670
Test name
Test status
Simulation time 20912082914 ps
CPU time 66.8 seconds
Started Jul 16 05:06:33 PM PDT 24
Finished Jul 16 05:07:41 PM PDT 24
Peak memory 275124 kb
Host smart-29c3c03d-57de-4b1e-997c-4e029bc5dde0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854164234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.854164234
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.734773992
Short name T264
Test name
Test status
Simulation time 13668010 ps
CPU time 0.88 seconds
Started Jul 16 05:06:31 PM PDT 24
Finished Jul 16 05:06:34 PM PDT 24
Peak memory 208240 kb
Host smart-44012806-8e25-4f04-9a16-d2d212a4c09c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734773992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.734773992
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2578420812
Short name T508
Test name
Test status
Simulation time 34448085 ps
CPU time 0.92 seconds
Started Jul 16 05:04:02 PM PDT 24
Finished Jul 16 05:04:03 PM PDT 24
Peak memory 208296 kb
Host smart-451bba33-2a3f-4d79-ae68-97953faa83c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578420812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2578420812
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.769859007
Short name T673
Test name
Test status
Simulation time 11817855 ps
CPU time 0.91 seconds
Started Jul 16 05:04:14 PM PDT 24
Finished Jul 16 05:04:16 PM PDT 24
Peak memory 208208 kb
Host smart-7c0b532c-7af9-40d4-99fc-f0efa63efd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769859007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.769859007
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1882766839
Short name T817
Test name
Test status
Simulation time 195154799 ps
CPU time 9.18 seconds
Started Jul 16 05:04:14 PM PDT 24
Finished Jul 16 05:04:25 PM PDT 24
Peak memory 225444 kb
Host smart-9bdc76a5-b16d-49f5-9f28-265ec8f31b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882766839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1882766839
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2303821232
Short name T804
Test name
Test status
Simulation time 1350048749 ps
CPU time 6.76 seconds
Started Jul 16 05:04:03 PM PDT 24
Finished Jul 16 05:04:10 PM PDT 24
Peak memory 217112 kb
Host smart-f4adad60-ac50-46f8-9ed1-0c21b5ce071a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303821232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2303821232
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.873165009
Short name T705
Test name
Test status
Simulation time 3014476369 ps
CPU time 42.59 seconds
Started Jul 16 05:03:59 PM PDT 24
Finished Jul 16 05:04:42 PM PDT 24
Peak memory 217672 kb
Host smart-5b08bc1a-bbb9-4d46-a499-b2e1493b0c31
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873165009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.873165009
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.671424340
Short name T168
Test name
Test status
Simulation time 245435833 ps
CPU time 7.2 seconds
Started Jul 16 05:04:00 PM PDT 24
Finished Jul 16 05:04:09 PM PDT 24
Peak memory 217196 kb
Host smart-9aa9a769-1da4-4eb8-a3a8-cf9c5f8593e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671424340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.671424340
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1085485372
Short name T809
Test name
Test status
Simulation time 97666489 ps
CPU time 2.47 seconds
Started Jul 16 05:03:59 PM PDT 24
Finished Jul 16 05:04:02 PM PDT 24
Peak memory 217552 kb
Host smart-772a99b1-22ee-40f9-809c-a50655384a2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085485372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1085485372
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3439003820
Short name T209
Test name
Test status
Simulation time 1270974805 ps
CPU time 16.13 seconds
Started Jul 16 05:04:00 PM PDT 24
Finished Jul 16 05:04:18 PM PDT 24
Peak memory 216992 kb
Host smart-97f2891a-ea42-4c62-8736-f4331b1a8e5d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439003820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3439003820
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1384887063
Short name T481
Test name
Test status
Simulation time 134269669 ps
CPU time 4.52 seconds
Started Jul 16 05:03:58 PM PDT 24
Finished Jul 16 05:04:03 PM PDT 24
Peak memory 217044 kb
Host smart-8902164b-5719-429c-8db2-a99c0d96789e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384887063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1384887063
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2927678999
Short name T289
Test name
Test status
Simulation time 716507104 ps
CPU time 24.21 seconds
Started Jul 16 05:04:00 PM PDT 24
Finished Jul 16 05:04:26 PM PDT 24
Peak memory 250376 kb
Host smart-c54c27d0-0bef-4527-93b3-9e74d48725f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927678999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2927678999
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2352520306
Short name T475
Test name
Test status
Simulation time 1834930753 ps
CPU time 8.08 seconds
Started Jul 16 05:04:14 PM PDT 24
Finished Jul 16 05:04:24 PM PDT 24
Peak memory 217628 kb
Host smart-95fc912b-161f-42a2-a3e4-1cf54f403911
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352520306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2352520306
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3628857499
Short name T214
Test name
Test status
Simulation time 122736468 ps
CPU time 2.63 seconds
Started Jul 16 05:04:14 PM PDT 24
Finished Jul 16 05:04:18 PM PDT 24
Peak memory 221636 kb
Host smart-fdd555e9-6b15-49a3-9477-54d57cfff8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628857499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3628857499
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3922075839
Short name T563
Test name
Test status
Simulation time 1098509552 ps
CPU time 15.42 seconds
Started Jul 16 05:04:14 PM PDT 24
Finished Jul 16 05:04:30 PM PDT 24
Peak memory 217136 kb
Host smart-0950a5a7-268a-4452-b8c3-dd39cfac74df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922075839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3922075839
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.308264109
Short name T589
Test name
Test status
Simulation time 422164165 ps
CPU time 13.94 seconds
Started Jul 16 05:04:01 PM PDT 24
Finished Jul 16 05:04:16 PM PDT 24
Peak memory 225496 kb
Host smart-903718f3-3d8d-4e59-8c5a-5d638993c0c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308264109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.308264109
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1282236852
Short name T691
Test name
Test status
Simulation time 374325547 ps
CPU time 6.67 seconds
Started Jul 16 05:03:59 PM PDT 24
Finished Jul 16 05:04:07 PM PDT 24
Peak memory 217604 kb
Host smart-511d56dc-6301-4b82-8c20-2bd21db6a916
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282236852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.1282236852
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.410600232
Short name T345
Test name
Test status
Simulation time 558520393 ps
CPU time 9.97 seconds
Started Jul 16 05:03:59 PM PDT 24
Finished Jul 16 05:04:11 PM PDT 24
Peak memory 217640 kb
Host smart-d3000f9e-3778-4afe-974f-687e321a5cd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410600232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.410600232
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3394324662
Short name T644
Test name
Test status
Simulation time 527868880 ps
CPU time 13.02 seconds
Started Jul 16 05:04:03 PM PDT 24
Finished Jul 16 05:04:17 PM PDT 24
Peak memory 225488 kb
Host smart-2e1ad839-9ec5-4821-8dbb-72c7a612ddfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394324662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3394324662
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.877783013
Short name T67
Test name
Test status
Simulation time 26755757 ps
CPU time 1.97 seconds
Started Jul 16 05:03:59 PM PDT 24
Finished Jul 16 05:04:03 PM PDT 24
Peak memory 213360 kb
Host smart-760c20b8-5d56-4710-aba9-cd63a2de1add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877783013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.877783013
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.2422369944
Short name T509
Test name
Test status
Simulation time 1669204220 ps
CPU time 19.81 seconds
Started Jul 16 05:04:02 PM PDT 24
Finished Jul 16 05:04:23 PM PDT 24
Peak memory 250324 kb
Host smart-15e426a3-0ef8-401e-97f6-a946389ddd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422369944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2422369944
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2888678916
Short name T277
Test name
Test status
Simulation time 312688032 ps
CPU time 7.26 seconds
Started Jul 16 05:03:59 PM PDT 24
Finished Jul 16 05:04:08 PM PDT 24
Peak memory 246672 kb
Host smart-91530c27-7169-45b5-8e48-1896ede079c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888678916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2888678916
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3521468917
Short name T582
Test name
Test status
Simulation time 9822081479 ps
CPU time 293.26 seconds
Started Jul 16 05:04:27 PM PDT 24
Finished Jul 16 05:09:21 PM PDT 24
Peak memory 250500 kb
Host smart-5a5231d1-dc3e-4d41-a9dc-3845a6b11613
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521468917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3521468917
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.3042054141
Short name T142
Test name
Test status
Simulation time 24979915145 ps
CPU time 153.06 seconds
Started Jul 16 05:04:01 PM PDT 24
Finished Jul 16 05:06:35 PM PDT 24
Peak memory 264172 kb
Host smart-9a752710-7b1c-475a-b2a0-5aa49959b7ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3042054141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.3042054141
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.753030719
Short name T552
Test name
Test status
Simulation time 39199239 ps
CPU time 0.89 seconds
Started Jul 16 05:04:01 PM PDT 24
Finished Jul 16 05:04:03 PM PDT 24
Peak memory 208536 kb
Host smart-ed62a226-8f1a-4535-bf5e-5ee7ea689b1f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753030719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.753030719
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2636218571
Short name T601
Test name
Test status
Simulation time 31266782 ps
CPU time 1.36 seconds
Started Jul 16 05:04:11 PM PDT 24
Finished Jul 16 05:04:14 PM PDT 24
Peak memory 208380 kb
Host smart-2c8b330d-2aab-4a8e-a93d-d368d5f03c81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636218571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2636218571
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3197515463
Short name T38
Test name
Test status
Simulation time 459430207 ps
CPU time 13.21 seconds
Started Jul 16 05:04:00 PM PDT 24
Finished Jul 16 05:04:14 PM PDT 24
Peak memory 217668 kb
Host smart-784de4c5-df94-4c94-8320-06ba7953d485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197515463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3197515463
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1994606040
Short name T353
Test name
Test status
Simulation time 1741439924 ps
CPU time 4.1 seconds
Started Jul 16 05:04:09 PM PDT 24
Finished Jul 16 05:04:14 PM PDT 24
Peak memory 217364 kb
Host smart-796dde10-d997-4251-b9d6-4df020558cd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994606040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1994606040
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2815215726
Short name T1
Test name
Test status
Simulation time 18151775806 ps
CPU time 90.51 seconds
Started Jul 16 05:04:09 PM PDT 24
Finished Jul 16 05:05:40 PM PDT 24
Peak memory 218384 kb
Host smart-502c1037-ac76-44b0-a091-7ba58af27a8b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815215726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2815215726
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.3556782213
Short name T320
Test name
Test status
Simulation time 515040163 ps
CPU time 6.77 seconds
Started Jul 16 05:04:10 PM PDT 24
Finished Jul 16 05:04:18 PM PDT 24
Peak memory 217148 kb
Host smart-edaa9cbd-d18b-4b58-a204-141d14a69adf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556782213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.3
556782213
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3189375205
Short name T805
Test name
Test status
Simulation time 298937141 ps
CPU time 9.85 seconds
Started Jul 16 05:04:10 PM PDT 24
Finished Jul 16 05:04:21 PM PDT 24
Peak memory 221580 kb
Host smart-9901e032-2cb5-4ee1-b0da-a62de5bfb223
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189375205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3189375205
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3566220472
Short name T584
Test name
Test status
Simulation time 669453691 ps
CPU time 10.48 seconds
Started Jul 16 05:04:11 PM PDT 24
Finished Jul 16 05:04:23 PM PDT 24
Peak memory 217072 kb
Host smart-59ea1f88-6219-4ddb-a18b-6ba450831500
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566220472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3566220472
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3154898520
Short name T456
Test name
Test status
Simulation time 383435456 ps
CPU time 3.34 seconds
Started Jul 16 05:04:12 PM PDT 24
Finished Jul 16 05:04:16 PM PDT 24
Peak memory 216972 kb
Host smart-19b74709-196d-4071-bf6f-44b1ed9c4c2b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154898520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3154898520
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3264942936
Short name T807
Test name
Test status
Simulation time 5120372873 ps
CPU time 51.03 seconds
Started Jul 16 05:04:11 PM PDT 24
Finished Jul 16 05:05:03 PM PDT 24
Peak memory 250508 kb
Host smart-10eae069-7f32-487e-86ba-8c78cae83974
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264942936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3264942936
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3877002862
Short name T605
Test name
Test status
Simulation time 2968660012 ps
CPU time 15.49 seconds
Started Jul 16 05:04:12 PM PDT 24
Finished Jul 16 05:04:29 PM PDT 24
Peak memory 250460 kb
Host smart-81bee0d7-5399-4a87-8e29-a5baaab37108
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877002862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3877002862
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3971425331
Short name T811
Test name
Test status
Simulation time 124995853 ps
CPU time 1.89 seconds
Started Jul 16 05:04:00 PM PDT 24
Finished Jul 16 05:04:03 PM PDT 24
Peak memory 221420 kb
Host smart-0c7e98a0-a3ec-4268-82f1-9bd693a1d119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971425331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3971425331
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1792228581
Short name T663
Test name
Test status
Simulation time 532028508 ps
CPU time 18.2 seconds
Started Jul 16 05:04:01 PM PDT 24
Finished Jul 16 05:04:20 PM PDT 24
Peak memory 213476 kb
Host smart-c53b0da6-c674-49fd-a4fa-a4e7c3a31311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792228581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1792228581
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3446066694
Short name T428
Test name
Test status
Simulation time 467070507 ps
CPU time 13.4 seconds
Started Jul 16 05:04:11 PM PDT 24
Finished Jul 16 05:04:26 PM PDT 24
Peak memory 225412 kb
Host smart-30ffac92-c520-4917-825a-c50a9a135465
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446066694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3446066694
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2444721128
Short name T706
Test name
Test status
Simulation time 435894659 ps
CPU time 15.64 seconds
Started Jul 16 05:04:12 PM PDT 24
Finished Jul 16 05:04:28 PM PDT 24
Peak memory 225480 kb
Host smart-3067758d-9e30-4c5c-8ada-238c2cfb6b36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444721128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.2444721128
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2204669949
Short name T611
Test name
Test status
Simulation time 2913612434 ps
CPU time 10.45 seconds
Started Jul 16 05:04:14 PM PDT 24
Finished Jul 16 05:04:26 PM PDT 24
Peak memory 217704 kb
Host smart-f9b46991-5bbd-4b59-b2ff-9b610d30739d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204669949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
204669949
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.4193562876
Short name T795
Test name
Test status
Simulation time 222527924 ps
CPU time 6.06 seconds
Started Jul 16 05:04:01 PM PDT 24
Finished Jul 16 05:04:08 PM PDT 24
Peak memory 217668 kb
Host smart-4c8bf2d5-65a5-4faa-82f1-08a6771726b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193562876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.4193562876
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.2230302108
Short name T761
Test name
Test status
Simulation time 24852112 ps
CPU time 1.06 seconds
Started Jul 16 05:04:00 PM PDT 24
Finished Jul 16 05:04:03 PM PDT 24
Peak memory 211440 kb
Host smart-66fd7fe1-fffa-4a84-93c9-d52b8a41faec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230302108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2230302108
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.2248433338
Short name T431
Test name
Test status
Simulation time 538764793 ps
CPU time 28.97 seconds
Started Jul 16 05:04:00 PM PDT 24
Finished Jul 16 05:04:31 PM PDT 24
Peak memory 250336 kb
Host smart-82afdff4-c9ce-4319-89ae-a30860258ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248433338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2248433338
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2141292461
Short name T12
Test name
Test status
Simulation time 253471356 ps
CPU time 7.47 seconds
Started Jul 16 05:03:59 PM PDT 24
Finished Jul 16 05:04:07 PM PDT 24
Peak memory 250452 kb
Host smart-5ec1100f-328d-482e-9e4d-ce5b3f769a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141292461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2141292461
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2211918384
Short name T707
Test name
Test status
Simulation time 7796795111 ps
CPU time 158.57 seconds
Started Jul 16 05:04:14 PM PDT 24
Finished Jul 16 05:06:54 PM PDT 24
Peak memory 275272 kb
Host smart-2512dd4c-6aec-4a6c-bc90-cca888f6b157
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211918384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2211918384
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3874982595
Short name T652
Test name
Test status
Simulation time 13254708 ps
CPU time 0.99 seconds
Started Jul 16 05:04:00 PM PDT 24
Finished Jul 16 05:04:02 PM PDT 24
Peak memory 208564 kb
Host smart-9cf4ba42-2c19-49c2-b709-97d47beb7961
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874982595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3874982595
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2266104687
Short name T433
Test name
Test status
Simulation time 24246665 ps
CPU time 0.83 seconds
Started Jul 16 05:04:22 PM PDT 24
Finished Jul 16 05:04:24 PM PDT 24
Peak memory 208096 kb
Host smart-b1c4a272-c55a-4070-affa-d76781e272e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266104687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2266104687
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1234838113
Short name T87
Test name
Test status
Simulation time 947040947 ps
CPU time 16.31 seconds
Started Jul 16 05:04:10 PM PDT 24
Finished Jul 16 05:04:27 PM PDT 24
Peak memory 225404 kb
Host smart-76b82ac3-a1a5-4b9c-aff7-0ae04e82815c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234838113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1234838113
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2582301128
Short name T314
Test name
Test status
Simulation time 322465805 ps
CPU time 7.69 seconds
Started Jul 16 05:04:10 PM PDT 24
Finished Jul 16 05:04:19 PM PDT 24
Peak memory 217136 kb
Host smart-62691aff-a481-408b-a792-4780d2cba7a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582301128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2582301128
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2276892534
Short name T583
Test name
Test status
Simulation time 3838066010 ps
CPU time 50.13 seconds
Started Jul 16 05:04:09 PM PDT 24
Finished Jul 16 05:05:00 PM PDT 24
Peak memory 219620 kb
Host smart-459e8a7c-5dfa-4cc7-9be8-3a645f9a5a88
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276892534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2276892534
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1423674931
Short name T551
Test name
Test status
Simulation time 9270722703 ps
CPU time 14.22 seconds
Started Jul 16 05:04:11 PM PDT 24
Finished Jul 16 05:04:27 PM PDT 24
Peak memory 217164 kb
Host smart-91e662b1-a51d-446b-97d3-e902c9418af8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423674931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
423674931
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.35689462
Short name T301
Test name
Test status
Simulation time 1242759743 ps
CPU time 12.73 seconds
Started Jul 16 05:04:09 PM PDT 24
Finished Jul 16 05:04:23 PM PDT 24
Peak memory 223480 kb
Host smart-193bbf42-778d-4043-ae50-9a29683946e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35689462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_p
rog_failure.35689462
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2341888615
Short name T859
Test name
Test status
Simulation time 843348638 ps
CPU time 22.76 seconds
Started Jul 16 05:04:10 PM PDT 24
Finished Jul 16 05:04:34 PM PDT 24
Peak memory 217076 kb
Host smart-232cefb3-4d77-4b68-860e-4c7ef8e55c8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341888615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2341888615
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.458785516
Short name T715
Test name
Test status
Simulation time 1242047472 ps
CPU time 15.78 seconds
Started Jul 16 05:04:10 PM PDT 24
Finished Jul 16 05:04:27 PM PDT 24
Peak memory 216996 kb
Host smart-39a59581-bb0e-4e60-9aec-5b3d0a2d8c40
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458785516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.458785516
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2358720843
Short name T442
Test name
Test status
Simulation time 2303278665 ps
CPU time 53.65 seconds
Started Jul 16 05:04:11 PM PDT 24
Finished Jul 16 05:05:06 PM PDT 24
Peak memory 276540 kb
Host smart-8a7e42c0-4685-4ce6-9534-f7e24db4380c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358720843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2358720843
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.152907867
Short name T828
Test name
Test status
Simulation time 788524825 ps
CPU time 27.22 seconds
Started Jul 16 05:04:09 PM PDT 24
Finished Jul 16 05:04:37 PM PDT 24
Peak memory 250328 kb
Host smart-eceaa9f6-a623-4c1a-a022-aa304ccc4152
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152907867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.152907867
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1213990829
Short name T598
Test name
Test status
Simulation time 293115675 ps
CPU time 4.58 seconds
Started Jul 16 05:04:10 PM PDT 24
Finished Jul 16 05:04:15 PM PDT 24
Peak memory 221992 kb
Host smart-9af039d1-f91e-4f99-9306-2b058954a73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213990829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1213990829
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.4290841116
Short name T840
Test name
Test status
Simulation time 257478131 ps
CPU time 9.43 seconds
Started Jul 16 05:04:09 PM PDT 24
Finished Jul 16 05:04:20 PM PDT 24
Peak memory 217100 kb
Host smart-ebdf2854-1f70-4ed4-b666-fd216f04414f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290841116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.4290841116
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3799073106
Short name T633
Test name
Test status
Simulation time 693187945 ps
CPU time 13.84 seconds
Started Jul 16 05:04:23 PM PDT 24
Finished Jul 16 05:04:38 PM PDT 24
Peak memory 217680 kb
Host smart-42548433-388d-42bc-acdd-cda3b029b060
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799073106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3799073106
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1965404685
Short name T458
Test name
Test status
Simulation time 451491177 ps
CPU time 9.37 seconds
Started Jul 16 05:04:09 PM PDT 24
Finished Jul 16 05:04:19 PM PDT 24
Peak memory 217580 kb
Host smart-12695274-9939-4db8-854f-f9dbdd4985e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965404685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
965404685
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.3908257468
Short name T495
Test name
Test status
Simulation time 236577138 ps
CPU time 10.17 seconds
Started Jul 16 05:04:10 PM PDT 24
Finished Jul 16 05:04:22 PM PDT 24
Peak memory 224128 kb
Host smart-6676dd4b-00ed-4d2d-ae55-696c963e102d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908257468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3908257468
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.222781275
Short name T368
Test name
Test status
Simulation time 217765582 ps
CPU time 2.36 seconds
Started Jul 16 05:04:10 PM PDT 24
Finished Jul 16 05:04:14 PM PDT 24
Peak memory 214104 kb
Host smart-4a389b2a-5b60-49a5-a945-96a600806b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222781275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.222781275
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.4253281146
Short name T588
Test name
Test status
Simulation time 6214959730 ps
CPU time 29.1 seconds
Started Jul 16 05:04:11 PM PDT 24
Finished Jul 16 05:04:41 PM PDT 24
Peak memory 250368 kb
Host smart-ce37d8ba-6c4a-415e-b036-d6d12794cb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253281146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.4253281146
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.204409282
Short name T164
Test name
Test status
Simulation time 169769288 ps
CPU time 4.08 seconds
Started Jul 16 05:04:10 PM PDT 24
Finished Jul 16 05:04:15 PM PDT 24
Peak memory 221948 kb
Host smart-26cc1344-d4c6-46f4-994c-5ccd2ddf0922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204409282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.204409282
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3946606397
Short name T778
Test name
Test status
Simulation time 11309323235 ps
CPU time 126.91 seconds
Started Jul 16 05:04:23 PM PDT 24
Finished Jul 16 05:06:32 PM PDT 24
Peak memory 281396 kb
Host smart-ca5deadd-54bb-4195-8e21-616c4937058b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946606397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3946606397
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3679934873
Short name T243
Test name
Test status
Simulation time 16064111 ps
CPU time 0.95 seconds
Started Jul 16 05:04:14 PM PDT 24
Finished Jul 16 05:04:16 PM PDT 24
Peak memory 211260 kb
Host smart-7ef4820b-68ef-4c3d-b5b1-10e7a362b881
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679934873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3679934873
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1799215938
Short name T374
Test name
Test status
Simulation time 36650250 ps
CPU time 0.92 seconds
Started Jul 16 05:04:30 PM PDT 24
Finished Jul 16 05:04:31 PM PDT 24
Peak memory 208236 kb
Host smart-ec86d55c-80f0-418e-9b22-f94bfcf558c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799215938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1799215938
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3418391736
Short name T252
Test name
Test status
Simulation time 16104537 ps
CPU time 0.85 seconds
Started Jul 16 05:04:24 PM PDT 24
Finished Jul 16 05:04:26 PM PDT 24
Peak memory 208060 kb
Host smart-e0458d0a-4928-4791-94b2-c30ba7aa48f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418391736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3418391736
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1354454034
Short name T550
Test name
Test status
Simulation time 944531326 ps
CPU time 9.99 seconds
Started Jul 16 05:04:28 PM PDT 24
Finished Jul 16 05:04:38 PM PDT 24
Peak memory 217724 kb
Host smart-227a836d-2c0f-4d48-b604-8ad267af885c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354454034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1354454034
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1784913106
Short name T773
Test name
Test status
Simulation time 329489071 ps
CPU time 8.73 seconds
Started Jul 16 05:04:22 PM PDT 24
Finished Jul 16 05:04:31 PM PDT 24
Peak memory 217136 kb
Host smart-d9b3db15-2309-48c6-bce3-63e9e29c267b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784913106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1784913106
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.3478962592
Short name T847
Test name
Test status
Simulation time 17749240359 ps
CPU time 95.96 seconds
Started Jul 16 05:04:23 PM PDT 24
Finished Jul 16 05:06:00 PM PDT 24
Peak memory 218296 kb
Host smart-f1cba860-fbc3-4e8a-9798-0a011c263f59
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478962592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.3478962592
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1403721850
Short name T269
Test name
Test status
Simulation time 922617671 ps
CPU time 5.04 seconds
Started Jul 16 05:04:23 PM PDT 24
Finished Jul 16 05:04:29 PM PDT 24
Peak memory 217104 kb
Host smart-5089660e-39bf-44d4-a455-6faf62f2924c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403721850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
403721850
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2141325430
Short name T557
Test name
Test status
Simulation time 1191388734 ps
CPU time 10.3 seconds
Started Jul 16 05:04:22 PM PDT 24
Finished Jul 16 05:04:33 PM PDT 24
Peak memory 217636 kb
Host smart-0487d99a-1455-48dc-b10e-ac4400175930
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141325430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2141325430
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1256593625
Short name T384
Test name
Test status
Simulation time 9013464219 ps
CPU time 8.99 seconds
Started Jul 16 05:04:28 PM PDT 24
Finished Jul 16 05:04:38 PM PDT 24
Peak memory 217132 kb
Host smart-d3e5cd74-9e38-4923-8bd2-6c8ef046b460
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256593625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1256593625
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1991635162
Short name T824
Test name
Test status
Simulation time 80569809 ps
CPU time 2.03 seconds
Started Jul 16 05:04:25 PM PDT 24
Finished Jul 16 05:04:28 PM PDT 24
Peak memory 217064 kb
Host smart-af66d5b9-b19c-4664-93f9-64b11c54faab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991635162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1991635162
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.513927211
Short name T792
Test name
Test status
Simulation time 1443357848 ps
CPU time 65.89 seconds
Started Jul 16 05:04:28 PM PDT 24
Finished Jul 16 05:05:35 PM PDT 24
Peak memory 266768 kb
Host smart-e2000928-026e-4538-a970-b2ee84c98592
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513927211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.513927211
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3572524548
Short name T464
Test name
Test status
Simulation time 573246979 ps
CPU time 14.84 seconds
Started Jul 16 05:04:24 PM PDT 24
Finished Jul 16 05:04:40 PM PDT 24
Peak memory 250384 kb
Host smart-0b912035-5f78-44c4-86f9-c42e98c71c13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572524548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3572524548
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3533973964
Short name T212
Test name
Test status
Simulation time 869070028 ps
CPU time 2.94 seconds
Started Jul 16 05:04:28 PM PDT 24
Finished Jul 16 05:04:32 PM PDT 24
Peak memory 217612 kb
Host smart-740e75e8-e491-4f6a-9688-6536d64a23ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533973964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3533973964
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3785710443
Short name T738
Test name
Test status
Simulation time 610194680 ps
CPU time 19.48 seconds
Started Jul 16 05:04:25 PM PDT 24
Finished Jul 16 05:04:46 PM PDT 24
Peak memory 217140 kb
Host smart-cfad83d4-dc63-4e70-b30c-a48d9806a92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785710443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3785710443
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2006643967
Short name T754
Test name
Test status
Simulation time 912726351 ps
CPU time 8.28 seconds
Started Jul 16 05:04:25 PM PDT 24
Finished Jul 16 05:04:34 PM PDT 24
Peak memory 225396 kb
Host smart-c7fbd581-5662-400f-8e94-61f2782e23a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006643967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2006643967
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.391947762
Short name T399
Test name
Test status
Simulation time 337824152 ps
CPU time 9.92 seconds
Started Jul 16 05:04:25 PM PDT 24
Finished Jul 16 05:04:36 PM PDT 24
Peak memory 225480 kb
Host smart-36b46ebb-9bd6-4e22-94fd-06bea7c486ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391947762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.391947762
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.377232061
Short name T485
Test name
Test status
Simulation time 2330084095 ps
CPU time 11.08 seconds
Started Jul 16 05:04:23 PM PDT 24
Finished Jul 16 05:04:35 PM PDT 24
Peak memory 224856 kb
Host smart-9c889c02-d187-424e-a0a2-039bf1e038dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377232061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.377232061
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.4135382432
Short name T576
Test name
Test status
Simulation time 44114638 ps
CPU time 1.67 seconds
Started Jul 16 05:04:24 PM PDT 24
Finished Jul 16 05:04:27 PM PDT 24
Peak memory 217032 kb
Host smart-cc9f0429-d00d-4d89-b02e-30321e9edb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135382432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.4135382432
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.175433358
Short name T536
Test name
Test status
Simulation time 708441413 ps
CPU time 24.57 seconds
Started Jul 16 05:04:22 PM PDT 24
Finished Jul 16 05:04:48 PM PDT 24
Peak memory 250460 kb
Host smart-6e7c4c5b-cf82-4f9b-83d4-c1bebd4aa8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175433358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.175433358
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.707218643
Short name T486
Test name
Test status
Simulation time 71444902 ps
CPU time 2.78 seconds
Started Jul 16 05:04:30 PM PDT 24
Finished Jul 16 05:04:33 PM PDT 24
Peak memory 220744 kb
Host smart-6e293ab7-72d0-456d-a161-0a492b9dd68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707218643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.707218643
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.178968952
Short name T233
Test name
Test status
Simulation time 5324099894 ps
CPU time 106.61 seconds
Started Jul 16 05:04:22 PM PDT 24
Finished Jul 16 05:06:09 PM PDT 24
Peak memory 250476 kb
Host smart-9cc1594b-c276-46be-9c61-ee86c8ac2830
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178968952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.178968952
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3471830245
Short name T745
Test name
Test status
Simulation time 14086860 ps
CPU time 0.81 seconds
Started Jul 16 05:04:24 PM PDT 24
Finished Jul 16 05:04:26 PM PDT 24
Peak memory 208348 kb
Host smart-884f0471-a8da-4c67-ab3d-11a2ff7294c2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471830245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3471830245
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3373945937
Short name T659
Test name
Test status
Simulation time 32576700 ps
CPU time 0.89 seconds
Started Jul 16 05:04:37 PM PDT 24
Finished Jul 16 05:04:41 PM PDT 24
Peak memory 208196 kb
Host smart-6525b7a2-bce2-4ea3-b8ab-b6d12ed154e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373945937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3373945937
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.564104869
Short name T459
Test name
Test status
Simulation time 34169378 ps
CPU time 0.84 seconds
Started Jul 16 05:04:21 PM PDT 24
Finished Jul 16 05:04:23 PM PDT 24
Peak memory 208100 kb
Host smart-8e6d99fa-6c92-44d3-891e-14ba6566ef95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564104869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.564104869
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.2121259180
Short name T580
Test name
Test status
Simulation time 2048185760 ps
CPU time 9.91 seconds
Started Jul 16 05:04:24 PM PDT 24
Finished Jul 16 05:04:35 PM PDT 24
Peak memory 217616 kb
Host smart-f3693653-da95-4433-8299-c0c99ec12b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121259180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2121259180
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.4176112747
Short name T667
Test name
Test status
Simulation time 644245773 ps
CPU time 8.36 seconds
Started Jul 16 05:04:23 PM PDT 24
Finished Jul 16 05:04:33 PM PDT 24
Peak memory 216760 kb
Host smart-4a08d9b8-1e73-49bf-b3d6-2040abbf37d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176112747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.4176112747
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3309089310
Short name T780
Test name
Test status
Simulation time 19281852775 ps
CPU time 59.59 seconds
Started Jul 16 05:04:26 PM PDT 24
Finished Jul 16 05:05:26 PM PDT 24
Peak memory 219284 kb
Host smart-fdd64439-3634-4c11-afea-3aa6bd8f2998
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309089310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3309089310
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3149255446
Short name T749
Test name
Test status
Simulation time 518157558 ps
CPU time 5.84 seconds
Started Jul 16 05:04:28 PM PDT 24
Finished Jul 16 05:04:35 PM PDT 24
Peak memory 217060 kb
Host smart-52ea017f-90cd-4512-863e-139dbcab8c33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149255446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
149255446
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2867015697
Short name T416
Test name
Test status
Simulation time 392490417 ps
CPU time 4.09 seconds
Started Jul 16 05:04:28 PM PDT 24
Finished Jul 16 05:04:33 PM PDT 24
Peak memory 221088 kb
Host smart-fbe6c229-a07e-499d-b0f8-ea5e7ef7685b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867015697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2867015697
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.906874644
Short name T242
Test name
Test status
Simulation time 1445397629 ps
CPU time 37.71 seconds
Started Jul 16 05:04:22 PM PDT 24
Finished Jul 16 05:05:01 PM PDT 24
Peak memory 216940 kb
Host smart-72a5134d-4d23-45e9-a365-ba676cc421c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906874644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.906874644
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3575768677
Short name T21
Test name
Test status
Simulation time 325687740 ps
CPU time 5.23 seconds
Started Jul 16 05:04:24 PM PDT 24
Finished Jul 16 05:04:30 PM PDT 24
Peak memory 217104 kb
Host smart-892b223a-8f44-44f8-9dc8-b7c9b61ef30d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575768677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3575768677
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2279821141
Short name T571
Test name
Test status
Simulation time 11502932731 ps
CPU time 66.83 seconds
Started Jul 16 05:04:22 PM PDT 24
Finished Jul 16 05:05:30 PM PDT 24
Peak memory 283188 kb
Host smart-be9f6032-d2cf-4765-bf7f-6883105e2d89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279821141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2279821141
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1161076227
Short name T339
Test name
Test status
Simulation time 825545098 ps
CPU time 11.9 seconds
Started Jul 16 05:04:26 PM PDT 24
Finished Jul 16 05:04:39 PM PDT 24
Peak memory 249896 kb
Host smart-50864bb7-37f0-4f97-8f6d-b9c28a169b42
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161076227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1161076227
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2783934982
Short name T261
Test name
Test status
Simulation time 995899359 ps
CPU time 2.7 seconds
Started Jul 16 05:04:27 PM PDT 24
Finished Jul 16 05:04:31 PM PDT 24
Peak memory 217704 kb
Host smart-c8fd147f-b4ec-4d12-8e9b-6b15099a3f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783934982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2783934982
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2261534605
Short name T648
Test name
Test status
Simulation time 1087131139 ps
CPU time 18.41 seconds
Started Jul 16 05:04:27 PM PDT 24
Finished Jul 16 05:04:46 PM PDT 24
Peak memory 214060 kb
Host smart-ed577d4f-c82a-4f1d-9167-6ec1f91b3605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261534605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2261534605
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1728995665
Short name T56
Test name
Test status
Simulation time 395450757 ps
CPU time 17.08 seconds
Started Jul 16 05:04:26 PM PDT 24
Finished Jul 16 05:04:44 PM PDT 24
Peak memory 225440 kb
Host smart-89a50b0d-0a71-4c72-9414-a38ca20975ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728995665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1728995665
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3322227526
Short name T213
Test name
Test status
Simulation time 4657150995 ps
CPU time 17.77 seconds
Started Jul 16 05:04:34 PM PDT 24
Finished Jul 16 05:04:53 PM PDT 24
Peak memory 225484 kb
Host smart-6a3cf0c4-10b0-4881-8024-36f08232e9bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322227526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3322227526
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1856536628
Short name T717
Test name
Test status
Simulation time 308887000 ps
CPU time 7.88 seconds
Started Jul 16 05:04:28 PM PDT 24
Finished Jul 16 05:04:36 PM PDT 24
Peak memory 225452 kb
Host smart-ca33940d-45ab-49e7-a28e-fea86ee87fbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856536628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
856536628
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2978619498
Short name T439
Test name
Test status
Simulation time 214019642 ps
CPU time 9.56 seconds
Started Jul 16 05:04:23 PM PDT 24
Finished Jul 16 05:04:34 PM PDT 24
Peak memory 224380 kb
Host smart-11cef5ab-0d8e-4469-97fa-01ce1a833afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978619498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2978619498
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2896499966
Short name T438
Test name
Test status
Simulation time 113501087 ps
CPU time 2.46 seconds
Started Jul 16 05:04:26 PM PDT 24
Finished Jul 16 05:04:30 PM PDT 24
Peak memory 213892 kb
Host smart-49740fca-b7bd-4268-afce-4c1086089d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896499966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2896499966
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2490167633
Short name T362
Test name
Test status
Simulation time 236566751 ps
CPU time 27.33 seconds
Started Jul 16 05:04:23 PM PDT 24
Finished Jul 16 05:04:52 PM PDT 24
Peak memory 250420 kb
Host smart-de606d8d-dfe1-4e4e-aad3-6a8b4241eada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490167633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2490167633
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3202125907
Short name T597
Test name
Test status
Simulation time 365812606 ps
CPU time 7.08 seconds
Started Jul 16 05:04:23 PM PDT 24
Finished Jul 16 05:04:32 PM PDT 24
Peak memory 249640 kb
Host smart-da0e2469-2327-4dad-9e14-91ede483469a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202125907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3202125907
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1788619252
Short name T396
Test name
Test status
Simulation time 2446062034 ps
CPU time 61.73 seconds
Started Jul 16 05:04:35 PM PDT 24
Finished Jul 16 05:05:38 PM PDT 24
Peak memory 250512 kb
Host smart-613c6d17-82fd-4179-a221-c4d29abc75eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788619252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1788619252
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3618567371
Short name T850
Test name
Test status
Simulation time 23493784 ps
CPU time 1.07 seconds
Started Jul 16 05:04:29 PM PDT 24
Finished Jul 16 05:04:30 PM PDT 24
Peak memory 211244 kb
Host smart-ffa6d7b6-b3a0-40c1-9c96-3d22a7fef20b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618567371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3618567371
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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