Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51101 |
1 |
|
|
T1 |
78 |
|
T2 |
182 |
|
T3 |
6 |
auto[1] |
1771 |
1 |
|
|
T2 |
16 |
|
T5 |
8 |
|
T39 |
9 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52216 |
1 |
|
|
T1 |
78 |
|
T2 |
198 |
|
T3 |
6 |
auto[1] |
656 |
1 |
|
|
T33 |
12 |
|
T67 |
21 |
|
T48 |
21 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50993 |
1 |
|
|
T1 |
72 |
|
T2 |
195 |
|
T3 |
6 |
auto[1] |
1879 |
1 |
|
|
T1 |
6 |
|
T2 |
3 |
|
T5 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51051 |
1 |
|
|
T1 |
69 |
|
T2 |
197 |
|
T3 |
6 |
auto[1] |
1821 |
1 |
|
|
T1 |
9 |
|
T2 |
1 |
|
T11 |
1 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51048 |
1 |
|
|
T1 |
71 |
|
T2 |
197 |
|
T3 |
6 |
auto[1] |
1824 |
1 |
|
|
T1 |
7 |
|
T2 |
1 |
|
T30 |
1 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
48072 |
1 |
|
|
T1 |
78 |
|
T2 |
152 |
|
T11 |
3 |
no_err_inj |
4800 |
1 |
|
|
T2 |
46 |
|
T3 |
6 |
|
T11 |
8 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51034 |
1 |
|
|
T1 |
78 |
|
T2 |
190 |
|
T3 |
6 |
auto[1] |
1838 |
1 |
|
|
T2 |
8 |
|
T5 |
9 |
|
T39 |
8 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52209 |
1 |
|
|
T1 |
78 |
|
T2 |
198 |
|
T3 |
6 |
auto[1] |
663 |
1 |
|
|
T33 |
7 |
|
T67 |
14 |
|
T48 |
20 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36854 |
1 |
|
|
T1 |
78 |
|
T2 |
169 |
|
T3 |
6 |
auto[1] |
16018 |
1 |
|
|
T2 |
29 |
|
T4 |
10 |
|
T5 |
33 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51037 |
1 |
|
|
T1 |
67 |
|
T2 |
197 |
|
T3 |
6 |
auto[1] |
1835 |
1 |
|
|
T1 |
11 |
|
T2 |
1 |
|
T11 |
1 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51077 |
1 |
|
|
T1 |
68 |
|
T2 |
197 |
|
T3 |
6 |
auto[1] |
1795 |
1 |
|
|
T1 |
10 |
|
T2 |
1 |
|
T5 |
3 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51098 |
1 |
|
|
T1 |
69 |
|
T2 |
197 |
|
T3 |
6 |
auto[1] |
1774 |
1 |
|
|
T1 |
9 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51066 |
1 |
|
|
T1 |
78 |
|
T2 |
186 |
|
T3 |
6 |
auto[1] |
1806 |
1 |
|
|
T2 |
12 |
|
T5 |
9 |
|
T39 |
14 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50391 |
1 |
|
|
T1 |
78 |
|
T2 |
159 |
|
T3 |
6 |
auto[1] |
2481 |
1 |
|
|
T2 |
39 |
|
T31 |
19 |
|
T65 |
19 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52185 |
1 |
|
|
T1 |
78 |
|
T2 |
198 |
|
T3 |
6 |
auto[1] |
687 |
1 |
|
|
T33 |
13 |
|
T67 |
17 |
|
T48 |
20 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52229 |
1 |
|
|
T1 |
78 |
|
T2 |
198 |
|
T3 |
6 |
auto[1] |
643 |
1 |
|
|
T33 |
11 |
|
T67 |
17 |
|
T48 |
15 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52157 |
1 |
|
|
T1 |
78 |
|
T2 |
198 |
|
T3 |
6 |
auto[1] |
715 |
1 |
|
|
T33 |
8 |
|
T67 |
15 |
|
T48 |
18 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49924 |
1 |
|
|
T1 |
78 |
|
T2 |
171 |
|
T3 |
6 |
auto[1] |
2948 |
1 |
|
|
T2 |
27 |
|
T11 |
11 |
|
T5 |
25 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49104 |
1 |
|
|
T1 |
78 |
|
T2 |
198 |
|
T3 |
6 |
auto[1] |
3768 |
1 |
|
|
T40 |
77 |
|
T52 |
90 |
|
T53 |
86 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51006 |
1 |
|
|
T1 |
70 |
|
T2 |
196 |
|
T3 |
6 |
auto[1] |
1866 |
1 |
|
|
T1 |
8 |
|
T2 |
2 |
|
T5 |
1 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51086 |
1 |
|
|
T1 |
68 |
|
T2 |
197 |
|
T3 |
6 |
auto[1] |
1786 |
1 |
|
|
T1 |
10 |
|
T2 |
1 |
|
T11 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51021 |
1 |
|
|
T1 |
70 |
|
T2 |
196 |
|
T3 |
6 |
auto[1] |
1851 |
1 |
|
|
T1 |
8 |
|
T2 |
2 |
|
T5 |
3 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51045 |
1 |
|
|
T1 |
78 |
|
T2 |
184 |
|
T3 |
6 |
auto[1] |
1827 |
1 |
|
|
T2 |
14 |
|
T5 |
9 |
|
T39 |
11 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47309 |
1 |
|
|
T1 |
78 |
|
T2 |
186 |
|
T3 |
6 |
auto[1] |
5563 |
1 |
|
|
T2 |
12 |
|
T12 |
89 |
|
T16 |
92 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49055 |
1 |
|
|
T1 |
78 |
|
T2 |
198 |
|
T3 |
6 |
auto[1] |
3817 |
1 |
|
|
T15 |
79 |
|
T29 |
54 |
|
T66 |
54 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52872 |
1 |
|
|
T1 |
78 |
|
T2 |
198 |
|
T3 |
6 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51056 |
1 |
|
|
T1 |
78 |
|
T2 |
183 |
|
T3 |
6 |
auto[1] |
1816 |
1 |
|
|
T2 |
15 |
|
T5 |
10 |
|
T39 |
13 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51120 |
1 |
|
|
T1 |
78 |
|
T2 |
187 |
|
T3 |
6 |
auto[1] |
1752 |
1 |
|
|
T2 |
11 |
|
T5 |
6 |
|
T39 |
17 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51034 |
1 |
|
|
T1 |
78 |
|
T2 |
186 |
|
T3 |
6 |
auto[1] |
1838 |
1 |
|
|
T2 |
12 |
|
T5 |
9 |
|
T39 |
17 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
46578 |
1 |
|
|
T1 |
78 |
|
T2 |
139 |
|
T12 |
89 |
auto[0] |
no_err_inj |
3346 |
1 |
|
|
T2 |
32 |
|
T3 |
6 |
|
T4 |
10 |
auto[1] |
err_inj |
1494 |
1 |
|
|
T2 |
13 |
|
T11 |
3 |
|
T5 |
11 |
auto[1] |
no_err_inj |
1454 |
1 |
|
|
T2 |
14 |
|
T11 |
8 |
|
T5 |
14 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48300 |
1 |
|
|
T1 |
68 |
|
T2 |
171 |
|
T3 |
6 |
auto[0] |
auto[1] |
1624 |
1 |
|
|
T1 |
10 |
|
T18 |
10 |
|
T19 |
5 |
auto[1] |
auto[0] |
2786 |
1 |
|
|
T2 |
26 |
|
T11 |
10 |
|
T5 |
24 |
auto[1] |
auto[1] |
162 |
1 |
|
|
T2 |
1 |
|
T11 |
1 |
|
T5 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48288 |
1 |
|
|
T1 |
68 |
|
T2 |
171 |
|
T3 |
6 |
auto[0] |
auto[1] |
1636 |
1 |
|
|
T1 |
10 |
|
T18 |
11 |
|
T19 |
5 |
auto[1] |
auto[0] |
2789 |
1 |
|
|
T2 |
26 |
|
T11 |
11 |
|
T5 |
22 |
auto[1] |
auto[1] |
159 |
1 |
|
|
T2 |
1 |
|
T5 |
3 |
|
T30 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48230 |
1 |
|
|
T1 |
70 |
|
T2 |
171 |
|
T3 |
6 |
auto[0] |
auto[1] |
1694 |
1 |
|
|
T1 |
8 |
|
T18 |
10 |
|
T19 |
4 |
auto[1] |
auto[0] |
2791 |
1 |
|
|
T2 |
25 |
|
T11 |
11 |
|
T5 |
22 |
auto[1] |
auto[1] |
157 |
1 |
|
|
T2 |
2 |
|
T5 |
3 |
|
T32 |
2 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48258 |
1 |
|
|
T1 |
69 |
|
T2 |
171 |
|
T3 |
6 |
auto[0] |
auto[1] |
1666 |
1 |
|
|
T1 |
9 |
|
T18 |
8 |
|
T19 |
9 |
auto[1] |
auto[0] |
2793 |
1 |
|
|
T2 |
26 |
|
T11 |
10 |
|
T5 |
24 |
auto[1] |
auto[1] |
155 |
1 |
|
|
T2 |
1 |
|
T11 |
1 |
|
T5 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48291 |
1 |
|
|
T1 |
71 |
|
T2 |
171 |
|
T3 |
6 |
auto[0] |
auto[1] |
1633 |
1 |
|
|
T1 |
7 |
|
T18 |
6 |
|
T19 |
6 |
auto[1] |
auto[0] |
2757 |
1 |
|
|
T2 |
26 |
|
T11 |
11 |
|
T5 |
25 |
auto[1] |
auto[1] |
191 |
1 |
|
|
T2 |
1 |
|
T30 |
1 |
|
T32 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48231 |
1 |
|
|
T1 |
72 |
|
T2 |
171 |
|
T3 |
6 |
auto[0] |
auto[1] |
1693 |
1 |
|
|
T1 |
6 |
|
T18 |
14 |
|
T19 |
5 |
auto[1] |
auto[0] |
2762 |
1 |
|
|
T2 |
24 |
|
T11 |
11 |
|
T5 |
24 |
auto[1] |
auto[1] |
186 |
1 |
|
|
T2 |
3 |
|
T5 |
1 |
|
T32 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35791 |
1 |
|
|
T1 |
78 |
|
T2 |
153 |
|
T3 |
6 |
auto[0] |
auto[1] |
1063 |
1 |
|
|
T2 |
16 |
|
T5 |
8 |
|
T39 |
9 |
auto[1] |
auto[0] |
15310 |
1 |
|
|
T2 |
29 |
|
T4 |
10 |
|
T5 |
33 |
auto[1] |
auto[1] |
708 |
1 |
|
|
T18 |
17 |
|
T19 |
7 |
|
T20 |
21 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35777 |
1 |
|
|
T1 |
78 |
|
T2 |
161 |
|
T3 |
6 |
auto[0] |
auto[1] |
1077 |
1 |
|
|
T2 |
8 |
|
T5 |
9 |
|
T39 |
8 |
auto[1] |
auto[0] |
15257 |
1 |
|
|
T2 |
29 |
|
T4 |
10 |
|
T5 |
33 |
auto[1] |
auto[1] |
761 |
1 |
|
|
T18 |
10 |
|
T19 |
11 |
|
T20 |
18 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35410 |
1 |
|
|
T1 |
78 |
|
T2 |
130 |
|
T3 |
6 |
auto[0] |
auto[1] |
1444 |
1 |
|
|
T2 |
39 |
|
T31 |
19 |
|
T65 |
19 |
auto[1] |
auto[0] |
14981 |
1 |
|
|
T2 |
29 |
|
T4 |
10 |
|
T5 |
33 |
auto[1] |
auto[1] |
1037 |
1 |
|
|
T19 |
43 |
|
T20 |
14 |
|
T47 |
18 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35751 |
1 |
|
|
T1 |
78 |
|
T2 |
157 |
|
T3 |
6 |
auto[0] |
auto[1] |
1103 |
1 |
|
|
T2 |
12 |
|
T5 |
9 |
|
T39 |
14 |
auto[1] |
auto[0] |
15315 |
1 |
|
|
T2 |
29 |
|
T4 |
10 |
|
T5 |
33 |
auto[1] |
auto[1] |
703 |
1 |
|
|
T18 |
7 |
|
T19 |
8 |
|
T20 |
20 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31986 |
1 |
|
|
T1 |
78 |
|
T2 |
157 |
|
T3 |
6 |
auto[0] |
auto[1] |
4868 |
1 |
|
|
T2 |
12 |
|
T12 |
89 |
|
T16 |
92 |
auto[1] |
auto[0] |
15323 |
1 |
|
|
T2 |
29 |
|
T4 |
10 |
|
T5 |
33 |
auto[1] |
auto[1] |
695 |
1 |
|
|
T18 |
9 |
|
T19 |
5 |
|
T20 |
21 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35857 |
1 |
|
|
T1 |
68 |
|
T2 |
168 |
|
T3 |
6 |
auto[0] |
auto[1] |
997 |
1 |
|
|
T1 |
10 |
|
T2 |
1 |
|
T11 |
1 |
auto[1] |
auto[0] |
15229 |
1 |
|
|
T2 |
29 |
|
T4 |
10 |
|
T5 |
32 |
auto[1] |
auto[1] |
789 |
1 |
|
|
T5 |
1 |
|
T18 |
10 |
|
T19 |
5 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35800 |
1 |
|
|
T1 |
70 |
|
T2 |
167 |
|
T3 |
6 |
auto[0] |
auto[1] |
1054 |
1 |
|
|
T1 |
8 |
|
T2 |
2 |
|
T18 |
2 |
auto[1] |
auto[0] |
15206 |
1 |
|
|
T2 |
29 |
|
T4 |
10 |
|
T5 |
32 |
auto[1] |
auto[1] |
812 |
1 |
|
|
T5 |
1 |
|
T18 |
16 |
|
T19 |
8 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35847 |
1 |
|
|
T1 |
68 |
|
T2 |
168 |
|
T3 |
6 |
auto[0] |
auto[1] |
1007 |
1 |
|
|
T1 |
10 |
|
T2 |
1 |
|
T30 |
1 |
auto[1] |
auto[0] |
15230 |
1 |
|
|
T2 |
29 |
|
T4 |
10 |
|
T5 |
30 |
auto[1] |
auto[1] |
788 |
1 |
|
|
T5 |
3 |
|
T18 |
11 |
|
T19 |
6 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35776 |
1 |
|
|
T1 |
67 |
|
T2 |
168 |
|
T3 |
6 |
auto[0] |
auto[1] |
1078 |
1 |
|
|
T1 |
11 |
|
T2 |
1 |
|
T11 |
1 |
auto[1] |
auto[0] |
15261 |
1 |
|
|
T2 |
29 |
|
T4 |
10 |
|
T5 |
33 |
auto[1] |
auto[1] |
757 |
1 |
|
|
T18 |
6 |
|
T19 |
7 |
|
T20 |
30 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35819 |
1 |
|
|
T1 |
69 |
|
T2 |
168 |
|
T3 |
6 |
auto[0] |
auto[1] |
1035 |
1 |
|
|
T1 |
9 |
|
T2 |
1 |
|
T11 |
1 |
auto[1] |
auto[0] |
15232 |
1 |
|
|
T2 |
29 |
|
T4 |
10 |
|
T5 |
32 |
auto[1] |
auto[1] |
786 |
1 |
|
|
T5 |
1 |
|
T18 |
8 |
|
T19 |
9 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35790 |
1 |
|
|
T1 |
72 |
|
T2 |
166 |
|
T3 |
6 |
auto[0] |
auto[1] |
1064 |
1 |
|
|
T1 |
6 |
|
T2 |
3 |
|
T32 |
1 |
auto[1] |
auto[0] |
15203 |
1 |
|
|
T2 |
29 |
|
T4 |
10 |
|
T5 |
32 |
auto[1] |
auto[1] |
815 |
1 |
|
|
T5 |
1 |
|
T18 |
14 |
|
T19 |
5 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35738 |
1 |
|
|
T1 |
78 |
|
T2 |
157 |
|
T3 |
6 |
auto[0] |
auto[1] |
1116 |
1 |
|
|
T2 |
12 |
|
T5 |
9 |
|
T39 |
17 |
auto[1] |
auto[0] |
15296 |
1 |
|
|
T2 |
29 |
|
T4 |
10 |
|
T5 |
33 |
auto[1] |
auto[1] |
722 |
1 |
|
|
T18 |
7 |
|
T19 |
12 |
|
T20 |
19 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35824 |
1 |
|
|
T1 |
78 |
|
T2 |
158 |
|
T3 |
6 |
auto[0] |
auto[1] |
1030 |
1 |
|
|
T2 |
11 |
|
T5 |
6 |
|
T39 |
17 |
auto[1] |
auto[0] |
15296 |
1 |
|
|
T2 |
29 |
|
T4 |
10 |
|
T5 |
33 |
auto[1] |
auto[1] |
722 |
1 |
|
|
T18 |
9 |
|
T19 |
14 |
|
T20 |
12 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35129 |
1 |
|
|
T1 |
78 |
|
T2 |
142 |
|
T3 |
6 |
auto[0] |
auto[1] |
1725 |
1 |
|
|
T2 |
27 |
|
T11 |
11 |
|
T30 |
13 |
auto[1] |
auto[0] |
14795 |
1 |
|
|
T2 |
29 |
|
T4 |
10 |
|
T5 |
8 |
auto[1] |
auto[1] |
1223 |
1 |
|
|
T5 |
25 |
|
T19 |
13 |
|
T20 |
14 |