Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98821521

1

T1

22428

T2

141889

T3

2910

auto[1]

1364098

1

T1

3762

T2

2970

T11

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98794340

1

T1

23913

T2

141839

T3

2910

auto[1]

1391279

1

T1

2277

T2

3465

T11

99

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7139588	1			T1	7995		T2	19375		T3	531
auto[IdleSt]	21432606	1			T1	1348		T2	129415		T3	635
auto[ClkMuxSt]	35384	1			T2	188		T3	6		T11	8
auto[CntIncrSt]	35104	1			T2	188		T3	6		T11	8
auto[CntProgSt]	1327677	1			T2	341		T3	248		T11	113
auto[TransCheckSt]	27193	1			T2	125		T3	6		T11	8
auto[TokenHashSt]	38435878	1			T2	122133		T3	64		T11	408
auto[FlashRmaSt]	34802	1			T2	164		T3	6		T11	48
auto[TokenCheck0St]	12501	1			T2	66		T3	6		T11	8
auto[TokenCheck1St]	9253	1			T2	59		T3	6		T11	8
auto[TransProgSt]	328484	1			T2	116		T3	265		T11	132
auto[PostTransSt]	12668903	1			T2	38984		T3	1131		T11	1412
auto[ScrapSt]	143774	1			T2	7		T5	28		T40	3
auto[EscalateSt]	6801668	1			T1	8544		T2	10121		T11	553
auto[InvalidSt]	11750929	1			T1	8293		T2	1371		T11	232

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1875	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11750929	1			T1	8293		T2	1371		T11	232
EscalateSt	6801668	1			T1	8544		T2	10121		T11	553
ScrapSt	143774	1			T2	7		T5	28		T40	3
PostTransSt	12668903	1			T2	38984		T3	1131		T11	1412
TransProgSt	328484	1			T2	116		T3	265		T11	132
TokenCheck1St	9253	1			T2	59		T3	6		T11	8
TokenCheck0St	12501	1			T2	66		T3	6		T11	8
FlashRmaSt	34802	1			T2	164		T3	6		T11	48
TokenHashSt	38435878	1			T2	122133		T3	64		T11	408
TransCheckSt	27193	1			T2	125		T3	6		T11	8
CntProgSt	1327677	1			T2	341		T3	248		T11	113
CntIncrSt	35104	1			T2	188		T3	6		T11	8
ClkMuxSt	35384	1			T2	188		T3	6		T11	8
IdleSt	21432606	1			T1	1348		T2	129415		T3	635
ResetSt	7139588	1			T1	7995		T2	19375		T3	531
arcs[ResetSt=>IdleSt]	53342	1			T1	70		T2	211		T3	6
arcs[IdleSt=>ScrapSt]	321	1			T2	1		T5	2		T40	1
arcs[IdleSt=>ClkMuxSt]	35176	1			T2	188		T3	6		T11	8
arcs[ClkMuxSt=>CntIncrSt]	35104	1			T2	188		T3	6		T11	8
arcs[CntIncrSt=>PostTransSt]	1752	1			T2	11		T5	6		T39	17
arcs[CntIncrSt=>CntProgSt]	33295	1			T2	177		T3	6		T11	8
arcs[CntProgSt=>PostTransSt]	4881	1			T2	52		T5	8		T31	19
arcs[CntProgSt=>TransCheckSt]	27193	1			T2	125		T3	6		T11	8
arcs[TransCheckSt=>PostTransSt]	3703	1			T2	13		T15	35		T5	9
arcs[TransCheckSt=>TokenHashSt]	23391	1			T2	112		T3	6		T11	8
arcs[TokenHashSt=>PostTransSt]	10171	1			T2	43		T12	89		T15	8
arcs[TokenHashSt=>FlashRmaSt]	12598	1			T2	66		T3	6		T11	8
arcs[FlashRmaSt=>TokenCheck0St]	12501	1			T2	66		T3	6		T11	8
arcs[TokenCheck0St=>PostTransSt]	3221	1			T2	7		T15	18		T5	8
arcs[TokenCheck0St=>TokenCheck1St]	9253	1			T2	59		T3	6		T11	8
arcs[TokenCheck1St=>PostTransSt]	683	1			T2	1		T15	18		T5	1
arcs[TransProgSt=>PostTransSt]	7657	1			T2	58		T3	6		T11	8
arcs[IdleSt=>EscalateSt]	202	1			T53	11		T55	10		T56	9
arcs[ClkMuxSt=>EscalateSt]	72	1			T52	4		T53	1		T54	1
arcs[CntIncrSt=>EscalateSt]	57	1			T40	1		T52	1		T53	1
arcs[CntProgSt=>EscalateSt]	1221	1			T40	9		T52	33		T53	28
arcs[TransCheckSt=>EscalateSt]	99	1			T40	8		T53	3		T61	1
arcs[TokenHashSt=>EscalateSt]	622	1			T2	3		T40	24		T18	1
arcs[FlashRmaSt=>EscalateSt]	97	1			T40	5		T52	3		T53	4
arcs[TokenCheck0St=>EscalateSt]	27	1			T40	1		T53	2		T60	1
arcs[TokenCheck1St=>EscalateSt]	146	1			T40	5		T52	5		T53	6
arcs[TransProgSt=>EscalateSt]	767	1			T40	9		T52	23		T53	17
arcs[PostTransSt=>EscalateSt]	5070	1			T2	52		T5	8		T40	12
arcs[InvalidSt=>EscalateSt]	13462	1			T1	61		T2	10		T11	3

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7139432	1			T1	7995		T2	19375		T3	531
auto[0]	auto[IdleSt]	21432480	1			T1	1348		T2	129415		T3	635
auto[0]	auto[ClkMuxSt]	35333	1			T2	188		T3	6		T11	8
auto[0]	auto[CntIncrSt]	35060	1			T2	188		T3	6		T11	8
auto[0]	auto[CntProgSt]	1326905	1			T2	341		T3	248		T11	113
auto[0]	auto[TransCheckSt]	27121	1			T2	125		T3	6		T11	8
auto[0]	auto[TokenHashSt]	38435474	1			T2	122133		T3	64		T11	408
auto[0]	auto[FlashRmaSt]	34734	1			T2	164		T3	6		T11	48
auto[0]	auto[TokenCheck0St]	12484	1			T2	66		T3	6		T11	8
auto[0]	auto[TokenCheck1St]	9158	1			T2	59		T3	6		T11	8
auto[0]	auto[TransProgSt]	327982	1			T2	116		T3	265		T11	132
auto[0]	auto[PostTransSt]	12666337	1			T2	38960		T3	1131		T11	1412
auto[0]	auto[ScrapSt]	143737	1			T2	7		T5	28		T40	2
auto[0]	auto[EscalateSt]	5449198	1			T1	4820		T2	7181		T11	357
auto[0]	auto[InvalidSt]	11744211	1			T1	8255		T2	1367		T11	230
auto[1]	auto[ResetSt]	156	1			T40	2		T52	3		T53	1
auto[1]	auto[IdleSt]	126	1			T53	8		T55	5		T56	6
auto[1]	auto[ClkMuxSt]	51	1			T52	2		T54	1		T55	1
auto[1]	auto[CntIncrSt]	44	1			T40	1		T52	1		T53	1
auto[1]	auto[CntProgSt]	772	1			T40	5		T52	15		T53	18
auto[1]	auto[TransCheckSt]	72	1			T40	4		T53	3		T61	1
auto[1]	auto[TokenHashSt]	404	1			T2	2		T40	19		T52	7
auto[1]	auto[FlashRmaSt]	68	1			T40	4		T52	1		T53	2
auto[1]	auto[TokenCheck0St]	17	1			T40	1		T53	2		T60	1
auto[1]	auto[TokenCheck1St]	95	1			T40	4		T52	2		T53	3
auto[1]	auto[TransProgSt]	502	1			T40	5		T52	17		T53	10
auto[1]	auto[PostTransSt]	2566	1			T2	24		T5	6		T40	7
auto[1]	auto[ScrapSt]	37	1			T40	1		T53	1		T56	1
auto[1]	auto[EscalateSt]	1352470	1			T1	3724		T2	2940		T11	196
auto[1]	auto[InvalidSt]	6718	1			T1	38		T2	4		T11	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7139412	1			T1	7995		T2	19375		T3	531
auto[0]	auto[IdleSt]	21432464	1			T1	1348		T2	129415		T3	635
auto[0]	auto[ClkMuxSt]	35338	1			T2	188		T3	6		T11	8
auto[0]	auto[CntIncrSt]	35069	1			T2	188		T3	6		T11	8
auto[0]	auto[CntProgSt]	1326829	1			T2	341		T3	248		T11	113
auto[0]	auto[TransCheckSt]	27124	1			T2	125		T3	6		T11	8
auto[0]	auto[TokenHashSt]	38435454	1			T2	122133		T3	64		T11	408
auto[0]	auto[FlashRmaSt]	34732	1			T2	164		T3	6		T11	48
auto[0]	auto[TokenCheck0St]	12481	1			T2	66		T3	6		T11	8
auto[0]	auto[TokenCheck1St]	9158	1			T2	59		T3	6		T11	8
auto[0]	auto[TransProgSt]	327952	1			T2	116		T3	265		T11	132
auto[0]	auto[PostTransSt]	12666348	1			T2	38956		T3	1131		T11	1412
auto[0]	auto[ScrapSt]	143729	1			T2	7		T5	28		T40	2
auto[0]	auto[EscalateSt]	5422190	1			T1	6290		T2	6691		T11	455
auto[0]	auto[InvalidSt]	11744185	1			T1	8270		T2	1365		T11	231
auto[1]	auto[ResetSt]	176	1			T40	1		T52	8		T53	4
auto[1]	auto[IdleSt]	142	1			T53	10		T55	8		T56	6
auto[1]	auto[ClkMuxSt]	46	1			T52	3		T53	1		T56	1
auto[1]	auto[CntIncrSt]	35	1			T40	1		T52	1		T54	1
auto[1]	auto[CntProgSt]	848	1			T40	7		T52	27		T53	19
auto[1]	auto[TransCheckSt]	69	1			T40	6		T53	3		T61	1
auto[1]	auto[TokenHashSt]	424	1			T2	1		T40	14		T18	1
auto[1]	auto[FlashRmaSt]	70	1			T40	3		T52	2		T53	4
auto[1]	auto[TokenCheck0St]	20	1			T40	1		T53	1		T60	1
auto[1]	auto[TokenCheck1St]	95	1			T40	1		T52	4		T53	5
auto[1]	auto[TransProgSt]	532	1			T40	8		T52	15		T53	15
auto[1]	auto[PostTransSt]	2555	1			T2	28		T5	2		T40	10
auto[1]	auto[ScrapSt]	45	1			T40	1		T53	1		T56	2
auto[1]	auto[EscalateSt]	1379478	1			T1	2254		T2	3430		T11	98
auto[1]	auto[InvalidSt]	6744	1			T1	23		T2	6		T11	1