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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.16 97.99 95.41 93.40 100.00 98.55 98.51 96.29


Total test records in report: 999
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T201 /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3772736751 Jul 17 05:15:47 PM PDT 24 Jul 17 05:15:52 PM PDT 24 14321657 ps
T812 /workspace/coverage/default/36.lc_ctrl_state_failure.561106872 Jul 17 05:17:19 PM PDT 24 Jul 17 05:17:48 PM PDT 24 811849766 ps
T813 /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.836091240 Jul 17 05:13:57 PM PDT 24 Jul 17 05:14:00 PM PDT 24 201638125 ps
T814 /workspace/coverage/default/3.lc_ctrl_state_post_trans.408116095 Jul 17 05:13:25 PM PDT 24 Jul 17 05:13:34 PM PDT 24 244354848 ps
T815 /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2004777108 Jul 17 05:17:55 PM PDT 24 Jul 17 05:18:10 PM PDT 24 919810846 ps
T816 /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2560807906 Jul 17 05:17:16 PM PDT 24 Jul 17 05:17:27 PM PDT 24 4618729514 ps
T817 /workspace/coverage/default/17.lc_ctrl_alert_test.234210805 Jul 17 05:14:58 PM PDT 24 Jul 17 05:15:00 PM PDT 24 55451219 ps
T818 /workspace/coverage/default/1.lc_ctrl_claim_transition_if.3804521780 Jul 17 05:15:40 PM PDT 24 Jul 17 05:15:42 PM PDT 24 87011718 ps
T819 /workspace/coverage/default/2.lc_ctrl_sec_token_digest.297576329 Jul 17 05:13:29 PM PDT 24 Jul 17 05:13:41 PM PDT 24 459003288 ps
T820 /workspace/coverage/default/31.lc_ctrl_alert_test.787652872 Jul 17 05:17:48 PM PDT 24 Jul 17 05:17:51 PM PDT 24 59462916 ps
T821 /workspace/coverage/default/4.lc_ctrl_prog_failure.92934722 Jul 17 05:13:25 PM PDT 24 Jul 17 05:13:29 PM PDT 24 426361999 ps
T822 /workspace/coverage/default/33.lc_ctrl_jtag_access.1056077731 Jul 17 05:15:58 PM PDT 24 Jul 17 05:16:13 PM PDT 24 243496638 ps
T823 /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.562367675 Jul 17 05:17:35 PM PDT 24 Jul 17 05:17:45 PM PDT 24 443294015 ps
T824 /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3302877873 Jul 17 05:18:09 PM PDT 24 Jul 17 05:18:26 PM PDT 24 721804763 ps
T825 /workspace/coverage/default/25.lc_ctrl_stress_all.4198707199 Jul 17 05:17:53 PM PDT 24 Jul 17 05:25:43 PM PDT 24 178672474926 ps
T826 /workspace/coverage/default/11.lc_ctrl_alert_test.2104924547 Jul 17 05:17:38 PM PDT 24 Jul 17 05:17:41 PM PDT 24 51296237 ps
T827 /workspace/coverage/default/2.lc_ctrl_state_failure.3298369492 Jul 17 05:13:18 PM PDT 24 Jul 17 05:13:51 PM PDT 24 867541722 ps
T828 /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2190143994 Jul 17 05:13:08 PM PDT 24 Jul 17 05:13:21 PM PDT 24 1339600967 ps
T829 /workspace/coverage/default/29.lc_ctrl_errors.3966017240 Jul 17 05:15:45 PM PDT 24 Jul 17 05:16:06 PM PDT 24 2043613243 ps
T830 /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2519720837 Jul 17 05:13:02 PM PDT 24 Jul 17 05:13:11 PM PDT 24 320646948 ps
T831 /workspace/coverage/default/7.lc_ctrl_state_failure.1124328936 Jul 17 05:13:56 PM PDT 24 Jul 17 05:14:25 PM PDT 24 843295155 ps
T832 /workspace/coverage/default/10.lc_ctrl_state_failure.110348289 Jul 17 05:14:03 PM PDT 24 Jul 17 05:14:33 PM PDT 24 199811022 ps
T833 /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2241794553 Jul 17 05:13:26 PM PDT 24 Jul 17 05:13:29 PM PDT 24 47816607 ps
T834 /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.367743700 Jul 17 05:17:51 PM PDT 24 Jul 17 05:24:34 PM PDT 24 47955641214 ps
T835 /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3874558291 Jul 17 05:13:15 PM PDT 24 Jul 17 05:13:17 PM PDT 24 40151802 ps
T836 /workspace/coverage/default/5.lc_ctrl_state_failure.2446314056 Jul 17 05:13:44 PM PDT 24 Jul 17 05:14:12 PM PDT 24 797813701 ps
T837 /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1322709169 Jul 17 05:17:16 PM PDT 24 Jul 17 05:17:33 PM PDT 24 1249265246 ps
T838 /workspace/coverage/default/42.lc_ctrl_jtag_access.2511916482 Jul 17 05:17:29 PM PDT 24 Jul 17 05:17:38 PM PDT 24 1067397317 ps
T839 /workspace/coverage/default/40.lc_ctrl_state_post_trans.2166256176 Jul 17 05:17:16 PM PDT 24 Jul 17 05:17:24 PM PDT 24 519078682 ps
T840 /workspace/coverage/default/46.lc_ctrl_jtag_access.24663111 Jul 17 05:18:12 PM PDT 24 Jul 17 05:18:17 PM PDT 24 77896831 ps
T841 /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1119110368 Jul 17 05:14:17 PM PDT 24 Jul 17 05:14:25 PM PDT 24 378207546 ps
T842 /workspace/coverage/default/23.lc_ctrl_prog_failure.3999550128 Jul 17 05:16:14 PM PDT 24 Jul 17 05:16:20 PM PDT 24 194877829 ps
T843 /workspace/coverage/default/35.lc_ctrl_errors.140277310 Jul 17 05:16:38 PM PDT 24 Jul 17 05:16:56 PM PDT 24 439640041 ps
T844 /workspace/coverage/default/48.lc_ctrl_sec_mubi.3537683844 Jul 17 05:18:15 PM PDT 24 Jul 17 05:18:34 PM PDT 24 671139301 ps
T845 /workspace/coverage/default/3.lc_ctrl_alert_test.2457561515 Jul 17 05:13:26 PM PDT 24 Jul 17 05:13:28 PM PDT 24 20888794 ps
T846 /workspace/coverage/default/10.lc_ctrl_sec_token_mux.320113746 Jul 17 05:15:01 PM PDT 24 Jul 17 05:15:17 PM PDT 24 406197235 ps
T847 /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3965828013 Jul 17 05:13:56 PM PDT 24 Jul 17 05:14:21 PM PDT 24 657649448 ps
T848 /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3888874808 Jul 17 05:15:50 PM PDT 24 Jul 17 05:16:08 PM PDT 24 259315982 ps
T849 /workspace/coverage/default/36.lc_ctrl_stress_all.619274658 Jul 17 05:17:12 PM PDT 24 Jul 17 05:18:29 PM PDT 24 14183382422 ps
T850 /workspace/coverage/default/20.lc_ctrl_state_failure.3032296712 Jul 17 05:17:36 PM PDT 24 Jul 17 05:17:56 PM PDT 24 181049204 ps
T851 /workspace/coverage/default/11.lc_ctrl_smoke.2525988368 Jul 17 05:14:14 PM PDT 24 Jul 17 05:14:16 PM PDT 24 29947640 ps
T852 /workspace/coverage/default/36.lc_ctrl_sec_token_mux.78241695 Jul 17 05:17:13 PM PDT 24 Jul 17 05:17:23 PM PDT 24 922137471 ps
T853 /workspace/coverage/default/11.lc_ctrl_jtag_errors.3128043856 Jul 17 05:14:15 PM PDT 24 Jul 17 05:15:05 PM PDT 24 5996549970 ps
T854 /workspace/coverage/default/8.lc_ctrl_sec_token_mux.2367783392 Jul 17 05:14:03 PM PDT 24 Jul 17 05:14:11 PM PDT 24 197989337 ps
T855 /workspace/coverage/default/15.lc_ctrl_prog_failure.474634905 Jul 17 05:14:39 PM PDT 24 Jul 17 05:14:44 PM PDT 24 245074152 ps
T134 /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.2989288314 Jul 17 05:15:03 PM PDT 24 Jul 17 05:28:41 PM PDT 24 566999849782 ps
T856 /workspace/coverage/default/6.lc_ctrl_jtag_errors.2073030955 Jul 17 05:13:54 PM PDT 24 Jul 17 05:14:58 PM PDT 24 19717867219 ps
T857 /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1620272683 Jul 17 05:15:02 PM PDT 24 Jul 17 05:15:11 PM PDT 24 1104018803 ps
T858 /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3515005557 Jul 17 05:13:43 PM PDT 24 Jul 17 05:14:56 PM PDT 24 1814725133 ps
T152 /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.2279251409 Jul 17 05:18:10 PM PDT 24 Jul 17 05:27:03 PM PDT 24 88478975744 ps
T859 /workspace/coverage/default/31.lc_ctrl_prog_failure.2291594092 Jul 17 05:16:06 PM PDT 24 Jul 17 05:16:16 PM PDT 24 287369334 ps
T860 /workspace/coverage/default/40.lc_ctrl_prog_failure.1952556388 Jul 17 05:17:51 PM PDT 24 Jul 17 05:17:57 PM PDT 24 20893876 ps
T861 /workspace/coverage/default/7.lc_ctrl_jtag_errors.2624439167 Jul 17 05:15:47 PM PDT 24 Jul 17 05:16:47 PM PDT 24 7091879269 ps
T862 /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3152461879 Jul 17 05:14:05 PM PDT 24 Jul 17 05:14:14 PM PDT 24 242182289 ps
T863 /workspace/coverage/default/5.lc_ctrl_security_escalation.2899725811 Jul 17 05:13:41 PM PDT 24 Jul 17 05:13:51 PM PDT 24 389773109 ps
T864 /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1340084786 Jul 17 05:13:43 PM PDT 24 Jul 17 05:13:49 PM PDT 24 458293734 ps
T865 /workspace/coverage/default/32.lc_ctrl_alert_test.3211330208 Jul 17 05:17:56 PM PDT 24 Jul 17 05:18:04 PM PDT 24 77701848 ps
T866 /workspace/coverage/default/34.lc_ctrl_errors.2647239754 Jul 17 05:17:22 PM PDT 24 Jul 17 05:17:34 PM PDT 24 229050920 ps
T867 /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2271570399 Jul 17 05:17:17 PM PDT 24 Jul 17 05:17:28 PM PDT 24 299159695 ps
T868 /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2130597104 Jul 17 05:17:50 PM PDT 24 Jul 17 05:17:53 PM PDT 24 23458545 ps
T869 /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3162330776 Jul 17 05:14:38 PM PDT 24 Jul 17 05:14:40 PM PDT 24 15788930 ps
T870 /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.228877725 Jul 17 05:14:14 PM PDT 24 Jul 17 05:14:16 PM PDT 24 13500143 ps
T871 /workspace/coverage/default/43.lc_ctrl_state_failure.3403053538 Jul 17 05:17:57 PM PDT 24 Jul 17 05:18:24 PM PDT 24 384608346 ps
T872 /workspace/coverage/default/44.lc_ctrl_smoke.2990785048 Jul 17 05:17:55 PM PDT 24 Jul 17 05:18:03 PM PDT 24 43211889 ps
T106 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1859638436 Jul 17 05:05:11 PM PDT 24 Jul 17 05:05:33 PM PDT 24 3990055770 ps
T111 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2552184220 Jul 17 05:04:37 PM PDT 24 Jul 17 05:04:47 PM PDT 24 769356864 ps
T112 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1730900060 Jul 17 05:05:36 PM PDT 24 Jul 17 05:05:38 PM PDT 24 237270818 ps
T101 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1636957444 Jul 17 05:05:12 PM PDT 24 Jul 17 05:05:15 PM PDT 24 81140616 ps
T107 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3615981487 Jul 17 05:04:38 PM PDT 24 Jul 17 05:04:42 PM PDT 24 64729499 ps
T873 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.624098705 Jul 17 05:05:00 PM PDT 24 Jul 17 05:05:02 PM PDT 24 249432646 ps
T131 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3980885208 Jul 17 05:05:00 PM PDT 24 Jul 17 05:05:03 PM PDT 24 387211862 ps
T97 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.226035935 Jul 17 05:05:26 PM PDT 24 Jul 17 05:05:32 PM PDT 24 369423014 ps
T874 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3764037076 Jul 17 05:05:00 PM PDT 24 Jul 17 05:05:03 PM PDT 24 53969971 ps
T98 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.905969038 Jul 17 05:05:41 PM PDT 24 Jul 17 05:05:49 PM PDT 24 127240957 ps
T99 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1812789447 Jul 17 05:05:25 PM PDT 24 Jul 17 05:05:30 PM PDT 24 129389301 ps
T102 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.212435838 Jul 17 05:05:13 PM PDT 24 Jul 17 05:05:17 PM PDT 24 117618867 ps
T103 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.115475464 Jul 17 05:05:39 PM PDT 24 Jul 17 05:05:44 PM PDT 24 130581958 ps
T104 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1313534191 Jul 17 05:05:25 PM PDT 24 Jul 17 05:05:30 PM PDT 24 35037640 ps
T153 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2905974060 Jul 17 05:05:24 PM PDT 24 Jul 17 05:05:27 PM PDT 24 17502216 ps
T193 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.636849680 Jul 17 05:05:27 PM PDT 24 Jul 17 05:05:30 PM PDT 24 132641155 ps
T105 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.386291338 Jul 17 05:05:25 PM PDT 24 Jul 17 05:05:30 PM PDT 24 28269011 ps
T875 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3802958309 Jul 17 05:04:48 PM PDT 24 Jul 17 05:04:51 PM PDT 24 40086666 ps
T113 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2435227097 Jul 17 05:05:00 PM PDT 24 Jul 17 05:05:05 PM PDT 24 125082877 ps
T178 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3397887441 Jul 17 05:05:00 PM PDT 24 Jul 17 05:05:02 PM PDT 24 12430831 ps
T179 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3602846620 Jul 17 05:04:48 PM PDT 24 Jul 17 05:04:51 PM PDT 24 14438192 ps
T118 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1718049835 Jul 17 05:05:23 PM PDT 24 Jul 17 05:05:26 PM PDT 24 263053694 ps
T129 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3858156976 Jul 17 05:04:47 PM PDT 24 Jul 17 05:04:53 PM PDT 24 164497392 ps
T135 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.446458864 Jul 17 05:05:12 PM PDT 24 Jul 17 05:05:16 PM PDT 24 256046510 ps
T876 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.785753213 Jul 17 05:04:50 PM PDT 24 Jul 17 05:04:55 PM PDT 24 122999216 ps
T194 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4293366865 Jul 17 05:05:23 PM PDT 24 Jul 17 05:05:26 PM PDT 24 77185477 ps
T115 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3828169037 Jul 17 05:05:23 PM PDT 24 Jul 17 05:05:26 PM PDT 24 89313207 ps
T136 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.515832601 Jul 17 05:04:49 PM PDT 24 Jul 17 05:04:53 PM PDT 24 40241272 ps
T877 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.710317896 Jul 17 05:04:48 PM PDT 24 Jul 17 05:04:52 PM PDT 24 66084743 ps
T137 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2838916496 Jul 17 05:05:01 PM PDT 24 Jul 17 05:05:05 PM PDT 24 31458180 ps
T195 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3508989510 Jul 17 05:05:23 PM PDT 24 Jul 17 05:05:25 PM PDT 24 25860926 ps
T878 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4022318374 Jul 17 05:04:49 PM PDT 24 Jul 17 05:04:53 PM PDT 24 101433257 ps
T180 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3977890018 Jul 17 05:04:49 PM PDT 24 Jul 17 05:04:52 PM PDT 24 22784395 ps
T879 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2468185794 Jul 17 05:05:02 PM PDT 24 Jul 17 05:05:06 PM PDT 24 40247169 ps
T130 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1027148515 Jul 17 05:05:24 PM PDT 24 Jul 17 05:05:27 PM PDT 24 61056753 ps
T196 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3887780579 Jul 17 05:05:42 PM PDT 24 Jul 17 05:05:46 PM PDT 24 25699907 ps
T880 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1760244327 Jul 17 05:04:35 PM PDT 24 Jul 17 05:05:05 PM PDT 24 1387478992 ps
T138 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.348678544 Jul 17 05:05:25 PM PDT 24 Jul 17 05:05:29 PM PDT 24 17717638 ps
T881 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2791616138 Jul 17 05:05:00 PM PDT 24 Jul 17 05:05:02 PM PDT 24 115919504 ps
T882 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.82911332 Jul 17 05:04:53 PM PDT 24 Jul 17 05:04:57 PM PDT 24 74628396 ps
T883 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1307585219 Jul 17 05:05:38 PM PDT 24 Jul 17 05:05:43 PM PDT 24 55753078 ps
T110 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1368424086 Jul 17 05:05:37 PM PDT 24 Jul 17 05:05:41 PM PDT 24 119684099 ps
T108 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4072988719 Jul 17 05:05:25 PM PDT 24 Jul 17 05:05:30 PM PDT 24 133305532 ps
T121 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3574513768 Jul 17 05:04:59 PM PDT 24 Jul 17 05:05:02 PM PDT 24 101177904 ps
T884 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2958766811 Jul 17 05:04:48 PM PDT 24 Jul 17 05:04:53 PM PDT 24 118688970 ps
T125 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4019340565 Jul 17 05:05:26 PM PDT 24 Jul 17 05:05:30 PM PDT 24 178064225 ps
T885 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1158608526 Jul 17 05:05:13 PM PDT 24 Jul 17 05:05:21 PM PDT 24 192657642 ps
T886 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3276706259 Jul 17 05:05:26 PM PDT 24 Jul 17 05:05:30 PM PDT 24 161669585 ps
T887 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.175083367 Jul 17 05:04:38 PM PDT 24 Jul 17 05:04:42 PM PDT 24 69194286 ps
T888 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2253581539 Jul 17 05:04:37 PM PDT 24 Jul 17 05:04:41 PM PDT 24 694554345 ps
T889 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1263083332 Jul 17 05:05:00 PM PDT 24 Jul 17 05:05:13 PM PDT 24 810161711 ps
T124 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1146591031 Jul 17 05:05:26 PM PDT 24 Jul 17 05:05:31 PM PDT 24 109992221 ps
T122 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2991652821 Jul 17 05:04:47 PM PDT 24 Jul 17 05:04:52 PM PDT 24 103736444 ps
T890 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.720981997 Jul 17 05:05:24 PM PDT 24 Jul 17 05:05:27 PM PDT 24 99703803 ps
T891 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3738615461 Jul 17 05:05:01 PM PDT 24 Jul 17 05:05:04 PM PDT 24 26464290 ps
T892 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4009205750 Jul 17 05:04:37 PM PDT 24 Jul 17 05:04:41 PM PDT 24 43579482 ps
T893 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3245633776 Jul 17 05:04:47 PM PDT 24 Jul 17 05:04:51 PM PDT 24 235677722 ps
T894 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.685307316 Jul 17 05:04:37 PM PDT 24 Jul 17 05:04:42 PM PDT 24 236719807 ps
T895 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.4143923684 Jul 17 05:05:38 PM PDT 24 Jul 17 05:05:42 PM PDT 24 14566099 ps
T896 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.24208445 Jul 17 05:04:51 PM PDT 24 Jul 17 05:04:56 PM PDT 24 75876255 ps
T897 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2727897667 Jul 17 05:04:59 PM PDT 24 Jul 17 05:05:02 PM PDT 24 20864953 ps
T898 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3088899740 Jul 17 05:04:48 PM PDT 24 Jul 17 05:04:53 PM PDT 24 1046540437 ps
T899 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.4229588417 Jul 17 05:05:10 PM PDT 24 Jul 17 05:05:13 PM PDT 24 524205636 ps
T900 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3859212634 Jul 17 05:04:36 PM PDT 24 Jul 17 05:04:40 PM PDT 24 106272663 ps
T901 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3030521257 Jul 17 05:05:00 PM PDT 24 Jul 17 05:05:04 PM PDT 24 90741260 ps
T902 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1358854970 Jul 17 05:04:37 PM PDT 24 Jul 17 05:04:41 PM PDT 24 88561270 ps
T181 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.248158179 Jul 17 05:05:00 PM PDT 24 Jul 17 05:05:04 PM PDT 24 26954263 ps
T182 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2944621770 Jul 17 05:04:36 PM PDT 24 Jul 17 05:04:40 PM PDT 24 272693212 ps
T903 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1801980123 Jul 17 05:04:51 PM PDT 24 Jul 17 05:05:00 PM PDT 24 1016177862 ps
T904 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1832409154 Jul 17 05:06:06 PM PDT 24 Jul 17 05:06:08 PM PDT 24 36570499 ps
T183 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.197543385 Jul 17 05:05:01 PM PDT 24 Jul 17 05:05:04 PM PDT 24 22108449 ps
T905 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3047510911 Jul 17 05:05:00 PM PDT 24 Jul 17 05:05:04 PM PDT 24 358355851 ps
T906 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.768940086 Jul 17 05:05:00 PM PDT 24 Jul 17 05:05:03 PM PDT 24 17146345 ps
T907 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1204258660 Jul 17 05:04:49 PM PDT 24 Jul 17 05:04:53 PM PDT 24 65427098 ps
T908 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2953231851 Jul 17 05:05:03 PM PDT 24 Jul 17 05:05:05 PM PDT 24 32123222 ps
T909 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1642083506 Jul 17 05:05:12 PM PDT 24 Jul 17 05:05:17 PM PDT 24 411668612 ps
T910 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2563524709 Jul 17 05:05:13 PM PDT 24 Jul 17 05:05:16 PM PDT 24 33290712 ps
T911 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.190138896 Jul 17 05:04:38 PM PDT 24 Jul 17 05:04:51 PM PDT 24 440389205 ps
T184 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3669858555 Jul 17 05:05:13 PM PDT 24 Jul 17 05:05:16 PM PDT 24 13357440 ps
T185 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3003374302 Jul 17 05:05:23 PM PDT 24 Jul 17 05:05:25 PM PDT 24 110047942 ps
T116 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1933946647 Jul 17 05:05:11 PM PDT 24 Jul 17 05:05:14 PM PDT 24 149932363 ps
T912 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1699163183 Jul 17 05:05:26 PM PDT 24 Jul 17 05:05:30 PM PDT 24 18120201 ps
T913 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1378717765 Jul 17 05:05:00 PM PDT 24 Jul 17 05:05:05 PM PDT 24 169628346 ps
T914 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3090174794 Jul 17 05:05:39 PM PDT 24 Jul 17 05:05:45 PM PDT 24 55879517 ps
T915 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2671680110 Jul 17 05:05:13 PM PDT 24 Jul 17 05:05:17 PM PDT 24 157082458 ps
T916 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.732457126 Jul 17 05:04:38 PM PDT 24 Jul 17 05:04:51 PM PDT 24 1690382403 ps
T917 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.311754773 Jul 17 05:05:30 PM PDT 24 Jul 17 05:05:32 PM PDT 24 52854452 ps
T918 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.359478258 Jul 17 05:05:13 PM PDT 24 Jul 17 05:05:16 PM PDT 24 109634375 ps
T919 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1633415108 Jul 17 05:05:39 PM PDT 24 Jul 17 05:05:46 PM PDT 24 30503029 ps
T920 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1999109812 Jul 17 05:05:13 PM PDT 24 Jul 17 05:05:16 PM PDT 24 320164933 ps
T921 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3011272760 Jul 17 05:05:41 PM PDT 24 Jul 17 05:05:48 PM PDT 24 40658735 ps
T922 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.4073588522 Jul 17 05:05:24 PM PDT 24 Jul 17 05:05:26 PM PDT 24 13758144 ps
T923 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2916115605 Jul 17 05:05:26 PM PDT 24 Jul 17 05:05:30 PM PDT 24 116238895 ps
T924 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1423039472 Jul 17 05:05:25 PM PDT 24 Jul 17 05:05:51 PM PDT 24 1144465350 ps
T925 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.449590353 Jul 17 05:05:25 PM PDT 24 Jul 17 05:05:29 PM PDT 24 111809117 ps
T926 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.471132841 Jul 17 05:05:24 PM PDT 24 Jul 17 05:06:10 PM PDT 24 4816672425 ps
T927 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2380167218 Jul 17 05:04:46 PM PDT 24 Jul 17 05:04:51 PM PDT 24 132790750 ps
T928 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1524975028 Jul 17 05:05:36 PM PDT 24 Jul 17 05:05:40 PM PDT 24 91351927 ps
T929 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.4267605136 Jul 17 05:05:37 PM PDT 24 Jul 17 05:05:40 PM PDT 24 15565707 ps
T930 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1328139075 Jul 17 05:05:23 PM PDT 24 Jul 17 05:05:25 PM PDT 24 157838214 ps
T931 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.213461037 Jul 17 05:05:01 PM PDT 24 Jul 17 05:05:14 PM PDT 24 1685083761 ps
T932 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3239795423 Jul 17 05:05:25 PM PDT 24 Jul 17 05:05:29 PM PDT 24 61092927 ps
T933 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1463912455 Jul 17 05:05:26 PM PDT 24 Jul 17 05:05:30 PM PDT 24 36569648 ps
T934 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1189862673 Jul 17 05:04:48 PM PDT 24 Jul 17 05:04:53 PM PDT 24 183393368 ps
T935 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3103038193 Jul 17 05:04:48 PM PDT 24 Jul 17 05:04:52 PM PDT 24 202590659 ps
T936 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2963013152 Jul 17 05:04:59 PM PDT 24 Jul 17 05:05:17 PM PDT 24 2986730237 ps
T937 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3042580295 Jul 17 05:04:49 PM PDT 24 Jul 17 05:04:52 PM PDT 24 21671626 ps
T938 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1787248835 Jul 17 05:05:10 PM PDT 24 Jul 17 05:05:12 PM PDT 24 30184161 ps
T939 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3797635622 Jul 17 05:05:12 PM PDT 24 Jul 17 05:05:15 PM PDT 24 75415478 ps
T940 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2680577926 Jul 17 05:04:50 PM PDT 24 Jul 17 05:04:54 PM PDT 24 98891117 ps
T120 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.714836006 Jul 17 05:05:25 PM PDT 24 Jul 17 05:05:31 PM PDT 24 117037252 ps
T941 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3658837675 Jul 17 05:05:24 PM PDT 24 Jul 17 05:05:26 PM PDT 24 32740655 ps
T126 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2173958193 Jul 17 05:05:00 PM PDT 24 Jul 17 05:05:03 PM PDT 24 128402610 ps
T942 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.602417479 Jul 17 05:05:25 PM PDT 24 Jul 17 05:05:29 PM PDT 24 39894914 ps
T943 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.610103269 Jul 17 05:05:13 PM PDT 24 Jul 17 05:05:17 PM PDT 24 419892125 ps
T944 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.911489283 Jul 17 05:05:24 PM PDT 24 Jul 17 05:05:26 PM PDT 24 93497925 ps
T945 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1729306220 Jul 17 05:05:25 PM PDT 24 Jul 17 05:05:29 PM PDT 24 68189057 ps
T946 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.177546173 Jul 17 05:05:25 PM PDT 24 Jul 17 05:05:29 PM PDT 24 97039108 ps
T947 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1894832001 Jul 17 05:05:25 PM PDT 24 Jul 17 05:05:29 PM PDT 24 85530430 ps
T948 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.4279006156 Jul 17 05:04:52 PM PDT 24 Jul 17 05:04:55 PM PDT 24 85714550 ps
T949 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2120267810 Jul 17 05:05:12 PM PDT 24 Jul 17 05:05:15 PM PDT 24 244762784 ps
T950 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4106703379 Jul 17 05:04:51 PM PDT 24 Jul 17 05:04:56 PM PDT 24 2212801694 ps
T951 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2332859229 Jul 17 05:04:50 PM PDT 24 Jul 17 05:04:53 PM PDT 24 44643850 ps
T952 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3585144595 Jul 17 05:05:26 PM PDT 24 Jul 17 05:05:30 PM PDT 24 42447006 ps
T186 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2809084274 Jul 17 05:05:02 PM PDT 24 Jul 17 05:05:05 PM PDT 24 42462515 ps
T953 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4168928507 Jul 17 05:05:13 PM PDT 24 Jul 17 05:05:27 PM PDT 24 1382264890 ps
T954 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3171426503 Jul 17 05:05:35 PM PDT 24 Jul 17 05:05:39 PM PDT 24 1046516169 ps
T187 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.176763014 Jul 17 05:05:02 PM PDT 24 Jul 17 05:05:05 PM PDT 24 26451966 ps
T955 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3113860746 Jul 17 05:05:26 PM PDT 24 Jul 17 05:05:30 PM PDT 24 45460851 ps
T956 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.13504506 Jul 17 05:05:01 PM PDT 24 Jul 17 05:05:06 PM PDT 24 87906535 ps
T127 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.179059273 Jul 17 05:04:46 PM PDT 24 Jul 17 05:04:49 PM PDT 24 59809816 ps
T957 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1864452682 Jul 17 05:05:38 PM PDT 24 Jul 17 05:05:42 PM PDT 24 34792185 ps
T958 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1341081632 Jul 17 05:05:12 PM PDT 24 Jul 17 05:05:15 PM PDT 24 46586177 ps
T959 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1530862786 Jul 17 05:05:11 PM PDT 24 Jul 17 05:05:22 PM PDT 24 2668234861 ps
T960 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1891672717 Jul 17 05:05:25 PM PDT 24 Jul 17 05:05:31 PM PDT 24 88140060 ps
T961 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1211988789 Jul 17 05:05:25 PM PDT 24 Jul 17 05:05:29 PM PDT 24 77414569 ps
T962 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.930342823 Jul 17 05:05:13 PM PDT 24 Jul 17 05:05:24 PM PDT 24 1122791825 ps
T963 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4388441 Jul 17 05:05:00 PM PDT 24 Jul 17 05:05:04 PM PDT 24 406432850 ps
T964 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3430554390 Jul 17 05:05:26 PM PDT 24 Jul 17 05:05:30 PM PDT 24 69303999 ps
T965 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.841129193 Jul 17 05:05:13 PM PDT 24 Jul 17 05:05:16 PM PDT 24 24136575 ps
T966 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.181302980 Jul 17 05:05:14 PM PDT 24 Jul 17 05:05:16 PM PDT 24 45722814 ps
T967 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2590849479 Jul 17 05:05:02 PM PDT 24 Jul 17 05:05:14 PM PDT 24 4279106023 ps
T968 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4266737569 Jul 17 05:04:48 PM PDT 24 Jul 17 05:04:51 PM PDT 24 15882120 ps
T969 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3516105921 Jul 17 05:04:39 PM PDT 24 Jul 17 05:04:43 PM PDT 24 75366599 ps
T970 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3475487407 Jul 17 05:04:51 PM PDT 24 Jul 17 05:04:57 PM PDT 24 876997888 ps
T971 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3070671594 Jul 17 05:04:48 PM PDT 24 Jul 17 05:04:53 PM PDT 24 86149869 ps
T972 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2133999555 Jul 17 05:05:24 PM PDT 24 Jul 17 05:05:27 PM PDT 24 77851695 ps
T973 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.418506590 Jul 17 05:05:01 PM PDT 24 Jul 17 05:05:05 PM PDT 24 317833934 ps
T974 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1987005948 Jul 17 05:04:48 PM PDT 24 Jul 17 05:05:01 PM PDT 24 3748674552 ps
T975 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3693264318 Jul 17 05:04:49 PM PDT 24 Jul 17 05:04:53 PM PDT 24 44488071 ps
T976 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2592344040 Jul 17 05:05:10 PM PDT 24 Jul 17 05:06:06 PM PDT 24 5079864965 ps
T977 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1674318267 Jul 17 05:04:58 PM PDT 24 Jul 17 05:05:00 PM PDT 24 28896541 ps
T978 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3148735506 Jul 17 05:05:27 PM PDT 24 Jul 17 05:05:30 PM PDT 24 15933077 ps
T188 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2537294672 Jul 17 05:05:00 PM PDT 24 Jul 17 05:05:03 PM PDT 24 87098476 ps
T109 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2671759296 Jul 17 05:05:02 PM PDT 24 Jul 17 05:05:07 PM PDT 24 327477678 ps
T979 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3474939591 Jul 17 05:04:49 PM PDT 24 Jul 17 05:04:52 PM PDT 24 54576033 ps
T980 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.665720439 Jul 17 05:04:49 PM PDT 24 Jul 17 05:04:53 PM PDT 24 108439409 ps
T981 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2010292663 Jul 17 05:05:13 PM PDT 24 Jul 17 05:05:17 PM PDT 24 92936013 ps
T982 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1382777067 Jul 17 05:05:41 PM PDT 24 Jul 17 05:05:46 PM PDT 24 155123576 ps
T983 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.923260151 Jul 17 05:04:51 PM PDT 24 Jul 17 05:04:55 PM PDT 24 772948741 ps
T984 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.4166107792 Jul 17 05:05:15 PM PDT 24 Jul 17 05:05:20 PM PDT 24 328613810 ps
T189 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.4057974368 Jul 17 05:05:39 PM PDT 24 Jul 17 05:05:43 PM PDT 24 31867377 ps
T985 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3952948430 Jul 17 05:04:52 PM PDT 24 Jul 17 05:04:55 PM PDT 24 37462202 ps
T986 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2637318996 Jul 17 05:05:37 PM PDT 24 Jul 17 05:05:41 PM PDT 24 54850297 ps
T987 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.66679570 Jul 17 05:05:12 PM PDT 24 Jul 17 05:05:14 PM PDT 24 15030014 ps
T988 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.180452424 Jul 17 05:05:01 PM PDT 24 Jul 17 05:05:05 PM PDT 24 187598687 ps
T989 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.229037196 Jul 17 05:04:52 PM PDT 24 Jul 17 05:05:03 PM PDT 24 1640927779 ps
T114 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2375719026 Jul 17 05:04:37 PM PDT 24 Jul 17 05:04:43 PM PDT 24 465075502 ps
T190 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2734711417 Jul 17 05:04:48 PM PDT 24 Jul 17 05:04:51 PM PDT 24 44767850 ps
T117 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1709094456 Jul 17 05:05:11 PM PDT 24 Jul 17 05:05:15 PM PDT 24 236499522 ps
T990 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1857084935 Jul 17 05:05:00 PM PDT 24 Jul 17 05:05:03 PM PDT 24 56360799 ps
T991 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1466734334 Jul 17 05:05:24 PM PDT 24 Jul 17 05:05:27 PM PDT 24 376099675 ps
T992 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3791881374 Jul 17 05:05:00 PM PDT 24 Jul 17 05:05:04 PM PDT 24 18721150 ps
T993 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.643149729 Jul 17 05:05:12 PM PDT 24 Jul 17 05:05:18 PM PDT 24 114758591 ps
T994 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.75842977 Jul 17 05:05:42 PM PDT 24 Jul 17 05:05:48 PM PDT 24 196592273 ps
T128 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1100159352 Jul 17 05:05:24 PM PDT 24 Jul 17 05:05:29 PM PDT 24 61490395 ps
T995 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1555002648 Jul 17 05:05:11 PM PDT 24 Jul 17 05:05:13 PM PDT 24 33386259 ps
T996 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.481820973 Jul 17 05:05:25 PM PDT 24 Jul 17 05:05:32 PM PDT 24 100864925 ps
T119 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.598002793 Jul 17 05:05:25 PM PDT 24 Jul 17 05:05:31 PM PDT 24 77980951 ps
T123 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1889355772 Jul 17 05:05:26 PM PDT 24 Jul 17 05:05:31 PM PDT 24 239902562 ps
T191 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2730851777 Jul 17 05:04:48 PM PDT 24 Jul 17 05:04:52 PM PDT 24 50053508 ps
T997 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3939058355 Jul 17 05:05:00 PM PDT 24 Jul 17 05:05:05 PM PDT 24 134607941 ps
T998 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3191636282 Jul 17 05:05:26 PM PDT 24 Jul 17 05:05:33 PM PDT 24 383602916 ps
T192 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.316254184 Jul 17 05:04:48 PM PDT 24 Jul 17 05:04:51 PM PDT 24 48317638 ps
T999 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3901796265 Jul 17 05:04:59 PM PDT 24 Jul 17 05:05:03 PM PDT 24 113123914 ps

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.1904527524
Short name T2
Test name
Test status
Simulation time 14811542546 ps
CPU time 255.74 seconds
Started Jul 17 05:14:14 PM PDT 24
Finished Jul 17 05:18:30 PM PDT 24
Peak memory 267088 kb
Host smart-1b4b1059-06c4-479c-ba76-767a740ef962
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1904527524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.1904527524
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3066283845
Short name T40
Test name
Test status
Simulation time 832886253 ps
CPU time 8.07 seconds
Started Jul 17 05:13:49 PM PDT 24
Finished Jul 17 05:13:58 PM PDT 24
Peak memory 224400 kb
Host smart-ac581070-6134-4c0f-bc22-8c55ffdde028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066283845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3066283845
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.46306455
Short name T33
Test name
Test status
Simulation time 684613175 ps
CPU time 7.88 seconds
Started Jul 17 05:17:56 PM PDT 24
Finished Jul 17 05:18:10 PM PDT 24
Peak memory 217824 kb
Host smart-b10d6b73-f98e-49a8-b32c-ad023247da9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46306455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.46306455
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.1778514514
Short name T20
Test name
Test status
Simulation time 90605866526 ps
CPU time 532.57 seconds
Started Jul 17 05:14:29 PM PDT 24
Finished Jul 17 05:23:22 PM PDT 24
Peak memory 496524 kb
Host smart-21fe3070-750b-4eaf-b30c-a09c7940e55f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1778514514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.1778514514
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.212435838
Short name T102
Test name
Test status
Simulation time 117618867 ps
CPU time 2.11 seconds
Started Jul 17 05:05:13 PM PDT 24
Finished Jul 17 05:05:17 PM PDT 24
Peak memory 219156 kb
Host smart-6d42e57b-c2d0-45c1-be2f-daf182fbf64b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212435
838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.212435838
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1577879625
Short name T237
Test name
Test status
Simulation time 8126484462 ps
CPU time 11.81 seconds
Started Jul 17 05:15:18 PM PDT 24
Finished Jul 17 05:15:31 PM PDT 24
Peak memory 225592 kb
Host smart-ceacb8fe-0e81-4ddf-a0f1-8957f3e12571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577879625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1577879625
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2773866038
Short name T38
Test name
Test status
Simulation time 37644739 ps
CPU time 0.78 seconds
Started Jul 17 05:17:37 PM PDT 24
Finished Jul 17 05:17:39 PM PDT 24
Peak memory 208236 kb
Host smart-ba31abaa-6f88-45b0-91ed-3f98c39d7efe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773866038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2773866038
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2248167962
Short name T57
Test name
Test status
Simulation time 440440458 ps
CPU time 38.12 seconds
Started Jul 17 05:13:42 PM PDT 24
Finished Jul 17 05:14:21 PM PDT 24
Peak memory 281772 kb
Host smart-79f303c4-c260-4c3f-85d1-7878fae8ff1d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248167962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2248167962
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.4081734022
Short name T15
Test name
Test status
Simulation time 1013977391 ps
CPU time 8.81 seconds
Started Jul 17 05:17:29 PM PDT 24
Finished Jul 17 05:17:38 PM PDT 24
Peak memory 217716 kb
Host smart-ee3b92e1-e9ae-4210-b5f3-5fd32a73cd50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081734022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
4081734022
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.905969038
Short name T98
Test name
Test status
Simulation time 127240957 ps
CPU time 4.07 seconds
Started Jul 17 05:05:41 PM PDT 24
Finished Jul 17 05:05:49 PM PDT 24
Peak memory 217556 kb
Host smart-42f70f8c-de8d-47cc-85af-0719327098fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905969038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_
err.905969038
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.4209644129
Short name T501
Test name
Test status
Simulation time 41053371901 ps
CPU time 679.47 seconds
Started Jul 17 05:13:25 PM PDT 24
Finished Jul 17 05:24:46 PM PDT 24
Peak memory 276232 kb
Host smart-5325defb-5998-4f63-953b-9d8faaf58499
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4209644129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.4209644129
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3567111279
Short name T149
Test name
Test status
Simulation time 954592446 ps
CPU time 11.82 seconds
Started Jul 17 05:17:59 PM PDT 24
Finished Jul 17 05:18:16 PM PDT 24
Peak memory 217652 kb
Host smart-00cf6e5f-a689-43ac-bc4b-4d368ba13653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567111279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3567111279
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3030591255
Short name T6
Test name
Test status
Simulation time 286312511 ps
CPU time 7.38 seconds
Started Jul 17 05:18:02 PM PDT 24
Finished Jul 17 05:18:13 PM PDT 24
Peak memory 216608 kb
Host smart-43937ed1-cfca-4659-9178-11fca567f088
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030591255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3030591255
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3397887441
Short name T178
Test name
Test status
Simulation time 12430831 ps
CPU time 0.91 seconds
Started Jul 17 05:05:00 PM PDT 24
Finished Jul 17 05:05:02 PM PDT 24
Peak memory 209224 kb
Host smart-343f5c10-c458-4590-9495-e80336bfc70c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397887441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3397887441
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2443254895
Short name T10
Test name
Test status
Simulation time 121287335 ps
CPU time 1.1 seconds
Started Jul 17 05:17:36 PM PDT 24
Finished Jul 17 05:17:39 PM PDT 24
Peak memory 208476 kb
Host smart-1588dfdb-537a-4701-a4ef-ac19e321e9ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443254895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2443254895
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.295087722
Short name T47
Test name
Test status
Simulation time 122832774917 ps
CPU time 741.89 seconds
Started Jul 17 05:17:54 PM PDT 24
Finished Jul 17 05:30:22 PM PDT 24
Peak memory 283464 kb
Host smart-99145193-3cb1-43aa-94df-4a61a2285c1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=295087722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.295087722
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3859212634
Short name T900
Test name
Test status
Simulation time 106272663 ps
CPU time 2.98 seconds
Started Jul 17 05:04:36 PM PDT 24
Finished Jul 17 05:04:40 PM PDT 24
Peak memory 217564 kb
Host smart-1121782a-bb73-4ff5-ac9f-abbe7ca94c23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859212634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3859212634
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1055754994
Short name T67
Test name
Test status
Simulation time 779818991 ps
CPU time 12.11 seconds
Started Jul 17 05:13:13 PM PDT 24
Finished Jul 17 05:13:26 PM PDT 24
Peak memory 225464 kb
Host smart-58b88c03-e89e-4623-b3e8-d0c627083045
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055754994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1055754994
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2671759296
Short name T109
Test name
Test status
Simulation time 327477678 ps
CPU time 2.74 seconds
Started Jul 17 05:05:02 PM PDT 24
Finished Jul 17 05:05:07 PM PDT 24
Peak memory 222400 kb
Host smart-e336261d-d104-458d-a7dc-a9538ecf54e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671759296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2671759296
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.714836006
Short name T120
Test name
Test status
Simulation time 117037252 ps
CPU time 2.92 seconds
Started Jul 17 05:05:25 PM PDT 24
Finished Jul 17 05:05:31 PM PDT 24
Peak memory 222108 kb
Host smart-692f9005-1624-429d-b8e1-3e7175452a28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714836006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.714836006
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.1376789262
Short name T19
Test name
Test status
Simulation time 23364803430 ps
CPU time 441.8 seconds
Started Jul 17 05:17:59 PM PDT 24
Finished Jul 17 05:25:26 PM PDT 24
Peak memory 283480 kb
Host smart-3c61c7c6-3921-4dee-93cb-b66e7a3a90b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1376789262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.1376789262
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2253581539
Short name T888
Test name
Test status
Simulation time 694554345 ps
CPU time 2.18 seconds
Started Jul 17 05:04:37 PM PDT 24
Finished Jul 17 05:04:41 PM PDT 24
Peak memory 210624 kb
Host smart-5baf6e12-d850-420b-87ce-785064ff9b9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253581539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2253581539
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3265856975
Short name T17
Test name
Test status
Simulation time 200637895 ps
CPU time 3.84 seconds
Started Jul 17 05:13:54 PM PDT 24
Finished Jul 17 05:13:59 PM PDT 24
Peak memory 217112 kb
Host smart-518d82e4-9216-4cc6-bca8-1bf8a5a3b89d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265856975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3265856975
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2375719026
Short name T114
Test name
Test status
Simulation time 465075502 ps
CPU time 4.12 seconds
Started Jul 17 05:04:37 PM PDT 24
Finished Jul 17 05:04:43 PM PDT 24
Peak memory 217484 kb
Host smart-d7dd9379-8f0d-4f55-82b0-b9f816491cd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375719026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.2375719026
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1812789447
Short name T99
Test name
Test status
Simulation time 129389301 ps
CPU time 2.55 seconds
Started Jul 17 05:05:25 PM PDT 24
Finished Jul 17 05:05:30 PM PDT 24
Peak memory 217476 kb
Host smart-20bf7732-5ca5-4261-a195-4b9cfc6aa493
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812789447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1812789447
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4072988719
Short name T108
Test name
Test status
Simulation time 133305532 ps
CPU time 2.19 seconds
Started Jul 17 05:05:25 PM PDT 24
Finished Jul 17 05:05:30 PM PDT 24
Peak memory 217400 kb
Host smart-a701bc4c-7005-40a0-b9cb-7e9e16e04b98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072988719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.4072988719
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2991652821
Short name T122
Test name
Test status
Simulation time 103736444 ps
CPU time 3.05 seconds
Started Jul 17 05:04:47 PM PDT 24
Finished Jul 17 05:04:52 PM PDT 24
Peak memory 217656 kb
Host smart-d4949492-7d05-4351-9886-5466847f78f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991652821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2991652821
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3599855382
Short name T199
Test name
Test status
Simulation time 12628933 ps
CPU time 0.84 seconds
Started Jul 17 05:13:07 PM PDT 24
Finished Jul 17 05:13:09 PM PDT 24
Peak memory 208188 kb
Host smart-8cc6e581-878b-4839-b993-2f9038824796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599855382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3599855382
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3767641456
Short name T91
Test name
Test status
Simulation time 13236263 ps
CPU time 0.91 seconds
Started Jul 17 05:16:01 PM PDT 24
Finished Jul 17 05:16:11 PM PDT 24
Peak memory 208048 kb
Host smart-85534a9f-1eb5-4038-b218-bf9c1a22d8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767641456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3767641456
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2329647999
Short name T202
Test name
Test status
Simulation time 12766461 ps
CPU time 1 seconds
Started Jul 17 05:13:54 PM PDT 24
Finished Jul 17 05:13:56 PM PDT 24
Peak memory 208288 kb
Host smart-18a9028d-ab19-4476-b9bd-1488434240ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329647999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2329647999
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3772736751
Short name T201
Test name
Test status
Simulation time 14321657 ps
CPU time 0.82 seconds
Started Jul 17 05:15:47 PM PDT 24
Finished Jul 17 05:15:52 PM PDT 24
Peak memory 208164 kb
Host smart-4ca22073-7207-4806-a25b-47a24f589547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772736751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3772736751
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.598002793
Short name T119
Test name
Test status
Simulation time 77980951 ps
CPU time 2.98 seconds
Started Jul 17 05:05:25 PM PDT 24
Finished Jul 17 05:05:31 PM PDT 24
Peak memory 222516 kb
Host smart-5697f987-1cbc-45b5-9978-51b5abec16e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598002793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.598002793
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.226035935
Short name T97
Test name
Test status
Simulation time 369423014 ps
CPU time 3.64 seconds
Started Jul 17 05:05:26 PM PDT 24
Finished Jul 17 05:05:32 PM PDT 24
Peak memory 217508 kb
Host smart-fb40e7df-ccf8-4ea8-a042-b9e0b93d44bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226035935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.226035935
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1889355772
Short name T123
Test name
Test status
Simulation time 239902562 ps
CPU time 1.96 seconds
Started Jul 17 05:05:26 PM PDT 24
Finished Jul 17 05:05:31 PM PDT 24
Peak memory 222112 kb
Host smart-f5099999-819a-4c9e-b67e-901691b06a84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889355772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1889355772
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2435227097
Short name T113
Test name
Test status
Simulation time 125082877 ps
CPU time 3.24 seconds
Started Jul 17 05:05:00 PM PDT 24
Finished Jul 17 05:05:05 PM PDT 24
Peak memory 221940 kb
Host smart-e7175d42-57b2-467c-9fe7-b41652374a23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435227097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2435227097
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1146591031
Short name T124
Test name
Test status
Simulation time 109992221 ps
CPU time 2.79 seconds
Started Jul 17 05:05:26 PM PDT 24
Finished Jul 17 05:05:31 PM PDT 24
Peak memory 217560 kb
Host smart-d93e53e5-77eb-4fed-a72a-c108a2a7bfc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146591031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1146591031
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2349358645
Short name T51
Test name
Test status
Simulation time 82232689830 ps
CPU time 948.01 seconds
Started Jul 17 05:17:47 PM PDT 24
Finished Jul 17 05:33:37 PM PDT 24
Peak memory 308060 kb
Host smart-b12c3407-11eb-4619-9140-6dfc80132f1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2349358645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.2349358645
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.4021578600
Short name T3
Test name
Test status
Simulation time 30340135 ps
CPU time 2.02 seconds
Started Jul 17 05:14:48 PM PDT 24
Finished Jul 17 05:14:51 PM PDT 24
Peak memory 217180 kb
Host smart-2ceb3f4d-ea9a-4e6e-be78-d02625168283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021578600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.4021578600
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2944621770
Short name T182
Test name
Test status
Simulation time 272693212 ps
CPU time 1.75 seconds
Started Jul 17 05:04:36 PM PDT 24
Finished Jul 17 05:04:40 PM PDT 24
Peak memory 209360 kb
Host smart-45ec84ad-181f-4419-be4c-46b08f272046
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944621770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2944621770
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.710317896
Short name T877
Test name
Test status
Simulation time 66084743 ps
CPU time 2.06 seconds
Started Jul 17 05:04:48 PM PDT 24
Finished Jul 17 05:04:52 PM PDT 24
Peak memory 209204 kb
Host smart-70a4e972-96e0-4775-92aa-471884497d7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710317896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash
.710317896
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2734711417
Short name T190
Test name
Test status
Simulation time 44767850 ps
CPU time 0.86 seconds
Started Jul 17 05:04:48 PM PDT 24
Finished Jul 17 05:04:51 PM PDT 24
Peak memory 209572 kb
Host smart-991a2ed5-af0c-4ab1-aed4-1c14b27ff135
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734711417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2734711417
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4009205750
Short name T892
Test name
Test status
Simulation time 43579482 ps
CPU time 1.39 seconds
Started Jul 17 05:04:37 PM PDT 24
Finished Jul 17 05:04:41 PM PDT 24
Peak memory 219072 kb
Host smart-7becf995-9344-457b-bd94-465fde355d66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009205750 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.4009205750
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3802958309
Short name T875
Test name
Test status
Simulation time 40086666 ps
CPU time 0.9 seconds
Started Jul 17 05:04:48 PM PDT 24
Finished Jul 17 05:04:51 PM PDT 24
Peak memory 209140 kb
Host smart-96fc0256-212e-42a2-be45-6237050d0a66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802958309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3802958309
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1358854970
Short name T902
Test name
Test status
Simulation time 88561270 ps
CPU time 1.39 seconds
Started Jul 17 05:04:37 PM PDT 24
Finished Jul 17 05:04:41 PM PDT 24
Peak memory 209124 kb
Host smart-dd17f990-e323-4a50-8f50-6144c611fee0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358854970 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1358854970
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.190138896
Short name T911
Test name
Test status
Simulation time 440389205 ps
CPU time 11.25 seconds
Started Jul 17 05:04:38 PM PDT 24
Finished Jul 17 05:04:51 PM PDT 24
Peak memory 209184 kb
Host smart-fe5796ea-c550-433c-bbdc-1408a65921c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190138896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.190138896
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.732457126
Short name T916
Test name
Test status
Simulation time 1690382403 ps
CPU time 10.58 seconds
Started Jul 17 05:04:38 PM PDT 24
Finished Jul 17 05:04:51 PM PDT 24
Peak memory 209212 kb
Host smart-8201b6ed-c577-440e-9409-3b6d075ec645
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732457126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.732457126
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1189862673
Short name T934
Test name
Test status
Simulation time 183393368 ps
CPU time 3.09 seconds
Started Jul 17 05:04:48 PM PDT 24
Finished Jul 17 05:04:53 PM PDT 24
Peak memory 217552 kb
Host smart-e8899137-9b54-42cc-b0f6-fbf18f468a1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118986
2673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1189862673
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.685307316
Short name T894
Test name
Test status
Simulation time 236719807 ps
CPU time 2.09 seconds
Started Jul 17 05:04:37 PM PDT 24
Finished Jul 17 05:04:42 PM PDT 24
Peak memory 209252 kb
Host smart-abb03348-5f93-4bb1-b730-989d8cdafbf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685307316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.685307316
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.175083367
Short name T887
Test name
Test status
Simulation time 69194286 ps
CPU time 1.15 seconds
Started Jul 17 05:04:38 PM PDT 24
Finished Jul 17 05:04:42 PM PDT 24
Peak memory 209228 kb
Host smart-4080ff7f-37eb-4c38-94a4-5d2b9bd102c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175083367 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.175083367
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3615981487
Short name T107
Test name
Test status
Simulation time 64729499 ps
CPU time 1.38 seconds
Started Jul 17 05:04:38 PM PDT 24
Finished Jul 17 05:04:42 PM PDT 24
Peak memory 209312 kb
Host smart-42220acd-da81-4628-8345-cec637b1ffb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615981487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3615981487
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3977890018
Short name T180
Test name
Test status
Simulation time 22784395 ps
CPU time 1.26 seconds
Started Jul 17 05:04:49 PM PDT 24
Finished Jul 17 05:04:52 PM PDT 24
Peak memory 208636 kb
Host smart-3b44ea0a-6bf6-41da-8928-fd4ddabc5c80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977890018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3977890018
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1204258660
Short name T907
Test name
Test status
Simulation time 65427098 ps
CPU time 1.81 seconds
Started Jul 17 05:04:49 PM PDT 24
Finished Jul 17 05:04:53 PM PDT 24
Peak memory 209272 kb
Host smart-3620dfd1-e981-47b1-83a8-7c3f937ab0d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204258660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1204258660
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3693264318
Short name T975
Test name
Test status
Simulation time 44488071 ps
CPU time 1.08 seconds
Started Jul 17 05:04:49 PM PDT 24
Finished Jul 17 05:04:53 PM PDT 24
Peak memory 209900 kb
Host smart-372a45e2-8839-4e07-9bad-0c56b88048e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693264318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3693264318
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2680577926
Short name T940
Test name
Test status
Simulation time 98891117 ps
CPU time 1.83 seconds
Started Jul 17 05:04:50 PM PDT 24
Finished Jul 17 05:04:54 PM PDT 24
Peak memory 217568 kb
Host smart-b627ca8e-8f15-4f87-9f52-4c78c137c454
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680577926 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2680577926
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.4279006156
Short name T948
Test name
Test status
Simulation time 85714550 ps
CPU time 0.89 seconds
Started Jul 17 05:04:52 PM PDT 24
Finished Jul 17 05:04:55 PM PDT 24
Peak memory 209228 kb
Host smart-1ff5d0d8-1c35-4b62-85c5-fa785b8b47ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279006156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.4279006156
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.785753213
Short name T876
Test name
Test status
Simulation time 122999216 ps
CPU time 2.25 seconds
Started Jul 17 05:04:50 PM PDT 24
Finished Jul 17 05:04:55 PM PDT 24
Peak memory 209144 kb
Host smart-e900b306-8067-4213-afe9-d27958e5a7e7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785753213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.785753213
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1760244327
Short name T880
Test name
Test status
Simulation time 1387478992 ps
CPU time 28.84 seconds
Started Jul 17 05:04:35 PM PDT 24
Finished Jul 17 05:05:05 PM PDT 24
Peak memory 208524 kb
Host smart-1d6627d2-82b5-4177-b989-3f9a7ae1bacb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760244327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1760244327
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2552184220
Short name T111
Test name
Test status
Simulation time 769356864 ps
CPU time 8 seconds
Started Jul 17 05:04:37 PM PDT 24
Finished Jul 17 05:04:47 PM PDT 24
Peak memory 209200 kb
Host smart-a406174c-215f-443d-95a9-fd5ffdcb88a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552184220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2552184220
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3245633776
Short name T893
Test name
Test status
Simulation time 235677722 ps
CPU time 3.14 seconds
Started Jul 17 05:04:47 PM PDT 24
Finished Jul 17 05:04:51 PM PDT 24
Peak memory 210752 kb
Host smart-8055ff5e-3f00-4f7a-9645-0f123855f7ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245633776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3245633776
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3088899740
Short name T898
Test name
Test status
Simulation time 1046540437 ps
CPU time 3.05 seconds
Started Jul 17 05:04:48 PM PDT 24
Finished Jul 17 05:04:53 PM PDT 24
Peak memory 217580 kb
Host smart-a3e110ca-a9b5-4ae4-89e3-7fceb3948270
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308889
9740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3088899740
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3516105921
Short name T969
Test name
Test status
Simulation time 75366599 ps
CPU time 1.45 seconds
Started Jul 17 05:04:39 PM PDT 24
Finished Jul 17 05:04:43 PM PDT 24
Peak memory 209100 kb
Host smart-491fa7e6-815d-4c8d-a8b4-ec91a4dcef2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516105921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3516105921
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3474939591
Short name T979
Test name
Test status
Simulation time 54576033 ps
CPU time 1.41 seconds
Started Jul 17 05:04:49 PM PDT 24
Finished Jul 17 05:04:52 PM PDT 24
Peak memory 209204 kb
Host smart-b8d53e2a-bf68-406d-a4fc-d98a599b4ffb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474939591 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3474939591
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3042580295
Short name T937
Test name
Test status
Simulation time 21671626 ps
CPU time 1.34 seconds
Started Jul 17 05:04:49 PM PDT 24
Finished Jul 17 05:04:52 PM PDT 24
Peak memory 217448 kb
Host smart-3693903f-55e7-4ac9-b2df-9c078559a4dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042580295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3042580295
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3070671594
Short name T971
Test name
Test status
Simulation time 86149869 ps
CPU time 3.22 seconds
Started Jul 17 05:04:48 PM PDT 24
Finished Jul 17 05:04:53 PM PDT 24
Peak memory 217360 kb
Host smart-efe3c9e5-a9b1-4242-ad95-4710614fe802
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070671594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3070671594
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.179059273
Short name T127
Test name
Test status
Simulation time 59809816 ps
CPU time 2.21 seconds
Started Jul 17 05:04:46 PM PDT 24
Finished Jul 17 05:04:49 PM PDT 24
Peak memory 222064 kb
Host smart-6795f727-db79-4c5c-b09a-ed70d3a81be8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179059273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e
rr.179059273
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3239795423
Short name T932
Test name
Test status
Simulation time 61092927 ps
CPU time 1.2 seconds
Started Jul 17 05:05:25 PM PDT 24
Finished Jul 17 05:05:29 PM PDT 24
Peak memory 217488 kb
Host smart-9c6100f2-8bb0-41ff-9a10-02ed21820447
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239795423 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3239795423
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.636849680
Short name T193
Test name
Test status
Simulation time 132641155 ps
CPU time 0.95 seconds
Started Jul 17 05:05:27 PM PDT 24
Finished Jul 17 05:05:30 PM PDT 24
Peak memory 209236 kb
Host smart-da1b2708-467e-4430-9dcd-51a85477119c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636849680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.636849680
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3276706259
Short name T886
Test name
Test status
Simulation time 161669585 ps
CPU time 1.39 seconds
Started Jul 17 05:05:26 PM PDT 24
Finished Jul 17 05:05:30 PM PDT 24
Peak memory 209256 kb
Host smart-ec349f60-4729-48dc-8ef6-0bf285c8fea3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276706259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3276706259
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1891672717
Short name T960
Test name
Test status
Simulation time 88140060 ps
CPU time 2.98 seconds
Started Jul 17 05:05:25 PM PDT 24
Finished Jul 17 05:05:31 PM PDT 24
Peak memory 217496 kb
Host smart-6a6bc67e-81c7-467b-b417-d71b6a58a345
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891672717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1891672717
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2916115605
Short name T923
Test name
Test status
Simulation time 116238895 ps
CPU time 1.29 seconds
Started Jul 17 05:05:26 PM PDT 24
Finished Jul 17 05:05:30 PM PDT 24
Peak memory 217512 kb
Host smart-67286e76-73f8-4ebd-b3e3-4afb20b7fee6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916115605 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2916115605
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3148735506
Short name T978
Test name
Test status
Simulation time 15933077 ps
CPU time 1.06 seconds
Started Jul 17 05:05:27 PM PDT 24
Finished Jul 17 05:05:30 PM PDT 24
Peak memory 209168 kb
Host smart-b1e907ea-566e-4fe5-86ec-9600c381baba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148735506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3148735506
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.449590353
Short name T925
Test name
Test status
Simulation time 111809117 ps
CPU time 1.46 seconds
Started Jul 17 05:05:25 PM PDT 24
Finished Jul 17 05:05:29 PM PDT 24
Peak memory 209280 kb
Host smart-71eaa3a3-d6f9-4086-b5a8-e9187818ccab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449590353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.449590353
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1718049835
Short name T118
Test name
Test status
Simulation time 263053694 ps
CPU time 2.91 seconds
Started Jul 17 05:05:23 PM PDT 24
Finished Jul 17 05:05:26 PM PDT 24
Peak memory 217676 kb
Host smart-8a1e439b-ff1d-43a8-8cd7-08a3f57423e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718049835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1718049835
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1832409154
Short name T904
Test name
Test status
Simulation time 36570499 ps
CPU time 1.84 seconds
Started Jul 17 05:06:06 PM PDT 24
Finished Jul 17 05:06:08 PM PDT 24
Peak memory 218484 kb
Host smart-96f60117-fd4b-4753-81e2-9d64732a1856
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832409154 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1832409154
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3003374302
Short name T185
Test name
Test status
Simulation time 110047942 ps
CPU time 1.06 seconds
Started Jul 17 05:05:23 PM PDT 24
Finished Jul 17 05:05:25 PM PDT 24
Peak memory 209248 kb
Host smart-1e3382b8-a3d1-4583-8725-e39e9cd59925
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003374302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3003374302
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3430554390
Short name T964
Test name
Test status
Simulation time 69303999 ps
CPU time 1.36 seconds
Started Jul 17 05:05:26 PM PDT 24
Finished Jul 17 05:05:30 PM PDT 24
Peak memory 209248 kb
Host smart-15dd7912-9f77-46e4-a705-e405cf78bf64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430554390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3430554390
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.177546173
Short name T946
Test name
Test status
Simulation time 97039108 ps
CPU time 1.8 seconds
Started Jul 17 05:05:25 PM PDT 24
Finished Jul 17 05:05:29 PM PDT 24
Peak memory 217788 kb
Host smart-afcd60a8-f0ff-40c2-972a-be68c8dc6c35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177546173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.177546173
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.348678544
Short name T138
Test name
Test status
Simulation time 17717638 ps
CPU time 1.27 seconds
Started Jul 17 05:05:25 PM PDT 24
Finished Jul 17 05:05:29 PM PDT 24
Peak memory 217512 kb
Host smart-d311be0d-722c-40c1-84af-14753370f1eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348678544 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.348678544
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1463912455
Short name T933
Test name
Test status
Simulation time 36569648 ps
CPU time 0.89 seconds
Started Jul 17 05:05:26 PM PDT 24
Finished Jul 17 05:05:30 PM PDT 24
Peak memory 209140 kb
Host smart-eaa9a113-4f6b-4496-8f50-97bc68f05895
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463912455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1463912455
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2133999555
Short name T972
Test name
Test status
Simulation time 77851695 ps
CPU time 1.44 seconds
Started Jul 17 05:05:24 PM PDT 24
Finished Jul 17 05:05:27 PM PDT 24
Peak memory 209248 kb
Host smart-beea1e28-e42b-41c9-a8ae-1b17403df326
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133999555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2133999555
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.386291338
Short name T105
Test name
Test status
Simulation time 28269011 ps
CPU time 2.31 seconds
Started Jul 17 05:05:25 PM PDT 24
Finished Jul 17 05:05:30 PM PDT 24
Peak memory 217424 kb
Host smart-753bb651-8fc8-42d5-b1f3-7d5080815e33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386291338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.386291338
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.911489283
Short name T944
Test name
Test status
Simulation time 93497925 ps
CPU time 1.47 seconds
Started Jul 17 05:05:24 PM PDT 24
Finished Jul 17 05:05:26 PM PDT 24
Peak memory 217568 kb
Host smart-43dfee6d-72b6-4d80-aa77-60ef24bf0929
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911489283 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.911489283
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3585144595
Short name T952
Test name
Test status
Simulation time 42447006 ps
CPU time 1.02 seconds
Started Jul 17 05:05:26 PM PDT 24
Finished Jul 17 05:05:30 PM PDT 24
Peak memory 209232 kb
Host smart-349bad0f-ddd1-41fd-a355-00a10dc9e834
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585144595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3585144595
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.720981997
Short name T890
Test name
Test status
Simulation time 99703803 ps
CPU time 2.13 seconds
Started Jul 17 05:05:24 PM PDT 24
Finished Jul 17 05:05:27 PM PDT 24
Peak memory 209240 kb
Host smart-83412efa-9788-4325-88d9-afe5efddc741
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720981997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.720981997
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3828169037
Short name T115
Test name
Test status
Simulation time 89313207 ps
CPU time 1.59 seconds
Started Jul 17 05:05:23 PM PDT 24
Finished Jul 17 05:05:26 PM PDT 24
Peak memory 209324 kb
Host smart-83fad7b9-e35d-4db3-bcf2-d46280f6159f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828169037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3828169037
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1211988789
Short name T961
Test name
Test status
Simulation time 77414569 ps
CPU time 1.45 seconds
Started Jul 17 05:05:25 PM PDT 24
Finished Jul 17 05:05:29 PM PDT 24
Peak memory 219308 kb
Host smart-440ac709-6244-4ae7-ad53-8ff203a3a4e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211988789 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1211988789
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.4073588522
Short name T922
Test name
Test status
Simulation time 13758144 ps
CPU time 0.82 seconds
Started Jul 17 05:05:24 PM PDT 24
Finished Jul 17 05:05:26 PM PDT 24
Peak memory 208620 kb
Host smart-40f29a11-be52-474f-8463-bf6df081932b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073588522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.4073588522
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3508989510
Short name T195
Test name
Test status
Simulation time 25860926 ps
CPU time 1.27 seconds
Started Jul 17 05:05:23 PM PDT 24
Finished Jul 17 05:05:25 PM PDT 24
Peak memory 211392 kb
Host smart-75c251c5-48a4-41fc-b1b7-58cef8ba2a84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508989510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3508989510
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1466734334
Short name T991
Test name
Test status
Simulation time 376099675 ps
CPU time 1.84 seconds
Started Jul 17 05:05:24 PM PDT 24
Finished Jul 17 05:05:27 PM PDT 24
Peak memory 217788 kb
Host smart-2e15c92d-9fea-4724-b18b-007129858074
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466734334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1466734334
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1100159352
Short name T128
Test name
Test status
Simulation time 61490395 ps
CPU time 2.09 seconds
Started Jul 17 05:05:24 PM PDT 24
Finished Jul 17 05:05:29 PM PDT 24
Peak memory 221964 kb
Host smart-9733176e-3d59-4eaa-b2b7-c07f576e2697
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100159352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1100159352
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.115475464
Short name T103
Test name
Test status
Simulation time 130581958 ps
CPU time 1.15 seconds
Started Jul 17 05:05:39 PM PDT 24
Finished Jul 17 05:05:44 PM PDT 24
Peak memory 217500 kb
Host smart-d20fb01d-a3ba-47a5-8b32-e69903c436cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115475464 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.115475464
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.4057974368
Short name T189
Test name
Test status
Simulation time 31867377 ps
CPU time 1.11 seconds
Started Jul 17 05:05:39 PM PDT 24
Finished Jul 17 05:05:43 PM PDT 24
Peak memory 209448 kb
Host smart-1a92f623-e6d8-4313-9641-18c6c88364ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057974368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.4057974368
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1730900060
Short name T112
Test name
Test status
Simulation time 237270818 ps
CPU time 1.1 seconds
Started Jul 17 05:05:36 PM PDT 24
Finished Jul 17 05:05:38 PM PDT 24
Peak memory 209284 kb
Host smart-bf49057f-76f8-410a-b25e-13bd2222f3bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730900060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1730900060
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1894832001
Short name T947
Test name
Test status
Simulation time 85530430 ps
CPU time 1.51 seconds
Started Jul 17 05:05:25 PM PDT 24
Finished Jul 17 05:05:29 PM PDT 24
Peak memory 218484 kb
Host smart-770159be-0718-4614-94f2-034be32f9efc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894832001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1894832001
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1368424086
Short name T110
Test name
Test status
Simulation time 119684099 ps
CPU time 2.29 seconds
Started Jul 17 05:05:37 PM PDT 24
Finished Jul 17 05:05:41 PM PDT 24
Peak memory 217632 kb
Host smart-24b5ae90-01c1-4a77-918a-37d2536f81fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368424086 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1368424086
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1864452682
Short name T957
Test name
Test status
Simulation time 34792185 ps
CPU time 0.87 seconds
Started Jul 17 05:05:38 PM PDT 24
Finished Jul 17 05:05:42 PM PDT 24
Peak memory 209172 kb
Host smart-4be3baab-11f0-4ea9-aa53-0203fbf7db87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864452682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1864452682
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2637318996
Short name T986
Test name
Test status
Simulation time 54850297 ps
CPU time 2.28 seconds
Started Jul 17 05:05:37 PM PDT 24
Finished Jul 17 05:05:41 PM PDT 24
Peak memory 211364 kb
Host smart-9e66ab21-866f-47c9-914a-940476a60c8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637318996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2637318996
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.75842977
Short name T994
Test name
Test status
Simulation time 196592273 ps
CPU time 2.83 seconds
Started Jul 17 05:05:42 PM PDT 24
Finished Jul 17 05:05:48 PM PDT 24
Peak memory 217380 kb
Host smart-90db9022-9722-458b-b79c-c664555f03a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75842977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.75842977
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1307585219
Short name T883
Test name
Test status
Simulation time 55753078 ps
CPU time 1.68 seconds
Started Jul 17 05:05:38 PM PDT 24
Finished Jul 17 05:05:43 PM PDT 24
Peak memory 217512 kb
Host smart-83bac907-ed2d-4fa1-9149-212edf81c489
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307585219 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1307585219
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.4143923684
Short name T895
Test name
Test status
Simulation time 14566099 ps
CPU time 0.9 seconds
Started Jul 17 05:05:38 PM PDT 24
Finished Jul 17 05:05:42 PM PDT 24
Peak memory 209244 kb
Host smart-1757d00f-edb8-4c0b-a2f6-b7725a8b292c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143923684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.4143923684
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3887780579
Short name T196
Test name
Test status
Simulation time 25699907 ps
CPU time 1.04 seconds
Started Jul 17 05:05:42 PM PDT 24
Finished Jul 17 05:05:46 PM PDT 24
Peak memory 209212 kb
Host smart-04be2292-c863-4103-b087-8daf96926969
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887780579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3887780579
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1633415108
Short name T919
Test name
Test status
Simulation time 30503029 ps
CPU time 1.89 seconds
Started Jul 17 05:05:39 PM PDT 24
Finished Jul 17 05:05:46 PM PDT 24
Peak memory 217480 kb
Host smart-598528d8-1d1d-4b35-be9e-ec10f52f3fdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633415108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1633415108
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1524975028
Short name T928
Test name
Test status
Simulation time 91351927 ps
CPU time 2.49 seconds
Started Jul 17 05:05:36 PM PDT 24
Finished Jul 17 05:05:40 PM PDT 24
Peak memory 221888 kb
Host smart-f6362262-82f4-4a88-9dc8-c2cee65f706c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524975028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1524975028
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3090174794
Short name T914
Test name
Test status
Simulation time 55879517 ps
CPU time 1.12 seconds
Started Jul 17 05:05:39 PM PDT 24
Finished Jul 17 05:05:45 PM PDT 24
Peak memory 217468 kb
Host smart-d17bb32d-be30-4c8e-9f6d-08ea9aea6c89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090174794 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3090174794
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.4267605136
Short name T929
Test name
Test status
Simulation time 15565707 ps
CPU time 1.06 seconds
Started Jul 17 05:05:37 PM PDT 24
Finished Jul 17 05:05:40 PM PDT 24
Peak memory 209284 kb
Host smart-aeecb863-0a16-4c74-bd15-f8fdf7f119d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267605136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.4267605136
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1382777067
Short name T982
Test name
Test status
Simulation time 155123576 ps
CPU time 1.43 seconds
Started Jul 17 05:05:41 PM PDT 24
Finished Jul 17 05:05:46 PM PDT 24
Peak memory 211200 kb
Host smart-59c8e759-a097-40ef-abba-4d3ff5c182df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382777067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1382777067
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3011272760
Short name T921
Test name
Test status
Simulation time 40658735 ps
CPU time 2.82 seconds
Started Jul 17 05:05:41 PM PDT 24
Finished Jul 17 05:05:48 PM PDT 24
Peak memory 218636 kb
Host smart-c671e218-c5d0-4520-898f-8f4093371074
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011272760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3011272760
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3171426503
Short name T954
Test name
Test status
Simulation time 1046516169 ps
CPU time 2.95 seconds
Started Jul 17 05:05:35 PM PDT 24
Finished Jul 17 05:05:39 PM PDT 24
Peak memory 222220 kb
Host smart-8023a04c-4f06-4cc9-9cd1-40917bdf260d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171426503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3171426503
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2730851777
Short name T191
Test name
Test status
Simulation time 50053508 ps
CPU time 1.74 seconds
Started Jul 17 05:04:48 PM PDT 24
Finished Jul 17 05:04:52 PM PDT 24
Peak memory 208472 kb
Host smart-61e66b1f-d83d-4266-a842-cc2019765f2f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730851777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2730851777
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.24208445
Short name T896
Test name
Test status
Simulation time 75876255 ps
CPU time 2.68 seconds
Started Jul 17 05:04:51 PM PDT 24
Finished Jul 17 05:04:56 PM PDT 24
Peak memory 209160 kb
Host smart-3cbca83a-3087-43e2-b5eb-2794d5a1e012
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24208445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash.24208445
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3602846620
Short name T179
Test name
Test status
Simulation time 14438192 ps
CPU time 0.88 seconds
Started Jul 17 05:04:48 PM PDT 24
Finished Jul 17 05:04:51 PM PDT 24
Peak memory 209724 kb
Host smart-acabea5e-68a1-4e62-bc14-e777093bd632
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602846620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3602846620
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3103038193
Short name T935
Test name
Test status
Simulation time 202590659 ps
CPU time 1.53 seconds
Started Jul 17 05:04:48 PM PDT 24
Finished Jul 17 05:04:52 PM PDT 24
Peak memory 217532 kb
Host smart-e3ff3b37-8685-41fe-8bbe-92ed0e09cc08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103038193 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3103038193
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.316254184
Short name T192
Test name
Test status
Simulation time 48317638 ps
CPU time 0.88 seconds
Started Jul 17 05:04:48 PM PDT 24
Finished Jul 17 05:04:51 PM PDT 24
Peak memory 209244 kb
Host smart-5a5dbc1b-1c16-469d-bf64-c0f2a39ac485
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316254184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.316254184
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2958766811
Short name T884
Test name
Test status
Simulation time 118688970 ps
CPU time 2.4 seconds
Started Jul 17 05:04:48 PM PDT 24
Finished Jul 17 05:04:53 PM PDT 24
Peak memory 209060 kb
Host smart-6f24c537-3fbf-4fab-98cc-c30fcd86d37c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958766811 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2958766811
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4106703379
Short name T950
Test name
Test status
Simulation time 2212801694 ps
CPU time 2.9 seconds
Started Jul 17 05:04:51 PM PDT 24
Finished Jul 17 05:04:56 PM PDT 24
Peak memory 207632 kb
Host smart-c2c8f1c7-c804-4e8c-a7c3-41659ca2fd7c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106703379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.4106703379
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1987005948
Short name T974
Test name
Test status
Simulation time 3748674552 ps
CPU time 11.7 seconds
Started Jul 17 05:04:48 PM PDT 24
Finished Jul 17 05:05:01 PM PDT 24
Peak memory 209296 kb
Host smart-4ff5a2ff-c05f-41b2-b202-c814562dee16
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987005948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1987005948
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.923260151
Short name T983
Test name
Test status
Simulation time 772948741 ps
CPU time 1.94 seconds
Started Jul 17 05:04:51 PM PDT 24
Finished Jul 17 05:04:55 PM PDT 24
Peak memory 210760 kb
Host smart-217b3345-b886-4ea9-840c-84a1430d116e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923260151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.923260151
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3475487407
Short name T970
Test name
Test status
Simulation time 876997888 ps
CPU time 3.94 seconds
Started Jul 17 05:04:51 PM PDT 24
Finished Jul 17 05:04:57 PM PDT 24
Peak memory 218500 kb
Host smart-cbf5b2f0-bad6-400a-8fa6-3f3a5b36caa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347548
7407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3475487407
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3952948430
Short name T985
Test name
Test status
Simulation time 37462202 ps
CPU time 1.19 seconds
Started Jul 17 05:04:52 PM PDT 24
Finished Jul 17 05:04:55 PM PDT 24
Peak memory 209168 kb
Host smart-9c3a774b-8ab5-4593-b37c-4d45f1d23b53
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952948430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3952948430
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2332859229
Short name T951
Test name
Test status
Simulation time 44643850 ps
CPU time 1.13 seconds
Started Jul 17 05:04:50 PM PDT 24
Finished Jul 17 05:04:53 PM PDT 24
Peak memory 209240 kb
Host smart-dfd19810-ac51-44e2-929d-7fabef0d9d98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332859229 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2332859229
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4266737569
Short name T968
Test name
Test status
Simulation time 15882120 ps
CPU time 1.25 seconds
Started Jul 17 05:04:48 PM PDT 24
Finished Jul 17 05:04:51 PM PDT 24
Peak memory 209364 kb
Host smart-e22e698c-e406-45c0-b595-3e19c5cda623
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266737569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.4266737569
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2380167218
Short name T927
Test name
Test status
Simulation time 132790750 ps
CPU time 3.54 seconds
Started Jul 17 05:04:46 PM PDT 24
Finished Jul 17 05:04:51 PM PDT 24
Peak memory 217456 kb
Host smart-057574b3-addd-49b3-93f6-fdbd44d787f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380167218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2380167218
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.248158179
Short name T181
Test name
Test status
Simulation time 26954263 ps
CPU time 1.46 seconds
Started Jul 17 05:05:00 PM PDT 24
Finished Jul 17 05:05:04 PM PDT 24
Peak memory 209276 kb
Host smart-992024cb-c340-4645-ac54-06f968100bfb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248158179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.248158179
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2468185794
Short name T879
Test name
Test status
Simulation time 40247169 ps
CPU time 1.8 seconds
Started Jul 17 05:05:02 PM PDT 24
Finished Jul 17 05:05:06 PM PDT 24
Peak memory 209088 kb
Host smart-9aed6e45-f552-44a0-8d39-b8be1a8d7ea1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468185794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2468185794
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2537294672
Short name T188
Test name
Test status
Simulation time 87098476 ps
CPU time 1.11 seconds
Started Jul 17 05:05:00 PM PDT 24
Finished Jul 17 05:05:03 PM PDT 24
Peak memory 210444 kb
Host smart-aaaaf811-82b0-4b5f-8e1f-303427a41ce9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537294672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2537294672
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.768940086
Short name T906
Test name
Test status
Simulation time 17146345 ps
CPU time 1.39 seconds
Started Jul 17 05:05:00 PM PDT 24
Finished Jul 17 05:05:03 PM PDT 24
Peak memory 219088 kb
Host smart-42c8ff6a-0c0a-4d01-b8d6-f9ce830962b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768940086 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.768940086
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.82911332
Short name T882
Test name
Test status
Simulation time 74628396 ps
CPU time 2.44 seconds
Started Jul 17 05:04:53 PM PDT 24
Finished Jul 17 05:04:57 PM PDT 24
Peak memory 209048 kb
Host smart-98d4ed40-9dc5-4e4c-8340-db8402e14cac
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82911332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_alert_test.82911332
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1801980123
Short name T903
Test name
Test status
Simulation time 1016177862 ps
CPU time 6.36 seconds
Started Jul 17 05:04:51 PM PDT 24
Finished Jul 17 05:05:00 PM PDT 24
Peak memory 208944 kb
Host smart-5cf8d619-77db-4f9b-808d-86cc15c2f017
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801980123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1801980123
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.229037196
Short name T989
Test name
Test status
Simulation time 1640927779 ps
CPU time 9.5 seconds
Started Jul 17 05:04:52 PM PDT 24
Finished Jul 17 05:05:03 PM PDT 24
Peak memory 209160 kb
Host smart-d4dab1e9-f493-40a4-957b-26b2581d9695
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229037196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.229037196
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3858156976
Short name T129
Test name
Test status
Simulation time 164497392 ps
CPU time 4.47 seconds
Started Jul 17 05:04:47 PM PDT 24
Finished Jul 17 05:04:53 PM PDT 24
Peak memory 211000 kb
Host smart-148fd86f-248e-4d44-8ad8-25ec0e2ca9b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858156976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3858156976
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.665720439
Short name T980
Test name
Test status
Simulation time 108439409 ps
CPU time 2.03 seconds
Started Jul 17 05:04:49 PM PDT 24
Finished Jul 17 05:04:53 PM PDT 24
Peak memory 218652 kb
Host smart-3f8416e7-5228-431d-9f63-a0e318e1ac6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665720
439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.665720439
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4022318374
Short name T878
Test name
Test status
Simulation time 101433257 ps
CPU time 1.66 seconds
Started Jul 17 05:04:49 PM PDT 24
Finished Jul 17 05:04:53 PM PDT 24
Peak memory 209208 kb
Host smart-81096917-60c5-4585-a84c-afe049246e27
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022318374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.4022318374
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.515832601
Short name T136
Test name
Test status
Simulation time 40241272 ps
CPU time 1.25 seconds
Started Jul 17 05:04:49 PM PDT 24
Finished Jul 17 05:04:53 PM PDT 24
Peak memory 209288 kb
Host smart-78560c29-1d15-4b1e-a220-ccef7e65ecd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515832601 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.515832601
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3791881374
Short name T992
Test name
Test status
Simulation time 18721150 ps
CPU time 1.29 seconds
Started Jul 17 05:05:00 PM PDT 24
Finished Jul 17 05:05:04 PM PDT 24
Peak memory 211280 kb
Host smart-f3221af3-a8af-41ab-861b-abb702da3019
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791881374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3791881374
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3901796265
Short name T999
Test name
Test status
Simulation time 113123914 ps
CPU time 2.44 seconds
Started Jul 17 05:04:59 PM PDT 24
Finished Jul 17 05:05:03 PM PDT 24
Peak memory 217492 kb
Host smart-d922aa1f-3add-48c5-b784-986feadd4650
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901796265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3901796265
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2173958193
Short name T126
Test name
Test status
Simulation time 128402610 ps
CPU time 1.88 seconds
Started Jul 17 05:05:00 PM PDT 24
Finished Jul 17 05:05:03 PM PDT 24
Peak memory 221996 kb
Host smart-4bf7cdb8-1b4f-408a-8a68-1f1eac0cd397
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173958193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2173958193
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.176763014
Short name T187
Test name
Test status
Simulation time 26451966 ps
CPU time 1.04 seconds
Started Jul 17 05:05:02 PM PDT 24
Finished Jul 17 05:05:05 PM PDT 24
Peak memory 209272 kb
Host smart-9d483c1c-8303-4f09-ab72-aa055aa041b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176763014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing
.176763014
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2791616138
Short name T881
Test name
Test status
Simulation time 115919504 ps
CPU time 1.17 seconds
Started Jul 17 05:05:00 PM PDT 24
Finished Jul 17 05:05:02 PM PDT 24
Peak memory 208944 kb
Host smart-c0d80b07-4f0b-4d01-8192-44fa3302f298
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791616138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2791616138
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.197543385
Short name T183
Test name
Test status
Simulation time 22108449 ps
CPU time 1.09 seconds
Started Jul 17 05:05:01 PM PDT 24
Finished Jul 17 05:05:04 PM PDT 24
Peak memory 211440 kb
Host smart-34d83acd-f3a3-4877-b1b9-7dc5a1516f79
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197543385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.197543385
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3574513768
Short name T121
Test name
Test status
Simulation time 101177904 ps
CPU time 1.24 seconds
Started Jul 17 05:04:59 PM PDT 24
Finished Jul 17 05:05:02 PM PDT 24
Peak memory 217560 kb
Host smart-d4c2ce94-7009-4558-aab8-52e435221588
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574513768 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3574513768
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2809084274
Short name T186
Test name
Test status
Simulation time 42462515 ps
CPU time 0.88 seconds
Started Jul 17 05:05:02 PM PDT 24
Finished Jul 17 05:05:05 PM PDT 24
Peak memory 209220 kb
Host smart-7bce7a46-d19c-492a-8589-38af1607de17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809084274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2809084274
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2953231851
Short name T908
Test name
Test status
Simulation time 32123222 ps
CPU time 0.91 seconds
Started Jul 17 05:05:03 PM PDT 24
Finished Jul 17 05:05:05 PM PDT 24
Peak memory 208992 kb
Host smart-454cb58a-cbf5-438a-a671-6ace5c61f5cc
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953231851 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2953231851
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1263083332
Short name T889
Test name
Test status
Simulation time 810161711 ps
CPU time 11.21 seconds
Started Jul 17 05:05:00 PM PDT 24
Finished Jul 17 05:05:13 PM PDT 24
Peak memory 208400 kb
Host smart-0561d547-227f-41a9-b5c6-db230f0a3c63
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263083332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1263083332
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.213461037
Short name T931
Test name
Test status
Simulation time 1685083761 ps
CPU time 10.97 seconds
Started Jul 17 05:05:01 PM PDT 24
Finished Jul 17 05:05:14 PM PDT 24
Peak memory 209180 kb
Host smart-72889c1e-8100-4e97-8687-18d4e7dd42a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213461037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.213461037
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3980885208
Short name T131
Test name
Test status
Simulation time 387211862 ps
CPU time 1.66 seconds
Started Jul 17 05:05:00 PM PDT 24
Finished Jul 17 05:05:03 PM PDT 24
Peak memory 210616 kb
Host smart-b5155c49-e5cd-40dc-a90d-bc3a0fd3930c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980885208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3980885208
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1378717765
Short name T913
Test name
Test status
Simulation time 169628346 ps
CPU time 2.65 seconds
Started Jul 17 05:05:00 PM PDT 24
Finished Jul 17 05:05:05 PM PDT 24
Peak memory 219064 kb
Host smart-63942410-6980-4973-9806-c19fe17f942d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137871
7765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1378717765
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3030521257
Short name T901
Test name
Test status
Simulation time 90741260 ps
CPU time 2.07 seconds
Started Jul 17 05:05:00 PM PDT 24
Finished Jul 17 05:05:04 PM PDT 24
Peak memory 209176 kb
Host smart-9585c729-fe63-4dab-abbe-8a2a2846f626
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030521257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3030521257
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2838916496
Short name T137
Test name
Test status
Simulation time 31458180 ps
CPU time 1.19 seconds
Started Jul 17 05:05:01 PM PDT 24
Finished Jul 17 05:05:05 PM PDT 24
Peak memory 209216 kb
Host smart-60918ee1-6c1e-4e18-8324-783ac9e24377
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838916496 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2838916496
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2727897667
Short name T897
Test name
Test status
Simulation time 20864953 ps
CPU time 1.43 seconds
Started Jul 17 05:04:59 PM PDT 24
Finished Jul 17 05:05:02 PM PDT 24
Peak memory 209240 kb
Host smart-ebbbd62d-ca37-452f-b7bf-db8ce2451baa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727897667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2727897667
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.418506590
Short name T973
Test name
Test status
Simulation time 317833934 ps
CPU time 1.93 seconds
Started Jul 17 05:05:01 PM PDT 24
Finished Jul 17 05:05:05 PM PDT 24
Peak memory 218044 kb
Host smart-afa98969-6cd6-4d11-8419-d21a6e183dcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418506590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.418506590
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1857084935
Short name T990
Test name
Test status
Simulation time 56360799 ps
CPU time 2.17 seconds
Started Jul 17 05:05:00 PM PDT 24
Finished Jul 17 05:05:03 PM PDT 24
Peak memory 219400 kb
Host smart-fac90e76-d917-4149-a90e-38e41e6a530d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857084935 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1857084935
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3764037076
Short name T874
Test name
Test status
Simulation time 53969971 ps
CPU time 0.97 seconds
Started Jul 17 05:05:00 PM PDT 24
Finished Jul 17 05:05:03 PM PDT 24
Peak memory 209108 kb
Host smart-6163689f-edce-4182-9d80-f648fba7b7b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764037076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3764037076
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.624098705
Short name T873
Test name
Test status
Simulation time 249432646 ps
CPU time 1.3 seconds
Started Jul 17 05:05:00 PM PDT 24
Finished Jul 17 05:05:02 PM PDT 24
Peak memory 209172 kb
Host smart-1dbb0e3a-bc2f-422a-9309-0be6846d57d7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624098705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.lc_ctrl_jtag_alert_test.624098705
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2963013152
Short name T936
Test name
Test status
Simulation time 2986730237 ps
CPU time 16.68 seconds
Started Jul 17 05:04:59 PM PDT 24
Finished Jul 17 05:05:17 PM PDT 24
Peak memory 209308 kb
Host smart-787d86f6-0aa7-4f98-9dce-343fdba9688b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963013152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2963013152
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2590849479
Short name T967
Test name
Test status
Simulation time 4279106023 ps
CPU time 10.43 seconds
Started Jul 17 05:05:02 PM PDT 24
Finished Jul 17 05:05:14 PM PDT 24
Peak memory 208340 kb
Host smart-ba251dc5-e068-44f0-a581-4b2209383556
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590849479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2590849479
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3939058355
Short name T997
Test name
Test status
Simulation time 134607941 ps
CPU time 2.31 seconds
Started Jul 17 05:05:00 PM PDT 24
Finished Jul 17 05:05:05 PM PDT 24
Peak memory 210844 kb
Host smart-4b5a4602-1756-41e3-972d-fe650f13ce13
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939058355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3939058355
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4388441
Short name T963
Test name
Test status
Simulation time 406432850 ps
CPU time 2.12 seconds
Started Jul 17 05:05:00 PM PDT 24
Finished Jul 17 05:05:04 PM PDT 24
Peak memory 217524 kb
Host smart-7576f1ce-274e-4338-9c0a-ad928af9f515
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438844
1 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4388441
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3047510911
Short name T905
Test name
Test status
Simulation time 358355851 ps
CPU time 1.13 seconds
Started Jul 17 05:05:00 PM PDT 24
Finished Jul 17 05:05:04 PM PDT 24
Peak memory 209224 kb
Host smart-42ba4494-5d30-4cf3-ae3b-d3f145311ed3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047510911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3047510911
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3738615461
Short name T891
Test name
Test status
Simulation time 26464290 ps
CPU time 1.04 seconds
Started Jul 17 05:05:01 PM PDT 24
Finished Jul 17 05:05:04 PM PDT 24
Peak memory 209248 kb
Host smart-db6367c2-b940-4b2d-83d8-ccf33a353930
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738615461 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3738615461
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1674318267
Short name T977
Test name
Test status
Simulation time 28896541 ps
CPU time 1.49 seconds
Started Jul 17 05:04:58 PM PDT 24
Finished Jul 17 05:05:00 PM PDT 24
Peak memory 209252 kb
Host smart-0b7b6872-e41e-49b7-8e2b-09ab62eded83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674318267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1674318267
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.13504506
Short name T956
Test name
Test status
Simulation time 87906535 ps
CPU time 2.95 seconds
Started Jul 17 05:05:01 PM PDT 24
Finished Jul 17 05:05:06 PM PDT 24
Peak memory 217476 kb
Host smart-b66f0f66-1483-4aa6-9118-0b0aa699d74c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13504506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.13504506
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.841129193
Short name T965
Test name
Test status
Simulation time 24136575 ps
CPU time 1.17 seconds
Started Jul 17 05:05:13 PM PDT 24
Finished Jul 17 05:05:16 PM PDT 24
Peak memory 218536 kb
Host smart-34fba9ab-d2ef-4ada-93e0-fdfdf4998db0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841129193 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.841129193
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1341081632
Short name T958
Test name
Test status
Simulation time 46586177 ps
CPU time 0.98 seconds
Started Jul 17 05:05:12 PM PDT 24
Finished Jul 17 05:05:15 PM PDT 24
Peak memory 209456 kb
Host smart-87d9497e-89dc-4df5-96b3-4e82f1e5b6df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341081632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1341081632
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1642083506
Short name T909
Test name
Test status
Simulation time 411668612 ps
CPU time 2.87 seconds
Started Jul 17 05:05:12 PM PDT 24
Finished Jul 17 05:05:17 PM PDT 24
Peak memory 209288 kb
Host smart-eafbf3b7-c8ab-4eb3-a672-8b317ceb9e2c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642083506 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1642083506
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1859638436
Short name T106
Test name
Test status
Simulation time 3990055770 ps
CPU time 20.89 seconds
Started Jul 17 05:05:11 PM PDT 24
Finished Jul 17 05:05:33 PM PDT 24
Peak memory 208592 kb
Host smart-f906868f-b62d-473a-b36e-3299fa60de25
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859638436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1859638436
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2592344040
Short name T976
Test name
Test status
Simulation time 5079864965 ps
CPU time 54.8 seconds
Started Jul 17 05:05:10 PM PDT 24
Finished Jul 17 05:06:06 PM PDT 24
Peak memory 208392 kb
Host smart-e95ebe5e-e783-441d-9246-3e47af630de4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592344040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2592344040
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.180452424
Short name T988
Test name
Test status
Simulation time 187598687 ps
CPU time 1.3 seconds
Started Jul 17 05:05:01 PM PDT 24
Finished Jul 17 05:05:05 PM PDT 24
Peak memory 210280 kb
Host smart-02cb3bba-4ffa-40d6-96c5-ce6fd9bb9b0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180452424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.180452424
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.359478258
Short name T918
Test name
Test status
Simulation time 109634375 ps
CPU time 1.76 seconds
Started Jul 17 05:05:13 PM PDT 24
Finished Jul 17 05:05:16 PM PDT 24
Peak memory 220288 kb
Host smart-53ee6131-7ab3-4345-a504-ecf1e61e9ecd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359478
258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.359478258
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.4166107792
Short name T984
Test name
Test status
Simulation time 328613810 ps
CPU time 4.31 seconds
Started Jul 17 05:05:15 PM PDT 24
Finished Jul 17 05:05:20 PM PDT 24
Peak memory 209172 kb
Host smart-df7b55ff-2876-4a82-9cc4-6c1884c6cc59
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166107792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.4166107792
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3797635622
Short name T939
Test name
Test status
Simulation time 75415478 ps
CPU time 1.47 seconds
Started Jul 17 05:05:12 PM PDT 24
Finished Jul 17 05:05:15 PM PDT 24
Peak memory 211324 kb
Host smart-34f5049e-ef72-41e2-a67d-a81a0c1ee2d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797635622 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3797635622
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2563524709
Short name T910
Test name
Test status
Simulation time 33290712 ps
CPU time 1.2 seconds
Started Jul 17 05:05:13 PM PDT 24
Finished Jul 17 05:05:16 PM PDT 24
Peak memory 209236 kb
Host smart-19dc1882-0ad6-40e8-b0c7-af0254db842f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563524709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2563524709
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.610103269
Short name T943
Test name
Test status
Simulation time 419892125 ps
CPU time 2.47 seconds
Started Jul 17 05:05:13 PM PDT 24
Finished Jul 17 05:05:17 PM PDT 24
Peak memory 217396 kb
Host smart-4f61c54c-5de3-4827-b9d0-1baa9ddbbe03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610103269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.610103269
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1933946647
Short name T116
Test name
Test status
Simulation time 149932363 ps
CPU time 1.79 seconds
Started Jul 17 05:05:11 PM PDT 24
Finished Jul 17 05:05:14 PM PDT 24
Peak memory 221808 kb
Host smart-29c970a8-ae43-49c7-be30-e5b10b7750c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933946647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1933946647
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1555002648
Short name T995
Test name
Test status
Simulation time 33386259 ps
CPU time 1.49 seconds
Started Jul 17 05:05:11 PM PDT 24
Finished Jul 17 05:05:13 PM PDT 24
Peak memory 217492 kb
Host smart-4f19ae3d-fe63-4004-bb8e-d6275395486e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555002648 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1555002648
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3669858555
Short name T184
Test name
Test status
Simulation time 13357440 ps
CPU time 0.94 seconds
Started Jul 17 05:05:13 PM PDT 24
Finished Jul 17 05:05:16 PM PDT 24
Peak memory 209456 kb
Host smart-bef3755f-b542-4645-9df0-3197a2fda14c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669858555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3669858555
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1999109812
Short name T920
Test name
Test status
Simulation time 320164933 ps
CPU time 1.44 seconds
Started Jul 17 05:05:13 PM PDT 24
Finished Jul 17 05:05:16 PM PDT 24
Peak memory 207760 kb
Host smart-5e28f4bc-c02b-41ca-beb7-448cd17e8e10
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999109812 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1999109812
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1530862786
Short name T959
Test name
Test status
Simulation time 2668234861 ps
CPU time 10.15 seconds
Started Jul 17 05:05:11 PM PDT 24
Finished Jul 17 05:05:22 PM PDT 24
Peak memory 209348 kb
Host smart-9accb939-1947-4101-b1c1-af356b491fb7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530862786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1530862786
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.930342823
Short name T962
Test name
Test status
Simulation time 1122791825 ps
CPU time 9.07 seconds
Started Jul 17 05:05:13 PM PDT 24
Finished Jul 17 05:05:24 PM PDT 24
Peak memory 208960 kb
Host smart-e04cf3dd-fbc7-41be-87c2-955e7bdf40ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930342823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.930342823
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.4229588417
Short name T899
Test name
Test status
Simulation time 524205636 ps
CPU time 1.85 seconds
Started Jul 17 05:05:10 PM PDT 24
Finished Jul 17 05:05:13 PM PDT 24
Peak memory 210820 kb
Host smart-17bc184d-824f-4378-a17a-71e9e0286e38
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229588417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.4229588417
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1636957444
Short name T101
Test name
Test status
Simulation time 81140616 ps
CPU time 1.72 seconds
Started Jul 17 05:05:12 PM PDT 24
Finished Jul 17 05:05:15 PM PDT 24
Peak memory 217508 kb
Host smart-5c0b7c58-6df6-4aa2-b8d8-8340ea7d2801
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163695
7444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1636957444
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2671680110
Short name T915
Test name
Test status
Simulation time 157082458 ps
CPU time 1.94 seconds
Started Jul 17 05:05:13 PM PDT 24
Finished Jul 17 05:05:17 PM PDT 24
Peak memory 209100 kb
Host smart-a64779df-b559-4d2b-81a6-5f173e427e8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671680110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2671680110
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.446458864
Short name T135
Test name
Test status
Simulation time 256046510 ps
CPU time 2.15 seconds
Started Jul 17 05:05:12 PM PDT 24
Finished Jul 17 05:05:16 PM PDT 24
Peak memory 217672 kb
Host smart-9509f1d4-7748-4ca9-bca6-32b7a66f13db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446458864 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.446458864
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.66679570
Short name T987
Test name
Test status
Simulation time 15030014 ps
CPU time 1.12 seconds
Started Jul 17 05:05:12 PM PDT 24
Finished Jul 17 05:05:14 PM PDT 24
Peak memory 209184 kb
Host smart-6e8c96a8-8d44-446d-950c-2b01682b68f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66679570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_s
ame_csr_outstanding.66679570
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.643149729
Short name T993
Test name
Test status
Simulation time 114758591 ps
CPU time 4.83 seconds
Started Jul 17 05:05:12 PM PDT 24
Finished Jul 17 05:05:18 PM PDT 24
Peak memory 217552 kb
Host smart-4492c642-3d7a-4e65-af13-880c4508b4e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643149729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.643149729
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1709094456
Short name T117
Test name
Test status
Simulation time 236499522 ps
CPU time 2.88 seconds
Started Jul 17 05:05:11 PM PDT 24
Finished Jul 17 05:05:15 PM PDT 24
Peak memory 222068 kb
Host smart-9f2c3fa6-eda4-491c-864b-abb8825d9cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709094456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1709094456
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.602417479
Short name T942
Test name
Test status
Simulation time 39894914 ps
CPU time 1.6 seconds
Started Jul 17 05:05:25 PM PDT 24
Finished Jul 17 05:05:29 PM PDT 24
Peak memory 222448 kb
Host smart-0e465afc-ef76-43e8-8e09-236fe94549e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602417479 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.602417479
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.311754773
Short name T917
Test name
Test status
Simulation time 52854452 ps
CPU time 0.88 seconds
Started Jul 17 05:05:30 PM PDT 24
Finished Jul 17 05:05:32 PM PDT 24
Peak memory 209228 kb
Host smart-516bdec8-9bfc-4068-b186-be068e20214b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311754773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.311754773
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2120267810
Short name T949
Test name
Test status
Simulation time 244762784 ps
CPU time 1.03 seconds
Started Jul 17 05:05:12 PM PDT 24
Finished Jul 17 05:05:15 PM PDT 24
Peak memory 209104 kb
Host smart-7e28c074-80de-46da-b19d-b985d0ad1dc7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120267810 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2120267810
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1158608526
Short name T885
Test name
Test status
Simulation time 192657642 ps
CPU time 5.6 seconds
Started Jul 17 05:05:13 PM PDT 24
Finished Jul 17 05:05:21 PM PDT 24
Peak memory 209400 kb
Host smart-ee7afc2f-4ac2-412e-b080-b5fce3d72a25
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158608526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1158608526
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4168928507
Short name T953
Test name
Test status
Simulation time 1382264890 ps
CPU time 12.55 seconds
Started Jul 17 05:05:13 PM PDT 24
Finished Jul 17 05:05:27 PM PDT 24
Peak memory 209112 kb
Host smart-6602bcfb-1182-4be1-bd14-200a55e811b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168928507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.4168928507
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2010292663
Short name T981
Test name
Test status
Simulation time 92936013 ps
CPU time 2.83 seconds
Started Jul 17 05:05:13 PM PDT 24
Finished Jul 17 05:05:17 PM PDT 24
Peak memory 210744 kb
Host smart-c14a43c3-8730-4773-815b-2b9ad2b9b3c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010292663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2010292663
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.181302980
Short name T966
Test name
Test status
Simulation time 45722814 ps
CPU time 1.19 seconds
Started Jul 17 05:05:14 PM PDT 24
Finished Jul 17 05:05:16 PM PDT 24
Peak memory 209292 kb
Host smart-c1bb8508-10b9-478d-94fc-7998973e2330
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181302980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.181302980
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1787248835
Short name T938
Test name
Test status
Simulation time 30184161 ps
CPU time 1.41 seconds
Started Jul 17 05:05:10 PM PDT 24
Finished Jul 17 05:05:12 PM PDT 24
Peak memory 209244 kb
Host smart-e69a0a1a-dd34-4bdf-bca8-ff34e3d05b47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787248835 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1787248835
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1729306220
Short name T945
Test name
Test status
Simulation time 68189057 ps
CPU time 1.45 seconds
Started Jul 17 05:05:25 PM PDT 24
Finished Jul 17 05:05:29 PM PDT 24
Peak memory 217552 kb
Host smart-b8bc5d33-6840-4b9c-9ce6-692b67985de8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729306220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1729306220
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3191636282
Short name T998
Test name
Test status
Simulation time 383602916 ps
CPU time 3.89 seconds
Started Jul 17 05:05:26 PM PDT 24
Finished Jul 17 05:05:33 PM PDT 24
Peak memory 218084 kb
Host smart-32ca6f08-dfd9-45d7-8800-d622651ec8a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191636282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3191636282
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2905974060
Short name T153
Test name
Test status
Simulation time 17502216 ps
CPU time 1.14 seconds
Started Jul 17 05:05:24 PM PDT 24
Finished Jul 17 05:05:27 PM PDT 24
Peak memory 219176 kb
Host smart-fdc7f5fc-cc68-40e4-8d28-48f12857519e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905974060 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2905974060
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1699163183
Short name T912
Test name
Test status
Simulation time 18120201 ps
CPU time 1.04 seconds
Started Jul 17 05:05:26 PM PDT 24
Finished Jul 17 05:05:30 PM PDT 24
Peak memory 208872 kb
Host smart-f8b2286f-f316-46b6-8d64-6515bb134cf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699163183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1699163183
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3658837675
Short name T941
Test name
Test status
Simulation time 32740655 ps
CPU time 1.04 seconds
Started Jul 17 05:05:24 PM PDT 24
Finished Jul 17 05:05:26 PM PDT 24
Peak memory 209136 kb
Host smart-e7ff15ef-c183-4725-ba42-97954ee1a3eb
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658837675 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3658837675
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1423039472
Short name T924
Test name
Test status
Simulation time 1144465350 ps
CPU time 23.74 seconds
Started Jul 17 05:05:25 PM PDT 24
Finished Jul 17 05:05:51 PM PDT 24
Peak memory 209200 kb
Host smart-240ed368-199a-4b9b-953e-8096e2568bb7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423039472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1423039472
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.471132841
Short name T926
Test name
Test status
Simulation time 4816672425 ps
CPU time 44.55 seconds
Started Jul 17 05:05:24 PM PDT 24
Finished Jul 17 05:06:10 PM PDT 24
Peak memory 209272 kb
Host smart-8e486ba9-2f2e-4aa1-a2a7-9227436df778
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471132841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.471132841
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1027148515
Short name T130
Test name
Test status
Simulation time 61056753 ps
CPU time 2.22 seconds
Started Jul 17 05:05:24 PM PDT 24
Finished Jul 17 05:05:27 PM PDT 24
Peak memory 210724 kb
Host smart-daf5d08a-0b98-4f5f-9015-f033c14105f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027148515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1027148515
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.481820973
Short name T996
Test name
Test status
Simulation time 100864925 ps
CPU time 3.42 seconds
Started Jul 17 05:05:25 PM PDT 24
Finished Jul 17 05:05:32 PM PDT 24
Peak memory 222444 kb
Host smart-aa9f8ba4-4a04-4620-af22-d36bb9559b15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481820
973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.481820973
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1328139075
Short name T930
Test name
Test status
Simulation time 157838214 ps
CPU time 1.14 seconds
Started Jul 17 05:05:23 PM PDT 24
Finished Jul 17 05:05:25 PM PDT 24
Peak memory 209180 kb
Host smart-ac12ed54-5b0c-42d8-bad2-8df8edba599d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328139075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1328139075
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3113860746
Short name T955
Test name
Test status
Simulation time 45460851 ps
CPU time 1.37 seconds
Started Jul 17 05:05:26 PM PDT 24
Finished Jul 17 05:05:30 PM PDT 24
Peak memory 209208 kb
Host smart-8065ccf2-615f-439b-9851-70a7e17fadf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113860746 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3113860746
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4293366865
Short name T194
Test name
Test status
Simulation time 77185477 ps
CPU time 1.31 seconds
Started Jul 17 05:05:23 PM PDT 24
Finished Jul 17 05:05:26 PM PDT 24
Peak memory 211356 kb
Host smart-24dcb0cb-8d2a-4d64-aafd-fa740c2483d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293366865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.4293366865
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1313534191
Short name T104
Test name
Test status
Simulation time 35037640 ps
CPU time 2.21 seconds
Started Jul 17 05:05:25 PM PDT 24
Finished Jul 17 05:05:30 PM PDT 24
Peak memory 217564 kb
Host smart-dfa48b76-efdb-4d9c-8863-b2dc6a78a8dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313534191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1313534191
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4019340565
Short name T125
Test name
Test status
Simulation time 178064225 ps
CPU time 2.17 seconds
Started Jul 17 05:05:26 PM PDT 24
Finished Jul 17 05:05:30 PM PDT 24
Peak memory 221916 kb
Host smart-f3ec3969-afb7-4535-b9d3-0f65c7d5aa73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019340565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.4019340565
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3091712534
Short name T631
Test name
Test status
Simulation time 45533283 ps
CPU time 0.83 seconds
Started Jul 17 05:14:42 PM PDT 24
Finished Jul 17 05:14:44 PM PDT 24
Peak memory 208156 kb
Host smart-5e977263-e19a-4a4f-a2b8-4fc13a0d2d25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091712534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3091712534
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1382437798
Short name T212
Test name
Test status
Simulation time 569720468 ps
CPU time 10.96 seconds
Started Jul 17 05:13:08 PM PDT 24
Finished Jul 17 05:13:20 PM PDT 24
Peak memory 225560 kb
Host smart-f82ff065-1f95-45b9-b284-7533217291c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382437798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1382437798
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.725678749
Short name T791
Test name
Test status
Simulation time 453130156 ps
CPU time 6.1 seconds
Started Jul 17 05:13:07 PM PDT 24
Finished Jul 17 05:13:14 PM PDT 24
Peak memory 217132 kb
Host smart-4cb04de0-de49-43cd-b610-45d135c038dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725678749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.725678749
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2925829337
Short name T697
Test name
Test status
Simulation time 4025284413 ps
CPU time 56.01 seconds
Started Jul 17 05:13:09 PM PDT 24
Finished Jul 17 05:14:06 PM PDT 24
Peak memory 218268 kb
Host smart-ac85e9ec-12d1-45db-ace4-2f33ae9ef3a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925829337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2925829337
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.3101843415
Short name T263
Test name
Test status
Simulation time 5030542869 ps
CPU time 24.58 seconds
Started Jul 17 05:13:04 PM PDT 24
Finished Jul 17 05:13:30 PM PDT 24
Peak memory 217312 kb
Host smart-65d356d8-7daf-4ad4-a242-6eb806d1c8ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101843415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.3
101843415
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2190143994
Short name T828
Test name
Test status
Simulation time 1339600967 ps
CPU time 12.55 seconds
Started Jul 17 05:13:08 PM PDT 24
Finished Jul 17 05:13:21 PM PDT 24
Peak memory 222688 kb
Host smart-4d014e54-f0e2-4f61-aef4-b200d1547027
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190143994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2190143994
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2203014176
Short name T68
Test name
Test status
Simulation time 4198663795 ps
CPU time 30.8 seconds
Started Jul 17 05:13:09 PM PDT 24
Finished Jul 17 05:13:41 PM PDT 24
Peak memory 217192 kb
Host smart-f55a7121-6df2-4d2d-8d8b-57fbfd81ab2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203014176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2203014176
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2768794880
Short name T79
Test name
Test status
Simulation time 330176367 ps
CPU time 5.21 seconds
Started Jul 17 05:13:07 PM PDT 24
Finished Jul 17 05:13:13 PM PDT 24
Peak memory 217024 kb
Host smart-886befc3-364d-42d2-991b-25b67feab00d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768794880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2768794880
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3133622910
Short name T142
Test name
Test status
Simulation time 3980341696 ps
CPU time 74.41 seconds
Started Jul 17 05:13:05 PM PDT 24
Finished Jul 17 05:14:20 PM PDT 24
Peak memory 283128 kb
Host smart-1d569260-bd52-419a-8f3f-a6273bc16a9e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133622910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3133622910
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.48057654
Short name T478
Test name
Test status
Simulation time 2976279291 ps
CPU time 13.82 seconds
Started Jul 17 05:15:01 PM PDT 24
Finished Jul 17 05:15:15 PM PDT 24
Peak memory 247804 kb
Host smart-93d56361-dc29-4fb5-9e13-8df9d8e2d72f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48057654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jt
ag_state_post_trans.48057654
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1432899597
Short name T305
Test name
Test status
Simulation time 56845231 ps
CPU time 2.91 seconds
Started Jul 17 05:13:05 PM PDT 24
Finished Jul 17 05:13:09 PM PDT 24
Peak memory 221928 kb
Host smart-992396f3-b808-4f16-82e8-3e8c588a0ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432899597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1432899597
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2519720837
Short name T830
Test name
Test status
Simulation time 320646948 ps
CPU time 8.15 seconds
Started Jul 17 05:13:02 PM PDT 24
Finished Jul 17 05:13:11 PM PDT 24
Peak memory 214156 kb
Host smart-d39dedf7-f131-4a4f-8030-769fcfb73cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519720837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2519720837
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3902554327
Short name T58
Test name
Test status
Simulation time 204292240 ps
CPU time 35.6 seconds
Started Jul 17 05:13:15 PM PDT 24
Finished Jul 17 05:13:52 PM PDT 24
Peak memory 282088 kb
Host smart-aae09644-980a-4199-8aa0-219cb09ebdb8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902554327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3902554327
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.396693233
Short name T388
Test name
Test status
Simulation time 2316465967 ps
CPU time 16.28 seconds
Started Jul 17 05:13:16 PM PDT 24
Finished Jul 17 05:13:33 PM PDT 24
Peak memory 217880 kb
Host smart-d2f046b9-4a8c-4c4f-bfc5-a2f3be6ac017
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396693233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.396693233
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3299845485
Short name T174
Test name
Test status
Simulation time 3864410848 ps
CPU time 9.54 seconds
Started Jul 17 05:16:15 PM PDT 24
Finished Jul 17 05:16:27 PM PDT 24
Peak memory 225512 kb
Host smart-111b2b40-b2bb-4960-aa5d-ce6c83473356
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299845485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3299845485
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.581702996
Short name T633
Test name
Test status
Simulation time 457912303 ps
CPU time 10.82 seconds
Started Jul 17 05:13:18 PM PDT 24
Finished Jul 17 05:13:30 PM PDT 24
Peak memory 225448 kb
Host smart-48ab8756-46d9-41d6-abdd-516ee9077327
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581702996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.581702996
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2018629762
Short name T575
Test name
Test status
Simulation time 1458143997 ps
CPU time 7.76 seconds
Started Jul 17 05:16:00 PM PDT 24
Finished Jul 17 05:16:17 PM PDT 24
Peak memory 225560 kb
Host smart-e03c7585-554a-46ab-8eb7-8a3017608850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018629762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2018629762
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2630032619
Short name T471
Test name
Test status
Simulation time 36507223 ps
CPU time 2.46 seconds
Started Jul 17 05:14:48 PM PDT 24
Finished Jul 17 05:14:52 PM PDT 24
Peak memory 213800 kb
Host smart-0e2b4ce8-2efd-43dd-b7bc-f083c8915e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630032619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2630032619
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1841573197
Short name T398
Test name
Test status
Simulation time 4253365638 ps
CPU time 31.4 seconds
Started Jul 17 05:13:09 PM PDT 24
Finished Jul 17 05:13:41 PM PDT 24
Peak memory 250576 kb
Host smart-ebc37815-12df-440e-a7a2-9a1ac9463433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841573197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1841573197
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1570761523
Short name T342
Test name
Test status
Simulation time 872060893 ps
CPU time 10.15 seconds
Started Jul 17 05:15:01 PM PDT 24
Finished Jul 17 05:15:12 PM PDT 24
Peak memory 250720 kb
Host smart-ecd28737-f8fd-4d54-a77b-a53cdff6dce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570761523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1570761523
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3975092268
Short name T765
Test name
Test status
Simulation time 2895460699 ps
CPU time 64.94 seconds
Started Jul 17 05:13:15 PM PDT 24
Finished Jul 17 05:14:22 PM PDT 24
Peak memory 250576 kb
Host smart-519c6de9-b625-48fb-960f-9ea4b216488e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975092268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3975092268
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1103297581
Short name T752
Test name
Test status
Simulation time 35897155 ps
CPU time 0.94 seconds
Started Jul 17 05:13:07 PM PDT 24
Finished Jul 17 05:13:09 PM PDT 24
Peak memory 211444 kb
Host smart-1e5c45e0-a161-45a3-85c1-9c7bc5f987f6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103297581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1103297581
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3115490337
Short name T261
Test name
Test status
Simulation time 196635181 ps
CPU time 0.87 seconds
Started Jul 17 05:13:18 PM PDT 24
Finished Jul 17 05:13:20 PM PDT 24
Peak memory 208280 kb
Host smart-2a9dc93f-c2b1-4ad6-b9ef-aa7b7e94bafe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115490337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3115490337
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.3804521780
Short name T818
Test name
Test status
Simulation time 87011718 ps
CPU time 0.9 seconds
Started Jul 17 05:15:40 PM PDT 24
Finished Jul 17 05:15:42 PM PDT 24
Peak memory 208276 kb
Host smart-d06e6ab5-ff6e-4459-883e-b6914f39f097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804521780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.3804521780
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2846398251
Short name T400
Test name
Test status
Simulation time 1046002664 ps
CPU time 11.86 seconds
Started Jul 17 05:13:18 PM PDT 24
Finished Jul 17 05:13:31 PM PDT 24
Peak memory 217776 kb
Host smart-e83a8d69-0b94-4dd1-8fa0-1081ef7b663a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846398251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2846398251
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2482990249
Short name T577
Test name
Test status
Simulation time 1308740290 ps
CPU time 4.61 seconds
Started Jul 17 05:16:03 PM PDT 24
Finished Jul 17 05:16:16 PM PDT 24
Peak memory 217180 kb
Host smart-cd23d167-f3c9-4beb-ac4c-6424e426a92d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482990249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2482990249
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.862481053
Short name T410
Test name
Test status
Simulation time 9469935483 ps
CPU time 28.4 seconds
Started Jul 17 05:15:23 PM PDT 24
Finished Jul 17 05:15:53 PM PDT 24
Peak memory 218372 kb
Host smart-9a3ce1a2-6c13-4a4a-b249-324bd1dfba68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862481053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.862481053
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3321590450
Short name T175
Test name
Test status
Simulation time 3068039975 ps
CPU time 18.86 seconds
Started Jul 17 05:13:15 PM PDT 24
Finished Jul 17 05:13:35 PM PDT 24
Peak memory 217268 kb
Host smart-99a62e86-1447-48fc-8f2b-9b57fcbdcb94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321590450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3
321590450
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2576833959
Short name T529
Test name
Test status
Simulation time 2696936137 ps
CPU time 12.75 seconds
Started Jul 17 05:13:16 PM PDT 24
Finished Jul 17 05:13:30 PM PDT 24
Peak memory 217740 kb
Host smart-90f9d9a6-1a1e-4476-82ac-5a3c72c05b68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576833959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2576833959
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3303566875
Short name T666
Test name
Test status
Simulation time 4150883173 ps
CPU time 32.58 seconds
Started Jul 17 05:13:16 PM PDT 24
Finished Jul 17 05:13:50 PM PDT 24
Peak memory 217164 kb
Host smart-31dc1c60-e2a9-4ab6-a6cf-f40824dd4b31
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303566875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3303566875
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1146392793
Short name T713
Test name
Test status
Simulation time 693822449 ps
CPU time 3.76 seconds
Started Jul 17 05:13:15 PM PDT 24
Finished Jul 17 05:13:20 PM PDT 24
Peak memory 217084 kb
Host smart-162c6c06-68af-46cc-bfe2-a1048bc1354d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146392793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1146392793
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3623197193
Short name T550
Test name
Test status
Simulation time 8299778793 ps
CPU time 48.72 seconds
Started Jul 17 05:15:01 PM PDT 24
Finished Jul 17 05:15:51 PM PDT 24
Peak memory 278624 kb
Host smart-bd4d101e-e850-4673-b1b3-cb9acaeddd95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623197193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3623197193
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3955020383
Short name T561
Test name
Test status
Simulation time 353116868 ps
CPU time 16.23 seconds
Started Jul 17 05:13:16 PM PDT 24
Finished Jul 17 05:13:34 PM PDT 24
Peak memory 250360 kb
Host smart-81fcaeb8-e933-44ac-8cac-2ee5e07cbdbe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955020383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3955020383
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.577232209
Short name T740
Test name
Test status
Simulation time 155735438 ps
CPU time 3.38 seconds
Started Jul 17 05:13:16 PM PDT 24
Finished Jul 17 05:13:20 PM PDT 24
Peak memory 221988 kb
Host smart-cc58969e-9a95-4213-b776-d75ae0b7315c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577232209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.577232209
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.109245051
Short name T487
Test name
Test status
Simulation time 320127123 ps
CPU time 20.72 seconds
Started Jul 17 05:13:14 PM PDT 24
Finished Jul 17 05:13:36 PM PDT 24
Peak memory 214252 kb
Host smart-1e15f13b-3013-41bd-b4c3-e436b021d4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109245051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.109245051
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2813748403
Short name T59
Test name
Test status
Simulation time 1020522711 ps
CPU time 37.04 seconds
Started Jul 17 05:15:39 PM PDT 24
Finished Jul 17 05:16:17 PM PDT 24
Peak memory 269240 kb
Host smart-65edb6a7-9bc9-47b1-b634-b230d35ba836
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813748403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2813748403
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2099411709
Short name T497
Test name
Test status
Simulation time 348810644 ps
CPU time 14.86 seconds
Started Jul 17 05:15:42 PM PDT 24
Finished Jul 17 05:16:00 PM PDT 24
Peak memory 225412 kb
Host smart-08b9294c-7b41-4c4d-8ee2-2c9d86f39dd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099411709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2099411709
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.138335572
Short name T289
Test name
Test status
Simulation time 1051159274 ps
CPU time 12.05 seconds
Started Jul 17 05:13:16 PM PDT 24
Finished Jul 17 05:13:30 PM PDT 24
Peak memory 225500 kb
Host smart-5ac98a21-d5eb-4f24-90a5-537721ccecec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138335572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.138335572
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3654747249
Short name T700
Test name
Test status
Simulation time 1277302675 ps
CPU time 11.06 seconds
Started Jul 17 05:13:15 PM PDT 24
Finished Jul 17 05:13:27 PM PDT 24
Peak memory 225560 kb
Host smart-1954c757-111c-4af0-a451-eb2b04f74c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654747249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3654747249
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.209616286
Short name T745
Test name
Test status
Simulation time 73346432 ps
CPU time 1.35 seconds
Started Jul 17 05:13:18 PM PDT 24
Finished Jul 17 05:13:20 PM PDT 24
Peak memory 217112 kb
Host smart-7ee7d991-c6a5-45ef-bed8-32d020b1b819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209616286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.209616286
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2251008838
Short name T472
Test name
Test status
Simulation time 680975229 ps
CPU time 23.66 seconds
Started Jul 17 05:17:28 PM PDT 24
Finished Jul 17 05:17:53 PM PDT 24
Peak memory 250488 kb
Host smart-206b582b-6d95-4641-91ef-b8e89dcf245b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251008838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2251008838
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3511743635
Short name T222
Test name
Test status
Simulation time 307527132 ps
CPU time 7.54 seconds
Started Jul 17 05:17:24 PM PDT 24
Finished Jul 17 05:17:33 PM PDT 24
Peak memory 250484 kb
Host smart-c9c2dd49-ec82-4681-8281-58aabe14316d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511743635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3511743635
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.1948854795
Short name T44
Test name
Test status
Simulation time 39781186475 ps
CPU time 365.86 seconds
Started Jul 17 05:15:26 PM PDT 24
Finished Jul 17 05:21:33 PM PDT 24
Peak memory 528972 kb
Host smart-532c5a56-5b27-4fe9-81da-225df2a8c054
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948854795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.1948854795
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.1463303425
Short name T441
Test name
Test status
Simulation time 589455819356 ps
CPU time 817.1 seconds
Started Jul 17 05:13:13 PM PDT 24
Finished Jul 17 05:26:51 PM PDT 24
Peak memory 372492 kb
Host smart-23242c62-6854-4e8f-9d6e-31d642a7e5ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1463303425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.1463303425
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3874558291
Short name T835
Test name
Test status
Simulation time 40151802 ps
CPU time 0.91 seconds
Started Jul 17 05:13:15 PM PDT 24
Finished Jul 17 05:13:17 PM PDT 24
Peak memory 211328 kb
Host smart-85e98010-a268-4ff6-b593-cb626f32f5e2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874558291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3874558291
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1047915306
Short name T669
Test name
Test status
Simulation time 75284759 ps
CPU time 1.16 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:17:54 PM PDT 24
Peak memory 208464 kb
Host smart-27f2683d-ba8c-4f9c-a0c5-db77bf5111d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047915306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1047915306
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1228270101
Short name T754
Test name
Test status
Simulation time 257508796 ps
CPU time 9.69 seconds
Started Jul 17 05:14:05 PM PDT 24
Finished Jul 17 05:14:16 PM PDT 24
Peak memory 217728 kb
Host smart-7a4361e9-48ac-4b0c-9b92-5d9ad248bdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228270101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1228270101
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3962267647
Short name T167
Test name
Test status
Simulation time 1669742873 ps
CPU time 6.82 seconds
Started Jul 17 05:16:10 PM PDT 24
Finished Jul 17 05:16:21 PM PDT 24
Peak memory 216564 kb
Host smart-9176462c-4504-471b-9bda-d442127158af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962267647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3962267647
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2347946566
Short name T800
Test name
Test status
Simulation time 23505739451 ps
CPU time 42.79 seconds
Started Jul 17 05:14:16 PM PDT 24
Finished Jul 17 05:15:00 PM PDT 24
Peak memory 218280 kb
Host smart-a063806e-d5f8-4de6-9d28-afd272461c69
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347946566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2347946566
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.988952369
Short name T727
Test name
Test status
Simulation time 475104304 ps
CPU time 14.92 seconds
Started Jul 17 05:14:14 PM PDT 24
Finished Jul 17 05:14:30 PM PDT 24
Peak memory 223900 kb
Host smart-cc6f8b68-6487-4183-bd63-dcd761c7c5d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988952369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_prog_failure.988952369
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2083182082
Short name T330
Test name
Test status
Simulation time 520052371 ps
CPU time 2.15 seconds
Started Jul 17 05:14:16 PM PDT 24
Finished Jul 17 05:14:20 PM PDT 24
Peak memory 217024 kb
Host smart-79cc4f2c-0fcf-489b-82b3-5fc1c733bb65
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083182082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2083182082
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1587284410
Short name T218
Test name
Test status
Simulation time 9686846350 ps
CPU time 54.38 seconds
Started Jul 17 05:14:15 PM PDT 24
Finished Jul 17 05:15:11 PM PDT 24
Peak memory 282960 kb
Host smart-263b1ad9-666d-4287-b326-51bb1dc8e2c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587284410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1587284410
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.956275984
Short name T422
Test name
Test status
Simulation time 1489637964 ps
CPU time 12.97 seconds
Started Jul 17 05:14:15 PM PDT 24
Finished Jul 17 05:14:29 PM PDT 24
Peak memory 225884 kb
Host smart-d360f13b-86c0-4d16-be11-1674b237efa1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956275984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.956275984
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.1181109109
Short name T744
Test name
Test status
Simulation time 15937103 ps
CPU time 1.68 seconds
Started Jul 17 05:14:02 PM PDT 24
Finished Jul 17 05:14:05 PM PDT 24
Peak memory 221272 kb
Host smart-f5384a8e-1ed2-464b-a9bf-ad38753a6706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181109109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1181109109
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3582904985
Short name T333
Test name
Test status
Simulation time 2432075696 ps
CPU time 17.18 seconds
Started Jul 17 05:14:24 PM PDT 24
Finished Jul 17 05:14:42 PM PDT 24
Peak memory 218728 kb
Host smart-fab12bfd-180d-401c-9d25-425cdd2c0be3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582904985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3582904985
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.510852757
Short name T677
Test name
Test status
Simulation time 353730515 ps
CPU time 14.92 seconds
Started Jul 17 05:14:18 PM PDT 24
Finished Jul 17 05:14:34 PM PDT 24
Peak memory 225468 kb
Host smart-d29a6b94-9ef4-4fa3-951c-d749da9c68bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510852757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.510852757
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.320113746
Short name T846
Test name
Test status
Simulation time 406197235 ps
CPU time 14.35 seconds
Started Jul 17 05:15:01 PM PDT 24
Finished Jul 17 05:15:17 PM PDT 24
Peak memory 217896 kb
Host smart-0b486355-8589-4884-99cb-6e3d3c6cdb3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320113746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.320113746
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.515844057
Short name T433
Test name
Test status
Simulation time 246072529 ps
CPU time 10.51 seconds
Started Jul 17 05:16:04 PM PDT 24
Finished Jul 17 05:16:22 PM PDT 24
Peak memory 225124 kb
Host smart-6798732d-8dfa-4d8f-aae8-352bc5db571f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515844057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.515844057
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3523015792
Short name T243
Test name
Test status
Simulation time 71507405 ps
CPU time 2.94 seconds
Started Jul 17 05:14:08 PM PDT 24
Finished Jul 17 05:14:11 PM PDT 24
Peak memory 222740 kb
Host smart-9616db00-fa88-4dbc-8e74-f6ca05c9b3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523015792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3523015792
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.110348289
Short name T832
Test name
Test status
Simulation time 199811022 ps
CPU time 29.8 seconds
Started Jul 17 05:14:03 PM PDT 24
Finished Jul 17 05:14:33 PM PDT 24
Peak memory 250516 kb
Host smart-f7202949-37ad-41a6-8491-ff23270b8113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110348289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.110348289
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3359243709
Short name T465
Test name
Test status
Simulation time 223937105 ps
CPU time 7.02 seconds
Started Jul 17 05:14:02 PM PDT 24
Finished Jul 17 05:14:10 PM PDT 24
Peak memory 250508 kb
Host smart-627d60ce-cfaf-4a79-86bc-e43d6fcdb17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359243709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3359243709
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2746426946
Short name T617
Test name
Test status
Simulation time 10716630504 ps
CPU time 217.87 seconds
Started Jul 17 05:14:15 PM PDT 24
Finished Jul 17 05:17:54 PM PDT 24
Peak memory 315224 kb
Host smart-7d63a154-4292-4ad6-99c8-ffa569cde167
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746426946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2746426946
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.290359902
Short name T549
Test name
Test status
Simulation time 36891308 ps
CPU time 0.92 seconds
Started Jul 17 05:14:06 PM PDT 24
Finished Jul 17 05:14:07 PM PDT 24
Peak memory 208412 kb
Host smart-613279e1-e612-45ea-9095-7776d76ed282
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290359902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.290359902
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2104924547
Short name T826
Test name
Test status
Simulation time 51296237 ps
CPU time 1.01 seconds
Started Jul 17 05:17:38 PM PDT 24
Finished Jul 17 05:17:41 PM PDT 24
Peak memory 208360 kb
Host smart-567aa46f-ccfa-4395-9579-5bec47515fbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104924547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2104924547
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3194084880
Short name T229
Test name
Test status
Simulation time 976064543 ps
CPU time 11.06 seconds
Started Jul 17 05:16:14 PM PDT 24
Finished Jul 17 05:16:29 PM PDT 24
Peak memory 225568 kb
Host smart-ab3a55f5-db2f-4e79-95f7-ecc6040725c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194084880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3194084880
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.657106285
Short name T366
Test name
Test status
Simulation time 926670565 ps
CPU time 4.85 seconds
Started Jul 17 05:14:16 PM PDT 24
Finished Jul 17 05:14:22 PM PDT 24
Peak memory 216712 kb
Host smart-06259f37-ad84-44ff-bd0b-37d607ecd0d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657106285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.657106285
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.3128043856
Short name T853
Test name
Test status
Simulation time 5996549970 ps
CPU time 48.6 seconds
Started Jul 17 05:14:15 PM PDT 24
Finished Jul 17 05:15:05 PM PDT 24
Peak memory 218404 kb
Host smart-2480f177-b27f-4b93-a9ea-1bc9ecb02918
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128043856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.3128043856
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.188742880
Short name T790
Test name
Test status
Simulation time 537074090 ps
CPU time 8.49 seconds
Started Jul 17 05:16:09 PM PDT 24
Finished Jul 17 05:16:23 PM PDT 24
Peak memory 217684 kb
Host smart-95e22e2e-f8f4-4781-92bc-0a01a96219ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188742880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.188742880
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3966084529
Short name T682
Test name
Test status
Simulation time 95312542 ps
CPU time 2.05 seconds
Started Jul 17 05:16:14 PM PDT 24
Finished Jul 17 05:16:20 PM PDT 24
Peak memory 217200 kb
Host smart-190fe310-65fb-4098-876a-4d5cd91be140
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966084529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3966084529
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.4043033634
Short name T268
Test name
Test status
Simulation time 17328768411 ps
CPU time 41.74 seconds
Started Jul 17 05:17:35 PM PDT 24
Finished Jul 17 05:18:18 PM PDT 24
Peak memory 250740 kb
Host smart-0e4b0990-305f-4a52-8ae9-836e338e7fe7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043033634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.4043033634
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.4120349048
Short name T439
Test name
Test status
Simulation time 1710006210 ps
CPU time 11.08 seconds
Started Jul 17 05:14:15 PM PDT 24
Finished Jul 17 05:14:27 PM PDT 24
Peak memory 249912 kb
Host smart-52703567-f945-4ce1-82ec-722294d03641
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120349048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.4120349048
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3749225864
Short name T340
Test name
Test status
Simulation time 355720586 ps
CPU time 6.61 seconds
Started Jul 17 05:17:35 PM PDT 24
Finished Jul 17 05:17:43 PM PDT 24
Peak memory 222328 kb
Host smart-cf6873ae-e2e1-4a6a-a4f5-69740a3c5e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749225864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3749225864
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2735812759
Short name T278
Test name
Test status
Simulation time 736646433 ps
CPU time 12.78 seconds
Started Jul 17 05:14:30 PM PDT 24
Finished Jul 17 05:14:43 PM PDT 24
Peak memory 218368 kb
Host smart-ac83820e-f939-433e-b719-635af341190b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735812759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2735812759
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1896742093
Short name T709
Test name
Test status
Simulation time 653833318 ps
CPU time 8.74 seconds
Started Jul 17 05:14:15 PM PDT 24
Finished Jul 17 05:14:25 PM PDT 24
Peak memory 225508 kb
Host smart-82ef59d8-d411-4a7e-aba0-8e5346c615b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896742093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1896742093
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3464557899
Short name T673
Test name
Test status
Simulation time 1201865583 ps
CPU time 11.33 seconds
Started Jul 17 05:14:15 PM PDT 24
Finished Jul 17 05:14:28 PM PDT 24
Peak memory 217728 kb
Host smart-a19e49d1-5e9d-4527-a675-670a8598f706
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464557899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3464557899
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.648436224
Short name T352
Test name
Test status
Simulation time 1004847799 ps
CPU time 9.19 seconds
Started Jul 17 05:14:16 PM PDT 24
Finished Jul 17 05:14:27 PM PDT 24
Peak memory 224724 kb
Host smart-0e7e1f22-b89b-4a61-9c92-9dd6ef96a69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648436224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.648436224
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2525988368
Short name T851
Test name
Test status
Simulation time 29947640 ps
CPU time 1.9 seconds
Started Jul 17 05:14:14 PM PDT 24
Finished Jul 17 05:14:16 PM PDT 24
Peak memory 217188 kb
Host smart-f9cb97f8-87d2-4b4f-b51b-2166f14acdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525988368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2525988368
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3821215975
Short name T603
Test name
Test status
Simulation time 1889652587 ps
CPU time 28.33 seconds
Started Jul 17 05:14:17 PM PDT 24
Finished Jul 17 05:14:47 PM PDT 24
Peak memory 250508 kb
Host smart-02a3e19d-84dd-4e30-928b-898a8490fe19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821215975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3821215975
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3812643122
Short name T784
Test name
Test status
Simulation time 64034291 ps
CPU time 6.07 seconds
Started Jul 17 05:14:17 PM PDT 24
Finished Jul 17 05:14:24 PM PDT 24
Peak memory 246428 kb
Host smart-147176c4-7b11-4fa2-a4ae-81d6d00b3a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812643122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3812643122
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.62000454
Short name T72
Test name
Test status
Simulation time 4466147478 ps
CPU time 38.74 seconds
Started Jul 17 05:14:14 PM PDT 24
Finished Jul 17 05:14:54 PM PDT 24
Peak memory 225628 kb
Host smart-c8b8f3c7-aa89-4f5e-b70a-fcf6300ae576
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62000454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.lc_ctrl_stress_all.62000454
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2181125246
Short name T498
Test name
Test status
Simulation time 23913862 ps
CPU time 0.91 seconds
Started Jul 17 05:15:55 PM PDT 24
Finished Jul 17 05:16:06 PM PDT 24
Peak memory 208356 kb
Host smart-a415751c-1461-4676-887b-79b53d321ec4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181125246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2181125246
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3982140794
Short name T425
Test name
Test status
Simulation time 45384754 ps
CPU time 1.22 seconds
Started Jul 17 05:16:06 PM PDT 24
Finished Jul 17 05:16:14 PM PDT 24
Peak memory 208280 kb
Host smart-9441d994-7bc6-49db-8c55-8eeb92bae809
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982140794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3982140794
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3832977262
Short name T443
Test name
Test status
Simulation time 352071966 ps
CPU time 7.03 seconds
Started Jul 17 05:14:17 PM PDT 24
Finished Jul 17 05:14:26 PM PDT 24
Peak memory 217940 kb
Host smart-8fccebfe-a8ba-44cf-92ee-5218c71ec996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832977262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3832977262
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3000785080
Short name T530
Test name
Test status
Simulation time 1568419995 ps
CPU time 3.68 seconds
Started Jul 17 05:14:17 PM PDT 24
Finished Jul 17 05:14:22 PM PDT 24
Peak memory 216760 kb
Host smart-b217abcc-6c0e-4e07-a8cc-11f0a279ce88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000785080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3000785080
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.442633046
Short name T165
Test name
Test status
Simulation time 9594262033 ps
CPU time 33.58 seconds
Started Jul 17 05:16:36 PM PDT 24
Finished Jul 17 05:17:11 PM PDT 24
Peak memory 217848 kb
Host smart-512060e7-6281-4829-a82d-a3243adda2d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442633046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er
rors.442633046
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1998642069
Short name T372
Test name
Test status
Simulation time 1382718069 ps
CPU time 7.14 seconds
Started Jul 17 05:14:15 PM PDT 24
Finished Jul 17 05:14:23 PM PDT 24
Peak memory 217716 kb
Host smart-428c1c56-0c30-4a42-b496-c3a762167ba8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998642069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1998642069
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1119110368
Short name T841
Test name
Test status
Simulation time 378207546 ps
CPU time 6.55 seconds
Started Jul 17 05:14:17 PM PDT 24
Finished Jul 17 05:14:25 PM PDT 24
Peak memory 217292 kb
Host smart-d34031f8-bcdc-43e8-9b36-16d385eea174
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119110368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1119110368
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2731238337
Short name T672
Test name
Test status
Simulation time 2353162884 ps
CPU time 71.65 seconds
Started Jul 17 05:16:36 PM PDT 24
Finished Jul 17 05:17:48 PM PDT 24
Peak memory 266724 kb
Host smart-7a16f60b-9bca-42f3-874d-68e2133ed886
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731238337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2731238337
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3240126155
Short name T581
Test name
Test status
Simulation time 380302394 ps
CPU time 17.44 seconds
Started Jul 17 05:14:16 PM PDT 24
Finished Jul 17 05:14:35 PM PDT 24
Peak memory 250440 kb
Host smart-5792434b-946a-4fd2-bdc2-4895d47f58ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240126155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3240126155
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3675814478
Short name T449
Test name
Test status
Simulation time 444029472 ps
CPU time 4.15 seconds
Started Jul 17 05:16:03 PM PDT 24
Finished Jul 17 05:16:16 PM PDT 24
Peak memory 217756 kb
Host smart-3958f94c-0b93-4ee6-b0c6-acea8b0f0cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675814478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3675814478
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.756427792
Short name T614
Test name
Test status
Simulation time 364737728 ps
CPU time 12.03 seconds
Started Jul 17 05:17:51 PM PDT 24
Finished Jul 17 05:18:08 PM PDT 24
Peak memory 217816 kb
Host smart-a0373a5f-840e-475f-a700-d17d4b0395c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756427792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.756427792
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.4073842131
Short name T394
Test name
Test status
Simulation time 259896503 ps
CPU time 10.92 seconds
Started Jul 17 05:17:51 PM PDT 24
Finished Jul 17 05:18:07 PM PDT 24
Peak memory 225468 kb
Host smart-0353d66a-0b4d-48d4-8cbe-eac1c2a04e37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073842131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.4073842131
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3748394628
Short name T329
Test name
Test status
Simulation time 8851803931 ps
CPU time 11.64 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:18:05 PM PDT 24
Peak memory 217472 kb
Host smart-2597cf6a-0b3d-4b73-b0a4-7cb49bad6dca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748394628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3748394628
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2212005045
Short name T508
Test name
Test status
Simulation time 1317786708 ps
CPU time 12.17 seconds
Started Jul 17 05:14:15 PM PDT 24
Finished Jul 17 05:14:29 PM PDT 24
Peak memory 225560 kb
Host smart-205b5653-8a9c-4788-9272-bdf5bf820337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212005045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2212005045
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.468233762
Short name T316
Test name
Test status
Simulation time 328649347 ps
CPU time 2.16 seconds
Started Jul 17 05:16:36 PM PDT 24
Finished Jul 17 05:16:39 PM PDT 24
Peak memory 216876 kb
Host smart-f20c772c-de09-45e0-8bb9-3adc2a3bc63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468233762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.468233762
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.3011616907
Short name T566
Test name
Test status
Simulation time 276753727 ps
CPU time 26.26 seconds
Started Jul 17 05:16:14 PM PDT 24
Finished Jul 17 05:16:43 PM PDT 24
Peak memory 250500 kb
Host smart-7f67e411-a960-43bf-ac1a-a93d4a887896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011616907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3011616907
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1441456422
Short name T415
Test name
Test status
Simulation time 82970120 ps
CPU time 7.03 seconds
Started Jul 17 05:16:04 PM PDT 24
Finished Jul 17 05:16:19 PM PDT 24
Peak memory 248068 kb
Host smart-324c7270-5b1f-45cb-8937-bfea2acbee16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441456422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1441456422
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2979154730
Short name T5
Test name
Test status
Simulation time 19575076261 ps
CPU time 144.76 seconds
Started Jul 17 05:14:27 PM PDT 24
Finished Jul 17 05:16:52 PM PDT 24
Peak memory 250248 kb
Host smart-4570eef3-ae53-45f2-adbd-1b4da1ed2c65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979154730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2979154730
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.228877725
Short name T870
Test name
Test status
Simulation time 13500143 ps
CPU time 1.1 seconds
Started Jul 17 05:14:14 PM PDT 24
Finished Jul 17 05:14:16 PM PDT 24
Peak memory 211344 kb
Host smart-6d017b0f-14be-4cda-aef9-c8a2f092577b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228877725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct
rl_volatile_unlock_smoke.228877725
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3403723836
Short name T437
Test name
Test status
Simulation time 40302592 ps
CPU time 0.87 seconds
Started Jul 17 05:16:13 PM PDT 24
Finished Jul 17 05:16:17 PM PDT 24
Peak memory 208336 kb
Host smart-4b42dc72-d74d-4633-836e-ef31dbfac49c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403723836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3403723836
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2452665425
Short name T664
Test name
Test status
Simulation time 266100810 ps
CPU time 8.95 seconds
Started Jul 17 05:17:44 PM PDT 24
Finished Jul 17 05:17:54 PM PDT 24
Peak memory 217744 kb
Host smart-8fb32feb-8440-40f8-b2db-33ae6d95feac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452665425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2452665425
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3503983559
Short name T468
Test name
Test status
Simulation time 12511395176 ps
CPU time 7.4 seconds
Started Jul 17 05:14:26 PM PDT 24
Finished Jul 17 05:14:34 PM PDT 24
Peak memory 217120 kb
Host smart-cd2f34b4-2046-4e97-9e40-bc5c9f49f0a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503983559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3503983559
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3091723075
Short name T252
Test name
Test status
Simulation time 23585925677 ps
CPU time 153.78 seconds
Started Jul 17 05:14:28 PM PDT 24
Finished Jul 17 05:17:02 PM PDT 24
Peak memory 219484 kb
Host smart-4d79c9ce-99ed-4cd1-8979-914a67b4a06b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091723075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3091723075
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2215130364
Short name T363
Test name
Test status
Simulation time 805694113 ps
CPU time 13.08 seconds
Started Jul 17 05:14:28 PM PDT 24
Finished Jul 17 05:14:42 PM PDT 24
Peak memory 217696 kb
Host smart-e5e74b15-acf2-49a3-811d-e07d3b479f82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215130364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2215130364
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.976348225
Short name T640
Test name
Test status
Simulation time 1852375229 ps
CPU time 13.72 seconds
Started Jul 17 05:17:27 PM PDT 24
Finished Jul 17 05:17:42 PM PDT 24
Peak memory 217112 kb
Host smart-28642554-7934-49b0-8c19-db15acf340a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976348225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
976348225
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3446966706
Short name T92
Test name
Test status
Simulation time 10620816764 ps
CPU time 57.5 seconds
Started Jul 17 05:14:27 PM PDT 24
Finished Jul 17 05:15:25 PM PDT 24
Peak memory 266848 kb
Host smart-ea42b05a-992d-44a1-94ee-49b87d98d5e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446966706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3446966706
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3000697114
Short name T286
Test name
Test status
Simulation time 4337074007 ps
CPU time 18.64 seconds
Started Jul 17 05:14:31 PM PDT 24
Finished Jul 17 05:14:50 PM PDT 24
Peak memory 250380 kb
Host smart-78506024-821e-47a0-bf55-ae0051137af1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000697114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3000697114
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.783067760
Short name T442
Test name
Test status
Simulation time 109009096 ps
CPU time 3.11 seconds
Started Jul 17 05:14:28 PM PDT 24
Finished Jul 17 05:14:32 PM PDT 24
Peak memory 217748 kb
Host smart-218a489d-017f-4aed-a89d-929daa18a015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783067760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.783067760
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2426100286
Short name T294
Test name
Test status
Simulation time 202893639 ps
CPU time 7.83 seconds
Started Jul 17 05:14:30 PM PDT 24
Finished Jul 17 05:14:39 PM PDT 24
Peak memory 225544 kb
Host smart-f73cad94-4c94-4c53-b19b-cd7919436380
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426100286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2426100286
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3422009969
Short name T678
Test name
Test status
Simulation time 1610604091 ps
CPU time 11.28 seconds
Started Jul 17 05:14:30 PM PDT 24
Finished Jul 17 05:14:41 PM PDT 24
Peak memory 225484 kb
Host smart-333a4dd9-1a02-46af-851f-0413d25b4700
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422009969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3422009969
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.4265157067
Short name T284
Test name
Test status
Simulation time 244291238 ps
CPU time 9.26 seconds
Started Jul 17 05:14:29 PM PDT 24
Finished Jul 17 05:14:39 PM PDT 24
Peak memory 225508 kb
Host smart-956e3f0a-3ed1-473d-8fc0-8fedc0326464
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265157067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
4265157067
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3134675954
Short name T739
Test name
Test status
Simulation time 205104752 ps
CPU time 9.18 seconds
Started Jul 17 05:14:25 PM PDT 24
Finished Jul 17 05:14:35 PM PDT 24
Peak memory 224732 kb
Host smart-828e20ce-eb41-442c-880c-b58329825236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134675954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3134675954
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2117901834
Short name T438
Test name
Test status
Simulation time 79165900 ps
CPU time 3.71 seconds
Started Jul 17 05:14:27 PM PDT 24
Finished Jul 17 05:14:32 PM PDT 24
Peak memory 222140 kb
Host smart-595e2b3e-3805-4fac-90f1-26826989a57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117901834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2117901834
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.19997588
Short name T314
Test name
Test status
Simulation time 1380490639 ps
CPU time 27.33 seconds
Started Jul 17 05:14:29 PM PDT 24
Finished Jul 17 05:14:57 PM PDT 24
Peak memory 250644 kb
Host smart-d306025a-44c2-475f-b971-ab0d3db2c42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19997588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.19997588
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.975450927
Short name T618
Test name
Test status
Simulation time 48141146 ps
CPU time 7.54 seconds
Started Jul 17 05:16:13 PM PDT 24
Finished Jul 17 05:16:24 PM PDT 24
Peak memory 250520 kb
Host smart-82b44e0c-ebe6-4135-9675-662c66ce889d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975450927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.975450927
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.524849186
Short name T591
Test name
Test status
Simulation time 2150704516 ps
CPU time 70.57 seconds
Started Jul 17 05:14:43 PM PDT 24
Finished Jul 17 05:15:54 PM PDT 24
Peak memory 267756 kb
Host smart-ebc12282-06ee-49de-8703-bafe414bbaa4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524849186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.524849186
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.4145263641
Short name T339
Test name
Test status
Simulation time 83790522 ps
CPU time 0.91 seconds
Started Jul 17 05:14:41 PM PDT 24
Finished Jul 17 05:14:43 PM PDT 24
Peak memory 208296 kb
Host smart-610095cf-c5eb-4e08-a0c0-c4c8e272f9cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145263641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.4145263641
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2150343289
Short name T528
Test name
Test status
Simulation time 1009424065 ps
CPU time 13.35 seconds
Started Jul 17 05:16:05 PM PDT 24
Finished Jul 17 05:16:25 PM PDT 24
Peak memory 217760 kb
Host smart-c5c6bd29-ff14-4927-b0f6-08ba4bd87462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150343289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2150343289
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2648504233
Short name T646
Test name
Test status
Simulation time 236350221 ps
CPU time 2.29 seconds
Started Jul 17 05:14:46 PM PDT 24
Finished Jul 17 05:14:49 PM PDT 24
Peak memory 217136 kb
Host smart-f0e633bb-3436-4838-ad7c-b2261c9ec554
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648504233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2648504233
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1888127086
Short name T341
Test name
Test status
Simulation time 1750005826 ps
CPU time 27.39 seconds
Started Jul 17 05:14:36 PM PDT 24
Finished Jul 17 05:15:04 PM PDT 24
Peak memory 217676 kb
Host smart-59ab4f63-5af4-4990-92fd-9b9f1de2f865
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888127086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1888127086
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3268027713
Short name T256
Test name
Test status
Simulation time 118468186 ps
CPU time 2.94 seconds
Started Jul 17 05:17:46 PM PDT 24
Finished Jul 17 05:17:50 PM PDT 24
Peak memory 217716 kb
Host smart-d58fbf28-cf5c-40c4-b254-18cc9e469161
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268027713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3268027713
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3200076553
Short name T568
Test name
Test status
Simulation time 221782888 ps
CPU time 2.36 seconds
Started Jul 17 05:14:27 PM PDT 24
Finished Jul 17 05:14:30 PM PDT 24
Peak memory 217072 kb
Host smart-66ca4c10-d3ed-4b62-95c6-affa3753c951
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200076553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.3200076553
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.602756652
Short name T166
Test name
Test status
Simulation time 2219377977 ps
CPU time 52.73 seconds
Started Jul 17 05:17:48 PM PDT 24
Finished Jul 17 05:18:43 PM PDT 24
Peak memory 280240 kb
Host smart-67f8ee36-5a67-4af3-af35-0613e0425ac4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602756652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.602756652
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.985293439
Short name T421
Test name
Test status
Simulation time 4224743507 ps
CPU time 18.56 seconds
Started Jul 17 05:14:40 PM PDT 24
Finished Jul 17 05:15:00 PM PDT 24
Peak memory 248524 kb
Host smart-1e6169de-fe5b-4ba1-91a0-a4d3cd14af0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985293439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.985293439
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2992323144
Short name T31
Test name
Test status
Simulation time 335989148 ps
CPU time 4.23 seconds
Started Jul 17 05:14:25 PM PDT 24
Finished Jul 17 05:14:30 PM PDT 24
Peak memory 217752 kb
Host smart-dab0e037-4b80-43c6-8b6c-edbb531f87ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992323144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2992323144
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.186658768
Short name T792
Test name
Test status
Simulation time 388492043 ps
CPU time 14.26 seconds
Started Jul 17 05:14:39 PM PDT 24
Finished Jul 17 05:14:55 PM PDT 24
Peak memory 218476 kb
Host smart-8922bd4c-8fca-4bde-a4aa-4ff0cc012ede
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186658768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.186658768
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2076160746
Short name T63
Test name
Test status
Simulation time 565743022 ps
CPU time 7.16 seconds
Started Jul 17 05:14:42 PM PDT 24
Finished Jul 17 05:14:50 PM PDT 24
Peak memory 225452 kb
Host smart-d8cb0f96-8c60-4527-8262-a52a2acdd1a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076160746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2076160746
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1116810609
Short name T241
Test name
Test status
Simulation time 233792794 ps
CPU time 7.12 seconds
Started Jul 17 05:14:41 PM PDT 24
Finished Jul 17 05:14:49 PM PDT 24
Peak memory 225452 kb
Host smart-71b47bea-8134-49db-bc10-aa073435497b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116810609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1116810609
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2705904404
Short name T367
Test name
Test status
Simulation time 1621789935 ps
CPU time 9.75 seconds
Started Jul 17 05:16:04 PM PDT 24
Finished Jul 17 05:16:21 PM PDT 24
Peak memory 217832 kb
Host smart-67c0b5b1-4622-43d1-b6b7-9c52bb212f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705904404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2705904404
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2909857705
Short name T456
Test name
Test status
Simulation time 90775726 ps
CPU time 2.8 seconds
Started Jul 17 05:14:28 PM PDT 24
Finished Jul 17 05:14:31 PM PDT 24
Peak memory 213904 kb
Host smart-a978db9a-d6c9-485c-b757-2af2de5d78ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909857705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2909857705
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3292697295
Short name T379
Test name
Test status
Simulation time 937679453 ps
CPU time 25.5 seconds
Started Jul 17 05:17:51 PM PDT 24
Finished Jul 17 05:18:21 PM PDT 24
Peak memory 250484 kb
Host smart-77bcd06c-9999-4071-a85f-aaab4c9c9c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292697295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3292697295
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2644394625
Short name T466
Test name
Test status
Simulation time 146946051 ps
CPU time 7.24 seconds
Started Jul 17 05:14:35 PM PDT 24
Finished Jul 17 05:14:43 PM PDT 24
Peak memory 250456 kb
Host smart-d5e3e68d-8ae7-4f46-b97d-40b983d112f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644394625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2644394625
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.497383631
Short name T225
Test name
Test status
Simulation time 33843314334 ps
CPU time 167.03 seconds
Started Jul 17 05:14:35 PM PDT 24
Finished Jul 17 05:17:23 PM PDT 24
Peak memory 269056 kb
Host smart-853f78aa-f04e-45e3-9eca-cbc707633cfb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497383631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.497383631
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.400923995
Short name T18
Test name
Test status
Simulation time 106043045157 ps
CPU time 660.44 seconds
Started Jul 17 05:16:25 PM PDT 24
Finished Jul 17 05:27:26 PM PDT 24
Peak memory 283480 kb
Host smart-5bf472d3-6411-4c55-b20e-06dca0d29c25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=400923995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.400923995
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3516743992
Short name T578
Test name
Test status
Simulation time 61776941 ps
CPU time 0.81 seconds
Started Jul 17 05:14:28 PM PDT 24
Finished Jul 17 05:14:30 PM PDT 24
Peak memory 207712 kb
Host smart-15fd8ced-dc2e-4352-b223-4ec61ab62537
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516743992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3516743992
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3097668162
Short name T281
Test name
Test status
Simulation time 19824114 ps
CPU time 1.17 seconds
Started Jul 17 05:14:38 PM PDT 24
Finished Jul 17 05:14:40 PM PDT 24
Peak memory 208636 kb
Host smart-e021cea5-1a1a-4b83-84c3-fa57033290d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097668162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3097668162
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1775769052
Short name T203
Test name
Test status
Simulation time 579674338 ps
CPU time 17.86 seconds
Started Jul 17 05:14:40 PM PDT 24
Finished Jul 17 05:14:58 PM PDT 24
Peak memory 225564 kb
Host smart-fcb7035b-0434-4b53-a176-9d6e5b67fd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775769052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1775769052
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2158023749
Short name T714
Test name
Test status
Simulation time 471354902 ps
CPU time 12.57 seconds
Started Jul 17 05:14:42 PM PDT 24
Finished Jul 17 05:14:56 PM PDT 24
Peak memory 216856 kb
Host smart-fbc0683c-f811-4331-bf13-8740afba3b00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158023749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2158023749
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2430027645
Short name T491
Test name
Test status
Simulation time 4362278660 ps
CPU time 35.37 seconds
Started Jul 17 05:14:40 PM PDT 24
Finished Jul 17 05:15:16 PM PDT 24
Peak memory 217808 kb
Host smart-e28bed9d-2f03-4222-ad99-57e2b847b501
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430027645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2430027645
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.4052764048
Short name T629
Test name
Test status
Simulation time 1676531843 ps
CPU time 7.19 seconds
Started Jul 17 05:14:38 PM PDT 24
Finished Jul 17 05:14:46 PM PDT 24
Peak memory 217012 kb
Host smart-cf517ce0-54d5-4dd8-9913-e54aa8ca4a9e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052764048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.4052764048
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.4135014886
Short name T223
Test name
Test status
Simulation time 480849663 ps
CPU time 8.31 seconds
Started Jul 17 05:16:08 PM PDT 24
Finished Jul 17 05:16:22 PM PDT 24
Peak memory 217100 kb
Host smart-eed5a0de-e4d1-4a2b-86c5-ca70683ec0f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135014886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.4135014886
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3835184015
Short name T606
Test name
Test status
Simulation time 1552855847 ps
CPU time 68.24 seconds
Started Jul 17 05:17:46 PM PDT 24
Finished Jul 17 05:18:55 PM PDT 24
Peak memory 266848 kb
Host smart-e3883cf1-9012-40d9-bddb-537982d509af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835184015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3835184015
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.333058633
Short name T254
Test name
Test status
Simulation time 2504917067 ps
CPU time 10.46 seconds
Started Jul 17 05:15:02 PM PDT 24
Finished Jul 17 05:15:13 PM PDT 24
Peak memory 250524 kb
Host smart-606b3755-3028-4c23-b1e1-d54b6cf5b686
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333058633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.333058633
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.474634905
Short name T855
Test name
Test status
Simulation time 245074152 ps
CPU time 4.17 seconds
Started Jul 17 05:14:39 PM PDT 24
Finished Jul 17 05:14:44 PM PDT 24
Peak memory 217740 kb
Host smart-cf7e1346-c470-490a-9f52-19977e252946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474634905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.474634905
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.3907425750
Short name T705
Test name
Test status
Simulation time 746540733 ps
CPU time 11.91 seconds
Started Jul 17 05:14:39 PM PDT 24
Finished Jul 17 05:14:52 PM PDT 24
Peak memory 217928 kb
Host smart-33898684-fe8a-4652-9fae-a3153f6ccd47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907425750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3907425750
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.4292701225
Short name T485
Test name
Test status
Simulation time 451641991 ps
CPU time 10.46 seconds
Started Jul 17 05:14:40 PM PDT 24
Finished Jul 17 05:14:51 PM PDT 24
Peak memory 217692 kb
Host smart-eb08052f-e115-469c-aab0-bc90202b28bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292701225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.4292701225
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3061939029
Short name T802
Test name
Test status
Simulation time 415401740 ps
CPU time 14.61 seconds
Started Jul 17 05:14:41 PM PDT 24
Finished Jul 17 05:14:57 PM PDT 24
Peak memory 217892 kb
Host smart-150a1203-b718-4689-93ca-971986c0e19d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061939029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3061939029
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3614776432
Short name T255
Test name
Test status
Simulation time 287386875 ps
CPU time 9.6 seconds
Started Jul 17 05:14:43 PM PDT 24
Finished Jul 17 05:14:53 PM PDT 24
Peak memory 224672 kb
Host smart-00bc144d-369c-480e-879e-240a3b8e7c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614776432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3614776432
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.852759278
Short name T520
Test name
Test status
Simulation time 62012511 ps
CPU time 2.78 seconds
Started Jul 17 05:14:36 PM PDT 24
Finished Jul 17 05:14:39 PM PDT 24
Peak memory 213980 kb
Host smart-c8647abd-889c-4176-bca1-f535fd7f18f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852759278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.852759278
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2462975553
Short name T205
Test name
Test status
Simulation time 714836846 ps
CPU time 18.86 seconds
Started Jul 17 05:14:41 PM PDT 24
Finished Jul 17 05:15:01 PM PDT 24
Peak memory 250468 kb
Host smart-1001e56a-52c1-41c6-9f00-a23428a8d4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462975553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2462975553
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.4105963117
Short name T807
Test name
Test status
Simulation time 103367696 ps
CPU time 6.92 seconds
Started Jul 17 05:17:48 PM PDT 24
Finished Jul 17 05:17:56 PM PDT 24
Peak memory 249840 kb
Host smart-57fbd036-bd8a-4b3d-b260-6fee3873a96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105963117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.4105963117
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.2776571950
Short name T168
Test name
Test status
Simulation time 4599289323 ps
CPU time 117.82 seconds
Started Jul 17 05:14:41 PM PDT 24
Finished Jul 17 05:16:40 PM PDT 24
Peak memory 273444 kb
Host smart-714fdb4f-76ad-4fd8-9075-eeb6898b9302
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776571950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.2776571950
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.2053910475
Short name T773
Test name
Test status
Simulation time 4217167556 ps
CPU time 80.78 seconds
Started Jul 17 05:14:39 PM PDT 24
Finished Jul 17 05:16:01 PM PDT 24
Peak memory 271132 kb
Host smart-6f0499ef-140d-4596-ba76-ad7d19e5b852
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2053910475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.2053910475
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3162330776
Short name T869
Test name
Test status
Simulation time 15788930 ps
CPU time 1.08 seconds
Started Jul 17 05:14:38 PM PDT 24
Finished Jul 17 05:14:40 PM PDT 24
Peak memory 211656 kb
Host smart-ec75f3cc-b462-4c81-a910-24cfcf384a91
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162330776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3162330776
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.65165027
Short name T733
Test name
Test status
Simulation time 13272618 ps
CPU time 0.88 seconds
Started Jul 17 05:16:11 PM PDT 24
Finished Jul 17 05:16:16 PM PDT 24
Peak memory 208164 kb
Host smart-e4848267-8028-4123-a68b-86cc73d07ba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65165027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.65165027
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.315368473
Short name T685
Test name
Test status
Simulation time 1568604878 ps
CPU time 14.7 seconds
Started Jul 17 05:16:09 PM PDT 24
Finished Jul 17 05:16:29 PM PDT 24
Peak memory 217752 kb
Host smart-cfed174e-5dfe-4a30-b29b-ceda472bbdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315368473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.315368473
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.4207627884
Short name T354
Test name
Test status
Simulation time 656660431 ps
CPU time 2.89 seconds
Started Jul 17 05:14:48 PM PDT 24
Finished Jul 17 05:14:52 PM PDT 24
Peak memory 216736 kb
Host smart-e0c59dff-f7e1-4d8d-83e9-7239e64949cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207627884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.4207627884
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3868330038
Short name T296
Test name
Test status
Simulation time 9263299276 ps
CPU time 32.73 seconds
Started Jul 17 05:17:52 PM PDT 24
Finished Jul 17 05:18:30 PM PDT 24
Peak memory 218388 kb
Host smart-90e4b193-1ee8-4624-a0eb-5111b3462246
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868330038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3868330038
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1345524887
Short name T380
Test name
Test status
Simulation time 714658856 ps
CPU time 6.36 seconds
Started Jul 17 05:16:59 PM PDT 24
Finished Jul 17 05:17:05 PM PDT 24
Peak memory 217712 kb
Host smart-7a6602fb-a51e-48dd-bb4a-dbaab68505da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345524887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1345524887
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2403266908
Short name T4
Test name
Test status
Simulation time 365811975 ps
CPU time 9.94 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:18:04 PM PDT 24
Peak memory 217096 kb
Host smart-1971f96b-9d60-4e50-b997-e8aef825c6f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403266908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2403266908
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.901050847
Short name T211
Test name
Test status
Simulation time 3350039080 ps
CPU time 43.51 seconds
Started Jul 17 05:16:12 PM PDT 24
Finished Jul 17 05:17:00 PM PDT 24
Peak memory 283272 kb
Host smart-f9c88a24-f774-4e0f-b710-b613d1c831cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901050847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.901050847
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.368272345
Short name T544
Test name
Test status
Simulation time 315890535 ps
CPU time 9.86 seconds
Started Jul 17 05:14:48 PM PDT 24
Finished Jul 17 05:15:00 PM PDT 24
Peak memory 250440 kb
Host smart-0a9e9af5-e413-417f-b442-ce49358be701
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368272345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.368272345
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1107609166
Short name T811
Test name
Test status
Simulation time 534093719 ps
CPU time 2.18 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:17:55 PM PDT 24
Peak memory 217632 kb
Host smart-dcf6dfdd-0cbe-43d5-a0a7-1c215b8f593a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107609166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1107609166
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1736624444
Short name T451
Test name
Test status
Simulation time 2579100680 ps
CPU time 18.25 seconds
Started Jul 17 05:16:08 PM PDT 24
Finished Jul 17 05:16:32 PM PDT 24
Peak memory 218472 kb
Host smart-78c3e678-b2c1-4e1b-9a7c-d05977921986
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736624444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1736624444
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1912870632
Short name T245
Test name
Test status
Simulation time 673867565 ps
CPU time 16.34 seconds
Started Jul 17 05:17:54 PM PDT 24
Finished Jul 17 05:18:17 PM PDT 24
Peak memory 225496 kb
Host smart-5badb25b-a271-4526-95a4-7d7272b87d26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912870632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1912870632
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.4003985487
Short name T573
Test name
Test status
Simulation time 1917043855 ps
CPU time 9.3 seconds
Started Jul 17 05:14:48 PM PDT 24
Finished Jul 17 05:14:58 PM PDT 24
Peak memory 217660 kb
Host smart-8f9e4e0f-a806-4a22-960e-a5f40827e9bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003985487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
4003985487
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.414670686
Short name T148
Test name
Test status
Simulation time 593096270 ps
CPU time 13.13 seconds
Started Jul 17 05:17:36 PM PDT 24
Finished Jul 17 05:17:51 PM PDT 24
Peak memory 225564 kb
Host smart-4e1e5859-6e68-4bcd-b4db-8e8f4f78ef62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414670686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.414670686
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3885725493
Short name T71
Test name
Test status
Simulation time 33952225 ps
CPU time 1.07 seconds
Started Jul 17 05:14:39 PM PDT 24
Finished Jul 17 05:14:41 PM PDT 24
Peak memory 212972 kb
Host smart-b572bb2f-2638-400a-9a09-c66f70993cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885725493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3885725493
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3680615123
Short name T320
Test name
Test status
Simulation time 292128121 ps
CPU time 30.88 seconds
Started Jul 17 05:14:38 PM PDT 24
Finished Jul 17 05:15:10 PM PDT 24
Peak memory 250516 kb
Host smart-03ee69da-f0d7-4db0-b009-0c0da18ee459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680615123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3680615123
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.605420276
Short name T220
Test name
Test status
Simulation time 105885106 ps
CPU time 7.5 seconds
Started Jul 17 05:16:05 PM PDT 24
Finished Jul 17 05:16:19 PM PDT 24
Peak memory 250420 kb
Host smart-85044d59-e038-4ccd-ba39-ee936f644fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605420276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.605420276
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2635440771
Short name T62
Test name
Test status
Simulation time 4705385388 ps
CPU time 175.71 seconds
Started Jul 17 05:17:49 PM PDT 24
Finished Jul 17 05:20:48 PM PDT 24
Peak memory 283284 kb
Host smart-9f98d4fd-c2d1-4d59-b0e3-7892235da0a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635440771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2635440771
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.462568576
Short name T639
Test name
Test status
Simulation time 24038167 ps
CPU time 0.8 seconds
Started Jul 17 05:17:45 PM PDT 24
Finished Jul 17 05:17:47 PM PDT 24
Peak memory 208372 kb
Host smart-c8f6c577-4148-40be-9974-8692eb42f854
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462568576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.462568576
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.234210805
Short name T817
Test name
Test status
Simulation time 55451219 ps
CPU time 0.85 seconds
Started Jul 17 05:14:58 PM PDT 24
Finished Jul 17 05:15:00 PM PDT 24
Peak memory 208192 kb
Host smart-e572f6d7-b2ca-4987-b973-a66c22767a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234210805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.234210805
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.576980853
Short name T413
Test name
Test status
Simulation time 255952096 ps
CPU time 11.79 seconds
Started Jul 17 05:14:54 PM PDT 24
Finished Jul 17 05:15:07 PM PDT 24
Peak memory 217764 kb
Host smart-d5bfe056-3909-49e2-8ccb-ae5582a81312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576980853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.576980853
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.702305122
Short name T494
Test name
Test status
Simulation time 148711830 ps
CPU time 2.53 seconds
Started Jul 17 05:14:47 PM PDT 24
Finished Jul 17 05:14:51 PM PDT 24
Peak memory 216680 kb
Host smart-c835f4b6-34de-4f88-8f50-f6c8b8338ca7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702305122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.702305122
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3617449271
Short name T308
Test name
Test status
Simulation time 4012023656 ps
CPU time 42.09 seconds
Started Jul 17 05:14:48 PM PDT 24
Finished Jul 17 05:15:31 PM PDT 24
Peak memory 218356 kb
Host smart-8a3f0a50-6771-44bb-a62f-879bb16a0b36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617449271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3617449271
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.386176257
Short name T675
Test name
Test status
Simulation time 171127463 ps
CPU time 6.15 seconds
Started Jul 17 05:14:52 PM PDT 24
Finished Jul 17 05:14:59 PM PDT 24
Peak memory 221424 kb
Host smart-d1909109-8ef1-46af-b17d-ec8d62ca1228
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386176257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.386176257
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3575326785
Short name T76
Test name
Test status
Simulation time 183207766 ps
CPU time 4.05 seconds
Started Jul 17 05:14:49 PM PDT 24
Finished Jul 17 05:14:54 PM PDT 24
Peak memory 217112 kb
Host smart-980ecc0b-f487-4695-810b-93c6511a6757
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575326785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3575326785
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.400980326
Short name T517
Test name
Test status
Simulation time 1990748527 ps
CPU time 71.85 seconds
Started Jul 17 05:17:35 PM PDT 24
Finished Jul 17 05:18:48 PM PDT 24
Peak memory 283220 kb
Host smart-89b47f61-81bc-4b29-b832-61756522c823
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400980326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.400980326
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.444239993
Short name T626
Test name
Test status
Simulation time 678157869 ps
CPU time 23.66 seconds
Started Jul 17 05:14:48 PM PDT 24
Finished Jul 17 05:15:13 PM PDT 24
Peak memory 245756 kb
Host smart-d6f02d90-fc1d-46d0-b53b-490cdc4caef2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444239993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.444239993
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2495670017
Short name T757
Test name
Test status
Simulation time 368716688 ps
CPU time 3.48 seconds
Started Jul 17 05:15:33 PM PDT 24
Finished Jul 17 05:15:38 PM PDT 24
Peak memory 222128 kb
Host smart-f63ece30-dd9e-479c-a06d-907bfb4fa03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495670017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2495670017
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3390464374
Short name T730
Test name
Test status
Simulation time 493502495 ps
CPU time 18.25 seconds
Started Jul 17 05:14:48 PM PDT 24
Finished Jul 17 05:15:08 PM PDT 24
Peak memory 225508 kb
Host smart-03cfb5f3-b8f0-4423-b489-d5d28529b056
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390464374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3390464374
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2605037104
Short name T279
Test name
Test status
Simulation time 719313317 ps
CPU time 6.18 seconds
Started Jul 17 05:14:50 PM PDT 24
Finished Jul 17 05:14:57 PM PDT 24
Peak memory 217896 kb
Host smart-716115a6-01b8-42bd-a46a-e7f54f610521
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605037104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2605037104
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.4196906733
Short name T61
Test name
Test status
Simulation time 268579907 ps
CPU time 7.81 seconds
Started Jul 17 05:17:48 PM PDT 24
Finished Jul 17 05:17:57 PM PDT 24
Peak memory 224324 kb
Host smart-7cd77cad-0791-4526-a7a9-903bcc402559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196906733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.4196906733
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2848367445
Short name T429
Test name
Test status
Simulation time 6116491282 ps
CPU time 29.99 seconds
Started Jul 17 05:15:33 PM PDT 24
Finished Jul 17 05:16:05 PM PDT 24
Peak memory 250552 kb
Host smart-535d9d59-d5b1-48dd-86d5-5420cba24bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848367445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2848367445
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.4223791648
Short name T348
Test name
Test status
Simulation time 132334360 ps
CPU time 6.42 seconds
Started Jul 17 05:16:24 PM PDT 24
Finished Jul 17 05:16:31 PM PDT 24
Peak memory 250032 kb
Host smart-87410127-b61b-483a-a02f-37d20f632c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223791648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.4223791648
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3730131257
Short name T655
Test name
Test status
Simulation time 9820788865 ps
CPU time 168.91 seconds
Started Jul 17 05:14:55 PM PDT 24
Finished Jul 17 05:17:44 PM PDT 24
Peak memory 275376 kb
Host smart-6fb65dec-ede9-48e0-a425-bb012f697087
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730131257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3730131257
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3422794947
Short name T208
Test name
Test status
Simulation time 61220454 ps
CPU time 0.96 seconds
Started Jul 17 05:14:52 PM PDT 24
Finished Jul 17 05:14:53 PM PDT 24
Peak memory 211324 kb
Host smart-96032920-de0e-4784-b205-50a04a30b57f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422794947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3422794947
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3541090077
Short name T396
Test name
Test status
Simulation time 34006699 ps
CPU time 1.07 seconds
Started Jul 17 05:17:37 PM PDT 24
Finished Jul 17 05:17:40 PM PDT 24
Peak memory 208360 kb
Host smart-3137cf04-1b73-44f2-86d8-25646214b962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541090077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3541090077
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.1163233987
Short name T599
Test name
Test status
Simulation time 352204168 ps
CPU time 12.26 seconds
Started Jul 17 05:16:39 PM PDT 24
Finished Jul 17 05:16:53 PM PDT 24
Peak memory 217728 kb
Host smart-182e9089-0be8-4d11-bc0d-db6ee903353a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163233987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1163233987
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3662561379
Short name T24
Test name
Test status
Simulation time 486703255 ps
CPU time 3.89 seconds
Started Jul 17 05:16:39 PM PDT 24
Finished Jul 17 05:16:45 PM PDT 24
Peak memory 217144 kb
Host smart-f9404057-500d-4dd9-b30f-3ac4be8ef598
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662561379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3662561379
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.936250107
Short name T158
Test name
Test status
Simulation time 4462787324 ps
CPU time 91.84 seconds
Started Jul 17 05:14:50 PM PDT 24
Finished Jul 17 05:16:23 PM PDT 24
Peak memory 218392 kb
Host smart-e687938d-10e4-4a19-8035-b64b65579c16
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936250107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.936250107
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.938099560
Short name T788
Test name
Test status
Simulation time 747732302 ps
CPU time 9.04 seconds
Started Jul 17 05:14:51 PM PDT 24
Finished Jul 17 05:15:01 PM PDT 24
Peak memory 223564 kb
Host smart-e32827b0-4131-4ef5-8df7-99d71a23fbe8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938099560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.938099560
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1600123181
Short name T532
Test name
Test status
Simulation time 429369891 ps
CPU time 11.86 seconds
Started Jul 17 05:17:52 PM PDT 24
Finished Jul 17 05:18:10 PM PDT 24
Peak memory 217060 kb
Host smart-4b121247-ba6a-4610-a901-91519e013074
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600123181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1600123181
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1971975272
Short name T233
Test name
Test status
Simulation time 3005876526 ps
CPU time 38.42 seconds
Started Jul 17 05:17:36 PM PDT 24
Finished Jul 17 05:18:16 PM PDT 24
Peak memory 267456 kb
Host smart-0ec9ac14-2663-42ef-a59d-276fa2fbc276
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971975272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1971975272
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.4210558878
Short name T357
Test name
Test status
Simulation time 492583399 ps
CPU time 20.87 seconds
Started Jul 17 05:16:13 PM PDT 24
Finished Jul 17 05:16:37 PM PDT 24
Peak memory 250356 kb
Host smart-05441d9d-ed67-4cdc-9ae0-61b07ebab664
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210558878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.4210558878
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2206049311
Short name T417
Test name
Test status
Simulation time 629798618 ps
CPU time 3.15 seconds
Started Jul 17 05:14:58 PM PDT 24
Finished Jul 17 05:15:03 PM PDT 24
Peak memory 217756 kb
Host smart-f37af672-68d2-4f8e-a0b8-ca2ea137ff62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206049311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2206049311
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2248794907
Short name T431
Test name
Test status
Simulation time 814871310 ps
CPU time 13.09 seconds
Started Jul 17 05:14:50 PM PDT 24
Finished Jul 17 05:15:04 PM PDT 24
Peak memory 217836 kb
Host smart-13ef1d2a-07ec-4fd9-8a3c-3bbfa556b2c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248794907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2248794907
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3547502944
Short name T371
Test name
Test status
Simulation time 3285840757 ps
CPU time 18.27 seconds
Started Jul 17 05:14:49 PM PDT 24
Finished Jul 17 05:15:09 PM PDT 24
Peak memory 225564 kb
Host smart-a9213339-d93f-498b-bcb9-1bd6694381c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547502944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3547502944
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.885233087
Short name T649
Test name
Test status
Simulation time 423997794 ps
CPU time 6.34 seconds
Started Jul 17 05:17:48 PM PDT 24
Finished Jul 17 05:17:56 PM PDT 24
Peak memory 217680 kb
Host smart-9543d759-8474-4430-943d-52dc38938704
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885233087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.885233087
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3495542233
Short name T53
Test name
Test status
Simulation time 784859495 ps
CPU time 9.16 seconds
Started Jul 17 05:14:52 PM PDT 24
Finished Jul 17 05:15:02 PM PDT 24
Peak memory 225560 kb
Host smart-c7207841-5350-4396-9357-9864b6ba50f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495542233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3495542233
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2763839045
Short name T216
Test name
Test status
Simulation time 263839800 ps
CPU time 2.2 seconds
Started Jul 17 05:14:50 PM PDT 24
Finished Jul 17 05:14:54 PM PDT 24
Peak memory 213632 kb
Host smart-f50b0af6-8cf1-40da-9480-7f61c9654835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763839045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2763839045
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2643216540
Short name T541
Test name
Test status
Simulation time 630143998 ps
CPU time 22.32 seconds
Started Jul 17 05:14:51 PM PDT 24
Finished Jul 17 05:15:14 PM PDT 24
Peak memory 246956 kb
Host smart-437836fe-28ca-41b8-8f86-43cc0aee2201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643216540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2643216540
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3672736132
Short name T557
Test name
Test status
Simulation time 64208736 ps
CPU time 3.79 seconds
Started Jul 17 05:14:47 PM PDT 24
Finished Jul 17 05:14:52 PM PDT 24
Peak memory 222224 kb
Host smart-8e4e3d65-c841-4c25-8dbb-10599a46dd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672736132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3672736132
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.38700493
Short name T786
Test name
Test status
Simulation time 3069643045 ps
CPU time 54.39 seconds
Started Jul 17 05:16:13 PM PDT 24
Finished Jul 17 05:17:11 PM PDT 24
Peak memory 250400 kb
Host smart-5328f113-f95f-4a90-8d04-a98ab14103a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38700493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.lc_ctrl_stress_all.38700493
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.3347596393
Short name T276
Test name
Test status
Simulation time 15589806174 ps
CPU time 248.32 seconds
Started Jul 17 05:17:52 PM PDT 24
Finished Jul 17 05:22:06 PM PDT 24
Peak memory 267144 kb
Host smart-32b197b3-7127-475b-a804-5e61c7ab2be4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3347596393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.3347596393
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1607528382
Short name T43
Test name
Test status
Simulation time 19932479 ps
CPU time 0.85 seconds
Started Jul 17 05:17:53 PM PDT 24
Finished Jul 17 05:18:01 PM PDT 24
Peak memory 208608 kb
Host smart-0d9e7ab2-c38a-4bdd-8309-c03d0f445e71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607528382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.1607528382
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1984407658
Short name T774
Test name
Test status
Simulation time 18467598 ps
CPU time 1.17 seconds
Started Jul 17 05:17:00 PM PDT 24
Finished Jul 17 05:17:01 PM PDT 24
Peak memory 208512 kb
Host smart-b9690bcd-6a15-4be6-a56a-b7e28ebcfa14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984407658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1984407658
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.153992744
Short name T150
Test name
Test status
Simulation time 1338623092 ps
CPU time 13.71 seconds
Started Jul 17 05:14:49 PM PDT 24
Finished Jul 17 05:15:04 PM PDT 24
Peak memory 217744 kb
Host smart-a5059b2a-e32a-4e4e-bdba-1b559c4c08cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153992744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.153992744
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1120079246
Short name T723
Test name
Test status
Simulation time 3381183301 ps
CPU time 6.17 seconds
Started Jul 17 05:15:05 PM PDT 24
Finished Jul 17 05:15:12 PM PDT 24
Peak memory 217300 kb
Host smart-602744c7-6def-42dd-94db-ccfbd2bf94a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120079246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1120079246
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3830789972
Short name T270
Test name
Test status
Simulation time 1801869993 ps
CPU time 26.89 seconds
Started Jul 17 05:16:47 PM PDT 24
Finished Jul 17 05:17:15 PM PDT 24
Peak memory 217668 kb
Host smart-f4199974-7e80-4fca-8f0e-d88d4b5fcd3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830789972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3830789972
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.55272226
Short name T206
Test name
Test status
Simulation time 48940167 ps
CPU time 1.96 seconds
Started Jul 17 05:15:02 PM PDT 24
Finished Jul 17 05:15:04 PM PDT 24
Peak memory 220960 kb
Host smart-e3fb27ad-3d42-4371-ac74-3ea105bb01fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55272226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_
prog_failure.55272226
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1453986752
Short name T534
Test name
Test status
Simulation time 967132929 ps
CPU time 8.22 seconds
Started Jul 17 05:17:36 PM PDT 24
Finished Jul 17 05:17:45 PM PDT 24
Peak memory 217124 kb
Host smart-f3958af0-6f89-4bd8-a638-e00940f2c40a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453986752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1453986752
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2774491695
Short name T303
Test name
Test status
Simulation time 1380611083 ps
CPU time 60.64 seconds
Started Jul 17 05:14:58 PM PDT 24
Finished Jul 17 05:15:59 PM PDT 24
Peak memory 266828 kb
Host smart-796ca96a-c1b0-42d1-9df3-1c7c72b7cbf0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774491695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2774491695
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3928784187
Short name T390
Test name
Test status
Simulation time 424978393 ps
CPU time 17.38 seconds
Started Jul 17 05:14:58 PM PDT 24
Finished Jul 17 05:15:16 PM PDT 24
Peak memory 250032 kb
Host smart-6b91dedc-9421-414e-9fe2-4aab0a399134
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928784187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.3928784187
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.224899599
Short name T322
Test name
Test status
Simulation time 263781663 ps
CPU time 3.26 seconds
Started Jul 17 05:14:50 PM PDT 24
Finished Jul 17 05:14:54 PM PDT 24
Peak memory 217732 kb
Host smart-3eb4d319-e5d4-4e6a-bb3a-0cd3382cf483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224899599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.224899599
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.449003710
Short name T156
Test name
Test status
Simulation time 1821633446 ps
CPU time 19.19 seconds
Started Jul 17 05:15:00 PM PDT 24
Finished Jul 17 05:15:20 PM PDT 24
Peak memory 225524 kb
Host smart-938716b0-8643-4e58-ad91-9c82716ae2dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449003710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.449003710
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1131705389
Short name T785
Test name
Test status
Simulation time 2587613108 ps
CPU time 24.04 seconds
Started Jul 17 05:15:02 PM PDT 24
Finished Jul 17 05:15:27 PM PDT 24
Peak memory 225480 kb
Host smart-0098099e-8556-46b8-ae22-28b13c2831c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131705389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1131705389
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1620272683
Short name T857
Test name
Test status
Simulation time 1104018803 ps
CPU time 7.47 seconds
Started Jul 17 05:15:02 PM PDT 24
Finished Jul 17 05:15:11 PM PDT 24
Peak memory 225684 kb
Host smart-50d661ce-7571-4ccc-8a81-0a268da8be4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620272683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1620272683
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1556633675
Short name T479
Test name
Test status
Simulation time 358527184 ps
CPU time 10.55 seconds
Started Jul 17 05:17:52 PM PDT 24
Finished Jul 17 05:18:09 PM PDT 24
Peak memory 225040 kb
Host smart-e14dedc6-d81f-42a1-b4a2-abab74f3b17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556633675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1556633675
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2457110724
Short name T383
Test name
Test status
Simulation time 291654038 ps
CPU time 3.7 seconds
Started Jul 17 05:14:58 PM PDT 24
Finished Jul 17 05:15:03 PM PDT 24
Peak memory 217184 kb
Host smart-b98d3fda-ca06-43ed-a0f8-6eabfc3c1d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457110724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2457110724
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.736824934
Short name T547
Test name
Test status
Simulation time 414122422 ps
CPU time 20.57 seconds
Started Jul 17 05:14:58 PM PDT 24
Finished Jul 17 05:15:20 PM PDT 24
Peak memory 250496 kb
Host smart-697143c4-b1eb-4190-929c-ad139335140d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736824934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.736824934
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.4167278564
Short name T275
Test name
Test status
Simulation time 358081469 ps
CPU time 4.41 seconds
Started Jul 17 05:17:52 PM PDT 24
Finished Jul 17 05:18:01 PM PDT 24
Peak memory 225500 kb
Host smart-1594f1e6-9487-4187-9079-287ee787f679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167278564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.4167278564
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.3834027077
Short name T689
Test name
Test status
Simulation time 69143115995 ps
CPU time 191.78 seconds
Started Jul 17 05:14:59 PM PDT 24
Finished Jul 17 05:18:12 PM PDT 24
Peak memory 272800 kb
Host smart-ee24930d-af34-4e5f-898d-9de346e28dfa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834027077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.3834027077
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3220809658
Short name T686
Test name
Test status
Simulation time 32140056 ps
CPU time 0.94 seconds
Started Jul 17 05:17:22 PM PDT 24
Finished Jul 17 05:17:24 PM PDT 24
Peak memory 212352 kb
Host smart-24699a7e-bf3d-4232-9020-59f86b83df92
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220809658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3220809658
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1845277807
Short name T783
Test name
Test status
Simulation time 52087956 ps
CPU time 0.83 seconds
Started Jul 17 05:13:28 PM PDT 24
Finished Jul 17 05:13:31 PM PDT 24
Peak memory 208312 kb
Host smart-7c04bf5f-e677-4516-8da9-de1221372958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845277807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1845277807
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3621542042
Short name T226
Test name
Test status
Simulation time 335633424 ps
CPU time 15.72 seconds
Started Jul 17 05:15:42 PM PDT 24
Finished Jul 17 05:16:01 PM PDT 24
Peak memory 225496 kb
Host smart-44633aa1-9339-4762-8f75-c9e36e360439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621542042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3621542042
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1770727135
Short name T753
Test name
Test status
Simulation time 366918089 ps
CPU time 5.48 seconds
Started Jul 17 05:17:34 PM PDT 24
Finished Jul 17 05:17:40 PM PDT 24
Peak memory 217216 kb
Host smart-e8e87748-d5bb-474a-bfee-ffc656b68d55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770727135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1770727135
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.3553024187
Short name T572
Test name
Test status
Simulation time 16500113822 ps
CPU time 31.59 seconds
Started Jul 17 05:13:18 PM PDT 24
Finished Jul 17 05:13:50 PM PDT 24
Peak memory 218180 kb
Host smart-0054d71c-3bf9-486f-804a-35943fd7a464
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553024187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.3553024187
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1360505561
Short name T343
Test name
Test status
Simulation time 385553243 ps
CPU time 3.92 seconds
Started Jul 17 05:13:16 PM PDT 24
Finished Jul 17 05:13:21 PM PDT 24
Peak memory 217204 kb
Host smart-7b35daa5-fd48-43ca-abf7-fdeb7839a75c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360505561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
360505561
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2135646257
Short name T147
Test name
Test status
Simulation time 1777131988 ps
CPU time 5.95 seconds
Started Jul 17 05:13:18 PM PDT 24
Finished Jul 17 05:13:25 PM PDT 24
Peak memory 223512 kb
Host smart-2ffda87e-a8a9-4fb7-ae58-6d928eb33a43
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135646257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2135646257
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2700214519
Short name T645
Test name
Test status
Simulation time 5923432509 ps
CPU time 21.45 seconds
Started Jul 17 05:17:24 PM PDT 24
Finished Jul 17 05:17:46 PM PDT 24
Peak memory 217168 kb
Host smart-5cca8b5d-fb96-457c-9448-f43ccd30672f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700214519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2700214519
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2645733197
Short name T70
Test name
Test status
Simulation time 355229719 ps
CPU time 4.3 seconds
Started Jul 17 05:13:15 PM PDT 24
Finished Jul 17 05:13:20 PM PDT 24
Peak memory 217124 kb
Host smart-f00d0ef5-8655-4873-86bd-7caf20c8dd3a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645733197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2645733197
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1858378828
Short name T516
Test name
Test status
Simulation time 4782359106 ps
CPU time 54.61 seconds
Started Jul 17 05:13:14 PM PDT 24
Finished Jul 17 05:14:10 PM PDT 24
Peak memory 250512 kb
Host smart-9c6a0e98-9524-4a32-9cd2-36252134b6b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858378828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1858378828
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.826341032
Short name T355
Test name
Test status
Simulation time 852899521 ps
CPU time 10.46 seconds
Started Jul 17 05:13:16 PM PDT 24
Finished Jul 17 05:13:27 PM PDT 24
Peak memory 249696 kb
Host smart-15174ab2-3999-4f96-a05e-b5cf836ff49b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826341032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.826341032
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3783591848
Short name T576
Test name
Test status
Simulation time 43492099 ps
CPU time 1.62 seconds
Started Jul 17 05:13:15 PM PDT 24
Finished Jul 17 05:13:18 PM PDT 24
Peak memory 217732 kb
Host smart-3d71105b-04af-4046-9fa4-78194f052a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783591848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3783591848
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1772834912
Short name T83
Test name
Test status
Simulation time 267567416 ps
CPU time 7.22 seconds
Started Jul 17 05:13:15 PM PDT 24
Finished Jul 17 05:13:24 PM PDT 24
Peak memory 217128 kb
Host smart-4d8fc9c7-f701-48a3-86d0-42d6c27a1a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772834912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1772834912
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3867720675
Short name T87
Test name
Test status
Simulation time 112679308 ps
CPU time 21.8 seconds
Started Jul 17 05:13:26 PM PDT 24
Finished Jul 17 05:13:50 PM PDT 24
Peak memory 281828 kb
Host smart-cf86c113-a729-4fc4-9748-240317904855
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867720675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3867720675
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.297576329
Short name T819
Test name
Test status
Simulation time 459003288 ps
CPU time 10.77 seconds
Started Jul 17 05:13:29 PM PDT 24
Finished Jul 17 05:13:41 PM PDT 24
Peak memory 217700 kb
Host smart-4d1d386b-dd4a-492c-a1ce-5bf3a35e2f7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297576329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig
est.297576329
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3789748084
Short name T586
Test name
Test status
Simulation time 301437818 ps
CPU time 10.72 seconds
Started Jul 17 05:13:18 PM PDT 24
Finished Jul 17 05:13:30 PM PDT 24
Peak memory 217704 kb
Host smart-d3f61414-5f2f-42db-acba-294311cda881
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789748084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
789748084
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.4210237968
Short name T78
Test name
Test status
Simulation time 34325970 ps
CPU time 1.57 seconds
Started Jul 17 05:13:16 PM PDT 24
Finished Jul 17 05:13:19 PM PDT 24
Peak memory 213276 kb
Host smart-7aaab8ea-5b35-478c-988d-b3c8261a2d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210237968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.4210237968
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3298369492
Short name T827
Test name
Test status
Simulation time 867541722 ps
CPU time 31.77 seconds
Started Jul 17 05:13:18 PM PDT 24
Finished Jul 17 05:13:51 PM PDT 24
Peak memory 250520 kb
Host smart-94eb98de-a27d-4eb1-9afc-55c042fb5b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298369492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3298369492
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3217982935
Short name T144
Test name
Test status
Simulation time 213200815 ps
CPU time 7.32 seconds
Started Jul 17 05:13:17 PM PDT 24
Finished Jul 17 05:13:26 PM PDT 24
Peak memory 250436 kb
Host smart-d76c0482-ba52-4648-88fb-5b8235a36d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217982935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3217982935
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.3101235759
Short name T540
Test name
Test status
Simulation time 20841311247 ps
CPU time 359.1 seconds
Started Jul 17 05:16:03 PM PDT 24
Finished Jul 17 05:22:10 PM PDT 24
Peak memory 316068 kb
Host smart-4fe61f19-bed2-45b7-8e7e-4708ca832beb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101235759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.3101235759
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2633351884
Short name T293
Test name
Test status
Simulation time 27825480 ps
CPU time 0.91 seconds
Started Jul 17 05:16:01 PM PDT 24
Finished Jul 17 05:16:11 PM PDT 24
Peak memory 208384 kb
Host smart-4ae20bbb-b497-4c65-869e-cfa819e3444f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633351884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2633351884
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1273683307
Short name T336
Test name
Test status
Simulation time 71365872 ps
CPU time 1.22 seconds
Started Jul 17 05:15:01 PM PDT 24
Finished Jul 17 05:15:03 PM PDT 24
Peak memory 208616 kb
Host smart-0d8b803f-25dd-4f6a-9671-ab1ad496ed1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273683307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1273683307
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3007354732
Short name T373
Test name
Test status
Simulation time 4188453895 ps
CPU time 16.97 seconds
Started Jul 17 05:15:02 PM PDT 24
Finished Jul 17 05:15:20 PM PDT 24
Peak memory 225540 kb
Host smart-8b375a99-f47c-4881-a475-9875053a7bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007354732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3007354732
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.582927420
Short name T710
Test name
Test status
Simulation time 846001959 ps
CPU time 5.75 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:17:59 PM PDT 24
Peak memory 217228 kb
Host smart-e21f6954-25f6-484d-9497-f9a61d4072db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582927420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.582927420
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1983952671
Short name T65
Test name
Test status
Simulation time 156671635 ps
CPU time 2.96 seconds
Started Jul 17 05:15:02 PM PDT 24
Finished Jul 17 05:15:06 PM PDT 24
Peak memory 221756 kb
Host smart-7ae1a0a3-cf08-48b6-9ea5-bad60b7e1c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983952671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1983952671
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2932878146
Short name T595
Test name
Test status
Simulation time 2089120707 ps
CPU time 10.44 seconds
Started Jul 17 05:17:02 PM PDT 24
Finished Jul 17 05:17:14 PM PDT 24
Peak memory 225516 kb
Host smart-1dd99d09-be78-447c-a16c-bc53236e3253
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932878146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2932878146
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3544854883
Short name T309
Test name
Test status
Simulation time 335868720 ps
CPU time 12.87 seconds
Started Jul 17 05:16:13 PM PDT 24
Finished Jul 17 05:16:29 PM PDT 24
Peak memory 225500 kb
Host smart-64024b09-5917-4133-b2cb-7033bc627c0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544854883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3544854883
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3298771638
Short name T580
Test name
Test status
Simulation time 305653439 ps
CPU time 10.16 seconds
Started Jul 17 05:15:00 PM PDT 24
Finished Jul 17 05:15:11 PM PDT 24
Peak memory 217712 kb
Host smart-46f26071-fe4c-4cbb-b21e-5ea6cc50c954
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298771638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3298771638
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3387894391
Short name T602
Test name
Test status
Simulation time 377326689 ps
CPU time 13.59 seconds
Started Jul 17 05:15:03 PM PDT 24
Finished Jul 17 05:15:18 PM PDT 24
Peak memory 217788 kb
Host smart-510fcdc7-78d5-43a2-bce9-e024ea7eecab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387894391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3387894391
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1922066441
Short name T803
Test name
Test status
Simulation time 20487888 ps
CPU time 1.25 seconds
Started Jul 17 05:15:05 PM PDT 24
Finished Jul 17 05:15:07 PM PDT 24
Peak memory 213024 kb
Host smart-76adb50b-8438-42e1-ab3d-fb85da6d551f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922066441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1922066441
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3032296712
Short name T850
Test name
Test status
Simulation time 181049204 ps
CPU time 18.32 seconds
Started Jul 17 05:17:36 PM PDT 24
Finished Jul 17 05:17:56 PM PDT 24
Peak memory 250512 kb
Host smart-2598129a-2ad5-46b9-87b1-7724f2bb2a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032296712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3032296712
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1035022588
Short name T32
Test name
Test status
Simulation time 46763472 ps
CPU time 6.61 seconds
Started Jul 17 05:15:00 PM PDT 24
Finished Jul 17 05:15:07 PM PDT 24
Peak memory 250016 kb
Host smart-56b88e9c-73d9-4760-81ba-40c4e3b32b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035022588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1035022588
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2732174316
Short name T273
Test name
Test status
Simulation time 2819119255 ps
CPU time 64.01 seconds
Started Jul 17 05:16:46 PM PDT 24
Finished Jul 17 05:17:51 PM PDT 24
Peak memory 272524 kb
Host smart-ca22229b-804e-4197-a1f8-d05f2e89091e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732174316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2732174316
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.2463745754
Short name T133
Test name
Test status
Simulation time 120806204430 ps
CPU time 653.67 seconds
Started Jul 17 05:15:02 PM PDT 24
Finished Jul 17 05:25:58 PM PDT 24
Peak memory 291676 kb
Host smart-0318a73d-2c7f-4e85-b970-0b157b31e534
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2463745754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.2463745754
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3352181095
Short name T321
Test name
Test status
Simulation time 26444639 ps
CPU time 1.22 seconds
Started Jul 17 05:15:02 PM PDT 24
Finished Jul 17 05:15:05 PM PDT 24
Peak memory 217364 kb
Host smart-c472bbb3-072d-45ac-8654-075621a118ef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352181095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.3352181095
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1949750093
Short name T615
Test name
Test status
Simulation time 419675958 ps
CPU time 10.15 seconds
Started Jul 17 05:15:02 PM PDT 24
Finished Jul 17 05:15:13 PM PDT 24
Peak memory 217760 kb
Host smart-87dd1979-9558-4560-9beb-22e4a89a8aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949750093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1949750093
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3066635240
Short name T499
Test name
Test status
Simulation time 1356484079 ps
CPU time 5.51 seconds
Started Jul 17 05:15:02 PM PDT 24
Finished Jul 17 05:15:09 PM PDT 24
Peak memory 216908 kb
Host smart-0967c253-d781-41ff-a7f3-284f1529ffec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066635240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3066635240
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3361234093
Short name T204
Test name
Test status
Simulation time 281456648 ps
CPU time 2.66 seconds
Started Jul 17 05:15:11 PM PDT 24
Finished Jul 17 05:15:14 PM PDT 24
Peak memory 217676 kb
Host smart-73dc0ef5-aa44-441a-96ee-aaa37b8e727f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361234093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3361234093
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1865483321
Short name T246
Test name
Test status
Simulation time 254781992 ps
CPU time 10.7 seconds
Started Jul 17 05:15:03 PM PDT 24
Finished Jul 17 05:15:15 PM PDT 24
Peak memory 225440 kb
Host smart-cdf5e0d5-9672-43b4-9cad-ec0c840503f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865483321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1865483321
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.449303805
Short name T464
Test name
Test status
Simulation time 372724533 ps
CPU time 12.45 seconds
Started Jul 17 05:15:03 PM PDT 24
Finished Jul 17 05:15:17 PM PDT 24
Peak memory 217876 kb
Host smart-f9745586-c00b-4ce9-8a3a-2806a8f6171e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449303805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.449303805
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1395326868
Short name T60
Test name
Test status
Simulation time 1285501773 ps
CPU time 12.15 seconds
Started Jul 17 05:14:59 PM PDT 24
Finished Jul 17 05:15:12 PM PDT 24
Peak memory 225424 kb
Host smart-0fa96d99-2c60-4318-897d-3dc93f8eaeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395326868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1395326868
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.2365641070
Short name T395
Test name
Test status
Simulation time 72150485 ps
CPU time 1.95 seconds
Started Jul 17 05:15:03 PM PDT 24
Finished Jul 17 05:15:06 PM PDT 24
Peak memory 213452 kb
Host smart-9df9076f-c4bc-47c5-b3e6-7036c03175a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365641070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2365641070
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2388891513
Short name T447
Test name
Test status
Simulation time 233147853 ps
CPU time 28.4 seconds
Started Jul 17 05:17:48 PM PDT 24
Finished Jul 17 05:18:19 PM PDT 24
Peak memory 245592 kb
Host smart-62d3e023-0986-4a27-ac01-6c9612a9e983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388891513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2388891513
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.688682527
Short name T632
Test name
Test status
Simulation time 204678174 ps
CPU time 7.7 seconds
Started Jul 17 05:15:02 PM PDT 24
Finished Jul 17 05:15:11 PM PDT 24
Peak memory 250460 kb
Host smart-af1e5e9b-0e18-434c-9c35-24cf1ab2818f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688682527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.688682527
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2786651904
Short name T690
Test name
Test status
Simulation time 10626915527 ps
CPU time 20.1 seconds
Started Jul 17 05:15:00 PM PDT 24
Finished Jul 17 05:15:21 PM PDT 24
Peak memory 225620 kb
Host smart-96de2a60-14f9-4348-8c69-9e493f4054b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786651904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2786651904
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.2989288314
Short name T134
Test name
Test status
Simulation time 566999849782 ps
CPU time 816.27 seconds
Started Jul 17 05:15:03 PM PDT 24
Finished Jul 17 05:28:41 PM PDT 24
Peak memory 447272 kb
Host smart-2b56a120-a863-4168-a4a8-41306cb57d29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2989288314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.2989288314
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.694159950
Short name T760
Test name
Test status
Simulation time 11255001 ps
CPU time 0.83 seconds
Started Jul 17 05:15:01 PM PDT 24
Finished Jul 17 05:15:03 PM PDT 24
Peak memory 208304 kb
Host smart-52c482e3-4672-4e86-a76c-76648d5668f4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694159950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.694159950
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.3388341427
Short name T548
Test name
Test status
Simulation time 212777714 ps
CPU time 1.04 seconds
Started Jul 17 05:15:16 PM PDT 24
Finished Jul 17 05:15:18 PM PDT 24
Peak memory 208376 kb
Host smart-0ab9353b-034e-49b5-9232-63a94bca7cce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388341427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3388341427
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3504550116
Short name T514
Test name
Test status
Simulation time 861280752 ps
CPU time 9.77 seconds
Started Jul 17 05:15:16 PM PDT 24
Finished Jul 17 05:15:26 PM PDT 24
Peak memory 217772 kb
Host smart-ebcb2193-4388-42d6-bfa8-953f6a2d5b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504550116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3504550116
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2457272067
Short name T9
Test name
Test status
Simulation time 261794756 ps
CPU time 7.3 seconds
Started Jul 17 05:17:30 PM PDT 24
Finished Jul 17 05:17:38 PM PDT 24
Peak memory 216652 kb
Host smart-ae9627d2-7e0a-49c5-8494-a2662ed5fe9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457272067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.2457272067
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.904207823
Short name T567
Test name
Test status
Simulation time 215100890 ps
CPU time 2.63 seconds
Started Jul 17 05:16:06 PM PDT 24
Finished Jul 17 05:16:15 PM PDT 24
Peak memory 221796 kb
Host smart-18cfe26c-1a58-4a94-838a-75b75bd33453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904207823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.904207823
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.4019346044
Short name T781
Test name
Test status
Simulation time 238719375 ps
CPU time 9.4 seconds
Started Jul 17 05:15:32 PM PDT 24
Finished Jul 17 05:15:43 PM PDT 24
Peak memory 218364 kb
Host smart-5c94e41e-7198-4a8e-8235-fd5f3d97446a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019346044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.4019346044
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2905563049
Short name T234
Test name
Test status
Simulation time 996308049 ps
CPU time 19.25 seconds
Started Jul 17 05:15:15 PM PDT 24
Finished Jul 17 05:15:35 PM PDT 24
Peak memory 225500 kb
Host smart-6bd33f43-d660-4027-b1ac-d9d8454503d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905563049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2905563049
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3573786244
Short name T446
Test name
Test status
Simulation time 1960071536 ps
CPU time 9.7 seconds
Started Jul 17 05:17:47 PM PDT 24
Finished Jul 17 05:17:57 PM PDT 24
Peak memory 217632 kb
Host smart-0d4d76ab-ecdd-47ce-ba21-6d6c2d4949cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573786244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3573786244
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3133786930
Short name T628
Test name
Test status
Simulation time 3234690635 ps
CPU time 7.96 seconds
Started Jul 17 05:17:56 PM PDT 24
Finished Jul 17 05:18:11 PM PDT 24
Peak memory 225188 kb
Host smart-38b65753-e4c8-403d-8130-0fa7ebf5b600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133786930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3133786930
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1100385745
Short name T643
Test name
Test status
Simulation time 28557344 ps
CPU time 2.06 seconds
Started Jul 17 05:17:01 PM PDT 24
Finished Jul 17 05:17:04 PM PDT 24
Peak memory 217184 kb
Host smart-5abc79be-1db5-443c-af0d-3ad70d53ac75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100385745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1100385745
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.2258502765
Short name T409
Test name
Test status
Simulation time 339037516 ps
CPU time 29.24 seconds
Started Jul 17 05:16:59 PM PDT 24
Finished Jul 17 05:17:28 PM PDT 24
Peak memory 250556 kb
Host smart-66d3e290-f141-4744-88ec-3d02f7ce78c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258502765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2258502765
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3936994787
Short name T624
Test name
Test status
Simulation time 237851018 ps
CPU time 7.07 seconds
Started Jul 17 05:15:21 PM PDT 24
Finished Jul 17 05:15:29 PM PDT 24
Peak memory 250404 kb
Host smart-8d27c0eb-ff48-4b92-bb6e-f018a3ee53c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936994787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3936994787
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1971370401
Short name T427
Test name
Test status
Simulation time 14969374398 ps
CPU time 131.36 seconds
Started Jul 17 05:17:32 PM PDT 24
Finished Jul 17 05:19:44 PM PDT 24
Peak memory 272556 kb
Host smart-7e205f7f-55a6-4af2-a389-2463c972a046
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971370401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1971370401
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.2502306871
Short name T163
Test name
Test status
Simulation time 15060759730 ps
CPU time 73.25 seconds
Started Jul 17 05:15:53 PM PDT 24
Finished Jul 17 05:17:16 PM PDT 24
Peak memory 258920 kb
Host smart-52fea424-34da-4674-a013-a9fdb3673432
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2502306871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.2502306871
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2763283524
Short name T748
Test name
Test status
Simulation time 41996653 ps
CPU time 0.79 seconds
Started Jul 17 05:17:02 PM PDT 24
Finished Jul 17 05:17:04 PM PDT 24
Peak memory 208188 kb
Host smart-8fe783e2-8659-4c7f-9d3f-28f9b4fc3fb7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763283524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2763283524
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1738586881
Short name T712
Test name
Test status
Simulation time 30940236 ps
CPU time 0.84 seconds
Started Jul 17 05:15:15 PM PDT 24
Finished Jul 17 05:15:17 PM PDT 24
Peak memory 208300 kb
Host smart-533b3acd-6235-4399-a0a2-362c8670a034
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738586881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1738586881
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3655435415
Short name T715
Test name
Test status
Simulation time 372265044 ps
CPU time 11.63 seconds
Started Jul 17 05:15:18 PM PDT 24
Finished Jul 17 05:15:30 PM PDT 24
Peak memory 217724 kb
Host smart-fe8dfb47-b6db-44dd-a9d8-324386e8e280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655435415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3655435415
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2725234211
Short name T661
Test name
Test status
Simulation time 470516458 ps
CPU time 11.68 seconds
Started Jul 17 05:15:17 PM PDT 24
Finished Jul 17 05:15:30 PM PDT 24
Peak memory 217184 kb
Host smart-e7fd764c-f362-4df6-bfb5-c6d310e5e110
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725234211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2725234211
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3999550128
Short name T842
Test name
Test status
Simulation time 194877829 ps
CPU time 2.62 seconds
Started Jul 17 05:16:14 PM PDT 24
Finished Jul 17 05:16:20 PM PDT 24
Peak memory 217760 kb
Host smart-6a59cb4a-8615-48ce-aff0-09e6fc1cd8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999550128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3999550128
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1609481923
Short name T331
Test name
Test status
Simulation time 250802501 ps
CPU time 11.95 seconds
Started Jul 17 05:15:16 PM PDT 24
Finished Jul 17 05:15:28 PM PDT 24
Peak memory 225392 kb
Host smart-d1917e3a-aa39-4262-9614-7ba3b8d8c936
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609481923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1609481923
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.232467276
Short name T648
Test name
Test status
Simulation time 224095173 ps
CPU time 8.1 seconds
Started Jul 17 05:17:54 PM PDT 24
Finished Jul 17 05:18:08 PM PDT 24
Peak memory 225500 kb
Host smart-d33ec8f7-e304-4497-b23d-4dfd55e59d7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232467276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.232467276
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.16336962
Short name T691
Test name
Test status
Simulation time 566975075 ps
CPU time 11.32 seconds
Started Jul 17 05:15:17 PM PDT 24
Finished Jul 17 05:15:30 PM PDT 24
Peak memory 217656 kb
Host smart-0a147bfe-7f1d-4250-b273-6f09791d8381
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16336962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.16336962
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1526300342
Short name T738
Test name
Test status
Simulation time 1341733491 ps
CPU time 9.87 seconds
Started Jul 17 05:17:01 PM PDT 24
Finished Jul 17 05:17:13 PM PDT 24
Peak memory 225184 kb
Host smart-7e994c6c-854a-4db3-9053-e17778b2d375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526300342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1526300342
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.128800485
Short name T679
Test name
Test status
Simulation time 179762929 ps
CPU time 2.38 seconds
Started Jul 17 05:15:14 PM PDT 24
Finished Jul 17 05:15:17 PM PDT 24
Peak memory 213740 kb
Host smart-e4c90dc3-81b5-4436-9401-f1535a021648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128800485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.128800485
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.4227724232
Short name T782
Test name
Test status
Simulation time 1513275023 ps
CPU time 37.3 seconds
Started Jul 17 05:15:18 PM PDT 24
Finished Jul 17 05:15:56 PM PDT 24
Peak memory 250700 kb
Host smart-72d0c49f-caae-4498-b549-149e173dedc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227724232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.4227724232
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.256192746
Short name T667
Test name
Test status
Simulation time 116176825 ps
CPU time 10.17 seconds
Started Jul 17 05:17:55 PM PDT 24
Finished Jul 17 05:18:12 PM PDT 24
Peak memory 250504 kb
Host smart-74db74a2-55a3-42a9-9007-c5e77afdb2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256192746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.256192746
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1364192849
Short name T473
Test name
Test status
Simulation time 11634289475 ps
CPU time 40.49 seconds
Started Jul 17 05:17:01 PM PDT 24
Finished Jul 17 05:17:44 PM PDT 24
Peak memory 251160 kb
Host smart-f9ec5cee-ee03-4060-bbbc-5538ec494c3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364192849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1364192849
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3935603378
Short name T235
Test name
Test status
Simulation time 12365989 ps
CPU time 0.78 seconds
Started Jul 17 05:15:18 PM PDT 24
Finished Jul 17 05:15:20 PM PDT 24
Peak memory 208384 kb
Host smart-b1af9607-3336-4b68-93b8-ea05637f52f2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935603378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3935603378
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.380950887
Short name T393
Test name
Test status
Simulation time 38643953 ps
CPU time 1.15 seconds
Started Jul 17 05:17:02 PM PDT 24
Finished Jul 17 05:17:05 PM PDT 24
Peak memory 208428 kb
Host smart-b43b796c-c312-4ed6-b00e-5b26988e53ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380950887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.380950887
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2546616104
Short name T772
Test name
Test status
Simulation time 3385469277 ps
CPU time 17.49 seconds
Started Jul 17 05:15:15 PM PDT 24
Finished Jul 17 05:15:34 PM PDT 24
Peak memory 218496 kb
Host smart-d372a399-e612-465c-a55c-192403310c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546616104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2546616104
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.948003035
Short name T22
Test name
Test status
Simulation time 269130492 ps
CPU time 7.95 seconds
Started Jul 17 05:15:32 PM PDT 24
Finished Jul 17 05:15:41 PM PDT 24
Peak memory 217136 kb
Host smart-7f3961ff-a5d8-4031-9a88-cf87f15a080e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948003035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.948003035
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.2530672578
Short name T493
Test name
Test status
Simulation time 325076956 ps
CPU time 2.42 seconds
Started Jul 17 05:16:46 PM PDT 24
Finished Jul 17 05:16:49 PM PDT 24
Peak memory 217720 kb
Host smart-7833497a-387b-4f17-86ca-3a674b6554fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530672578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2530672578
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.399914758
Short name T596
Test name
Test status
Simulation time 376152432 ps
CPU time 15.38 seconds
Started Jul 17 05:17:38 PM PDT 24
Finished Jul 17 05:17:55 PM PDT 24
Peak memory 225488 kb
Host smart-486bc6b8-9e81-4150-997d-b06944dabea4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399914758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.399914758
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2453561450
Short name T301
Test name
Test status
Simulation time 241034089 ps
CPU time 8.88 seconds
Started Jul 17 05:15:32 PM PDT 24
Finished Jul 17 05:15:42 PM PDT 24
Peak memory 217660 kb
Host smart-6dead00a-63b7-4c5c-ab06-6e9a7eb6e6f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453561450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2453561450
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3825788037
Short name T290
Test name
Test status
Simulation time 29304724 ps
CPU time 1.26 seconds
Started Jul 17 05:15:18 PM PDT 24
Finished Jul 17 05:15:20 PM PDT 24
Peak memory 217268 kb
Host smart-a0c282f1-2060-4aee-ae9b-e1f2e5c8f787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825788037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3825788037
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.4266106411
Short name T805
Test name
Test status
Simulation time 272571650 ps
CPU time 26.39 seconds
Started Jul 17 05:16:05 PM PDT 24
Finished Jul 17 05:16:38 PM PDT 24
Peak memory 250508 kb
Host smart-3c079431-07e4-47cb-8c61-54d43a6f16f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266106411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.4266106411
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.4047071548
Short name T653
Test name
Test status
Simulation time 729298271 ps
CPU time 8.37 seconds
Started Jul 17 05:15:16 PM PDT 24
Finished Jul 17 05:15:25 PM PDT 24
Peak memory 250428 kb
Host smart-3794e096-0c0b-4bba-8433-68f21e8e6434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047071548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.4047071548
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2442586979
Short name T750
Test name
Test status
Simulation time 2348994755 ps
CPU time 57.8 seconds
Started Jul 17 05:17:39 PM PDT 24
Finished Jul 17 05:18:38 PM PDT 24
Peak memory 219488 kb
Host smart-d196d81d-dd1a-4230-941f-47751fb30da2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442586979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2442586979
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2467267744
Short name T486
Test name
Test status
Simulation time 16294330 ps
CPU time 1.02 seconds
Started Jul 17 05:15:16 PM PDT 24
Finished Jul 17 05:15:17 PM PDT 24
Peak memory 212328 kb
Host smart-bd18c182-f3c9-4777-972d-bd5551a349b7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467267744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2467267744
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.4230340158
Short name T13
Test name
Test status
Simulation time 17330732 ps
CPU time 1.07 seconds
Started Jul 17 05:17:51 PM PDT 24
Finished Jul 17 05:17:57 PM PDT 24
Peak memory 208364 kb
Host smart-11f00585-0ee2-43c6-8a4e-5b9c814cf3f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230340158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.4230340158
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1884468831
Short name T638
Test name
Test status
Simulation time 2310054056 ps
CPU time 18.15 seconds
Started Jul 17 05:17:55 PM PDT 24
Finished Jul 17 05:18:19 PM PDT 24
Peak memory 217760 kb
Host smart-698c7c32-d954-46bd-897c-fdbe41d198a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884468831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1884468831
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3845921125
Short name T654
Test name
Test status
Simulation time 818702101 ps
CPU time 3.47 seconds
Started Jul 17 05:15:30 PM PDT 24
Finished Jul 17 05:15:34 PM PDT 24
Peak memory 217004 kb
Host smart-c373ad52-e275-430b-9cbc-ecc55d42f981
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845921125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3845921125
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1047145946
Short name T381
Test name
Test status
Simulation time 257389047 ps
CPU time 3.66 seconds
Started Jul 17 05:15:32 PM PDT 24
Finished Jul 17 05:15:37 PM PDT 24
Peak memory 217940 kb
Host smart-8d3d96bd-81c1-48e8-bebe-fcb045166949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047145946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1047145946
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1280528769
Short name T287
Test name
Test status
Simulation time 1387754844 ps
CPU time 13.01 seconds
Started Jul 17 05:17:35 PM PDT 24
Finished Jul 17 05:17:49 PM PDT 24
Peak memory 225500 kb
Host smart-81699af5-37d2-4d81-a1cd-66b7b918c299
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280528769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1280528769
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1103046719
Short name T651
Test name
Test status
Simulation time 728555722 ps
CPU time 9.87 seconds
Started Jul 17 05:15:34 PM PDT 24
Finished Jul 17 05:15:45 PM PDT 24
Peak memory 217664 kb
Host smart-5d0bbebd-4c94-4076-a791-1c5894d4c705
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103046719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1103046719
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.291536966
Short name T598
Test name
Test status
Simulation time 424256550 ps
CPU time 10.18 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:18:04 PM PDT 24
Peak memory 225540 kb
Host smart-d76dfacf-9072-425d-9972-e93a0fa8aaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291536966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.291536966
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2723961399
Short name T426
Test name
Test status
Simulation time 48904132 ps
CPU time 2.2 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:17:55 PM PDT 24
Peak memory 222604 kb
Host smart-1777f39c-6d3e-41a4-9a1c-6d6d272c21fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723961399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2723961399
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.856012529
Short name T732
Test name
Test status
Simulation time 3119596731 ps
CPU time 18.65 seconds
Started Jul 17 05:17:57 PM PDT 24
Finished Jul 17 05:18:22 PM PDT 24
Peak memory 250552 kb
Host smart-b195c18a-1d5e-4144-bcf8-0003265f2c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856012529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.856012529
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.315958343
Short name T30
Test name
Test status
Simulation time 531946575 ps
CPU time 5.92 seconds
Started Jul 17 05:16:13 PM PDT 24
Finished Jul 17 05:16:22 PM PDT 24
Peak memory 222492 kb
Host smart-fb112310-418b-4326-961b-89577b7acaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315958343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.315958343
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.4198707199
Short name T825
Test name
Test status
Simulation time 178672474926 ps
CPU time 463.74 seconds
Started Jul 17 05:17:53 PM PDT 24
Finished Jul 17 05:25:43 PM PDT 24
Peak memory 271308 kb
Host smart-9f9731f6-bba2-4f1c-bc69-67911694ca97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198707199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.4198707199
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.2836075114
Short name T95
Test name
Test status
Simulation time 92997071227 ps
CPU time 96.72 seconds
Started Jul 17 05:15:34 PM PDT 24
Finished Jul 17 05:17:12 PM PDT 24
Peak memory 260076 kb
Host smart-fc58d1b6-57c6-44fc-b966-304a9bf1a7d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2836075114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.2836075114
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2818046129
Short name T787
Test name
Test status
Simulation time 15203242 ps
CPU time 1.14 seconds
Started Jul 17 05:15:30 PM PDT 24
Finished Jul 17 05:15:32 PM PDT 24
Peak memory 211580 kb
Host smart-72cbe936-7637-42b5-a882-adb5193a345a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818046129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2818046129
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.100897929
Short name T699
Test name
Test status
Simulation time 61264086 ps
CPU time 1.1 seconds
Started Jul 17 05:15:28 PM PDT 24
Finished Jul 17 05:15:30 PM PDT 24
Peak memory 208452 kb
Host smart-4fa554a2-8fe0-45d2-97e7-4460660b707a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100897929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.100897929
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.2956200604
Short name T552
Test name
Test status
Simulation time 437334904 ps
CPU time 8.04 seconds
Started Jul 17 05:15:34 PM PDT 24
Finished Jul 17 05:15:43 PM PDT 24
Peak memory 217724 kb
Host smart-2b1074c9-0d62-4620-b533-805050ffe8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956200604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2956200604
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3653922750
Short name T513
Test name
Test status
Simulation time 470090831 ps
CPU time 4.09 seconds
Started Jul 17 05:17:51 PM PDT 24
Finished Jul 17 05:18:01 PM PDT 24
Peak memory 217156 kb
Host smart-5624b467-4314-475c-88c4-1f3cfeb4b824
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653922750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3653922750
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1665995898
Short name T562
Test name
Test status
Simulation time 110421658 ps
CPU time 3.09 seconds
Started Jul 17 05:16:25 PM PDT 24
Finished Jul 17 05:16:29 PM PDT 24
Peak memory 217648 kb
Host smart-5fabc44c-47b2-4ac9-8d45-b6fee80455b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665995898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1665995898
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.2077068363
Short name T397
Test name
Test status
Simulation time 3265442449 ps
CPU time 8.92 seconds
Started Jul 17 05:17:54 PM PDT 24
Finished Jul 17 05:18:09 PM PDT 24
Peak memory 225616 kb
Host smart-21748ce0-9ad0-4ed2-9e26-92d0a910176d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077068363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2077068363
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2913360698
Short name T810
Test name
Test status
Simulation time 2735498477 ps
CPU time 9.48 seconds
Started Jul 17 05:15:27 PM PDT 24
Finished Jul 17 05:15:37 PM PDT 24
Peak memory 225564 kb
Host smart-0af1d29a-1196-4ddf-a93c-9d740f6b35c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913360698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2913360698
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3368517740
Short name T93
Test name
Test status
Simulation time 389399773 ps
CPU time 13.12 seconds
Started Jul 17 05:17:49 PM PDT 24
Finished Jul 17 05:18:05 PM PDT 24
Peak memory 217720 kb
Host smart-b9fd92b0-b77e-44e9-b404-9fe1c5c1517a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368517740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3368517740
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2878430617
Short name T55
Test name
Test status
Simulation time 1813507166 ps
CPU time 16.01 seconds
Started Jul 17 05:15:29 PM PDT 24
Finished Jul 17 05:15:46 PM PDT 24
Peak memory 225568 kb
Host smart-728889bb-712d-4727-bb0a-1bf39e8b23c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878430617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2878430617
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.205791243
Short name T84
Test name
Test status
Simulation time 60451882 ps
CPU time 3.32 seconds
Started Jul 17 05:15:33 PM PDT 24
Finished Jul 17 05:15:38 PM PDT 24
Peak memory 214416 kb
Host smart-cccaf6ff-c24b-46c8-a93d-14f40d5213c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205791243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.205791243
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1374722918
Short name T543
Test name
Test status
Simulation time 542446767 ps
CPU time 15.98 seconds
Started Jul 17 05:15:33 PM PDT 24
Finished Jul 17 05:15:50 PM PDT 24
Peak memory 243668 kb
Host smart-ef225ae1-0be8-436a-9656-3139c0fce426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374722918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1374722918
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1500883017
Short name T251
Test name
Test status
Simulation time 548805886 ps
CPU time 4.91 seconds
Started Jul 17 05:17:01 PM PDT 24
Finished Jul 17 05:17:08 PM PDT 24
Peak memory 222540 kb
Host smart-1fdee249-d9a2-4ee2-8f29-18516e97e3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500883017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1500883017
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1872558059
Short name T46
Test name
Test status
Simulation time 6713411616 ps
CPU time 230.06 seconds
Started Jul 17 05:17:56 PM PDT 24
Finished Jul 17 05:21:53 PM PDT 24
Peak memory 275120 kb
Host smart-b2dcb03e-f2f5-463e-99a7-f7cb3a3e2999
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872558059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1872558059
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2254086710
Short name T37
Test name
Test status
Simulation time 78288689 ps
CPU time 0.81 seconds
Started Jul 17 05:15:34 PM PDT 24
Finished Jul 17 05:15:36 PM PDT 24
Peak memory 208352 kb
Host smart-9b686954-a6e9-4372-ac71-8fb5e0e9868d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254086710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2254086710
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2101785674
Short name T253
Test name
Test status
Simulation time 20346986 ps
CPU time 1.02 seconds
Started Jul 17 05:15:35 PM PDT 24
Finished Jul 17 05:15:37 PM PDT 24
Peak memory 208356 kb
Host smart-9e89b76a-ff1d-4966-91be-ea6e22275563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101785674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2101785674
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3402117996
Short name T272
Test name
Test status
Simulation time 2742962915 ps
CPU time 20.52 seconds
Started Jul 17 05:15:29 PM PDT 24
Finished Jul 17 05:15:50 PM PDT 24
Peak memory 218492 kb
Host smart-0d14b119-f4dd-45e5-844a-84aac94cefc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402117996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3402117996
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.3431365951
Short name T720
Test name
Test status
Simulation time 199968113 ps
CPU time 2.1 seconds
Started Jul 17 05:15:34 PM PDT 24
Finished Jul 17 05:15:37 PM PDT 24
Peak memory 216592 kb
Host smart-27ab1e46-1c5e-4b94-a7c1-6e4e2ebf693d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431365951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.3431365951
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3531986981
Short name T801
Test name
Test status
Simulation time 131431265 ps
CPU time 5.84 seconds
Started Jul 17 05:15:32 PM PDT 24
Finished Jul 17 05:15:39 PM PDT 24
Peak memory 217736 kb
Host smart-e16f19f6-ea65-4c40-81fd-084cf34d3e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531986981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3531986981
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.390950666
Short name T346
Test name
Test status
Simulation time 434758720 ps
CPU time 13.84 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:18:08 PM PDT 24
Peak memory 225564 kb
Host smart-54a23801-5c7c-4b61-8fa8-50acd3e7c042
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390950666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.390950666
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2898610596
Short name T257
Test name
Test status
Simulation time 2153789435 ps
CPU time 9.19 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:18:02 PM PDT 24
Peak memory 225624 kb
Host smart-a679d8d9-bd3d-4665-bdee-3b600782e7bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898610596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2898610596
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.4261486329
Short name T531
Test name
Test status
Simulation time 1855460488 ps
CPU time 7.11 seconds
Started Jul 17 05:15:28 PM PDT 24
Finished Jul 17 05:15:36 PM PDT 24
Peak memory 225704 kb
Host smart-a3dc2800-17f7-46d0-a3e9-4f0d4ca649cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261486329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
4261486329
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3509747922
Short name T310
Test name
Test status
Simulation time 271080978 ps
CPU time 8.33 seconds
Started Jul 17 05:15:36 PM PDT 24
Finished Jul 17 05:15:45 PM PDT 24
Peak memory 225556 kb
Host smart-ed71d09b-1171-4a8b-95a5-2ff261615ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509747922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3509747922
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3947582991
Short name T81
Test name
Test status
Simulation time 20567127 ps
CPU time 1.6 seconds
Started Jul 17 05:15:28 PM PDT 24
Finished Jul 17 05:15:31 PM PDT 24
Peak memory 213232 kb
Host smart-f7874349-4e8b-4fc6-a920-f1d321bc2627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947582991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3947582991
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3268984788
Short name T302
Test name
Test status
Simulation time 211724192 ps
CPU time 18.64 seconds
Started Jul 17 05:17:01 PM PDT 24
Finished Jul 17 05:17:21 PM PDT 24
Peak memory 250432 kb
Host smart-90361ca8-357c-46df-a8ef-658137368bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268984788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3268984788
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.133932718
Short name T717
Test name
Test status
Simulation time 57298480 ps
CPU time 8.76 seconds
Started Jul 17 05:15:44 PM PDT 24
Finished Jul 17 05:15:57 PM PDT 24
Peak memory 246712 kb
Host smart-790b536e-5f22-4d25-b6c6-ca909de94af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133932718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.133932718
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.229716788
Short name T249
Test name
Test status
Simulation time 2851947584 ps
CPU time 40.76 seconds
Started Jul 17 05:17:49 PM PDT 24
Finished Jul 17 05:18:33 PM PDT 24
Peak memory 225556 kb
Host smart-31f58441-e224-4a2c-81aa-11d601b6c416
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229716788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.229716788
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3037287968
Short name T291
Test name
Test status
Simulation time 23381641 ps
CPU time 0.94 seconds
Started Jul 17 05:15:33 PM PDT 24
Finished Jul 17 05:15:35 PM PDT 24
Peak memory 211388 kb
Host smart-cb654cda-59ce-47bd-a552-5bce227a7bfd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037287968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3037287968
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1628477987
Short name T428
Test name
Test status
Simulation time 84117285 ps
CPU time 1.27 seconds
Started Jul 17 05:15:44 PM PDT 24
Finished Jul 17 05:15:49 PM PDT 24
Peak memory 208540 kb
Host smart-62bb55d0-b4fc-4657-8bb6-2d0a3960ae15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628477987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1628477987
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3552169166
Short name T584
Test name
Test status
Simulation time 189205024 ps
CPU time 9.42 seconds
Started Jul 17 05:15:43 PM PDT 24
Finished Jul 17 05:15:56 PM PDT 24
Peak memory 217760 kb
Host smart-fdcf0673-f4a3-4a23-b0f8-1a89f96ceedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552169166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3552169166
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3854059155
Short name T25
Test name
Test status
Simulation time 226887144 ps
CPU time 7.01 seconds
Started Jul 17 05:15:43 PM PDT 24
Finished Jul 17 05:15:54 PM PDT 24
Peak memory 216980 kb
Host smart-ca12b630-3d53-4487-b3d8-00cb8445f0fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854059155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3854059155
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2803897710
Short name T670
Test name
Test status
Simulation time 46154240 ps
CPU time 2.13 seconds
Started Jul 17 05:17:53 PM PDT 24
Finished Jul 17 05:18:02 PM PDT 24
Peak memory 217820 kb
Host smart-9624fabc-9d36-4fff-84c7-4ff25cb24608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803897710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2803897710
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.2059567463
Short name T780
Test name
Test status
Simulation time 1165751902 ps
CPU time 8.55 seconds
Started Jul 17 05:15:44 PM PDT 24
Finished Jul 17 05:15:56 PM PDT 24
Peak memory 225568 kb
Host smart-3469a692-d5c1-43b9-a177-ba412384f255
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059567463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2059567463
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3735830255
Short name T450
Test name
Test status
Simulation time 425138758 ps
CPU time 12.55 seconds
Started Jul 17 05:15:47 PM PDT 24
Finished Jul 17 05:16:04 PM PDT 24
Peak memory 225476 kb
Host smart-7317af74-c0ca-464a-9e8d-d33bb5b3faa6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735830255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3735830255
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1355811636
Short name T527
Test name
Test status
Simulation time 282605846 ps
CPU time 10.87 seconds
Started Jul 17 05:15:42 PM PDT 24
Finished Jul 17 05:15:56 PM PDT 24
Peak memory 217720 kb
Host smart-4722424b-5c3f-4fca-8697-9857ef03d5be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355811636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1355811636
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.280851743
Short name T385
Test name
Test status
Simulation time 340998489 ps
CPU time 7.67 seconds
Started Jul 17 05:15:51 PM PDT 24
Finished Jul 17 05:16:07 PM PDT 24
Peak memory 224664 kb
Host smart-4f3aa581-1d55-4f83-8d0c-21444679e71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280851743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.280851743
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1958817837
Short name T545
Test name
Test status
Simulation time 148725774 ps
CPU time 2.52 seconds
Started Jul 17 05:17:56 PM PDT 24
Finished Jul 17 05:18:05 PM PDT 24
Peak memory 213660 kb
Host smart-96fd51dc-2b35-452e-9512-9c8601b27fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958817837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1958817837
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.466769475
Short name T420
Test name
Test status
Simulation time 181270196 ps
CPU time 18.99 seconds
Started Jul 17 05:17:55 PM PDT 24
Finished Jul 17 05:18:20 PM PDT 24
Peak memory 250516 kb
Host smart-f1395283-d421-48a2-860e-4d28d15c19d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466769475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.466769475
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.475701609
Short name T358
Test name
Test status
Simulation time 344552432 ps
CPU time 7.97 seconds
Started Jul 17 05:15:34 PM PDT 24
Finished Jul 17 05:15:43 PM PDT 24
Peak memory 250028 kb
Host smart-c50072a0-ae8c-4bfd-8df5-df9022e00875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475701609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.475701609
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3941019389
Short name T558
Test name
Test status
Simulation time 7987567668 ps
CPU time 57.52 seconds
Started Jul 17 05:17:55 PM PDT 24
Finished Jul 17 05:18:59 PM PDT 24
Peak memory 225612 kb
Host smart-d84a1bbb-ee89-4fe6-be2a-08092bef591d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941019389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3941019389
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1706282831
Short name T718
Test name
Test status
Simulation time 14935604 ps
CPU time 1 seconds
Started Jul 17 05:15:37 PM PDT 24
Finished Jul 17 05:15:39 PM PDT 24
Peak memory 208596 kb
Host smart-e7cd68f4-893a-4440-bbc7-b40884a8df2f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706282831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1706282831
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2299643387
Short name T619
Test name
Test status
Simulation time 74560353 ps
CPU time 1.11 seconds
Started Jul 17 05:15:43 PM PDT 24
Finished Jul 17 05:15:47 PM PDT 24
Peak memory 208400 kb
Host smart-0486e095-8acc-44af-978f-71ae7d280866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299643387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2299643387
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3966017240
Short name T829
Test name
Test status
Simulation time 2043613243 ps
CPU time 17.04 seconds
Started Jul 17 05:15:45 PM PDT 24
Finished Jul 17 05:16:06 PM PDT 24
Peak memory 217776 kb
Host smart-4e1eb099-0b6d-4f73-8f5e-9ffa660dcd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966017240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3966017240
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2532467793
Short name T741
Test name
Test status
Simulation time 1794157242 ps
CPU time 12.74 seconds
Started Jul 17 05:15:43 PM PDT 24
Finished Jul 17 05:15:59 PM PDT 24
Peak memory 217056 kb
Host smart-cd77c084-4930-433c-a75f-1222830b7bba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532467793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2532467793
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.548356336
Short name T315
Test name
Test status
Simulation time 267287412 ps
CPU time 2.34 seconds
Started Jul 17 05:17:48 PM PDT 24
Finished Jul 17 05:17:52 PM PDT 24
Peak memory 217424 kb
Host smart-59f99490-de7c-48d7-83a3-330d26b5c02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548356336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.548356336
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.948071109
Short name T299
Test name
Test status
Simulation time 1303732243 ps
CPU time 15.85 seconds
Started Jul 17 05:15:51 PM PDT 24
Finished Jul 17 05:16:15 PM PDT 24
Peak memory 225352 kb
Host smart-e726615e-3208-4b4b-a79e-5eeb6dc56596
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948071109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.948071109
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1461110103
Short name T778
Test name
Test status
Simulation time 267097715 ps
CPU time 9.09 seconds
Started Jul 17 05:15:43 PM PDT 24
Finished Jul 17 05:15:55 PM PDT 24
Peak memory 225500 kb
Host smart-055da95f-3ca9-42f2-a93d-0e67dfddaf3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461110103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1461110103
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.882125924
Short name T808
Test name
Test status
Simulation time 658965320 ps
CPU time 12.93 seconds
Started Jul 17 05:15:45 PM PDT 24
Finished Jul 17 05:16:02 PM PDT 24
Peak memory 217656 kb
Host smart-86efb2a1-8819-496a-b0bf-21bb2c6fd6c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882125924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.882125924
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.821729834
Short name T551
Test name
Test status
Simulation time 758626644 ps
CPU time 12.06 seconds
Started Jul 17 05:17:01 PM PDT 24
Finished Jul 17 05:17:15 PM PDT 24
Peak memory 225556 kb
Host smart-642c1250-c146-4e77-9d75-d20feaca6ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821729834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.821729834
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2835783821
Short name T518
Test name
Test status
Simulation time 59147639 ps
CPU time 1.78 seconds
Started Jul 17 05:15:43 PM PDT 24
Finished Jul 17 05:15:47 PM PDT 24
Peak memory 217300 kb
Host smart-0247ba4f-c0ff-464a-9476-90290b43e6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835783821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2835783821
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1577399322
Short name T1
Test name
Test status
Simulation time 534505887 ps
CPU time 23.65 seconds
Started Jul 17 05:15:45 PM PDT 24
Finished Jul 17 05:16:13 PM PDT 24
Peak memory 250488 kb
Host smart-ca64cc8e-8303-4a49-8176-ee3c74fab478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577399322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1577399322
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2448090888
Short name T247
Test name
Test status
Simulation time 120647386 ps
CPU time 7.25 seconds
Started Jul 17 05:15:51 PM PDT 24
Finished Jul 17 05:16:06 PM PDT 24
Peak memory 246264 kb
Host smart-4a3ad323-b8db-4c64-bd44-b9672983670f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448090888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2448090888
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2179602521
Short name T361
Test name
Test status
Simulation time 10891252940 ps
CPU time 74.88 seconds
Started Jul 17 05:15:42 PM PDT 24
Finished Jul 17 05:16:59 PM PDT 24
Peak memory 225472 kb
Host smart-8077a9c9-186b-489b-9032-136703e69e8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179602521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2179602521
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1470409137
Short name T35
Test name
Test status
Simulation time 54885096 ps
CPU time 1.06 seconds
Started Jul 17 05:17:01 PM PDT 24
Finished Jul 17 05:17:03 PM PDT 24
Peak memory 211328 kb
Host smart-a39345ae-b380-4256-9ef0-585dae712b8c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470409137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1470409137
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2457561515
Short name T845
Test name
Test status
Simulation time 20888794 ps
CPU time 1.16 seconds
Started Jul 17 05:13:26 PM PDT 24
Finished Jul 17 05:13:28 PM PDT 24
Peak memory 208468 kb
Host smart-b9418beb-71f3-4426-870f-575c5f28034a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457561515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2457561515
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.714250671
Short name T200
Test name
Test status
Simulation time 14413089 ps
CPU time 0.86 seconds
Started Jul 17 05:17:35 PM PDT 24
Finished Jul 17 05:17:37 PM PDT 24
Peak memory 208096 kb
Host smart-ead04916-7ae1-49f7-bbad-dc1cad5533e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714250671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.714250671
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2776504447
Short name T706
Test name
Test status
Simulation time 843983150 ps
CPU time 9.39 seconds
Started Jul 17 05:17:35 PM PDT 24
Finished Jul 17 05:17:45 PM PDT 24
Peak memory 217748 kb
Host smart-0024f075-0638-4c65-8262-66345aa986a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776504447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2776504447
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.403062488
Short name T317
Test name
Test status
Simulation time 390138833 ps
CPU time 1.98 seconds
Started Jul 17 05:13:26 PM PDT 24
Finished Jul 17 05:13:29 PM PDT 24
Peak memory 216828 kb
Host smart-385c8821-df75-4a4e-902c-ee9351c8de12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403062488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.403062488
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.3756791943
Short name T401
Test name
Test status
Simulation time 1458514142 ps
CPU time 47.95 seconds
Started Jul 17 05:13:27 PM PDT 24
Finished Jul 17 05:14:17 PM PDT 24
Peak memory 217708 kb
Host smart-49af5354-4cfd-438a-9808-aa8443864fd4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756791943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.3756791943
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.4200633312
Short name T523
Test name
Test status
Simulation time 761065075 ps
CPU time 7.66 seconds
Started Jul 17 05:13:26 PM PDT 24
Finished Jul 17 05:13:36 PM PDT 24
Peak memory 217212 kb
Host smart-99c512f1-8759-4253-af2c-70cc126d51de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200633312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.4
200633312
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.95828210
Short name T641
Test name
Test status
Simulation time 4163109358 ps
CPU time 6.45 seconds
Started Jul 17 05:15:50 PM PDT 24
Finished Jul 17 05:16:05 PM PDT 24
Peak memory 217772 kb
Host smart-985a45bb-6abd-45fc-a5b8-f89a9820e9c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95828210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_p
rog_failure.95828210
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1514693185
Short name T236
Test name
Test status
Simulation time 12804439526 ps
CPU time 16.32 seconds
Started Jul 17 05:13:27 PM PDT 24
Finished Jul 17 05:13:46 PM PDT 24
Peak memory 217176 kb
Host smart-468b0d40-de1e-46c0-b509-c2b03a3260cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514693185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1514693185
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3086180037
Short name T515
Test name
Test status
Simulation time 510310144 ps
CPU time 6.36 seconds
Started Jul 17 05:13:25 PM PDT 24
Finished Jul 17 05:13:32 PM PDT 24
Peak memory 217056 kb
Host smart-d5503d02-c1bc-4c99-888f-da535612f43d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086180037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3086180037
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3521199195
Short name T809
Test name
Test status
Simulation time 1432439762 ps
CPU time 63.5 seconds
Started Jul 17 05:13:27 PM PDT 24
Finished Jul 17 05:14:32 PM PDT 24
Peak memory 251576 kb
Host smart-9df4622f-a635-4309-b423-442ed7dc8f63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521199195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3521199195
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.562367675
Short name T823
Test name
Test status
Simulation time 443294015 ps
CPU time 8.81 seconds
Started Jul 17 05:17:35 PM PDT 24
Finished Jul 17 05:17:45 PM PDT 24
Peak memory 222524 kb
Host smart-ac8f4a7d-21eb-4f69-884d-108fcdf19814
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562367675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.562367675
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2164986231
Short name T161
Test name
Test status
Simulation time 101714689 ps
CPU time 2.22 seconds
Started Jul 17 05:13:27 PM PDT 24
Finished Jul 17 05:13:31 PM PDT 24
Peak memory 217740 kb
Host smart-97730450-ce68-4f60-9640-46e80d7ea535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164986231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2164986231
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2306115723
Short name T146
Test name
Test status
Simulation time 499668168 ps
CPU time 16.6 seconds
Started Jul 17 05:13:32 PM PDT 24
Finished Jul 17 05:13:49 PM PDT 24
Peak memory 214080 kb
Host smart-d3c977b8-8128-49bc-bfc9-227afc61d0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306115723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2306115723
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2532369730
Short name T85
Test name
Test status
Simulation time 1365900539 ps
CPU time 26.48 seconds
Started Jul 17 05:13:29 PM PDT 24
Finished Jul 17 05:13:57 PM PDT 24
Peak memory 282348 kb
Host smart-6a1b35d4-7886-4eae-b5b3-262ac2db87cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532369730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2532369730
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.3461637977
Short name T375
Test name
Test status
Simulation time 2354320374 ps
CPU time 14.43 seconds
Started Jul 17 05:16:03 PM PDT 24
Finished Jul 17 05:16:26 PM PDT 24
Peak memory 225620 kb
Host smart-c9d7e212-f6f9-4cfb-a061-75669e529816
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461637977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.3461637977
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2655461971
Short name T242
Test name
Test status
Simulation time 323130087 ps
CPU time 8.76 seconds
Started Jul 17 05:13:31 PM PDT 24
Finished Jul 17 05:13:40 PM PDT 24
Peak memory 225496 kb
Host smart-5303aa08-6647-4ca9-9418-eeb865c2122a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655461971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2655461971
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3746286281
Short name T313
Test name
Test status
Simulation time 235207174 ps
CPU time 8.1 seconds
Started Jul 17 05:13:30 PM PDT 24
Finished Jul 17 05:13:39 PM PDT 24
Peak memory 217660 kb
Host smart-3fe16413-4a0e-493b-94bf-dc20d9e5d821
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746286281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3
746286281
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3544001513
Short name T54
Test name
Test status
Simulation time 617534772 ps
CPU time 9.14 seconds
Started Jul 17 05:13:26 PM PDT 24
Finished Jul 17 05:13:37 PM PDT 24
Peak memory 224156 kb
Host smart-f2006733-1b06-4fda-b6e4-a2d686788756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544001513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3544001513
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3980299997
Short name T399
Test name
Test status
Simulation time 24175027 ps
CPU time 1.6 seconds
Started Jul 17 05:13:30 PM PDT 24
Finished Jul 17 05:13:32 PM PDT 24
Peak memory 217204 kb
Host smart-2b3b6de9-0bd0-4bde-a0ff-2698327f09d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980299997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3980299997
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3449711497
Short name T463
Test name
Test status
Simulation time 186695366 ps
CPU time 25.28 seconds
Started Jul 17 05:13:26 PM PDT 24
Finished Jul 17 05:13:53 PM PDT 24
Peak memory 250584 kb
Host smart-ece79441-89c6-43b4-a521-0cf3e4058734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449711497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3449711497
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.408116095
Short name T814
Test name
Test status
Simulation time 244354848 ps
CPU time 7.76 seconds
Started Jul 17 05:13:25 PM PDT 24
Finished Jul 17 05:13:34 PM PDT 24
Peak memory 246664 kb
Host smart-c1d570d0-d31a-43d2-a28a-9646def496c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408116095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.408116095
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2697202659
Short name T736
Test name
Test status
Simulation time 2311021695 ps
CPU time 123.06 seconds
Started Jul 17 05:13:25 PM PDT 24
Finished Jul 17 05:15:29 PM PDT 24
Peak memory 267180 kb
Host smart-a88a3e2b-d616-4469-83be-22e9af64ca49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697202659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2697202659
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2241794553
Short name T833
Test name
Test status
Simulation time 47816607 ps
CPU time 0.9 seconds
Started Jul 17 05:13:26 PM PDT 24
Finished Jul 17 05:13:29 PM PDT 24
Peak memory 212360 kb
Host smart-772f4338-a0ff-462a-acbd-0dff01f2e9df
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241794553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2241794553
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2831058013
Short name T777
Test name
Test status
Simulation time 111062092 ps
CPU time 1.05 seconds
Started Jul 17 05:15:59 PM PDT 24
Finished Jul 17 05:16:10 PM PDT 24
Peak memory 208612 kb
Host smart-b0dddccf-36b0-4755-a83f-762c7fc482a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831058013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2831058013
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1187184057
Short name T145
Test name
Test status
Simulation time 1022572517 ps
CPU time 12.36 seconds
Started Jul 17 05:17:37 PM PDT 24
Finished Jul 17 05:17:51 PM PDT 24
Peak memory 217716 kb
Host smart-471f4367-70eb-4a03-832d-b6ee16abea27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187184057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1187184057
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1842108648
Short name T435
Test name
Test status
Simulation time 279036968 ps
CPU time 1.44 seconds
Started Jul 17 05:15:45 PM PDT 24
Finished Jul 17 05:15:50 PM PDT 24
Peak memory 217488 kb
Host smart-f607ea46-fb69-459f-9b58-8c19df80a8b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842108648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1842108648
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3421543091
Short name T292
Test name
Test status
Simulation time 55122789 ps
CPU time 2.68 seconds
Started Jul 17 05:17:00 PM PDT 24
Finished Jul 17 05:17:04 PM PDT 24
Peak memory 217752 kb
Host smart-8d83eeb8-172d-4b25-b0a4-e4133989a3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421543091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3421543091
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.4062144495
Short name T172
Test name
Test status
Simulation time 1647142562 ps
CPU time 17.01 seconds
Started Jul 17 05:15:51 PM PDT 24
Finished Jul 17 05:16:16 PM PDT 24
Peak memory 218368 kb
Host smart-cb62dbeb-681b-4995-8510-516a9680be1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062144495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.4062144495
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.521908102
Short name T474
Test name
Test status
Simulation time 424477901 ps
CPU time 11.75 seconds
Started Jul 17 05:17:48 PM PDT 24
Finished Jul 17 05:18:02 PM PDT 24
Peak memory 225436 kb
Host smart-83098e59-e25f-47d9-9e27-5b64462cabb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521908102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.521908102
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1410482420
Short name T280
Test name
Test status
Simulation time 329313188 ps
CPU time 7.06 seconds
Started Jul 17 05:17:00 PM PDT 24
Finished Jul 17 05:17:09 PM PDT 24
Peak memory 217672 kb
Host smart-79b30b5b-6a08-45f9-92f5-4555457feeb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410482420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1410482420
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.4069582456
Short name T170
Test name
Test status
Simulation time 1146519385 ps
CPU time 9.76 seconds
Started Jul 17 05:15:44 PM PDT 24
Finished Jul 17 05:15:57 PM PDT 24
Peak memory 217812 kb
Host smart-eb240451-fa7d-48b6-945f-ab0f86400422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069582456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.4069582456
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3782794040
Short name T759
Test name
Test status
Simulation time 108417493 ps
CPU time 2.38 seconds
Started Jul 17 05:15:46 PM PDT 24
Finished Jul 17 05:15:52 PM PDT 24
Peak memory 213908 kb
Host smart-87ef0feb-2e68-4c51-a311-866e20db6298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782794040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3782794040
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.56285267
Short name T335
Test name
Test status
Simulation time 268656934 ps
CPU time 24.35 seconds
Started Jul 17 05:17:55 PM PDT 24
Finished Jul 17 05:18:25 PM PDT 24
Peak memory 250364 kb
Host smart-5184c37f-2975-4f49-81d2-d01e680e16a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56285267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.56285267
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3425080094
Short name T789
Test name
Test status
Simulation time 44973936 ps
CPU time 3.09 seconds
Started Jul 17 05:17:55 PM PDT 24
Finished Jul 17 05:18:05 PM PDT 24
Peak memory 217688 kb
Host smart-ffaffe27-6a65-417c-9774-56557fd9eb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425080094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3425080094
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3311468776
Short name T143
Test name
Test status
Simulation time 5779439463 ps
CPU time 23.83 seconds
Started Jul 17 05:15:45 PM PDT 24
Finished Jul 17 05:16:13 PM PDT 24
Peak memory 219704 kb
Host smart-93dc1a26-9c17-402e-a4a7-08224a46d95a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311468776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3311468776
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3497504629
Short name T283
Test name
Test status
Simulation time 95595507 ps
CPU time 0.78 seconds
Started Jul 17 05:17:52 PM PDT 24
Finished Jul 17 05:17:58 PM PDT 24
Peak memory 208368 kb
Host smart-80412e26-71cb-414b-ae61-eca81e19ec78
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497504629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3497504629
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.787652872
Short name T820
Test name
Test status
Simulation time 59462916 ps
CPU time 1.05 seconds
Started Jul 17 05:17:48 PM PDT 24
Finished Jul 17 05:17:51 PM PDT 24
Peak memory 208212 kb
Host smart-4998fa09-399e-4d56-94f2-9822734142c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787652872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.787652872
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1743233379
Short name T350
Test name
Test status
Simulation time 903352058 ps
CPU time 14.23 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:18:07 PM PDT 24
Peak memory 225220 kb
Host smart-eed7aa83-28eb-4948-b022-3dc73910ccf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743233379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1743233379
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2499718715
Short name T7
Test name
Test status
Simulation time 670066012 ps
CPU time 4.44 seconds
Started Jul 17 05:16:06 PM PDT 24
Finished Jul 17 05:16:17 PM PDT 24
Peak memory 217176 kb
Host smart-c28046d7-841d-43ce-a52c-6ffe73262c23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499718715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2499718715
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2291594092
Short name T859
Test name
Test status
Simulation time 287369334 ps
CPU time 3.65 seconds
Started Jul 17 05:16:06 PM PDT 24
Finished Jul 17 05:16:16 PM PDT 24
Peak memory 217612 kb
Host smart-e58fc93e-d8b9-413f-9f3c-fef5ab51c920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291594092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2291594092
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2875673099
Short name T505
Test name
Test status
Simulation time 330748622 ps
CPU time 13.63 seconds
Started Jul 17 05:15:55 PM PDT 24
Finished Jul 17 05:16:19 PM PDT 24
Peak memory 219500 kb
Host smart-1314c6db-ea2b-451b-97c5-c8343797ba4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875673099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2875673099
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3052849058
Short name T369
Test name
Test status
Simulation time 1474704283 ps
CPU time 12.38 seconds
Started Jul 17 05:15:55 PM PDT 24
Finished Jul 17 05:16:17 PM PDT 24
Peak memory 225444 kb
Host smart-bbbb640c-7854-4562-ae8c-b301353bb2b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052849058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3052849058
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2059713238
Short name T467
Test name
Test status
Simulation time 638476972 ps
CPU time 11.58 seconds
Started Jul 17 05:17:23 PM PDT 24
Finished Jul 17 05:17:35 PM PDT 24
Peak memory 217712 kb
Host smart-bac722e8-a306-47d1-a94a-4f3cdab2fd50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059713238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2059713238
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1493124960
Short name T652
Test name
Test status
Simulation time 1139627903 ps
CPU time 10.29 seconds
Started Jul 17 05:16:05 PM PDT 24
Finished Jul 17 05:16:22 PM PDT 24
Peak memory 224912 kb
Host smart-29684e86-7fa2-4f45-ab3a-f36cfbbde04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493124960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1493124960
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1599589009
Short name T798
Test name
Test status
Simulation time 1005364258 ps
CPU time 14.2 seconds
Started Jul 17 05:15:54 PM PDT 24
Finished Jul 17 05:16:17 PM PDT 24
Peak memory 217184 kb
Host smart-01940d4e-ff9c-474d-baf5-7066a28d3a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599589009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1599589009
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1402077878
Short name T231
Test name
Test status
Simulation time 456881503 ps
CPU time 24.26 seconds
Started Jul 17 05:16:05 PM PDT 24
Finished Jul 17 05:16:36 PM PDT 24
Peak memory 250464 kb
Host smart-84eb614f-0803-4623-9da5-3a6bfef1b599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402077878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1402077878
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1540511981
Short name T536
Test name
Test status
Simulation time 72902273 ps
CPU time 3.02 seconds
Started Jul 17 05:17:32 PM PDT 24
Finished Jul 17 05:17:35 PM PDT 24
Peak memory 217768 kb
Host smart-1ec9065a-bcc3-41cd-8e19-f34a4f415d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540511981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1540511981
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.824814434
Short name T504
Test name
Test status
Simulation time 14405899489 ps
CPU time 228.57 seconds
Started Jul 17 05:15:55 PM PDT 24
Finished Jul 17 05:19:53 PM PDT 24
Peak memory 275172 kb
Host smart-2b5d6b85-8ff4-400c-8fb9-bbb7389e7270
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824814434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.824814434
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.2258607812
Short name T490
Test name
Test status
Simulation time 32922267275 ps
CPU time 386.63 seconds
Started Jul 17 05:15:54 PM PDT 24
Finished Jul 17 05:22:31 PM PDT 24
Peak memory 421648 kb
Host smart-dd4d7d6f-7f1c-4818-9793-da0ae2f1a4b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2258607812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.2258607812
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3260567717
Short name T711
Test name
Test status
Simulation time 24386428 ps
CPU time 0.99 seconds
Started Jul 17 05:15:53 PM PDT 24
Finished Jul 17 05:16:04 PM PDT 24
Peak memory 208620 kb
Host smart-7fed376e-c50f-494f-a547-c32fc3307198
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260567717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3260567717
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3211330208
Short name T865
Test name
Test status
Simulation time 77701848 ps
CPU time 0.87 seconds
Started Jul 17 05:17:56 PM PDT 24
Finished Jul 17 05:18:04 PM PDT 24
Peak memory 208176 kb
Host smart-9e1c5bfd-73f8-4114-846b-111511394abc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211330208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3211330208
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.709818717
Short name T637
Test name
Test status
Simulation time 508329544 ps
CPU time 16.1 seconds
Started Jul 17 05:15:55 PM PDT 24
Finished Jul 17 05:16:21 PM PDT 24
Peak memory 217744 kb
Host smart-fbba05a7-5fd9-4507-9db6-e95c90aaef74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709818717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.709818717
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1226611332
Short name T500
Test name
Test status
Simulation time 201379006 ps
CPU time 3.63 seconds
Started Jul 17 05:15:56 PM PDT 24
Finished Jul 17 05:16:10 PM PDT 24
Peak memory 216520 kb
Host smart-26be6f91-432f-42db-b28c-a602a8bddd78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226611332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1226611332
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.377182605
Short name T722
Test name
Test status
Simulation time 47597391 ps
CPU time 1.47 seconds
Started Jul 17 05:15:53 PM PDT 24
Finished Jul 17 05:16:04 PM PDT 24
Peak memory 217668 kb
Host smart-b1d41cda-9dee-4d1b-965d-fdf6f031d4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377182605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.377182605
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.855017680
Short name T49
Test name
Test status
Simulation time 1305898048 ps
CPU time 12.82 seconds
Started Jul 17 05:15:57 PM PDT 24
Finished Jul 17 05:16:20 PM PDT 24
Peak memory 225540 kb
Host smart-59959078-3246-4f03-a629-f9db1a9b77d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855017680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.855017680
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2669889276
Short name T492
Test name
Test status
Simulation time 408883748 ps
CPU time 10.87 seconds
Started Jul 17 05:17:48 PM PDT 24
Finished Jul 17 05:18:01 PM PDT 24
Peak memory 225448 kb
Host smart-5cd9a5b0-90df-4a81-90c6-48083a0350e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669889276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2669889276
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2150050154
Short name T262
Test name
Test status
Simulation time 361010114 ps
CPU time 9.83 seconds
Started Jul 17 05:15:58 PM PDT 24
Finished Jul 17 05:16:18 PM PDT 24
Peak memory 225452 kb
Host smart-d65fff0e-b9a9-4422-a363-526fa5af2b68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150050154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2150050154
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1832808590
Short name T634
Test name
Test status
Simulation time 333199406 ps
CPU time 5.8 seconds
Started Jul 17 05:16:08 PM PDT 24
Finished Jul 17 05:16:19 PM PDT 24
Peak memory 225540 kb
Host smart-0190715f-27f4-469d-9344-d88b5b79e9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832808590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1832808590
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2310459808
Short name T328
Test name
Test status
Simulation time 117143618 ps
CPU time 3.24 seconds
Started Jul 17 05:15:56 PM PDT 24
Finished Jul 17 05:16:10 PM PDT 24
Peak memory 217164 kb
Host smart-2d7709c1-8fc9-452b-a206-94d5b823716b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310459808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2310459808
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2953092198
Short name T274
Test name
Test status
Simulation time 749426144 ps
CPU time 23.87 seconds
Started Jul 17 05:17:47 PM PDT 24
Finished Jul 17 05:18:12 PM PDT 24
Peak memory 250428 kb
Host smart-54e531fb-82ac-40f0-af18-c97f86bfe684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953092198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2953092198
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.615047729
Short name T228
Test name
Test status
Simulation time 92861095 ps
CPU time 9 seconds
Started Jul 17 05:17:00 PM PDT 24
Finished Jul 17 05:17:10 PM PDT 24
Peak memory 250476 kb
Host smart-d716dabf-c773-4f6c-a8ca-143af40c83dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615047729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.615047729
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1825288717
Short name T588
Test name
Test status
Simulation time 12935024030 ps
CPU time 126.61 seconds
Started Jul 17 05:17:33 PM PDT 24
Finished Jul 17 05:19:40 PM PDT 24
Peak memory 266904 kb
Host smart-166b8299-55b1-4665-9c28-8f3857c86211
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825288717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1825288717
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3063938932
Short name T36
Test name
Test status
Simulation time 11588004 ps
CPU time 0.91 seconds
Started Jul 17 05:15:58 PM PDT 24
Finished Jul 17 05:16:09 PM PDT 24
Peak memory 208424 kb
Host smart-15d81afb-733b-4b49-9afe-f0191eb61d67
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063938932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3063938932
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3276794464
Short name T657
Test name
Test status
Simulation time 91989733 ps
CPU time 1.02 seconds
Started Jul 17 05:16:03 PM PDT 24
Finished Jul 17 05:16:12 PM PDT 24
Peak memory 207984 kb
Host smart-6797938c-cd84-4906-bbe6-4b6ca8bf6f8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276794464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3276794464
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.130240434
Short name T349
Test name
Test status
Simulation time 563010904 ps
CPU time 9.89 seconds
Started Jul 17 05:17:56 PM PDT 24
Finished Jul 17 05:18:13 PM PDT 24
Peak memory 225512 kb
Host smart-b0d3bdf5-8d50-47c2-90d4-1910df78e656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130240434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.130240434
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1056077731
Short name T822
Test name
Test status
Simulation time 243496638 ps
CPU time 3.85 seconds
Started Jul 17 05:15:58 PM PDT 24
Finished Jul 17 05:16:13 PM PDT 24
Peak memory 217212 kb
Host smart-7f59dec6-0554-45aa-9bf2-8d325bcd2e1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056077731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1056077731
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3620340814
Short name T702
Test name
Test status
Simulation time 106622905 ps
CPU time 4.66 seconds
Started Jul 17 05:17:33 PM PDT 24
Finished Jul 17 05:17:38 PM PDT 24
Peak memory 217724 kb
Host smart-2cef2dcd-7905-48aa-8196-86acb4a5e63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620340814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3620340814
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.3662805029
Short name T48
Test name
Test status
Simulation time 309754454 ps
CPU time 13.55 seconds
Started Jul 17 05:17:55 PM PDT 24
Finished Jul 17 05:18:15 PM PDT 24
Peak memory 218408 kb
Host smart-61b4161a-8942-4bc5-80df-cad0dae3ba84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662805029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.3662805029
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.4104916049
Short name T725
Test name
Test status
Simulation time 1489254697 ps
CPU time 13.77 seconds
Started Jul 17 05:17:57 PM PDT 24
Finished Jul 17 05:18:17 PM PDT 24
Peak memory 225444 kb
Host smart-70b98674-b79f-4e35-88e8-41ecc12dab49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104916049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.4104916049
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2098023167
Short name T796
Test name
Test status
Simulation time 798804439 ps
CPU time 6 seconds
Started Jul 17 05:17:55 PM PDT 24
Finished Jul 17 05:18:07 PM PDT 24
Peak memory 217704 kb
Host smart-844381ce-8ab3-4652-bc08-d55978e5c2a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098023167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2098023167
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1981000712
Short name T608
Test name
Test status
Simulation time 913092414 ps
CPU time 6.98 seconds
Started Jul 17 05:16:01 PM PDT 24
Finished Jul 17 05:16:17 PM PDT 24
Peak memory 224352 kb
Host smart-6e1e278e-fa39-407f-aae1-c02822b2d373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981000712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1981000712
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2701756894
Short name T484
Test name
Test status
Simulation time 80589981 ps
CPU time 2.74 seconds
Started Jul 17 05:15:56 PM PDT 24
Finished Jul 17 05:16:08 PM PDT 24
Peak memory 217140 kb
Host smart-15e90b5e-b0c0-469d-9860-8ae49b2480f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701756894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2701756894
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1962891574
Short name T217
Test name
Test status
Simulation time 1068712942 ps
CPU time 29.41 seconds
Started Jul 17 05:15:54 PM PDT 24
Finished Jul 17 05:16:33 PM PDT 24
Peak memory 250484 kb
Host smart-9264ac0f-04a7-414f-96a4-ffe61e0320e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962891574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1962891574
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3756134498
Short name T459
Test name
Test status
Simulation time 67058593 ps
CPU time 3.93 seconds
Started Jul 17 05:17:54 PM PDT 24
Finished Jul 17 05:18:04 PM PDT 24
Peak memory 222356 kb
Host smart-1c20c509-b30a-46f3-b5ec-0ce7c5ce1c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756134498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3756134498
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1972571044
Short name T694
Test name
Test status
Simulation time 1184775494 ps
CPU time 44.26 seconds
Started Jul 17 05:17:28 PM PDT 24
Finished Jul 17 05:18:13 PM PDT 24
Peak memory 271208 kb
Host smart-e08a9867-8e97-46b6-815d-2c0184bfb263
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972571044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1972571044
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2256957197
Short name T436
Test name
Test status
Simulation time 36873727 ps
CPU time 0.78 seconds
Started Jul 17 05:17:56 PM PDT 24
Finished Jul 17 05:18:03 PM PDT 24
Peak memory 208216 kb
Host smart-791064b2-2f80-4c6f-9d87-636deb6ef8a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256957197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2256957197
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1350076533
Short name T613
Test name
Test status
Simulation time 100634379 ps
CPU time 1.3 seconds
Started Jul 17 05:16:39 PM PDT 24
Finished Jul 17 05:16:42 PM PDT 24
Peak memory 208696 kb
Host smart-5ecce1fc-1986-48f6-b55d-9c708c533a8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350076533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1350076533
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2647239754
Short name T866
Test name
Test status
Simulation time 229050920 ps
CPU time 11.66 seconds
Started Jul 17 05:17:22 PM PDT 24
Finished Jul 17 05:17:34 PM PDT 24
Peak memory 217876 kb
Host smart-f4c8ef0e-e656-4799-b0eb-97c74b6b1491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647239754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2647239754
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.2947820991
Short name T762
Test name
Test status
Simulation time 112541804 ps
CPU time 2.75 seconds
Started Jul 17 05:17:37 PM PDT 24
Finished Jul 17 05:17:41 PM PDT 24
Peak memory 217372 kb
Host smart-c5d0cce2-d2a5-462d-8b23-18ae062379e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947820991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.2947820991
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3236891741
Short name T259
Test name
Test status
Simulation time 246276792 ps
CPU time 2.78 seconds
Started Jul 17 05:15:57 PM PDT 24
Finished Jul 17 05:16:10 PM PDT 24
Peak memory 217940 kb
Host smart-f65d784d-9aa2-4bde-8842-53e9b9c7be68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236891741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3236891741
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3996210916
Short name T684
Test name
Test status
Simulation time 1224701738 ps
CPU time 18.8 seconds
Started Jul 17 05:16:37 PM PDT 24
Finished Jul 17 05:16:57 PM PDT 24
Peak memory 225316 kb
Host smart-f962a56d-906c-47f4-9af6-1ddb33efd9c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996210916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3996210916
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3526475083
Short name T698
Test name
Test status
Simulation time 309703969 ps
CPU time 10.26 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:18:04 PM PDT 24
Peak memory 225496 kb
Host smart-839a9611-744e-4933-923b-736a0ab27f14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526475083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3526475083
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3490625751
Short name T708
Test name
Test status
Simulation time 911059558 ps
CPU time 11.89 seconds
Started Jul 17 05:17:01 PM PDT 24
Finished Jul 17 05:17:14 PM PDT 24
Peak memory 224880 kb
Host smart-9d69b7ba-019b-43fe-8131-6d67850b6f5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490625751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3490625751
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.765901604
Short name T56
Test name
Test status
Simulation time 343191288 ps
CPU time 12.57 seconds
Started Jul 17 05:17:52 PM PDT 24
Finished Jul 17 05:18:11 PM PDT 24
Peak memory 225748 kb
Host smart-32dac3df-31c6-4282-85ff-37bae4c06fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765901604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.765901604
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1508388881
Short name T609
Test name
Test status
Simulation time 140224322 ps
CPU time 3.76 seconds
Started Jul 17 05:16:03 PM PDT 24
Finished Jul 17 05:16:15 PM PDT 24
Peak memory 217188 kb
Host smart-4641f2d1-87af-42a3-bb93-046056f42fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508388881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1508388881
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.466103511
Short name T701
Test name
Test status
Simulation time 1023737153 ps
CPU time 29.81 seconds
Started Jul 17 05:16:03 PM PDT 24
Finished Jul 17 05:16:41 PM PDT 24
Peak memory 250352 kb
Host smart-8f2d82f9-0d97-431c-97a4-29eede1e3e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466103511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.466103511
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1252294279
Short name T351
Test name
Test status
Simulation time 120447560 ps
CPU time 7.43 seconds
Started Jul 17 05:16:03 PM PDT 24
Finished Jul 17 05:16:19 PM PDT 24
Peak memory 249288 kb
Host smart-ca8ba3ec-559d-4456-88c7-82882d82f50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252294279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1252294279
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2775699612
Short name T681
Test name
Test status
Simulation time 4015602816 ps
CPU time 52.23 seconds
Started Jul 17 05:17:57 PM PDT 24
Finished Jul 17 05:18:55 PM PDT 24
Peak memory 225568 kb
Host smart-69d2d26b-5fd7-4814-a299-1c6c9d179cf3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775699612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2775699612
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.3366120549
Short name T539
Test name
Test status
Simulation time 19504020715 ps
CPU time 263.04 seconds
Started Jul 17 05:16:36 PM PDT 24
Finished Jul 17 05:21:00 PM PDT 24
Peak memory 496400 kb
Host smart-eaf23715-cfab-4f2b-9fbd-902c8b6d7703
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3366120549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.3366120549
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3285941273
Short name T42
Test name
Test status
Simulation time 42631671 ps
CPU time 1 seconds
Started Jul 17 05:17:01 PM PDT 24
Finished Jul 17 05:17:03 PM PDT 24
Peak memory 208576 kb
Host smart-adcd829f-3641-42ea-82fd-22b784f1faa2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285941273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.3285941273
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2158203006
Short name T542
Test name
Test status
Simulation time 226201082 ps
CPU time 0.89 seconds
Started Jul 17 05:17:13 PM PDT 24
Finished Jul 17 05:17:15 PM PDT 24
Peak memory 208372 kb
Host smart-10d9a4cd-7c8d-4d30-a234-5a80f972a147
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158203006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2158203006
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.140277310
Short name T843
Test name
Test status
Simulation time 439640041 ps
CPU time 15.65 seconds
Started Jul 17 05:16:38 PM PDT 24
Finished Jul 17 05:16:56 PM PDT 24
Peak memory 217760 kb
Host smart-44470f8e-c1d0-4b8a-a488-b2e4ed74ee00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140277310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.140277310
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.751082404
Short name T721
Test name
Test status
Simulation time 611990448 ps
CPU time 2.66 seconds
Started Jul 17 05:17:59 PM PDT 24
Finished Jul 17 05:18:07 PM PDT 24
Peak memory 216608 kb
Host smart-08ac03f5-a289-4e71-bf08-a0f23104622d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751082404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.751082404
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2196810634
Short name T525
Test name
Test status
Simulation time 69201254 ps
CPU time 2.66 seconds
Started Jul 17 05:16:39 PM PDT 24
Finished Jul 17 05:16:43 PM PDT 24
Peak memory 217712 kb
Host smart-61f2c2df-180e-4888-82a3-228431d9ddd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196810634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2196810634
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2468168836
Short name T512
Test name
Test status
Simulation time 212457741 ps
CPU time 8.83 seconds
Started Jul 17 05:17:51 PM PDT 24
Finished Jul 17 05:18:03 PM PDT 24
Peak memory 225568 kb
Host smart-08763cdb-43f2-49f3-896b-a61d2b2478a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468168836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2468168836
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3036160310
Short name T418
Test name
Test status
Simulation time 317076113 ps
CPU time 8.9 seconds
Started Jul 17 05:17:47 PM PDT 24
Finished Jul 17 05:17:57 PM PDT 24
Peak memory 225492 kb
Host smart-d84b565f-9f4c-4013-949c-5d017d3b4e8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036160310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3036160310
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3601207046
Short name T424
Test name
Test status
Simulation time 320627434 ps
CPU time 10.59 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:18:04 PM PDT 24
Peak memory 225476 kb
Host smart-35482223-535b-4b4b-b45c-37e2adfb4b8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601207046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
3601207046
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2807846670
Short name T642
Test name
Test status
Simulation time 1388964448 ps
CPU time 10.81 seconds
Started Jul 17 05:16:39 PM PDT 24
Finished Jul 17 05:16:51 PM PDT 24
Peak memory 225116 kb
Host smart-09b9af85-9f69-4b77-9ad0-0371c7c9c648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807846670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2807846670
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3233852365
Short name T445
Test name
Test status
Simulation time 31040373 ps
CPU time 1.63 seconds
Started Jul 17 05:17:51 PM PDT 24
Finished Jul 17 05:17:57 PM PDT 24
Peak memory 213460 kb
Host smart-dd9e7963-efc6-4318-8be2-c3a3c07438db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233852365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3233852365
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2223117758
Short name T387
Test name
Test status
Simulation time 267509700 ps
CPU time 25.94 seconds
Started Jul 17 05:16:37 PM PDT 24
Finished Jul 17 05:17:04 PM PDT 24
Peak memory 250504 kb
Host smart-3fd3a549-f2f1-4922-9c7a-45b6f068cdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223117758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2223117758
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1134854670
Short name T488
Test name
Test status
Simulation time 240326382 ps
CPU time 9.26 seconds
Started Jul 17 05:16:37 PM PDT 24
Finished Jul 17 05:16:48 PM PDT 24
Peak memory 250464 kb
Host smart-5dbca520-34f0-423d-bb48-edbb51d6ba99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134854670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1134854670
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.121120619
Short name T767
Test name
Test status
Simulation time 6863936708 ps
CPU time 51.79 seconds
Started Jul 17 05:17:47 PM PDT 24
Finished Jul 17 05:18:40 PM PDT 24
Peak memory 244652 kb
Host smart-49f34a38-273d-469b-a5f0-edadf1b9ef23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121120619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.121120619
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.3376445102
Short name T647
Test name
Test status
Simulation time 57338011800 ps
CPU time 463.61 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:25:38 PM PDT 24
Peak memory 332716 kb
Host smart-44b4ae69-3dfd-4200-894d-a328387ee054
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3376445102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.3376445102
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3235147282
Short name T382
Test name
Test status
Simulation time 56562302 ps
CPU time 0.87 seconds
Started Jul 17 05:17:54 PM PDT 24
Finished Jul 17 05:18:01 PM PDT 24
Peak memory 212336 kb
Host smart-297fb97a-bf51-4fa8-b6e0-cd52f53cb210
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235147282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3235147282
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.423976048
Short name T597
Test name
Test status
Simulation time 16157869 ps
CPU time 1.1 seconds
Started Jul 17 05:17:12 PM PDT 24
Finished Jul 17 05:17:14 PM PDT 24
Peak memory 208420 kb
Host smart-80b5bd05-7da8-42ca-a1b2-adcca4b073dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423976048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.423976048
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1053752146
Short name T524
Test name
Test status
Simulation time 835481601 ps
CPU time 10.91 seconds
Started Jul 17 05:17:13 PM PDT 24
Finished Jul 17 05:17:26 PM PDT 24
Peak memory 225568 kb
Host smart-8514d07a-7fb1-47e3-b310-82f2453a20ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053752146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1053752146
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.409727314
Short name T23
Test name
Test status
Simulation time 3608396143 ps
CPU time 16.58 seconds
Started Jul 17 05:17:48 PM PDT 24
Finished Jul 17 05:18:07 PM PDT 24
Peak memory 217256 kb
Host smart-c4c50ff6-45b2-402d-a3f3-ed965396935d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409727314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.409727314
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1206717114
Short name T285
Test name
Test status
Simulation time 1451487638 ps
CPU time 3.27 seconds
Started Jul 17 05:17:16 PM PDT 24
Finished Jul 17 05:17:21 PM PDT 24
Peak memory 217636 kb
Host smart-f76f843d-32f5-49be-8f44-207d38446f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206717114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1206717114
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1129767618
Short name T325
Test name
Test status
Simulation time 512368012 ps
CPU time 16.28 seconds
Started Jul 17 05:17:49 PM PDT 24
Finished Jul 17 05:18:08 PM PDT 24
Peak memory 218416 kb
Host smart-e5db514a-00ca-4b9e-b0c6-86373995cde5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129767618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1129767618
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1141743789
Short name T731
Test name
Test status
Simulation time 239417974 ps
CPU time 10.44 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:18:04 PM PDT 24
Peak memory 225500 kb
Host smart-39bfbd8e-5ccb-4f58-baae-eb2cbe1bb414
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141743789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1141743789
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.78241695
Short name T852
Test name
Test status
Simulation time 922137471 ps
CPU time 8.66 seconds
Started Jul 17 05:17:13 PM PDT 24
Finished Jul 17 05:17:23 PM PDT 24
Peak memory 217712 kb
Host smart-b098c758-fd0e-4166-8505-2dbcf819cbe7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78241695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.78241695
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1195093550
Short name T724
Test name
Test status
Simulation time 4636676402 ps
CPU time 9.38 seconds
Started Jul 17 05:17:55 PM PDT 24
Finished Jul 17 05:18:11 PM PDT 24
Peak memory 225620 kb
Host smart-275f8c45-e761-40e0-8630-b06bdfa95203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195093550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1195093550
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.697796482
Short name T304
Test name
Test status
Simulation time 1426258154 ps
CPU time 4.73 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:17:59 PM PDT 24
Peak memory 217160 kb
Host smart-c635e7e5-1217-432a-8f24-963457bde987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697796482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.697796482
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.561106872
Short name T812
Test name
Test status
Simulation time 811849766 ps
CPU time 27.74 seconds
Started Jul 17 05:17:19 PM PDT 24
Finished Jul 17 05:17:48 PM PDT 24
Peak memory 250468 kb
Host smart-18675041-2941-46f7-af82-8c16f38bb889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561106872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.561106872
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.4057425868
Short name T771
Test name
Test status
Simulation time 167562396 ps
CPU time 6.96 seconds
Started Jul 17 05:17:14 PM PDT 24
Finished Jul 17 05:17:22 PM PDT 24
Peak memory 242276 kb
Host smart-9f7fd76e-0f60-436e-8fb7-e161fa651c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057425868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.4057425868
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.619274658
Short name T849
Test name
Test status
Simulation time 14183382422 ps
CPU time 75.65 seconds
Started Jul 17 05:17:12 PM PDT 24
Finished Jul 17 05:18:29 PM PDT 24
Peak memory 225596 kb
Host smart-b9e87eb9-9948-4112-83be-1808b2500945
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619274658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.619274658
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.813026561
Short name T41
Test name
Test status
Simulation time 12071020 ps
CPU time 0.93 seconds
Started Jul 17 05:17:53 PM PDT 24
Finished Jul 17 05:18:00 PM PDT 24
Peak memory 208412 kb
Host smart-b7fd103b-1436-4832-81b0-293399cafe08
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813026561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.813026561
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2558245536
Short name T378
Test name
Test status
Simulation time 38424472 ps
CPU time 1.04 seconds
Started Jul 17 05:17:13 PM PDT 24
Finished Jul 17 05:17:15 PM PDT 24
Peak memory 208392 kb
Host smart-4fa0bf2b-9d15-4648-8c44-f671dd547f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558245536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2558245536
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1829579158
Short name T419
Test name
Test status
Simulation time 293330990 ps
CPU time 9.91 seconds
Started Jul 17 05:17:13 PM PDT 24
Finished Jul 17 05:17:24 PM PDT 24
Peak memory 225340 kb
Host smart-b1f9ddde-98c3-4558-86ef-71e354a1eb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829579158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1829579158
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3586737268
Short name T27
Test name
Test status
Simulation time 421687333 ps
CPU time 3.57 seconds
Started Jul 17 05:17:13 PM PDT 24
Finished Jul 17 05:17:18 PM PDT 24
Peak memory 217184 kb
Host smart-33737476-a5ee-4550-a278-2a040e4d2564
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586737268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3586737268
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2503518349
Short name T526
Test name
Test status
Simulation time 451108945 ps
CPU time 3.23 seconds
Started Jul 17 05:17:46 PM PDT 24
Finished Jul 17 05:17:50 PM PDT 24
Peak memory 217732 kb
Host smart-b628b4fa-ecf0-4f80-8cfc-14b4a42dded4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503518349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2503518349
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2874798642
Short name T495
Test name
Test status
Simulation time 417136208 ps
CPU time 11.06 seconds
Started Jul 17 05:17:21 PM PDT 24
Finished Jul 17 05:17:33 PM PDT 24
Peak memory 217776 kb
Host smart-d45538a3-ecf0-43a6-8a80-276d1e831666
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874798642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2874798642
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1322709169
Short name T837
Test name
Test status
Simulation time 1249265246 ps
CPU time 13.97 seconds
Started Jul 17 05:17:16 PM PDT 24
Finished Jul 17 05:17:33 PM PDT 24
Peak memory 225496 kb
Host smart-9cc58c76-ece3-4a59-a0fc-f59d9057bfb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322709169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1322709169
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2204443069
Short name T659
Test name
Test status
Simulation time 1118903385 ps
CPU time 11.82 seconds
Started Jul 17 05:17:56 PM PDT 24
Finished Jul 17 05:18:15 PM PDT 24
Peak memory 217660 kb
Host smart-84c1964b-16c4-4ae4-ac6a-1e9d69858afc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204443069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2204443069
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.376105689
Short name T556
Test name
Test status
Simulation time 301524144 ps
CPU time 9.91 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:18:04 PM PDT 24
Peak memory 225276 kb
Host smart-e904c3a7-818f-48bf-9374-1af8048fb9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376105689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.376105689
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.968259627
Short name T269
Test name
Test status
Simulation time 61352458 ps
CPU time 2.1 seconds
Started Jul 17 05:17:15 PM PDT 24
Finished Jul 17 05:17:19 PM PDT 24
Peak memory 217392 kb
Host smart-2d6e4486-266d-440c-b0b9-82a7895bda48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968259627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.968259627
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3409448688
Short name T88
Test name
Test status
Simulation time 617242234 ps
CPU time 23.78 seconds
Started Jul 17 05:17:16 PM PDT 24
Finished Jul 17 05:17:42 PM PDT 24
Peak memory 250532 kb
Host smart-809fe233-9979-4264-a379-2a4c27510c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409448688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3409448688
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.553848300
Short name T519
Test name
Test status
Simulation time 152522235 ps
CPU time 9.86 seconds
Started Jul 17 05:17:56 PM PDT 24
Finished Jul 17 05:18:13 PM PDT 24
Peak memory 249968 kb
Host smart-c72d06ad-0d2e-4da3-a9cd-1d49523c39de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553848300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.553848300
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2834390190
Short name T347
Test name
Test status
Simulation time 3993509505 ps
CPU time 94.75 seconds
Started Jul 17 05:17:19 PM PDT 24
Finished Jul 17 05:18:55 PM PDT 24
Peak memory 278476 kb
Host smart-213b3bdc-a461-4ed7-9a59-143b0947156c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834390190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2834390190
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1784398143
Short name T605
Test name
Test status
Simulation time 34819602 ps
CPU time 0.85 seconds
Started Jul 17 05:17:16 PM PDT 24
Finished Jul 17 05:17:19 PM PDT 24
Peak memory 208388 kb
Host smart-f8c51bfb-e5d6-4920-a540-5248c3313d7a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784398143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1784398143
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2192631205
Short name T414
Test name
Test status
Simulation time 28464821 ps
CPU time 1.35 seconds
Started Jul 17 05:17:53 PM PDT 24
Finished Jul 17 05:17:59 PM PDT 24
Peak memory 208440 kb
Host smart-fc52876f-a004-4d54-85a4-617436f6c7b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192631205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2192631205
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.3720235888
Short name T610
Test name
Test status
Simulation time 961479948 ps
CPU time 11.82 seconds
Started Jul 17 05:17:16 PM PDT 24
Finished Jul 17 05:17:31 PM PDT 24
Peak memory 217724 kb
Host smart-ec2e9c0e-b6aa-4cb1-acfa-891659e2967d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720235888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3720235888
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.864950362
Short name T644
Test name
Test status
Simulation time 112128786 ps
CPU time 3.76 seconds
Started Jul 17 05:17:11 PM PDT 24
Finished Jul 17 05:17:15 PM PDT 24
Peak memory 216664 kb
Host smart-862af3b1-ccea-4e99-8779-2601d6f7e4ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864950362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.864950362
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1009468667
Short name T764
Test name
Test status
Simulation time 59852850 ps
CPU time 1.62 seconds
Started Jul 17 05:17:18 PM PDT 24
Finished Jul 17 05:17:22 PM PDT 24
Peak memory 221548 kb
Host smart-e15087f2-ff77-45cd-a959-d8b855f21c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009468667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1009468667
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2959970780
Short name T430
Test name
Test status
Simulation time 1324444944 ps
CPU time 13.57 seconds
Started Jul 17 05:17:14 PM PDT 24
Finished Jul 17 05:17:29 PM PDT 24
Peak memory 218436 kb
Host smart-4e015b39-a875-4da0-b156-ed9a8c560c2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959970780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2959970780
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.4043166039
Short name T434
Test name
Test status
Simulation time 1840801444 ps
CPU time 10.33 seconds
Started Jul 17 05:17:15 PM PDT 24
Finished Jul 17 05:17:27 PM PDT 24
Peak memory 225684 kb
Host smart-66048257-2926-4577-913c-f696e6454c4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043166039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.4043166039
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3306592913
Short name T522
Test name
Test status
Simulation time 458265732 ps
CPU time 8.59 seconds
Started Jul 17 05:17:49 PM PDT 24
Finished Jul 17 05:18:01 PM PDT 24
Peak memory 217704 kb
Host smart-bd12839c-cadd-4445-9bab-082dffea0335
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306592913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3306592913
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.807294480
Short name T52
Test name
Test status
Simulation time 794974153 ps
CPU time 9.85 seconds
Started Jul 17 05:17:17 PM PDT 24
Finished Jul 17 05:17:29 PM PDT 24
Peak memory 225552 kb
Host smart-478789ee-2e0d-4c1f-81c6-890d545983ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807294480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.807294480
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2870516515
Short name T334
Test name
Test status
Simulation time 122065652 ps
CPU time 2.29 seconds
Started Jul 17 05:17:52 PM PDT 24
Finished Jul 17 05:18:00 PM PDT 24
Peak memory 223256 kb
Host smart-6c7101c6-130f-45e4-8aa1-df1f5bbe65ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870516515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2870516515
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.682918979
Short name T266
Test name
Test status
Simulation time 1170245189 ps
CPU time 26.72 seconds
Started Jul 17 05:17:45 PM PDT 24
Finished Jul 17 05:18:13 PM PDT 24
Peak memory 250484 kb
Host smart-0860eb81-ebcc-4f74-a80e-43f7f58a23c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682918979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.682918979
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2055965472
Short name T616
Test name
Test status
Simulation time 81900877 ps
CPU time 8.03 seconds
Started Jul 17 05:17:47 PM PDT 24
Finished Jul 17 05:17:56 PM PDT 24
Peak memory 249960 kb
Host smart-40b36d17-9a5d-4f1a-83f2-568f6282e767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055965472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2055965472
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3365154977
Short name T636
Test name
Test status
Simulation time 3406545050 ps
CPU time 62.44 seconds
Started Jul 17 05:17:52 PM PDT 24
Finished Jul 17 05:18:59 PM PDT 24
Peak memory 246912 kb
Host smart-ede40344-e89d-4c01-a57b-62fd78ba0548
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365154977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3365154977
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2130597104
Short name T868
Test name
Test status
Simulation time 23458545 ps
CPU time 0.79 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:17:53 PM PDT 24
Peak memory 208352 kb
Host smart-9c2b2ec4-011f-44fd-ad0d-9ffdf541513c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130597104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2130597104
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.852686420
Short name T392
Test name
Test status
Simulation time 46654750 ps
CPU time 1.05 seconds
Started Jul 17 05:17:18 PM PDT 24
Finished Jul 17 05:17:21 PM PDT 24
Peak memory 208368 kb
Host smart-9b3b6425-eaa9-45db-83bb-ca846a5a73ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852686420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.852686420
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3775111658
Short name T630
Test name
Test status
Simulation time 1570473808 ps
CPU time 9.44 seconds
Started Jul 17 05:17:17 PM PDT 24
Finished Jul 17 05:17:29 PM PDT 24
Peak memory 217672 kb
Host smart-d8a9acce-9ee0-49ab-89f5-b02933ae65bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775111658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3775111658
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3079503907
Short name T265
Test name
Test status
Simulation time 870302589 ps
CPU time 5.68 seconds
Started Jul 17 05:17:14 PM PDT 24
Finished Jul 17 05:17:21 PM PDT 24
Peak memory 216640 kb
Host smart-628ee84c-776d-46c2-9d8a-98f318967918
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079503907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3079503907
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3162206220
Short name T676
Test name
Test status
Simulation time 25620817 ps
CPU time 2.09 seconds
Started Jul 17 05:17:19 PM PDT 24
Finished Jul 17 05:17:22 PM PDT 24
Peak memory 221548 kb
Host smart-967f1731-04b2-429d-a2d2-ab4a65ef96ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162206220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3162206220
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.439231516
Short name T726
Test name
Test status
Simulation time 340066265 ps
CPU time 15.08 seconds
Started Jul 17 05:17:51 PM PDT 24
Finished Jul 17 05:18:11 PM PDT 24
Peak memory 219508 kb
Host smart-bac6bf58-a50e-40bc-9476-b32932acedc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439231516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.439231516
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2560807906
Short name T816
Test name
Test status
Simulation time 4618729514 ps
CPU time 7.99 seconds
Started Jul 17 05:17:16 PM PDT 24
Finished Jul 17 05:17:27 PM PDT 24
Peak memory 225552 kb
Host smart-1cd2fdb8-d748-4bae-93c7-19ef5ba87532
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560807906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2560807906
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3553013590
Short name T29
Test name
Test status
Simulation time 943997310 ps
CPU time 6.56 seconds
Started Jul 17 05:17:17 PM PDT 24
Finished Jul 17 05:17:26 PM PDT 24
Peak memory 217712 kb
Host smart-3f2b5777-5eb4-41db-b6f4-1942987e8238
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553013590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3553013590
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.968694502
Short name T169
Test name
Test status
Simulation time 1009825928 ps
CPU time 10.97 seconds
Started Jul 17 05:17:14 PM PDT 24
Finished Jul 17 05:17:26 PM PDT 24
Peak memory 225560 kb
Host smart-e862e79a-33f1-4408-8856-791d23b78fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968694502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.968694502
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2973853377
Short name T271
Test name
Test status
Simulation time 99377372 ps
CPU time 1.63 seconds
Started Jul 17 05:17:51 PM PDT 24
Finished Jul 17 05:17:57 PM PDT 24
Peak memory 213360 kb
Host smart-78c314e8-9099-4b48-8d61-28e87f3d5658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973853377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2973853377
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1425070429
Short name T157
Test name
Test status
Simulation time 568853830 ps
CPU time 22.38 seconds
Started Jul 17 05:17:16 PM PDT 24
Finished Jul 17 05:17:41 PM PDT 24
Peak memory 250440 kb
Host smart-dc793f24-dd5c-416e-b4e3-4f19b9b51bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425070429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1425070429
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3604637866
Short name T564
Test name
Test status
Simulation time 56116822 ps
CPU time 5.66 seconds
Started Jul 17 05:17:15 PM PDT 24
Finished Jul 17 05:17:23 PM PDT 24
Peak memory 242332 kb
Host smart-6f382994-2bb3-44a1-a4f2-64faaec32383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604637866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3604637866
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1277735182
Short name T288
Test name
Test status
Simulation time 1395792695 ps
CPU time 33.16 seconds
Started Jul 17 05:17:14 PM PDT 24
Finished Jul 17 05:17:49 PM PDT 24
Peak memory 217160 kb
Host smart-dc8e4272-245b-4a1e-b0e7-a74fed2b4d57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277735182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1277735182
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.4214645593
Short name T238
Test name
Test status
Simulation time 39467711 ps
CPU time 0.9 seconds
Started Jul 17 05:17:11 PM PDT 24
Finished Jul 17 05:17:12 PM PDT 24
Peak memory 208396 kb
Host smart-7b3b2f91-46a4-4723-84b6-665583abe0fb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214645593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.4214645593
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.954770219
Short name T86
Test name
Test status
Simulation time 35578361 ps
CPU time 1.17 seconds
Started Jul 17 05:13:41 PM PDT 24
Finished Jul 17 05:13:43 PM PDT 24
Peak memory 208440 kb
Host smart-1538abd1-4552-41ec-8893-0338f548e1a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954770219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.954770219
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.21426748
Short name T198
Test name
Test status
Simulation time 31986232 ps
CPU time 0.84 seconds
Started Jul 17 05:17:32 PM PDT 24
Finished Jul 17 05:17:34 PM PDT 24
Peak memory 208540 kb
Host smart-846e1e42-8249-4c72-bfd0-ead92c60230a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21426748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.21426748
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3601504589
Short name T50
Test name
Test status
Simulation time 1101251448 ps
CPU time 22.02 seconds
Started Jul 17 05:13:25 PM PDT 24
Finished Jul 17 05:13:48 PM PDT 24
Peak memory 225520 kb
Host smart-6a1a11bc-63d2-48ac-88e6-01aea24ea2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601504589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3601504589
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.119577900
Short name T332
Test name
Test status
Simulation time 217373366 ps
CPU time 3.45 seconds
Started Jul 17 05:13:44 PM PDT 24
Finished Jul 17 05:13:48 PM PDT 24
Peak memory 217180 kb
Host smart-a260c9a3-7771-4609-a1a9-ec5fcc3b3457
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119577900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.119577900
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3308383458
Short name T758
Test name
Test status
Simulation time 4049683929 ps
CPU time 59.73 seconds
Started Jul 17 05:13:41 PM PDT 24
Finished Jul 17 05:14:42 PM PDT 24
Peak memory 218444 kb
Host smart-37381d3c-a93d-4072-944f-5362be511830
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308383458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3308383458
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3183841591
Short name T360
Test name
Test status
Simulation time 575894219 ps
CPU time 7.58 seconds
Started Jul 17 05:13:43 PM PDT 24
Finished Jul 17 05:13:52 PM PDT 24
Peak memory 217220 kb
Host smart-82a03c86-c1cb-4f8e-8166-899e7217213a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183841591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.3
183841591
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.4104273852
Short name T553
Test name
Test status
Simulation time 552558681 ps
CPU time 8.02 seconds
Started Jul 17 05:13:41 PM PDT 24
Finished Jul 17 05:13:50 PM PDT 24
Peak memory 217700 kb
Host smart-6827f7f3-fc2e-490b-8a99-ba9f62aac5e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104273852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.4104273852
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.670650501
Short name T460
Test name
Test status
Simulation time 1604451501 ps
CPU time 11.37 seconds
Started Jul 17 05:13:41 PM PDT 24
Finished Jul 17 05:13:53 PM PDT 24
Peak memory 217084 kb
Host smart-d2c0aedb-25f4-4b7b-9d79-6f73eeeb5999
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670650501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.670650501
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3668447181
Short name T506
Test name
Test status
Simulation time 343883831 ps
CPU time 5.14 seconds
Started Jul 17 05:13:27 PM PDT 24
Finished Jul 17 05:13:34 PM PDT 24
Peak memory 217120 kb
Host smart-47df6d98-f855-41b3-a1b6-394fbd93e1bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668447181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3668447181
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2272428313
Short name T611
Test name
Test status
Simulation time 5141504035 ps
CPU time 59.33 seconds
Started Jul 17 05:13:28 PM PDT 24
Finished Jul 17 05:14:29 PM PDT 24
Peak memory 269700 kb
Host smart-a777b181-f024-461a-a547-169dbf0263cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272428313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2272428313
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2696146882
Short name T742
Test name
Test status
Simulation time 3006735200 ps
CPU time 7.06 seconds
Started Jul 17 05:13:28 PM PDT 24
Finished Jul 17 05:13:37 PM PDT 24
Peak memory 222816 kb
Host smart-4483776b-7a1b-49ef-9a3f-021e280ae56b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696146882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2696146882
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.92934722
Short name T821
Test name
Test status
Simulation time 426361999 ps
CPU time 2.53 seconds
Started Jul 17 05:13:25 PM PDT 24
Finished Jul 17 05:13:29 PM PDT 24
Peak memory 221756 kb
Host smart-dfe5f7e9-87d3-4e05-af5b-2b65ee348c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92934722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.92934722
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2558469160
Short name T74
Test name
Test status
Simulation time 218454158 ps
CPU time 4.09 seconds
Started Jul 17 05:13:29 PM PDT 24
Finished Jul 17 05:13:34 PM PDT 24
Peak memory 217304 kb
Host smart-b0d6d799-d4bd-4195-b530-1835e3aeb1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558469160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2558469160
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1143906870
Short name T565
Test name
Test status
Simulation time 365290794 ps
CPU time 14.65 seconds
Started Jul 17 05:17:39 PM PDT 24
Finished Jul 17 05:17:55 PM PDT 24
Peak memory 225552 kb
Host smart-6c55b43d-5033-4135-afb0-e7dd0b06ab3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143906870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1143906870
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.830304178
Short name T587
Test name
Test status
Simulation time 295444667 ps
CPU time 10.06 seconds
Started Jul 17 05:13:42 PM PDT 24
Finished Jul 17 05:13:53 PM PDT 24
Peak memory 217680 kb
Host smart-562eb1ec-1c69-481c-acca-20451566c4b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830304178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dig
est.830304178
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3267280385
Short name T221
Test name
Test status
Simulation time 323411274 ps
CPU time 8.72 seconds
Started Jul 17 05:13:40 PM PDT 24
Finished Jul 17 05:13:49 PM PDT 24
Peak memory 217732 kb
Host smart-da0bb88d-71aa-4a3b-8978-f15fc854179a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267280385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
267280385
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1759252652
Short name T140
Test name
Test status
Simulation time 488462012 ps
CPU time 17.95 seconds
Started Jul 17 05:13:26 PM PDT 24
Finished Jul 17 05:13:45 PM PDT 24
Peak memory 225560 kb
Host smart-67467923-cabf-4773-9338-bc54e147c6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759252652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1759252652
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3676613936
Short name T75
Test name
Test status
Simulation time 52045404 ps
CPU time 2.55 seconds
Started Jul 17 05:13:25 PM PDT 24
Finished Jul 17 05:13:28 PM PDT 24
Peak memory 223044 kb
Host smart-a8340335-64eb-44b9-997e-03ef1ddf403c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676613936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3676613936
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.564324302
Short name T327
Test name
Test status
Simulation time 268427980 ps
CPU time 36.69 seconds
Started Jul 17 05:13:27 PM PDT 24
Finished Jul 17 05:14:06 PM PDT 24
Peak memory 250560 kb
Host smart-01ed3969-9e2d-4852-b600-1dde308e32f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564324302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.564324302
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.27920722
Short name T735
Test name
Test status
Simulation time 69950690 ps
CPU time 7.3 seconds
Started Jul 17 05:17:34 PM PDT 24
Finished Jul 17 05:17:42 PM PDT 24
Peak memory 242896 kb
Host smart-09ad4848-1c63-4a6e-8bcd-b78971b06902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27920722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.27920722
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1785083793
Short name T90
Test name
Test status
Simulation time 7359003170 ps
CPU time 217.39 seconds
Started Jul 17 05:13:42 PM PDT 24
Finished Jul 17 05:17:20 PM PDT 24
Peak memory 266968 kb
Host smart-11c11d5b-7d32-4798-83b0-2951c9d09e04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785083793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1785083793
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.2594063130
Short name T151
Test name
Test status
Simulation time 146611847061 ps
CPU time 1156.71 seconds
Started Jul 17 05:13:42 PM PDT 24
Finished Jul 17 05:33:00 PM PDT 24
Peak memory 349200 kb
Host smart-601368ab-faa0-45be-bc80-106c92af233f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2594063130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.2594063130
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2995624989
Short name T729
Test name
Test status
Simulation time 32800478 ps
CPU time 0.77 seconds
Started Jul 17 05:13:28 PM PDT 24
Finished Jul 17 05:13:31 PM PDT 24
Peak memory 208260 kb
Host smart-74ed01ff-ab68-40e1-a24e-9a323a72df5b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995624989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2995624989
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.2880142404
Short name T546
Test name
Test status
Simulation time 39973804 ps
CPU time 1.2 seconds
Started Jul 17 05:17:19 PM PDT 24
Finished Jul 17 05:17:22 PM PDT 24
Peak memory 208532 kb
Host smart-2f3cd9b9-df40-4554-a2a0-ae40b199edab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880142404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2880142404
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2349801265
Short name T806
Test name
Test status
Simulation time 217569680 ps
CPU time 10.72 seconds
Started Jul 17 05:17:52 PM PDT 24
Finished Jul 17 05:18:08 PM PDT 24
Peak memory 217736 kb
Host smart-1dcc0513-8673-4daa-a604-8cf0d05dbb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349801265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2349801265
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3766368567
Short name T574
Test name
Test status
Simulation time 259220378 ps
CPU time 1.84 seconds
Started Jul 17 05:17:16 PM PDT 24
Finished Jul 17 05:17:20 PM PDT 24
Peak memory 217192 kb
Host smart-dc3d8975-ee3b-43ab-80be-7ebe9e2c54af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766368567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3766368567
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1952556388
Short name T860
Test name
Test status
Simulation time 20893876 ps
CPU time 1.73 seconds
Started Jul 17 05:17:51 PM PDT 24
Finished Jul 17 05:17:57 PM PDT 24
Peak memory 217760 kb
Host smart-220a9129-5171-4cf5-a981-f4aabf2c808a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952556388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1952556388
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.4011113562
Short name T483
Test name
Test status
Simulation time 352059238 ps
CPU time 10.4 seconds
Started Jul 17 05:17:51 PM PDT 24
Finished Jul 17 05:18:07 PM PDT 24
Peak memory 225564 kb
Host smart-01773736-eeac-461d-a8ec-ebf57fd7c8ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011113562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.4011113562
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2903673685
Short name T300
Test name
Test status
Simulation time 1314293616 ps
CPU time 8.95 seconds
Started Jul 17 05:17:16 PM PDT 24
Finished Jul 17 05:17:27 PM PDT 24
Peak memory 217652 kb
Host smart-b08ad6b1-1924-41ab-a700-e747ab6b3ee7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903673685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2903673685
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.670593986
Short name T384
Test name
Test status
Simulation time 691217282 ps
CPU time 12.28 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:18:07 PM PDT 24
Peak memory 217704 kb
Host smart-b3de5ccd-c1dd-4c18-866e-010e85cf33df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670593986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.670593986
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1497903531
Short name T359
Test name
Test status
Simulation time 2398210835 ps
CPU time 10.98 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:18:05 PM PDT 24
Peak memory 217896 kb
Host smart-91e89d3d-bd58-459c-a6c3-a9f8cc191f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497903531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1497903531
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3376070285
Short name T402
Test name
Test status
Simulation time 27010285 ps
CPU time 1.07 seconds
Started Jul 17 05:17:15 PM PDT 24
Finished Jul 17 05:17:18 PM PDT 24
Peak memory 217180 kb
Host smart-62af6564-dadf-4de1-926d-9429833997f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376070285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3376070285
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3617723805
Short name T570
Test name
Test status
Simulation time 365100334 ps
CPU time 30.74 seconds
Started Jul 17 05:17:52 PM PDT 24
Finished Jul 17 05:18:29 PM PDT 24
Peak memory 250428 kb
Host smart-ef4d4f75-307e-43ef-8180-4209779b12e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617723805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3617723805
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2166256176
Short name T839
Test name
Test status
Simulation time 519078682 ps
CPU time 5.92 seconds
Started Jul 17 05:17:16 PM PDT 24
Finished Jul 17 05:17:24 PM PDT 24
Peak memory 246472 kb
Host smart-a0b262db-aa3a-47ab-9c76-e46ccecf3645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166256176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2166256176
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1163125855
Short name T766
Test name
Test status
Simulation time 17334935802 ps
CPU time 143.67 seconds
Started Jul 17 05:17:51 PM PDT 24
Finished Jul 17 05:20:19 PM PDT 24
Peak memory 250588 kb
Host smart-404ba878-a4c1-475e-89ea-c478f9bed530
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163125855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1163125855
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.1397327712
Short name T132
Test name
Test status
Simulation time 16906686019 ps
CPU time 524.8 seconds
Started Jul 17 05:17:51 PM PDT 24
Finished Jul 17 05:26:41 PM PDT 24
Peak memory 250512 kb
Host smart-ff0f299e-ebf1-4c88-875a-9a3b2626afbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1397327712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.1397327712
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1288756441
Short name T406
Test name
Test status
Simulation time 36043896 ps
CPU time 0.85 seconds
Started Jul 17 05:17:15 PM PDT 24
Finished Jul 17 05:17:18 PM PDT 24
Peak memory 208384 kb
Host smart-c7ea9e85-927f-4146-b5b2-1927b0e96d5e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288756441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1288756441
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2148016395
Short name T668
Test name
Test status
Simulation time 13143143 ps
CPU time 0.85 seconds
Started Jul 17 05:17:14 PM PDT 24
Finished Jul 17 05:17:16 PM PDT 24
Peak memory 208192 kb
Host smart-629af5d7-bdea-430c-aad5-f02163dfae40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148016395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2148016395
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.773126007
Short name T267
Test name
Test status
Simulation time 419288207 ps
CPU time 10.82 seconds
Started Jul 17 05:17:21 PM PDT 24
Finished Jul 17 05:17:33 PM PDT 24
Peak memory 225492 kb
Host smart-60acbde9-9184-4722-a209-73d79ad36301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773126007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.773126007
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.470401787
Short name T364
Test name
Test status
Simulation time 236910290 ps
CPU time 2.65 seconds
Started Jul 17 05:17:21 PM PDT 24
Finished Jul 17 05:17:25 PM PDT 24
Peak memory 217184 kb
Host smart-fa94bfdd-cea7-492d-b75c-5e7a5e0a1906
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470401787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.470401787
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.4098798540
Short name T746
Test name
Test status
Simulation time 42348455 ps
CPU time 2.19 seconds
Started Jul 17 05:17:21 PM PDT 24
Finished Jul 17 05:17:24 PM PDT 24
Peak memory 221652 kb
Host smart-073c1846-ce60-426e-9c35-a3e41c8f2713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098798540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.4098798540
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2271570399
Short name T867
Test name
Test status
Simulation time 299159695 ps
CPU time 7.96 seconds
Started Jul 17 05:17:17 PM PDT 24
Finished Jul 17 05:17:28 PM PDT 24
Peak memory 225496 kb
Host smart-3531e059-b30a-42e5-a6c6-257f6024bba4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271570399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2271570399
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3751543419
Short name T563
Test name
Test status
Simulation time 703377231 ps
CPU time 10.79 seconds
Started Jul 17 05:17:21 PM PDT 24
Finished Jul 17 05:17:32 PM PDT 24
Peak memory 217708 kb
Host smart-d9621c55-879d-4046-9720-1d383dd1ea81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751543419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3751543419
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3916045738
Short name T674
Test name
Test status
Simulation time 1288299447 ps
CPU time 11.77 seconds
Started Jul 17 05:17:16 PM PDT 24
Finished Jul 17 05:17:30 PM PDT 24
Peak memory 224264 kb
Host smart-3d0be2b4-c430-4587-998b-156fc22ac998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916045738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3916045738
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3679407795
Short name T298
Test name
Test status
Simulation time 14089273 ps
CPU time 1.31 seconds
Started Jul 17 05:17:51 PM PDT 24
Finished Jul 17 05:17:56 PM PDT 24
Peak memory 213100 kb
Host smart-af6eaade-615a-4079-bfff-63766d6ce512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679407795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3679407795
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.486872531
Short name T755
Test name
Test status
Simulation time 754416181 ps
CPU time 21.89 seconds
Started Jul 17 05:17:17 PM PDT 24
Finished Jul 17 05:17:41 PM PDT 24
Peak memory 250568 kb
Host smart-152ade81-df11-4e38-8c35-94a80fa3e5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486872531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.486872531
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.9901894
Short name T458
Test name
Test status
Simulation time 204871204 ps
CPU time 7.73 seconds
Started Jul 17 05:17:20 PM PDT 24
Finished Jul 17 05:17:29 PM PDT 24
Peak memory 250636 kb
Host smart-99c14744-ac9d-42a9-a86d-c210011de9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9901894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.9901894
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2767490972
Short name T769
Test name
Test status
Simulation time 8222821886 ps
CPU time 20.7 seconds
Started Jul 17 05:17:16 PM PDT 24
Finished Jul 17 05:17:39 PM PDT 24
Peak memory 245596 kb
Host smart-ee286147-b071-4504-87f0-71731295fedf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767490972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2767490972
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3311055166
Short name T209
Test name
Test status
Simulation time 25864753 ps
CPU time 1.07 seconds
Started Jul 17 05:17:19 PM PDT 24
Finished Jul 17 05:17:21 PM PDT 24
Peak memory 211396 kb
Host smart-f55bb97d-cd98-497b-9f6b-2d757fff3760
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311055166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3311055166
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.822324966
Short name T248
Test name
Test status
Simulation time 18902184 ps
CPU time 1 seconds
Started Jul 17 05:17:28 PM PDT 24
Finished Jul 17 05:17:30 PM PDT 24
Peak memory 208388 kb
Host smart-03cd733c-cb2d-4040-a995-cd7a7b2d8678
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822324966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.822324966
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.519879541
Short name T407
Test name
Test status
Simulation time 450387265 ps
CPU time 9.18 seconds
Started Jul 17 05:17:28 PM PDT 24
Finished Jul 17 05:17:39 PM PDT 24
Peak memory 217684 kb
Host smart-6e411b65-b80e-4955-aca8-14e4045e55f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519879541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.519879541
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.2511916482
Short name T838
Test name
Test status
Simulation time 1067397317 ps
CPU time 8.04 seconds
Started Jul 17 05:17:29 PM PDT 24
Finished Jul 17 05:17:38 PM PDT 24
Peak memory 217180 kb
Host smart-dc0dbf00-29aa-4f36-b130-059d6664c7a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511916482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.2511916482
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3918625496
Short name T469
Test name
Test status
Simulation time 136624423 ps
CPU time 1.97 seconds
Started Jul 17 05:17:32 PM PDT 24
Finished Jul 17 05:17:35 PM PDT 24
Peak memory 221720 kb
Host smart-abe45b24-7e20-43b2-a285-d23c7aa25fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918625496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3918625496
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.2110223695
Short name T521
Test name
Test status
Simulation time 233961644 ps
CPU time 9.12 seconds
Started Jul 17 05:17:49 PM PDT 24
Finished Jul 17 05:18:00 PM PDT 24
Peak memory 225552 kb
Host smart-2cd95f46-8467-4179-9e28-201ecfb8006d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110223695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2110223695
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2452904746
Short name T737
Test name
Test status
Simulation time 387085660 ps
CPU time 11.39 seconds
Started Jul 17 05:17:34 PM PDT 24
Finished Jul 17 05:17:46 PM PDT 24
Peak memory 225500 kb
Host smart-a0246236-8ea4-4b23-a0ff-ba69927296df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452904746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2452904746
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3717910656
Short name T749
Test name
Test status
Simulation time 1879165477 ps
CPU time 11.51 seconds
Started Jul 17 05:17:26 PM PDT 24
Finished Jul 17 05:17:39 PM PDT 24
Peak memory 225516 kb
Host smart-a7989dcf-3962-4b59-b3ff-848edec4a33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717910656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3717910656
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1759476913
Short name T82
Test name
Test status
Simulation time 100878709 ps
CPU time 1.31 seconds
Started Jul 17 05:17:27 PM PDT 24
Finished Jul 17 05:17:29 PM PDT 24
Peak memory 222168 kb
Host smart-56d8223c-7aa4-40e9-995b-986de6cde51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759476913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1759476913
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3558825333
Short name T89
Test name
Test status
Simulation time 206035191 ps
CPU time 21.12 seconds
Started Jul 17 05:17:28 PM PDT 24
Finished Jul 17 05:17:50 PM PDT 24
Peak memory 250504 kb
Host smart-7bf19690-64ec-401e-a79a-19809cbd8028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558825333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3558825333
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.805352405
Short name T11
Test name
Test status
Simulation time 197852776 ps
CPU time 2.86 seconds
Started Jul 17 05:17:28 PM PDT 24
Finished Jul 17 05:17:32 PM PDT 24
Peak memory 221844 kb
Host smart-39a32b99-397b-4672-b8e4-7925f717beef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805352405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.805352405
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.150625198
Short name T728
Test name
Test status
Simulation time 25249788505 ps
CPU time 219.73 seconds
Started Jul 17 05:17:27 PM PDT 24
Finished Jul 17 05:21:07 PM PDT 24
Peak memory 250540 kb
Host smart-1e1a0850-764c-4691-bb2e-e4ee52648339
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150625198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.150625198
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.4169299760
Short name T555
Test name
Test status
Simulation time 15031257 ps
CPU time 0.97 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:17:55 PM PDT 24
Peak memory 208428 kb
Host smart-b2a63832-5e09-4062-a541-337783f2494c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169299760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.4169299760
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.670257670
Short name T282
Test name
Test status
Simulation time 14482024 ps
CPU time 1.05 seconds
Started Jul 17 05:18:00 PM PDT 24
Finished Jul 17 05:18:06 PM PDT 24
Peak memory 208436 kb
Host smart-7033b9e0-185c-4ccb-baef-ee9061d0bfc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670257670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.670257670
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2447033519
Short name T21
Test name
Test status
Simulation time 806820879 ps
CPU time 5.99 seconds
Started Jul 17 05:17:56 PM PDT 24
Finished Jul 17 05:18:09 PM PDT 24
Peak memory 217308 kb
Host smart-e8271a6a-72b6-41a9-8c94-0207013792cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447033519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2447033519
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1262400530
Short name T665
Test name
Test status
Simulation time 29113949 ps
CPU time 2.25 seconds
Started Jul 17 05:17:57 PM PDT 24
Finished Jul 17 05:18:06 PM PDT 24
Peak memory 217756 kb
Host smart-e6f6acfc-3094-4c34-9527-9e1a956f92a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262400530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1262400530
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.1153202567
Short name T592
Test name
Test status
Simulation time 1283091756 ps
CPU time 15.3 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:18:09 PM PDT 24
Peak memory 225520 kb
Host smart-bc742a64-8ad8-4e49-ada1-49fc0555bbb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153202567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1153202567
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2004777108
Short name T815
Test name
Test status
Simulation time 919810846 ps
CPU time 9.28 seconds
Started Jul 17 05:17:55 PM PDT 24
Finished Jul 17 05:18:10 PM PDT 24
Peak memory 225440 kb
Host smart-b3a8cb12-eb94-4d69-9de6-c08e7ea4e142
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004777108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2004777108
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3381339902
Short name T470
Test name
Test status
Simulation time 6295545949 ps
CPU time 12.48 seconds
Started Jul 17 05:17:52 PM PDT 24
Finished Jul 17 05:18:10 PM PDT 24
Peak memory 217776 kb
Host smart-93fa02fe-9b22-472e-a26e-1531c450c796
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381339902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3381339902
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3899734253
Short name T365
Test name
Test status
Simulation time 268482814 ps
CPU time 7.88 seconds
Started Jul 17 05:17:52 PM PDT 24
Finished Jul 17 05:18:05 PM PDT 24
Peak memory 225540 kb
Host smart-1fdb4481-7d06-4d78-9471-92a2c9100185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899734253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3899734253
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1897231252
Short name T696
Test name
Test status
Simulation time 29995929 ps
CPU time 1.17 seconds
Started Jul 17 05:17:29 PM PDT 24
Finished Jul 17 05:17:31 PM PDT 24
Peak memory 211664 kb
Host smart-90cb9a2f-0027-416a-b457-28ed7056b45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897231252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1897231252
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3403053538
Short name T871
Test name
Test status
Simulation time 384608346 ps
CPU time 20.58 seconds
Started Jul 17 05:17:57 PM PDT 24
Finished Jul 17 05:18:24 PM PDT 24
Peak memory 250532 kb
Host smart-70436e6b-3076-470a-b400-5020468eca35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403053538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3403053538
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.569723648
Short name T155
Test name
Test status
Simulation time 67679191 ps
CPU time 8.1 seconds
Started Jul 17 05:17:48 PM PDT 24
Finished Jul 17 05:17:58 PM PDT 24
Peak memory 250524 kb
Host smart-db49669f-2b97-40f3-b739-6bdca669b3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569723648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.569723648
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1240383216
Short name T227
Test name
Test status
Simulation time 11853790443 ps
CPU time 358.84 seconds
Started Jul 17 05:18:01 PM PDT 24
Finished Jul 17 05:24:04 PM PDT 24
Peak memory 315896 kb
Host smart-f8391302-747a-49c1-af1a-ff7bcbff776e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240383216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1240383216
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.897213371
Short name T338
Test name
Test status
Simulation time 49693856 ps
CPU time 0.91 seconds
Started Jul 17 05:17:35 PM PDT 24
Finished Jul 17 05:17:37 PM PDT 24
Peak memory 208440 kb
Host smart-6aa4d253-0935-4f63-a24e-c12b3b15728b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897213371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.897213371
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3169042452
Short name T412
Test name
Test status
Simulation time 96314748 ps
CPU time 1.14 seconds
Started Jul 17 05:17:51 PM PDT 24
Finished Jul 17 05:17:57 PM PDT 24
Peak memory 208368 kb
Host smart-688ed53c-621f-41be-8c4c-96db1bb8a830
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169042452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3169042452
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1926178248
Short name T240
Test name
Test status
Simulation time 584056535 ps
CPU time 13.46 seconds
Started Jul 17 05:17:51 PM PDT 24
Finished Jul 17 05:18:09 PM PDT 24
Peak memory 217772 kb
Host smart-f6e93852-13e1-4fb3-b483-a60d6c7f65b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926178248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1926178248
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2750390177
Short name T8
Test name
Test status
Simulation time 1095076276 ps
CPU time 3.48 seconds
Started Jul 17 05:17:59 PM PDT 24
Finished Jul 17 05:18:08 PM PDT 24
Peak memory 217100 kb
Host smart-048d07f8-8769-4c1d-b3c4-f62fa1cf093f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750390177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2750390177
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3095649158
Short name T264
Test name
Test status
Simulation time 957918612 ps
CPU time 2.94 seconds
Started Jul 17 05:18:01 PM PDT 24
Finished Jul 17 05:18:08 PM PDT 24
Peak memory 221740 kb
Host smart-8b5df54f-9d2f-4e43-90fd-851ce221f9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095649158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3095649158
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2850525312
Short name T376
Test name
Test status
Simulation time 798432633 ps
CPU time 19.97 seconds
Started Jul 17 05:17:58 PM PDT 24
Finished Jul 17 05:18:24 PM PDT 24
Peak memory 225540 kb
Host smart-02badef9-4dbf-4a31-9321-c5314897cd7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850525312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2850525312
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.545926210
Short name T12
Test name
Test status
Simulation time 1753619719 ps
CPU time 12.18 seconds
Started Jul 17 05:17:54 PM PDT 24
Finished Jul 17 05:18:13 PM PDT 24
Peak memory 225440 kb
Host smart-fba4d018-598f-4bd2-a7e7-21404e3ab6d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545926210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.545926210
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.345353286
Short name T423
Test name
Test status
Simulation time 3267583216 ps
CPU time 7.79 seconds
Started Jul 17 05:18:00 PM PDT 24
Finished Jul 17 05:18:13 PM PDT 24
Peak memory 217468 kb
Host smart-c0dce726-5568-4f9c-b85f-767e0e996ba8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345353286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.345353286
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2093409145
Short name T386
Test name
Test status
Simulation time 1548637354 ps
CPU time 13.37 seconds
Started Jul 17 05:17:54 PM PDT 24
Finished Jul 17 05:18:13 PM PDT 24
Peak memory 225512 kb
Host smart-8bf95ed3-a2ee-4cc8-9560-be6ce14524ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093409145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2093409145
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2990785048
Short name T872
Test name
Test status
Simulation time 43211889 ps
CPU time 2.15 seconds
Started Jul 17 05:17:55 PM PDT 24
Finished Jul 17 05:18:03 PM PDT 24
Peak memory 217184 kb
Host smart-3176cba0-0bf0-4a57-9189-5fc5bfa7094d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990785048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2990785048
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1259377673
Short name T612
Test name
Test status
Simulation time 1846144713 ps
CPU time 25.05 seconds
Started Jul 17 05:17:53 PM PDT 24
Finished Jul 17 05:18:25 PM PDT 24
Peak memory 250508 kb
Host smart-238677b9-2c2f-4bad-a10c-d7270793d276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259377673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1259377673
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2232280890
Short name T411
Test name
Test status
Simulation time 66646719 ps
CPU time 7.47 seconds
Started Jul 17 05:17:53 PM PDT 24
Finished Jul 17 05:18:07 PM PDT 24
Peak memory 249948 kb
Host smart-360a3b74-7683-4c88-a3ac-880c8ef349c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232280890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2232280890
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3240813306
Short name T362
Test name
Test status
Simulation time 3906966784 ps
CPU time 150.86 seconds
Started Jul 17 05:18:00 PM PDT 24
Finished Jul 17 05:20:36 PM PDT 24
Peak memory 246256 kb
Host smart-c917eda8-9590-4e39-8e2e-42a6fcdb5b04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240813306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3240813306
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.2340270784
Short name T64
Test name
Test status
Simulation time 73674386199 ps
CPU time 566.62 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:27:21 PM PDT 24
Peak memory 282628 kb
Host smart-02e099c8-aab3-491f-ba46-dfb3baafd554
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2340270784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.2340270784
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.94288738
Short name T77
Test name
Test status
Simulation time 89975236 ps
CPU time 0.91 seconds
Started Jul 17 05:18:01 PM PDT 24
Finished Jul 17 05:18:06 PM PDT 24
Peak memory 211412 kb
Host smart-b0b69586-0c46-4a87-9a1a-2a3a7b931a09
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94288738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctr
l_volatile_unlock_smoke.94288738
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2351749028
Short name T537
Test name
Test status
Simulation time 116615356 ps
CPU time 0.87 seconds
Started Jul 17 05:17:59 PM PDT 24
Finished Jul 17 05:18:05 PM PDT 24
Peak memory 208332 kb
Host smart-f4aaa8ae-bb19-44dc-a90a-ecd8c29c45b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351749028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2351749028
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3737965263
Short name T295
Test name
Test status
Simulation time 1760337836 ps
CPU time 18 seconds
Started Jul 17 05:17:59 PM PDT 24
Finished Jul 17 05:18:23 PM PDT 24
Peak memory 217676 kb
Host smart-682a57e1-71fe-4509-bfdd-18bc26ae9ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737965263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3737965263
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2096802047
Short name T477
Test name
Test status
Simulation time 69715897 ps
CPU time 3.61 seconds
Started Jul 17 05:18:00 PM PDT 24
Finished Jul 17 05:18:08 PM PDT 24
Peak memory 217544 kb
Host smart-02f6b6e4-6826-4fd2-8262-e8997211d2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096802047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2096802047
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3400642309
Short name T582
Test name
Test status
Simulation time 725404203 ps
CPU time 11.62 seconds
Started Jul 17 05:17:54 PM PDT 24
Finished Jul 17 05:18:13 PM PDT 24
Peak memory 225464 kb
Host smart-b48b6674-d9e8-4116-8f79-487a7637a2b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400642309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3400642309
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3201418543
Short name T66
Test name
Test status
Simulation time 1505914748 ps
CPU time 9.84 seconds
Started Jul 17 05:17:54 PM PDT 24
Finished Jul 17 05:18:10 PM PDT 24
Peak memory 217704 kb
Host smart-73c47203-f723-477c-acc2-57dd84169cd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201418543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
3201418543
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.951565576
Short name T593
Test name
Test status
Simulation time 304617300 ps
CPU time 7.36 seconds
Started Jul 17 05:17:53 PM PDT 24
Finished Jul 17 05:18:06 PM PDT 24
Peak memory 224164 kb
Host smart-d9f820b0-f989-45f0-a66f-13f245f8a51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951565576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.951565576
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2778254077
Short name T650
Test name
Test status
Simulation time 223610641 ps
CPU time 2.13 seconds
Started Jul 17 05:17:49 PM PDT 24
Finished Jul 17 05:17:54 PM PDT 24
Peak memory 214168 kb
Host smart-e7742fc9-6caf-4c16-acf2-defac2042541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778254077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2778254077
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2787475900
Short name T589
Test name
Test status
Simulation time 302115192 ps
CPU time 24.69 seconds
Started Jul 17 05:17:57 PM PDT 24
Finished Jul 17 05:18:28 PM PDT 24
Peak memory 250392 kb
Host smart-9dab04c1-563e-4f37-8982-4198644e808e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787475900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2787475900
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2158701830
Short name T318
Test name
Test status
Simulation time 138865815 ps
CPU time 6.88 seconds
Started Jul 17 05:18:00 PM PDT 24
Finished Jul 17 05:18:12 PM PDT 24
Peak memory 248192 kb
Host smart-cabf7af6-e8cf-4860-ab13-d7739dd1ff4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158701830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2158701830
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.98122270
Short name T797
Test name
Test status
Simulation time 3036310370 ps
CPU time 95.07 seconds
Started Jul 17 05:17:50 PM PDT 24
Finished Jul 17 05:19:29 PM PDT 24
Peak memory 250764 kb
Host smart-738a19d9-256d-4d3d-a096-5af12ef8e8fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98122270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.lc_ctrl_stress_all.98122270
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.616880159
Short name T763
Test name
Test status
Simulation time 7269595392 ps
CPU time 232.64 seconds
Started Jul 17 05:18:00 PM PDT 24
Finished Jul 17 05:21:58 PM PDT 24
Peak memory 280144 kb
Host smart-017defb5-445c-4ca3-aeb4-298bbd2cb797
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=616880159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.616880159
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2867814348
Short name T623
Test name
Test status
Simulation time 13827795 ps
CPU time 0.8 seconds
Started Jul 17 05:18:00 PM PDT 24
Finished Jul 17 05:18:06 PM PDT 24
Peak memory 208512 kb
Host smart-df865743-eef6-4f73-8773-d1f854a0dd3f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867814348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.2867814348
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3766012512
Short name T232
Test name
Test status
Simulation time 79245120 ps
CPU time 0.85 seconds
Started Jul 17 05:18:09 PM PDT 24
Finished Jul 17 05:18:13 PM PDT 24
Peak memory 208224 kb
Host smart-3abef7a5-ac95-4290-b5de-29ef7a639cc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766012512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3766012512
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.664477217
Short name T39
Test name
Test status
Simulation time 819617371 ps
CPU time 17.65 seconds
Started Jul 17 05:18:07 PM PDT 24
Finished Jul 17 05:18:27 PM PDT 24
Peak memory 225564 kb
Host smart-be38eee0-2edd-4ca4-88da-b88c64d385f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664477217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.664477217
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.24663111
Short name T840
Test name
Test status
Simulation time 77896831 ps
CPU time 2.7 seconds
Started Jul 17 05:18:12 PM PDT 24
Finished Jul 17 05:18:17 PM PDT 24
Peak memory 216640 kb
Host smart-589877b4-f511-45aa-8e6c-4271c63c825e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24663111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.24663111
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3157791767
Short name T775
Test name
Test status
Simulation time 120018124 ps
CPU time 3.53 seconds
Started Jul 17 05:18:08 PM PDT 24
Finished Jul 17 05:18:14 PM PDT 24
Peak memory 217756 kb
Host smart-d7f50f46-7f51-48b8-a6e1-174bc93a3035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157791767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3157791767
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3913304851
Short name T604
Test name
Test status
Simulation time 268786222 ps
CPU time 10.64 seconds
Started Jul 17 05:18:08 PM PDT 24
Finished Jul 17 05:18:20 PM PDT 24
Peak memory 217784 kb
Host smart-8966bc04-e7a0-4955-90fc-8659fb140cef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913304851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3913304851
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2110482533
Short name T311
Test name
Test status
Simulation time 3521921672 ps
CPU time 10.21 seconds
Started Jul 17 05:18:11 PM PDT 24
Finished Jul 17 05:18:24 PM PDT 24
Peak memory 225524 kb
Host smart-56fb2837-b71c-4827-a7bf-ee14129f92c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110482533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2110482533
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.4256438393
Short name T368
Test name
Test status
Simulation time 942027423 ps
CPU time 5.88 seconds
Started Jul 17 05:18:08 PM PDT 24
Finished Jul 17 05:18:16 PM PDT 24
Peak memory 225428 kb
Host smart-7b753ef0-0f56-4327-9fad-4731ef5d4f17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256438393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
4256438393
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3601305189
Short name T374
Test name
Test status
Simulation time 547064684 ps
CPU time 10.48 seconds
Started Jul 17 05:18:12 PM PDT 24
Finished Jul 17 05:18:25 PM PDT 24
Peak memory 225432 kb
Host smart-6b5a8698-025b-46ce-b137-477b13a76cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601305189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3601305189
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1839016258
Short name T14
Test name
Test status
Simulation time 42376252 ps
CPU time 2.54 seconds
Started Jul 17 05:17:54 PM PDT 24
Finished Jul 17 05:18:03 PM PDT 24
Peak memory 217176 kb
Host smart-241e67be-9d2a-42bc-bd8a-3247645a5bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839016258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1839016258
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1987801411
Short name T688
Test name
Test status
Simulation time 1030904622 ps
CPU time 22.7 seconds
Started Jul 17 05:18:06 PM PDT 24
Finished Jul 17 05:18:30 PM PDT 24
Peak memory 250632 kb
Host smart-09a6fdc0-4517-403a-ae01-4745bd175c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987801411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1987801411
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2776753973
Short name T693
Test name
Test status
Simulation time 147869636 ps
CPU time 11.02 seconds
Started Jul 17 05:18:10 PM PDT 24
Finished Jul 17 05:18:24 PM PDT 24
Peak memory 250488 kb
Host smart-c7d73ad3-580c-4d9c-9c7d-96533dfa2107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776753973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2776753973
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3631621036
Short name T622
Test name
Test status
Simulation time 17455472532 ps
CPU time 121.39 seconds
Started Jul 17 05:18:15 PM PDT 24
Finished Jul 17 05:20:18 PM PDT 24
Peak memory 283324 kb
Host smart-ddee31c9-1f6c-490f-8395-1686d71b661e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631621036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3631621036
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3848905505
Short name T627
Test name
Test status
Simulation time 39248130 ps
CPU time 0.92 seconds
Started Jul 17 05:17:57 PM PDT 24
Finished Jul 17 05:18:04 PM PDT 24
Peak memory 211328 kb
Host smart-b1a15e9d-bdc9-4137-bbb1-f51453ff0035
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848905505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3848905505
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3641555557
Short name T481
Test name
Test status
Simulation time 37639433 ps
CPU time 0.91 seconds
Started Jul 17 05:18:09 PM PDT 24
Finished Jul 17 05:18:13 PM PDT 24
Peak memory 208376 kb
Host smart-87bc4d28-5aa4-447e-8cba-47a922882356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641555557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3641555557
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3170762973
Short name T635
Test name
Test status
Simulation time 497287378 ps
CPU time 8.38 seconds
Started Jul 17 05:18:07 PM PDT 24
Finished Jul 17 05:18:17 PM PDT 24
Peak memory 225508 kb
Host smart-be9a1d99-3af1-415a-80b2-02fb3cc73c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170762973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3170762973
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3723174196
Short name T440
Test name
Test status
Simulation time 385554025 ps
CPU time 2.84 seconds
Started Jul 17 05:18:12 PM PDT 24
Finished Jul 17 05:18:18 PM PDT 24
Peak memory 216656 kb
Host smart-1c79da4c-3d23-474f-8b26-3a7374ab96cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723174196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3723174196
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.3003064824
Short name T482
Test name
Test status
Simulation time 92924937 ps
CPU time 4.41 seconds
Started Jul 17 05:18:07 PM PDT 24
Finished Jul 17 05:18:14 PM PDT 24
Peak memory 222196 kb
Host smart-1bd4d453-f431-47c7-9ce0-68bdef2d15e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003064824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3003064824
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.1015129405
Short name T695
Test name
Test status
Simulation time 585597271 ps
CPU time 18.4 seconds
Started Jul 17 05:18:13 PM PDT 24
Finished Jul 17 05:18:34 PM PDT 24
Peak memory 219496 kb
Host smart-814f57fe-0f59-4ef4-aaf4-7e6a966bde30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015129405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1015129405
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2805556785
Short name T244
Test name
Test status
Simulation time 422143740 ps
CPU time 11.37 seconds
Started Jul 17 05:18:09 PM PDT 24
Finished Jul 17 05:18:23 PM PDT 24
Peak memory 225500 kb
Host smart-6eb73764-e973-4b67-9eb8-3aef89b05d20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805556785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2805556785
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3134479630
Short name T496
Test name
Test status
Simulation time 1455598679 ps
CPU time 13.65 seconds
Started Jul 17 05:18:09 PM PDT 24
Finished Jul 17 05:18:26 PM PDT 24
Peak memory 225504 kb
Host smart-e342ce7f-06ad-43fe-9a4e-dd736a9a7709
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134479630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3134479630
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1014346071
Short name T171
Test name
Test status
Simulation time 1254186856 ps
CPU time 8.99 seconds
Started Jul 17 05:18:07 PM PDT 24
Finished Jul 17 05:18:18 PM PDT 24
Peak memory 225564 kb
Host smart-aa8cae64-5e48-473f-b7a2-2ecebee19a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014346071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1014346071
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1175034670
Short name T663
Test name
Test status
Simulation time 151701004 ps
CPU time 2.95 seconds
Started Jul 17 05:18:13 PM PDT 24
Finished Jul 17 05:18:19 PM PDT 24
Peak memory 214388 kb
Host smart-d28100f2-7a7a-457e-8971-85d178c99dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175034670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1175034670
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.768598065
Short name T751
Test name
Test status
Simulation time 1665607328 ps
CPU time 24.3 seconds
Started Jul 17 05:18:09 PM PDT 24
Finished Jul 17 05:18:36 PM PDT 24
Peak memory 246920 kb
Host smart-a6e5f7aa-f5e8-4a37-90d8-cb53afd8dd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768598065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.768598065
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3859038715
Short name T370
Test name
Test status
Simulation time 47852068 ps
CPU time 8.74 seconds
Started Jul 17 05:18:08 PM PDT 24
Finished Jul 17 05:18:19 PM PDT 24
Peak memory 250512 kb
Host smart-808f51ea-7ed1-42ba-8fa4-756733bc27ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859038715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3859038715
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.474507307
Short name T177
Test name
Test status
Simulation time 22008999171 ps
CPU time 85.33 seconds
Started Jul 17 05:18:11 PM PDT 24
Finished Jul 17 05:19:39 PM PDT 24
Peak memory 278032 kb
Host smart-c63ec03f-6a46-427a-82f6-902363c4a582
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474507307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.474507307
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2099918964
Short name T408
Test name
Test status
Simulation time 38823798 ps
CPU time 0.85 seconds
Started Jul 17 05:18:09 PM PDT 24
Finished Jul 17 05:18:12 PM PDT 24
Peak memory 212392 kb
Host smart-df652d80-9669-43fb-a86a-5774b6daef6f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099918964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2099918964
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.312642859
Short name T756
Test name
Test status
Simulation time 244779582 ps
CPU time 1 seconds
Started Jul 17 05:18:13 PM PDT 24
Finished Jul 17 05:18:16 PM PDT 24
Peak memory 208352 kb
Host smart-9ab8eada-e3bc-447a-aa9a-74c30185da28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312642859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.312642859
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2385559833
Short name T462
Test name
Test status
Simulation time 328150282 ps
CPU time 10.39 seconds
Started Jul 17 05:18:17 PM PDT 24
Finished Jul 17 05:18:29 PM PDT 24
Peak memory 225568 kb
Host smart-f1b2dd26-f17a-4c5f-9619-aa19ec6a1aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385559833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2385559833
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.57479360
Short name T687
Test name
Test status
Simulation time 1689893210 ps
CPU time 4.69 seconds
Started Jul 17 05:18:12 PM PDT 24
Finished Jul 17 05:18:19 PM PDT 24
Peak memory 217256 kb
Host smart-6e55bcc8-afb1-4dee-b5a5-4ffd8da6eedb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57479360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.57479360
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3594670725
Short name T794
Test name
Test status
Simulation time 150016920 ps
CPU time 2.77 seconds
Started Jul 17 05:18:15 PM PDT 24
Finished Jul 17 05:18:20 PM PDT 24
Peak memory 221960 kb
Host smart-e87d8925-c244-4066-93f6-629abdc142a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594670725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3594670725
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3537683844
Short name T844
Test name
Test status
Simulation time 671139301 ps
CPU time 16.71 seconds
Started Jul 17 05:18:15 PM PDT 24
Finished Jul 17 05:18:34 PM PDT 24
Peak memory 218412 kb
Host smart-e527e404-da61-4173-9b53-f8644359c401
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537683844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3537683844
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3302877873
Short name T824
Test name
Test status
Simulation time 721804763 ps
CPU time 14.06 seconds
Started Jul 17 05:18:09 PM PDT 24
Finished Jul 17 05:18:26 PM PDT 24
Peak memory 225496 kb
Host smart-3c64947d-a35b-47db-8d91-55d1e6618f97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302877873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3302877873
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2965523164
Short name T224
Test name
Test status
Simulation time 1638446259 ps
CPU time 11.18 seconds
Started Jul 17 05:18:11 PM PDT 24
Finished Jul 17 05:18:26 PM PDT 24
Peak memory 217636 kb
Host smart-b6e1a5c7-e951-478d-844d-bb5e252c5590
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965523164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2965523164
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1354817792
Short name T454
Test name
Test status
Simulation time 367479386 ps
CPU time 9.39 seconds
Started Jul 17 05:18:13 PM PDT 24
Finished Jul 17 05:18:25 PM PDT 24
Peak memory 217824 kb
Host smart-d5cac154-f7d5-4c6f-a4bd-e1f869be6acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354817792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1354817792
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.105256172
Short name T239
Test name
Test status
Simulation time 27697327 ps
CPU time 1.87 seconds
Started Jul 17 05:18:09 PM PDT 24
Finished Jul 17 05:18:14 PM PDT 24
Peak memory 217268 kb
Host smart-9f44ccae-40a8-4f38-b302-e60627d2826f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105256172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.105256172
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3650988876
Short name T662
Test name
Test status
Simulation time 191610472 ps
CPU time 20.1 seconds
Started Jul 17 05:18:17 PM PDT 24
Finished Jul 17 05:18:38 PM PDT 24
Peak memory 250488 kb
Host smart-250f84b9-a75c-4104-966e-642ca57a6cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650988876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3650988876
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3373091546
Short name T571
Test name
Test status
Simulation time 139540573 ps
CPU time 2.95 seconds
Started Jul 17 05:18:15 PM PDT 24
Finished Jul 17 05:18:20 PM PDT 24
Peak memory 221772 kb
Host smart-3eff54a3-b08e-4d1a-b73f-facd44bbbabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373091546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3373091546
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.894465886
Short name T162
Test name
Test status
Simulation time 42205268886 ps
CPU time 141.44 seconds
Started Jul 17 05:18:16 PM PDT 24
Finished Jul 17 05:20:39 PM PDT 24
Peak memory 221136 kb
Host smart-84f612ae-7945-47dc-817e-f75a4335b8c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894465886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.894465886
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.3795757982
Short name T100
Test name
Test status
Simulation time 134152799153 ps
CPU time 677.96 seconds
Started Jul 17 05:18:08 PM PDT 24
Finished Jul 17 05:29:28 PM PDT 24
Peak memory 512832 kb
Host smart-1c7050cb-3c6f-45a5-a50c-5c6e819c7572
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3795757982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.3795757982
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.490536399
Short name T297
Test name
Test status
Simulation time 22423971 ps
CPU time 0.78 seconds
Started Jul 17 05:18:13 PM PDT 24
Finished Jul 17 05:18:16 PM PDT 24
Peak memory 208348 kb
Host smart-58d03589-6fb1-4308-ac27-fdcdbab4c3a9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490536399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct
rl_volatile_unlock_smoke.490536399
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1527465975
Short name T403
Test name
Test status
Simulation time 34294347 ps
CPU time 0.93 seconds
Started Jul 17 05:18:14 PM PDT 24
Finished Jul 17 05:18:17 PM PDT 24
Peak memory 208376 kb
Host smart-5d6b18aa-bd9e-44ee-bc4a-7a104784b655
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527465975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1527465975
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1999273856
Short name T560
Test name
Test status
Simulation time 807190506 ps
CPU time 10.71 seconds
Started Jul 17 05:18:16 PM PDT 24
Finished Jul 17 05:18:28 PM PDT 24
Peak memory 217716 kb
Host smart-3aede90e-f13e-437c-802e-8bc0d51e507e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999273856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1999273856
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.3764883605
Short name T761
Test name
Test status
Simulation time 3675400768 ps
CPU time 6.76 seconds
Started Jul 17 05:18:13 PM PDT 24
Finished Jul 17 05:18:22 PM PDT 24
Peak memory 217200 kb
Host smart-9c8cc2ea-cc19-414b-b191-5b0200381e27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764883605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3764883605
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2877380032
Short name T776
Test name
Test status
Simulation time 544422491 ps
CPU time 2.55 seconds
Started Jul 17 05:18:14 PM PDT 24
Finished Jul 17 05:18:19 PM PDT 24
Peak memory 217712 kb
Host smart-b42d3866-3731-4ea6-825a-9b4b08081f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877380032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2877380032
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1914396815
Short name T323
Test name
Test status
Simulation time 1040894740 ps
CPU time 8.49 seconds
Started Jul 17 05:18:13 PM PDT 24
Finished Jul 17 05:18:24 PM PDT 24
Peak memory 225496 kb
Host smart-e13c2a27-b251-409d-9a4d-9e91995afb95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914396815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1914396815
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.631369376
Short name T377
Test name
Test status
Simulation time 440600864 ps
CPU time 10.27 seconds
Started Jul 17 05:18:15 PM PDT 24
Finished Jul 17 05:18:27 PM PDT 24
Peak memory 217700 kb
Host smart-a8d7cccb-ac61-430a-8111-c21c4a475b25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631369376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.631369376
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3111941941
Short name T453
Test name
Test status
Simulation time 585307010 ps
CPU time 12.05 seconds
Started Jul 17 05:18:16 PM PDT 24
Finished Jul 17 05:18:30 PM PDT 24
Peak memory 225560 kb
Host smart-188ae4a5-722d-490f-874c-69ec845b890f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111941941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3111941941
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.557791205
Short name T768
Test name
Test status
Simulation time 304328482 ps
CPU time 2.68 seconds
Started Jul 17 05:18:16 PM PDT 24
Finished Jul 17 05:18:21 PM PDT 24
Peak memory 217108 kb
Host smart-31c0ef74-bb27-494c-9ddd-c7a5928c6a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557791205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.557791205
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1404613520
Short name T210
Test name
Test status
Simulation time 257216190 ps
CPU time 25.04 seconds
Started Jul 17 05:18:13 PM PDT 24
Finished Jul 17 05:18:41 PM PDT 24
Peak memory 246764 kb
Host smart-8178e0d3-cafa-40fe-af65-404e3d92049b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404613520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1404613520
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.2710010741
Short name T353
Test name
Test status
Simulation time 53329368 ps
CPU time 8.67 seconds
Started Jul 17 05:18:08 PM PDT 24
Finished Jul 17 05:18:19 PM PDT 24
Peak memory 250572 kb
Host smart-cde9c8a7-0a9f-44a6-8cf7-d5709b22ebd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710010741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2710010741
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3780218739
Short name T80
Test name
Test status
Simulation time 2174205785 ps
CPU time 82.72 seconds
Started Jul 17 05:18:14 PM PDT 24
Finished Jul 17 05:19:39 PM PDT 24
Peak memory 266920 kb
Host smart-a284f0db-3c13-490e-b337-4894c1ca678e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780218739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3780218739
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.2279251409
Short name T152
Test name
Test status
Simulation time 88478975744 ps
CPU time 529.25 seconds
Started Jul 17 05:18:10 PM PDT 24
Finished Jul 17 05:27:03 PM PDT 24
Peak memory 299868 kb
Host smart-d98062a4-8347-4923-98bf-d6588ad07786
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2279251409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.2279251409
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1073238198
Short name T461
Test name
Test status
Simulation time 16912567 ps
CPU time 1.01 seconds
Started Jul 17 05:18:09 PM PDT 24
Finished Jul 17 05:18:12 PM PDT 24
Peak memory 208644 kb
Host smart-37a4eb18-02ff-4622-b64d-0cdc0907a1af
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073238198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1073238198
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.4013714567
Short name T277
Test name
Test status
Simulation time 97316493 ps
CPU time 1.17 seconds
Started Jul 17 05:13:52 PM PDT 24
Finished Jul 17 05:13:54 PM PDT 24
Peak memory 208340 kb
Host smart-0e44dd1a-6f27-428f-83bf-bd9ee935b8d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013714567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.4013714567
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2221046944
Short name T197
Test name
Test status
Simulation time 62689672 ps
CPU time 0.94 seconds
Started Jul 17 05:16:04 PM PDT 24
Finished Jul 17 05:16:13 PM PDT 24
Peak memory 207868 kb
Host smart-760e3bbc-f96f-41ea-840f-6bf24e7c0edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221046944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2221046944
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.3949977745
Short name T219
Test name
Test status
Simulation time 167069882 ps
CPU time 8.67 seconds
Started Jul 17 05:13:40 PM PDT 24
Finished Jul 17 05:13:50 PM PDT 24
Peak memory 225520 kb
Host smart-8a75a55c-1cb0-428f-aee0-2dbffa6cfd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949977745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3949977745
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2987386867
Short name T345
Test name
Test status
Simulation time 556041470 ps
CPU time 4.08 seconds
Started Jul 17 05:16:25 PM PDT 24
Finished Jul 17 05:16:30 PM PDT 24
Peak memory 217032 kb
Host smart-e2afee8e-6b41-4893-b072-39d537f4fa74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987386867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2987386867
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.620985509
Short name T475
Test name
Test status
Simulation time 10655393213 ps
CPU time 23.37 seconds
Started Jul 17 05:13:41 PM PDT 24
Finished Jul 17 05:14:06 PM PDT 24
Peak memory 218380 kb
Host smart-fe04be0c-d764-45c4-9ca6-345d40a2376b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620985509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.620985509
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1886646193
Short name T448
Test name
Test status
Simulation time 1225941474 ps
CPU time 15.66 seconds
Started Jul 17 05:13:52 PM PDT 24
Finished Jul 17 05:14:09 PM PDT 24
Peak memory 217244 kb
Host smart-0016ca50-43ed-4b1c-92c1-1f3f95fee5a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886646193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.1
886646193
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.302893247
Short name T704
Test name
Test status
Simulation time 3032792336 ps
CPU time 7.39 seconds
Started Jul 17 05:16:25 PM PDT 24
Finished Jul 17 05:16:33 PM PDT 24
Peak memory 217732 kb
Host smart-ec53f2b1-7294-4c1c-9ec0-69a3524d86ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302893247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
prog_failure.302893247
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3962611528
Short name T569
Test name
Test status
Simulation time 1100619112 ps
CPU time 27.95 seconds
Started Jul 17 05:13:50 PM PDT 24
Finished Jul 17 05:14:19 PM PDT 24
Peak memory 217020 kb
Host smart-073edb98-0ebc-49fe-b604-ebb0375eeec5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962611528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3962611528
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1340084786
Short name T864
Test name
Test status
Simulation time 458293734 ps
CPU time 4.24 seconds
Started Jul 17 05:13:43 PM PDT 24
Finished Jul 17 05:13:49 PM PDT 24
Peak memory 217104 kb
Host smart-99983bca-da80-4caf-9f95-69ce6811476d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340084786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1340084786
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3515005557
Short name T858
Test name
Test status
Simulation time 1814725133 ps
CPU time 72.25 seconds
Started Jul 17 05:13:43 PM PDT 24
Finished Jul 17 05:14:56 PM PDT 24
Peak memory 266856 kb
Host smart-68c9b5d1-419e-4d2f-ae2c-86ed4ec59760
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515005557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3515005557
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3888874808
Short name T848
Test name
Test status
Simulation time 259315982 ps
CPU time 9.48 seconds
Started Jul 17 05:15:50 PM PDT 24
Finished Jul 17 05:16:08 PM PDT 24
Peak memory 245624 kb
Host smart-61fa37ce-c4ea-4ea5-87d6-dab8e8770732
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888874808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3888874808
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.665691050
Short name T660
Test name
Test status
Simulation time 356454433 ps
CPU time 4.01 seconds
Started Jul 17 05:20:45 PM PDT 24
Finished Jul 17 05:20:55 PM PDT 24
Peak memory 217704 kb
Host smart-5d5b9964-1c13-42d2-9362-ab33b0909b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665691050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.665691050
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2385046348
Short name T793
Test name
Test status
Simulation time 258878498 ps
CPU time 15.44 seconds
Started Jul 17 05:13:40 PM PDT 24
Finished Jul 17 05:13:56 PM PDT 24
Peak memory 213544 kb
Host smart-76811651-dd2c-47aa-aa1e-754548061d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385046348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2385046348
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.3790007821
Short name T455
Test name
Test status
Simulation time 946168762 ps
CPU time 15.02 seconds
Started Jul 17 05:13:51 PM PDT 24
Finished Jul 17 05:14:06 PM PDT 24
Peak memory 219452 kb
Host smart-ba74c573-36c9-462c-b089-4599189a1fb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790007821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.3790007821
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.148156361
Short name T214
Test name
Test status
Simulation time 226715755 ps
CPU time 7.42 seconds
Started Jul 17 05:13:53 PM PDT 24
Finished Jul 17 05:14:01 PM PDT 24
Peak memory 225472 kb
Host smart-dbdc93c4-5f80-417d-897a-f3f5d9879cc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148156361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.148156361
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1093098437
Short name T312
Test name
Test status
Simulation time 1074685140 ps
CPU time 11.34 seconds
Started Jul 17 05:13:57 PM PDT 24
Finished Jul 17 05:14:09 PM PDT 24
Peak memory 217700 kb
Host smart-729c4002-9fd0-4628-951d-c6df7650006c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093098437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
093098437
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.2899725811
Short name T863
Test name
Test status
Simulation time 389773109 ps
CPU time 9.3 seconds
Started Jul 17 05:13:41 PM PDT 24
Finished Jul 17 05:13:51 PM PDT 24
Peak memory 217796 kb
Host smart-74c975b6-212f-4be2-b2d1-7e7c5d4eaabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899725811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2899725811
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1899394431
Short name T69
Test name
Test status
Simulation time 15117549 ps
CPU time 1.03 seconds
Started Jul 17 05:13:41 PM PDT 24
Finished Jul 17 05:13:44 PM PDT 24
Peak memory 208444 kb
Host smart-eb6b766c-69cd-4dd1-9b0c-c14a5b9d5d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899394431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1899394431
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.2446314056
Short name T836
Test name
Test status
Simulation time 797813701 ps
CPU time 26.9 seconds
Started Jul 17 05:13:44 PM PDT 24
Finished Jul 17 05:14:12 PM PDT 24
Peak memory 250508 kb
Host smart-c4d23e88-7ac8-454a-97cc-5c24be8b5d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446314056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2446314056
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.253068766
Short name T213
Test name
Test status
Simulation time 67913186 ps
CPU time 3.56 seconds
Started Jul 17 05:13:39 PM PDT 24
Finished Jul 17 05:13:43 PM PDT 24
Peak memory 217760 kb
Host smart-75e266c1-1597-40d1-8a66-4a0f2253c239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253068766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.253068766
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2090667487
Short name T476
Test name
Test status
Simulation time 15567901724 ps
CPU time 253.84 seconds
Started Jul 17 05:13:51 PM PDT 24
Finished Jul 17 05:18:06 PM PDT 24
Peak memory 283468 kb
Host smart-2177511e-a4c8-4c43-9dea-d9a5da17ee03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090667487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2090667487
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2810292671
Short name T319
Test name
Test status
Simulation time 53311317 ps
CPU time 0.84 seconds
Started Jul 17 05:13:41 PM PDT 24
Finished Jul 17 05:13:43 PM PDT 24
Peak memory 211348 kb
Host smart-7b824295-bf0f-4c48-a862-ac8a76f7fdf6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810292671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2810292671
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.457252233
Short name T799
Test name
Test status
Simulation time 20205098 ps
CPU time 1.16 seconds
Started Jul 17 05:17:51 PM PDT 24
Finished Jul 17 05:17:57 PM PDT 24
Peak memory 208384 kb
Host smart-1f894bc6-9d52-4035-bd12-8bb246767f92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457252233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.457252233
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1274688213
Short name T405
Test name
Test status
Simulation time 1400321410 ps
CPU time 15.7 seconds
Started Jul 17 05:13:52 PM PDT 24
Finished Jul 17 05:14:09 PM PDT 24
Peak memory 217940 kb
Host smart-9cf25341-ba85-4978-9acd-6a0c7aae877d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274688213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1274688213
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2381498627
Short name T337
Test name
Test status
Simulation time 1591799596 ps
CPU time 10.21 seconds
Started Jul 17 05:16:06 PM PDT 24
Finished Jul 17 05:16:23 PM PDT 24
Peak memory 216964 kb
Host smart-2fb9b2dc-95af-43a8-92a4-90cd2f09bb7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381498627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2381498627
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2073030955
Short name T856
Test name
Test status
Simulation time 19717867219 ps
CPU time 62.56 seconds
Started Jul 17 05:13:54 PM PDT 24
Finished Jul 17 05:14:58 PM PDT 24
Peak memory 219180 kb
Host smart-2af16f45-8d74-481c-8462-58f01bf1495b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073030955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2073030955
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2175605079
Short name T173
Test name
Test status
Simulation time 2010811098 ps
CPU time 4.86 seconds
Started Jul 17 05:16:06 PM PDT 24
Finished Jul 17 05:16:17 PM PDT 24
Peak memory 217204 kb
Host smart-6323361d-edf0-45c3-818e-16d14428c894
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175605079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.2
175605079
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.262378869
Short name T159
Test name
Test status
Simulation time 5126603252 ps
CPU time 12.84 seconds
Started Jul 17 05:13:52 PM PDT 24
Finished Jul 17 05:14:05 PM PDT 24
Peak memory 218500 kb
Host smart-54f260b4-4fb5-4641-8688-d2548ed7343e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262378869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.262378869
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2534040420
Short name T509
Test name
Test status
Simulation time 6243117785 ps
CPU time 24.11 seconds
Started Jul 17 05:16:05 PM PDT 24
Finished Jul 17 05:16:36 PM PDT 24
Peak memory 217188 kb
Host smart-d539c886-aefb-46b0-8dc7-5470176a7d6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534040420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2534040420
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2567081732
Short name T538
Test name
Test status
Simulation time 7480924947 ps
CPU time 7.29 seconds
Started Jul 17 05:13:54 PM PDT 24
Finished Jul 17 05:14:02 PM PDT 24
Peak memory 217172 kb
Host smart-78dc8467-9675-4a0e-b078-693e6ab7b91c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567081732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2567081732
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.4092818007
Short name T703
Test name
Test status
Simulation time 9205269440 ps
CPU time 78.61 seconds
Started Jul 17 05:13:51 PM PDT 24
Finished Jul 17 05:15:10 PM PDT 24
Peak memory 283264 kb
Host smart-60256e57-3ae5-4f6c-ad5d-fd17f4a85a9b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092818007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.4092818007
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1073489356
Short name T620
Test name
Test status
Simulation time 1601012293 ps
CPU time 26.39 seconds
Started Jul 17 05:16:03 PM PDT 24
Finished Jul 17 05:16:38 PM PDT 24
Peak memory 250436 kb
Host smart-49b3293e-9512-4551-8117-c19bf0379a89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073489356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1073489356
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3571747916
Short name T680
Test name
Test status
Simulation time 486036884 ps
CPU time 2.7 seconds
Started Jul 17 05:13:53 PM PDT 24
Finished Jul 17 05:13:57 PM PDT 24
Peak memory 217820 kb
Host smart-419e3fb4-82e5-4369-a1bb-b4ca298b972f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571747916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3571747916
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.4112195414
Short name T176
Test name
Test status
Simulation time 692705586 ps
CPU time 19.6 seconds
Started Jul 17 05:14:48 PM PDT 24
Finished Jul 17 05:15:09 PM PDT 24
Peak memory 214332 kb
Host smart-80a03f64-cd4a-42af-b129-de7e67181003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112195414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.4112195414
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3085601707
Short name T600
Test name
Test status
Simulation time 1107308509 ps
CPU time 13.12 seconds
Started Jul 17 05:13:54 PM PDT 24
Finished Jul 17 05:14:07 PM PDT 24
Peak memory 218408 kb
Host smart-a3dc0e5f-365a-40c7-b745-05066ed7d236
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085601707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3085601707
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2236983390
Short name T260
Test name
Test status
Simulation time 622099239 ps
CPU time 13.62 seconds
Started Jul 17 05:15:54 PM PDT 24
Finished Jul 17 05:16:18 PM PDT 24
Peak memory 225436 kb
Host smart-af5133d4-45ae-4f67-a1e4-32ccf93c6c0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236983390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.2236983390
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1688934580
Short name T747
Test name
Test status
Simulation time 500583374 ps
CPU time 14.41 seconds
Started Jul 17 05:13:53 PM PDT 24
Finished Jul 17 05:14:08 PM PDT 24
Peak memory 217656 kb
Host smart-cecccd10-4c2f-42b6-ae51-b47401c6bb2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688934580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
688934580
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2206302318
Short name T535
Test name
Test status
Simulation time 329603896 ps
CPU time 8.94 seconds
Started Jul 17 05:13:50 PM PDT 24
Finished Jul 17 05:14:00 PM PDT 24
Peak memory 224268 kb
Host smart-9dd22dc5-b899-4dfc-bc23-2abe956abdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206302318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2206302318
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.4234282497
Short name T324
Test name
Test status
Simulation time 56353867 ps
CPU time 2.64 seconds
Started Jul 17 05:16:06 PM PDT 24
Finished Jul 17 05:16:15 PM PDT 24
Peak memory 214268 kb
Host smart-7e5fe544-c348-4b56-a5a1-0c4e255d646b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234282497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.4234282497
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.842412354
Short name T94
Test name
Test status
Simulation time 2672348223 ps
CPU time 32.82 seconds
Started Jul 17 05:17:39 PM PDT 24
Finished Jul 17 05:18:14 PM PDT 24
Peak memory 250632 kb
Host smart-c5933a22-fa88-47d3-8c40-fa5b0618baa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842412354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.842412354
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3401826964
Short name T656
Test name
Test status
Simulation time 145015060 ps
CPU time 7 seconds
Started Jul 17 05:13:51 PM PDT 24
Finished Jul 17 05:13:59 PM PDT 24
Peak memory 250408 kb
Host smart-e2c12351-93ae-46a0-80bb-2d411a8a3b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401826964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3401826964
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2525402158
Short name T160
Test name
Test status
Simulation time 9907503735 ps
CPU time 110.48 seconds
Started Jul 17 05:13:54 PM PDT 24
Finished Jul 17 05:15:45 PM PDT 24
Peak memory 283204 kb
Host smart-a882d810-52e6-4376-8331-456af99587b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525402158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2525402158
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.367743700
Short name T834
Test name
Test status
Simulation time 47955641214 ps
CPU time 398.92 seconds
Started Jul 17 05:17:51 PM PDT 24
Finished Jul 17 05:24:34 PM PDT 24
Peak memory 283436 kb
Host smart-81bd6203-e44b-45b5-b36d-827e60b79007
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=367743700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.367743700
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.4206320060
Short name T28
Test name
Test status
Simulation time 25861856 ps
CPU time 0.95 seconds
Started Jul 17 05:13:51 PM PDT 24
Finished Jul 17 05:13:53 PM PDT 24
Peak memory 211336 kb
Host smart-99d41777-0f44-425d-99be-33ec1f59bb81
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206320060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.4206320060
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2594796833
Short name T719
Test name
Test status
Simulation time 45761274 ps
CPU time 0.86 seconds
Started Jul 17 05:13:58 PM PDT 24
Finished Jul 17 05:13:59 PM PDT 24
Peak memory 208136 kb
Host smart-3bf3f3c6-9a4a-4721-8f84-11adcc5a7b3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594796833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2594796833
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.686672869
Short name T621
Test name
Test status
Simulation time 2780471879 ps
CPU time 14.48 seconds
Started Jul 17 05:13:55 PM PDT 24
Finished Jul 17 05:14:10 PM PDT 24
Peak memory 218392 kb
Host smart-8ae80179-5b35-457d-a9a0-d2444b4f0a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686672869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.686672869
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2165716970
Short name T432
Test name
Test status
Simulation time 2181879769 ps
CPU time 8.01 seconds
Started Jul 17 05:13:56 PM PDT 24
Finished Jul 17 05:14:04 PM PDT 24
Peak memory 217192 kb
Host smart-7d0a1309-87f5-416d-9773-5ec0f24364d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165716970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2165716970
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2624439167
Short name T861
Test name
Test status
Simulation time 7091879269 ps
CPU time 55.19 seconds
Started Jul 17 05:15:47 PM PDT 24
Finished Jul 17 05:16:47 PM PDT 24
Peak memory 218388 kb
Host smart-e07b31d4-a9b1-43d0-8837-cb96527b9094
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624439167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2624439167
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3484018339
Short name T671
Test name
Test status
Simulation time 9144156903 ps
CPU time 38.63 seconds
Started Jul 17 05:17:33 PM PDT 24
Finished Jul 17 05:18:13 PM PDT 24
Peak memory 217284 kb
Host smart-49f0289c-67ea-4a2e-8824-a809cc8d6331
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484018339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
484018339
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.836091240
Short name T813
Test name
Test status
Simulation time 201638125 ps
CPU time 2.36 seconds
Started Jul 17 05:13:57 PM PDT 24
Finished Jul 17 05:14:00 PM PDT 24
Peak memory 217640 kb
Host smart-67c421dc-a8aa-44ac-9f8e-d57184eb27ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836091240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.836091240
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.4171434506
Short name T452
Test name
Test status
Simulation time 4771901602 ps
CPU time 30.68 seconds
Started Jul 17 05:13:55 PM PDT 24
Finished Jul 17 05:14:27 PM PDT 24
Peak memory 217192 kb
Host smart-8c8b191e-41b0-4482-aa7d-497d88459591
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171434506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.4171434506
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.689376086
Short name T215
Test name
Test status
Simulation time 2122935183 ps
CPU time 2.23 seconds
Started Jul 17 05:15:55 PM PDT 24
Finished Jul 17 05:16:07 PM PDT 24
Peak memory 217096 kb
Host smart-d4fe88f6-8408-4290-83ce-062dd5c02e10
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689376086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.689376086
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.409791901
Short name T389
Test name
Test status
Simulation time 17463865730 ps
CPU time 56.99 seconds
Started Jul 17 05:13:56 PM PDT 24
Finished Jul 17 05:14:54 PM PDT 24
Peak memory 266840 kb
Host smart-699df567-6539-49ab-84e8-7595bc3a511e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409791901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.409791901
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.581830947
Short name T503
Test name
Test status
Simulation time 1000495161 ps
CPU time 17.54 seconds
Started Jul 17 05:16:05 PM PDT 24
Finished Jul 17 05:16:30 PM PDT 24
Peak memory 250388 kb
Host smart-d9adca51-207f-42ce-94d5-6093bf428a52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581830947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.581830947
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.902612193
Short name T743
Test name
Test status
Simulation time 326509131 ps
CPU time 3.01 seconds
Started Jul 17 05:16:11 PM PDT 24
Finished Jul 17 05:16:18 PM PDT 24
Peak memory 217684 kb
Host smart-699d4b52-9f01-4c79-a6f2-319a60c2ec8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902612193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.902612193
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3112683380
Short name T73
Test name
Test status
Simulation time 1771164041 ps
CPU time 9.49 seconds
Started Jul 17 05:16:27 PM PDT 24
Finished Jul 17 05:16:37 PM PDT 24
Peak memory 217128 kb
Host smart-c323fdea-0daa-4e37-9c57-e8581ce0ba9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112683380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3112683380
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3410072880
Short name T554
Test name
Test status
Simulation time 207194138 ps
CPU time 10.64 seconds
Started Jul 17 05:13:54 PM PDT 24
Finished Jul 17 05:14:06 PM PDT 24
Peak memory 217776 kb
Host smart-42b99387-9179-45c0-b143-657fc7628354
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410072880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3410072880
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.188537646
Short name T391
Test name
Test status
Simulation time 1739799482 ps
CPU time 15.26 seconds
Started Jul 17 05:17:31 PM PDT 24
Finished Jul 17 05:17:47 PM PDT 24
Peak memory 225464 kb
Host smart-1097384f-6fa1-483e-ab7d-790e0a5b441b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188537646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.188537646
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.873227596
Short name T590
Test name
Test status
Simulation time 740080524 ps
CPU time 7.61 seconds
Started Jul 17 05:15:43 PM PDT 24
Finished Jul 17 05:15:54 PM PDT 24
Peak memory 225468 kb
Host smart-6346cc2d-b236-400b-a594-54a27d3cb6f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873227596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.873227596
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.3564441278
Short name T559
Test name
Test status
Simulation time 307627074 ps
CPU time 8.61 seconds
Started Jul 17 05:15:56 PM PDT 24
Finished Jul 17 05:16:14 PM PDT 24
Peak memory 217820 kb
Host smart-732fe544-c3c1-4b36-b068-7a18af157c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564441278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3564441278
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.889354379
Short name T489
Test name
Test status
Simulation time 203537434 ps
CPU time 2.77 seconds
Started Jul 17 05:15:55 PM PDT 24
Finished Jul 17 05:16:08 PM PDT 24
Peak memory 217188 kb
Host smart-d9e499b3-66d7-4fa9-af4a-be5d81f15226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889354379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.889354379
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1124328936
Short name T831
Test name
Test status
Simulation time 843295155 ps
CPU time 28.89 seconds
Started Jul 17 05:13:56 PM PDT 24
Finished Jul 17 05:14:25 PM PDT 24
Peak memory 250444 kb
Host smart-8a4e36ee-7843-4db5-9e16-abee6f04f28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124328936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1124328936
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1497462024
Short name T154
Test name
Test status
Simulation time 136204058 ps
CPU time 8 seconds
Started Jul 17 05:15:56 PM PDT 24
Finished Jul 17 05:16:14 PM PDT 24
Peak memory 250504 kb
Host smart-ee105ed8-a4c5-4d93-9f3d-9d37eceef4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497462024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1497462024
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2765249764
Short name T45
Test name
Test status
Simulation time 21094211222 ps
CPU time 113.95 seconds
Started Jul 17 05:13:58 PM PDT 24
Finished Jul 17 05:15:53 PM PDT 24
Peak memory 271560 kb
Host smart-fb4d119d-d145-4954-90f8-db7c091b3785
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765249764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2765249764
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3844273171
Short name T457
Test name
Test status
Simulation time 41434480 ps
CPU time 0.91 seconds
Started Jul 17 05:13:55 PM PDT 24
Finished Jul 17 05:13:57 PM PDT 24
Peak memory 208324 kb
Host smart-b512f4b7-23b6-4ea1-8e02-a7a6538673f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844273171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3844273171
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3334560329
Short name T707
Test name
Test status
Simulation time 18566848 ps
CPU time 1.1 seconds
Started Jul 17 05:14:03 PM PDT 24
Finished Jul 17 05:14:05 PM PDT 24
Peak memory 208440 kb
Host smart-62d097bc-8620-4d93-ad66-8f1e1363442c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334560329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3334560329
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.369363765
Short name T404
Test name
Test status
Simulation time 52908305 ps
CPU time 0.83 seconds
Started Jul 17 05:13:56 PM PDT 24
Finished Jul 17 05:13:58 PM PDT 24
Peak memory 208648 kb
Host smart-18648b0f-bf33-4c46-8d7c-57225cbe9e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369363765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.369363765
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.4184881625
Short name T480
Test name
Test status
Simulation time 2230726430 ps
CPU time 17.3 seconds
Started Jul 17 05:17:22 PM PDT 24
Finished Jul 17 05:17:40 PM PDT 24
Peak memory 217836 kb
Host smart-37251398-359b-44fd-ae55-bf272d8075d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184881625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.4184881625
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3966979137
Short name T26
Test name
Test status
Simulation time 4253614166 ps
CPU time 9.46 seconds
Started Jul 17 05:13:53 PM PDT 24
Finished Jul 17 05:14:03 PM PDT 24
Peak memory 217244 kb
Host smart-fb9b23ae-38de-4c6f-9a22-07db6eb773aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966979137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3966979137
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2031288248
Short name T207
Test name
Test status
Simulation time 5371085339 ps
CPU time 44.65 seconds
Started Jul 17 05:13:53 PM PDT 24
Finished Jul 17 05:14:38 PM PDT 24
Peak memory 217824 kb
Host smart-7a6b57ab-5bd9-4cd4-83c5-bd03bdb3143d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031288248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2031288248
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1623456334
Short name T779
Test name
Test status
Simulation time 226280344 ps
CPU time 3.33 seconds
Started Jul 17 05:14:03 PM PDT 24
Finished Jul 17 05:14:07 PM PDT 24
Peak memory 217308 kb
Host smart-ac1dd357-94fa-4b6c-95bb-b4d55bb7ba9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623456334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
623456334
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2424316130
Short name T344
Test name
Test status
Simulation time 549646742 ps
CPU time 5.18 seconds
Started Jul 17 05:15:50 PM PDT 24
Finished Jul 17 05:16:01 PM PDT 24
Peak memory 217692 kb
Host smart-d3cb500b-3405-4b63-824f-5e4785da7165
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424316130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2424316130
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2862833177
Short name T230
Test name
Test status
Simulation time 1208471819 ps
CPU time 10.01 seconds
Started Jul 17 05:14:01 PM PDT 24
Finished Jul 17 05:14:12 PM PDT 24
Peak memory 217076 kb
Host smart-f9e924c6-d3a2-481e-9542-e6d1e7840932
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862833177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2862833177
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1196576659
Short name T258
Test name
Test status
Simulation time 1111071960 ps
CPU time 46.57 seconds
Started Jul 17 05:14:00 PM PDT 24
Finished Jul 17 05:14:47 PM PDT 24
Peak memory 275036 kb
Host smart-56f65125-47da-4ad8-b73e-47e130b454e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196576659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1196576659
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3965828013
Short name T847
Test name
Test status
Simulation time 657649448 ps
CPU time 24.24 seconds
Started Jul 17 05:13:56 PM PDT 24
Finished Jul 17 05:14:21 PM PDT 24
Peak memory 247384 kb
Host smart-77546c81-977f-48f4-a656-1f540f9b036f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965828013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3965828013
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1005958923
Short name T585
Test name
Test status
Simulation time 137809606 ps
CPU time 2.87 seconds
Started Jul 17 05:17:32 PM PDT 24
Finished Jul 17 05:17:36 PM PDT 24
Peak memory 221964 kb
Host smart-d5759acc-b474-445b-87e0-e22055a75964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005958923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1005958923
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1720504050
Short name T510
Test name
Test status
Simulation time 504585462 ps
CPU time 11.56 seconds
Started Jul 17 05:13:57 PM PDT 24
Finished Jul 17 05:14:09 PM PDT 24
Peak memory 222688 kb
Host smart-e89f6f23-b89d-4d92-9edd-03b89e6344ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720504050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1720504050
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3123239646
Short name T326
Test name
Test status
Simulation time 616756570 ps
CPU time 12.34 seconds
Started Jul 17 05:14:04 PM PDT 24
Finished Jul 17 05:14:17 PM PDT 24
Peak memory 225440 kb
Host smart-f8a95e01-fd4e-4277-b6a9-10aa7ed327a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123239646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3123239646
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3817077277
Short name T734
Test name
Test status
Simulation time 464256143 ps
CPU time 11.73 seconds
Started Jul 17 05:14:05 PM PDT 24
Finished Jul 17 05:14:17 PM PDT 24
Peak memory 225492 kb
Host smart-6052b341-08a3-42ec-9cda-527fdafc9c78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817077277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3817077277
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.2367783392
Short name T854
Test name
Test status
Simulation time 197989337 ps
CPU time 6.55 seconds
Started Jul 17 05:14:03 PM PDT 24
Finished Jul 17 05:14:11 PM PDT 24
Peak memory 225500 kb
Host smart-49ea30a6-9f2b-4c0d-b411-7bd00bcdd296
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367783392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2
367783392
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.635512623
Short name T307
Test name
Test status
Simulation time 245164056 ps
CPU time 7.8 seconds
Started Jul 17 05:15:52 PM PDT 24
Finished Jul 17 05:16:10 PM PDT 24
Peak memory 225564 kb
Host smart-649af8a1-14ca-46a8-82bc-f747861bc0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635512623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.635512623
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1580483136
Short name T795
Test name
Test status
Simulation time 123736341 ps
CPU time 2.22 seconds
Started Jul 17 05:17:27 PM PDT 24
Finished Jul 17 05:17:30 PM PDT 24
Peak memory 217152 kb
Host smart-0a9b4a16-7536-4f3f-bdfe-7ab2df603780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580483136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1580483136
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3690801881
Short name T356
Test name
Test status
Simulation time 289147769 ps
CPU time 20.11 seconds
Started Jul 17 05:13:58 PM PDT 24
Finished Jul 17 05:14:19 PM PDT 24
Peak memory 250464 kb
Host smart-8587a81e-39f4-4626-ab10-aac40b4fe82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690801881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3690801881
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.463153095
Short name T164
Test name
Test status
Simulation time 141459284 ps
CPU time 3.81 seconds
Started Jul 17 05:17:22 PM PDT 24
Finished Jul 17 05:17:27 PM PDT 24
Peak memory 222168 kb
Host smart-29e00838-5822-4637-a1db-c519aab087d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463153095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.463153095
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3861163306
Short name T607
Test name
Test status
Simulation time 12645972759 ps
CPU time 78.08 seconds
Started Jul 17 05:14:02 PM PDT 24
Finished Jul 17 05:15:21 PM PDT 24
Peak memory 277472 kb
Host smart-49bdfb12-3691-4393-b180-b2b8ca36b818
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861163306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3861163306
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3442117694
Short name T502
Test name
Test status
Simulation time 191913134051 ps
CPU time 517.98 seconds
Started Jul 17 05:14:07 PM PDT 24
Finished Jul 17 05:22:46 PM PDT 24
Peak memory 420792 kb
Host smart-5527ec1b-e258-4bb5-95c9-f9ee3aa0472a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3442117694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3442117694
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3687349035
Short name T716
Test name
Test status
Simulation time 14381832 ps
CPU time 1.12 seconds
Started Jul 17 05:13:58 PM PDT 24
Finished Jul 17 05:14:00 PM PDT 24
Peak memory 211352 kb
Host smart-ef8fb6c1-f16c-4bff-9b22-8c61e44f627f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687349035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3687349035
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3286817625
Short name T139
Test name
Test status
Simulation time 78285241 ps
CPU time 1.06 seconds
Started Jul 17 05:14:05 PM PDT 24
Finished Jul 17 05:14:07 PM PDT 24
Peak memory 208404 kb
Host smart-0062de87-5096-4ac2-825a-d8dbfae9567d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286817625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3286817625
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1147896188
Short name T594
Test name
Test status
Simulation time 14944461 ps
CPU time 0.83 seconds
Started Jul 17 05:14:48 PM PDT 24
Finished Jul 17 05:14:51 PM PDT 24
Peak memory 208056 kb
Host smart-b38166e9-afe4-488f-a8ff-5c1219775112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147896188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1147896188
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.170772100
Short name T507
Test name
Test status
Simulation time 795393957 ps
CPU time 10.41 seconds
Started Jul 17 05:16:04 PM PDT 24
Finished Jul 17 05:16:22 PM PDT 24
Peak memory 225484 kb
Host smart-43cea8c7-51bc-4d89-843b-b0de2a294f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170772100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.170772100
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.4227481923
Short name T658
Test name
Test status
Simulation time 2944839581 ps
CPU time 5.88 seconds
Started Jul 17 05:14:02 PM PDT 24
Finished Jul 17 05:14:08 PM PDT 24
Peak memory 217252 kb
Host smart-d1a4871e-e5fb-4f16-af6d-1c72fc2a74ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227481923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.4227481923
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3181186957
Short name T444
Test name
Test status
Simulation time 3091139627 ps
CPU time 83.83 seconds
Started Jul 17 05:14:07 PM PDT 24
Finished Jul 17 05:15:32 PM PDT 24
Peak memory 218760 kb
Host smart-81823834-97c5-401b-85a3-ce8d10a9d171
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181186957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3181186957
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2235806001
Short name T804
Test name
Test status
Simulation time 1460232573 ps
CPU time 19.35 seconds
Started Jul 17 05:14:04 PM PDT 24
Finished Jul 17 05:14:24 PM PDT 24
Peak memory 217420 kb
Host smart-78b4244e-bca9-4b51-85da-efb28a64c893
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235806001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
235806001
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3152461879
Short name T862
Test name
Test status
Simulation time 242182289 ps
CPU time 8.3 seconds
Started Jul 17 05:14:05 PM PDT 24
Finished Jul 17 05:14:14 PM PDT 24
Peak memory 222596 kb
Host smart-bbd7c13d-2318-47b6-9895-d0d8e3ae06bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152461879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.3152461879
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1905114605
Short name T141
Test name
Test status
Simulation time 7354958436 ps
CPU time 37.55 seconds
Started Jul 17 05:14:03 PM PDT 24
Finished Jul 17 05:14:41 PM PDT 24
Peak memory 217176 kb
Host smart-5d0c1cd8-1339-4f96-aa5f-ba33ce7605cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905114605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1905114605
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2316659692
Short name T625
Test name
Test status
Simulation time 202009225 ps
CPU time 3.71 seconds
Started Jul 17 05:14:03 PM PDT 24
Finished Jul 17 05:14:07 PM PDT 24
Peak memory 217056 kb
Host smart-5a734b7d-3b95-45ac-9566-9537cec08be1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316659692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2316659692
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2530828468
Short name T601
Test name
Test status
Simulation time 2528755818 ps
CPU time 58.99 seconds
Started Jul 17 05:17:33 PM PDT 24
Finished Jul 17 05:18:33 PM PDT 24
Peak memory 266852 kb
Host smart-b68c19e2-8c25-4e3c-bbc2-9a46e7588670
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530828468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2530828468
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2533190742
Short name T579
Test name
Test status
Simulation time 1364440791 ps
CPU time 16.82 seconds
Started Jul 17 05:14:05 PM PDT 24
Finished Jul 17 05:14:22 PM PDT 24
Peak memory 250432 kb
Host smart-742b4b29-67bb-43d3-bcca-c12436d99752
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533190742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2533190742
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.234129563
Short name T683
Test name
Test status
Simulation time 65866704 ps
CPU time 2.77 seconds
Started Jul 17 05:14:04 PM PDT 24
Finished Jul 17 05:14:07 PM PDT 24
Peak memory 221872 kb
Host smart-7fa3c59a-a67b-41ac-a06b-aac18093f40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234129563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.234129563
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1207965771
Short name T416
Test name
Test status
Simulation time 3831446567 ps
CPU time 15.7 seconds
Started Jul 17 05:15:50 PM PDT 24
Finished Jul 17 05:16:14 PM PDT 24
Peak memory 214760 kb
Host smart-015c949c-0bd9-46a3-9cb8-b7c6a2262208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207965771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1207965771
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.2726543220
Short name T250
Test name
Test status
Simulation time 418238027 ps
CPU time 17.45 seconds
Started Jul 17 05:14:02 PM PDT 24
Finished Jul 17 05:14:20 PM PDT 24
Peak memory 217972 kb
Host smart-78f04302-f371-4eeb-b6b0-74ff759d7c79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726543220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2726543220
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.342683707
Short name T16
Test name
Test status
Simulation time 1438771709 ps
CPU time 11.21 seconds
Started Jul 17 05:14:12 PM PDT 24
Finished Jul 17 05:14:24 PM PDT 24
Peak memory 225528 kb
Host smart-9121c4ca-6f8a-42bc-81a7-b8d194de28ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342683707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.342683707
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.118357398
Short name T511
Test name
Test status
Simulation time 280438821 ps
CPU time 7.56 seconds
Started Jul 17 05:14:05 PM PDT 24
Finished Jul 17 05:14:13 PM PDT 24
Peak memory 217712 kb
Host smart-891898f3-aecf-46aa-b2d3-3b15e6c15d03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118357398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.118357398
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.643614702
Short name T306
Test name
Test status
Simulation time 1138870351 ps
CPU time 10.56 seconds
Started Jul 17 05:14:04 PM PDT 24
Finished Jul 17 05:14:16 PM PDT 24
Peak memory 224496 kb
Host smart-05dc52c6-6ff7-4ef8-91cc-11ef3ffa1a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643614702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.643614702
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2276309603
Short name T770
Test name
Test status
Simulation time 70779594 ps
CPU time 1.2 seconds
Started Jul 17 05:14:04 PM PDT 24
Finished Jul 17 05:14:07 PM PDT 24
Peak memory 213120 kb
Host smart-9cb266a3-a43a-4109-872c-7e20632e17cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276309603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2276309603
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2320624227
Short name T533
Test name
Test status
Simulation time 1279230217 ps
CPU time 30.82 seconds
Started Jul 17 05:14:04 PM PDT 24
Finished Jul 17 05:14:36 PM PDT 24
Peak memory 250540 kb
Host smart-efe5d6d3-fa6b-4862-8f47-c3671e2b0a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320624227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2320624227
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2079961616
Short name T692
Test name
Test status
Simulation time 72415626 ps
CPU time 8.26 seconds
Started Jul 17 05:15:54 PM PDT 24
Finished Jul 17 05:16:13 PM PDT 24
Peak memory 250476 kb
Host smart-488b297f-7c56-4370-b254-5e3adfc60234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079961616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2079961616
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3654742569
Short name T96
Test name
Test status
Simulation time 2958605718 ps
CPU time 67.15 seconds
Started Jul 17 05:14:04 PM PDT 24
Finished Jul 17 05:15:12 PM PDT 24
Peak memory 272856 kb
Host smart-ebf31fb2-eff3-4730-bb59-db9855adcf89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654742569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3654742569
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.3679451658
Short name T583
Test name
Test status
Simulation time 18594585091 ps
CPU time 408.01 seconds
Started Jul 17 05:15:01 PM PDT 24
Finished Jul 17 05:21:50 PM PDT 24
Peak memory 496728 kb
Host smart-16d09d77-b89a-4822-9e10-f49a43288ff4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3679451658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.3679451658
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1846083142
Short name T34
Test name
Test status
Simulation time 33908247 ps
CPU time 1.01 seconds
Started Jul 17 05:14:02 PM PDT 24
Finished Jul 17 05:14:04 PM PDT 24
Peak memory 211452 kb
Host smart-f8a8469e-6f60-4ea3-9acb-74d4c8e7831f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846083142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1846083142
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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