Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48305 |
1 |
|
|
T1 |
19 |
|
T2 |
82 |
|
T4 |
86 |
auto[1] |
1863 |
1 |
|
|
T2 |
13 |
|
T18 |
8 |
|
T26 |
4 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49585 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[1] |
583 |
1 |
|
|
T41 |
20 |
|
T47 |
22 |
|
T52 |
10 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48486 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[1] |
1682 |
1 |
|
|
T50 |
7 |
|
T23 |
14 |
|
T71 |
16 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48398 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[1] |
1770 |
1 |
|
|
T40 |
1 |
|
T49 |
1 |
|
T69 |
1 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48393 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[1] |
1775 |
1 |
|
|
T44 |
1 |
|
T49 |
1 |
|
T69 |
1 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
46309 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
no_err_inj |
3859 |
1 |
|
|
T13 |
17 |
|
T5 |
8 |
|
T28 |
8 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48404 |
1 |
|
|
T1 |
19 |
|
T2 |
85 |
|
T4 |
86 |
auto[1] |
1764 |
1 |
|
|
T2 |
10 |
|
T18 |
15 |
|
T26 |
9 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49620 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[1] |
548 |
1 |
|
|
T41 |
10 |
|
T47 |
13 |
|
T52 |
18 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
35019 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[1] |
15149 |
1 |
|
|
T5 |
8 |
|
T10 |
85 |
|
T19 |
95 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48499 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[1] |
1669 |
1 |
|
|
T49 |
1 |
|
T57 |
1 |
|
T50 |
5 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48419 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[1] |
1749 |
1 |
|
|
T40 |
2 |
|
T44 |
1 |
|
T69 |
2 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48451 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[1] |
1717 |
1 |
|
|
T40 |
1 |
|
T49 |
1 |
|
T50 |
7 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48329 |
1 |
|
|
T1 |
19 |
|
T2 |
79 |
|
T4 |
86 |
auto[1] |
1839 |
1 |
|
|
T2 |
16 |
|
T18 |
13 |
|
T26 |
8 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48173 |
1 |
|
|
T2 |
95 |
|
T4 |
86 |
|
T13 |
17 |
auto[1] |
1995 |
1 |
|
|
T1 |
19 |
|
T12 |
13 |
|
T16 |
19 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49605 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[1] |
563 |
1 |
|
|
T41 |
13 |
|
T47 |
21 |
|
T52 |
13 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49601 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[1] |
567 |
1 |
|
|
T41 |
13 |
|
T47 |
21 |
|
T52 |
15 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49609 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[1] |
559 |
1 |
|
|
T41 |
7 |
|
T47 |
13 |
|
T52 |
11 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48032 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[1] |
2136 |
1 |
|
|
T40 |
12 |
|
T44 |
14 |
|
T49 |
12 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46456 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T12 |
13 |
auto[1] |
3712 |
1 |
|
|
T4 |
86 |
|
T30 |
94 |
|
T43 |
95 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48401 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[1] |
1767 |
1 |
|
|
T40 |
1 |
|
T44 |
1 |
|
T50 |
7 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48321 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[1] |
1847 |
1 |
|
|
T40 |
2 |
|
T44 |
2 |
|
T49 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48445 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[1] |
1723 |
1 |
|
|
T40 |
1 |
|
T44 |
2 |
|
T49 |
1 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48334 |
1 |
|
|
T1 |
19 |
|
T2 |
84 |
|
T4 |
86 |
auto[1] |
1834 |
1 |
|
|
T2 |
11 |
|
T18 |
8 |
|
T26 |
12 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
44706 |
1 |
|
|
T1 |
19 |
|
T2 |
82 |
|
T4 |
86 |
auto[1] |
5462 |
1 |
|
|
T2 |
13 |
|
T15 |
63 |
|
T18 |
7 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46350 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[1] |
3818 |
1 |
|
|
T17 |
98 |
|
T48 |
80 |
|
T68 |
59 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50168 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48323 |
1 |
|
|
T1 |
19 |
|
T2 |
87 |
|
T4 |
86 |
auto[1] |
1845 |
1 |
|
|
T2 |
8 |
|
T18 |
8 |
|
T26 |
7 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48310 |
1 |
|
|
T1 |
19 |
|
T2 |
88 |
|
T4 |
86 |
auto[1] |
1858 |
1 |
|
|
T2 |
7 |
|
T18 |
13 |
|
T26 |
6 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48368 |
1 |
|
|
T1 |
19 |
|
T2 |
78 |
|
T4 |
86 |
auto[1] |
1800 |
1 |
|
|
T2 |
17 |
|
T18 |
9 |
|
T26 |
5 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
45249 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[0] |
no_err_inj |
2783 |
1 |
|
|
T13 |
17 |
|
T5 |
8 |
|
T28 |
8 |
auto[1] |
err_inj |
1060 |
1 |
|
|
T40 |
8 |
|
T44 |
7 |
|
T49 |
6 |
auto[1] |
no_err_inj |
1076 |
1 |
|
|
T40 |
4 |
|
T44 |
7 |
|
T49 |
6 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46317 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[0] |
auto[1] |
1715 |
1 |
|
|
T50 |
3 |
|
T23 |
11 |
|
T71 |
22 |
auto[1] |
auto[0] |
2004 |
1 |
|
|
T40 |
10 |
|
T44 |
12 |
|
T49 |
11 |
auto[1] |
auto[1] |
132 |
1 |
|
|
T40 |
2 |
|
T44 |
2 |
|
T49 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46396 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[0] |
auto[1] |
1636 |
1 |
|
|
T50 |
4 |
|
T23 |
4 |
|
T71 |
19 |
auto[1] |
auto[0] |
2023 |
1 |
|
|
T40 |
10 |
|
T44 |
13 |
|
T49 |
12 |
auto[1] |
auto[1] |
113 |
1 |
|
|
T40 |
2 |
|
T44 |
1 |
|
T69 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46427 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[0] |
auto[1] |
1605 |
1 |
|
|
T50 |
5 |
|
T23 |
5 |
|
T71 |
16 |
auto[1] |
auto[0] |
2018 |
1 |
|
|
T40 |
11 |
|
T44 |
12 |
|
T49 |
11 |
auto[1] |
auto[1] |
118 |
1 |
|
|
T40 |
1 |
|
T44 |
2 |
|
T49 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46393 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[0] |
auto[1] |
1639 |
1 |
|
|
T50 |
6 |
|
T23 |
5 |
|
T71 |
16 |
auto[1] |
auto[0] |
2005 |
1 |
|
|
T40 |
11 |
|
T44 |
14 |
|
T49 |
11 |
auto[1] |
auto[1] |
131 |
1 |
|
|
T40 |
1 |
|
T49 |
1 |
|
T69 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46391 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[0] |
auto[1] |
1641 |
1 |
|
|
T50 |
9 |
|
T23 |
13 |
|
T71 |
17 |
auto[1] |
auto[0] |
2002 |
1 |
|
|
T40 |
12 |
|
T44 |
13 |
|
T49 |
11 |
auto[1] |
auto[1] |
134 |
1 |
|
|
T44 |
1 |
|
T49 |
1 |
|
T69 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46481 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[0] |
auto[1] |
1551 |
1 |
|
|
T50 |
7 |
|
T23 |
14 |
|
T71 |
14 |
auto[1] |
auto[0] |
2005 |
1 |
|
|
T40 |
12 |
|
T44 |
14 |
|
T49 |
12 |
auto[1] |
auto[1] |
131 |
1 |
|
|
T71 |
2 |
|
T220 |
1 |
|
T103 |
3 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33873 |
1 |
|
|
T1 |
19 |
|
T2 |
82 |
|
T4 |
86 |
auto[0] |
auto[1] |
1146 |
1 |
|
|
T2 |
13 |
|
T18 |
8 |
|
T26 |
4 |
auto[1] |
auto[0] |
14432 |
1 |
|
|
T5 |
8 |
|
T10 |
77 |
|
T19 |
81 |
auto[1] |
auto[1] |
717 |
1 |
|
|
T10 |
8 |
|
T19 |
14 |
|
T20 |
9 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33933 |
1 |
|
|
T1 |
19 |
|
T2 |
85 |
|
T4 |
86 |
auto[0] |
auto[1] |
1086 |
1 |
|
|
T2 |
10 |
|
T18 |
15 |
|
T26 |
9 |
auto[1] |
auto[0] |
14471 |
1 |
|
|
T5 |
8 |
|
T10 |
64 |
|
T19 |
82 |
auto[1] |
auto[1] |
678 |
1 |
|
|
T10 |
21 |
|
T19 |
13 |
|
T20 |
11 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33850 |
1 |
|
|
T2 |
95 |
|
T4 |
86 |
|
T13 |
17 |
auto[0] |
auto[1] |
1169 |
1 |
|
|
T1 |
19 |
|
T12 |
13 |
|
T16 |
19 |
auto[1] |
auto[0] |
14323 |
1 |
|
|
T5 |
8 |
|
T10 |
85 |
|
T19 |
95 |
auto[1] |
auto[1] |
826 |
1 |
|
|
T21 |
3 |
|
T71 |
10 |
|
T221 |
1 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33851 |
1 |
|
|
T1 |
19 |
|
T2 |
79 |
|
T4 |
86 |
auto[0] |
auto[1] |
1168 |
1 |
|
|
T2 |
16 |
|
T18 |
13 |
|
T26 |
8 |
auto[1] |
auto[0] |
14478 |
1 |
|
|
T5 |
8 |
|
T10 |
76 |
|
T19 |
82 |
auto[1] |
auto[1] |
671 |
1 |
|
|
T10 |
9 |
|
T19 |
13 |
|
T20 |
15 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30255 |
1 |
|
|
T1 |
19 |
|
T2 |
82 |
|
T4 |
86 |
auto[0] |
auto[1] |
4764 |
1 |
|
|
T2 |
13 |
|
T15 |
63 |
|
T18 |
7 |
auto[1] |
auto[0] |
14451 |
1 |
|
|
T5 |
8 |
|
T10 |
74 |
|
T19 |
86 |
auto[1] |
auto[1] |
698 |
1 |
|
|
T10 |
11 |
|
T19 |
9 |
|
T20 |
12 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33975 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[0] |
auto[1] |
1044 |
1 |
|
|
T40 |
2 |
|
T44 |
2 |
|
T49 |
1 |
auto[1] |
auto[0] |
14346 |
1 |
|
|
T5 |
8 |
|
T10 |
85 |
|
T19 |
95 |
auto[1] |
auto[1] |
803 |
1 |
|
|
T23 |
11 |
|
T103 |
2 |
|
T65 |
7 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33996 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[0] |
auto[1] |
1023 |
1 |
|
|
T40 |
1 |
|
T44 |
1 |
|
T50 |
7 |
auto[1] |
auto[0] |
14405 |
1 |
|
|
T5 |
8 |
|
T10 |
85 |
|
T19 |
95 |
auto[1] |
auto[1] |
744 |
1 |
|
|
T23 |
11 |
|
T103 |
1 |
|
T65 |
6 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34041 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[0] |
auto[1] |
978 |
1 |
|
|
T40 |
2 |
|
T44 |
1 |
|
T69 |
2 |
auto[1] |
auto[0] |
14378 |
1 |
|
|
T5 |
8 |
|
T10 |
85 |
|
T19 |
95 |
auto[1] |
auto[1] |
771 |
1 |
|
|
T23 |
4 |
|
T65 |
2 |
|
T96 |
1 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34053 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[0] |
auto[1] |
966 |
1 |
|
|
T49 |
1 |
|
T57 |
1 |
|
T50 |
5 |
auto[1] |
auto[0] |
14446 |
1 |
|
|
T5 |
8 |
|
T10 |
85 |
|
T19 |
95 |
auto[1] |
auto[1] |
703 |
1 |
|
|
T23 |
13 |
|
T65 |
7 |
|
T96 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34038 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[0] |
auto[1] |
981 |
1 |
|
|
T40 |
1 |
|
T49 |
1 |
|
T69 |
1 |
auto[1] |
auto[0] |
14360 |
1 |
|
|
T5 |
8 |
|
T10 |
85 |
|
T19 |
95 |
auto[1] |
auto[1] |
789 |
1 |
|
|
T23 |
5 |
|
T65 |
11 |
|
T95 |
2 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34084 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[0] |
auto[1] |
935 |
1 |
|
|
T50 |
7 |
|
T71 |
16 |
|
T220 |
1 |
auto[1] |
auto[0] |
14402 |
1 |
|
|
T5 |
8 |
|
T10 |
85 |
|
T19 |
95 |
auto[1] |
auto[1] |
747 |
1 |
|
|
T23 |
14 |
|
T103 |
3 |
|
T65 |
7 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33903 |
1 |
|
|
T1 |
19 |
|
T2 |
78 |
|
T4 |
86 |
auto[0] |
auto[1] |
1116 |
1 |
|
|
T2 |
17 |
|
T18 |
9 |
|
T26 |
5 |
auto[1] |
auto[0] |
14465 |
1 |
|
|
T5 |
8 |
|
T10 |
79 |
|
T19 |
85 |
auto[1] |
auto[1] |
684 |
1 |
|
|
T10 |
6 |
|
T19 |
10 |
|
T20 |
11 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33862 |
1 |
|
|
T1 |
19 |
|
T2 |
88 |
|
T4 |
86 |
auto[0] |
auto[1] |
1157 |
1 |
|
|
T2 |
7 |
|
T18 |
13 |
|
T26 |
6 |
auto[1] |
auto[0] |
14448 |
1 |
|
|
T5 |
8 |
|
T10 |
77 |
|
T19 |
77 |
auto[1] |
auto[1] |
701 |
1 |
|
|
T10 |
8 |
|
T19 |
18 |
|
T20 |
10 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33783 |
1 |
|
|
T1 |
19 |
|
T2 |
95 |
|
T4 |
86 |
auto[0] |
auto[1] |
1236 |
1 |
|
|
T40 |
12 |
|
T44 |
14 |
|
T49 |
12 |
auto[1] |
auto[0] |
14249 |
1 |
|
|
T5 |
8 |
|
T10 |
85 |
|
T19 |
95 |
auto[1] |
auto[1] |
900 |
1 |
|
|
T103 |
14 |
|
T95 |
12 |
|
T96 |
36 |