Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97457956

1

T1

6048

T2

36471

T3

1220

auto[1]

1326350

1

T1

693

T2

891

T4

11020

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97451127

1

T1

5553

T2

36966

T3

1220

auto[1]

1333179

1

T1

1188

T2

396

T4

11004

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6960816	1			T1	1715		T2	8751		T3	114
auto[IdleSt]	22670753	1			T1	1277		T2	7846		T3	1106
auto[ClkMuxSt]	33419	1			T1	19		T2	95		T4	71
auto[CntIncrSt]	33183	1			T1	19		T2	95		T4	68
auto[CntProgSt]	1852694	1			T1	206		T2	2365		T4	938
auto[TransCheckSt]	25873	1			T2	75		T4	35		T13	17
auto[TokenHashSt]	35071805	1			T2	632		T4	588		T13	948
auto[FlashRmaSt]	30709	1			T2	45		T4	75		T13	43
auto[TokenCheck0St]	11175	1			T2	26		T4	20		T13	17
auto[TokenCheck1St]	8126	1			T2	16		T4	20		T13	17
auto[TransProgSt]	489229	1			T2	464		T4	51		T13	461
auto[PostTransSt]	13191368	1			T1	1099		T2	15148		T12	1008
auto[ScrapSt]	142279	1			T4	6		T5	3365		T30	6
auto[EscalateSt]	6524713	1			T1	2406		T2	1804		T4	16325
auto[InvalidSt]	11736354	1			T40	448		T41	1033		T44	375

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1810	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11736354	1			T40	448		T41	1033		T44	375
EscalateSt	6524713	1			T1	2406		T2	1804		T4	16325
ScrapSt	142279	1			T4	6		T5	3365		T30	6
PostTransSt	13191368	1			T1	1099		T2	15148		T12	1008
TransProgSt	489229	1			T2	464		T4	51		T13	461
TokenCheck1St	8126	1			T2	16		T4	20		T13	17
TokenCheck0St	11175	1			T2	26		T4	20		T13	17
FlashRmaSt	30709	1			T2	45		T4	75		T13	43
TokenHashSt	35071805	1			T2	632		T4	588		T13	948
TransCheckSt	25873	1			T2	75		T4	35		T13	17
CntProgSt	1852694	1			T1	206		T2	2365		T4	938
CntIncrSt	33183	1			T1	19		T2	95		T4	68
ClkMuxSt	33419	1			T1	19		T2	95		T4	71
IdleSt	22670753	1			T1	1277		T2	7846		T3	1106
ResetSt	6960816	1			T1	1715		T2	8751		T3	114
arcs[ResetSt=>IdleSt]	50389	1			T1	20		T2	96		T3	1
arcs[IdleSt=>ScrapSt]	251	1			T4	2		T5	1		T30	2
arcs[IdleSt=>ClkMuxSt]	33264	1			T1	19		T2	95		T4	71
arcs[ClkMuxSt=>CntIncrSt]	33183	1			T1	19		T2	95		T4	68
arcs[CntIncrSt=>PostTransSt]	1858	1			T2	7		T18	13		T26	6
arcs[CntIncrSt=>CntProgSt]	31260	1			T1	19		T2	88		T4	65
arcs[CntProgSt=>PostTransSt]	4417	1			T1	19		T2	13		T12	13
arcs[CntProgSt=>TransCheckSt]	25873	1			T2	75		T4	35		T13	17
arcs[TransCheckSt=>PostTransSt]	3764	1			T2	17		T17	46		T18	9
arcs[TransCheckSt=>TokenHashSt]	21972	1			T2	58		T4	35		T13	17
arcs[TokenHashSt=>PostTransSt]	9988	1			T2	32		T15	63		T17	12
arcs[TokenHashSt=>FlashRmaSt]	11288	1			T2	26		T4	25		T13	17
arcs[FlashRmaSt=>TokenCheck0St]	11175	1			T2	26		T4	20		T13	17
arcs[TokenCheck0St=>PostTransSt]	3023	1			T2	10		T17	26		T18	12
arcs[TokenCheck0St=>TokenCheck1St]	8126	1			T2	16		T4	20		T13	17
arcs[TokenCheck1St=>PostTransSt]	620	1			T17	14		T18	3		T27	3
arcs[TransProgSt=>PostTransSt]	6667	1			T2	16		T13	17		T5	7
arcs[IdleSt=>EscalateSt]	231	1			T4	8		T43	11		T58	6
arcs[ClkMuxSt=>EscalateSt]	81	1			T4	3		T30	1		T43	5
arcs[CntIncrSt=>EscalateSt]	65	1			T4	3		T30	2		T43	3
arcs[CntProgSt=>EscalateSt]	970	1			T4	30		T30	14		T43	21
arcs[TransCheckSt=>EscalateSt]	137	1			T30	10		T43	3		T58	5
arcs[TokenHashSt=>EscalateSt]	696	1			T4	10		T27	1		T30	31
arcs[FlashRmaSt=>EscalateSt]	113	1			T4	5		T30	1		T43	3
arcs[TokenCheck0St=>EscalateSt]	26	1			T43	1		T58	1		T62	2
arcs[TokenCheck1St=>EscalateSt]	143	1			T30	6		T43	3		T58	4
arcs[TransProgSt=>EscalateSt]	696	1			T4	20		T30	10		T43	19
arcs[PostTransSt=>EscalateSt]	4680	1			T1	19		T2	13		T12	13
arcs[InvalidSt=>EscalateSt]	12834	1			T40	6		T41	13		T44	5

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6960638	1			T1	1715		T2	8751		T3	114
auto[0]	auto[IdleSt]	22670614	1			T1	1277		T2	7846		T3	1106
auto[0]	auto[ClkMuxSt]	33365	1			T1	19		T2	95		T4	68
auto[0]	auto[CntIncrSt]	33139	1			T1	19		T2	95		T4	65
auto[0]	auto[CntProgSt]	1852075	1			T1	206		T2	2365		T4	920
auto[0]	auto[TransCheckSt]	25789	1			T2	75		T4	35		T13	17
auto[0]	auto[TokenHashSt]	35071338	1			T2	632		T4	581		T13	948
auto[0]	auto[FlashRmaSt]	30631	1			T2	45		T4	71		T13	43
auto[0]	auto[TokenCheck0St]	11157	1			T2	26		T4	20		T13	17
auto[0]	auto[TokenCheck1St]	8028	1			T2	16		T4	20		T13	17
auto[0]	auto[TransProgSt]	488787	1			T2	464		T4	38		T13	461
auto[0]	auto[PostTransSt]	13188902	1			T1	1092		T2	15139		T12	1002
auto[0]	auto[ScrapSt]	142239	1			T4	5		T5	3365		T30	6
auto[0]	auto[EscalateSt]	5209490	1			T1	1720		T2	922		T4	5362
auto[0]	auto[InvalidSt]	11729954	1			T40	445		T41	1025		T44	374
auto[1]	auto[ResetSt]	178	1			T4	5		T30	5		T43	3
auto[1]	auto[IdleSt]	139	1			T4	3		T43	7		T58	4
auto[1]	auto[ClkMuxSt]	54	1			T4	3		T43	3		T58	2
auto[1]	auto[CntIncrSt]	44	1			T4	3		T43	2		T92	2
auto[1]	auto[CntProgSt]	619	1			T4	18		T30	5		T43	13
auto[1]	auto[TransCheckSt]	84	1			T30	5		T43	2		T58	3
auto[1]	auto[TokenHashSt]	467	1			T4	7		T27	1		T30	18
auto[1]	auto[FlashRmaSt]	78	1			T4	4		T30	1		T43	2
auto[1]	auto[TokenCheck0St]	18	1			T58	1		T62	2		T219	1
auto[1]	auto[TokenCheck1St]	98	1			T30	3		T43	3		T58	3
auto[1]	auto[TransProgSt]	442	1			T4	13		T30	5		T43	14
auto[1]	auto[PostTransSt]	2466	1			T1	7		T2	9		T12	6
auto[1]	auto[ScrapSt]	40	1			T4	1		T43	2		T58	1
auto[1]	auto[EscalateSt]	1315223	1			T1	686		T2	882		T4	10963
auto[1]	auto[InvalidSt]	6400	1			T40	3		T41	8		T44	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6960640	1			T1	1715		T2	8751		T3	114
auto[0]	auto[IdleSt]	22670590	1			T1	1277		T2	7846		T3	1106
auto[0]	auto[ClkMuxSt]	33363	1			T1	19		T2	95		T4	70
auto[0]	auto[CntIncrSt]	33141	1			T1	19		T2	95		T4	68
auto[0]	auto[CntProgSt]	1852036	1			T1	206		T2	2365		T4	920
auto[0]	auto[TransCheckSt]	25778	1			T2	75		T4	35		T13	17
auto[0]	auto[TokenHashSt]	35071336	1			T2	632		T4	580		T13	948
auto[0]	auto[FlashRmaSt]	30636	1			T2	45		T4	72		T13	43
auto[0]	auto[TokenCheck0St]	11155	1			T2	26		T4	20		T13	17
auto[0]	auto[TokenCheck1St]	8030	1			T2	16		T4	20		T13	17
auto[0]	auto[TransProgSt]	488742	1			T2	464		T4	37		T13	461
auto[0]	auto[PostTransSt]	13189078	1			T1	1087		T2	15144		T12	1001
auto[0]	auto[ScrapSt]	142241	1			T4	4		T5	3365		T30	4
auto[0]	auto[EscalateSt]	5202631	1			T1	1230		T2	1412		T4	5379
auto[0]	auto[InvalidSt]	11729920	1			T40	445		T41	1028		T44	371
auto[1]	auto[ResetSt]	176	1			T4	4		T30	3		T43	1
auto[1]	auto[IdleSt]	163	1			T4	8		T43	6		T58	5
auto[1]	auto[ClkMuxSt]	56	1			T4	1		T30	1		T43	5
auto[1]	auto[CntIncrSt]	42	1			T30	2		T43	2		T58	2
auto[1]	auto[CntProgSt]	658	1			T4	18		T30	13		T43	16
auto[1]	auto[TransCheckSt]	95	1			T30	7		T43	2		T58	4
auto[1]	auto[TokenHashSt]	469	1			T4	8		T30	21		T43	12
auto[1]	auto[FlashRmaSt]	73	1			T4	3		T30	1		T43	2
auto[1]	auto[TokenCheck0St]	20	1			T43	1		T58	1		T62	1
auto[1]	auto[TokenCheck1St]	96	1			T30	5		T43	2		T58	4
auto[1]	auto[TransProgSt]	487	1			T4	14		T30	7		T43	15
auto[1]	auto[PostTransSt]	2290	1			T1	12		T2	4		T12	7
auto[1]	auto[ScrapSt]	38	1			T4	2		T30	2		T43	1
auto[1]	auto[EscalateSt]	1322082	1			T1	1176		T2	392		T4	10946
auto[1]	auto[InvalidSt]	6434	1			T40	3		T41	5		T44	4