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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.88 97.99 95.77 93.40 97.67 98.55 98.51 96.29


Total test records in report: 989
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T812 /workspace/coverage/default/13.lc_ctrl_smoke.2548564505 Jul 19 05:01:17 PM PDT 24 Jul 19 05:01:22 PM PDT 24 96550857 ps
T108 /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.4253626696 Jul 19 05:00:51 PM PDT 24 Jul 19 05:04:32 PM PDT 24 7785415164 ps
T813 /workspace/coverage/default/19.lc_ctrl_jtag_smoke.508115892 Jul 19 05:01:46 PM PDT 24 Jul 19 05:01:54 PM PDT 24 196872129 ps
T814 /workspace/coverage/default/30.lc_ctrl_security_escalation.2009077930 Jul 19 05:02:34 PM PDT 24 Jul 19 05:02:44 PM PDT 24 1120546430 ps
T815 /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3611602598 Jul 19 05:00:16 PM PDT 24 Jul 19 05:01:04 PM PDT 24 12185093281 ps
T816 /workspace/coverage/default/22.lc_ctrl_prog_failure.3814888307 Jul 19 05:01:51 PM PDT 24 Jul 19 05:01:54 PM PDT 24 114690938 ps
T817 /workspace/coverage/default/13.lc_ctrl_state_failure.3777646752 Jul 19 05:01:17 PM PDT 24 Jul 19 05:01:39 PM PDT 24 753788538 ps
T818 /workspace/coverage/default/38.lc_ctrl_errors.1651859442 Jul 19 05:02:57 PM PDT 24 Jul 19 05:03:13 PM PDT 24 418650642 ps
T819 /workspace/coverage/default/7.lc_ctrl_sec_token_digest.688695406 Jul 19 05:00:51 PM PDT 24 Jul 19 05:01:04 PM PDT 24 758316566 ps
T820 /workspace/coverage/default/39.lc_ctrl_security_escalation.3668101767 Jul 19 05:02:59 PM PDT 24 Jul 19 05:03:12 PM PDT 24 549788750 ps
T821 /workspace/coverage/default/12.lc_ctrl_stress_all.2525472958 Jul 19 05:01:18 PM PDT 24 Jul 19 05:02:42 PM PDT 24 9190560820 ps
T822 /workspace/coverage/default/22.lc_ctrl_jtag_access.2279818211 Jul 19 05:01:57 PM PDT 24 Jul 19 05:02:06 PM PDT 24 3254374482 ps
T823 /workspace/coverage/default/35.lc_ctrl_smoke.424612297 Jul 19 05:02:45 PM PDT 24 Jul 19 05:02:52 PM PDT 24 20297198 ps
T824 /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1423724947 Jul 19 05:00:59 PM PDT 24 Jul 19 05:01:42 PM PDT 24 2620581894 ps
T825 /workspace/coverage/default/48.lc_ctrl_state_post_trans.4087588561 Jul 19 05:03:32 PM PDT 24 Jul 19 05:03:38 PM PDT 24 88633448 ps
T826 /workspace/coverage/default/5.lc_ctrl_jtag_priority.393652726 Jul 19 05:00:40 PM PDT 24 Jul 19 05:00:50 PM PDT 24 551267739 ps
T827 /workspace/coverage/default/37.lc_ctrl_errors.1695802638 Jul 19 05:02:59 PM PDT 24 Jul 19 05:03:16 PM PDT 24 296776102 ps
T828 /workspace/coverage/default/29.lc_ctrl_state_post_trans.221324024 Jul 19 05:02:25 PM PDT 24 Jul 19 05:02:35 PM PDT 24 86591612 ps
T829 /workspace/coverage/default/43.lc_ctrl_errors.2458100980 Jul 19 05:03:16 PM PDT 24 Jul 19 05:03:34 PM PDT 24 455735045 ps
T830 /workspace/coverage/default/18.lc_ctrl_state_post_trans.768564089 Jul 19 05:01:41 PM PDT 24 Jul 19 05:01:51 PM PDT 24 72915541 ps
T831 /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1765513356 Jul 19 05:01:24 PM PDT 24 Jul 19 05:01:43 PM PDT 24 358071261 ps
T832 /workspace/coverage/default/9.lc_ctrl_security_escalation.3991183706 Jul 19 05:01:01 PM PDT 24 Jul 19 05:01:11 PM PDT 24 281213489 ps
T833 /workspace/coverage/default/39.lc_ctrl_errors.3767808350 Jul 19 05:03:02 PM PDT 24 Jul 19 05:03:18 PM PDT 24 2193485780 ps
T834 /workspace/coverage/default/10.lc_ctrl_security_escalation.3653222257 Jul 19 05:01:08 PM PDT 24 Jul 19 05:01:21 PM PDT 24 245398357 ps
T835 /workspace/coverage/default/46.lc_ctrl_errors.2998826416 Jul 19 05:03:25 PM PDT 24 Jul 19 05:03:42 PM PDT 24 327648219 ps
T836 /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2368219733 Jul 19 05:00:17 PM PDT 24 Jul 19 05:00:23 PM PDT 24 135606815 ps
T837 /workspace/coverage/default/29.lc_ctrl_sec_token_mux.225016190 Jul 19 05:02:25 PM PDT 24 Jul 19 05:02:38 PM PDT 24 634370295 ps
T838 /workspace/coverage/default/20.lc_ctrl_smoke.979069793 Jul 19 05:01:51 PM PDT 24 Jul 19 05:01:55 PM PDT 24 94583909 ps
T839 /workspace/coverage/default/46.lc_ctrl_sec_token_mux.381435507 Jul 19 05:03:22 PM PDT 24 Jul 19 05:03:33 PM PDT 24 4690100208 ps
T840 /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3394267942 Jul 19 05:01:26 PM PDT 24 Jul 19 05:01:44 PM PDT 24 2979856192 ps
T841 /workspace/coverage/default/46.lc_ctrl_prog_failure.89543254 Jul 19 05:03:21 PM PDT 24 Jul 19 05:03:26 PM PDT 24 185554106 ps
T842 /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3548596297 Jul 19 05:00:35 PM PDT 24 Jul 19 05:00:40 PM PDT 24 23562930 ps
T843 /workspace/coverage/default/16.lc_ctrl_state_failure.1041241385 Jul 19 05:01:39 PM PDT 24 Jul 19 05:02:12 PM PDT 24 548885325 ps
T844 /workspace/coverage/default/44.lc_ctrl_smoke.40166593 Jul 19 05:03:17 PM PDT 24 Jul 19 05:03:20 PM PDT 24 23569307 ps
T845 /workspace/coverage/default/26.lc_ctrl_alert_test.1130159958 Jul 19 05:02:17 PM PDT 24 Jul 19 05:02:21 PM PDT 24 38105910 ps
T846 /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3273034392 Jul 19 05:01:19 PM PDT 24 Jul 19 05:01:30 PM PDT 24 1606958766 ps
T847 /workspace/coverage/default/9.lc_ctrl_prog_failure.3803192474 Jul 19 05:00:58 PM PDT 24 Jul 19 05:01:02 PM PDT 24 72963920 ps
T848 /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2774164420 Jul 19 05:00:08 PM PDT 24 Jul 19 05:00:26 PM PDT 24 1738733817 ps
T849 /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3084584559 Jul 19 05:01:36 PM PDT 24 Jul 19 05:02:28 PM PDT 24 2540500882 ps
T850 /workspace/coverage/default/45.lc_ctrl_jtag_access.1544717097 Jul 19 05:03:34 PM PDT 24 Jul 19 05:03:38 PM PDT 24 491587005 ps
T851 /workspace/coverage/default/25.lc_ctrl_state_post_trans.192158828 Jul 19 05:02:07 PM PDT 24 Jul 19 05:02:15 PM PDT 24 256324421 ps
T852 /workspace/coverage/default/35.lc_ctrl_state_post_trans.4013922058 Jul 19 05:02:44 PM PDT 24 Jul 19 05:02:57 PM PDT 24 62468906 ps
T853 /workspace/coverage/default/37.lc_ctrl_sec_token_digest.536457768 Jul 19 05:02:50 PM PDT 24 Jul 19 05:03:07 PM PDT 24 1183896573 ps
T854 /workspace/coverage/default/23.lc_ctrl_state_post_trans.2466623300 Jul 19 05:02:01 PM PDT 24 Jul 19 05:02:10 PM PDT 24 358836245 ps
T855 /workspace/coverage/default/36.lc_ctrl_state_post_trans.879583395 Jul 19 05:02:49 PM PDT 24 Jul 19 05:03:03 PM PDT 24 128607712 ps
T856 /workspace/coverage/default/34.lc_ctrl_prog_failure.2019838750 Jul 19 05:02:41 PM PDT 24 Jul 19 05:02:46 PM PDT 24 738419108 ps
T857 /workspace/coverage/default/8.lc_ctrl_alert_test.644778663 Jul 19 05:00:53 PM PDT 24 Jul 19 05:00:56 PM PDT 24 50682326 ps
T858 /workspace/coverage/default/2.lc_ctrl_jtag_priority.2732336927 Jul 19 05:00:28 PM PDT 24 Jul 19 05:00:48 PM PDT 24 1345504350 ps
T859 /workspace/coverage/default/40.lc_ctrl_stress_all.2771416940 Jul 19 05:03:07 PM PDT 24 Jul 19 05:04:58 PM PDT 24 11994635384 ps
T860 /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2900645147 Jul 19 05:03:26 PM PDT 24 Jul 19 05:03:28 PM PDT 24 15295867 ps
T861 /workspace/coverage/default/10.lc_ctrl_jtag_access.1437735697 Jul 19 05:01:08 PM PDT 24 Jul 19 05:01:18 PM PDT 24 1319108535 ps
T862 /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3671770238 Jul 19 05:00:43 PM PDT 24 Jul 19 05:00:57 PM PDT 24 937945991 ps
T863 /workspace/coverage/default/32.lc_ctrl_prog_failure.213301435 Jul 19 05:02:34 PM PDT 24 Jul 19 05:02:39 PM PDT 24 36791598 ps
T864 /workspace/coverage/default/48.lc_ctrl_state_failure.4010319794 Jul 19 05:03:30 PM PDT 24 Jul 19 05:03:56 PM PDT 24 264257550 ps
T118 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1584735405 Jul 19 04:33:14 PM PDT 24 Jul 19 04:33:24 PM PDT 24 35849477 ps
T110 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3379705503 Jul 19 04:33:21 PM PDT 24 Jul 19 04:33:32 PM PDT 24 389352710 ps
T114 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.345483043 Jul 19 04:33:10 PM PDT 24 Jul 19 04:33:19 PM PDT 24 58863996 ps
T123 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.66240033 Jul 19 04:33:15 PM PDT 24 Jul 19 04:33:25 PM PDT 24 38937007 ps
T119 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2308099736 Jul 19 04:33:12 PM PDT 24 Jul 19 04:33:22 PM PDT 24 17307346 ps
T120 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.439826919 Jul 19 04:33:17 PM PDT 24 Jul 19 04:33:27 PM PDT 24 25910188 ps
T192 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1304079340 Jul 19 04:33:25 PM PDT 24 Jul 19 04:33:35 PM PDT 24 19452774 ps
T142 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2127105617 Jul 19 04:33:05 PM PDT 24 Jul 19 04:33:11 PM PDT 24 147916593 ps
T207 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1520003575 Jul 19 04:33:17 PM PDT 24 Jul 19 04:33:27 PM PDT 24 38735785 ps
T134 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1096437483 Jul 19 04:33:11 PM PDT 24 Jul 19 04:33:20 PM PDT 24 32644027 ps
T156 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2899761680 Jul 19 04:33:12 PM PDT 24 Jul 19 04:33:21 PM PDT 24 187866619 ps
T111 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3774287176 Jul 19 04:33:18 PM PDT 24 Jul 19 04:33:30 PM PDT 24 376358254 ps
T112 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2281015332 Jul 19 04:33:18 PM PDT 24 Jul 19 04:33:29 PM PDT 24 57121822 ps
T121 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.4222111811 Jul 19 04:33:08 PM PDT 24 Jul 19 04:33:17 PM PDT 24 36374363 ps
T122 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3819268801 Jul 19 04:32:58 PM PDT 24 Jul 19 04:33:03 PM PDT 24 26995470 ps
T208 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.316023713 Jul 19 04:33:27 PM PDT 24 Jul 19 04:33:41 PM PDT 24 24485389 ps
T115 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3168567312 Jul 19 04:33:14 PM PDT 24 Jul 19 04:33:26 PM PDT 24 93540603 ps
T157 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3325931538 Jul 19 04:33:09 PM PDT 24 Jul 19 04:33:17 PM PDT 24 166799174 ps
T209 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2129021531 Jul 19 04:43:31 PM PDT 24 Jul 19 04:43:40 PM PDT 24 221134062 ps
T145 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3492726816 Jul 19 04:33:17 PM PDT 24 Jul 19 04:33:28 PM PDT 24 82049575 ps
T116 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2351861559 Jul 19 04:33:15 PM PDT 24 Jul 19 04:33:26 PM PDT 24 164897686 ps
T143 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1598569107 Jul 19 04:33:07 PM PDT 24 Jul 19 04:33:15 PM PDT 24 746787367 ps
T128 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1784322146 Jul 19 04:33:18 PM PDT 24 Jul 19 04:33:29 PM PDT 24 223139805 ps
T865 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2602288667 Jul 19 04:33:18 PM PDT 24 Jul 19 04:33:28 PM PDT 24 112425794 ps
T866 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1741191192 Jul 19 04:33:21 PM PDT 24 Jul 19 04:33:30 PM PDT 24 61120443 ps
T144 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2821334127 Jul 19 04:33:05 PM PDT 24 Jul 19 04:33:16 PM PDT 24 925902993 ps
T138 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.540778013 Jul 19 04:33:04 PM PDT 24 Jul 19 04:33:10 PM PDT 24 59811470 ps
T867 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1152567395 Jul 19 04:33:17 PM PDT 24 Jul 19 04:33:27 PM PDT 24 66740008 ps
T868 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.465962421 Jul 19 04:33:17 PM PDT 24 Jul 19 04:33:27 PM PDT 24 18405075 ps
T869 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.732754388 Jul 19 04:33:19 PM PDT 24 Jul 19 04:33:30 PM PDT 24 763579817 ps
T870 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.187478075 Jul 19 04:33:07 PM PDT 24 Jul 19 04:33:15 PM PDT 24 270535605 ps
T871 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1251010910 Jul 19 04:33:10 PM PDT 24 Jul 19 04:33:25 PM PDT 24 1410870840 ps
T210 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2051834088 Jul 19 04:33:12 PM PDT 24 Jul 19 04:33:22 PM PDT 24 15456066 ps
T872 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3593483987 Jul 19 04:33:06 PM PDT 24 Jul 19 04:33:21 PM PDT 24 28408487 ps
T211 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3125922118 Jul 19 04:33:00 PM PDT 24 Jul 19 04:33:05 PM PDT 24 18933994 ps
T193 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3240480981 Jul 19 04:33:15 PM PDT 24 Jul 19 04:33:25 PM PDT 24 12539983 ps
T873 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3638755557 Jul 19 04:33:11 PM PDT 24 Jul 19 04:33:46 PM PDT 24 4693406629 ps
T874 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2759980253 Jul 19 04:33:07 PM PDT 24 Jul 19 04:33:14 PM PDT 24 51611810 ps
T875 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3276148217 Jul 19 04:33:13 PM PDT 24 Jul 19 04:33:23 PM PDT 24 25209969 ps
T876 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1441411101 Jul 19 04:33:21 PM PDT 24 Jul 19 04:33:33 PM PDT 24 235567890 ps
T877 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.211371879 Jul 19 04:33:14 PM PDT 24 Jul 19 04:33:24 PM PDT 24 98209322 ps
T878 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.954828046 Jul 19 04:33:16 PM PDT 24 Jul 19 04:33:28 PM PDT 24 110768029 ps
T879 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.511574433 Jul 19 04:33:10 PM PDT 24 Jul 19 04:33:20 PM PDT 24 49867613 ps
T880 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4104521283 Jul 19 04:33:00 PM PDT 24 Jul 19 04:33:07 PM PDT 24 96171531 ps
T158 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1934436467 Jul 19 04:33:11 PM PDT 24 Jul 19 04:33:20 PM PDT 24 28341623 ps
T881 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2688569612 Jul 19 04:33:11 PM PDT 24 Jul 19 04:33:30 PM PDT 24 1093911597 ps
T882 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1833554522 Jul 19 04:33:06 PM PDT 24 Jul 19 04:33:11 PM PDT 24 132531696 ps
T883 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.666794930 Jul 19 04:33:04 PM PDT 24 Jul 19 04:33:09 PM PDT 24 61894804 ps
T884 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.4252308298 Jul 19 04:33:20 PM PDT 24 Jul 19 04:33:31 PM PDT 24 64358368 ps
T117 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.890794152 Jul 19 04:33:08 PM PDT 24 Jul 19 04:33:18 PM PDT 24 992909412 ps
T885 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1314772889 Jul 19 04:33:05 PM PDT 24 Jul 19 04:33:22 PM PDT 24 1373375079 ps
T886 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2176788592 Jul 19 04:33:04 PM PDT 24 Jul 19 04:33:16 PM PDT 24 1669838016 ps
T131 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2192226896 Jul 19 04:33:22 PM PDT 24 Jul 19 04:33:35 PM PDT 24 436797947 ps
T159 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1168346297 Jul 19 04:33:28 PM PDT 24 Jul 19 04:33:38 PM PDT 24 22491311 ps
T887 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4106863786 Jul 19 04:33:22 PM PDT 24 Jul 19 04:33:31 PM PDT 24 16493587 ps
T888 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2803779142 Jul 19 04:33:11 PM PDT 24 Jul 19 04:33:21 PM PDT 24 87680404 ps
T889 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.146466869 Jul 19 04:33:15 PM PDT 24 Jul 19 04:33:26 PM PDT 24 23861075 ps
T124 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1307816751 Jul 19 04:33:11 PM PDT 24 Jul 19 04:33:21 PM PDT 24 203341296 ps
T890 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3389314119 Jul 19 04:33:12 PM PDT 24 Jul 19 04:33:22 PM PDT 24 179233117 ps
T891 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.978967399 Jul 19 04:33:19 PM PDT 24 Jul 19 04:33:30 PM PDT 24 167889136 ps
T892 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3419161890 Jul 19 04:33:22 PM PDT 24 Jul 19 04:33:32 PM PDT 24 28210028 ps
T893 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2582704511 Jul 19 04:33:04 PM PDT 24 Jul 19 04:33:11 PM PDT 24 133615326 ps
T160 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3360012749 Jul 19 04:33:14 PM PDT 24 Jul 19 04:33:23 PM PDT 24 101433599 ps
T894 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.558422935 Jul 19 04:33:14 PM PDT 24 Jul 19 04:33:28 PM PDT 24 820044861 ps
T895 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1671051264 Jul 19 04:33:11 PM PDT 24 Jul 19 04:33:22 PM PDT 24 446685942 ps
T896 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.103282965 Jul 19 04:32:58 PM PDT 24 Jul 19 04:33:03 PM PDT 24 88439846 ps
T897 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3190004477 Jul 19 04:33:06 PM PDT 24 Jul 19 04:33:39 PM PDT 24 1588700940 ps
T898 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.96641108 Jul 19 04:33:10 PM PDT 24 Jul 19 04:33:21 PM PDT 24 75900262 ps
T135 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1211899911 Jul 19 04:33:22 PM PDT 24 Jul 19 04:33:33 PM PDT 24 61246969 ps
T194 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1316831416 Jul 19 04:33:08 PM PDT 24 Jul 19 04:33:16 PM PDT 24 14885705 ps
T899 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3936143059 Jul 19 04:33:11 PM PDT 24 Jul 19 04:33:20 PM PDT 24 86183069 ps
T195 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2978463449 Jul 19 04:33:25 PM PDT 24 Jul 19 04:33:35 PM PDT 24 13661199 ps
T900 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1002366170 Jul 19 04:33:15 PM PDT 24 Jul 19 04:33:27 PM PDT 24 220800207 ps
T196 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3767707089 Jul 19 04:33:02 PM PDT 24 Jul 19 04:33:07 PM PDT 24 44371582 ps
T901 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2603103841 Jul 19 04:33:15 PM PDT 24 Jul 19 04:33:25 PM PDT 24 160250074 ps
T197 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1133898605 Jul 19 04:33:14 PM PDT 24 Jul 19 04:33:23 PM PDT 24 16144963 ps
T902 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3916471863 Jul 19 04:33:08 PM PDT 24 Jul 19 04:33:40 PM PDT 24 1168277410 ps
T903 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3361873021 Jul 19 04:33:09 PM PDT 24 Jul 19 04:33:19 PM PDT 24 188879395 ps
T136 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3492098237 Jul 19 04:33:15 PM PDT 24 Jul 19 04:33:26 PM PDT 24 105035102 ps
T904 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1871115578 Jul 19 04:33:08 PM PDT 24 Jul 19 04:33:33 PM PDT 24 1599608760 ps
T905 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.256512226 Jul 19 04:32:57 PM PDT 24 Jul 19 04:33:01 PM PDT 24 182989657 ps
T906 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2467237905 Jul 19 04:33:10 PM PDT 24 Jul 19 04:33:19 PM PDT 24 23233171 ps
T907 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.123973655 Jul 19 04:33:09 PM PDT 24 Jul 19 04:33:23 PM PDT 24 1382907565 ps
T908 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.40932960 Jul 19 04:32:57 PM PDT 24 Jul 19 04:33:00 PM PDT 24 22244271 ps
T909 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3631189567 Jul 19 04:33:18 PM PDT 24 Jul 19 04:33:29 PM PDT 24 50183829 ps
T910 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.50720305 Jul 19 04:33:17 PM PDT 24 Jul 19 04:33:27 PM PDT 24 12339675 ps
T911 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.435176475 Jul 19 04:33:23 PM PDT 24 Jul 19 04:33:34 PM PDT 24 84581590 ps
T912 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2132296112 Jul 19 04:33:09 PM PDT 24 Jul 19 04:33:22 PM PDT 24 518265387 ps
T913 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1754045692 Jul 19 04:33:10 PM PDT 24 Jul 19 04:33:22 PM PDT 24 123728120 ps
T198 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.297774189 Jul 19 04:33:05 PM PDT 24 Jul 19 04:33:10 PM PDT 24 47123062 ps
T199 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2278296805 Jul 19 04:33:11 PM PDT 24 Jul 19 04:33:20 PM PDT 24 41875371 ps
T914 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.742759168 Jul 19 04:33:04 PM PDT 24 Jul 19 04:33:10 PM PDT 24 32079526 ps
T915 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1410114276 Jul 19 04:33:08 PM PDT 24 Jul 19 04:33:15 PM PDT 24 33290662 ps
T916 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3137109408 Jul 19 04:33:09 PM PDT 24 Jul 19 04:33:17 PM PDT 24 54909429 ps
T200 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2915075861 Jul 19 04:33:08 PM PDT 24 Jul 19 04:33:15 PM PDT 24 21494402 ps
T126 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3670303540 Jul 19 04:33:13 PM PDT 24 Jul 19 04:33:24 PM PDT 24 47301053 ps
T917 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2151554462 Jul 19 04:33:08 PM PDT 24 Jul 19 04:33:16 PM PDT 24 18204963 ps
T918 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1062913217 Jul 19 04:33:12 PM PDT 24 Jul 19 04:33:25 PM PDT 24 882463652 ps
T919 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4015506937 Jul 19 04:33:07 PM PDT 24 Jul 19 04:33:14 PM PDT 24 57221624 ps
T920 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2098108413 Jul 19 04:33:20 PM PDT 24 Jul 19 04:33:30 PM PDT 24 37833745 ps
T921 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2996943486 Jul 19 04:33:09 PM PDT 24 Jul 19 04:33:28 PM PDT 24 4802760647 ps
T922 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3855763344 Jul 19 04:33:08 PM PDT 24 Jul 19 04:33:16 PM PDT 24 321265261 ps
T923 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1366394012 Jul 19 04:33:11 PM PDT 24 Jul 19 04:33:22 PM PDT 24 893487428 ps
T924 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3749201813 Jul 19 04:32:56 PM PDT 24 Jul 19 04:33:01 PM PDT 24 75625806 ps
T202 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1940584205 Jul 19 04:33:10 PM PDT 24 Jul 19 04:33:19 PM PDT 24 99812948 ps
T137 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3301002758 Jul 19 04:33:06 PM PDT 24 Jul 19 04:33:13 PM PDT 24 387298212 ps
T925 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2787617943 Jul 19 04:33:12 PM PDT 24 Jul 19 04:33:28 PM PDT 24 582488121 ps
T926 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1437272927 Jul 19 04:33:10 PM PDT 24 Jul 19 04:33:19 PM PDT 24 104841174 ps
T125 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3080219801 Jul 19 04:33:06 PM PDT 24 Jul 19 04:33:14 PM PDT 24 79001354 ps
T201 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3756987001 Jul 19 04:33:10 PM PDT 24 Jul 19 04:33:19 PM PDT 24 20972324 ps
T927 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.214768686 Jul 19 04:33:13 PM PDT 24 Jul 19 04:33:23 PM PDT 24 167068336 ps
T928 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3058006406 Jul 19 04:33:30 PM PDT 24 Jul 19 04:33:42 PM PDT 24 23894922 ps
T929 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.4200368001 Jul 19 04:33:28 PM PDT 24 Jul 19 04:33:37 PM PDT 24 46891323 ps
T930 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2828645546 Jul 19 04:33:13 PM PDT 24 Jul 19 04:33:23 PM PDT 24 260983130 ps
T206 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1104090517 Jul 19 04:33:07 PM PDT 24 Jul 19 04:33:14 PM PDT 24 51656968 ps
T931 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3247733571 Jul 19 04:33:12 PM PDT 24 Jul 19 04:33:21 PM PDT 24 298416615 ps
T932 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2345809689 Jul 19 04:32:59 PM PDT 24 Jul 19 04:33:04 PM PDT 24 88148986 ps
T933 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3413806168 Jul 19 04:33:16 PM PDT 24 Jul 19 04:33:30 PM PDT 24 449262390 ps
T934 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.478947890 Jul 19 04:33:08 PM PDT 24 Jul 19 04:33:27 PM PDT 24 517054068 ps
T935 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2552141846 Jul 19 04:33:30 PM PDT 24 Jul 19 04:33:43 PM PDT 24 399902551 ps
T936 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4001191523 Jul 19 04:33:15 PM PDT 24 Jul 19 04:33:26 PM PDT 24 93426317 ps
T937 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.210057772 Jul 19 04:33:08 PM PDT 24 Jul 19 04:33:15 PM PDT 24 45972925 ps
T938 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2107360582 Jul 19 04:33:30 PM PDT 24 Jul 19 04:33:42 PM PDT 24 52005188 ps
T939 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1762644312 Jul 19 04:33:13 PM PDT 24 Jul 19 04:33:23 PM PDT 24 220915256 ps
T940 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3313445775 Jul 19 04:33:11 PM PDT 24 Jul 19 04:33:20 PM PDT 24 20789763 ps
T941 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1410824275 Jul 19 04:33:07 PM PDT 24 Jul 19 04:33:14 PM PDT 24 257983470 ps
T140 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.31114634 Jul 19 04:33:25 PM PDT 24 Jul 19 04:33:36 PM PDT 24 40776877 ps
T139 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3541477780 Jul 19 04:33:18 PM PDT 24 Jul 19 04:33:29 PM PDT 24 112229472 ps
T129 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1710245129 Jul 19 04:33:08 PM PDT 24 Jul 19 04:33:17 PM PDT 24 164477751 ps
T942 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1160205941 Jul 19 04:33:10 PM PDT 24 Jul 19 04:33:18 PM PDT 24 192317543 ps
T943 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2925260997 Jul 19 04:33:16 PM PDT 24 Jul 19 04:33:27 PM PDT 24 118608247 ps
T944 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1825922029 Jul 19 04:33:19 PM PDT 24 Jul 19 04:33:29 PM PDT 24 231821646 ps
T945 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3828317475 Jul 19 04:33:15 PM PDT 24 Jul 19 04:33:26 PM PDT 24 40130571 ps
T946 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2195552284 Jul 19 04:33:04 PM PDT 24 Jul 19 04:33:09 PM PDT 24 20070247 ps
T141 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1617631177 Jul 19 04:33:10 PM PDT 24 Jul 19 04:33:21 PM PDT 24 438758862 ps
T947 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2927070834 Jul 19 04:33:21 PM PDT 24 Jul 19 04:33:31 PM PDT 24 90300286 ps
T203 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1624329002 Jul 19 04:33:10 PM PDT 24 Jul 19 04:33:18 PM PDT 24 14508823 ps
T948 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2985958557 Jul 19 04:33:11 PM PDT 24 Jul 19 04:33:20 PM PDT 24 97598391 ps
T949 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1590153726 Jul 19 04:33:15 PM PDT 24 Jul 19 04:33:25 PM PDT 24 74739256 ps
T950 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1684357677 Jul 19 04:33:01 PM PDT 24 Jul 19 04:33:06 PM PDT 24 119782726 ps
T951 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1132000353 Jul 19 04:33:28 PM PDT 24 Jul 19 04:33:38 PM PDT 24 25251745 ps
T952 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1839656428 Jul 19 04:33:13 PM PDT 24 Jul 19 04:33:26 PM PDT 24 1396856131 ps
T953 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1043358115 Jul 19 04:33:16 PM PDT 24 Jul 19 04:33:30 PM PDT 24 2834982427 ps
T954 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.669381542 Jul 19 04:33:12 PM PDT 24 Jul 19 04:33:21 PM PDT 24 219583705 ps
T955 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2426975629 Jul 19 04:33:11 PM PDT 24 Jul 19 04:33:21 PM PDT 24 81846491 ps
T956 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2464805325 Jul 19 04:33:13 PM PDT 24 Jul 19 04:33:23 PM PDT 24 19243607 ps
T957 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3376366926 Jul 19 04:33:08 PM PDT 24 Jul 19 04:33:15 PM PDT 24 53775465 ps
T958 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3859102673 Jul 19 04:33:09 PM PDT 24 Jul 19 04:33:18 PM PDT 24 80834529 ps
T132 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1019502449 Jul 19 04:33:22 PM PDT 24 Jul 19 04:33:33 PM PDT 24 580029051 ps
T959 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3191878422 Jul 19 04:33:07 PM PDT 24 Jul 19 04:33:14 PM PDT 24 74366088 ps
T960 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2628450774 Jul 19 04:33:06 PM PDT 24 Jul 19 04:33:17 PM PDT 24 3617358469 ps
T961 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.207857761 Jul 19 04:33:08 PM PDT 24 Jul 19 04:33:17 PM PDT 24 419843472 ps
T962 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.381524736 Jul 19 04:33:29 PM PDT 24 Jul 19 04:33:38 PM PDT 24 43718162 ps
T963 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.471227968 Jul 19 04:33:13 PM PDT 24 Jul 19 04:33:24 PM PDT 24 234676329 ps
T964 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1149718815 Jul 19 04:33:09 PM PDT 24 Jul 19 04:33:20 PM PDT 24 301065012 ps
T965 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1403140387 Jul 19 04:33:11 PM PDT 24 Jul 19 04:33:21 PM PDT 24 16476685 ps
T966 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2992360892 Jul 19 04:33:12 PM PDT 24 Jul 19 04:33:22 PM PDT 24 32235040 ps
T967 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2505236218 Jul 19 04:32:59 PM PDT 24 Jul 19 04:33:04 PM PDT 24 57263049 ps
T968 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3020006909 Jul 19 04:33:09 PM PDT 24 Jul 19 04:33:19 PM PDT 24 101411603 ps
T205 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.388758653 Jul 19 04:33:06 PM PDT 24 Jul 19 04:33:12 PM PDT 24 13687739 ps
T969 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.195623415 Jul 19 04:33:21 PM PDT 24 Jul 19 04:33:30 PM PDT 24 51095138 ps
T970 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.258438347 Jul 19 04:33:08 PM PDT 24 Jul 19 04:33:15 PM PDT 24 27472994 ps
T971 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1327194145 Jul 19 04:33:57 PM PDT 24 Jul 19 04:34:35 PM PDT 24 3031255315 ps
T972 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2899054057 Jul 19 04:33:05 PM PDT 24 Jul 19 04:33:11 PM PDT 24 81600840 ps
T973 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.4221265825 Jul 19 04:33:13 PM PDT 24 Jul 19 04:33:23 PM PDT 24 253236259 ps
T127 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1836990557 Jul 19 04:33:28 PM PDT 24 Jul 19 04:33:39 PM PDT 24 89943422 ps
T974 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1248991191 Jul 19 04:33:22 PM PDT 24 Jul 19 04:33:32 PM PDT 24 71741272 ps
T975 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3592765173 Jul 19 04:33:06 PM PDT 24 Jul 19 04:33:12 PM PDT 24 54243277 ps
T976 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2264853941 Jul 19 04:33:08 PM PDT 24 Jul 19 04:33:15 PM PDT 24 197019361 ps
T977 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3377892936 Jul 19 04:33:11 PM PDT 24 Jul 19 04:33:20 PM PDT 24 17723899 ps
T978 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3504513339 Jul 19 04:33:14 PM PDT 24 Jul 19 04:33:27 PM PDT 24 1339348664 ps
T204 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2131143501 Jul 19 04:33:05 PM PDT 24 Jul 19 04:33:11 PM PDT 24 264037943 ps
T979 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2698872439 Jul 19 04:33:14 PM PDT 24 Jul 19 04:33:27 PM PDT 24 567012615 ps
T980 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3965667000 Jul 19 04:33:15 PM PDT 24 Jul 19 04:33:27 PM PDT 24 166300538 ps
T981 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3193251374 Jul 19 04:33:07 PM PDT 24 Jul 19 04:33:15 PM PDT 24 79730796 ps
T982 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1405661189 Jul 19 04:33:07 PM PDT 24 Jul 19 04:33:15 PM PDT 24 62369242 ps
T983 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1828303855 Jul 19 04:33:08 PM PDT 24 Jul 19 04:33:16 PM PDT 24 201122719 ps
T984 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1945310245 Jul 19 04:33:20 PM PDT 24 Jul 19 04:33:30 PM PDT 24 211490152 ps
T985 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1321747880 Jul 19 04:32:50 PM PDT 24 Jul 19 04:32:55 PM PDT 24 170298124 ps
T986 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2509804862 Jul 19 04:33:04 PM PDT 24 Jul 19 04:33:09 PM PDT 24 179464388 ps
T130 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3515864216 Jul 19 04:33:28 PM PDT 24 Jul 19 04:33:40 PM PDT 24 108606178 ps
T987 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3902363319 Jul 19 04:33:28 PM PDT 24 Jul 19 04:33:38 PM PDT 24 16696422 ps
T988 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3993676661 Jul 19 04:33:04 PM PDT 24 Jul 19 04:33:09 PM PDT 24 44742088 ps
T989 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2750732974 Jul 19 04:32:58 PM PDT 24 Jul 19 04:33:03 PM PDT 24 117082109 ps
T133 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.338656669 Jul 19 04:33:19 PM PDT 24 Jul 19 04:33:30 PM PDT 24 1248954552 ps

Test location /workspace/coverage/default/0.lc_ctrl_errors.1826709465
Short name T2
Test name
Test status
Simulation time 1624447483 ps
CPU time 16.7 seconds
Started Jul 19 05:00:16 PM PDT 24
Finished Jul 19 05:00:35 PM PDT 24
Peak memory 217796 kb
Host smart-76b87bdb-300d-45b9-93a6-028a657a10ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826709465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1826709465
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2306293643
Short name T5
Test name
Test status
Simulation time 18529502026 ps
CPU time 15.31 seconds
Started Jul 19 05:00:51 PM PDT 24
Finished Jul 19 05:01:08 PM PDT 24
Peak memory 217208 kb
Host smart-e38e5bd3-e428-44b0-ba52-4a73ad82eb48
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306293643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2306293643
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.190469871
Short name T43
Test name
Test status
Simulation time 408640023 ps
CPU time 14.89 seconds
Started Jul 19 05:02:42 PM PDT 24
Finished Jul 19 05:02:59 PM PDT 24
Peak memory 217856 kb
Host smart-eee91088-4410-44cd-9add-0274d9c307fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190469871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.190469871
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.2227916327
Short name T93
Test name
Test status
Simulation time 2750966683 ps
CPU time 11.43 seconds
Started Jul 19 05:00:44 PM PDT 24
Finished Jul 19 05:00:57 PM PDT 24
Peak memory 225664 kb
Host smart-b2413005-63cd-4b26-a00e-734eacd68694
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227916327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.2227916327
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.3678112299
Short name T71
Test name
Test status
Simulation time 7887871371 ps
CPU time 135 seconds
Started Jul 19 05:02:51 PM PDT 24
Finished Jul 19 05:05:10 PM PDT 24
Peak memory 283112 kb
Host smart-6d18a4d3-ee81-4179-9649-0e6296b4ce0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678112299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.3678112299
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.583849411
Short name T109
Test name
Test status
Simulation time 244486080651 ps
CPU time 485.01 seconds
Started Jul 19 05:00:21 PM PDT 24
Finished Jul 19 05:08:27 PM PDT 24
Peak memory 267076 kb
Host smart-f1741ea9-5072-47c9-9602-e6d370579001
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=583849411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.583849411
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2305414036
Short name T24
Test name
Test status
Simulation time 45039611 ps
CPU time 0.81 seconds
Started Jul 19 05:01:52 PM PDT 24
Finished Jul 19 05:01:54 PM PDT 24
Peak memory 208584 kb
Host smart-62b38dca-abf2-4314-b415-3237e01e254d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305414036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2305414036
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2460415866
Short name T59
Test name
Test status
Simulation time 428915869 ps
CPU time 41.31 seconds
Started Jul 19 05:00:28 PM PDT 24
Finished Jul 19 05:01:14 PM PDT 24
Peak memory 282092 kb
Host smart-f97dd56f-ef19-47fa-a0fa-c0aff75886fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460415866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2460415866
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.2231006701
Short name T106
Test name
Test status
Simulation time 54160747120 ps
CPU time 440.72 seconds
Started Jul 19 05:00:27 PM PDT 24
Finished Jul 19 05:07:52 PM PDT 24
Peak memory 299624 kb
Host smart-836ed646-6205-4919-adbe-fe7ff53ee8c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2231006701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.2231006701
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2939276587
Short name T17
Test name
Test status
Simulation time 833218669 ps
CPU time 16.75 seconds
Started Jul 19 05:01:17 PM PDT 24
Finished Jul 19 05:01:36 PM PDT 24
Peak memory 225660 kb
Host smart-1e91ce7c-3931-4c44-9cde-77be772bcd85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939276587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2939276587
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3168567312
Short name T115
Test name
Test status
Simulation time 93540603 ps
CPU time 2.73 seconds
Started Jul 19 04:33:14 PM PDT 24
Finished Jul 19 04:33:26 PM PDT 24
Peak memory 222428 kb
Host smart-6a874d5f-2a5b-43dc-9d4f-70483aa1a559
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168567312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3168567312
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2821334127
Short name T144
Test name
Test status
Simulation time 925902993 ps
CPU time 6.1 seconds
Started Jul 19 04:33:05 PM PDT 24
Finished Jul 19 04:33:16 PM PDT 24
Peak memory 218888 kb
Host smart-87e9eac3-48d4-4667-8aa8-cf58f0938d68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282133
4127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2821334127
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.4202446442
Short name T146
Test name
Test status
Simulation time 57952783965 ps
CPU time 646.54 seconds
Started Jul 19 05:03:14 PM PDT 24
Finished Jul 19 05:14:03 PM PDT 24
Peak memory 496412 kb
Host smart-3e2dae0b-def5-40b0-87de-0713c4660da3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4202446442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.4202446442
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.790184866
Short name T34
Test name
Test status
Simulation time 516431691 ps
CPU time 6.79 seconds
Started Jul 19 05:01:35 PM PDT 24
Finished Jul 19 05:01:43 PM PDT 24
Peak memory 216952 kb
Host smart-9ae0a259-a749-40cc-8d77-3c26406a595b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790184866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.790184866
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1304079340
Short name T192
Test name
Test status
Simulation time 19452774 ps
CPU time 0.86 seconds
Started Jul 19 04:33:25 PM PDT 24
Finished Jul 19 04:33:35 PM PDT 24
Peak memory 209524 kb
Host smart-bb56a3a0-396d-442d-9472-f91b9e0d62b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304079340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1304079340
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1670980920
Short name T3
Test name
Test status
Simulation time 93908213 ps
CPU time 1.06 seconds
Started Jul 19 05:03:40 PM PDT 24
Finished Jul 19 05:03:41 PM PDT 24
Peak memory 208424 kb
Host smart-ae9c175b-9655-4271-a82c-1dbd5b91ed69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670980920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1670980920
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.270271249
Short name T96
Test name
Test status
Simulation time 25826616859 ps
CPU time 153.33 seconds
Started Jul 19 05:01:50 PM PDT 24
Finished Jul 19 05:04:24 PM PDT 24
Peak memory 267740 kb
Host smart-bb9d40d4-d6b5-4c98-b779-3f25b83ceaa3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=270271249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.270271249
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.4222111811
Short name T121
Test name
Test status
Simulation time 36374363 ps
CPU time 2.14 seconds
Started Jul 19 04:33:08 PM PDT 24
Finished Jul 19 04:33:17 PM PDT 24
Peak memory 218980 kb
Host smart-9d668cbf-a6ee-4204-a48a-110ae310288b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222111811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.4222111811
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2192226896
Short name T131
Test name
Test status
Simulation time 436797947 ps
CPU time 3.96 seconds
Started Jul 19 04:33:22 PM PDT 24
Finished Jul 19 04:33:35 PM PDT 24
Peak memory 217824 kb
Host smart-37bb3baa-df5d-4130-ad00-7fb74784fd5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192226896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2192226896
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1249128016
Short name T27
Test name
Test status
Simulation time 1221253263 ps
CPU time 9.7 seconds
Started Jul 19 05:02:10 PM PDT 24
Finished Jul 19 05:02:21 PM PDT 24
Peak memory 217648 kb
Host smart-b1570eeb-1df1-4e0a-b3ba-c116ff203db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249128016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1249128016
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2915075861
Short name T200
Test name
Test status
Simulation time 21494402 ps
CPU time 1.14 seconds
Started Jul 19 04:33:08 PM PDT 24
Finished Jul 19 04:33:15 PM PDT 24
Peak memory 209576 kb
Host smart-f0365786-8d44-4687-9444-b8a98f2a83e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915075861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2915075861
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3515864216
Short name T130
Test name
Test status
Simulation time 108606178 ps
CPU time 3.94 seconds
Started Jul 19 04:33:28 PM PDT 24
Finished Jul 19 04:33:40 PM PDT 24
Peak memory 217700 kb
Host smart-d0aa95c0-4d47-47f0-ba07-0819a59c6851
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515864216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3515864216
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.338656669
Short name T133
Test name
Test status
Simulation time 1248954552 ps
CPU time 2.64 seconds
Started Jul 19 04:33:19 PM PDT 24
Finished Jul 19 04:33:30 PM PDT 24
Peak memory 222668 kb
Host smart-23f68aa1-cd58-4e72-a67b-082f96b2fdd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338656669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_
err.338656669
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1414541773
Short name T56
Test name
Test status
Simulation time 746273842 ps
CPU time 11.1 seconds
Started Jul 19 05:01:25 PM PDT 24
Finished Jul 19 05:01:38 PM PDT 24
Peak memory 217888 kb
Host smart-71cbb2de-5900-46f3-aa09-ccda59ca08ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414541773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1414541773
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.688242197
Short name T107
Test name
Test status
Simulation time 59776821081 ps
CPU time 1765.98 seconds
Started Jul 19 05:01:17 PM PDT 24
Finished Jul 19 05:30:44 PM PDT 24
Peak memory 512844 kb
Host smart-1bfb79de-694d-4d53-88fa-3d0da9269c6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=688242197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.688242197
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3492098237
Short name T136
Test name
Test status
Simulation time 105035102 ps
CPU time 2.68 seconds
Started Jul 19 04:33:15 PM PDT 24
Finished Jul 19 04:33:26 PM PDT 24
Peak memory 222480 kb
Host smart-4bc77eb5-be79-4d4d-8705-0a038ffeb374
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492098237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.3492098237
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3495513124
Short name T1
Test name
Test status
Simulation time 132214928 ps
CPU time 3.1 seconds
Started Jul 19 05:01:17 PM PDT 24
Finished Jul 19 05:01:22 PM PDT 24
Peak memory 217808 kb
Host smart-688d49c4-8924-48ca-b6dd-b6cf1e8df8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495513124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3495513124
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3749684220
Short name T216
Test name
Test status
Simulation time 31234704 ps
CPU time 0.91 seconds
Started Jul 19 05:00:08 PM PDT 24
Finished Jul 19 05:00:12 PM PDT 24
Peak memory 208288 kb
Host smart-a4273847-face-4ecd-aeca-4f532e106fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749684220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3749684220
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.4214745729
Short name T410
Test name
Test status
Simulation time 638073923 ps
CPU time 8.3 seconds
Started Jul 19 05:01:26 PM PDT 24
Finished Jul 19 05:01:36 PM PDT 24
Peak memory 225196 kb
Host smart-db73ee25-6ca8-446b-bec7-2540d3640cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214745729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.4214745729
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3919888940
Short name T218
Test name
Test status
Simulation time 108417301 ps
CPU time 0.83 seconds
Started Jul 19 05:00:22 PM PDT 24
Finished Jul 19 05:00:24 PM PDT 24
Peak memory 208516 kb
Host smart-3c8cbd31-6bee-4181-87aa-584fa50c7df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919888940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3919888940
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3859136141
Short name T213
Test name
Test status
Simulation time 18894323 ps
CPU time 0.93 seconds
Started Jul 19 05:00:27 PM PDT 24
Finished Jul 19 05:00:31 PM PDT 24
Peak memory 208264 kb
Host smart-1124ff60-39dd-4351-915a-0fbb1d52271c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859136141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3859136141
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3467509069
Short name T217
Test name
Test status
Simulation time 11323986 ps
CPU time 0.98 seconds
Started Jul 19 05:00:53 PM PDT 24
Finished Jul 19 05:00:56 PM PDT 24
Peak memory 208356 kb
Host smart-8c56215e-23a3-42f9-8fd7-a53feb9e5584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467509069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3467509069
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2930782107
Short name T166
Test name
Test status
Simulation time 9496037368 ps
CPU time 47.11 seconds
Started Jul 19 05:00:10 PM PDT 24
Finished Jul 19 05:01:00 PM PDT 24
Peak memory 273964 kb
Host smart-098e76c4-91c2-49f1-895c-df37760b282a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930782107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.2930782107
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.751943106
Short name T12
Test name
Test status
Simulation time 272934637 ps
CPU time 3.03 seconds
Started Jul 19 05:03:30 PM PDT 24
Finished Jul 19 05:03:35 PM PDT 24
Peak memory 217816 kb
Host smart-057aa298-c77f-4ccc-9d36-0cfb1c7c1949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751943106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.751943106
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.890794152
Short name T117
Test name
Test status
Simulation time 992909412 ps
CPU time 3.94 seconds
Started Jul 19 04:33:08 PM PDT 24
Finished Jul 19 04:33:18 PM PDT 24
Peak memory 217888 kb
Host smart-3ca3bcc4-c1b8-4cfa-8111-89e50513fe08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890794152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e
rr.890794152
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.31114634
Short name T140
Test name
Test status
Simulation time 40776877 ps
CPU time 1.81 seconds
Started Jul 19 04:33:25 PM PDT 24
Finished Jul 19 04:33:36 PM PDT 24
Peak memory 221888 kb
Host smart-1ea5ea98-f839-41e9-ad5e-11478780959a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31114634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_e
rr.31114634
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1836990557
Short name T127
Test name
Test status
Simulation time 89943422 ps
CPU time 2.62 seconds
Started Jul 19 04:33:28 PM PDT 24
Finished Jul 19 04:33:39 PM PDT 24
Peak memory 217800 kb
Host smart-c649c39c-025e-41ea-bc52-1c650073a62d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836990557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1836990557
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3080219801
Short name T125
Test name
Test status
Simulation time 79001354 ps
CPU time 3.38 seconds
Started Jul 19 04:33:06 PM PDT 24
Finished Jul 19 04:33:14 PM PDT 24
Peak memory 217724 kb
Host smart-da1fa1f4-ce29-4197-bce2-d5449dd8f087
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080219801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3080219801
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2444098933
Short name T55
Test name
Test status
Simulation time 1646156223 ps
CPU time 13.66 seconds
Started Jul 19 05:01:43 PM PDT 24
Finished Jul 19 05:02:00 PM PDT 24
Peak memory 217860 kb
Host smart-d5327fdc-3fa1-455d-a32e-0dab6b9ba19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444098933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2444098933
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3622388846
Short name T39
Test name
Test status
Simulation time 1058279634 ps
CPU time 8.59 seconds
Started Jul 19 05:00:07 PM PDT 24
Finished Jul 19 05:00:18 PM PDT 24
Peak memory 225532 kb
Host smart-b8a3c846-2ec2-4245-a4bb-ec5c98145c67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622388846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3622388846
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3855763344
Short name T922
Test name
Test status
Simulation time 321265261 ps
CPU time 1.94 seconds
Started Jul 19 04:33:08 PM PDT 24
Finished Jul 19 04:33:16 PM PDT 24
Peak memory 208856 kb
Host smart-ae558b3e-11d4-4702-80e5-9f96be728b64
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855763344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3855763344
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3592765173
Short name T975
Test name
Test status
Simulation time 54243277 ps
CPU time 0.89 seconds
Started Jul 19 04:33:06 PM PDT 24
Finished Jul 19 04:33:12 PM PDT 24
Peak memory 210252 kb
Host smart-6d86bc40-6e0e-4854-a9c8-d7e331d97c05
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592765173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3592765173
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.742759168
Short name T914
Test name
Test status
Simulation time 32079526 ps
CPU time 1.64 seconds
Started Jul 19 04:33:04 PM PDT 24
Finished Jul 19 04:33:10 PM PDT 24
Peak memory 219584 kb
Host smart-75ad93a7-0c7a-4d5d-98a8-0d9f8fedf861
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742759168 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.742759168
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1104090517
Short name T206
Test name
Test status
Simulation time 51656968 ps
CPU time 1.05 seconds
Started Jul 19 04:33:07 PM PDT 24
Finished Jul 19 04:33:14 PM PDT 24
Peak memory 209616 kb
Host smart-310092c0-132b-43ec-b841-55abd6df7985
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104090517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.1104090517
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2345809689
Short name T932
Test name
Test status
Simulation time 88148986 ps
CPU time 1.29 seconds
Started Jul 19 04:32:59 PM PDT 24
Finished Jul 19 04:33:04 PM PDT 24
Peak memory 208232 kb
Host smart-9be29f75-3658-40f0-bd0a-128947bf4e51
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345809689 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2345809689
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1871115578
Short name T904
Test name
Test status
Simulation time 1599608760 ps
CPU time 18.57 seconds
Started Jul 19 04:33:08 PM PDT 24
Finished Jul 19 04:33:33 PM PDT 24
Peak memory 209600 kb
Host smart-ce34695c-6111-47e4-907f-2e2adc1119e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871115578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1871115578
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3638755557
Short name T873
Test name
Test status
Simulation time 4693406629 ps
CPU time 26.03 seconds
Started Jul 19 04:33:11 PM PDT 24
Finished Jul 19 04:33:46 PM PDT 24
Peak memory 208880 kb
Host smart-860518d1-3cae-403b-ab50-026ab3cacd4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638755557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.3638755557
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2127105617
Short name T142
Test name
Test status
Simulation time 147916593 ps
CPU time 2.43 seconds
Started Jul 19 04:33:05 PM PDT 24
Finished Jul 19 04:33:11 PM PDT 24
Peak memory 210952 kb
Host smart-744ba658-c38b-4030-a0f8-3df4c9002c20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127105617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2127105617
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1160205941
Short name T942
Test name
Test status
Simulation time 192317543 ps
CPU time 1.4 seconds
Started Jul 19 04:33:10 PM PDT 24
Finished Jul 19 04:33:18 PM PDT 24
Peak memory 217804 kb
Host smart-e5b0692e-29fc-4df2-a520-cf755b65596c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116020
5941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1160205941
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2750732974
Short name T989
Test name
Test status
Simulation time 117082109 ps
CPU time 3.25 seconds
Started Jul 19 04:32:58 PM PDT 24
Finished Jul 19 04:33:03 PM PDT 24
Peak memory 209484 kb
Host smart-1ea22797-e6bf-4283-bc15-797b0d3ed9a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750732974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2750732974
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3125922118
Short name T211
Test name
Test status
Simulation time 18933994 ps
CPU time 1.35 seconds
Started Jul 19 04:33:00 PM PDT 24
Finished Jul 19 04:33:05 PM PDT 24
Peak memory 209480 kb
Host smart-afd4a2d0-1b92-4097-a7cb-22262763961e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125922118 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3125922118
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3749201813
Short name T924
Test name
Test status
Simulation time 75625806 ps
CPU time 1.78 seconds
Started Jul 19 04:32:56 PM PDT 24
Finished Jul 19 04:33:01 PM PDT 24
Peak memory 209776 kb
Host smart-54dcd0fe-e564-463d-87d0-d4d8a7279923
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749201813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3749201813
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.540778013
Short name T138
Test name
Test status
Simulation time 59811470 ps
CPU time 2.25 seconds
Started Jul 19 04:33:04 PM PDT 24
Finished Jul 19 04:33:10 PM PDT 24
Peak memory 217772 kb
Host smart-924a0ded-d963-48d9-b8bc-d662215d8bcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540778013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.540778013
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1307816751
Short name T124
Test name
Test status
Simulation time 203341296 ps
CPU time 1.58 seconds
Started Jul 19 04:33:11 PM PDT 24
Finished Jul 19 04:33:21 PM PDT 24
Peak memory 222008 kb
Host smart-66a299fd-52fe-4375-9d75-17d8604b6473
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307816751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1307816751
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3767707089
Short name T196
Test name
Test status
Simulation time 44371582 ps
CPU time 1.29 seconds
Started Jul 19 04:33:02 PM PDT 24
Finished Jul 19 04:33:07 PM PDT 24
Peak memory 209080 kb
Host smart-de7cac59-9308-416e-99a7-72c6f486dec4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767707089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3767707089
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2509804862
Short name T986
Test name
Test status
Simulation time 179464388 ps
CPU time 1.24 seconds
Started Jul 19 04:33:04 PM PDT 24
Finished Jul 19 04:33:09 PM PDT 24
Peak memory 208512 kb
Host smart-39464503-a3f1-4c26-b334-296b6d5c8cf1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509804862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2509804862
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.297774189
Short name T198
Test name
Test status
Simulation time 47123062 ps
CPU time 0.97 seconds
Started Jul 19 04:33:05 PM PDT 24
Finished Jul 19 04:33:10 PM PDT 24
Peak memory 210684 kb
Host smart-4b262d65-498c-42fc-ab8a-dbe2d9d7e4e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297774189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.297774189
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.103282965
Short name T896
Test name
Test status
Simulation time 88439846 ps
CPU time 1.28 seconds
Started Jul 19 04:32:58 PM PDT 24
Finished Jul 19 04:33:03 PM PDT 24
Peak memory 222868 kb
Host smart-ebd26770-7f93-4671-be1e-3d4a8cd955bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103282965 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.103282965
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.388758653
Short name T205
Test name
Test status
Simulation time 13687739 ps
CPU time 1.05 seconds
Started Jul 19 04:33:06 PM PDT 24
Finished Jul 19 04:33:12 PM PDT 24
Peak memory 209504 kb
Host smart-7c7caadc-108c-4e7e-af26-a45363bbfc1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388758653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.388758653
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1684357677
Short name T950
Test name
Test status
Simulation time 119782726 ps
CPU time 0.96 seconds
Started Jul 19 04:33:01 PM PDT 24
Finished Jul 19 04:33:06 PM PDT 24
Peak memory 208056 kb
Host smart-905fcabe-dafc-4849-aca1-0bbefcec8127
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684357677 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1684357677
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2132296112
Short name T912
Test name
Test status
Simulation time 518265387 ps
CPU time 5.83 seconds
Started Jul 19 04:33:09 PM PDT 24
Finished Jul 19 04:33:22 PM PDT 24
Peak memory 209340 kb
Host smart-b123b201-19c6-449e-b8b2-efc5f1f4deac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132296112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2132296112
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1327194145
Short name T971
Test name
Test status
Simulation time 3031255315 ps
CPU time 33.05 seconds
Started Jul 19 04:33:57 PM PDT 24
Finished Jul 19 04:34:35 PM PDT 24
Peak memory 209632 kb
Host smart-bd6c45ad-b706-4b42-9e55-d98c8d023764
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327194145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1327194145
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2107360582
Short name T938
Test name
Test status
Simulation time 52005188 ps
CPU time 1.22 seconds
Started Jul 19 04:33:30 PM PDT 24
Finished Jul 19 04:33:42 PM PDT 24
Peak memory 211000 kb
Host smart-37dd09f6-5c50-41d6-b939-ec8db83ea705
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107360582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2107360582
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3191878422
Short name T959
Test name
Test status
Simulation time 74366088 ps
CPU time 1.39 seconds
Started Jul 19 04:33:07 PM PDT 24
Finished Jul 19 04:33:14 PM PDT 24
Peak memory 209452 kb
Host smart-416cf28a-8414-4d66-b6d6-cd540ac9b074
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191878422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3191878422
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1321747880
Short name T985
Test name
Test status
Simulation time 170298124 ps
CPU time 0.97 seconds
Started Jul 19 04:32:50 PM PDT 24
Finished Jul 19 04:32:55 PM PDT 24
Peak memory 209648 kb
Host smart-1d6e150f-86ab-4b2b-bf47-eea372f19a42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321747880 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1321747880
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2129021531
Short name T209
Test name
Test status
Simulation time 221134062 ps
CPU time 1.18 seconds
Started Jul 19 04:43:31 PM PDT 24
Finished Jul 19 04:43:40 PM PDT 24
Peak memory 217860 kb
Host smart-161d9415-b7da-4c5f-83e7-da66bc78f2bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129021531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2129021531
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1132000353
Short name T951
Test name
Test status
Simulation time 25251745 ps
CPU time 1.53 seconds
Started Jul 19 04:33:28 PM PDT 24
Finished Jul 19 04:33:38 PM PDT 24
Peak memory 221816 kb
Host smart-8d0b16cb-0e81-4412-8274-21601d3aac34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132000353 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1132000353
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3240480981
Short name T193
Test name
Test status
Simulation time 12539983 ps
CPU time 0.89 seconds
Started Jul 19 04:33:15 PM PDT 24
Finished Jul 19 04:33:25 PM PDT 24
Peak memory 209448 kb
Host smart-47628663-1e7c-48ed-9e15-4fa3630288e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240480981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3240480981
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.316023713
Short name T208
Test name
Test status
Simulation time 24485389 ps
CPU time 1.28 seconds
Started Jul 19 04:33:27 PM PDT 24
Finished Jul 19 04:33:41 PM PDT 24
Peak memory 209584 kb
Host smart-b2d4e834-5a03-4d9c-966c-07449ab517c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316023713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.316023713
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3631189567
Short name T909
Test name
Test status
Simulation time 50183829 ps
CPU time 1.74 seconds
Started Jul 19 04:33:18 PM PDT 24
Finished Jul 19 04:33:29 PM PDT 24
Peak memory 217676 kb
Host smart-4f0ecac7-8293-453b-823f-a887871ab89b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631189567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3631189567
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1617631177
Short name T141
Test name
Test status
Simulation time 438758862 ps
CPU time 3.11 seconds
Started Jul 19 04:33:10 PM PDT 24
Finished Jul 19 04:33:21 PM PDT 24
Peak memory 222544 kb
Host smart-c31b74ed-317c-4368-b4d7-6f53f0ddeb98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617631177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1617631177
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1168346297
Short name T159
Test name
Test status
Simulation time 22491311 ps
CPU time 1.28 seconds
Started Jul 19 04:33:28 PM PDT 24
Finished Jul 19 04:33:38 PM PDT 24
Peak memory 217764 kb
Host smart-99e0517b-32d8-4ad8-a8f5-51758eb70d88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168346297 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1168346297
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.381524736
Short name T962
Test name
Test status
Simulation time 43718162 ps
CPU time 0.97 seconds
Started Jul 19 04:33:29 PM PDT 24
Finished Jul 19 04:33:38 PM PDT 24
Peak memory 209488 kb
Host smart-f914509f-c427-4c6c-a818-2a90beea7b47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381524736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.381524736
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2899761680
Short name T156
Test name
Test status
Simulation time 187866619 ps
CPU time 1.09 seconds
Started Jul 19 04:33:12 PM PDT 24
Finished Jul 19 04:33:21 PM PDT 24
Peak memory 209520 kb
Host smart-ea3188b2-7acd-4225-8200-07e0d921bafa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899761680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.2899761680
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1784322146
Short name T128
Test name
Test status
Simulation time 223139805 ps
CPU time 2.78 seconds
Started Jul 19 04:33:18 PM PDT 24
Finished Jul 19 04:33:29 PM PDT 24
Peak memory 217744 kb
Host smart-a66bc5d1-00ca-4b08-9777-cb56f7de75d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784322146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1784322146
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1096437483
Short name T134
Test name
Test status
Simulation time 32644027 ps
CPU time 1.26 seconds
Started Jul 19 04:33:11 PM PDT 24
Finished Jul 19 04:33:20 PM PDT 24
Peak memory 217916 kb
Host smart-28a11b02-1183-40fa-845f-fbb51bc0c8f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096437483 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1096437483
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3902363319
Short name T987
Test name
Test status
Simulation time 16696422 ps
CPU time 1.08 seconds
Started Jul 19 04:33:28 PM PDT 24
Finished Jul 19 04:33:38 PM PDT 24
Peak memory 209216 kb
Host smart-ea52a5d6-dbca-4dc7-81a1-7871850c0f68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902363319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3902363319
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1590153726
Short name T949
Test name
Test status
Simulation time 74739256 ps
CPU time 1.4 seconds
Started Jul 19 04:33:15 PM PDT 24
Finished Jul 19 04:33:25 PM PDT 24
Peak memory 211428 kb
Host smart-08279b2c-3ba1-4534-941f-5e25b6aaef78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590153726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1590153726
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3774287176
Short name T111
Test name
Test status
Simulation time 376358254 ps
CPU time 3.06 seconds
Started Jul 19 04:33:18 PM PDT 24
Finished Jul 19 04:33:30 PM PDT 24
Peak memory 219048 kb
Host smart-f19cc490-99e4-4624-bea8-27c08d934a78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774287176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3774287176
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.4252308298
Short name T884
Test name
Test status
Simulation time 64358368 ps
CPU time 2.42 seconds
Started Jul 19 04:33:20 PM PDT 24
Finished Jul 19 04:33:31 PM PDT 24
Peak memory 219988 kb
Host smart-81c2f342-ff3d-4e07-9375-a3a62b945bbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252308298 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.4252308298
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1945310245
Short name T984
Test name
Test status
Simulation time 211490152 ps
CPU time 0.86 seconds
Started Jul 19 04:33:20 PM PDT 24
Finished Jul 19 04:33:30 PM PDT 24
Peak memory 209504 kb
Host smart-5f232304-d177-4146-9719-3f781b400a62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945310245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1945310245
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3247733571
Short name T931
Test name
Test status
Simulation time 298416615 ps
CPU time 1.37 seconds
Started Jul 19 04:33:12 PM PDT 24
Finished Jul 19 04:33:21 PM PDT 24
Peak memory 209536 kb
Host smart-a074c8b3-ae9a-4458-8d36-07d4c3f4042f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247733571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3247733571
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1002366170
Short name T900
Test name
Test status
Simulation time 220800207 ps
CPU time 2.68 seconds
Started Jul 19 04:33:15 PM PDT 24
Finished Jul 19 04:33:27 PM PDT 24
Peak memory 217716 kb
Host smart-52dcb653-c2bd-4e54-beaa-ae116a9b6be7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002366170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1002366170
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.345483043
Short name T114
Test name
Test status
Simulation time 58863996 ps
CPU time 1.02 seconds
Started Jul 19 04:33:10 PM PDT 24
Finished Jul 19 04:33:19 PM PDT 24
Peak memory 217864 kb
Host smart-7147446a-eeaa-4708-9ac1-fbe3546045b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345483043 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.345483043
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.50720305
Short name T910
Test name
Test status
Simulation time 12339675 ps
CPU time 0.82 seconds
Started Jul 19 04:33:17 PM PDT 24
Finished Jul 19 04:33:27 PM PDT 24
Peak memory 208900 kb
Host smart-e4cf163b-7ed8-4ac0-94cc-df9d7a36eaaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50720305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.50720305
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2992360892
Short name T966
Test name
Test status
Simulation time 32235040 ps
CPU time 1.13 seconds
Started Jul 19 04:33:12 PM PDT 24
Finished Jul 19 04:33:22 PM PDT 24
Peak memory 209544 kb
Host smart-e32eb866-0a49-44a3-8070-5498b7768ecd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992360892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2992360892
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4001191523
Short name T936
Test name
Test status
Simulation time 93426317 ps
CPU time 2.77 seconds
Started Jul 19 04:33:15 PM PDT 24
Finished Jul 19 04:33:26 PM PDT 24
Peak memory 218268 kb
Host smart-53cd4e3e-f772-4d8d-824a-7d0450a2a105
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001191523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.4001191523
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.4200368001
Short name T929
Test name
Test status
Simulation time 46891323 ps
CPU time 1.24 seconds
Started Jul 19 04:33:28 PM PDT 24
Finished Jul 19 04:33:37 PM PDT 24
Peak memory 217972 kb
Host smart-5de70abf-8362-47ac-bb2e-dbe05d54eead
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200368001 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.4200368001
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.511574433
Short name T879
Test name
Test status
Simulation time 49867613 ps
CPU time 0.82 seconds
Started Jul 19 04:33:10 PM PDT 24
Finished Jul 19 04:33:20 PM PDT 24
Peak memory 209440 kb
Host smart-8d6ae447-4a5a-4f06-893a-35e782a6ce19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511574433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.511574433
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2098108413
Short name T920
Test name
Test status
Simulation time 37833745 ps
CPU time 1.76 seconds
Started Jul 19 04:33:20 PM PDT 24
Finished Jul 19 04:33:30 PM PDT 24
Peak memory 209508 kb
Host smart-e7e4f971-cfb0-4b16-9f63-ed60d61f0ddc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098108413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2098108413
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2925260997
Short name T943
Test name
Test status
Simulation time 118608247 ps
CPU time 2.27 seconds
Started Jul 19 04:33:16 PM PDT 24
Finished Jul 19 04:33:27 PM PDT 24
Peak memory 217720 kb
Host smart-e148cc03-b781-490b-910c-85b5f4934a19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925260997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2925260997
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4106863786
Short name T887
Test name
Test status
Simulation time 16493587 ps
CPU time 1 seconds
Started Jul 19 04:33:22 PM PDT 24
Finished Jul 19 04:33:31 PM PDT 24
Peak memory 219744 kb
Host smart-f7487720-816f-42e3-b732-b7b34c4fbe96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106863786 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.4106863786
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.439826919
Short name T120
Test name
Test status
Simulation time 25910188 ps
CPU time 1.34 seconds
Started Jul 19 04:33:17 PM PDT 24
Finished Jul 19 04:33:27 PM PDT 24
Peak memory 209528 kb
Host smart-d3083646-00e5-46a1-8869-522df19d1ae3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439826919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_same_csr_outstanding.439826919
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2552141846
Short name T935
Test name
Test status
Simulation time 399902551 ps
CPU time 4.15 seconds
Started Jul 19 04:33:30 PM PDT 24
Finished Jul 19 04:33:43 PM PDT 24
Peak memory 217784 kb
Host smart-d1da4104-e725-4a98-b024-7221bcd35b4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552141846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2552141846
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3419161890
Short name T892
Test name
Test status
Simulation time 28210028 ps
CPU time 1.26 seconds
Started Jul 19 04:33:22 PM PDT 24
Finished Jul 19 04:33:32 PM PDT 24
Peak memory 218600 kb
Host smart-f805892a-1b2a-4951-ab0b-c1357d66cad8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419161890 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3419161890
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2978463449
Short name T195
Test name
Test status
Simulation time 13661199 ps
CPU time 0.82 seconds
Started Jul 19 04:33:25 PM PDT 24
Finished Jul 19 04:33:35 PM PDT 24
Peak memory 209528 kb
Host smart-39822626-c0b7-41b8-90de-c14d9c194133
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978463449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2978463449
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3058006406
Short name T928
Test name
Test status
Simulation time 23894922 ps
CPU time 1.3 seconds
Started Jul 19 04:33:30 PM PDT 24
Finished Jul 19 04:33:42 PM PDT 24
Peak memory 209600 kb
Host smart-fb83ad74-9625-4582-8314-1397db642df7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058006406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3058006406
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2281015332
Short name T112
Test name
Test status
Simulation time 57121822 ps
CPU time 2.6 seconds
Started Jul 19 04:33:18 PM PDT 24
Finished Jul 19 04:33:29 PM PDT 24
Peak memory 217928 kb
Host smart-9074c020-6d21-4465-ad5b-5f9c3ea5de85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281015332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2281015332
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1211899911
Short name T135
Test name
Test status
Simulation time 61246969 ps
CPU time 2.52 seconds
Started Jul 19 04:33:22 PM PDT 24
Finished Jul 19 04:33:33 PM PDT 24
Peak memory 217716 kb
Host smart-34e03291-113c-4fdb-bb74-b026079ed770
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211899911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1211899911
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1741191192
Short name T866
Test name
Test status
Simulation time 61120443 ps
CPU time 0.98 seconds
Started Jul 19 04:33:21 PM PDT 24
Finished Jul 19 04:33:30 PM PDT 24
Peak memory 217748 kb
Host smart-2578e678-0290-469f-b7ed-615fe9d21860
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741191192 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1741191192
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1152567395
Short name T867
Test name
Test status
Simulation time 66740008 ps
CPU time 0.95 seconds
Started Jul 19 04:33:17 PM PDT 24
Finished Jul 19 04:33:27 PM PDT 24
Peak memory 209596 kb
Host smart-26ae6802-19a5-40ec-a9bd-a0ac1e0d09db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152567395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1152567395
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1520003575
Short name T207
Test name
Test status
Simulation time 38735785 ps
CPU time 1.42 seconds
Started Jul 19 04:33:17 PM PDT 24
Finished Jul 19 04:33:27 PM PDT 24
Peak memory 211636 kb
Host smart-f4cfc99f-ce3d-4bda-9f54-c19a4ec9a60e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520003575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1520003575
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.435176475
Short name T911
Test name
Test status
Simulation time 84581590 ps
CPU time 2.68 seconds
Started Jul 19 04:33:23 PM PDT 24
Finished Jul 19 04:33:34 PM PDT 24
Peak memory 217732 kb
Host smart-b920c13e-ddbd-4053-8090-38ea31ecf5e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435176475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.435176475
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1019502449
Short name T132
Test name
Test status
Simulation time 580029051 ps
CPU time 3 seconds
Started Jul 19 04:33:22 PM PDT 24
Finished Jul 19 04:33:33 PM PDT 24
Peak memory 217716 kb
Host smart-26a35e10-fca9-4b28-9b78-d3bf81fa5196
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019502449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1019502449
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2927070834
Short name T947
Test name
Test status
Simulation time 90300286 ps
CPU time 1.06 seconds
Started Jul 19 04:33:21 PM PDT 24
Finished Jul 19 04:33:31 PM PDT 24
Peak memory 219796 kb
Host smart-dc0d8efe-3d09-4177-b729-7afdfd0c33da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927070834 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2927070834
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.195623415
Short name T969
Test name
Test status
Simulation time 51095138 ps
CPU time 0.79 seconds
Started Jul 19 04:33:21 PM PDT 24
Finished Jul 19 04:33:30 PM PDT 24
Peak memory 208944 kb
Host smart-56dbb39e-6e3b-4b04-b81a-98f0a2d9ef76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195623415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.195623415
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1248991191
Short name T974
Test name
Test status
Simulation time 71741272 ps
CPU time 1.67 seconds
Started Jul 19 04:33:22 PM PDT 24
Finished Jul 19 04:33:32 PM PDT 24
Peak memory 209516 kb
Host smart-1ea72b58-6753-4e80-b9b2-32b0b134f4fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248991191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1248991191
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3379705503
Short name T110
Test name
Test status
Simulation time 389352710 ps
CPU time 2.14 seconds
Started Jul 19 04:33:21 PM PDT 24
Finished Jul 19 04:33:32 PM PDT 24
Peak memory 217836 kb
Host smart-6137ddeb-1b01-42cc-b96d-6f2baa2be941
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379705503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3379705503
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2351861559
Short name T116
Test name
Test status
Simulation time 164897686 ps
CPU time 2 seconds
Started Jul 19 04:33:15 PM PDT 24
Finished Jul 19 04:33:26 PM PDT 24
Peak memory 217728 kb
Host smart-42082cb5-b0ad-4481-ba77-85cc7fcf32e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351861559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2351861559
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2131143501
Short name T204
Test name
Test status
Simulation time 264037943 ps
CPU time 1.3 seconds
Started Jul 19 04:33:05 PM PDT 24
Finished Jul 19 04:33:11 PM PDT 24
Peak memory 209484 kb
Host smart-5b7a25a8-6fee-4c9a-99d7-ce09ea8ce66a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131143501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2131143501
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3593483987
Short name T872
Test name
Test status
Simulation time 28408487 ps
CPU time 1.78 seconds
Started Jul 19 04:33:06 PM PDT 24
Finished Jul 19 04:33:21 PM PDT 24
Peak memory 209588 kb
Host smart-9bb460f4-5796-47fc-9d71-01b7260de6ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593483987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3593483987
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2195552284
Short name T946
Test name
Test status
Simulation time 20070247 ps
CPU time 1 seconds
Started Jul 19 04:33:04 PM PDT 24
Finished Jul 19 04:33:09 PM PDT 24
Peak memory 210056 kb
Host smart-11b65fff-311c-40a3-a719-aa180482f7f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195552284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2195552284
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2467237905
Short name T906
Test name
Test status
Simulation time 23233171 ps
CPU time 1.42 seconds
Started Jul 19 04:33:10 PM PDT 24
Finished Jul 19 04:33:19 PM PDT 24
Peak memory 217780 kb
Host smart-bb34b750-ab64-4c66-bd0b-c82ab4720943
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467237905 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2467237905
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.40932960
Short name T908
Test name
Test status
Simulation time 22244271 ps
CPU time 0.93 seconds
Started Jul 19 04:32:57 PM PDT 24
Finished Jul 19 04:33:00 PM PDT 24
Peak memory 209580 kb
Host smart-4d57ea5e-1dc2-4699-bf30-6301fcc614e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40932960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.40932960
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3936143059
Short name T899
Test name
Test status
Simulation time 86183069 ps
CPU time 0.97 seconds
Started Jul 19 04:33:11 PM PDT 24
Finished Jul 19 04:33:20 PM PDT 24
Peak memory 209348 kb
Host smart-6466802b-37d4-46c5-8e39-c4ef3ea60f9c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936143059 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3936143059
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1149718815
Short name T964
Test name
Test status
Simulation time 301065012 ps
CPU time 3.87 seconds
Started Jul 19 04:33:09 PM PDT 24
Finished Jul 19 04:33:20 PM PDT 24
Peak memory 209332 kb
Host smart-ea099029-8251-49dc-9b28-cc5e91d98b10
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149718815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1149718815
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3916471863
Short name T902
Test name
Test status
Simulation time 1168277410 ps
CPU time 25.62 seconds
Started Jul 19 04:33:08 PM PDT 24
Finished Jul 19 04:33:40 PM PDT 24
Peak memory 208768 kb
Host smart-1b5698f7-734e-4185-a4be-1154e1ba46a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916471863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3916471863
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.207857761
Short name T961
Test name
Test status
Simulation time 419843472 ps
CPU time 3.35 seconds
Started Jul 19 04:33:08 PM PDT 24
Finished Jul 19 04:33:17 PM PDT 24
Peak memory 211192 kb
Host smart-a00f243a-7b7f-4fe4-951b-e7eb5201f52b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207857761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.207857761
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2582704511
Short name T893
Test name
Test status
Simulation time 133615326 ps
CPU time 2.24 seconds
Started Jul 19 04:33:04 PM PDT 24
Finished Jul 19 04:33:11 PM PDT 24
Peak memory 218792 kb
Host smart-8b36603a-ef4c-49d3-ab0b-c0abb3a491f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258270
4511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2582704511
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1833554522
Short name T882
Test name
Test status
Simulation time 132531696 ps
CPU time 1.06 seconds
Started Jul 19 04:33:06 PM PDT 24
Finished Jul 19 04:33:11 PM PDT 24
Peak memory 209400 kb
Host smart-bc199955-5e8e-4a2d-adeb-8f8e0910b581
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833554522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1833554522
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3313445775
Short name T940
Test name
Test status
Simulation time 20789763 ps
CPU time 1.2 seconds
Started Jul 19 04:33:11 PM PDT 24
Finished Jul 19 04:33:20 PM PDT 24
Peak memory 217728 kb
Host smart-49b52714-29f7-4192-8c71-83782fdc2bc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313445775 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3313445775
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.258438347
Short name T970
Test name
Test status
Simulation time 27472994 ps
CPU time 1.12 seconds
Started Jul 19 04:33:08 PM PDT 24
Finished Jul 19 04:33:15 PM PDT 24
Peak memory 209504 kb
Host smart-ca87aef3-edc2-4e70-91f6-ac72ec2d758c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258438347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.258438347
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3819268801
Short name T122
Test name
Test status
Simulation time 26995470 ps
CPU time 1.83 seconds
Started Jul 19 04:32:58 PM PDT 24
Finished Jul 19 04:33:03 PM PDT 24
Peak memory 218800 kb
Host smart-643dcf0f-16b2-432b-8fcc-bd6eefcc0e66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819268801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3819268801
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.211371879
Short name T877
Test name
Test status
Simulation time 98209322 ps
CPU time 0.96 seconds
Started Jul 19 04:33:14 PM PDT 24
Finished Jul 19 04:33:24 PM PDT 24
Peak memory 209460 kb
Host smart-eeac06a7-342e-4826-8e0a-f7470b392bda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211371879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.211371879
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1940584205
Short name T202
Test name
Test status
Simulation time 99812948 ps
CPU time 1.36 seconds
Started Jul 19 04:33:10 PM PDT 24
Finished Jul 19 04:33:19 PM PDT 24
Peak memory 209440 kb
Host smart-f3b3916c-2bcf-45e4-97ff-824a4f664e10
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940584205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1940584205
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2278296805
Short name T199
Test name
Test status
Simulation time 41875371 ps
CPU time 1.06 seconds
Started Jul 19 04:33:11 PM PDT 24
Finished Jul 19 04:33:20 PM PDT 24
Peak memory 210060 kb
Host smart-9a6eba5d-1cf4-43a3-aacc-5c7b87285b40
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278296805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2278296805
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2759980253
Short name T874
Test name
Test status
Simulation time 51611810 ps
CPU time 0.9 seconds
Started Jul 19 04:33:07 PM PDT 24
Finished Jul 19 04:33:14 PM PDT 24
Peak memory 217700 kb
Host smart-d26e4fe7-66b0-4423-8627-037ea0a028a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759980253 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2759980253
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1624329002
Short name T203
Test name
Test status
Simulation time 14508823 ps
CPU time 0.85 seconds
Started Jul 19 04:33:10 PM PDT 24
Finished Jul 19 04:33:18 PM PDT 24
Peak memory 209456 kb
Host smart-7d86f7d6-c23b-44b8-84c2-4ca7aa0c3e3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624329002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1624329002
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.256512226
Short name T905
Test name
Test status
Simulation time 182989657 ps
CPU time 1.11 seconds
Started Jul 19 04:32:57 PM PDT 24
Finished Jul 19 04:33:01 PM PDT 24
Peak memory 208192 kb
Host smart-b9b01276-cdba-4e2c-b5b1-fde6ddd5cf43
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256512226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.256512226
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2176788592
Short name T886
Test name
Test status
Simulation time 1669838016 ps
CPU time 7.91 seconds
Started Jul 19 04:33:04 PM PDT 24
Finished Jul 19 04:33:16 PM PDT 24
Peak memory 209428 kb
Host smart-6a18487d-79f9-451e-a4df-41f65500f6cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176788592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2176788592
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3190004477
Short name T897
Test name
Test status
Simulation time 1588700940 ps
CPU time 27.99 seconds
Started Jul 19 04:33:06 PM PDT 24
Finished Jul 19 04:33:39 PM PDT 24
Peak memory 209328 kb
Host smart-730d6038-b9b5-44ae-b466-5f62c37731de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190004477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3190004477
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.210057772
Short name T937
Test name
Test status
Simulation time 45972925 ps
CPU time 1.26 seconds
Started Jul 19 04:33:08 PM PDT 24
Finished Jul 19 04:33:15 PM PDT 24
Peak memory 210996 kb
Host smart-c1fc9c01-f997-49fd-a7fe-f632fff8fd8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210057772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.210057772
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.558422935
Short name T894
Test name
Test status
Simulation time 820044861 ps
CPU time 5.14 seconds
Started Jul 19 04:33:14 PM PDT 24
Finished Jul 19 04:33:28 PM PDT 24
Peak memory 218864 kb
Host smart-f96b31f8-d1e2-4ce4-ae2e-0ef286a822f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558422
935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.558422935
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2505236218
Short name T967
Test name
Test status
Simulation time 57263049 ps
CPU time 1.25 seconds
Started Jul 19 04:32:59 PM PDT 24
Finished Jul 19 04:33:04 PM PDT 24
Peak memory 209604 kb
Host smart-e3905d2e-b443-498c-9e67-c679c14a8dd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505236218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2505236218
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.214768686
Short name T927
Test name
Test status
Simulation time 167068336 ps
CPU time 1.88 seconds
Started Jul 19 04:33:13 PM PDT 24
Finished Jul 19 04:33:23 PM PDT 24
Peak memory 217716 kb
Host smart-76b8f30e-4400-4040-99e7-68bae88df50f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214768686 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.214768686
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3993676661
Short name T988
Test name
Test status
Simulation time 44742088 ps
CPU time 1.42 seconds
Started Jul 19 04:33:04 PM PDT 24
Finished Jul 19 04:33:09 PM PDT 24
Peak memory 211712 kb
Host smart-6f560629-e257-4b7f-a2da-7b4c7592b4ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993676661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3993676661
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4104521283
Short name T880
Test name
Test status
Simulation time 96171531 ps
CPU time 3.69 seconds
Started Jul 19 04:33:00 PM PDT 24
Finished Jul 19 04:33:07 PM PDT 24
Peak memory 217816 kb
Host smart-f2b637f6-5d61-4a64-8c36-7ed1c87fbf64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104521283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.4104521283
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3301002758
Short name T137
Test name
Test status
Simulation time 387298212 ps
CPU time 2.17 seconds
Started Jul 19 04:33:06 PM PDT 24
Finished Jul 19 04:33:13 PM PDT 24
Peak memory 217720 kb
Host smart-7b5df331-be65-40e6-9751-8c7eca04e8fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301002758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3301002758
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4015506937
Short name T919
Test name
Test status
Simulation time 57221624 ps
CPU time 1.09 seconds
Started Jul 19 04:33:07 PM PDT 24
Finished Jul 19 04:33:14 PM PDT 24
Peak memory 209452 kb
Host smart-277e0543-d802-4fc4-b92f-a8ea35141c60
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015506937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.4015506937
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2264853941
Short name T976
Test name
Test status
Simulation time 197019361 ps
CPU time 1.33 seconds
Started Jul 19 04:33:08 PM PDT 24
Finished Jul 19 04:33:15 PM PDT 24
Peak memory 209472 kb
Host smart-2a239f03-db4a-4c0f-83c0-ce0fa2be4bbf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264853941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2264853941
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3137109408
Short name T916
Test name
Test status
Simulation time 54909429 ps
CPU time 1.23 seconds
Started Jul 19 04:33:09 PM PDT 24
Finished Jul 19 04:33:17 PM PDT 24
Peak memory 218224 kb
Host smart-b2eb64a7-0575-4272-b0e4-358ec17c2156
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137109408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3137109408
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1762644312
Short name T939
Test name
Test status
Simulation time 220915256 ps
CPU time 1.81 seconds
Started Jul 19 04:33:13 PM PDT 24
Finished Jul 19 04:33:23 PM PDT 24
Peak memory 218868 kb
Host smart-56f5c928-b6f8-4ce3-b5ac-b4d1d7823dfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762644312 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1762644312
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2308099736
Short name T119
Test name
Test status
Simulation time 17307346 ps
CPU time 1.03 seconds
Started Jul 19 04:33:12 PM PDT 24
Finished Jul 19 04:33:22 PM PDT 24
Peak memory 209476 kb
Host smart-cc011fe4-3e41-433d-b365-9f4aa58109bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308099736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2308099736
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1437272927
Short name T926
Test name
Test status
Simulation time 104841174 ps
CPU time 0.97 seconds
Started Jul 19 04:33:10 PM PDT 24
Finished Jul 19 04:33:19 PM PDT 24
Peak memory 209400 kb
Host smart-4d97cf65-38fe-4ae7-9969-9762e057a85b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437272927 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1437272927
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2787617943
Short name T925
Test name
Test status
Simulation time 582488121 ps
CPU time 6.96 seconds
Started Jul 19 04:33:12 PM PDT 24
Finished Jul 19 04:33:28 PM PDT 24
Peak memory 209444 kb
Host smart-c7f3e4e4-81b8-40dd-92fb-f49d6b85ab85
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787617943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2787617943
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2688569612
Short name T881
Test name
Test status
Simulation time 1093911597 ps
CPU time 10.75 seconds
Started Jul 19 04:33:11 PM PDT 24
Finished Jul 19 04:33:30 PM PDT 24
Peak memory 209444 kb
Host smart-c78a8309-a19a-4dea-baf9-9b08b058bd52
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688569612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2688569612
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2628450774
Short name T960
Test name
Test status
Simulation time 3617358469 ps
CPU time 5.45 seconds
Started Jul 19 04:33:06 PM PDT 24
Finished Jul 19 04:33:17 PM PDT 24
Peak memory 211308 kb
Host smart-27362e62-2a01-40ee-8909-883303995a93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628450774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2628450774
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.187478075
Short name T870
Test name
Test status
Simulation time 270535605 ps
CPU time 2.5 seconds
Started Jul 19 04:33:07 PM PDT 24
Finished Jul 19 04:33:15 PM PDT 24
Peak memory 218180 kb
Host smart-eda92ad8-906f-4732-a9e1-1c721fad8831
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187478
075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.187478075
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2828645546
Short name T930
Test name
Test status
Simulation time 260983130 ps
CPU time 1.65 seconds
Started Jul 19 04:33:13 PM PDT 24
Finished Jul 19 04:33:23 PM PDT 24
Peak memory 209580 kb
Host smart-0d5a1c69-0edd-476d-9c3b-dc1993fc7b4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828645546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2828645546
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.146466869
Short name T889
Test name
Test status
Simulation time 23861075 ps
CPU time 1.63 seconds
Started Jul 19 04:33:15 PM PDT 24
Finished Jul 19 04:33:26 PM PDT 24
Peak memory 211676 kb
Host smart-e02e14ff-7540-42b4-b25c-b224d789f36b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146466869 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.146466869
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3325931538
Short name T157
Test name
Test status
Simulation time 166799174 ps
CPU time 1.82 seconds
Started Jul 19 04:33:09 PM PDT 24
Finished Jul 19 04:33:17 PM PDT 24
Peak memory 211448 kb
Host smart-2bbadf5f-b5ee-47bb-b5b4-060601f9085e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325931538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3325931538
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1410824275
Short name T941
Test name
Test status
Simulation time 257983470 ps
CPU time 2.68 seconds
Started Jul 19 04:33:07 PM PDT 24
Finished Jul 19 04:33:14 PM PDT 24
Peak memory 217740 kb
Host smart-2e92a2e3-7b9a-4580-8159-d8208cc7b5ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410824275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1410824275
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3670303540
Short name T126
Test name
Test status
Simulation time 47301053 ps
CPU time 2.3 seconds
Started Jul 19 04:33:13 PM PDT 24
Finished Jul 19 04:33:24 PM PDT 24
Peak memory 217728 kb
Host smart-48c1594c-c4e8-4789-89bb-2c9311ce4404
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670303540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.3670303540
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1410114276
Short name T915
Test name
Test status
Simulation time 33290662 ps
CPU time 1.39 seconds
Started Jul 19 04:33:08 PM PDT 24
Finished Jul 19 04:33:15 PM PDT 24
Peak memory 218976 kb
Host smart-fa49113b-ba88-4c57-ba57-e8682c8b4c1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410114276 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1410114276
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1316831416
Short name T194
Test name
Test status
Simulation time 14885705 ps
CPU time 1.04 seconds
Started Jul 19 04:33:08 PM PDT 24
Finished Jul 19 04:33:16 PM PDT 24
Peak memory 209420 kb
Host smart-cb2b7736-ae6d-4ef7-91bb-6afaf3adc7d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316831416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1316831416
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2985958557
Short name T948
Test name
Test status
Simulation time 97598391 ps
CPU time 1.72 seconds
Started Jul 19 04:33:11 PM PDT 24
Finished Jul 19 04:33:20 PM PDT 24
Peak memory 209432 kb
Host smart-b6ed29f1-047c-4d64-a002-afa33cba4743
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985958557 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2985958557
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1062913217
Short name T918
Test name
Test status
Simulation time 882463652 ps
CPU time 4.09 seconds
Started Jul 19 04:33:12 PM PDT 24
Finished Jul 19 04:33:25 PM PDT 24
Peak memory 209288 kb
Host smart-df05c7a8-7bb6-452c-8670-308660c9230c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062913217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1062913217
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1839656428
Short name T952
Test name
Test status
Simulation time 1396856131 ps
CPU time 4.42 seconds
Started Jul 19 04:33:13 PM PDT 24
Finished Jul 19 04:33:26 PM PDT 24
Peak memory 209360 kb
Host smart-51cdcb89-a220-45bc-9642-a1a9983240f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839656428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1839656428
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1828303855
Short name T983
Test name
Test status
Simulation time 201122719 ps
CPU time 1.31 seconds
Started Jul 19 04:33:08 PM PDT 24
Finished Jul 19 04:33:16 PM PDT 24
Peak memory 211176 kb
Host smart-8c3fe6a5-a59b-4406-a2dc-f231120e7379
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828303855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1828303855
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3361873021
Short name T903
Test name
Test status
Simulation time 188879395 ps
CPU time 3.07 seconds
Started Jul 19 04:33:09 PM PDT 24
Finished Jul 19 04:33:19 PM PDT 24
Peak memory 217372 kb
Host smart-cac5d0e3-0c3f-45d9-a4f1-78110c9e2865
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336187
3021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3361873021
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1825922029
Short name T944
Test name
Test status
Simulation time 231821646 ps
CPU time 1.71 seconds
Started Jul 19 04:33:19 PM PDT 24
Finished Jul 19 04:33:29 PM PDT 24
Peak memory 209500 kb
Host smart-4c826df3-7e2a-49e9-90e5-05754848d3da
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825922029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1825922029
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3376366926
Short name T957
Test name
Test status
Simulation time 53775465 ps
CPU time 1.12 seconds
Started Jul 19 04:33:08 PM PDT 24
Finished Jul 19 04:33:15 PM PDT 24
Peak memory 209536 kb
Host smart-fe36d6fb-6a00-402f-9d00-3a47a5ea8dfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376366926 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3376366926
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3276148217
Short name T875
Test name
Test status
Simulation time 25209969 ps
CPU time 1.19 seconds
Started Jul 19 04:33:13 PM PDT 24
Finished Jul 19 04:33:23 PM PDT 24
Peak memory 209544 kb
Host smart-642040dc-baf2-428a-ab09-b00b302f105c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276148217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3276148217
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2698872439
Short name T979
Test name
Test status
Simulation time 567012615 ps
CPU time 4.99 seconds
Started Jul 19 04:33:14 PM PDT 24
Finished Jul 19 04:33:27 PM PDT 24
Peak memory 217724 kb
Host smart-850bc46b-c4a0-4397-a263-f6028d8575d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698872439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2698872439
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1710245129
Short name T129
Test name
Test status
Simulation time 164477751 ps
CPU time 3.55 seconds
Started Jul 19 04:33:08 PM PDT 24
Finished Jul 19 04:33:17 PM PDT 24
Peak memory 217732 kb
Host smart-82395ec7-9d98-4675-b360-075e2d5f75ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710245129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1710245129
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2464805325
Short name T956
Test name
Test status
Simulation time 19243607 ps
CPU time 1.48 seconds
Started Jul 19 04:33:13 PM PDT 24
Finished Jul 19 04:33:23 PM PDT 24
Peak memory 219680 kb
Host smart-ad5f655b-4466-49b3-af53-c73a9aeab292
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464805325 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2464805325
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1133898605
Short name T197
Test name
Test status
Simulation time 16144963 ps
CPU time 1.04 seconds
Started Jul 19 04:33:14 PM PDT 24
Finished Jul 19 04:33:23 PM PDT 24
Peak memory 209512 kb
Host smart-308edee5-1212-4681-9a51-a2e5d0271c9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133898605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1133898605
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2602288667
Short name T865
Test name
Test status
Simulation time 112425794 ps
CPU time 0.95 seconds
Started Jul 19 04:33:18 PM PDT 24
Finished Jul 19 04:33:28 PM PDT 24
Peak memory 208116 kb
Host smart-d650462d-ce39-4e25-b7e6-4feac0cb71c7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602288667 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2602288667
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.478947890
Short name T934
Test name
Test status
Simulation time 517054068 ps
CPU time 12.44 seconds
Started Jul 19 04:33:08 PM PDT 24
Finished Jul 19 04:33:27 PM PDT 24
Peak memory 209396 kb
Host smart-32da42a0-c13c-4575-9c01-00c46b6ca393
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478947890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.478947890
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.123973655
Short name T907
Test name
Test status
Simulation time 1382907565 ps
CPU time 6.39 seconds
Started Jul 19 04:33:09 PM PDT 24
Finished Jul 19 04:33:23 PM PDT 24
Peak memory 209348 kb
Host smart-2be8f5f5-4b06-43e1-b541-b9c1a1c2f5da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123973655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.123973655
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1598569107
Short name T143
Test name
Test status
Simulation time 746787367 ps
CPU time 2.17 seconds
Started Jul 19 04:33:07 PM PDT 24
Finished Jul 19 04:33:15 PM PDT 24
Peak memory 211076 kb
Host smart-ed303e04-a2ed-4e7c-a792-3cb6b372c122
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598569107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1598569107
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3413806168
Short name T933
Test name
Test status
Simulation time 449262390 ps
CPU time 5.87 seconds
Started Jul 19 04:33:16 PM PDT 24
Finished Jul 19 04:33:30 PM PDT 24
Peak memory 221912 kb
Host smart-f8c7a17b-297a-488b-8c99-58a9bdde713f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341380
6168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3413806168
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1754045692
Short name T913
Test name
Test status
Simulation time 123728120 ps
CPU time 3.33 seconds
Started Jul 19 04:33:10 PM PDT 24
Finished Jul 19 04:33:22 PM PDT 24
Peak memory 209516 kb
Host smart-2f3e785b-4e51-42a0-9749-a9c61394fc53
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754045692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1754045692
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3193251374
Short name T981
Test name
Test status
Simulation time 79730796 ps
CPU time 1.32 seconds
Started Jul 19 04:33:07 PM PDT 24
Finished Jul 19 04:33:15 PM PDT 24
Peak memory 209540 kb
Host smart-fcbf517f-296b-4f2d-a9da-065d911aefc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193251374 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3193251374
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.666794930
Short name T883
Test name
Test status
Simulation time 61894804 ps
CPU time 1.15 seconds
Started Jul 19 04:33:04 PM PDT 24
Finished Jul 19 04:33:09 PM PDT 24
Peak memory 209340 kb
Host smart-88894b78-2248-4247-8d15-a2490f5b5a0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666794930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.666794930
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1405661189
Short name T982
Test name
Test status
Simulation time 62369242 ps
CPU time 2.73 seconds
Started Jul 19 04:33:07 PM PDT 24
Finished Jul 19 04:33:15 PM PDT 24
Peak memory 217736 kb
Host smart-69d47d82-07a8-47fa-8eb4-3f10b2630e71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405661189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1405661189
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.471227968
Short name T963
Test name
Test status
Simulation time 234676329 ps
CPU time 1.9 seconds
Started Jul 19 04:33:13 PM PDT 24
Finished Jul 19 04:33:24 PM PDT 24
Peak memory 213360 kb
Host smart-80e292cb-c529-4bbe-9ad2-aba02c4fa198
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471227968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.471227968
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3360012749
Short name T160
Test name
Test status
Simulation time 101433599 ps
CPU time 1.11 seconds
Started Jul 19 04:33:14 PM PDT 24
Finished Jul 19 04:33:23 PM PDT 24
Peak memory 218768 kb
Host smart-95637b41-23f0-4c6c-9798-9c6ac0f45982
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360012749 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3360012749
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.66240033
Short name T123
Test name
Test status
Simulation time 38937007 ps
CPU time 0.86 seconds
Started Jul 19 04:33:15 PM PDT 24
Finished Jul 19 04:33:25 PM PDT 24
Peak memory 209424 kb
Host smart-ed4344f4-c87f-4880-85f2-e6a06be89c94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66240033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.66240033
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2803779142
Short name T888
Test name
Test status
Simulation time 87680404 ps
CPU time 1.51 seconds
Started Jul 19 04:33:11 PM PDT 24
Finished Jul 19 04:33:21 PM PDT 24
Peak memory 209464 kb
Host smart-9508d7fd-c217-4ebb-aa78-5007350eb249
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803779142 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2803779142
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1251010910
Short name T871
Test name
Test status
Simulation time 1410870840 ps
CPU time 7.94 seconds
Started Jul 19 04:33:10 PM PDT 24
Finished Jul 19 04:33:25 PM PDT 24
Peak memory 208780 kb
Host smart-8c128f23-b132-40b7-b62a-4f64ed7e9564
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251010910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1251010910
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1314772889
Short name T885
Test name
Test status
Simulation time 1373375079 ps
CPU time 12.82 seconds
Started Jul 19 04:33:05 PM PDT 24
Finished Jul 19 04:33:22 PM PDT 24
Peak memory 208252 kb
Host smart-f3c4f83c-98cc-4a9d-8008-9e3463b98dc1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314772889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1314772889
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3965667000
Short name T980
Test name
Test status
Simulation time 166300538 ps
CPU time 3.62 seconds
Started Jul 19 04:33:15 PM PDT 24
Finished Jul 19 04:33:27 PM PDT 24
Peak memory 211236 kb
Host smart-b57a2078-1aa3-4241-aec4-c437614172be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965667000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3965667000
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3020006909
Short name T968
Test name
Test status
Simulation time 101411603 ps
CPU time 3.18 seconds
Started Jul 19 04:33:09 PM PDT 24
Finished Jul 19 04:33:19 PM PDT 24
Peak memory 218452 kb
Host smart-77aec740-db49-4205-bfd8-8f28a7bbf7a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302000
6909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3020006909
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.669381542
Short name T954
Test name
Test status
Simulation time 219583705 ps
CPU time 1.37 seconds
Started Jul 19 04:33:12 PM PDT 24
Finished Jul 19 04:33:21 PM PDT 24
Peak memory 209500 kb
Host smart-8dca4c5f-bd02-48ce-9281-06aa04828945
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669381542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.669381542
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2899054057
Short name T972
Test name
Test status
Simulation time 81600840 ps
CPU time 1.27 seconds
Started Jul 19 04:33:05 PM PDT 24
Finished Jul 19 04:33:11 PM PDT 24
Peak memory 209628 kb
Host smart-43e12be3-57e8-4250-8ab4-cea3ce16e269
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899054057 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2899054057
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3828317475
Short name T945
Test name
Test status
Simulation time 40130571 ps
CPU time 1.31 seconds
Started Jul 19 04:33:15 PM PDT 24
Finished Jul 19 04:33:26 PM PDT 24
Peak memory 209520 kb
Host smart-444c5f8d-c2b7-430d-820f-a81fb5eeaee7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828317475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3828317475
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3504513339
Short name T978
Test name
Test status
Simulation time 1339348664 ps
CPU time 3.41 seconds
Started Jul 19 04:33:14 PM PDT 24
Finished Jul 19 04:33:27 PM PDT 24
Peak memory 217720 kb
Host smart-cb39bca1-149d-4e22-9451-a865d689b202
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504513339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3504513339
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1403140387
Short name T965
Test name
Test status
Simulation time 16476685 ps
CPU time 1.31 seconds
Started Jul 19 04:33:11 PM PDT 24
Finished Jul 19 04:33:21 PM PDT 24
Peak memory 217932 kb
Host smart-155b381f-0c3e-48b5-9213-7699aa946f46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403140387 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1403140387
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3756987001
Short name T201
Test name
Test status
Simulation time 20972324 ps
CPU time 0.97 seconds
Started Jul 19 04:33:10 PM PDT 24
Finished Jul 19 04:33:19 PM PDT 24
Peak memory 209508 kb
Host smart-d5b8bb49-34ad-4764-b0e3-0455b9c0fa32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756987001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3756987001
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1441411101
Short name T876
Test name
Test status
Simulation time 235567890 ps
CPU time 3.21 seconds
Started Jul 19 04:33:21 PM PDT 24
Finished Jul 19 04:33:33 PM PDT 24
Peak memory 209452 kb
Host smart-41ffb683-d380-476f-9321-7db85608f260
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441411101 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1441411101
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.732754388
Short name T869
Test name
Test status
Simulation time 763579817 ps
CPU time 2.65 seconds
Started Jul 19 04:33:19 PM PDT 24
Finished Jul 19 04:33:30 PM PDT 24
Peak memory 208708 kb
Host smart-efc42fe7-dca7-4e20-85a7-6998fd0973f1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732754388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.732754388
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2996943486
Short name T921
Test name
Test status
Simulation time 4802760647 ps
CPU time 11.98 seconds
Started Jul 19 04:33:09 PM PDT 24
Finished Jul 19 04:33:28 PM PDT 24
Peak memory 209608 kb
Host smart-226d831e-8405-43e3-bc3e-068736d2c5c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996943486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2996943486
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3492726816
Short name T145
Test name
Test status
Simulation time 82049575 ps
CPU time 1.74 seconds
Started Jul 19 04:33:17 PM PDT 24
Finished Jul 19 04:33:28 PM PDT 24
Peak memory 210968 kb
Host smart-29d18762-1b4b-4266-8b2b-3b5f3c1d4388
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492726816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3492726816
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1366394012
Short name T923
Test name
Test status
Simulation time 893487428 ps
CPU time 2.91 seconds
Started Jul 19 04:33:11 PM PDT 24
Finished Jul 19 04:33:22 PM PDT 24
Peak memory 219380 kb
Host smart-aeeca696-6688-4d27-b504-75dffd77aea3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136639
4012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1366394012
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2603103841
Short name T901
Test name
Test status
Simulation time 160250074 ps
CPU time 1.13 seconds
Started Jul 19 04:33:15 PM PDT 24
Finished Jul 19 04:33:25 PM PDT 24
Peak memory 209664 kb
Host smart-8e434c36-263b-4209-bf24-0113f305e04e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603103841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2603103841
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2051834088
Short name T210
Test name
Test status
Simulation time 15456066 ps
CPU time 1.16 seconds
Started Jul 19 04:33:12 PM PDT 24
Finished Jul 19 04:33:22 PM PDT 24
Peak memory 209468 kb
Host smart-2e0fcdfa-9607-46d1-8b18-fec47205b24d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051834088 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2051834088
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1584735405
Short name T118
Test name
Test status
Simulation time 35849477 ps
CPU time 1.27 seconds
Started Jul 19 04:33:14 PM PDT 24
Finished Jul 19 04:33:24 PM PDT 24
Peak memory 209488 kb
Host smart-6c0edb15-db80-49b2-a334-e99fcf6d1207
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584735405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1584735405
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.954828046
Short name T878
Test name
Test status
Simulation time 110768029 ps
CPU time 3.25 seconds
Started Jul 19 04:33:16 PM PDT 24
Finished Jul 19 04:33:28 PM PDT 24
Peak memory 219956 kb
Host smart-16878ab0-042d-474a-bd9c-0391a43a7fa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954828046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.954828046
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3541477780
Short name T139
Test name
Test status
Simulation time 112229472 ps
CPU time 2.51 seconds
Started Jul 19 04:33:18 PM PDT 24
Finished Jul 19 04:33:29 PM PDT 24
Peak memory 217720 kb
Host smart-ee2fbe93-4b5f-482b-837a-ce9222891614
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541477780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3541477780
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1934436467
Short name T158
Test name
Test status
Simulation time 28341623 ps
CPU time 1.24 seconds
Started Jul 19 04:33:11 PM PDT 24
Finished Jul 19 04:33:20 PM PDT 24
Peak memory 217856 kb
Host smart-dc56040b-b63f-4a5c-b277-c78fabd0468f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934436467 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1934436467
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2151554462
Short name T917
Test name
Test status
Simulation time 18204963 ps
CPU time 0.9 seconds
Started Jul 19 04:33:08 PM PDT 24
Finished Jul 19 04:33:16 PM PDT 24
Peak memory 209164 kb
Host smart-90c2a492-b501-495a-84e9-a1b4ec55fb91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151554462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2151554462
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.465962421
Short name T868
Test name
Test status
Simulation time 18405075 ps
CPU time 1.17 seconds
Started Jul 19 04:33:17 PM PDT 24
Finished Jul 19 04:33:27 PM PDT 24
Peak memory 209440 kb
Host smart-0cfcb28d-52d3-4b2a-b15d-8bb3372c7654
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465962421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.465962421
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1671051264
Short name T895
Test name
Test status
Simulation time 446685942 ps
CPU time 3.09 seconds
Started Jul 19 04:33:11 PM PDT 24
Finished Jul 19 04:33:22 PM PDT 24
Peak memory 209332 kb
Host smart-283df11a-4e83-4281-90e7-2a198640ea08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671051264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1671051264
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1043358115
Short name T953
Test name
Test status
Simulation time 2834982427 ps
CPU time 5.37 seconds
Started Jul 19 04:33:16 PM PDT 24
Finished Jul 19 04:33:30 PM PDT 24
Peak memory 209584 kb
Host smart-81ab652e-79f8-4b4c-9881-a259d4ce1bf6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043358115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1043358115
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3389314119
Short name T890
Test name
Test status
Simulation time 179233117 ps
CPU time 1.23 seconds
Started Jul 19 04:33:12 PM PDT 24
Finished Jul 19 04:33:22 PM PDT 24
Peak memory 210916 kb
Host smart-b83c30af-d1f8-4dbc-91a2-0af488cbc483
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389314119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3389314119
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.96641108
Short name T898
Test name
Test status
Simulation time 75900262 ps
CPU time 2.51 seconds
Started Jul 19 04:33:10 PM PDT 24
Finished Jul 19 04:33:21 PM PDT 24
Peak memory 218420 kb
Host smart-7ff541fe-e2a4-4166-83a0-3c279174f9ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966411
08 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.96641108
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3859102673
Short name T958
Test name
Test status
Simulation time 80834529 ps
CPU time 2.17 seconds
Started Jul 19 04:33:09 PM PDT 24
Finished Jul 19 04:33:18 PM PDT 24
Peak memory 209436 kb
Host smart-0fdd65ee-911f-4a26-8c32-1262342509a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859102673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3859102673
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.4221265825
Short name T973
Test name
Test status
Simulation time 253236259 ps
CPU time 1.84 seconds
Started Jul 19 04:33:13 PM PDT 24
Finished Jul 19 04:33:23 PM PDT 24
Peak memory 209524 kb
Host smart-133a9b51-c741-43ec-be46-1db86f09c1ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221265825 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.4221265825
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3377892936
Short name T977
Test name
Test status
Simulation time 17723899 ps
CPU time 1.21 seconds
Started Jul 19 04:33:11 PM PDT 24
Finished Jul 19 04:33:20 PM PDT 24
Peak memory 209576 kb
Host smart-0bdc7cf4-bfb5-4913-959f-b98efa5835f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377892936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3377892936
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.978967399
Short name T891
Test name
Test status
Simulation time 167889136 ps
CPU time 2.59 seconds
Started Jul 19 04:33:19 PM PDT 24
Finished Jul 19 04:33:30 PM PDT 24
Peak memory 217876 kb
Host smart-40e1f692-563b-47ec-ad77-3485b3632c9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978967399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.978967399
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2426975629
Short name T955
Test name
Test status
Simulation time 81846491 ps
CPU time 1.88 seconds
Started Jul 19 04:33:11 PM PDT 24
Finished Jul 19 04:33:21 PM PDT 24
Peak memory 222004 kb
Host smart-b6c114f4-640f-4001-b6e9-94d057714c28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426975629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.2426975629
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.569852859
Short name T442
Test name
Test status
Simulation time 23502630 ps
CPU time 1.07 seconds
Started Jul 19 05:00:17 PM PDT 24
Finished Jul 19 05:00:21 PM PDT 24
Peak memory 208404 kb
Host smart-505bd04d-761a-4e31-98fd-d7d322ceea51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569852859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.569852859
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.4282847582
Short name T8
Test name
Test status
Simulation time 388520430 ps
CPU time 7.23 seconds
Started Jul 19 05:00:06 PM PDT 24
Finished Jul 19 05:00:15 PM PDT 24
Peak memory 217000 kb
Host smart-4b9b8af7-af40-48f0-8296-11affd04648d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282847582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.4282847582
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1949452130
Short name T19
Test name
Test status
Simulation time 5831579056 ps
CPU time 46.05 seconds
Started Jul 19 05:00:10 PM PDT 24
Finished Jul 19 05:00:59 PM PDT 24
Peak memory 219296 kb
Host smart-a26e79d8-8774-409c-9e31-4fee5e04bda2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949452130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1949452130
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.37798570
Short name T6
Test name
Test status
Simulation time 3060076300 ps
CPU time 4.29 seconds
Started Jul 19 05:00:16 PM PDT 24
Finished Jul 19 05:00:22 PM PDT 24
Peak memory 217200 kb
Host smart-249b0149-9893-4362-9634-b1c0b7dd0b8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37798570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.37798570
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3253935391
Short name T282
Test name
Test status
Simulation time 600918937 ps
CPU time 3.13 seconds
Started Jul 19 05:00:09 PM PDT 24
Finished Jul 19 05:00:15 PM PDT 24
Peak memory 221300 kb
Host smart-4df2897c-ed9d-4fca-9688-f440f6343f51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253935391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3253935391
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.4114640182
Short name T390
Test name
Test status
Simulation time 2549666440 ps
CPU time 16.14 seconds
Started Jul 19 05:00:07 PM PDT 24
Finished Jul 19 05:00:26 PM PDT 24
Peak memory 217188 kb
Host smart-325b1c05-f146-407a-b67d-937b6f426495
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114640182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.4114640182
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2911051144
Short name T348
Test name
Test status
Simulation time 119963791 ps
CPU time 3.05 seconds
Started Jul 19 05:00:08 PM PDT 24
Finished Jul 19 05:00:14 PM PDT 24
Peak memory 217148 kb
Host smart-9d8d0acf-4a60-48bf-ad1d-9c9350029058
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911051144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2911051144
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.3635715431
Short name T601
Test name
Test status
Simulation time 577039964 ps
CPU time 13.81 seconds
Started Jul 19 05:00:07 PM PDT 24
Finished Jul 19 05:00:23 PM PDT 24
Peak memory 249956 kb
Host smart-e3d6f465-8db0-459c-a54c-b457c824734c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635715431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.3635715431
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1829568408
Short name T687
Test name
Test status
Simulation time 86701807 ps
CPU time 4.24 seconds
Started Jul 19 05:00:10 PM PDT 24
Finished Jul 19 05:00:17 PM PDT 24
Peak memory 217772 kb
Host smart-5e6cc20c-c492-43d9-9ce4-c9fcfd839829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829568408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1829568408
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3188660809
Short name T212
Test name
Test status
Simulation time 5155679550 ps
CPU time 8.74 seconds
Started Jul 19 05:00:09 PM PDT 24
Finished Jul 19 05:00:21 PM PDT 24
Peak memory 217324 kb
Host smart-57e9f68c-bccb-4939-bf04-798fc75cb9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188660809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3188660809
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3355631884
Short name T99
Test name
Test status
Simulation time 1602992279 ps
CPU time 23.96 seconds
Started Jul 19 05:00:17 PM PDT 24
Finished Jul 19 05:00:44 PM PDT 24
Peak memory 281372 kb
Host smart-efc2faa7-b630-4047-8ece-d56eaf33df2c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355631884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3355631884
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.125878887
Short name T437
Test name
Test status
Simulation time 1769455760 ps
CPU time 10.84 seconds
Started Jul 19 05:00:06 PM PDT 24
Finished Jul 19 05:00:18 PM PDT 24
Peak memory 225504 kb
Host smart-57a649ff-7dae-40ce-b324-a1c110be2e10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125878887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.125878887
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2774164420
Short name T848
Test name
Test status
Simulation time 1738733817 ps
CPU time 14.69 seconds
Started Jul 19 05:00:08 PM PDT 24
Finished Jul 19 05:00:26 PM PDT 24
Peak memory 225488 kb
Host smart-9ad87db9-1f01-4372-8b58-65ceb8147fd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774164420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
774164420
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2711091942
Short name T698
Test name
Test status
Simulation time 4318616787 ps
CPU time 9.11 seconds
Started Jul 19 05:00:09 PM PDT 24
Finished Jul 19 05:00:21 PM PDT 24
Peak memory 225608 kb
Host smart-6a5d8367-63df-4ae2-a243-236b9103f48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711091942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2711091942
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1897333749
Short name T465
Test name
Test status
Simulation time 60244231 ps
CPU time 3.44 seconds
Started Jul 19 05:00:07 PM PDT 24
Finished Jul 19 05:00:13 PM PDT 24
Peak memory 217200 kb
Host smart-aefd88bd-0874-43d5-96c8-306552c025a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897333749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1897333749
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1475890319
Short name T708
Test name
Test status
Simulation time 221073717 ps
CPU time 26.13 seconds
Started Jul 19 05:00:08 PM PDT 24
Finished Jul 19 05:00:37 PM PDT 24
Peak memory 250532 kb
Host smart-e7356241-ce04-4e48-a1d2-4b5bc6a5d76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475890319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1475890319
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1014263939
Short name T398
Test name
Test status
Simulation time 248815315 ps
CPU time 9.47 seconds
Started Jul 19 05:00:08 PM PDT 24
Finished Jul 19 05:00:20 PM PDT 24
Peak memory 250508 kb
Host smart-45b2a06d-55aa-40e2-a830-487e38805569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014263939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1014263939
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2277386615
Short name T714
Test name
Test status
Simulation time 14740637899 ps
CPU time 55.96 seconds
Started Jul 19 05:00:08 PM PDT 24
Finished Jul 19 05:01:07 PM PDT 24
Peak memory 225668 kb
Host smart-974124b7-3e9d-46a5-b992-9e947d289682
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277386615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2277386615
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2629201613
Short name T811
Test name
Test status
Simulation time 12141926 ps
CPU time 1.09 seconds
Started Jul 19 05:00:16 PM PDT 24
Finished Jul 19 05:00:19 PM PDT 24
Peak memory 211356 kb
Host smart-e5842eeb-acff-415c-9f60-fbe92cfabc3a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629201613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2629201613
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.203749090
Short name T717
Test name
Test status
Simulation time 63347675 ps
CPU time 1.11 seconds
Started Jul 19 05:00:16 PM PDT 24
Finished Jul 19 05:00:19 PM PDT 24
Peak memory 208520 kb
Host smart-2f8b0739-ebb2-43ce-a5d4-8b22c3f9cb1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203749090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.203749090
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.3351423583
Short name T475
Test name
Test status
Simulation time 69964491 ps
CPU time 0.82 seconds
Started Jul 19 05:00:18 PM PDT 24
Finished Jul 19 05:00:22 PM PDT 24
Peak memory 208512 kb
Host smart-f02e718d-b865-4901-a35c-919cacacf4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351423583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.3351423583
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1908007392
Short name T288
Test name
Test status
Simulation time 218306051 ps
CPU time 7.95 seconds
Started Jul 19 05:00:19 PM PDT 24
Finished Jul 19 05:00:29 PM PDT 24
Peak memory 217832 kb
Host smart-aa4743ed-7d74-4e18-95ef-fa3f1d4a1461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908007392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1908007392
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1147233278
Short name T594
Test name
Test status
Simulation time 1989579923 ps
CPU time 11.97 seconds
Started Jul 19 05:00:18 PM PDT 24
Finished Jul 19 05:00:33 PM PDT 24
Peak memory 216968 kb
Host smart-1e254372-8f9e-49c9-a52a-a625486a1411
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147233278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1147233278
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1801469337
Short name T704
Test name
Test status
Simulation time 2226494238 ps
CPU time 63.77 seconds
Started Jul 19 05:00:17 PM PDT 24
Finished Jul 19 05:01:24 PM PDT 24
Peak memory 217844 kb
Host smart-9e932896-a720-447d-9a3e-6874b6c5bafc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801469337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1801469337
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3966272989
Short name T498
Test name
Test status
Simulation time 82401704 ps
CPU time 3.04 seconds
Started Jul 19 05:00:17 PM PDT 24
Finished Jul 19 05:00:23 PM PDT 24
Peak memory 217216 kb
Host smart-518a5e0f-8126-419f-9240-10194b2f409b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966272989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3
966272989
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2368219733
Short name T836
Test name
Test status
Simulation time 135606815 ps
CPU time 2.76 seconds
Started Jul 19 05:00:17 PM PDT 24
Finished Jul 19 05:00:23 PM PDT 24
Peak memory 221164 kb
Host smart-874bab53-e713-4e77-b465-b6349daa4f66
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368219733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2368219733
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.739878449
Short name T318
Test name
Test status
Simulation time 1175408160 ps
CPU time 32.12 seconds
Started Jul 19 05:00:18 PM PDT 24
Finished Jul 19 05:00:53 PM PDT 24
Peak memory 217124 kb
Host smart-3d7bde32-b86a-4905-b7f8-24c7390efaa9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739878449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_regwen_during_op.739878449
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3713929470
Short name T22
Test name
Test status
Simulation time 222292277 ps
CPU time 4.31 seconds
Started Jul 19 05:00:19 PM PDT 24
Finished Jul 19 05:00:26 PM PDT 24
Peak memory 217144 kb
Host smart-a2f201df-1dab-41be-86d8-fd4ca5d74080
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713929470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3713929470
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3611602598
Short name T815
Test name
Test status
Simulation time 12185093281 ps
CPU time 46.5 seconds
Started Jul 19 05:00:16 PM PDT 24
Finished Jul 19 05:01:04 PM PDT 24
Peak memory 275112 kb
Host smart-8b52e3e3-0ed9-4a96-a86e-2219599be4fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611602598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3611602598
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1939457737
Short name T283
Test name
Test status
Simulation time 1082372409 ps
CPU time 12.78 seconds
Started Jul 19 05:00:20 PM PDT 24
Finished Jul 19 05:00:35 PM PDT 24
Peak memory 250392 kb
Host smart-867d3e1b-40ef-4e14-aa71-ff1eea42b24e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939457737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1939457737
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.4132478941
Short name T682
Test name
Test status
Simulation time 81643246 ps
CPU time 2.79 seconds
Started Jul 19 05:00:19 PM PDT 24
Finished Jul 19 05:00:24 PM PDT 24
Peak memory 217760 kb
Host smart-9a85c9fd-ac67-411f-b63d-0a8dbddada8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132478941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.4132478941
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.355439468
Short name T726
Test name
Test status
Simulation time 189539287 ps
CPU time 10.92 seconds
Started Jul 19 05:00:18 PM PDT 24
Finished Jul 19 05:00:32 PM PDT 24
Peak memory 214092 kb
Host smart-7049028e-778c-4dac-bf33-1fc4ca665ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355439468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.355439468
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2606560245
Short name T61
Test name
Test status
Simulation time 237306727 ps
CPU time 21.95 seconds
Started Jul 19 05:00:17 PM PDT 24
Finished Jul 19 05:00:42 PM PDT 24
Peak memory 267548 kb
Host smart-02f3d392-595c-416f-84a5-43f1cf5a225e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606560245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2606560245
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3267581974
Short name T415
Test name
Test status
Simulation time 263567405 ps
CPU time 10.93 seconds
Started Jul 19 05:00:20 PM PDT 24
Finished Jul 19 05:00:33 PM PDT 24
Peak memory 218436 kb
Host smart-90875f92-0a51-468d-a635-3bfb6d76591d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267581974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3267581974
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1452159117
Short name T184
Test name
Test status
Simulation time 3343971544 ps
CPU time 17.23 seconds
Started Jul 19 05:00:16 PM PDT 24
Finished Jul 19 05:00:36 PM PDT 24
Peak memory 218584 kb
Host smart-c19c09af-fb58-49f9-a6b0-e25175983a9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452159117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1452159117
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2073442255
Short name T425
Test name
Test status
Simulation time 2608408614 ps
CPU time 11.38 seconds
Started Jul 19 05:00:16 PM PDT 24
Finished Jul 19 05:00:30 PM PDT 24
Peak memory 224924 kb
Host smart-1eb25110-eb8d-4a95-8759-478899a52f88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073442255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
073442255
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.715668542
Short name T477
Test name
Test status
Simulation time 956329938 ps
CPU time 9.23 seconds
Started Jul 19 05:00:17 PM PDT 24
Finished Jul 19 05:00:29 PM PDT 24
Peak memory 224116 kb
Host smart-961b595b-d233-47ff-aebb-c180bdfe2fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715668542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.715668542
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1500879553
Short name T569
Test name
Test status
Simulation time 46532809 ps
CPU time 2.19 seconds
Started Jul 19 05:00:17 PM PDT 24
Finished Jul 19 05:00:22 PM PDT 24
Peak memory 213956 kb
Host smart-6d144934-f05f-4f17-abfa-c87988ddbba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500879553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1500879553
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1122687658
Short name T343
Test name
Test status
Simulation time 655068599 ps
CPU time 27.65 seconds
Started Jul 19 05:00:18 PM PDT 24
Finished Jul 19 05:00:49 PM PDT 24
Peak memory 247168 kb
Host smart-b2090bf3-b6d5-44d7-b8be-4da560097fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122687658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1122687658
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.4221632133
Short name T617
Test name
Test status
Simulation time 281705337 ps
CPU time 7.97 seconds
Started Jul 19 05:00:17 PM PDT 24
Finished Jul 19 05:00:28 PM PDT 24
Peak memory 246744 kb
Host smart-d9795834-6f1b-4503-b479-5ac8fdf06429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221632133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.4221632133
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.4258628834
Short name T327
Test name
Test status
Simulation time 9928750317 ps
CPU time 131.06 seconds
Started Jul 19 05:00:19 PM PDT 24
Finished Jul 19 05:02:32 PM PDT 24
Peak memory 271520 kb
Host smart-88df433c-3943-4587-9124-f12da1b1a812
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258628834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.4258628834
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1040237418
Short name T46
Test name
Test status
Simulation time 22239183 ps
CPU time 0.91 seconds
Started Jul 19 05:00:20 PM PDT 24
Finished Jul 19 05:00:23 PM PDT 24
Peak memory 208428 kb
Host smart-60e1ac1d-7641-4a13-b878-b529b4f95ad8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040237418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1040237418
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3210225355
Short name T406
Test name
Test status
Simulation time 19031534 ps
CPU time 0.92 seconds
Started Jul 19 05:01:08 PM PDT 24
Finished Jul 19 05:01:11 PM PDT 24
Peak memory 208336 kb
Host smart-60150020-65f2-4492-9b51-c33bc9bc1a68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210225355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3210225355
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.4283028619
Short name T777
Test name
Test status
Simulation time 354844587 ps
CPU time 11.72 seconds
Started Jul 19 05:00:58 PM PDT 24
Finished Jul 19 05:01:11 PM PDT 24
Peak memory 217820 kb
Host smart-1334cf23-8237-427d-98eb-cc8816502870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283028619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.4283028619
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1437735697
Short name T861
Test name
Test status
Simulation time 1319108535 ps
CPU time 8.66 seconds
Started Jul 19 05:01:08 PM PDT 24
Finished Jul 19 05:01:18 PM PDT 24
Peak memory 216892 kb
Host smart-9d6fc62e-17a7-41bd-94c6-e26da87bb5cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437735697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1437735697
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.988317537
Short name T230
Test name
Test status
Simulation time 2613254083 ps
CPU time 76.46 seconds
Started Jul 19 05:01:08 PM PDT 24
Finished Jul 19 05:02:27 PM PDT 24
Peak memory 225580 kb
Host smart-e0af8b7d-99de-40d1-b9f4-17456138ecbd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988317537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_er
rors.988317537
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1412320570
Short name T461
Test name
Test status
Simulation time 1465669970 ps
CPU time 11.09 seconds
Started Jul 19 05:01:07 PM PDT 24
Finished Jul 19 05:01:19 PM PDT 24
Peak memory 224928 kb
Host smart-10f29ce2-5e8f-4493-8d6d-29fd17251b2d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412320570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1412320570
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1099605485
Short name T783
Test name
Test status
Simulation time 1063524892 ps
CPU time 7.43 seconds
Started Jul 19 05:01:08 PM PDT 24
Finished Jul 19 05:01:17 PM PDT 24
Peak memory 217156 kb
Host smart-d6b932de-0d77-4e72-bd88-40ce446e8ab4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099605485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1099605485
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1461029674
Short name T741
Test name
Test status
Simulation time 6094870732 ps
CPU time 60.07 seconds
Started Jul 19 05:01:06 PM PDT 24
Finished Jul 19 05:02:07 PM PDT 24
Peak memory 257180 kb
Host smart-3396091a-39b4-4c81-ab66-a6e01a464373
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461029674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1461029674
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1293598748
Short name T289
Test name
Test status
Simulation time 1861350763 ps
CPU time 17.46 seconds
Started Jul 19 05:01:09 PM PDT 24
Finished Jul 19 05:01:29 PM PDT 24
Peak memory 247328 kb
Host smart-6aab6475-0dcf-43ff-beca-7ff20f89c7ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293598748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1293598748
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2177773595
Short name T774
Test name
Test status
Simulation time 655719307 ps
CPU time 3.34 seconds
Started Jul 19 05:00:58 PM PDT 24
Finished Jul 19 05:01:03 PM PDT 24
Peak memory 217808 kb
Host smart-b89f3db9-e435-4a37-a46a-439bdc07fed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177773595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2177773595
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3118689753
Short name T773
Test name
Test status
Simulation time 418600585 ps
CPU time 10.91 seconds
Started Jul 19 05:01:07 PM PDT 24
Finished Jul 19 05:01:20 PM PDT 24
Peak memory 225600 kb
Host smart-aed27ca5-7e62-4028-96cd-a8a4f809979a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118689753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3118689753
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.792322741
Short name T291
Test name
Test status
Simulation time 2566904510 ps
CPU time 22.39 seconds
Started Jul 19 05:01:08 PM PDT 24
Finished Jul 19 05:01:32 PM PDT 24
Peak memory 218444 kb
Host smart-7d374bda-fb9f-4e14-90b0-ff6cb3e8c886
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792322741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.792322741
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2770050501
Short name T530
Test name
Test status
Simulation time 562276908 ps
CPU time 10.91 seconds
Started Jul 19 05:01:06 PM PDT 24
Finished Jul 19 05:01:19 PM PDT 24
Peak memory 225540 kb
Host smart-23893e02-0891-457e-9d8d-90e4dea7e463
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770050501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2770050501
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3653222257
Short name T834
Test name
Test status
Simulation time 245398357 ps
CPU time 11.1 seconds
Started Jul 19 05:01:08 PM PDT 24
Finished Jul 19 05:01:21 PM PDT 24
Peak memory 225592 kb
Host smart-ac33851d-8c68-4b8d-b42b-41aa7563d28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653222257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3653222257
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3323676744
Short name T75
Test name
Test status
Simulation time 37762431 ps
CPU time 1.81 seconds
Started Jul 19 05:01:02 PM PDT 24
Finished Jul 19 05:01:06 PM PDT 24
Peak memory 213380 kb
Host smart-14c202a1-bece-4904-be2c-aec68e79f3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323676744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3323676744
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3385726225
Short name T787
Test name
Test status
Simulation time 225139705 ps
CPU time 22.04 seconds
Started Jul 19 05:00:58 PM PDT 24
Finished Jul 19 05:01:20 PM PDT 24
Peak memory 250452 kb
Host smart-fead514f-80bd-4924-afc1-8a8b1b06ec2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385726225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3385726225
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.469917625
Short name T396
Test name
Test status
Simulation time 61855811 ps
CPU time 9.89 seconds
Started Jul 19 05:00:58 PM PDT 24
Finished Jul 19 05:01:09 PM PDT 24
Peak memory 250508 kb
Host smart-eb1dd8fc-492e-46df-a59c-b64b25e1a169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469917625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.469917625
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2213136595
Short name T313
Test name
Test status
Simulation time 7686807174 ps
CPU time 101.31 seconds
Started Jul 19 05:01:08 PM PDT 24
Finished Jul 19 05:02:52 PM PDT 24
Peak memory 283292 kb
Host smart-bbfa2d17-a3b5-4e28-9a8b-64d9abfbc022
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213136595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2213136595
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3381959451
Short name T765
Test name
Test status
Simulation time 30007308 ps
CPU time 1.62 seconds
Started Jul 19 05:00:58 PM PDT 24
Finished Jul 19 05:01:01 PM PDT 24
Peak memory 217176 kb
Host smart-c1b23ff6-6a7d-400c-90b4-d7238f2709de
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381959451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3381959451
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3458468238
Short name T715
Test name
Test status
Simulation time 87101417 ps
CPU time 0.87 seconds
Started Jul 19 05:01:16 PM PDT 24
Finished Jul 19 05:01:18 PM PDT 24
Peak memory 208336 kb
Host smart-fbab3908-da73-4835-861c-a7a2dc635ef1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458468238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3458468238
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.491619611
Short name T389
Test name
Test status
Simulation time 1118473014 ps
CPU time 15.33 seconds
Started Jul 19 05:01:07 PM PDT 24
Finished Jul 19 05:01:25 PM PDT 24
Peak memory 217824 kb
Host smart-a1d2947e-ac27-440a-ba03-9a87b4dec1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491619611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.491619611
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3993326157
Short name T802
Test name
Test status
Simulation time 315811233 ps
CPU time 8.17 seconds
Started Jul 19 05:01:16 PM PDT 24
Finished Jul 19 05:01:25 PM PDT 24
Peak memory 216692 kb
Host smart-91071e84-ce2c-4701-a6eb-22d4350cb2d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993326157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3993326157
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2540801503
Short name T731
Test name
Test status
Simulation time 3044404807 ps
CPU time 45.14 seconds
Started Jul 19 05:01:19 PM PDT 24
Finished Jul 19 05:02:05 PM PDT 24
Peak memory 225464 kb
Host smart-33ceb3a7-e495-4437-a356-de2c1ae3215b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540801503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2540801503
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.195479152
Short name T632
Test name
Test status
Simulation time 262717557 ps
CPU time 5.26 seconds
Started Jul 19 05:01:19 PM PDT 24
Finished Jul 19 05:01:26 PM PDT 24
Peak memory 222748 kb
Host smart-23a4ac2b-5e28-457b-b921-1d296dc1e487
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195479152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.195479152
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3973483892
Short name T489
Test name
Test status
Simulation time 72608624 ps
CPU time 2.75 seconds
Started Jul 19 05:01:07 PM PDT 24
Finished Jul 19 05:01:12 PM PDT 24
Peak memory 217128 kb
Host smart-273d43cc-1c37-4d3d-84ec-2ff8b798d815
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973483892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3973483892
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3970318590
Short name T245
Test name
Test status
Simulation time 6582649433 ps
CPU time 30.51 seconds
Started Jul 19 05:01:17 PM PDT 24
Finished Jul 19 05:01:49 PM PDT 24
Peak memory 252564 kb
Host smart-abffe8ed-c04b-4bfe-b7ad-5d468cdcb75b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970318590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3970318590
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2697526053
Short name T660
Test name
Test status
Simulation time 653946964 ps
CPU time 6.43 seconds
Started Jul 19 05:01:16 PM PDT 24
Finished Jul 19 05:01:23 PM PDT 24
Peak memory 222296 kb
Host smart-6d14f912-9c29-4d49-94a9-dd42b2becac8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697526053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.2697526053
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.286592332
Short name T721
Test name
Test status
Simulation time 326800609 ps
CPU time 3.43 seconds
Started Jul 19 05:01:07 PM PDT 24
Finished Jul 19 05:01:13 PM PDT 24
Peak memory 217764 kb
Host smart-39aac43b-792b-4282-b80c-13b1c5483cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286592332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.286592332
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.3129002223
Short name T806
Test name
Test status
Simulation time 333174687 ps
CPU time 16.28 seconds
Started Jul 19 05:01:18 PM PDT 24
Finished Jul 19 05:01:36 PM PDT 24
Peak memory 218448 kb
Host smart-efec9dab-8cc5-4f55-b0c9-bc095b5e5b93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129002223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3129002223
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.687130347
Short name T637
Test name
Test status
Simulation time 963043401 ps
CPU time 10.56 seconds
Started Jul 19 05:01:19 PM PDT 24
Finished Jul 19 05:01:31 PM PDT 24
Peak memory 225352 kb
Host smart-86094496-0757-4a01-a628-e02b5ccb3b2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687130347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_di
gest.687130347
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1065533551
Short name T604
Test name
Test status
Simulation time 258477992 ps
CPU time 7.97 seconds
Started Jul 19 05:01:06 PM PDT 24
Finished Jul 19 05:01:16 PM PDT 24
Peak memory 217872 kb
Host smart-ad39cb6f-a6d0-4419-b181-0f7925f12bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065533551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1065533551
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3253131031
Short name T368
Test name
Test status
Simulation time 23313640 ps
CPU time 1.83 seconds
Started Jul 19 05:01:08 PM PDT 24
Finished Jul 19 05:01:12 PM PDT 24
Peak memory 213488 kb
Host smart-02b91493-e12b-4c61-981c-27f1ede2e824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253131031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3253131031
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.2145386346
Short name T711
Test name
Test status
Simulation time 297327506 ps
CPU time 29.64 seconds
Started Jul 19 05:01:06 PM PDT 24
Finished Jul 19 05:01:38 PM PDT 24
Peak memory 250596 kb
Host smart-bf1dee3a-f1d6-4eff-892e-78596f35ff22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145386346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2145386346
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1729376019
Short name T730
Test name
Test status
Simulation time 73254974 ps
CPU time 10.54 seconds
Started Jul 19 05:01:09 PM PDT 24
Finished Jul 19 05:01:22 PM PDT 24
Peak memory 250544 kb
Host smart-5d1ef456-8f2a-40d6-8cad-3a8916908604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729376019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1729376019
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1320223947
Short name T427
Test name
Test status
Simulation time 11765472856 ps
CPU time 59.99 seconds
Started Jul 19 05:01:17 PM PDT 24
Finished Jul 19 05:02:18 PM PDT 24
Peak memory 227936 kb
Host smart-c5b63356-b6ee-4542-90a5-5f4e2b7f3529
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320223947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1320223947
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1180041260
Short name T45
Test name
Test status
Simulation time 13121076 ps
CPU time 1.01 seconds
Started Jul 19 05:01:08 PM PDT 24
Finished Jul 19 05:01:11 PM PDT 24
Peak memory 208468 kb
Host smart-254692e8-c9c5-4a13-bbac-07a3a8891e7b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180041260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1180041260
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1495677196
Short name T325
Test name
Test status
Simulation time 235613136 ps
CPU time 1.46 seconds
Started Jul 19 05:01:16 PM PDT 24
Finished Jul 19 05:01:19 PM PDT 24
Peak memory 208532 kb
Host smart-7ca2f69d-e155-4279-93ce-e989f5d332e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495677196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1495677196
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1396966666
Short name T591
Test name
Test status
Simulation time 270694923 ps
CPU time 11.32 seconds
Started Jul 19 05:01:20 PM PDT 24
Finished Jul 19 05:01:32 PM PDT 24
Peak memory 217740 kb
Host smart-6b14741f-7ce7-4cb3-86ca-2be0e2a87690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396966666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1396966666
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.484812998
Short name T697
Test name
Test status
Simulation time 460277635 ps
CPU time 2.06 seconds
Started Jul 19 05:01:18 PM PDT 24
Finished Jul 19 05:01:22 PM PDT 24
Peak memory 216692 kb
Host smart-791b792e-fc90-496a-b4a3-0017aaa05b25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484812998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.484812998
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3664298316
Short name T747
Test name
Test status
Simulation time 8608643264 ps
CPU time 34.6 seconds
Started Jul 19 05:01:17 PM PDT 24
Finished Jul 19 05:01:53 PM PDT 24
Peak memory 225544 kb
Host smart-6eaf303c-2760-459a-b6a5-3b33b3c77057
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664298316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3664298316
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2654912162
Short name T585
Test name
Test status
Simulation time 1621150048 ps
CPU time 5.21 seconds
Started Jul 19 05:01:18 PM PDT 24
Finished Jul 19 05:01:25 PM PDT 24
Peak memory 222648 kb
Host smart-9bf93c87-44b4-443d-9257-9c966d57614a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654912162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2654912162
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3776961196
Short name T543
Test name
Test status
Simulation time 1298441764 ps
CPU time 10.92 seconds
Started Jul 19 05:01:18 PM PDT 24
Finished Jul 19 05:01:30 PM PDT 24
Peak memory 216832 kb
Host smart-914caeb6-ab38-4a00-b2b4-0c6958310a59
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776961196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3776961196
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2683356784
Short name T487
Test name
Test status
Simulation time 12601382521 ps
CPU time 59.23 seconds
Started Jul 19 05:01:18 PM PDT 24
Finished Jul 19 05:02:19 PM PDT 24
Peak memory 250968 kb
Host smart-464e3f4e-0d3b-4a74-9095-12abc425b427
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683356784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2683356784
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.4115076451
Short name T340
Test name
Test status
Simulation time 1891869458 ps
CPU time 17.89 seconds
Started Jul 19 05:01:17 PM PDT 24
Finished Jul 19 05:01:37 PM PDT 24
Peak memory 249840 kb
Host smart-470b2ea6-8ea8-409f-9e35-2ee96e1f05e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115076451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.4115076451
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.504727624
Short name T262
Test name
Test status
Simulation time 1275750562 ps
CPU time 15.5 seconds
Started Jul 19 05:01:16 PM PDT 24
Finished Jul 19 05:01:32 PM PDT 24
Peak memory 219480 kb
Host smart-4348b0f9-0ef5-4d51-9bf0-a702d3d2a341
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504727624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.504727624
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3469678150
Short name T371
Test name
Test status
Simulation time 3225966464 ps
CPU time 11.66 seconds
Started Jul 19 05:01:18 PM PDT 24
Finished Jul 19 05:01:31 PM PDT 24
Peak memory 225368 kb
Host smart-d6a0e745-a726-48ac-9f86-8bbe639bd7db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469678150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3469678150
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3273034392
Short name T846
Test name
Test status
Simulation time 1606958766 ps
CPU time 9.43 seconds
Started Jul 19 05:01:19 PM PDT 24
Finished Jul 19 05:01:30 PM PDT 24
Peak memory 225560 kb
Host smart-3c1d1a9c-7d69-43ae-8905-56692deffb30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273034392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3273034392
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.25498297
Short name T268
Test name
Test status
Simulation time 1374366946 ps
CPU time 12.52 seconds
Started Jul 19 05:01:15 PM PDT 24
Finished Jul 19 05:01:28 PM PDT 24
Peak memory 217824 kb
Host smart-55d447d3-ee41-4e40-804e-08f29ce99eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25498297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.25498297
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.718528805
Short name T375
Test name
Test status
Simulation time 51546921 ps
CPU time 2.64 seconds
Started Jul 19 05:01:17 PM PDT 24
Finished Jul 19 05:01:22 PM PDT 24
Peak memory 214064 kb
Host smart-9ed40409-5a2f-4989-82f1-dee2426544aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718528805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.718528805
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.782296692
Short name T753
Test name
Test status
Simulation time 178889674 ps
CPU time 18.08 seconds
Started Jul 19 05:01:17 PM PDT 24
Finished Jul 19 05:01:37 PM PDT 24
Peak memory 250628 kb
Host smart-706c61eb-a20f-4f2d-a269-278749287cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782296692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.782296692
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3594967503
Short name T739
Test name
Test status
Simulation time 107784164 ps
CPU time 10.38 seconds
Started Jul 19 05:01:16 PM PDT 24
Finished Jul 19 05:01:28 PM PDT 24
Peak memory 250544 kb
Host smart-cf8b90bb-bb2a-4f2a-8e2d-62e9d86eb539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594967503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3594967503
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2525472958
Short name T821
Test name
Test status
Simulation time 9190560820 ps
CPU time 81.64 seconds
Started Jul 19 05:01:18 PM PDT 24
Finished Jul 19 05:02:42 PM PDT 24
Peak memory 243796 kb
Host smart-b6e515fb-e20b-4d9e-b0fc-f2df325210a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525472958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2525472958
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.405293346
Short name T309
Test name
Test status
Simulation time 89077676 ps
CPU time 0.8 seconds
Started Jul 19 05:01:15 PM PDT 24
Finished Jul 19 05:01:17 PM PDT 24
Peak memory 208280 kb
Host smart-10b73dd9-6828-4ba1-9c72-43f2026b8616
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405293346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct
rl_volatile_unlock_smoke.405293346
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.1715297580
Short name T430
Test name
Test status
Simulation time 105960523 ps
CPU time 1.07 seconds
Started Jul 19 05:01:26 PM PDT 24
Finished Jul 19 05:01:30 PM PDT 24
Peak memory 208484 kb
Host smart-94ec6d09-aef2-4d53-b9e0-eaad47fa1dd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715297580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1715297580
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1516204976
Short name T665
Test name
Test status
Simulation time 2111087871 ps
CPU time 16.92 seconds
Started Jul 19 05:01:24 PM PDT 24
Finished Jul 19 05:01:42 PM PDT 24
Peak memory 217784 kb
Host smart-2a67f4a3-86e8-4ce9-8ad7-0bd59d673d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516204976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1516204976
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2908314587
Short name T545
Test name
Test status
Simulation time 364103057 ps
CPU time 4.26 seconds
Started Jul 19 05:01:26 PM PDT 24
Finished Jul 19 05:01:32 PM PDT 24
Peak memory 216764 kb
Host smart-413bc53a-fb1b-455a-be60-9d0f1bddf4e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908314587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2908314587
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.4201219657
Short name T428
Test name
Test status
Simulation time 3185115782 ps
CPU time 86.22 seconds
Started Jul 19 05:01:26 PM PDT 24
Finished Jul 19 05:02:54 PM PDT 24
Peak memory 218512 kb
Host smart-6c66535d-146e-4f71-9e22-46e7386b01d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201219657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.4201219657
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2889912005
Short name T573
Test name
Test status
Simulation time 962467080 ps
CPU time 7.98 seconds
Started Jul 19 05:01:26 PM PDT 24
Finished Jul 19 05:01:37 PM PDT 24
Peak memory 222652 kb
Host smart-f3e61c20-0f6b-42fa-8042-1007aa417ede
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889912005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2889912005
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2283720881
Short name T462
Test name
Test status
Simulation time 384276406 ps
CPU time 6.52 seconds
Started Jul 19 05:01:24 PM PDT 24
Finished Jul 19 05:01:33 PM PDT 24
Peak memory 217136 kb
Host smart-b5d1e0b6-1805-4904-863e-91eece6b189a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283720881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2283720881
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2449398564
Short name T266
Test name
Test status
Simulation time 763994129 ps
CPU time 39.91 seconds
Started Jul 19 05:01:25 PM PDT 24
Finished Jul 19 05:02:07 PM PDT 24
Peak memory 250484 kb
Host smart-afc7c4d8-a0b5-414d-a9e3-fb3cd5e9d216
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449398564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2449398564
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1765513356
Short name T831
Test name
Test status
Simulation time 358071261 ps
CPU time 17.25 seconds
Started Jul 19 05:01:24 PM PDT 24
Finished Jul 19 05:01:43 PM PDT 24
Peak memory 250496 kb
Host smart-227a3f87-c8b1-46bb-aec3-36aa4fc4e30f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765513356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1765513356
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2396126995
Short name T481
Test name
Test status
Simulation time 135641506 ps
CPU time 5.79 seconds
Started Jul 19 05:01:27 PM PDT 24
Finished Jul 19 05:01:35 PM PDT 24
Peak memory 217812 kb
Host smart-ba30bc5b-f4b9-4e65-a7a2-fc12c4788ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396126995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2396126995
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3141696510
Short name T690
Test name
Test status
Simulation time 1086685727 ps
CPU time 15.09 seconds
Started Jul 19 05:01:23 PM PDT 24
Finished Jul 19 05:01:39 PM PDT 24
Peak memory 225420 kb
Host smart-131cc065-7fa8-4a02-a092-e632cd8ec59c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141696510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3141696510
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3394267942
Short name T840
Test name
Test status
Simulation time 2979856192 ps
CPU time 15.96 seconds
Started Jul 19 05:01:26 PM PDT 24
Finished Jul 19 05:01:44 PM PDT 24
Peak memory 217856 kb
Host smart-55127c90-84f5-48a6-9bd1-1dd982787a9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394267942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3394267942
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1617438795
Short name T277
Test name
Test status
Simulation time 1576546416 ps
CPU time 7.33 seconds
Started Jul 19 05:01:26 PM PDT 24
Finished Jul 19 05:01:35 PM PDT 24
Peak memory 217688 kb
Host smart-b49169e8-ea5d-4ed7-870f-7946cd43386f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617438795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1617438795
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3462670531
Short name T315
Test name
Test status
Simulation time 437385595 ps
CPU time 9.63 seconds
Started Jul 19 05:01:25 PM PDT 24
Finished Jul 19 05:01:36 PM PDT 24
Peak memory 217828 kb
Host smart-6b4296f2-eba7-4259-9d7f-b05d157aa075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462670531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3462670531
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2548564505
Short name T812
Test name
Test status
Simulation time 96550857 ps
CPU time 3.12 seconds
Started Jul 19 05:01:17 PM PDT 24
Finished Jul 19 05:01:22 PM PDT 24
Peak memory 217228 kb
Host smart-00acab63-fe6d-4d63-9b16-aee11a97cb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548564505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2548564505
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.3777646752
Short name T817
Test name
Test status
Simulation time 753788538 ps
CPU time 19.84 seconds
Started Jul 19 05:01:17 PM PDT 24
Finished Jul 19 05:01:39 PM PDT 24
Peak memory 250492 kb
Host smart-25a8b42f-2ca0-4f10-b8ab-1e40212e87e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777646752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.3777646752
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1246515401
Short name T720
Test name
Test status
Simulation time 245818917 ps
CPU time 6.74 seconds
Started Jul 19 05:01:19 PM PDT 24
Finished Jul 19 05:01:27 PM PDT 24
Peak memory 246140 kb
Host smart-dbe1bdab-37ce-45be-8c30-59e26c462487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246515401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1246515401
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.4134582751
Short name T281
Test name
Test status
Simulation time 1514673667 ps
CPU time 62.43 seconds
Started Jul 19 05:01:28 PM PDT 24
Finished Jul 19 05:02:32 PM PDT 24
Peak memory 276476 kb
Host smart-f5c0372e-7aa5-4f0e-82b5-cdd3dd439b7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134582751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.4134582751
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.1087099495
Short name T170
Test name
Test status
Simulation time 48484094310 ps
CPU time 366.58 seconds
Started Jul 19 05:01:26 PM PDT 24
Finished Jul 19 05:07:34 PM PDT 24
Peak memory 300652 kb
Host smart-64c93fc4-060e-48c7-8d8a-596d0c2fe5e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1087099495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.1087099495
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2151651867
Short name T597
Test name
Test status
Simulation time 36133681 ps
CPU time 0.85 seconds
Started Jul 19 05:01:17 PM PDT 24
Finished Jul 19 05:01:20 PM PDT 24
Peak memory 208192 kb
Host smart-3f35a580-e405-44b4-9a22-4044a6e9b3fc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151651867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2151651867
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3065477708
Short name T150
Test name
Test status
Simulation time 58003638 ps
CPU time 0.95 seconds
Started Jul 19 05:01:27 PM PDT 24
Finished Jul 19 05:01:30 PM PDT 24
Peak memory 208420 kb
Host smart-ad1351be-e735-4d7d-9819-5d902b016ca5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065477708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3065477708
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.1945132364
Short name T807
Test name
Test status
Simulation time 886550410 ps
CPU time 22.03 seconds
Started Jul 19 05:01:26 PM PDT 24
Finished Jul 19 05:01:50 PM PDT 24
Peak memory 217208 kb
Host smart-56253c2f-1117-47ca-b02b-71731ee936be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945132364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1945132364
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2581290316
Short name T20
Test name
Test status
Simulation time 8396837847 ps
CPU time 117.79 seconds
Started Jul 19 05:01:24 PM PDT 24
Finished Jul 19 05:03:24 PM PDT 24
Peak memory 218512 kb
Host smart-ece3f331-9c92-4566-8759-508216b4d1bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581290316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2581290316
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2293334524
Short name T754
Test name
Test status
Simulation time 983324744 ps
CPU time 5.78 seconds
Started Jul 19 05:01:25 PM PDT 24
Finished Jul 19 05:01:33 PM PDT 24
Peak memory 222652 kb
Host smart-b2d76dc9-6e80-4486-b416-3992a927923f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293334524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2293334524
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.525461110
Short name T152
Test name
Test status
Simulation time 363935065 ps
CPU time 4.66 seconds
Started Jul 19 05:01:24 PM PDT 24
Finished Jul 19 05:01:30 PM PDT 24
Peak memory 217172 kb
Host smart-39c5804a-ffbd-4e5a-a895-3a6d2c6773cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525461110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
525461110
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3963302113
Short name T247
Test name
Test status
Simulation time 25991113945 ps
CPU time 60.02 seconds
Started Jul 19 05:01:25 PM PDT 24
Finished Jul 19 05:02:27 PM PDT 24
Peak memory 275128 kb
Host smart-4b746b50-0df2-4b87-a4be-03f344337f63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963302113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3963302113
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2900008580
Short name T699
Test name
Test status
Simulation time 5400643378 ps
CPU time 7.23 seconds
Started Jul 19 05:01:27 PM PDT 24
Finished Jul 19 05:01:36 PM PDT 24
Peak memory 225940 kb
Host smart-feebdeb7-2f8b-4902-875a-865e51f7d0c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900008580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2900008580
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3195415095
Short name T388
Test name
Test status
Simulation time 138723314 ps
CPU time 2.82 seconds
Started Jul 19 05:01:25 PM PDT 24
Finished Jul 19 05:01:30 PM PDT 24
Peak memory 217936 kb
Host smart-2eb3bf98-085b-482f-8b19-276b47aa9379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195415095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3195415095
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1491636808
Short name T619
Test name
Test status
Simulation time 768371656 ps
CPU time 16.2 seconds
Started Jul 19 05:01:26 PM PDT 24
Finished Jul 19 05:01:44 PM PDT 24
Peak memory 218472 kb
Host smart-2f1d610f-bf53-41ba-97e2-df5ee23d5789
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491636808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1491636808
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.249506099
Short name T531
Test name
Test status
Simulation time 612702625 ps
CPU time 9.43 seconds
Started Jul 19 05:01:26 PM PDT 24
Finished Jul 19 05:01:38 PM PDT 24
Peak memory 217788 kb
Host smart-f0d2f92c-804d-465f-ae92-0dc31187fa00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249506099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.249506099
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2923870514
Short name T232
Test name
Test status
Simulation time 1952237059 ps
CPU time 11.51 seconds
Started Jul 19 05:01:27 PM PDT 24
Finished Jul 19 05:01:40 PM PDT 24
Peak memory 225500 kb
Host smart-d710cffb-53ee-481d-a10c-5c7c1f9ac7dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923870514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2923870514
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1598465187
Short name T438
Test name
Test status
Simulation time 177571872 ps
CPU time 2.23 seconds
Started Jul 19 05:01:26 PM PDT 24
Finished Jul 19 05:01:31 PM PDT 24
Peak memory 217204 kb
Host smart-afed99cf-a452-4976-a537-3df8cd654d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598465187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1598465187
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.1744828837
Short name T535
Test name
Test status
Simulation time 614520794 ps
CPU time 19.45 seconds
Started Jul 19 05:01:27 PM PDT 24
Finished Jul 19 05:01:48 PM PDT 24
Peak memory 250476 kb
Host smart-c0f573c6-ea98-4c52-8370-49f29996647f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744828837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1744828837
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.588893171
Short name T179
Test name
Test status
Simulation time 98346904 ps
CPU time 8.01 seconds
Started Jul 19 05:01:25 PM PDT 24
Finished Jul 19 05:01:36 PM PDT 24
Peak memory 250556 kb
Host smart-51cb1972-4c2b-4278-ab6e-57ec33cb5851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588893171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.588893171
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3180534351
Short name T419
Test name
Test status
Simulation time 28098765426 ps
CPU time 363.05 seconds
Started Jul 19 05:01:25 PM PDT 24
Finished Jul 19 05:07:30 PM PDT 24
Peak memory 315532 kb
Host smart-62ea8868-1009-40ce-b2ef-50a7a5797570
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180534351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3180534351
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3954163187
Short name T737
Test name
Test status
Simulation time 11361842 ps
CPU time 0.79 seconds
Started Jul 19 05:01:25 PM PDT 24
Finished Jul 19 05:01:28 PM PDT 24
Peak memory 208344 kb
Host smart-e0b193d0-20f6-445e-abb4-c282893d406e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954163187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3954163187
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3449991514
Short name T519
Test name
Test status
Simulation time 21062563 ps
CPU time 1.13 seconds
Started Jul 19 05:01:37 PM PDT 24
Finished Jul 19 05:01:40 PM PDT 24
Peak memory 208488 kb
Host smart-1d9b6db3-8e58-4722-af9b-3b4504f8fd7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449991514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3449991514
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2377852574
Short name T483
Test name
Test status
Simulation time 162778749 ps
CPU time 9.27 seconds
Started Jul 19 05:01:35 PM PDT 24
Finished Jul 19 05:01:46 PM PDT 24
Peak memory 217752 kb
Host smart-9a00f943-0a79-4a62-a843-69695f978bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377852574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2377852574
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.3889889184
Short name T799
Test name
Test status
Simulation time 1650432938 ps
CPU time 34.04 seconds
Started Jul 19 05:01:35 PM PDT 24
Finished Jul 19 05:02:11 PM PDT 24
Peak memory 218400 kb
Host smart-ee9f8ff8-aa28-40d3-b464-9ae774231e64
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889889184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.3889889184
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.482574811
Short name T302
Test name
Test status
Simulation time 1927374990 ps
CPU time 11.37 seconds
Started Jul 19 05:01:37 PM PDT 24
Finished Jul 19 05:01:50 PM PDT 24
Peak memory 222816 kb
Host smart-cfaaf5ca-6d54-45a2-9a3e-2859d388bcbd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482574811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.482574811
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.817422363
Short name T308
Test name
Test status
Simulation time 450295750 ps
CPU time 2.49 seconds
Started Jul 19 05:01:34 PM PDT 24
Finished Jul 19 05:01:38 PM PDT 24
Peak memory 217088 kb
Host smart-8e5f985b-78d5-4be7-8122-e493f04db693
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817422363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.
817422363
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3084584559
Short name T849
Test name
Test status
Simulation time 2540500882 ps
CPU time 50.25 seconds
Started Jul 19 05:01:36 PM PDT 24
Finished Jul 19 05:02:28 PM PDT 24
Peak memory 276852 kb
Host smart-a656e916-3f8e-4b09-9096-523d83eac4e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084584559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3084584559
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3423109369
Short name T377
Test name
Test status
Simulation time 21047307703 ps
CPU time 35.93 seconds
Started Jul 19 05:01:34 PM PDT 24
Finished Jul 19 05:02:12 PM PDT 24
Peak memory 250524 kb
Host smart-756bfe61-cb2b-4218-9521-f37494d1c912
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423109369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.3423109369
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2900562803
Short name T488
Test name
Test status
Simulation time 175847914 ps
CPU time 3.96 seconds
Started Jul 19 05:01:38 PM PDT 24
Finished Jul 19 05:01:43 PM PDT 24
Peak memory 222040 kb
Host smart-7fda482f-8bbf-4d05-bef2-d6cffe330ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900562803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2900562803
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2233208576
Short name T630
Test name
Test status
Simulation time 2776151267 ps
CPU time 14.49 seconds
Started Jul 19 05:01:34 PM PDT 24
Finished Jul 19 05:01:50 PM PDT 24
Peak memory 217864 kb
Host smart-0045821b-6aa6-4962-bad7-2401df8a6221
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233208576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2233208576
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.4050232158
Short name T586
Test name
Test status
Simulation time 562421812 ps
CPU time 11.33 seconds
Started Jul 19 05:01:36 PM PDT 24
Finished Jul 19 05:01:49 PM PDT 24
Peak memory 225540 kb
Host smart-2b621637-a63a-4efa-8c43-b93f1e666c8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050232158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
4050232158
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2999718532
Short name T728
Test name
Test status
Simulation time 163521819 ps
CPU time 7.56 seconds
Started Jul 19 05:01:34 PM PDT 24
Finished Jul 19 05:01:43 PM PDT 24
Peak memory 225544 kb
Host smart-c3139665-5f61-4b9b-99de-4fd03d13d791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999718532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2999718532
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2187756461
Short name T76
Test name
Test status
Simulation time 55112528 ps
CPU time 2.36 seconds
Started Jul 19 05:01:36 PM PDT 24
Finished Jul 19 05:01:40 PM PDT 24
Peak memory 213576 kb
Host smart-3deba8aa-d074-485a-939f-a32bb935d6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187756461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2187756461
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3029378318
Short name T596
Test name
Test status
Simulation time 2399791553 ps
CPU time 25.73 seconds
Started Jul 19 05:01:39 PM PDT 24
Finished Jul 19 05:02:06 PM PDT 24
Peak memory 250572 kb
Host smart-d363fa0e-2320-49b2-b42a-aeba2ff43181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029378318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3029378318
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1537344210
Short name T562
Test name
Test status
Simulation time 226052119 ps
CPU time 6.73 seconds
Started Jul 19 05:01:34 PM PDT 24
Finished Jul 19 05:01:41 PM PDT 24
Peak memory 246488 kb
Host smart-9fd82eba-e068-4fb0-8254-c24e75f146b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537344210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1537344210
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.4126108085
Short name T693
Test name
Test status
Simulation time 30591034300 ps
CPU time 151.67 seconds
Started Jul 19 05:01:35 PM PDT 24
Finished Jul 19 05:04:09 PM PDT 24
Peak memory 332456 kb
Host smart-8042b4aa-58fb-4898-b4f7-34f9c1e8a6bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126108085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.4126108085
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.606405198
Short name T95
Test name
Test status
Simulation time 68622553198 ps
CPU time 534.24 seconds
Started Jul 19 05:01:32 PM PDT 24
Finished Jul 19 05:10:27 PM PDT 24
Peak memory 283564 kb
Host smart-e63d67ad-2509-41ea-be19-69a814b895e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=606405198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.606405198
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.992600287
Short name T172
Test name
Test status
Simulation time 12899103 ps
CPU time 0.97 seconds
Started Jul 19 05:01:38 PM PDT 24
Finished Jul 19 05:01:41 PM PDT 24
Peak memory 208444 kb
Host smart-5fab2f94-df9f-424e-b0c8-5e3e2e245ec4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992600287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.992600287
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2827477536
Short name T222
Test name
Test status
Simulation time 38571256 ps
CPU time 1.19 seconds
Started Jul 19 05:01:35 PM PDT 24
Finished Jul 19 05:01:39 PM PDT 24
Peak memory 208548 kb
Host smart-71ab5b1e-520b-417d-8c24-298b81bb07a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827477536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2827477536
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.666333597
Short name T511
Test name
Test status
Simulation time 370690259 ps
CPU time 15.37 seconds
Started Jul 19 05:01:34 PM PDT 24
Finished Jul 19 05:01:51 PM PDT 24
Peak memory 217660 kb
Host smart-d458db46-2325-4b9d-b784-552312798e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666333597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.666333597
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1223098519
Short name T303
Test name
Test status
Simulation time 172412699 ps
CPU time 1.86 seconds
Started Jul 19 05:01:33 PM PDT 24
Finished Jul 19 05:01:36 PM PDT 24
Peak memory 216604 kb
Host smart-29e9cf86-e485-471b-a726-bd904c1681dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223098519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1223098519
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.334288739
Short name T542
Test name
Test status
Simulation time 9617329035 ps
CPU time 59.37 seconds
Started Jul 19 05:01:33 PM PDT 24
Finished Jul 19 05:02:34 PM PDT 24
Peak memory 225560 kb
Host smart-3869d3a6-692e-40dd-a426-0c33f43467f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334288739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.334288739
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.2703785037
Short name T463
Test name
Test status
Simulation time 900017444 ps
CPU time 5.7 seconds
Started Jul 19 05:01:38 PM PDT 24
Finished Jul 19 05:01:45 PM PDT 24
Peak memory 222572 kb
Host smart-22a4ed37-19a1-4cd7-a6dc-d3e8e23f2a12
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703785037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.2703785037
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2220315308
Short name T657
Test name
Test status
Simulation time 1201806059 ps
CPU time 4.46 seconds
Started Jul 19 05:01:38 PM PDT 24
Finished Jul 19 05:01:44 PM PDT 24
Peak memory 217120 kb
Host smart-389fff68-0c08-4822-b0cb-4faf47015a36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220315308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2220315308
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2935903174
Short name T23
Test name
Test status
Simulation time 1534424883 ps
CPU time 74.02 seconds
Started Jul 19 05:01:38 PM PDT 24
Finished Jul 19 05:02:54 PM PDT 24
Peak memory 283172 kb
Host smart-38a0d3aa-fc7c-4402-843a-a2859c64a4d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935903174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2935903174
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3334737577
Short name T781
Test name
Test status
Simulation time 2369330968 ps
CPU time 13.59 seconds
Started Jul 19 05:01:35 PM PDT 24
Finished Jul 19 05:01:51 PM PDT 24
Peak memory 250684 kb
Host smart-67d52853-8ed1-43df-89c2-fef5cb0f235e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334737577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3334737577
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3931012732
Short name T499
Test name
Test status
Simulation time 50947607 ps
CPU time 1.7 seconds
Started Jul 19 05:01:38 PM PDT 24
Finished Jul 19 05:01:41 PM PDT 24
Peak memory 217732 kb
Host smart-c8a8e6f5-7ee4-46bc-a7c0-40f4384f110b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931012732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3931012732
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.3462525387
Short name T466
Test name
Test status
Simulation time 2073454442 ps
CPU time 13.07 seconds
Started Jul 19 05:01:36 PM PDT 24
Finished Jul 19 05:01:51 PM PDT 24
Peak memory 217752 kb
Host smart-0670529e-e0d8-4dd8-bebb-3c87786b266f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462525387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.3462525387
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1301485307
Short name T64
Test name
Test status
Simulation time 2783174287 ps
CPU time 14.84 seconds
Started Jul 19 05:01:35 PM PDT 24
Finished Jul 19 05:01:52 PM PDT 24
Peak memory 225468 kb
Host smart-1a8cfe7a-02d5-4fa4-b77d-14153c341a3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301485307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
1301485307
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3481074555
Short name T384
Test name
Test status
Simulation time 435885829 ps
CPU time 15.3 seconds
Started Jul 19 05:01:33 PM PDT 24
Finished Jul 19 05:01:50 PM PDT 24
Peak memory 217876 kb
Host smart-3054cb59-672c-4ca5-9798-f6b26f538905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481074555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3481074555
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.372000959
Short name T370
Test name
Test status
Simulation time 53190158 ps
CPU time 3.09 seconds
Started Jul 19 05:01:39 PM PDT 24
Finished Jul 19 05:01:44 PM PDT 24
Peak memory 214192 kb
Host smart-8a213fca-93bb-4a8b-8c60-5a8bbf6dd30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372000959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.372000959
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1041241385
Short name T843
Test name
Test status
Simulation time 548885325 ps
CPU time 31.69 seconds
Started Jul 19 05:01:39 PM PDT 24
Finished Jul 19 05:02:12 PM PDT 24
Peak memory 250512 kb
Host smart-c8da1fe9-1bae-43a7-821e-8a9468cfa06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041241385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1041241385
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3915879065
Short name T311
Test name
Test status
Simulation time 63165632 ps
CPU time 2.99 seconds
Started Jul 19 05:01:31 PM PDT 24
Finished Jul 19 05:01:35 PM PDT 24
Peak memory 222428 kb
Host smart-fa3e18c7-54ec-4e71-bcea-f5814b268d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915879065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3915879065
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2529023548
Short name T450
Test name
Test status
Simulation time 10351402828 ps
CPU time 82.98 seconds
Started Jul 19 05:01:37 PM PDT 24
Finished Jul 19 05:03:02 PM PDT 24
Peak memory 250568 kb
Host smart-cd19c8d4-cde4-47bc-97a7-e8f98b112ffb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529023548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2529023548
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3226417769
Short name T706
Test name
Test status
Simulation time 56278917 ps
CPU time 0.8 seconds
Started Jul 19 05:01:33 PM PDT 24
Finished Jul 19 05:01:35 PM PDT 24
Peak memory 208348 kb
Host smart-80d875df-54bf-4805-86ab-77a8bff61e15
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226417769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3226417769
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3616337662
Short name T587
Test name
Test status
Simulation time 53129035 ps
CPU time 0.87 seconds
Started Jul 19 05:01:42 PM PDT 24
Finished Jul 19 05:01:46 PM PDT 24
Peak memory 208352 kb
Host smart-f3147efc-ca91-4ea6-bb78-a8f41b56a55c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616337662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3616337662
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2559619310
Short name T171
Test name
Test status
Simulation time 783668690 ps
CPU time 9.89 seconds
Started Jul 19 05:01:43 PM PDT 24
Finished Jul 19 05:01:55 PM PDT 24
Peak memory 217820 kb
Host smart-2e68313b-070d-4181-bdd4-5f4d152573e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559619310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2559619310
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3252862451
Short name T608
Test name
Test status
Simulation time 245805477 ps
CPU time 3.96 seconds
Started Jul 19 05:01:42 PM PDT 24
Finished Jul 19 05:01:48 PM PDT 24
Peak memory 217120 kb
Host smart-224590b9-904d-4b18-b9e4-dc8d01da9def
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252862451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3252862451
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.677654597
Short name T255
Test name
Test status
Simulation time 7517386309 ps
CPU time 70.1 seconds
Started Jul 19 05:01:43 PM PDT 24
Finished Jul 19 05:02:57 PM PDT 24
Peak memory 218440 kb
Host smart-85b284d8-acd4-4f32-a6c2-cb6ffa0de45e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677654597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er
rors.677654597
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1370851002
Short name T331
Test name
Test status
Simulation time 878871886 ps
CPU time 3.37 seconds
Started Jul 19 05:01:42 PM PDT 24
Finished Jul 19 05:01:48 PM PDT 24
Peak memory 222568 kb
Host smart-bc5bb426-dd04-4b66-ae54-01d72dcb52ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370851002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.1370851002
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.438402049
Short name T73
Test name
Test status
Simulation time 1184617555 ps
CPU time 1.88 seconds
Started Jul 19 05:01:43 PM PDT 24
Finished Jul 19 05:01:48 PM PDT 24
Peak memory 217096 kb
Host smart-2bba80e6-9775-4ba6-a72e-761124452160
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438402049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
438402049
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1789165726
Short name T267
Test name
Test status
Simulation time 7624813287 ps
CPU time 45.85 seconds
Started Jul 19 05:01:44 PM PDT 24
Finished Jul 19 05:02:33 PM PDT 24
Peak memory 266892 kb
Host smart-362e4665-4a0d-4e05-9cfe-a00e79705c74
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789165726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1789165726
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.565761088
Short name T426
Test name
Test status
Simulation time 671076757 ps
CPU time 10.89 seconds
Started Jul 19 05:01:43 PM PDT 24
Finished Jul 19 05:01:58 PM PDT 24
Peak memory 221652 kb
Host smart-7ddc8011-af6f-4301-b1e7-0b11439a54e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565761088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.565761088
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3309840073
Short name T16
Test name
Test status
Simulation time 190064519 ps
CPU time 3.93 seconds
Started Jul 19 05:01:42 PM PDT 24
Finished Jul 19 05:01:48 PM PDT 24
Peak memory 221992 kb
Host smart-d87417e9-eb57-4f20-8c3e-f75137c6951c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309840073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3309840073
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1199477458
Short name T633
Test name
Test status
Simulation time 309029807 ps
CPU time 10.42 seconds
Started Jul 19 05:01:43 PM PDT 24
Finished Jul 19 05:01:57 PM PDT 24
Peak memory 218456 kb
Host smart-37e0bf65-86d9-442c-a1aa-7d7d15192865
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199477458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1199477458
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3390576731
Short name T712
Test name
Test status
Simulation time 1261016544 ps
CPU time 10.78 seconds
Started Jul 19 05:01:42 PM PDT 24
Finished Jul 19 05:01:56 PM PDT 24
Peak memory 225536 kb
Host smart-6ec595cb-bebd-45a1-8003-115e753d67fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390576731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3390576731
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.950705246
Short name T48
Test name
Test status
Simulation time 1117022240 ps
CPU time 8.92 seconds
Started Jul 19 05:01:46 PM PDT 24
Finished Jul 19 05:01:58 PM PDT 24
Peak memory 225532 kb
Host smart-7cecd221-2190-4682-bbf5-8d00366df26f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950705246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.950705246
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.379727019
Short name T304
Test name
Test status
Simulation time 294827096 ps
CPU time 7.33 seconds
Started Jul 19 05:01:43 PM PDT 24
Finished Jul 19 05:01:54 PM PDT 24
Peak memory 217788 kb
Host smart-f2e122d6-a734-4838-8d70-5c1dc2e69248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379727019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.379727019
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3091104614
Short name T794
Test name
Test status
Simulation time 47595351 ps
CPU time 2.84 seconds
Started Jul 19 05:01:34 PM PDT 24
Finished Jul 19 05:01:39 PM PDT 24
Peak memory 217164 kb
Host smart-1cd20d02-e9b3-4dee-a946-054ca2831af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091104614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3091104614
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2565384910
Short name T401
Test name
Test status
Simulation time 817237151 ps
CPU time 19.92 seconds
Started Jul 19 05:01:36 PM PDT 24
Finished Jul 19 05:01:58 PM PDT 24
Peak memory 250556 kb
Host smart-02787d67-a229-4a9c-9487-43f20d531d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565384910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2565384910
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2142061932
Short name T546
Test name
Test status
Simulation time 232805876 ps
CPU time 2.73 seconds
Started Jul 19 05:01:35 PM PDT 24
Finished Jul 19 05:01:39 PM PDT 24
Peak memory 221948 kb
Host smart-dbb163b4-bee2-4f9c-a03f-ba14c7187fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142061932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2142061932
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3665016939
Short name T103
Test name
Test status
Simulation time 4134447996 ps
CPU time 63.82 seconds
Started Jul 19 05:01:42 PM PDT 24
Finished Jul 19 05:02:48 PM PDT 24
Peak memory 267396 kb
Host smart-daf642d2-2bfa-4aef-a472-f61bf1707cc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665016939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3665016939
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2803058954
Short name T66
Test name
Test status
Simulation time 19009725 ps
CPU time 1.19 seconds
Started Jul 19 05:01:37 PM PDT 24
Finished Jul 19 05:01:41 PM PDT 24
Peak memory 217388 kb
Host smart-20f38b17-8c90-4fba-aed9-e27f6f35ed73
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803058954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2803058954
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.153709857
Short name T14
Test name
Test status
Simulation time 14814851 ps
CPU time 0.85 seconds
Started Jul 19 05:01:44 PM PDT 24
Finished Jul 19 05:01:48 PM PDT 24
Peak memory 208332 kb
Host smart-99386288-b6f4-404b-aa1a-ff6e506a7cbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153709857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.153709857
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.639362122
Short name T151
Test name
Test status
Simulation time 291073313 ps
CPU time 13.79 seconds
Started Jul 19 05:01:43 PM PDT 24
Finished Jul 19 05:02:01 PM PDT 24
Peak memory 217768 kb
Host smart-5258bd38-ecbc-455a-97cb-f1cec5f80c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639362122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.639362122
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.886181561
Short name T9
Test name
Test status
Simulation time 224709532 ps
CPU time 3.96 seconds
Started Jul 19 05:01:44 PM PDT 24
Finished Jul 19 05:01:51 PM PDT 24
Peak memory 216796 kb
Host smart-a75938ac-4024-441c-9e3b-e69c3133a048
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886181561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.886181561
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2565267286
Short name T243
Test name
Test status
Simulation time 39439059876 ps
CPU time 115.85 seconds
Started Jul 19 05:01:42 PM PDT 24
Finished Jul 19 05:03:41 PM PDT 24
Peak memory 219548 kb
Host smart-8954a70b-c868-41bf-a979-367c9c176e12
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565267286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2565267286
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3070814866
Short name T21
Test name
Test status
Simulation time 451667988 ps
CPU time 2.66 seconds
Started Jul 19 05:01:42 PM PDT 24
Finished Jul 19 05:01:46 PM PDT 24
Peak memory 221376 kb
Host smart-562ff210-b00a-4480-bfaf-b618a7f37f8f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070814866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3070814866
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.571751678
Short name T759
Test name
Test status
Simulation time 306697547 ps
CPU time 4.83 seconds
Started Jul 19 05:01:43 PM PDT 24
Finished Jul 19 05:01:51 PM PDT 24
Peak memory 217140 kb
Host smart-05374586-708a-4661-8c01-c9cc94b3006a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571751678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
571751678
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.409843794
Short name T454
Test name
Test status
Simulation time 3029063805 ps
CPU time 60.34 seconds
Started Jul 19 05:01:42 PM PDT 24
Finished Jul 19 05:02:46 PM PDT 24
Peak memory 250544 kb
Host smart-49892d97-f202-44ee-a45e-71c41c866d32
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409843794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.409843794
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2030856116
Short name T436
Test name
Test status
Simulation time 2204990372 ps
CPU time 17.93 seconds
Started Jul 19 05:01:42 PM PDT 24
Finished Jul 19 05:02:03 PM PDT 24
Peak memory 246204 kb
Host smart-5af7f7be-de12-4b00-9084-d96032b566b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030856116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2030856116
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.530117709
Short name T174
Test name
Test status
Simulation time 264591324 ps
CPU time 3.6 seconds
Started Jul 19 05:01:44 PM PDT 24
Finished Jul 19 05:01:51 PM PDT 24
Peak memory 222252 kb
Host smart-1fb4497d-4812-4dd2-8d43-0ce2c53d9788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530117709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.530117709
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.839676336
Short name T301
Test name
Test status
Simulation time 1814555040 ps
CPU time 14.76 seconds
Started Jul 19 05:01:42 PM PDT 24
Finished Jul 19 05:01:59 PM PDT 24
Peak memory 219488 kb
Host smart-e8071d57-2620-441d-8e6c-16d91b99e1a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839676336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.839676336
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1507052405
Short name T392
Test name
Test status
Simulation time 1958969665 ps
CPU time 17.01 seconds
Started Jul 19 05:01:45 PM PDT 24
Finished Jul 19 05:02:05 PM PDT 24
Peak memory 217744 kb
Host smart-90751bfa-160b-4e07-bd4e-221a5a5e0045
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507052405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1507052405
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1795717094
Short name T572
Test name
Test status
Simulation time 282048638 ps
CPU time 8.26 seconds
Started Jul 19 05:01:43 PM PDT 24
Finished Jul 19 05:01:54 PM PDT 24
Peak memory 225520 kb
Host smart-efc916ba-7b50-4d62-a7ef-9a95a7c926ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795717094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1795717094
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3874054159
Short name T182
Test name
Test status
Simulation time 530322383 ps
CPU time 18.73 seconds
Started Jul 19 05:01:43 PM PDT 24
Finished Jul 19 05:02:04 PM PDT 24
Peak memory 217880 kb
Host smart-f484bb66-3426-4fbb-a781-67256dd95f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874054159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3874054159
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1941946453
Short name T28
Test name
Test status
Simulation time 225077691 ps
CPU time 3.73 seconds
Started Jul 19 05:01:43 PM PDT 24
Finished Jul 19 05:01:50 PM PDT 24
Peak memory 217224 kb
Host smart-33336e87-6c2a-4497-aefe-15e92fb6ddee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941946453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1941946453
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3584472735
Short name T701
Test name
Test status
Simulation time 1303506593 ps
CPU time 27.8 seconds
Started Jul 19 05:01:43 PM PDT 24
Finished Jul 19 05:02:14 PM PDT 24
Peak memory 250548 kb
Host smart-8c2acf0d-3c67-4451-8a16-01413531f64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584472735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3584472735
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.768564089
Short name T830
Test name
Test status
Simulation time 72915541 ps
CPU time 7.73 seconds
Started Jul 19 05:01:41 PM PDT 24
Finished Jul 19 05:01:51 PM PDT 24
Peak memory 250692 kb
Host smart-254841fb-3e3b-4624-9766-25ea08ba1f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768564089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.768564089
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.665629523
Short name T445
Test name
Test status
Simulation time 5756476125 ps
CPU time 133.65 seconds
Started Jul 19 05:01:43 PM PDT 24
Finished Jul 19 05:04:01 PM PDT 24
Peak memory 271860 kb
Host smart-a4e9ddb1-163c-4d7c-9e34-bf1673a002c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665629523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.665629523
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3753920612
Short name T513
Test name
Test status
Simulation time 57013924 ps
CPU time 0.98 seconds
Started Jul 19 05:01:43 PM PDT 24
Finished Jul 19 05:01:48 PM PDT 24
Peak memory 212432 kb
Host smart-f4a39567-dbbd-46d7-a36e-c7ab4549d536
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753920612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.3753920612
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2230686621
Short name T310
Test name
Test status
Simulation time 31756034 ps
CPU time 0.89 seconds
Started Jul 19 05:01:51 PM PDT 24
Finished Jul 19 05:01:53 PM PDT 24
Peak memory 208332 kb
Host smart-a33c7bbb-b997-4457-babf-7e4e962fb674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230686621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2230686621
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.451956495
Short name T551
Test name
Test status
Simulation time 724306919 ps
CPU time 5.35 seconds
Started Jul 19 05:01:46 PM PDT 24
Finished Jul 19 05:01:54 PM PDT 24
Peak memory 216832 kb
Host smart-4162c51b-e9a7-4bdb-8740-3ebac525d58b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451956495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.451956495
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.66830594
Short name T10
Test name
Test status
Simulation time 1705823754 ps
CPU time 34.62 seconds
Started Jul 19 05:01:47 PM PDT 24
Finished Jul 19 05:02:24 PM PDT 24
Peak memory 217792 kb
Host smart-17aad7a9-739e-4615-a5d7-4c07cec7da9d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66830594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_err
ors.66830594
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.993884097
Short name T323
Test name
Test status
Simulation time 140659622 ps
CPU time 2.7 seconds
Started Jul 19 05:01:47 PM PDT 24
Finished Jul 19 05:01:52 PM PDT 24
Peak memory 221072 kb
Host smart-3ed61c32-40ed-4ebe-9d09-49cf77c00e87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993884097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.993884097
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.508115892
Short name T813
Test name
Test status
Simulation time 196872129 ps
CPU time 5.61 seconds
Started Jul 19 05:01:46 PM PDT 24
Finished Jul 19 05:01:54 PM PDT 24
Peak memory 217088 kb
Host smart-c10a4450-e1b2-48ff-89dd-4bc93d27c850
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508115892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke.
508115892
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1931669275
Short name T260
Test name
Test status
Simulation time 3677702229 ps
CPU time 48.8 seconds
Started Jul 19 05:01:48 PM PDT 24
Finished Jul 19 05:02:38 PM PDT 24
Peak memory 280072 kb
Host smart-992c44c0-3c5f-480e-acf1-e38f7c99cd5f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931669275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1931669275
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3870168114
Short name T634
Test name
Test status
Simulation time 3606721346 ps
CPU time 19.16 seconds
Started Jul 19 05:01:46 PM PDT 24
Finished Jul 19 05:02:08 PM PDT 24
Peak memory 217788 kb
Host smart-9a0f011e-83b3-46bf-9575-fcef6a0b23c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870168114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.3870168114
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.4106409531
Short name T402
Test name
Test status
Simulation time 128448374 ps
CPU time 2.73 seconds
Started Jul 19 05:01:45 PM PDT 24
Finished Jul 19 05:01:51 PM PDT 24
Peak memory 217828 kb
Host smart-c8d8e5be-05e7-404b-a965-4e28dfa845b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106409531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.4106409531
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.749532594
Short name T580
Test name
Test status
Simulation time 305235407 ps
CPU time 14.53 seconds
Started Jul 19 05:01:46 PM PDT 24
Finished Jul 19 05:02:03 PM PDT 24
Peak memory 218464 kb
Host smart-434c7b53-3811-49ae-a0de-1c22c35a17f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749532594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.749532594
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3196039604
Short name T376
Test name
Test status
Simulation time 354658452 ps
CPU time 10.57 seconds
Started Jul 19 05:01:53 PM PDT 24
Finished Jul 19 05:02:06 PM PDT 24
Peak memory 225516 kb
Host smart-b1a042c7-f247-4030-8090-9ad293d980ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196039604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3196039604
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.861504553
Short name T177
Test name
Test status
Simulation time 1265910871 ps
CPU time 8.86 seconds
Started Jul 19 05:01:52 PM PDT 24
Finished Jul 19 05:02:02 PM PDT 24
Peak memory 225492 kb
Host smart-2df2734e-ac56-41bf-8388-0fafbd5ba7bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861504553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.861504553
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2327908401
Short name T448
Test name
Test status
Simulation time 229274768 ps
CPU time 9.01 seconds
Started Jul 19 05:01:43 PM PDT 24
Finished Jul 19 05:01:55 PM PDT 24
Peak memory 224896 kb
Host smart-0296cb97-6e9a-4ff9-8a17-49a7f062c5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327908401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2327908401
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2201851066
Short name T618
Test name
Test status
Simulation time 34004660 ps
CPU time 1.7 seconds
Started Jul 19 05:01:45 PM PDT 24
Finished Jul 19 05:01:50 PM PDT 24
Peak memory 217244 kb
Host smart-c1725184-1c75-4c4e-9d66-b399b92eb7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201851066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2201851066
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1181485999
Short name T422
Test name
Test status
Simulation time 278897769 ps
CPU time 25.74 seconds
Started Jul 19 05:01:45 PM PDT 24
Finished Jul 19 05:02:14 PM PDT 24
Peak memory 250524 kb
Host smart-d1deeac5-aa70-4d1a-84e8-323d1e240794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181485999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1181485999
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.288805981
Short name T399
Test name
Test status
Simulation time 106250394 ps
CPU time 7.45 seconds
Started Jul 19 05:01:44 PM PDT 24
Finished Jul 19 05:01:55 PM PDT 24
Peak memory 246380 kb
Host smart-580d4ba3-ecb6-46e9-90c2-ef1275821c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288805981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.288805981
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1111479253
Short name T471
Test name
Test status
Simulation time 15548946429 ps
CPU time 137.82 seconds
Started Jul 19 05:01:53 PM PDT 24
Finished Jul 19 05:04:13 PM PDT 24
Peak memory 290880 kb
Host smart-7ba8b6d3-a4c1-44fe-bf1c-9b9e8db23ac0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111479253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1111479253
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2787560332
Short name T521
Test name
Test status
Simulation time 15533776 ps
CPU time 1.16 seconds
Started Jul 19 05:01:45 PM PDT 24
Finished Jul 19 05:01:50 PM PDT 24
Peak memory 211476 kb
Host smart-0c19a70d-a319-4ea6-a1b6-5dddce2b14a0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787560332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2787560332
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.188362574
Short name T644
Test name
Test status
Simulation time 17682671 ps
CPU time 1.13 seconds
Started Jul 19 05:00:31 PM PDT 24
Finished Jul 19 05:00:36 PM PDT 24
Peak memory 208372 kb
Host smart-eb7f9277-1ac7-4bac-b379-d09377026a1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188362574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.188362574
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.987005736
Short name T771
Test name
Test status
Simulation time 422739569 ps
CPU time 10.02 seconds
Started Jul 19 05:00:17 PM PDT 24
Finished Jul 19 05:00:30 PM PDT 24
Peak memory 217816 kb
Host smart-fecf2da2-4928-4bd0-a2e7-5101a3484aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987005736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.987005736
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1810971015
Short name T393
Test name
Test status
Simulation time 3394981128 ps
CPU time 20.48 seconds
Started Jul 19 05:00:27 PM PDT 24
Finished Jul 19 05:00:52 PM PDT 24
Peak memory 217276 kb
Host smart-70d101a2-4be3-4650-a05b-7f4deebe2a93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810971015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1810971015
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2640578917
Short name T724
Test name
Test status
Simulation time 4094871457 ps
CPU time 32.53 seconds
Started Jul 19 05:00:26 PM PDT 24
Finished Jul 19 05:01:00 PM PDT 24
Peak memory 218392 kb
Host smart-145c413b-7326-4e18-a3ca-d303a1d47619
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640578917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2640578917
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2732336927
Short name T858
Test name
Test status
Simulation time 1345504350 ps
CPU time 15.02 seconds
Started Jul 19 05:00:28 PM PDT 24
Finished Jul 19 05:00:48 PM PDT 24
Peak memory 217140 kb
Host smart-768e0db5-6d0e-473d-afa0-89aa8d672605
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732336927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
732336927
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3697491956
Short name T468
Test name
Test status
Simulation time 1588772829 ps
CPU time 5.38 seconds
Started Jul 19 05:00:37 PM PDT 24
Finished Jul 19 05:00:46 PM PDT 24
Peak memory 222628 kb
Host smart-b0547f8e-adbe-4c4e-8853-15588f189f51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697491956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3697491956
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3201297365
Short name T508
Test name
Test status
Simulation time 1177798505 ps
CPU time 34.49 seconds
Started Jul 19 05:00:26 PM PDT 24
Finished Jul 19 05:01:02 PM PDT 24
Peak memory 217140 kb
Host smart-0b1439db-0376-4815-8be5-f440e3c67c6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201297365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.3201297365
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2951392147
Short name T89
Test name
Test status
Simulation time 3601852884 ps
CPU time 13.47 seconds
Started Jul 19 05:00:17 PM PDT 24
Finished Jul 19 05:00:34 PM PDT 24
Peak memory 217264 kb
Host smart-cd5d5dc0-a702-44ae-af93-d4e297a8d45f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951392147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2951392147
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2881661939
Short name T365
Test name
Test status
Simulation time 7734905382 ps
CPU time 49.27 seconds
Started Jul 19 05:00:17 PM PDT 24
Finished Jul 19 05:01:09 PM PDT 24
Peak memory 274548 kb
Host smart-d92da762-3749-4195-8bf7-2ce7a687d7a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881661939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2881661939
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3915187213
Short name T414
Test name
Test status
Simulation time 763955846 ps
CPU time 15.72 seconds
Started Jul 19 05:00:18 PM PDT 24
Finished Jul 19 05:00:36 PM PDT 24
Peak memory 248932 kb
Host smart-b05661cc-cdcf-4074-b09d-ec7145a3c832
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915187213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3915187213
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.848260677
Short name T652
Test name
Test status
Simulation time 37278801 ps
CPU time 2.27 seconds
Started Jul 19 05:00:16 PM PDT 24
Finished Jul 19 05:00:22 PM PDT 24
Peak memory 217804 kb
Host smart-031e73a5-d536-47dc-b100-59983222def9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848260677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.848260677
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2452183506
Short name T165
Test name
Test status
Simulation time 340610849 ps
CPU time 7.06 seconds
Started Jul 19 05:00:18 PM PDT 24
Finished Jul 19 05:00:28 PM PDT 24
Peak memory 221788 kb
Host smart-b06ff525-ae9e-4259-b836-121c46608572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452183506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2452183506
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2400772398
Short name T94
Test name
Test status
Simulation time 409427159 ps
CPU time 25.55 seconds
Started Jul 19 05:00:27 PM PDT 24
Finished Jul 19 05:00:57 PM PDT 24
Peak memory 284072 kb
Host smart-750321db-cd4e-4781-bc69-52b9421828bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400772398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2400772398
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2255668352
Short name T239
Test name
Test status
Simulation time 706966668 ps
CPU time 7.92 seconds
Started Jul 19 05:00:27 PM PDT 24
Finished Jul 19 05:00:40 PM PDT 24
Peak memory 217740 kb
Host smart-640d529a-aec3-43a6-9c50-131259d81df4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255668352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2255668352
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2667552907
Short name T688
Test name
Test status
Simulation time 239095560 ps
CPU time 9.51 seconds
Started Jul 19 05:00:27 PM PDT 24
Finished Jul 19 05:00:40 PM PDT 24
Peak memory 225524 kb
Host smart-47921b58-9d3f-493c-89fe-d62badfb825a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667552907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
667552907
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1819032128
Short name T725
Test name
Test status
Simulation time 1451366451 ps
CPU time 10.76 seconds
Started Jul 19 05:00:18 PM PDT 24
Finished Jul 19 05:00:32 PM PDT 24
Peak memory 217820 kb
Host smart-8d82698d-4fb0-4558-91de-564e7a9622f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819032128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1819032128
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2619237314
Short name T627
Test name
Test status
Simulation time 403648435 ps
CPU time 3.8 seconds
Started Jul 19 05:00:15 PM PDT 24
Finished Jul 19 05:00:21 PM PDT 24
Peak memory 217200 kb
Host smart-1dcdd65b-8bf7-47de-9102-ae15b22b6f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619237314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2619237314
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.282472704
Short name T290
Test name
Test status
Simulation time 206744483 ps
CPU time 23.56 seconds
Started Jul 19 05:00:18 PM PDT 24
Finished Jul 19 05:00:44 PM PDT 24
Peak memory 250516 kb
Host smart-7ae8234c-c656-419d-aff0-904bff4e7841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282472704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.282472704
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1747422517
Short name T514
Test name
Test status
Simulation time 201479665 ps
CPU time 7.12 seconds
Started Jul 19 05:00:16 PM PDT 24
Finished Jul 19 05:00:26 PM PDT 24
Peak memory 250552 kb
Host smart-8c660c18-005d-41de-bea0-52a7ebd071a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747422517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1747422517
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2049837984
Short name T460
Test name
Test status
Simulation time 5947146108 ps
CPU time 62.64 seconds
Started Jul 19 05:00:25 PM PDT 24
Finished Jul 19 05:01:29 PM PDT 24
Peak memory 250452 kb
Host smart-ceebdc5c-4c09-44af-b112-65514a366bad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049837984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2049837984
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3003670489
Short name T105
Test name
Test status
Simulation time 22685131133 ps
CPU time 435.46 seconds
Started Jul 19 05:00:37 PM PDT 24
Finished Jul 19 05:07:56 PM PDT 24
Peak memory 258612 kb
Host smart-222eaef5-d264-4ed7-a93c-31cdf1006f5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3003670489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.3003670489
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1820402233
Short name T261
Test name
Test status
Simulation time 39926282 ps
CPU time 0.88 seconds
Started Jul 19 05:00:20 PM PDT 24
Finished Jul 19 05:00:23 PM PDT 24
Peak memory 208436 kb
Host smart-0261272a-d428-4ff8-aade-cd6bb7685b3a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820402233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1820402233
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1721886442
Short name T642
Test name
Test status
Simulation time 25389118 ps
CPU time 0.89 seconds
Started Jul 19 05:01:52 PM PDT 24
Finished Jul 19 05:01:54 PM PDT 24
Peak memory 208164 kb
Host smart-a3066e93-c67d-47f6-91dd-f3a0593221f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721886442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1721886442
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.658353514
Short name T412
Test name
Test status
Simulation time 329291094 ps
CPU time 16.69 seconds
Started Jul 19 05:01:59 PM PDT 24
Finished Jul 19 05:02:18 PM PDT 24
Peak memory 217808 kb
Host smart-62b8d0aa-3bbf-4386-845b-c71217fa1f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658353514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.658353514
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2469516565
Short name T183
Test name
Test status
Simulation time 681461945 ps
CPU time 7.89 seconds
Started Jul 19 05:01:52 PM PDT 24
Finished Jul 19 05:02:01 PM PDT 24
Peak memory 216972 kb
Host smart-e1337dd6-cd7d-43dc-ad22-514f0bae9fd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469516565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2469516565
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1033218150
Short name T434
Test name
Test status
Simulation time 27844101 ps
CPU time 1.69 seconds
Started Jul 19 05:01:51 PM PDT 24
Finished Jul 19 05:01:55 PM PDT 24
Peak memory 217752 kb
Host smart-ffdca6ae-c4cb-48d3-bd5d-69ee28a55d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033218150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1033218150
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.148212452
Short name T742
Test name
Test status
Simulation time 1217914011 ps
CPU time 26.54 seconds
Started Jul 19 05:01:50 PM PDT 24
Finished Jul 19 05:02:18 PM PDT 24
Peak memory 218568 kb
Host smart-fa8c95d7-6d96-45a1-9cfa-66fc9b7f8a1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148212452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.148212452
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1615371768
Short name T620
Test name
Test status
Simulation time 2397146341 ps
CPU time 14.68 seconds
Started Jul 19 05:01:50 PM PDT 24
Finished Jul 19 05:02:06 PM PDT 24
Peak memory 217852 kb
Host smart-59c10591-52ae-4ad5-8f27-3b06ccdb44ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615371768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.1615371768
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3744292225
Short name T525
Test name
Test status
Simulation time 235073532 ps
CPU time 5.97 seconds
Started Jul 19 05:01:58 PM PDT 24
Finished Jul 19 05:02:06 PM PDT 24
Peak memory 224576 kb
Host smart-248b8ff7-49c7-443f-bad8-bb164ebcca0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744292225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3744292225
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.488033130
Short name T764
Test name
Test status
Simulation time 354106180 ps
CPU time 13.14 seconds
Started Jul 19 05:01:59 PM PDT 24
Finished Jul 19 05:02:14 PM PDT 24
Peak memory 217868 kb
Host smart-065afde2-3d85-4bb2-af90-3ba7455df05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488033130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.488033130
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.979069793
Short name T838
Test name
Test status
Simulation time 94583909 ps
CPU time 2.57 seconds
Started Jul 19 05:01:51 PM PDT 24
Finished Jul 19 05:01:55 PM PDT 24
Peak memory 214060 kb
Host smart-af7c103e-6baa-4bc5-902c-8a4238f5fb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979069793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.979069793
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.547069984
Short name T98
Test name
Test status
Simulation time 2896118779 ps
CPU time 24.51 seconds
Started Jul 19 05:01:51 PM PDT 24
Finished Jul 19 05:02:17 PM PDT 24
Peak memory 250600 kb
Host smart-27de1ac6-faac-4005-9540-2bfa59ce1102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547069984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.547069984
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1222304525
Short name T231
Test name
Test status
Simulation time 90568697 ps
CPU time 4.37 seconds
Started Jul 19 05:01:50 PM PDT 24
Finished Jul 19 05:01:56 PM PDT 24
Peak memory 222196 kb
Host smart-8267f710-23d0-425f-b104-1f96ce649e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222304525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1222304525
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.4035217092
Short name T757
Test name
Test status
Simulation time 4203579467 ps
CPU time 12.88 seconds
Started Jul 19 05:01:50 PM PDT 24
Finished Jul 19 05:02:05 PM PDT 24
Peak memory 225620 kb
Host smart-bc84630d-7b4f-49b7-8a2c-a6f664e2cee5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035217092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.4035217092
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2489807198
Short name T719
Test name
Test status
Simulation time 22022084 ps
CPU time 0.96 seconds
Started Jul 19 05:01:52 PM PDT 24
Finished Jul 19 05:01:54 PM PDT 24
Peak memory 208384 kb
Host smart-c1ded72f-8a20-4af7-8654-792bbb893a3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489807198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2489807198
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1390157318
Short name T798
Test name
Test status
Simulation time 414790565 ps
CPU time 12.1 seconds
Started Jul 19 05:01:54 PM PDT 24
Finished Jul 19 05:02:08 PM PDT 24
Peak memory 217820 kb
Host smart-29c412a2-5668-4f24-84bf-60de7e9b5ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390157318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1390157318
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1857793487
Short name T599
Test name
Test status
Simulation time 3832585362 ps
CPU time 21.51 seconds
Started Jul 19 05:01:53 PM PDT 24
Finished Jul 19 05:02:17 PM PDT 24
Peak memory 217200 kb
Host smart-f5568eba-afe9-43fa-9cc1-e63bc3c1c56b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857793487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1857793487
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.4163008112
Short name T560
Test name
Test status
Simulation time 22193512 ps
CPU time 1.85 seconds
Started Jul 19 05:01:50 PM PDT 24
Finished Jul 19 05:01:53 PM PDT 24
Peak memory 217812 kb
Host smart-ad2ca987-8a28-48c0-b8e0-dae0e5dd0a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163008112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.4163008112
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2273283554
Short name T734
Test name
Test status
Simulation time 558682895 ps
CPU time 20.89 seconds
Started Jul 19 05:01:59 PM PDT 24
Finished Jul 19 05:02:22 PM PDT 24
Peak memory 219480 kb
Host smart-19c02607-f219-4784-97f0-d773b8fbe4f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273283554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2273283554
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.4232897279
Short name T653
Test name
Test status
Simulation time 1276615049 ps
CPU time 13.39 seconds
Started Jul 19 05:01:50 PM PDT 24
Finished Jul 19 05:02:05 PM PDT 24
Peak memory 217792 kb
Host smart-0929333d-b504-4a75-8e4a-c16013703e3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232897279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.4232897279
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1259078077
Short name T354
Test name
Test status
Simulation time 432136797 ps
CPU time 11.02 seconds
Started Jul 19 05:01:51 PM PDT 24
Finished Jul 19 05:02:04 PM PDT 24
Peak memory 225480 kb
Host smart-876e45fa-a345-4309-bb66-106e5246a70f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259078077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1259078077
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.400235762
Short name T784
Test name
Test status
Simulation time 212249447 ps
CPU time 9.45 seconds
Started Jul 19 05:01:52 PM PDT 24
Finished Jul 19 05:02:02 PM PDT 24
Peak memory 217884 kb
Host smart-b15e62c1-46f9-49f6-8d96-4501776041e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400235762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.400235762
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.2669250027
Short name T528
Test name
Test status
Simulation time 348274280 ps
CPU time 6.56 seconds
Started Jul 19 05:01:50 PM PDT 24
Finished Jul 19 05:01:58 PM PDT 24
Peak memory 217224 kb
Host smart-8f635916-35d9-45cd-aa02-6f81f2d7830f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669250027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2669250027
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1029729198
Short name T372
Test name
Test status
Simulation time 188730587 ps
CPU time 22.2 seconds
Started Jul 19 05:01:53 PM PDT 24
Finished Jul 19 05:02:17 PM PDT 24
Peak memory 250444 kb
Host smart-92fe653c-795c-419c-a760-6729c108c272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029729198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1029729198
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1387334852
Short name T227
Test name
Test status
Simulation time 74217182 ps
CPU time 6.1 seconds
Started Jul 19 05:01:53 PM PDT 24
Finished Jul 19 05:02:00 PM PDT 24
Peak memory 246040 kb
Host smart-0146aec7-a60c-401f-88f0-66215029aa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387334852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1387334852
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1965503479
Short name T88
Test name
Test status
Simulation time 821725105 ps
CPU time 34.29 seconds
Started Jul 19 05:01:49 PM PDT 24
Finished Jul 19 05:02:25 PM PDT 24
Peak memory 250556 kb
Host smart-44ffe720-f953-45bb-9c48-cf38c14553bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965503479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1965503479
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.304220783
Short name T113
Test name
Test status
Simulation time 108535486005 ps
CPU time 360.4 seconds
Started Jul 19 05:01:54 PM PDT 24
Finished Jul 19 05:07:56 PM PDT 24
Peak memory 372600 kb
Host smart-35ee78f6-14fd-409c-a279-0bf795e8f269
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=304220783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.304220783
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.4148581481
Short name T780
Test name
Test status
Simulation time 41244913 ps
CPU time 0.91 seconds
Started Jul 19 05:01:52 PM PDT 24
Finished Jul 19 05:01:54 PM PDT 24
Peak memory 208448 kb
Host smart-8b0e8346-2c62-497e-94f3-8b6feb14b625
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148581481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.4148581481
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.177290613
Short name T505
Test name
Test status
Simulation time 392488294 ps
CPU time 1.34 seconds
Started Jul 19 05:01:58 PM PDT 24
Finished Jul 19 05:02:01 PM PDT 24
Peak memory 208616 kb
Host smart-6e3ff1ee-b78b-46bd-a3f1-bd55f44efac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177290613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.177290613
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.239014281
Short name T18
Test name
Test status
Simulation time 1492168840 ps
CPU time 12.6 seconds
Started Jul 19 05:01:59 PM PDT 24
Finished Jul 19 05:02:13 PM PDT 24
Peak memory 217948 kb
Host smart-d9ea0063-f56d-4af9-ade2-ad457c1f3f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239014281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.239014281
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2279818211
Short name T822
Test name
Test status
Simulation time 3254374482 ps
CPU time 7.86 seconds
Started Jul 19 05:01:57 PM PDT 24
Finished Jul 19 05:02:06 PM PDT 24
Peak memory 217304 kb
Host smart-93235179-60cf-45c6-a4cf-47e990c1a428
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279818211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.2279818211
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3814888307
Short name T816
Test name
Test status
Simulation time 114690938 ps
CPU time 2.18 seconds
Started Jul 19 05:01:51 PM PDT 24
Finished Jul 19 05:01:54 PM PDT 24
Peak memory 221784 kb
Host smart-90e0ab05-f5d4-4161-8745-ea34d0edb004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814888307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3814888307
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.3481360729
Short name T625
Test name
Test status
Simulation time 2380011451 ps
CPU time 15.31 seconds
Started Jul 19 05:02:08 PM PDT 24
Finished Jul 19 05:02:24 PM PDT 24
Peak memory 218468 kb
Host smart-57d7e3b5-5e79-4c06-bf64-0dc8047bd105
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481360729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3481360729
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1287907931
Short name T228
Test name
Test status
Simulation time 1994422423 ps
CPU time 14.61 seconds
Started Jul 19 05:01:59 PM PDT 24
Finished Jul 19 05:02:16 PM PDT 24
Peak memory 217728 kb
Host smart-867b4948-b6d8-426f-96b0-9dcc5a19e2b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287907931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1287907931
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2642819117
Short name T104
Test name
Test status
Simulation time 629393837 ps
CPU time 12.01 seconds
Started Jul 19 05:01:58 PM PDT 24
Finished Jul 19 05:02:12 PM PDT 24
Peak memory 225536 kb
Host smart-2ca0a979-04ee-4e75-bc61-fea11db28308
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642819117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2642819117
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.201829694
Short name T663
Test name
Test status
Simulation time 396087298 ps
CPU time 8.4 seconds
Started Jul 19 05:02:00 PM PDT 24
Finished Jul 19 05:02:10 PM PDT 24
Peak memory 217868 kb
Host smart-787917a8-b5be-49eb-b10b-af5fcc859c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201829694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.201829694
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2660503070
Short name T615
Test name
Test status
Simulation time 934457436 ps
CPU time 3.38 seconds
Started Jul 19 05:01:50 PM PDT 24
Finished Jul 19 05:01:54 PM PDT 24
Peak memory 217220 kb
Host smart-61ff4491-867b-4805-98cf-c9ee279c0eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660503070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2660503070
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.2080492926
Short name T162
Test name
Test status
Simulation time 385728187 ps
CPU time 26.67 seconds
Started Jul 19 05:01:53 PM PDT 24
Finished Jul 19 05:02:20 PM PDT 24
Peak memory 250372 kb
Host smart-24f3256c-fb3a-482e-9129-f6c15fb765b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080492926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2080492926
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1502105610
Short name T556
Test name
Test status
Simulation time 63307668 ps
CPU time 6.05 seconds
Started Jul 19 05:01:53 PM PDT 24
Finished Jul 19 05:02:01 PM PDT 24
Peak memory 242348 kb
Host smart-47fba04f-9691-4a6f-9add-0d97571b651e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502105610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1502105610
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1630523068
Short name T707
Test name
Test status
Simulation time 2671711343 ps
CPU time 38.69 seconds
Started Jul 19 05:02:08 PM PDT 24
Finished Jul 19 05:02:48 PM PDT 24
Peak memory 250560 kb
Host smart-aabfb9cb-bb8e-4009-baad-2a18e10f0be6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630523068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1630523068
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.72466112
Short name T178
Test name
Test status
Simulation time 21216495 ps
CPU time 1 seconds
Started Jul 19 05:01:59 PM PDT 24
Finished Jul 19 05:02:02 PM PDT 24
Peak memory 211472 kb
Host smart-d5027923-44ae-4f7c-9425-748d6ffa8e37
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72466112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctr
l_volatile_unlock_smoke.72466112
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1026542231
Short name T248
Test name
Test status
Simulation time 16133384 ps
CPU time 0.87 seconds
Started Jul 19 05:01:57 PM PDT 24
Finished Jul 19 05:01:59 PM PDT 24
Peak memory 208344 kb
Host smart-4b5813c0-fce8-44d2-93ef-6111506d3168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026542231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1026542231
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.4092902533
Short name T603
Test name
Test status
Simulation time 2894549358 ps
CPU time 10.65 seconds
Started Jul 19 05:01:58 PM PDT 24
Finished Jul 19 05:02:11 PM PDT 24
Peak memory 218464 kb
Host smart-b106f545-284b-46c8-9ef7-2b6adde8ec99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092902533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.4092902533
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3660280736
Short name T441
Test name
Test status
Simulation time 1618566106 ps
CPU time 4 seconds
Started Jul 19 05:01:59 PM PDT 24
Finished Jul 19 05:02:04 PM PDT 24
Peak memory 216644 kb
Host smart-cc6835e0-fe06-485a-bd84-62537c7ee973
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660280736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3660280736
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2099045008
Short name T258
Test name
Test status
Simulation time 59486292 ps
CPU time 1.44 seconds
Started Jul 19 05:01:58 PM PDT 24
Finished Jul 19 05:02:01 PM PDT 24
Peak memory 217816 kb
Host smart-0bce4cc0-caf9-4452-9365-d0805f59eadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099045008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2099045008
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.521660984
Short name T246
Test name
Test status
Simulation time 257380211 ps
CPU time 9.4 seconds
Started Jul 19 05:02:08 PM PDT 24
Finished Jul 19 05:02:19 PM PDT 24
Peak memory 218376 kb
Host smart-61f1e02f-166a-408b-8031-0918872c2e15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521660984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.521660984
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.525155149
Short name T364
Test name
Test status
Simulation time 482446997 ps
CPU time 13.99 seconds
Started Jul 19 05:02:00 PM PDT 24
Finished Jul 19 05:02:16 PM PDT 24
Peak memory 217804 kb
Host smart-ae8473d4-fbf5-4aae-8f35-668ef11b03c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525155149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.525155149
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1670476874
Short name T408
Test name
Test status
Simulation time 998030323 ps
CPU time 10.1 seconds
Started Jul 19 05:02:00 PM PDT 24
Finished Jul 19 05:02:12 PM PDT 24
Peak memory 225536 kb
Host smart-091a5025-c7c4-407a-ad6c-24eb602540c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670476874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1670476874
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.623413759
Short name T456
Test name
Test status
Simulation time 1585137553 ps
CPU time 12.02 seconds
Started Jul 19 05:02:08 PM PDT 24
Finished Jul 19 05:02:21 PM PDT 24
Peak memory 225000 kb
Host smart-cf676acb-6d70-483d-8a73-26d840cd5de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623413759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.623413759
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.297534366
Short name T77
Test name
Test status
Simulation time 25535826 ps
CPU time 1.98 seconds
Started Jul 19 05:01:58 PM PDT 24
Finished Jul 19 05:02:01 PM PDT 24
Peak memory 213620 kb
Host smart-1ff3a2b5-7d8e-4dd5-9964-c2738c4e2bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297534366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.297534366
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.4090586231
Short name T610
Test name
Test status
Simulation time 435800987 ps
CPU time 20.37 seconds
Started Jul 19 05:01:56 PM PDT 24
Finished Jul 19 05:02:17 PM PDT 24
Peak memory 250520 kb
Host smart-fcfd9786-ae38-457c-943a-26db565bfff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090586231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.4090586231
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2466623300
Short name T854
Test name
Test status
Simulation time 358836245 ps
CPU time 7.42 seconds
Started Jul 19 05:02:01 PM PDT 24
Finished Jul 19 05:02:10 PM PDT 24
Peak memory 246212 kb
Host smart-e4f35b91-8736-4bbb-a9eb-72589c64248c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466623300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2466623300
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2280444355
Short name T790
Test name
Test status
Simulation time 28103085563 ps
CPU time 152.81 seconds
Started Jul 19 05:01:59 PM PDT 24
Finished Jul 19 05:04:34 PM PDT 24
Peak memory 283124 kb
Host smart-02817b6c-06d2-4da1-8c08-b4a61d63c5dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280444355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2280444355
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2978425805
Short name T241
Test name
Test status
Simulation time 31908181 ps
CPU time 0.77 seconds
Started Jul 19 05:02:07 PM PDT 24
Finished Jul 19 05:02:09 PM PDT 24
Peak memory 208440 kb
Host smart-9d9af3f3-ce2a-44ea-8966-2de64c599025
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978425805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2978425805
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.4043623019
Short name T565
Test name
Test status
Simulation time 41044852 ps
CPU time 0.97 seconds
Started Jul 19 05:02:09 PM PDT 24
Finished Jul 19 05:02:11 PM PDT 24
Peak memory 208412 kb
Host smart-5a107ff7-bd91-4526-99e9-6ddacc9c69a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043623019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.4043623019
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3272842878
Short name T504
Test name
Test status
Simulation time 2192176384 ps
CPU time 5.69 seconds
Started Jul 19 05:02:08 PM PDT 24
Finished Jul 19 05:02:15 PM PDT 24
Peak memory 216796 kb
Host smart-d232bbb7-9b17-4210-8a24-68deebf9826a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272842878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3272842878
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3274325557
Short name T357
Test name
Test status
Simulation time 72734632 ps
CPU time 3.94 seconds
Started Jul 19 05:02:09 PM PDT 24
Finished Jul 19 05:02:14 PM PDT 24
Peak memory 222344 kb
Host smart-a796a694-5eb5-40a4-a187-343fd5d5d820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274325557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3274325557
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2332654803
Short name T440
Test name
Test status
Simulation time 212095960 ps
CPU time 11.05 seconds
Started Jul 19 05:02:09 PM PDT 24
Finished Jul 19 05:02:22 PM PDT 24
Peak memory 217908 kb
Host smart-36bd69ab-ea03-41a8-8c22-9f19fc68e18b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332654803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2332654803
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2182121542
Short name T786
Test name
Test status
Simulation time 5877248432 ps
CPU time 18.79 seconds
Started Jul 19 05:02:08 PM PDT 24
Finished Jul 19 05:02:27 PM PDT 24
Peak memory 217872 kb
Host smart-4df66dcd-65c3-4552-8248-62e0054e3439
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182121542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2182121542
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.372540644
Short name T479
Test name
Test status
Simulation time 1311976355 ps
CPU time 12.98 seconds
Started Jul 19 05:02:06 PM PDT 24
Finished Jul 19 05:02:20 PM PDT 24
Peak memory 217776 kb
Host smart-7a65ca2d-429f-4685-93df-a133f2bc95a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372540644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.372540644
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1515900443
Short name T691
Test name
Test status
Simulation time 953270246 ps
CPU time 6.8 seconds
Started Jul 19 05:02:08 PM PDT 24
Finished Jul 19 05:02:17 PM PDT 24
Peak memory 224400 kb
Host smart-73797578-dd50-49ee-99cb-94fc1c097e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515900443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1515900443
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1940892016
Short name T85
Test name
Test status
Simulation time 48622228 ps
CPU time 2.24 seconds
Started Jul 19 05:02:07 PM PDT 24
Finished Jul 19 05:02:10 PM PDT 24
Peak memory 217180 kb
Host smart-e7ec8c4a-8499-4a00-b238-876c900657ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940892016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1940892016
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1719729766
Short name T350
Test name
Test status
Simulation time 1046174514 ps
CPU time 20.91 seconds
Started Jul 19 05:02:00 PM PDT 24
Finished Jul 19 05:02:23 PM PDT 24
Peak memory 250560 kb
Host smart-b6676e6f-8be9-4ed3-b4e6-ca5e9ebdb977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719729766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1719729766
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1282640352
Short name T57
Test name
Test status
Simulation time 554517486 ps
CPU time 3.52 seconds
Started Jul 19 05:02:08 PM PDT 24
Finished Jul 19 05:02:13 PM PDT 24
Peak memory 222072 kb
Host smart-84d1a8e5-bfa4-4bd8-92fc-a0a67e46da3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282640352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1282640352
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2904676603
Short name T566
Test name
Test status
Simulation time 11783246843 ps
CPU time 228.9 seconds
Started Jul 19 05:02:08 PM PDT 24
Finished Jul 19 05:05:59 PM PDT 24
Peak memory 275008 kb
Host smart-13ce16b7-163e-47fc-bf96-d77b9fc2cf63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904676603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2904676603
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.202978360
Short name T567
Test name
Test status
Simulation time 25373601 ps
CPU time 0.91 seconds
Started Jul 19 05:02:08 PM PDT 24
Finished Jul 19 05:02:11 PM PDT 24
Peak memory 211368 kb
Host smart-eb99ca91-174b-47d8-b9f3-e41e84c8916f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202978360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct
rl_volatile_unlock_smoke.202978360
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2031895572
Short name T449
Test name
Test status
Simulation time 40068360 ps
CPU time 0.91 seconds
Started Jul 19 05:02:18 PM PDT 24
Finished Jul 19 05:02:22 PM PDT 24
Peak memory 208384 kb
Host smart-61657f9b-2525-40df-acbc-46b0c0562a80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031895572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2031895572
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.4145260203
Short name T51
Test name
Test status
Simulation time 1366210175 ps
CPU time 15.09 seconds
Started Jul 19 05:02:07 PM PDT 24
Finished Jul 19 05:02:23 PM PDT 24
Peak memory 217880 kb
Host smart-cb6bebba-e970-4cfd-801f-71b2c5882693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145260203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.4145260203
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3682847851
Short name T37
Test name
Test status
Simulation time 3823413906 ps
CPU time 5.65 seconds
Started Jul 19 05:02:08 PM PDT 24
Finished Jul 19 05:02:15 PM PDT 24
Peak memory 217260 kb
Host smart-74d18096-da45-47b7-a1c7-d424903720b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682847851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3682847851
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1863616218
Short name T431
Test name
Test status
Simulation time 92766525 ps
CPU time 2 seconds
Started Jul 19 05:02:08 PM PDT 24
Finished Jul 19 05:02:12 PM PDT 24
Peak memory 217804 kb
Host smart-83766f5a-cbcb-4f50-82ea-36c6cce0bcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863616218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1863616218
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.3652405192
Short name T102
Test name
Test status
Simulation time 386548963 ps
CPU time 16.33 seconds
Started Jul 19 05:02:08 PM PDT 24
Finished Jul 19 05:02:26 PM PDT 24
Peak memory 218468 kb
Host smart-90ec9f22-f45b-4b15-aa79-4dbdd8773e68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652405192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3652405192
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1464385719
Short name T421
Test name
Test status
Simulation time 432204464 ps
CPU time 11.92 seconds
Started Jul 19 05:02:18 PM PDT 24
Finished Jul 19 05:02:33 PM PDT 24
Peak memory 217808 kb
Host smart-b5b858e7-7a94-4423-8f96-0941d1127f38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464385719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1464385719
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.895374264
Short name T321
Test name
Test status
Simulation time 358141584 ps
CPU time 13.37 seconds
Started Jul 19 05:02:19 PM PDT 24
Finished Jul 19 05:02:35 PM PDT 24
Peak memory 225672 kb
Host smart-93372585-b011-4839-a45e-93b42c8a7432
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895374264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.895374264
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1726438464
Short name T4
Test name
Test status
Simulation time 1468262417 ps
CPU time 12.27 seconds
Started Jul 19 05:02:09 PM PDT 24
Finished Jul 19 05:02:22 PM PDT 24
Peak memory 217876 kb
Host smart-74c7d529-836c-4c56-b1ec-478e66359034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726438464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1726438464
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3303394183
Short name T686
Test name
Test status
Simulation time 230501629 ps
CPU time 2.79 seconds
Started Jul 19 05:02:06 PM PDT 24
Finished Jul 19 05:02:10 PM PDT 24
Peak memory 214392 kb
Host smart-47927bcb-a275-49b7-8e1c-a1c9bc5bd023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303394183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3303394183
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.308124523
Short name T676
Test name
Test status
Simulation time 370400381 ps
CPU time 24.52 seconds
Started Jul 19 05:02:27 PM PDT 24
Finished Jul 19 05:02:53 PM PDT 24
Peak memory 250548 kb
Host smart-594cdb83-6125-4a46-8881-3e31222bbcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308124523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.308124523
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.192158828
Short name T851
Test name
Test status
Simulation time 256324421 ps
CPU time 7.48 seconds
Started Jul 19 05:02:07 PM PDT 24
Finished Jul 19 05:02:15 PM PDT 24
Peak memory 250116 kb
Host smart-7ed92303-f45f-495e-ac4a-7f3e1b905a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192158828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.192158828
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.428313229
Short name T82
Test name
Test status
Simulation time 10710799914 ps
CPU time 185.11 seconds
Started Jul 19 05:02:17 PM PDT 24
Finished Jul 19 05:05:25 PM PDT 24
Peak memory 253028 kb
Host smart-38818304-fa26-4dd3-b6be-abd9d2531988
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428313229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.428313229
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.687131598
Short name T353
Test name
Test status
Simulation time 369372111664 ps
CPU time 569.52 seconds
Started Jul 19 05:02:17 PM PDT 24
Finished Jul 19 05:11:49 PM PDT 24
Peak memory 299848 kb
Host smart-53f162a1-883e-44ed-b8b7-0d42e1ef78b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=687131598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.687131598
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2745782972
Short name T458
Test name
Test status
Simulation time 65762860 ps
CPU time 1 seconds
Started Jul 19 05:02:06 PM PDT 24
Finished Jul 19 05:02:08 PM PDT 24
Peak memory 212408 kb
Host smart-2ee294fb-11c5-479d-868c-20aff918f986
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745782972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2745782972
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1130159958
Short name T845
Test name
Test status
Simulation time 38105910 ps
CPU time 0.94 seconds
Started Jul 19 05:02:17 PM PDT 24
Finished Jul 19 05:02:21 PM PDT 24
Peak memory 208424 kb
Host smart-d3f6f7cd-c20d-4420-a284-79d216f8c8cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130159958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1130159958
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.994282971
Short name T256
Test name
Test status
Simulation time 1040132979 ps
CPU time 13.09 seconds
Started Jul 19 05:02:14 PM PDT 24
Finished Jul 19 05:02:28 PM PDT 24
Peak memory 225552 kb
Host smart-85f9b0df-62d3-4c82-8938-d8b4aa484f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994282971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.994282971
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1968063917
Short name T674
Test name
Test status
Simulation time 1555979590 ps
CPU time 10.47 seconds
Started Jul 19 05:02:17 PM PDT 24
Finished Jul 19 05:02:31 PM PDT 24
Peak memory 216892 kb
Host smart-17c21035-2f78-4da9-8962-4a0f196bcc33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968063917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1968063917
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1913665531
Short name T744
Test name
Test status
Simulation time 98666371 ps
CPU time 4.27 seconds
Started Jul 19 05:02:16 PM PDT 24
Finished Jul 19 05:02:22 PM PDT 24
Peak memory 217796 kb
Host smart-d0f70d02-33bc-447f-9799-684f2cc28157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913665531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1913665531
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3569512049
Short name T319
Test name
Test status
Simulation time 324155382 ps
CPU time 13.87 seconds
Started Jul 19 05:02:16 PM PDT 24
Finished Jul 19 05:02:32 PM PDT 24
Peak memory 217776 kb
Host smart-dc57d7df-3e95-42c1-9c0b-70d16a15fdfa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569512049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3569512049
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.847522760
Short name T804
Test name
Test status
Simulation time 383238039 ps
CPU time 13.54 seconds
Started Jul 19 05:02:16 PM PDT 24
Finished Jul 19 05:02:32 PM PDT 24
Peak memory 225532 kb
Host smart-108fdb38-00e5-4871-944f-204a9b8c6ef4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847522760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.847522760
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.4209931636
Short name T58
Test name
Test status
Simulation time 1312399136 ps
CPU time 13.73 seconds
Started Jul 19 05:02:16 PM PDT 24
Finished Jul 19 05:02:32 PM PDT 24
Peak memory 225560 kb
Host smart-e005b803-4a46-4fe3-9553-2fe9295a95dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209931636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.4209931636
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.760605265
Short name T789
Test name
Test status
Simulation time 26454761 ps
CPU time 1.71 seconds
Started Jul 19 05:02:15 PM PDT 24
Finished Jul 19 05:02:19 PM PDT 24
Peak memory 217228 kb
Host smart-6b51adfe-24cc-4e79-8737-0c0d93fd04fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760605265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.760605265
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2576592530
Short name T681
Test name
Test status
Simulation time 962077729 ps
CPU time 31.38 seconds
Started Jul 19 05:02:17 PM PDT 24
Finished Jul 19 05:02:52 PM PDT 24
Peak memory 250556 kb
Host smart-3392ce25-a297-49e2-ad81-c0c4d83ca5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576592530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2576592530
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2065920582
Short name T655
Test name
Test status
Simulation time 186866662 ps
CPU time 6.69 seconds
Started Jul 19 05:02:18 PM PDT 24
Finished Jul 19 05:02:28 PM PDT 24
Peak memory 246788 kb
Host smart-e8f1982e-710c-4c73-9474-a2892dc760e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065920582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2065920582
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.17489212
Short name T190
Test name
Test status
Simulation time 19750618095 ps
CPU time 370.07 seconds
Started Jul 19 05:02:14 PM PDT 24
Finished Jul 19 05:08:25 PM PDT 24
Peak memory 283248 kb
Host smart-b6249a98-93f0-43d8-87fc-6dad09df7828
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17489212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.lc_ctrl_stress_all.17489212
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1760439874
Short name T602
Test name
Test status
Simulation time 11141822 ps
CPU time 0.76 seconds
Started Jul 19 05:02:17 PM PDT 24
Finished Jul 19 05:02:20 PM PDT 24
Peak memory 207620 kb
Host smart-db571109-cd11-4a23-970f-e4f5994e9f83
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760439874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1760439874
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.194916677
Short name T334
Test name
Test status
Simulation time 12118810 ps
CPU time 0.9 seconds
Started Jul 19 05:02:17 PM PDT 24
Finished Jul 19 05:02:21 PM PDT 24
Peak memory 208176 kb
Host smart-d14ab20f-4780-431a-8725-a3bd7d4f2623
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194916677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.194916677
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.160761620
Short name T452
Test name
Test status
Simulation time 220000288 ps
CPU time 9.21 seconds
Started Jul 19 05:02:19 PM PDT 24
Finished Jul 19 05:02:31 PM PDT 24
Peak memory 217840 kb
Host smart-cb3ad9bd-b3da-4163-8109-fa1d3c04bcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160761620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.160761620
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.131755285
Short name T515
Test name
Test status
Simulation time 94671998 ps
CPU time 1.95 seconds
Started Jul 19 05:02:16 PM PDT 24
Finished Jul 19 05:02:19 PM PDT 24
Peak memory 216604 kb
Host smart-1620a394-5914-434e-83eb-6c8c163ea0ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131755285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.131755285
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1922529096
Short name T168
Test name
Test status
Simulation time 167227861 ps
CPU time 2.65 seconds
Started Jul 19 05:02:18 PM PDT 24
Finished Jul 19 05:02:24 PM PDT 24
Peak memory 221776 kb
Host smart-0c820aef-1624-4b1b-9cef-1d864c937948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922529096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1922529096
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1320114526
Short name T605
Test name
Test status
Simulation time 2957373776 ps
CPU time 28 seconds
Started Jul 19 05:02:17 PM PDT 24
Finished Jul 19 05:02:47 PM PDT 24
Peak memory 218388 kb
Host smart-5500f63d-ec47-47be-adfa-95cd9d996aff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320114526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1320114526
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.4280792740
Short name T746
Test name
Test status
Simulation time 755405415 ps
CPU time 9.18 seconds
Started Jul 19 05:02:17 PM PDT 24
Finished Jul 19 05:02:28 PM PDT 24
Peak memory 225560 kb
Host smart-73b7ff26-245f-4047-86fd-93a543294d33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280792740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
4280792740
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2537488245
Short name T788
Test name
Test status
Simulation time 1293765001 ps
CPU time 6.47 seconds
Started Jul 19 05:02:18 PM PDT 24
Finished Jul 19 05:02:27 PM PDT 24
Peak memory 217876 kb
Host smart-97182212-53d3-4165-aefc-f88a9fe07ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537488245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2537488245
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.685716050
Short name T683
Test name
Test status
Simulation time 68707876 ps
CPU time 1.98 seconds
Started Jul 19 05:02:16 PM PDT 24
Finished Jul 19 05:02:19 PM PDT 24
Peak memory 217144 kb
Host smart-b2c5c21f-3596-470a-aa08-6611049b08cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685716050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.685716050
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1619280094
Short name T710
Test name
Test status
Simulation time 254858956 ps
CPU time 26.39 seconds
Started Jul 19 05:02:16 PM PDT 24
Finished Jul 19 05:02:45 PM PDT 24
Peak memory 250616 kb
Host smart-7c0be842-36e4-432f-9e4a-5cb3969318a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619280094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1619280094
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.2617517616
Short name T163
Test name
Test status
Simulation time 557697154 ps
CPU time 7.51 seconds
Started Jul 19 05:02:19 PM PDT 24
Finished Jul 19 05:02:29 PM PDT 24
Peak memory 246272 kb
Host smart-fb1bda7c-82d7-4d6f-9e2d-5ff8c0085ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617517616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2617517616
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1888064953
Short name T700
Test name
Test status
Simulation time 14488090614 ps
CPU time 99.9 seconds
Started Jul 19 05:02:17 PM PDT 24
Finished Jul 19 05:04:01 PM PDT 24
Peak memory 283328 kb
Host smart-ba40515e-b8ff-41c2-bf0c-9a38f80b1a61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888064953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1888064953
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.133542063
Short name T169
Test name
Test status
Simulation time 21475951593 ps
CPU time 766.05 seconds
Started Jul 19 05:02:17 PM PDT 24
Finished Jul 19 05:15:06 PM PDT 24
Peak memory 299992 kb
Host smart-77cc9df8-cc98-4795-ac3e-74c95671d23d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=133542063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.133542063
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3163239642
Short name T332
Test name
Test status
Simulation time 40385463 ps
CPU time 0.94 seconds
Started Jul 19 05:02:19 PM PDT 24
Finished Jul 19 05:02:22 PM PDT 24
Peak memory 208776 kb
Host smart-824b58fe-168e-470e-b118-77ac31e4a92f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163239642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3163239642
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1197298174
Short name T526
Test name
Test status
Simulation time 12721796 ps
CPU time 0.84 seconds
Started Jul 19 05:02:25 PM PDT 24
Finished Jul 19 05:02:28 PM PDT 24
Peak memory 208184 kb
Host smart-2ce8f707-fdf1-433b-8bb4-e36fac907a82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197298174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1197298174
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3158636089
Short name T751
Test name
Test status
Simulation time 1447113056 ps
CPU time 15.08 seconds
Started Jul 19 05:02:23 PM PDT 24
Finished Jul 19 05:02:40 PM PDT 24
Peak memory 217816 kb
Host smart-8ce3486f-0fea-4914-ac25-68128981f359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158636089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3158636089
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.158623392
Short name T677
Test name
Test status
Simulation time 193225193 ps
CPU time 2.04 seconds
Started Jul 19 05:02:22 PM PDT 24
Finished Jul 19 05:02:26 PM PDT 24
Peak memory 216552 kb
Host smart-b8f73437-b429-4ad2-a46b-eb92ae51bd1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158623392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.158623392
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.4236342420
Short name T611
Test name
Test status
Simulation time 154211408 ps
CPU time 3.13 seconds
Started Jul 19 05:02:26 PM PDT 24
Finished Jul 19 05:02:30 PM PDT 24
Peak memory 217808 kb
Host smart-77c323cd-05a8-4632-b56f-2802b7068d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236342420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.4236342420
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.2910381646
Short name T512
Test name
Test status
Simulation time 255325086 ps
CPU time 8.8 seconds
Started Jul 19 05:02:25 PM PDT 24
Finished Jul 19 05:02:35 PM PDT 24
Peak memory 225596 kb
Host smart-3171cb40-1fcf-4655-9e3c-d117939548b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910381646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2910381646
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2775369173
Short name T761
Test name
Test status
Simulation time 464571182 ps
CPU time 17.35 seconds
Started Jul 19 05:02:21 PM PDT 24
Finished Jul 19 05:02:40 PM PDT 24
Peak memory 217776 kb
Host smart-af2c906e-b108-41fa-9330-e3777b0223fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775369173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2775369173
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3728509983
Short name T236
Test name
Test status
Simulation time 256938596 ps
CPU time 10.03 seconds
Started Jul 19 05:02:26 PM PDT 24
Finished Jul 19 05:02:37 PM PDT 24
Peak memory 225504 kb
Host smart-82259233-90f6-4a08-b5f9-8cc29f2819d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728509983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3728509983
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.509569160
Short name T300
Test name
Test status
Simulation time 223433116 ps
CPU time 6.07 seconds
Started Jul 19 05:02:25 PM PDT 24
Finished Jul 19 05:02:33 PM PDT 24
Peak memory 224308 kb
Host smart-1751e3ac-3aa5-4fca-a5c1-6e77d1b3aed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509569160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.509569160
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3989287196
Short name T648
Test name
Test status
Simulation time 429774763 ps
CPU time 2.67 seconds
Started Jul 19 05:02:15 PM PDT 24
Finished Jul 19 05:02:19 PM PDT 24
Peak memory 217128 kb
Host smart-201c1802-bedb-4e84-b0d5-e9b4bffd308a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989287196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3989287196
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2366713581
Short name T366
Test name
Test status
Simulation time 301919804 ps
CPU time 31.43 seconds
Started Jul 19 05:02:15 PM PDT 24
Finished Jul 19 05:02:48 PM PDT 24
Peak memory 250552 kb
Host smart-312529eb-ea82-40b2-bdf7-623b5ef43c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366713581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2366713581
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1740740174
Short name T539
Test name
Test status
Simulation time 65436479 ps
CPU time 8.18 seconds
Started Jul 19 05:02:16 PM PDT 24
Finished Jul 19 05:02:26 PM PDT 24
Peak memory 250548 kb
Host smart-80790f48-4a9f-43bd-8bb2-eab799f1d419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740740174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1740740174
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.919590728
Short name T191
Test name
Test status
Simulation time 15137373522 ps
CPU time 99.45 seconds
Started Jul 19 05:02:22 PM PDT 24
Finished Jul 19 05:04:03 PM PDT 24
Peak memory 269388 kb
Host smart-423b3a94-f404-463b-8077-0b2596444645
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919590728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.919590728
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.2042934646
Short name T148
Test name
Test status
Simulation time 23059992972 ps
CPU time 794.18 seconds
Started Jul 19 05:02:22 PM PDT 24
Finished Jul 19 05:15:38 PM PDT 24
Peak memory 388924 kb
Host smart-aa6e3b01-7f38-441b-9cca-3bf0eab864ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2042934646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.2042934646
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.4024938207
Short name T338
Test name
Test status
Simulation time 15681411 ps
CPU time 1.07 seconds
Started Jul 19 05:02:16 PM PDT 24
Finished Jul 19 05:02:20 PM PDT 24
Peak memory 211456 kb
Host smart-24e7f83a-b46f-48b7-b607-77ebfb79b3ce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024938207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.4024938207
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3624011724
Short name T432
Test name
Test status
Simulation time 130705292 ps
CPU time 1.21 seconds
Started Jul 19 05:02:22 PM PDT 24
Finished Jul 19 05:02:25 PM PDT 24
Peak memory 208424 kb
Host smart-39bf3356-90ef-4242-9ed5-8650a72a913c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624011724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3624011724
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2799545421
Short name T305
Test name
Test status
Simulation time 1307789583 ps
CPU time 11.19 seconds
Started Jul 19 05:02:22 PM PDT 24
Finished Jul 19 05:02:34 PM PDT 24
Peak memory 217784 kb
Host smart-aba8f315-8c41-4eae-a2d6-128c66bb8e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799545421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2799545421
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1619893766
Short name T337
Test name
Test status
Simulation time 646895509 ps
CPU time 9.06 seconds
Started Jul 19 05:02:24 PM PDT 24
Finished Jul 19 05:02:35 PM PDT 24
Peak memory 217144 kb
Host smart-43fe1512-e63f-4b0d-96c1-265c541072d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619893766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1619893766
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1536317724
Short name T100
Test name
Test status
Simulation time 55955122 ps
CPU time 3.43 seconds
Started Jul 19 05:02:25 PM PDT 24
Finished Jul 19 05:02:30 PM PDT 24
Peak memory 217784 kb
Host smart-9688d49b-ad79-4eec-8eb4-e2d13fa42f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536317724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1536317724
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3645980128
Short name T779
Test name
Test status
Simulation time 7020213808 ps
CPU time 12.32 seconds
Started Jul 19 05:02:25 PM PDT 24
Finished Jul 19 05:02:39 PM PDT 24
Peak memory 218044 kb
Host smart-3ea36ae8-039b-4896-b85f-77de33876e2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645980128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3645980128
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2863193435
Short name T476
Test name
Test status
Simulation time 310523296 ps
CPU time 9.65 seconds
Started Jul 19 05:02:24 PM PDT 24
Finished Jul 19 05:02:35 PM PDT 24
Peak memory 225536 kb
Host smart-7c5b9881-90fd-4bb8-b64a-b2a934332ac7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863193435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2863193435
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.225016190
Short name T837
Test name
Test status
Simulation time 634370295 ps
CPU time 11.69 seconds
Started Jul 19 05:02:25 PM PDT 24
Finished Jul 19 05:02:38 PM PDT 24
Peak memory 225536 kb
Host smart-1160e236-a95f-4918-9bd8-cbf29558f96f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225016190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.225016190
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.986313722
Short name T645
Test name
Test status
Simulation time 325171411 ps
CPU time 6.36 seconds
Started Jul 19 05:02:24 PM PDT 24
Finished Jul 19 05:02:32 PM PDT 24
Peak memory 217820 kb
Host smart-9391f146-4a33-433c-86f1-0e730b25be6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986313722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.986313722
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.4260490137
Short name T342
Test name
Test status
Simulation time 68763176 ps
CPU time 3.02 seconds
Started Jul 19 05:02:23 PM PDT 24
Finished Jul 19 05:02:28 PM PDT 24
Peak memory 214412 kb
Host smart-980a14a8-e0f5-4cc2-bfeb-f96b49174236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260490137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.4260490137
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.134186217
Short name T623
Test name
Test status
Simulation time 345205207 ps
CPU time 31.73 seconds
Started Jul 19 05:02:22 PM PDT 24
Finished Jul 19 05:02:55 PM PDT 24
Peak memory 250500 kb
Host smart-f529d90d-1ba4-4c61-9d79-a88efe7474b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134186217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.134186217
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.221324024
Short name T828
Test name
Test status
Simulation time 86591612 ps
CPU time 8.77 seconds
Started Jul 19 05:02:25 PM PDT 24
Finished Jul 19 05:02:35 PM PDT 24
Peak memory 250520 kb
Host smart-673dd951-ee80-4409-a812-d57f63e8a320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221324024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.221324024
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.860762855
Short name T672
Test name
Test status
Simulation time 160512304374 ps
CPU time 809.19 seconds
Started Jul 19 05:02:26 PM PDT 24
Finished Jul 19 05:15:57 PM PDT 24
Peak memory 283368 kb
Host smart-76fb4deb-65d3-4fbf-993f-6187a485e590
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860762855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.860762855
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3248791997
Short name T716
Test name
Test status
Simulation time 25984295 ps
CPU time 0.95 seconds
Started Jul 19 05:02:24 PM PDT 24
Finished Jul 19 05:02:26 PM PDT 24
Peak memory 211428 kb
Host smart-a2d12448-3d0a-44c6-9c15-b6ad17004695
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248791997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3248791997
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2602142789
Short name T577
Test name
Test status
Simulation time 28149540 ps
CPU time 0.8 seconds
Started Jul 19 05:00:26 PM PDT 24
Finished Jul 19 05:00:29 PM PDT 24
Peak memory 208676 kb
Host smart-47242245-25b5-4628-867f-981f10d817fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602142789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2602142789
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1492577295
Short name T675
Test name
Test status
Simulation time 456532559 ps
CPU time 18.82 seconds
Started Jul 19 05:00:26 PM PDT 24
Finished Jul 19 05:00:47 PM PDT 24
Peak memory 217836 kb
Host smart-0a51ddc2-f033-4a38-822c-ad22b4d6e387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492577295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1492577295
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.53950512
Short name T36
Test name
Test status
Simulation time 2237437000 ps
CPU time 8.46 seconds
Started Jul 19 05:00:27 PM PDT 24
Finished Jul 19 05:00:40 PM PDT 24
Peak memory 217072 kb
Host smart-c4a3a660-7937-44e4-b2cb-5e3b70f197e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53950512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.53950512
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1820341193
Short name T635
Test name
Test status
Simulation time 3692113958 ps
CPU time 102.16 seconds
Started Jul 19 05:00:30 PM PDT 24
Finished Jul 19 05:02:17 PM PDT 24
Peak memory 218464 kb
Host smart-89607488-889b-4663-a18b-ee7d6f75d079
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820341193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1820341193
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3984543101
Short name T326
Test name
Test status
Simulation time 1404711618 ps
CPU time 7.24 seconds
Started Jul 19 05:00:27 PM PDT 24
Finished Jul 19 05:00:38 PM PDT 24
Peak memory 217212 kb
Host smart-97c1d7e1-0783-4a15-ae9f-f34ef61fb19c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984543101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
984543101
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1313057149
Short name T382
Test name
Test status
Simulation time 371702835 ps
CPU time 12.05 seconds
Started Jul 19 05:00:28 PM PDT 24
Finished Jul 19 05:00:44 PM PDT 24
Peak memory 222908 kb
Host smart-51c97fec-8af7-454d-8e6b-19bbacdb03ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313057149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1313057149
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3760853962
Short name T766
Test name
Test status
Simulation time 1414485084 ps
CPU time 20.26 seconds
Started Jul 19 05:00:27 PM PDT 24
Finished Jul 19 05:00:51 PM PDT 24
Peak memory 217176 kb
Host smart-11f1b3d2-9559-4644-8a0b-7a1deab4d273
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760853962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3760853962
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2463863327
Short name T70
Test name
Test status
Simulation time 159938037 ps
CPU time 3.44 seconds
Started Jul 19 05:00:28 PM PDT 24
Finished Jul 19 05:00:36 PM PDT 24
Peak memory 217156 kb
Host smart-8edae1f5-0729-4dbb-bd5c-508ce99770d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463863327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2463863327
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3841299248
Short name T775
Test name
Test status
Simulation time 1346802443 ps
CPU time 58.62 seconds
Started Jul 19 05:00:26 PM PDT 24
Finished Jul 19 05:01:26 PM PDT 24
Peak memory 266900 kb
Host smart-4f2959f8-d95d-4669-acee-b12f1a50bb7d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841299248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3841299248
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1694530062
Short name T167
Test name
Test status
Simulation time 2867582370 ps
CPU time 14.53 seconds
Started Jul 19 05:00:27 PM PDT 24
Finished Jul 19 05:00:45 PM PDT 24
Peak memory 250552 kb
Host smart-171d7305-6b86-486b-8594-d9ec8a0a7e18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694530062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.1694530062
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1788765221
Short name T571
Test name
Test status
Simulation time 131458688 ps
CPU time 2.23 seconds
Started Jul 19 05:00:26 PM PDT 24
Finished Jul 19 05:00:30 PM PDT 24
Peak memory 217800 kb
Host smart-6e2a7c43-9522-495c-8d21-ae000a540dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788765221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1788765221
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2377580553
Short name T367
Test name
Test status
Simulation time 416774958 ps
CPU time 15.54 seconds
Started Jul 19 05:00:27 PM PDT 24
Finished Jul 19 05:00:46 PM PDT 24
Peak memory 213664 kb
Host smart-61d9a5d3-adc9-4d3c-bbd5-d24e24af5bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377580553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2377580553
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.4048708440
Short name T413
Test name
Test status
Simulation time 178927755 ps
CPU time 9.74 seconds
Started Jul 19 05:00:28 PM PDT 24
Finished Jul 19 05:00:42 PM PDT 24
Peak memory 217808 kb
Host smart-138070dd-29ee-4ef1-858b-81c57c900705
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048708440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.4048708440
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1518666069
Short name T735
Test name
Test status
Simulation time 514118677 ps
CPU time 11.37 seconds
Started Jul 19 05:00:28 PM PDT 24
Finished Jul 19 05:00:44 PM PDT 24
Peak memory 217792 kb
Host smart-c6573363-6a2c-4087-bd63-3aef3a8c5571
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518666069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1518666069
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2573359475
Short name T280
Test name
Test status
Simulation time 814577380 ps
CPU time 7.62 seconds
Started Jul 19 05:00:25 PM PDT 24
Finished Jul 19 05:00:34 PM PDT 24
Peak memory 225476 kb
Host smart-b3e17233-d4cd-4ada-8dc3-479e19fd0882
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573359475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
573359475
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.715347320
Short name T647
Test name
Test status
Simulation time 1728376749 ps
CPU time 15.39 seconds
Started Jul 19 05:00:28 PM PDT 24
Finished Jul 19 05:00:48 PM PDT 24
Peak memory 217880 kb
Host smart-a0e4df43-9b59-47a5-b3d3-878646ac912a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715347320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.715347320
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2256530641
Short name T473
Test name
Test status
Simulation time 53119209 ps
CPU time 1.78 seconds
Started Jul 19 05:00:28 PM PDT 24
Finished Jul 19 05:00:34 PM PDT 24
Peak memory 217220 kb
Host smart-35721504-5700-45f6-a229-6fd86548299d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256530641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2256530641
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3476878069
Short name T359
Test name
Test status
Simulation time 236823207 ps
CPU time 20.2 seconds
Started Jul 19 05:00:29 PM PDT 24
Finished Jul 19 05:00:54 PM PDT 24
Peak memory 250460 kb
Host smart-cb9b09a1-fcd5-404d-96f4-9eac0a37ba96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476878069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3476878069
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3180186660
Short name T470
Test name
Test status
Simulation time 309111827 ps
CPU time 6.67 seconds
Started Jul 19 05:00:28 PM PDT 24
Finished Jul 19 05:00:39 PM PDT 24
Peak memory 250248 kb
Host smart-54bbf1dd-d641-4feb-ab94-bbb23d397fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180186660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3180186660
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3739957754
Short name T755
Test name
Test status
Simulation time 13301263222 ps
CPU time 88.16 seconds
Started Jul 19 05:00:27 PM PDT 24
Finished Jul 19 05:01:58 PM PDT 24
Peak memory 276400 kb
Host smart-07515de1-1d1a-420e-99ff-488584713972
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739957754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3739957754
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3383715152
Short name T685
Test name
Test status
Simulation time 21510776 ps
CPU time 0.91 seconds
Started Jul 19 05:00:37 PM PDT 24
Finished Jul 19 05:00:42 PM PDT 24
Peak memory 208452 kb
Host smart-7fd939e4-c5f8-4d2a-8ee9-05587aac112c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383715152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.3383715152
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.941292140
Short name T650
Test name
Test status
Simulation time 62290932 ps
CPU time 1.14 seconds
Started Jul 19 05:02:35 PM PDT 24
Finished Jul 19 05:02:38 PM PDT 24
Peak memory 208464 kb
Host smart-4412c581-6762-43b3-a792-d503d582c3f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941292140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.941292140
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2157545716
Short name T253
Test name
Test status
Simulation time 875929597 ps
CPU time 11.42 seconds
Started Jul 19 05:02:38 PM PDT 24
Finished Jul 19 05:02:51 PM PDT 24
Peak memory 217928 kb
Host smart-6d8f403f-5d2a-4527-8c61-dcece708dc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157545716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2157545716
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.315427425
Short name T31
Test name
Test status
Simulation time 622418179 ps
CPU time 1.99 seconds
Started Jul 19 05:02:35 PM PDT 24
Finished Jul 19 05:02:39 PM PDT 24
Peak memory 217192 kb
Host smart-8aec6a10-03b7-4abd-92ff-ef4193a6ef76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315427425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.315427425
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2603247926
Short name T510
Test name
Test status
Simulation time 30512854 ps
CPU time 2.34 seconds
Started Jul 19 05:02:37 PM PDT 24
Finished Jul 19 05:02:42 PM PDT 24
Peak memory 221704 kb
Host smart-1c113c2a-8f28-479e-8cc0-e59f6f713113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603247926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2603247926
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1540131347
Short name T640
Test name
Test status
Simulation time 820553135 ps
CPU time 9.18 seconds
Started Jul 19 05:02:33 PM PDT 24
Finished Jul 19 05:02:45 PM PDT 24
Peak memory 217824 kb
Host smart-a1291a43-4617-437a-8e43-189373121dc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540131347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1540131347
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3126491618
Short name T360
Test name
Test status
Simulation time 7403277948 ps
CPU time 20.63 seconds
Started Jul 19 05:02:33 PM PDT 24
Finished Jul 19 05:02:56 PM PDT 24
Peak memory 217780 kb
Host smart-62d4c242-9722-4129-a9f7-b19f4705be6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126491618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3126491618
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1588044328
Short name T588
Test name
Test status
Simulation time 494205142 ps
CPU time 12.52 seconds
Started Jul 19 05:02:34 PM PDT 24
Finished Jul 19 05:02:49 PM PDT 24
Peak memory 225180 kb
Host smart-578836c2-3ae0-4dea-9b87-f69967528b86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588044328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1588044328
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.2009077930
Short name T814
Test name
Test status
Simulation time 1120546430 ps
CPU time 7.38 seconds
Started Jul 19 05:02:34 PM PDT 24
Finished Jul 19 05:02:44 PM PDT 24
Peak memory 225588 kb
Host smart-5eb05155-1dc8-4351-ba7d-bef30af7baef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009077930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2009077930
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1433746340
Short name T90
Test name
Test status
Simulation time 34260357 ps
CPU time 1.49 seconds
Started Jul 19 05:02:22 PM PDT 24
Finished Jul 19 05:02:25 PM PDT 24
Peak memory 221268 kb
Host smart-2322f065-b0aa-4717-8129-24f85717e3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433746340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1433746340
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1804767843
Short name T749
Test name
Test status
Simulation time 161108337 ps
CPU time 16.98 seconds
Started Jul 19 05:02:24 PM PDT 24
Finished Jul 19 05:02:42 PM PDT 24
Peak memory 250548 kb
Host smart-c4b25adc-f78d-4245-a00a-49a7a516c90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804767843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1804767843
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1173110082
Short name T220
Test name
Test status
Simulation time 168265138 ps
CPU time 7.93 seconds
Started Jul 19 05:02:33 PM PDT 24
Finished Jul 19 05:02:44 PM PDT 24
Peak memory 250500 kb
Host smart-7cf0c57a-b8bf-449d-8e7b-6c5c85550fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173110082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1173110082
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1710638918
Short name T795
Test name
Test status
Simulation time 1983295361 ps
CPU time 73.01 seconds
Started Jul 19 05:02:35 PM PDT 24
Finished Jul 19 05:03:51 PM PDT 24
Peak memory 273000 kb
Host smart-3af3424d-50b6-43ba-bfe3-42666d9ed757
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710638918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1710638918
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.4285387952
Short name T11
Test name
Test status
Simulation time 178962209 ps
CPU time 1.14 seconds
Started Jul 19 05:02:34 PM PDT 24
Finished Jul 19 05:02:38 PM PDT 24
Peak memory 208408 kb
Host smart-dbeea978-8824-4fa0-bfa3-c2194fd173e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285387952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.4285387952
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1007433393
Short name T296
Test name
Test status
Simulation time 318757590 ps
CPU time 13.16 seconds
Started Jul 19 05:02:35 PM PDT 24
Finished Jul 19 05:02:51 PM PDT 24
Peak memory 217776 kb
Host smart-c980f1bf-7f9e-4698-bb9e-5faa02488e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007433393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1007433393
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.589006884
Short name T770
Test name
Test status
Simulation time 649916924 ps
CPU time 7.39 seconds
Started Jul 19 05:02:32 PM PDT 24
Finished Jul 19 05:02:42 PM PDT 24
Peak memory 216960 kb
Host smart-9d213149-64e1-4b1a-bfeb-95bc8b958316
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589006884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.589006884
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.1522687050
Short name T278
Test name
Test status
Simulation time 491831133 ps
CPU time 2.95 seconds
Started Jul 19 05:02:35 PM PDT 24
Finished Jul 19 05:02:40 PM PDT 24
Peak memory 222136 kb
Host smart-ef2f4481-88ef-467d-9516-16082b9bf7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522687050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1522687050
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.1931440475
Short name T656
Test name
Test status
Simulation time 258696252 ps
CPU time 8.42 seconds
Started Jul 19 05:02:35 PM PDT 24
Finished Jul 19 05:02:46 PM PDT 24
Peak memory 218452 kb
Host smart-efff88af-c5c0-4315-af14-d3f12895884d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931440475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1931440475
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.217757155
Short name T15
Test name
Test status
Simulation time 846327359 ps
CPU time 7.99 seconds
Started Jul 19 05:02:36 PM PDT 24
Finished Jul 19 05:02:46 PM PDT 24
Peak memory 225540 kb
Host smart-9b7cabde-7f24-4907-92f3-32905ea5e3ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217757155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di
gest.217757155
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.63013164
Short name T242
Test name
Test status
Simulation time 1328501015 ps
CPU time 8.89 seconds
Started Jul 19 05:02:37 PM PDT 24
Finished Jul 19 05:02:48 PM PDT 24
Peak memory 225492 kb
Host smart-69c07d4b-a8cb-48b5-a735-eaf8751d5ee2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63013164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.63013164
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.936596944
Short name T509
Test name
Test status
Simulation time 540796719 ps
CPU time 12.24 seconds
Started Jul 19 05:02:36 PM PDT 24
Finished Jul 19 05:02:50 PM PDT 24
Peak memory 225392 kb
Host smart-dec88236-cea3-4d75-92c4-fd91d0319b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936596944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.936596944
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3249632112
Short name T13
Test name
Test status
Simulation time 193690940 ps
CPU time 3.53 seconds
Started Jul 19 05:02:34 PM PDT 24
Finished Jul 19 05:02:40 PM PDT 24
Peak memory 217204 kb
Host smart-e304985e-add0-4b8d-8969-c38b9594cce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249632112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3249632112
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1007190036
Short name T335
Test name
Test status
Simulation time 1054532653 ps
CPU time 41.92 seconds
Started Jul 19 05:02:37 PM PDT 24
Finished Jul 19 05:03:21 PM PDT 24
Peak memory 250548 kb
Host smart-83d7b855-6b2b-4ac8-ab05-e1e3fdb6d9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007190036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1007190036
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1703239928
Short name T40
Test name
Test status
Simulation time 196673702 ps
CPU time 5.72 seconds
Started Jul 19 05:02:36 PM PDT 24
Finished Jul 19 05:02:44 PM PDT 24
Peak memory 246416 kb
Host smart-4aa546d1-b725-4658-8b4b-746cf380778f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703239928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1703239928
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2681295201
Short name T809
Test name
Test status
Simulation time 7275744760 ps
CPU time 71.59 seconds
Started Jul 19 05:02:36 PM PDT 24
Finished Jul 19 05:03:50 PM PDT 24
Peak memory 283320 kb
Host smart-7589e55d-d3c0-4e4a-b0b9-df78d0ffe02f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681295201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2681295201
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2555261814
Short name T87
Test name
Test status
Simulation time 24256445 ps
CPU time 1.08 seconds
Started Jul 19 05:02:36 PM PDT 24
Finished Jul 19 05:02:40 PM PDT 24
Peak memory 211500 kb
Host smart-d09c8aba-678a-4b78-bccc-913d85f0ca9e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555261814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2555261814
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.2402121869
Short name T576
Test name
Test status
Simulation time 66392234 ps
CPU time 1.14 seconds
Started Jul 19 05:02:43 PM PDT 24
Finished Jul 19 05:02:50 PM PDT 24
Peak memory 208512 kb
Host smart-8d84a8a9-bfc3-4564-a822-acf43ab06543
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402121869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2402121869
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.965271885
Short name T785
Test name
Test status
Simulation time 3391155697 ps
CPU time 10.92 seconds
Started Jul 19 05:02:38 PM PDT 24
Finished Jul 19 05:02:51 PM PDT 24
Peak memory 218616 kb
Host smart-f2cc96ed-7370-461a-bb5a-b3df8b9d1780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965271885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.965271885
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3577022890
Short name T793
Test name
Test status
Simulation time 783683270 ps
CPU time 10.52 seconds
Started Jul 19 05:02:33 PM PDT 24
Finished Jul 19 05:02:46 PM PDT 24
Peak memory 217200 kb
Host smart-43cb1341-646b-4c3e-adee-9331d2908d9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577022890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3577022890
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.213301435
Short name T863
Test name
Test status
Simulation time 36791598 ps
CPU time 2.02 seconds
Started Jul 19 05:02:34 PM PDT 24
Finished Jul 19 05:02:39 PM PDT 24
Peak memory 217724 kb
Host smart-6d0a4903-b0d6-4f92-8ba7-76276476a06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213301435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.213301435
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.2872456574
Short name T403
Test name
Test status
Simulation time 275781767 ps
CPU time 9.27 seconds
Started Jul 19 05:02:37 PM PDT 24
Finished Jul 19 05:02:48 PM PDT 24
Peak memory 218452 kb
Host smart-c979061b-1cbf-43ae-8521-8d36ae49671a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872456574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.2872456574
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.4113156952
Short name T549
Test name
Test status
Simulation time 691661980 ps
CPU time 17.19 seconds
Started Jul 19 05:02:36 PM PDT 24
Finished Jul 19 05:02:55 PM PDT 24
Peak memory 225612 kb
Host smart-b0e2c85f-72a0-4144-b0bb-70f8cfedc736
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113156952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.4113156952
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.4048481471
Short name T490
Test name
Test status
Simulation time 869038911 ps
CPU time 9.5 seconds
Started Jul 19 05:02:33 PM PDT 24
Finished Jul 19 05:02:45 PM PDT 24
Peak memory 225484 kb
Host smart-4108d83a-4aab-433a-852e-5916d3135de9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048481471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
4048481471
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.4184149208
Short name T517
Test name
Test status
Simulation time 262843425 ps
CPU time 6.13 seconds
Started Jul 19 05:02:34 PM PDT 24
Finished Jul 19 05:02:43 PM PDT 24
Peak memory 223696 kb
Host smart-e6bee634-6be7-4729-bcde-a629aeddf24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184149208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.4184149208
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2845261931
Short name T405
Test name
Test status
Simulation time 262844063 ps
CPU time 2.6 seconds
Started Jul 19 05:02:35 PM PDT 24
Finished Jul 19 05:02:40 PM PDT 24
Peak memory 217228 kb
Host smart-117c4d60-8d41-4d37-95e5-6d76eed97529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845261931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2845261931
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1426185477
Short name T547
Test name
Test status
Simulation time 374457843 ps
CPU time 28.85 seconds
Started Jul 19 05:02:36 PM PDT 24
Finished Jul 19 05:03:07 PM PDT 24
Peak memory 250544 kb
Host smart-7e1ed2bd-1fd1-4a58-b605-f8cdebacd292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426185477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1426185477
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.2017300431
Short name T101
Test name
Test status
Simulation time 178618892 ps
CPU time 2.68 seconds
Started Jul 19 05:02:33 PM PDT 24
Finished Jul 19 05:02:38 PM PDT 24
Peak memory 217796 kb
Host smart-274625f2-120b-47d9-bdf8-9d779ae55177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017300431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2017300431
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2701101060
Short name T607
Test name
Test status
Simulation time 6897724090 ps
CPU time 86.9 seconds
Started Jul 19 05:02:36 PM PDT 24
Finished Jul 19 05:04:06 PM PDT 24
Peak memory 279460 kb
Host smart-5537ba22-f778-4354-9bd8-dbb7edca430c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701101060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2701101060
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.94410345
Short name T613
Test name
Test status
Simulation time 8671818681 ps
CPU time 299.63 seconds
Started Jul 19 05:02:41 PM PDT 24
Finished Jul 19 05:07:43 PM PDT 24
Peak memory 280236 kb
Host smart-5c1d1a36-cecd-4d0e-a9cd-605993dd6991
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=94410345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.94410345
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.656773650
Short name T501
Test name
Test status
Simulation time 81322501 ps
CPU time 1.15 seconds
Started Jul 19 05:02:35 PM PDT 24
Finished Jul 19 05:02:39 PM PDT 24
Peak memory 217204 kb
Host smart-40e6157b-50e4-43be-a41d-7abe81bcc2ad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656773650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.656773650
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.540140557
Short name T472
Test name
Test status
Simulation time 110022064 ps
CPU time 0.86 seconds
Started Jul 19 05:02:45 PM PDT 24
Finished Jul 19 05:02:51 PM PDT 24
Peak memory 208368 kb
Host smart-b371050c-4c7f-4241-826a-1d9908c8b0ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540140557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.540140557
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.443783607
Short name T312
Test name
Test status
Simulation time 297924879 ps
CPU time 10.38 seconds
Started Jul 19 05:02:42 PM PDT 24
Finished Jul 19 05:02:57 PM PDT 24
Peak memory 217888 kb
Host smart-81eeabd4-6f6a-4163-9866-0df9067c082f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443783607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.443783607
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.236830660
Short name T386
Test name
Test status
Simulation time 291491630 ps
CPU time 4.95 seconds
Started Jul 19 05:02:40 PM PDT 24
Finished Jul 19 05:02:46 PM PDT 24
Peak memory 216608 kb
Host smart-e0c54210-17ce-4483-a218-469fd51406f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236830660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.236830660
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2796320254
Short name T750
Test name
Test status
Simulation time 194357637 ps
CPU time 2.36 seconds
Started Jul 19 05:02:42 PM PDT 24
Finished Jul 19 05:02:47 PM PDT 24
Peak memory 221664 kb
Host smart-12d8cbc5-4b45-4827-9900-7c2f58d1be92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796320254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2796320254
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.547963555
Short name T523
Test name
Test status
Simulation time 1111714290 ps
CPU time 17.25 seconds
Started Jul 19 05:02:41 PM PDT 24
Finished Jul 19 05:02:59 PM PDT 24
Peak memory 218528 kb
Host smart-a0836eed-3070-4e2b-a7a8-c5335b782704
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547963555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.547963555
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3305765862
Short name T341
Test name
Test status
Simulation time 232473832 ps
CPU time 7.58 seconds
Started Jul 19 05:02:44 PM PDT 24
Finished Jul 19 05:02:57 PM PDT 24
Peak memory 217788 kb
Host smart-ac772131-bc7e-45ca-96cc-b05a820077c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305765862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3305765862
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.572486196
Short name T320
Test name
Test status
Simulation time 251190999 ps
CPU time 6.22 seconds
Started Jul 19 05:02:44 PM PDT 24
Finished Jul 19 05:02:56 PM PDT 24
Peak memory 225160 kb
Host smart-d717f99a-bd55-4576-851b-09cdeaf3a210
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572486196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.572486196
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.541761161
Short name T30
Test name
Test status
Simulation time 790046282 ps
CPU time 9.28 seconds
Started Jul 19 05:02:44 PM PDT 24
Finished Jul 19 05:02:59 PM PDT 24
Peak memory 217592 kb
Host smart-aa8eb20b-3855-44da-8b00-749523ab0b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541761161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.541761161
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3010837472
Short name T276
Test name
Test status
Simulation time 21696089 ps
CPU time 1.83 seconds
Started Jul 19 05:02:44 PM PDT 24
Finished Jul 19 05:02:51 PM PDT 24
Peak memory 213480 kb
Host smart-e1ca8108-eb37-446f-be4c-bce55a68242c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010837472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3010837472
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2594077501
Short name T616
Test name
Test status
Simulation time 283709383 ps
CPU time 27.88 seconds
Started Jul 19 05:02:43 PM PDT 24
Finished Jul 19 05:03:16 PM PDT 24
Peak memory 250536 kb
Host smart-a9053577-f156-4989-8161-6b31fccaf8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594077501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2594077501
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1771715714
Short name T44
Test name
Test status
Simulation time 115134150 ps
CPU time 6.34 seconds
Started Jul 19 05:02:43 PM PDT 24
Finished Jul 19 05:02:54 PM PDT 24
Peak memory 246600 kb
Host smart-e97668f2-f850-44a7-937e-4eb77c27c1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771715714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1771715714
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.3278847931
Short name T251
Test name
Test status
Simulation time 678010056 ps
CPU time 36.41 seconds
Started Jul 19 05:02:42 PM PDT 24
Finished Jul 19 05:03:23 PM PDT 24
Peak memory 250544 kb
Host smart-4c057f36-de04-423f-984b-f237393953d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278847931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.3278847931
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.485344473
Short name T600
Test name
Test status
Simulation time 22638390 ps
CPU time 0.96 seconds
Started Jul 19 05:02:42 PM PDT 24
Finished Jul 19 05:02:47 PM PDT 24
Peak memory 211380 kb
Host smart-ab8bb36d-df09-46b3-b3b9-2500fc7cd549
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485344473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.485344473
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2355319412
Short name T692
Test name
Test status
Simulation time 12910554 ps
CPU time 0.98 seconds
Started Jul 19 05:02:43 PM PDT 24
Finished Jul 19 05:02:49 PM PDT 24
Peak memory 208416 kb
Host smart-72ba32e5-8f5b-42af-9c73-d2cec6a5a86b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355319412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2355319412
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.872467847
Short name T273
Test name
Test status
Simulation time 912488848 ps
CPU time 13.05 seconds
Started Jul 19 05:02:42 PM PDT 24
Finished Jul 19 05:02:58 PM PDT 24
Peak memory 217696 kb
Host smart-6cd0e038-90e0-463a-8fb8-bac0f6f3650e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872467847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.872467847
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.849543906
Short name T570
Test name
Test status
Simulation time 358251186 ps
CPU time 3.04 seconds
Started Jul 19 05:02:42 PM PDT 24
Finished Jul 19 05:02:49 PM PDT 24
Peak memory 216756 kb
Host smart-6f2cd0dc-7cb7-4fe4-82e6-0474ee87bb78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849543906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.849543906
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2019838750
Short name T856
Test name
Test status
Simulation time 738419108 ps
CPU time 3.51 seconds
Started Jul 19 05:02:41 PM PDT 24
Finished Jul 19 05:02:46 PM PDT 24
Peak memory 217736 kb
Host smart-efe41009-d694-441a-9f1c-2a453fc3bb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019838750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2019838750
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3481242898
Short name T662
Test name
Test status
Simulation time 1566090633 ps
CPU time 13.63 seconds
Started Jul 19 05:02:45 PM PDT 24
Finished Jul 19 05:03:04 PM PDT 24
Peak memory 225544 kb
Host smart-a29ff100-4801-4273-8466-53a252e5000f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481242898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3481242898
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2682438599
Short name T272
Test name
Test status
Simulation time 471842367 ps
CPU time 10.23 seconds
Started Jul 19 05:02:42 PM PDT 24
Finished Jul 19 05:02:57 PM PDT 24
Peak memory 217800 kb
Host smart-7b874301-67b2-4254-9de9-0ab522e4cbb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682438599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2682438599
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2220820850
Short name T153
Test name
Test status
Simulation time 1282134731 ps
CPU time 11.13 seconds
Started Jul 19 05:02:41 PM PDT 24
Finished Jul 19 05:02:54 PM PDT 24
Peak memory 225536 kb
Host smart-51cce50c-2865-4846-a9ff-ba4135df2ebe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220820850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2220820850
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3433382082
Short name T527
Test name
Test status
Simulation time 110160986 ps
CPU time 2.18 seconds
Started Jul 19 05:02:42 PM PDT 24
Finished Jul 19 05:02:48 PM PDT 24
Peak memory 214156 kb
Host smart-6a837aaa-1f29-474f-8f50-4506f8fee31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433382082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3433382082
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1580358646
Short name T355
Test name
Test status
Simulation time 296418817 ps
CPU time 32.09 seconds
Started Jul 19 05:02:42 PM PDT 24
Finished Jul 19 05:03:18 PM PDT 24
Peak memory 250592 kb
Host smart-6be453a3-9c95-4e42-8b95-a3a629478eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580358646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1580358646
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.993358611
Short name T548
Test name
Test status
Simulation time 76187731 ps
CPU time 3.99 seconds
Started Jul 19 05:02:44 PM PDT 24
Finished Jul 19 05:02:53 PM PDT 24
Peak memory 222460 kb
Host smart-00cfccf4-076f-4796-9d05-97bcc17c30af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993358611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.993358611
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.4226109981
Short name T259
Test name
Test status
Simulation time 12912021390 ps
CPU time 411.06 seconds
Started Jul 19 05:02:42 PM PDT 24
Finished Jul 19 05:09:37 PM PDT 24
Peak memory 282856 kb
Host smart-dc1c57ca-18dc-4f3f-aa3e-487b3e4bdc96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226109981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.4226109981
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3351156505
Short name T666
Test name
Test status
Simulation time 11491462 ps
CPU time 0.92 seconds
Started Jul 19 05:02:42 PM PDT 24
Finished Jul 19 05:02:46 PM PDT 24
Peak memory 208460 kb
Host smart-8c74d48b-46d9-438c-b7b0-7f06ecd81888
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351156505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.3351156505
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1187243949
Short name T455
Test name
Test status
Simulation time 94009779 ps
CPU time 0.96 seconds
Started Jul 19 05:02:48 PM PDT 24
Finished Jul 19 05:02:54 PM PDT 24
Peak memory 208472 kb
Host smart-1afa8397-f8d1-49e6-8579-887ae32f4329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187243949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1187243949
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.2895794590
Short name T429
Test name
Test status
Simulation time 1202417448 ps
CPU time 25.59 seconds
Started Jul 19 05:02:42 PM PDT 24
Finished Jul 19 05:03:10 PM PDT 24
Peak memory 217856 kb
Host smart-b9ca6448-2f97-42eb-8d7f-bf4a154cb5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895794590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2895794590
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.1550250248
Short name T743
Test name
Test status
Simulation time 250806314 ps
CPU time 3.72 seconds
Started Jul 19 05:02:41 PM PDT 24
Finished Jul 19 05:02:48 PM PDT 24
Peak memory 216588 kb
Host smart-058102ce-e266-4a2a-b618-e3387c7bb600
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550250248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.1550250248
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2275497905
Short name T561
Test name
Test status
Simulation time 21014928 ps
CPU time 1.79 seconds
Started Jul 19 05:02:43 PM PDT 24
Finished Jul 19 05:02:50 PM PDT 24
Peak memory 217796 kb
Host smart-7ac29735-c9a2-4d51-8211-d77fe3360859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275497905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2275497905
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.229414012
Short name T381
Test name
Test status
Simulation time 178285266 ps
CPU time 9.41 seconds
Started Jul 19 05:02:43 PM PDT 24
Finished Jul 19 05:02:57 PM PDT 24
Peak memory 225544 kb
Host smart-5654437b-82a4-4ed2-884e-e08c9a855c3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229414012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.229414012
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.247129285
Short name T552
Test name
Test status
Simulation time 858129781 ps
CPU time 20.68 seconds
Started Jul 19 05:02:49 PM PDT 24
Finished Jul 19 05:03:15 PM PDT 24
Peak memory 217792 kb
Host smart-868c7d96-a320-4971-b019-c6089a3f4e43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247129285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.247129285
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3850201917
Short name T529
Test name
Test status
Simulation time 451092529 ps
CPU time 9.07 seconds
Started Jul 19 05:02:52 PM PDT 24
Finished Jul 19 05:03:05 PM PDT 24
Peak memory 217752 kb
Host smart-7148a544-c48d-45d8-b289-015309e39ba3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850201917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
3850201917
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2252453960
Short name T444
Test name
Test status
Simulation time 414251944 ps
CPU time 14.48 seconds
Started Jul 19 05:02:44 PM PDT 24
Finished Jul 19 05:03:04 PM PDT 24
Peak memory 217884 kb
Host smart-1e57770b-382a-4483-8a9a-4bf06926b8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252453960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2252453960
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.424612297
Short name T823
Test name
Test status
Simulation time 20297198 ps
CPU time 1.6 seconds
Started Jul 19 05:02:45 PM PDT 24
Finished Jul 19 05:02:52 PM PDT 24
Peak memory 217228 kb
Host smart-3f7117af-3d65-4da8-9cbe-1fdd9b3d2d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424612297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.424612297
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3050828919
Short name T292
Test name
Test status
Simulation time 336556846 ps
CPU time 30.22 seconds
Started Jul 19 05:02:42 PM PDT 24
Finished Jul 19 05:03:15 PM PDT 24
Peak memory 250552 kb
Host smart-c826c2c5-7712-4b36-a724-ceaa6909252f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050828919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3050828919
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.4013922058
Short name T852
Test name
Test status
Simulation time 62468906 ps
CPU time 7.37 seconds
Started Jul 19 05:02:44 PM PDT 24
Finished Jul 19 05:02:57 PM PDT 24
Peak memory 250540 kb
Host smart-f924dea2-af12-4e3e-a9ec-8f8a424e6b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013922058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.4013922058
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.642055453
Short name T451
Test name
Test status
Simulation time 5865476906 ps
CPU time 28.69 seconds
Started Jul 19 05:02:56 PM PDT 24
Finished Jul 19 05:03:28 PM PDT 24
Peak memory 242432 kb
Host smart-3b65da91-35c7-4d90-8e0c-3f5cf5e290e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642055453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.642055453
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.940318911
Short name T723
Test name
Test status
Simulation time 35320650 ps
CPU time 0.81 seconds
Started Jul 19 05:02:42 PM PDT 24
Finished Jul 19 05:02:47 PM PDT 24
Peak memory 208448 kb
Host smart-7b0316d2-fe11-4869-8e3d-bd24b6405e28
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940318911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct
rl_volatile_unlock_smoke.940318911
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3520944226
Short name T238
Test name
Test status
Simulation time 39132791 ps
CPU time 0.95 seconds
Started Jul 19 05:02:50 PM PDT 24
Finished Jul 19 05:02:55 PM PDT 24
Peak memory 208420 kb
Host smart-f381c254-94c7-4da7-97a1-39b3de297e34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520944226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3520944226
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.800729998
Short name T314
Test name
Test status
Simulation time 1900225907 ps
CPU time 15.61 seconds
Started Jul 19 05:02:52 PM PDT 24
Finished Jul 19 05:03:11 PM PDT 24
Peak memory 217816 kb
Host smart-55de6b34-8b11-4047-af1f-8b2a5c28b9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800729998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.800729998
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2998114793
Short name T74
Test name
Test status
Simulation time 272178021 ps
CPU time 1.95 seconds
Started Jul 19 05:02:57 PM PDT 24
Finished Jul 19 05:03:01 PM PDT 24
Peak memory 216544 kb
Host smart-b7febac3-5db0-4c84-9c47-1b36e0bde0e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998114793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2998114793
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1108541967
Short name T584
Test name
Test status
Simulation time 168072265 ps
CPU time 2.73 seconds
Started Jul 19 05:02:51 PM PDT 24
Finished Jul 19 05:02:58 PM PDT 24
Peak memory 221908 kb
Host smart-6ac5bf63-a5c8-4751-8700-d660ca6e6798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108541967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1108541967
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1229120139
Short name T810
Test name
Test status
Simulation time 2121643441 ps
CPU time 15.37 seconds
Started Jul 19 05:02:59 PM PDT 24
Finished Jul 19 05:03:17 PM PDT 24
Peak memory 219636 kb
Host smart-0e0f8c28-4be5-47b0-a36f-2cb1d6b78955
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229120139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1229120139
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3960942320
Short name T265
Test name
Test status
Simulation time 4117224224 ps
CPU time 11.85 seconds
Started Jul 19 05:02:54 PM PDT 24
Finished Jul 19 05:03:09 PM PDT 24
Peak memory 225592 kb
Host smart-120aa95b-f8e3-4dee-9ff4-99f1c72430c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960942320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3960942320
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1599615879
Short name T252
Test name
Test status
Simulation time 1026885363 ps
CPU time 10.75 seconds
Started Jul 19 05:02:52 PM PDT 24
Finished Jul 19 05:03:06 PM PDT 24
Peak memory 225528 kb
Host smart-d685ae8c-7d47-4d6c-af86-d5606720b34d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599615879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1599615879
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.4001463687
Short name T768
Test name
Test status
Simulation time 1418635065 ps
CPU time 8.86 seconds
Started Jul 19 05:02:51 PM PDT 24
Finished Jul 19 05:03:04 PM PDT 24
Peak memory 217872 kb
Host smart-07d5f3e3-a1ba-4c3f-8236-6627daa2356e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001463687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.4001463687
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1203161233
Short name T81
Test name
Test status
Simulation time 159532367 ps
CPU time 2.23 seconds
Started Jul 19 05:02:49 PM PDT 24
Finished Jul 19 05:02:56 PM PDT 24
Peak memory 223080 kb
Host smart-85acac43-1831-470a-ac14-100f80ef88c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203161233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1203161233
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3647434909
Short name T598
Test name
Test status
Simulation time 178098774 ps
CPU time 20.76 seconds
Started Jul 19 05:02:52 PM PDT 24
Finished Jul 19 05:03:16 PM PDT 24
Peak memory 250560 kb
Host smart-9c0b0865-7243-4234-a36f-42c8ed0ee0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647434909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3647434909
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.879583395
Short name T855
Test name
Test status
Simulation time 128607712 ps
CPU time 8.76 seconds
Started Jul 19 05:02:49 PM PDT 24
Finished Jul 19 05:03:03 PM PDT 24
Peak memory 250380 kb
Host smart-26c1698e-3eb9-4d95-8b5d-fc9756fdd09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879583395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.879583395
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2693915825
Short name T439
Test name
Test status
Simulation time 8453289538 ps
CPU time 174.73 seconds
Started Jul 19 05:02:55 PM PDT 24
Finished Jul 19 05:05:53 PM PDT 24
Peak memory 267380 kb
Host smart-07451d2f-65cc-4f95-9316-6cca92652b81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693915825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2693915825
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3699939606
Short name T469
Test name
Test status
Simulation time 41950822 ps
CPU time 0.9 seconds
Started Jul 19 05:02:50 PM PDT 24
Finished Jul 19 05:02:55 PM PDT 24
Peak memory 211408 kb
Host smart-f46ae13d-0a0e-4383-9fc4-ba9f6ebbc630
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699939606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3699939606
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1825359883
Short name T482
Test name
Test status
Simulation time 14027115 ps
CPU time 0.88 seconds
Started Jul 19 05:02:57 PM PDT 24
Finished Jul 19 05:03:01 PM PDT 24
Peak memory 208224 kb
Host smart-ce5f7c02-4008-47f3-98fc-1d046f099bda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825359883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1825359883
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1695802638
Short name T827
Test name
Test status
Simulation time 296776102 ps
CPU time 14.58 seconds
Started Jul 19 05:02:59 PM PDT 24
Finished Jul 19 05:03:16 PM PDT 24
Peak memory 217836 kb
Host smart-04df45db-08c2-4844-bba6-46ba38cb6161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695802638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1695802638
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.169120128
Short name T678
Test name
Test status
Simulation time 657800244 ps
CPU time 8.61 seconds
Started Jul 19 05:02:53 PM PDT 24
Finished Jul 19 05:03:05 PM PDT 24
Peak memory 216588 kb
Host smart-0e35710a-e062-4eb0-8b93-f3976ecb05c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169120128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.169120128
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.683419253
Short name T352
Test name
Test status
Simulation time 1081775558 ps
CPU time 2.97 seconds
Started Jul 19 05:02:52 PM PDT 24
Finished Jul 19 05:02:59 PM PDT 24
Peak memory 217784 kb
Host smart-ba68595a-d95d-48c9-9946-658564251fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683419253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.683419253
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.536457768
Short name T853
Test name
Test status
Simulation time 1183896573 ps
CPU time 12.4 seconds
Started Jul 19 05:02:50 PM PDT 24
Finished Jul 19 05:03:07 PM PDT 24
Peak memory 225524 kb
Host smart-dd44387d-cc9d-44de-93e4-71045dd2c5f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536457768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.536457768
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1524826415
Short name T68
Test name
Test status
Simulation time 790870880 ps
CPU time 11.38 seconds
Started Jul 19 05:02:53 PM PDT 24
Finished Jul 19 05:03:09 PM PDT 24
Peak memory 225528 kb
Host smart-15a8df09-5dfc-4bf8-92fc-d647e62890a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524826415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1524826415
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.549268528
Short name T654
Test name
Test status
Simulation time 993512511 ps
CPU time 8 seconds
Started Jul 19 05:02:52 PM PDT 24
Finished Jul 19 05:03:04 PM PDT 24
Peak memory 217820 kb
Host smart-d171640a-89ea-47db-bc07-c089a7213137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549268528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.549268528
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1611301092
Short name T423
Test name
Test status
Simulation time 174006917 ps
CPU time 2.3 seconds
Started Jul 19 05:02:50 PM PDT 24
Finished Jul 19 05:02:57 PM PDT 24
Peak memory 213668 kb
Host smart-656890a0-3ab4-47ea-9883-6c2de1617658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611301092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1611301092
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2808611521
Short name T532
Test name
Test status
Simulation time 2969741838 ps
CPU time 22.72 seconds
Started Jul 19 05:02:51 PM PDT 24
Finished Jul 19 05:03:18 PM PDT 24
Peak memory 250484 kb
Host smart-d30fb8a5-8f42-4361-b0f3-062790e32b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808611521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2808611521
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3940359128
Short name T279
Test name
Test status
Simulation time 400135345 ps
CPU time 8.67 seconds
Started Jul 19 05:02:51 PM PDT 24
Finished Jul 19 05:03:04 PM PDT 24
Peak memory 250444 kb
Host smart-157c7f35-b155-47c7-92fb-2fa41355e1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940359128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3940359128
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2095601177
Short name T339
Test name
Test status
Simulation time 33031620 ps
CPU time 0.77 seconds
Started Jul 19 05:02:52 PM PDT 24
Finished Jul 19 05:02:57 PM PDT 24
Peak memory 208220 kb
Host smart-d0fe6143-3910-42fa-afb0-359fd1f2d062
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095601177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.2095601177
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.144935944
Short name T385
Test name
Test status
Simulation time 23882011 ps
CPU time 1.26 seconds
Started Jul 19 05:03:00 PM PDT 24
Finished Jul 19 05:03:04 PM PDT 24
Peak memory 208548 kb
Host smart-ca045275-3fc6-4a16-9737-207b5917d2a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144935944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.144935944
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1651859442
Short name T818
Test name
Test status
Simulation time 418650642 ps
CPU time 13.48 seconds
Started Jul 19 05:02:57 PM PDT 24
Finished Jul 19 05:03:13 PM PDT 24
Peak memory 217716 kb
Host smart-48b2c1c9-c365-4fc1-be81-1cb6f39c5b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651859442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1651859442
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.2494791207
Short name T740
Test name
Test status
Simulation time 92663339 ps
CPU time 1.96 seconds
Started Jul 19 05:03:00 PM PDT 24
Finished Jul 19 05:03:04 PM PDT 24
Peak memory 216516 kb
Host smart-51161c5b-70cf-4682-b5bb-57984e1058da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494791207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2494791207
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.88800339
Short name T356
Test name
Test status
Simulation time 452313644 ps
CPU time 2.4 seconds
Started Jul 19 05:02:56 PM PDT 24
Finished Jul 19 05:03:02 PM PDT 24
Peak memory 217780 kb
Host smart-b32ed793-8737-4684-8729-428cf61bc1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88800339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.88800339
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2895206840
Short name T668
Test name
Test status
Simulation time 867165683 ps
CPU time 9.55 seconds
Started Jul 19 05:02:59 PM PDT 24
Finished Jul 19 05:03:12 PM PDT 24
Peak memory 225484 kb
Host smart-053c7d3c-6fe2-4f95-bf0f-e6cc14c837f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895206840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2895206840
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1776773564
Short name T237
Test name
Test status
Simulation time 765101520 ps
CPU time 11.68 seconds
Started Jul 19 05:03:01 PM PDT 24
Finished Jul 19 05:03:16 PM PDT 24
Peak memory 217732 kb
Host smart-68e5a9b8-26bb-43ce-913f-cbdc88e19b28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776773564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1776773564
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1897725436
Short name T186
Test name
Test status
Simulation time 1112503953 ps
CPU time 10.48 seconds
Started Jul 19 05:02:56 PM PDT 24
Finished Jul 19 05:03:10 PM PDT 24
Peak memory 217860 kb
Host smart-a3fac321-95bf-4ff2-af83-9d96cf78a7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897725436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1897725436
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.4061839698
Short name T709
Test name
Test status
Simulation time 67188421 ps
CPU time 1.55 seconds
Started Jul 19 05:02:51 PM PDT 24
Finished Jul 19 05:02:57 PM PDT 24
Peak memory 217184 kb
Host smart-b95b5f38-1089-4ea1-bc2b-a330f1fed2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061839698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.4061839698
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3820008965
Short name T673
Test name
Test status
Simulation time 247745146 ps
CPU time 29.09 seconds
Started Jul 19 05:02:58 PM PDT 24
Finished Jul 19 05:03:30 PM PDT 24
Peak memory 250552 kb
Host smart-1164ae1b-0ad4-43a3-9a45-bf67e7090644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820008965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3820008965
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2355286088
Short name T69
Test name
Test status
Simulation time 334089006 ps
CPU time 4.38 seconds
Started Jul 19 05:03:00 PM PDT 24
Finished Jul 19 05:03:07 PM PDT 24
Peak memory 222516 kb
Host smart-9b87cfae-717d-4a96-a6b1-8b98c81a6ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355286088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2355286088
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.50272106
Short name T758
Test name
Test status
Simulation time 4509874945 ps
CPU time 86.05 seconds
Started Jul 19 05:02:59 PM PDT 24
Finished Jul 19 05:04:28 PM PDT 24
Peak memory 275028 kb
Host smart-110f91b7-8958-46f4-b796-9ad3a4685c4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50272106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.lc_ctrl_stress_all.50272106
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.1672108920
Short name T590
Test name
Test status
Simulation time 17253303642 ps
CPU time 275.47 seconds
Started Jul 19 05:03:01 PM PDT 24
Finished Jul 19 05:07:39 PM PDT 24
Peak memory 269192 kb
Host smart-5e4f6f50-0738-4a56-ba3b-5c55d5783322
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1672108920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.1672108920
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.354469926
Short name T659
Test name
Test status
Simulation time 62111053 ps
CPU time 0.9 seconds
Started Jul 19 05:02:51 PM PDT 24
Finished Jul 19 05:02:56 PM PDT 24
Peak memory 211384 kb
Host smart-f8edf08e-6560-4cdc-b7cd-05732b6460f1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354469926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.354469926
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.2531072214
Short name T524
Test name
Test status
Simulation time 134733715 ps
CPU time 0.84 seconds
Started Jul 19 05:02:59 PM PDT 24
Finished Jul 19 05:03:02 PM PDT 24
Peak memory 208260 kb
Host smart-29a4d965-ad96-4305-96ac-956637fbf213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531072214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2531072214
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3767808350
Short name T833
Test name
Test status
Simulation time 2193485780 ps
CPU time 13.48 seconds
Started Jul 19 05:03:02 PM PDT 24
Finished Jul 19 05:03:18 PM PDT 24
Peak memory 217876 kb
Host smart-1eca83f6-7063-4a49-b8ca-28731e68f715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767808350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3767808350
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2427711967
Short name T651
Test name
Test status
Simulation time 296264702 ps
CPU time 4.13 seconds
Started Jul 19 05:02:59 PM PDT 24
Finished Jul 19 05:03:06 PM PDT 24
Peak memory 216540 kb
Host smart-7a48c2b7-dd99-4eb0-8bc8-3c2ec4ba727f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427711967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2427711967
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3144687799
Short name T738
Test name
Test status
Simulation time 43498236 ps
CPU time 2.82 seconds
Started Jul 19 05:03:00 PM PDT 24
Finished Jul 19 05:03:05 PM PDT 24
Peak memory 217832 kb
Host smart-c4813d20-85bb-49d2-9799-c00f847def07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144687799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3144687799
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2154574689
Short name T694
Test name
Test status
Simulation time 3392388809 ps
CPU time 7.26 seconds
Started Jul 19 05:02:58 PM PDT 24
Finished Jul 19 05:03:08 PM PDT 24
Peak memory 217848 kb
Host smart-7b87f27f-c03c-4c2c-b9a7-291b2e1a1786
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154574689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2154574689
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2522478782
Short name T595
Test name
Test status
Simulation time 310591221 ps
CPU time 7.95 seconds
Started Jul 19 05:02:57 PM PDT 24
Finished Jul 19 05:03:08 PM PDT 24
Peak memory 225664 kb
Host smart-14f0418d-7b2a-43ee-b216-5f767480a440
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522478782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2522478782
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3668101767
Short name T820
Test name
Test status
Simulation time 549788750 ps
CPU time 10.61 seconds
Started Jul 19 05:02:59 PM PDT 24
Finished Jul 19 05:03:12 PM PDT 24
Peak memory 217788 kb
Host smart-69a20c6b-6008-4d37-8dc8-564881b74e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668101767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3668101767
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3071890882
Short name T91
Test name
Test status
Simulation time 224832358 ps
CPU time 6.59 seconds
Started Jul 19 05:03:02 PM PDT 24
Finished Jul 19 05:03:11 PM PDT 24
Peak memory 217220 kb
Host smart-780986f6-4b04-45b7-9ae9-4b4f625e5812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071890882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3071890882
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.4275283506
Short name T745
Test name
Test status
Simulation time 1244547402 ps
CPU time 25.99 seconds
Started Jul 19 05:02:57 PM PDT 24
Finished Jul 19 05:03:26 PM PDT 24
Peak memory 250536 kb
Host smart-90960a44-a253-4c8f-8f11-9c0d061d3611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275283506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.4275283506
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.512008262
Short name T324
Test name
Test status
Simulation time 287235127 ps
CPU time 7 seconds
Started Jul 19 05:03:00 PM PDT 24
Finished Jul 19 05:03:10 PM PDT 24
Peak memory 246780 kb
Host smart-6f1e35b0-8dfd-473e-a3d6-e454ac103825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512008262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.512008262
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1151691912
Short name T67
Test name
Test status
Simulation time 33006623233 ps
CPU time 416.47 seconds
Started Jul 19 05:03:06 PM PDT 24
Finished Jul 19 05:10:05 PM PDT 24
Peak memory 242432 kb
Host smart-d7674cca-8531-483d-92bc-8c387853b3d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151691912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1151691912
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3076294281
Short name T97
Test name
Test status
Simulation time 93695872578 ps
CPU time 550.88 seconds
Started Jul 19 05:03:00 PM PDT 24
Finished Jul 19 05:12:14 PM PDT 24
Peak memory 272156 kb
Host smart-77fe0641-b016-4e6e-b94b-a0254a54ab96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3076294281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.3076294281
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.136300608
Short name T181
Test name
Test status
Simulation time 19953869 ps
CPU time 0.92 seconds
Started Jul 19 05:02:57 PM PDT 24
Finished Jul 19 05:03:00 PM PDT 24
Peak memory 208432 kb
Host smart-7ee2d258-a157-498a-a620-f63d14c2ead1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136300608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct
rl_volatile_unlock_smoke.136300608
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1570316436
Short name T234
Test name
Test status
Simulation time 51040507 ps
CPU time 0.89 seconds
Started Jul 19 05:00:36 PM PDT 24
Finished Jul 19 05:00:40 PM PDT 24
Peak memory 208364 kb
Host smart-af58799e-f2c0-48d1-acc5-7c03137eb459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570316436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1570316436
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.4175959053
Short name T223
Test name
Test status
Simulation time 86619960 ps
CPU time 0.83 seconds
Started Jul 19 05:00:30 PM PDT 24
Finished Jul 19 05:00:35 PM PDT 24
Peak memory 208504 kb
Host smart-ecbc02f3-6da5-4d5c-a483-efa3ee6787e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175959053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.4175959053
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.809012108
Short name T254
Test name
Test status
Simulation time 355244101 ps
CPU time 11.16 seconds
Started Jul 19 05:00:26 PM PDT 24
Finished Jul 19 05:00:40 PM PDT 24
Peak memory 217632 kb
Host smart-b18dcd50-7a2a-4690-821b-5e771803097d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809012108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.809012108
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1066281810
Short name T621
Test name
Test status
Simulation time 1782361611 ps
CPU time 12.66 seconds
Started Jul 19 05:00:30 PM PDT 24
Finished Jul 19 05:00:47 PM PDT 24
Peak memory 216932 kb
Host smart-009fc9c8-053c-4c96-8172-1439434d38ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066281810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1066281810
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.4197102386
Short name T762
Test name
Test status
Simulation time 1753234178 ps
CPU time 26.06 seconds
Started Jul 19 05:00:31 PM PDT 24
Finished Jul 19 05:01:01 PM PDT 24
Peak memory 217708 kb
Host smart-d0f18280-8731-4eca-a17a-1b4435f1a964
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197102386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.4197102386
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3565348230
Short name T767
Test name
Test status
Simulation time 2945087404 ps
CPU time 13.65 seconds
Started Jul 19 05:00:29 PM PDT 24
Finished Jul 19 05:00:47 PM PDT 24
Peak memory 217292 kb
Host smart-70db9a32-fef6-4061-bae7-a655c5ee6d2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565348230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.3
565348230
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1680228567
Short name T533
Test name
Test status
Simulation time 130775315 ps
CPU time 2.62 seconds
Started Jul 19 05:00:27 PM PDT 24
Finished Jul 19 05:00:34 PM PDT 24
Peak memory 221004 kb
Host smart-49aa30d5-abb5-4629-8cbd-1cd2a5eb9147
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680228567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1680228567
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.83618196
Short name T83
Test name
Test status
Simulation time 913590257 ps
CPU time 9.92 seconds
Started Jul 19 05:00:27 PM PDT 24
Finished Jul 19 05:00:42 PM PDT 24
Peak memory 217164 kb
Host smart-3a6f0ea2-14f4-409c-9dd2-802aa5f61e4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83618196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jt
ag_regwen_during_op.83618196
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1398017041
Short name T269
Test name
Test status
Simulation time 755213901 ps
CPU time 20.01 seconds
Started Jul 19 05:00:30 PM PDT 24
Finished Jul 19 05:00:54 PM PDT 24
Peak memory 217128 kb
Host smart-ced16e25-4a53-4862-8ae4-11f1d4c10646
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398017041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
1398017041
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2481614335
Short name T664
Test name
Test status
Simulation time 10004063366 ps
CPU time 52.93 seconds
Started Jul 19 05:00:27 PM PDT 24
Finished Jul 19 05:01:25 PM PDT 24
Peak memory 275708 kb
Host smart-c6719c14-5f50-42c7-9561-d6b49be0df82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481614335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2481614335
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1417458947
Short name T383
Test name
Test status
Simulation time 499865929 ps
CPU time 9.92 seconds
Started Jul 19 05:00:30 PM PDT 24
Finished Jul 19 05:00:45 PM PDT 24
Peak memory 222520 kb
Host smart-34c3085d-d676-4a3a-9dd9-8ad77c81ba72
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417458947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1417458947
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2094256347
Short name T760
Test name
Test status
Simulation time 67095235 ps
CPU time 3.57 seconds
Started Jul 19 05:00:27 PM PDT 24
Finished Jul 19 05:00:35 PM PDT 24
Peak memory 217812 kb
Host smart-ba765dd2-37d9-41d7-b72a-f26acecf4af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094256347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2094256347
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3830843735
Short name T84
Test name
Test status
Simulation time 381282407 ps
CPU time 22.36 seconds
Started Jul 19 05:00:28 PM PDT 24
Finished Jul 19 05:00:55 PM PDT 24
Peak memory 213676 kb
Host smart-30504fa8-9496-4db0-867e-54a85dfb71cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830843735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3830843735
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2717355527
Short name T60
Test name
Test status
Simulation time 515211765 ps
CPU time 27.28 seconds
Started Jul 19 05:00:40 PM PDT 24
Finished Jul 19 05:01:10 PM PDT 24
Peak memory 281380 kb
Host smart-270e5fb2-76ee-4bb3-b37a-359302be128b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717355527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2717355527
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.3027418469
Short name T493
Test name
Test status
Simulation time 535425199 ps
CPU time 20.16 seconds
Started Jul 19 05:00:27 PM PDT 24
Finished Jul 19 05:00:50 PM PDT 24
Peak memory 218412 kb
Host smart-18562edb-1cc6-4385-88e4-ded4f32ba265
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027418469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.3027418469
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2929612811
Short name T42
Test name
Test status
Simulation time 246990526 ps
CPU time 9.05 seconds
Started Jul 19 05:00:37 PM PDT 24
Finished Jul 19 05:00:50 PM PDT 24
Peak memory 225516 kb
Host smart-fc58b0d1-24c9-494d-b245-43f0f69342ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929612811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2929612811
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3293664571
Short name T671
Test name
Test status
Simulation time 197836237 ps
CPU time 7.75 seconds
Started Jul 19 05:00:26 PM PDT 24
Finished Jul 19 05:00:36 PM PDT 24
Peak memory 225460 kb
Host smart-528df159-7976-49c7-b035-abc0bb176cbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293664571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
293664571
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3005301646
Short name T62
Test name
Test status
Simulation time 493321262 ps
CPU time 12.95 seconds
Started Jul 19 05:00:26 PM PDT 24
Finished Jul 19 05:00:42 PM PDT 24
Peak memory 217848 kb
Host smart-607ea630-54c2-473e-8d83-30376d3ca1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005301646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3005301646
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3083869874
Short name T78
Test name
Test status
Simulation time 153642241 ps
CPU time 2.63 seconds
Started Jul 19 05:00:27 PM PDT 24
Finished Jul 19 05:00:34 PM PDT 24
Peak memory 217224 kb
Host smart-00d41921-94a1-4d83-b2c9-672a66ebcc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083869874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3083869874
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1449283443
Short name T550
Test name
Test status
Simulation time 157180265 ps
CPU time 19.69 seconds
Started Jul 19 05:00:26 PM PDT 24
Finished Jul 19 05:00:49 PM PDT 24
Peak memory 250548 kb
Host smart-e0c476e5-d0a2-4543-bc45-79b0daf38851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449283443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1449283443
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3110021504
Short name T679
Test name
Test status
Simulation time 353780706 ps
CPU time 6.5 seconds
Started Jul 19 05:00:37 PM PDT 24
Finished Jul 19 05:00:47 PM PDT 24
Peak memory 242368 kb
Host smart-59d68d05-34bb-464e-9475-1fba830e9d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110021504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3110021504
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2061986725
Short name T363
Test name
Test status
Simulation time 1424082916 ps
CPU time 18.52 seconds
Started Jul 19 05:00:37 PM PDT 24
Finished Jul 19 05:00:59 PM PDT 24
Peak memory 217436 kb
Host smart-19427b66-4d27-4b9e-a744-8bdfefe57a14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061986725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2061986725
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1859666154
Short name T680
Test name
Test status
Simulation time 46931528 ps
CPU time 0.81 seconds
Started Jul 19 05:00:28 PM PDT 24
Finished Jul 19 05:00:33 PM PDT 24
Peak memory 208380 kb
Host smart-95d5f7a1-9420-4688-9692-4ce288d9d660
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859666154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1859666154
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.982059565
Short name T226
Test name
Test status
Simulation time 164522206 ps
CPU time 1.03 seconds
Started Jul 19 05:03:08 PM PDT 24
Finished Jul 19 05:03:11 PM PDT 24
Peak memory 208556 kb
Host smart-950b6ab8-732c-4e4d-8d03-136905997d7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982059565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.982059565
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1232978135
Short name T752
Test name
Test status
Simulation time 248397220 ps
CPU time 11.58 seconds
Started Jul 19 05:02:58 PM PDT 24
Finished Jul 19 05:03:12 PM PDT 24
Peak memory 217728 kb
Host smart-44e3c71d-dbb7-49f0-976c-eb15ee61f2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232978135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1232978135
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3358981291
Short name T407
Test name
Test status
Simulation time 2003674319 ps
CPU time 10.11 seconds
Started Jul 19 05:03:01 PM PDT 24
Finished Jul 19 05:03:14 PM PDT 24
Peak memory 216996 kb
Host smart-b2f776d9-13c9-460b-b9ee-fc369ceacf32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358981291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3358981291
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1454218257
Short name T689
Test name
Test status
Simulation time 43951021 ps
CPU time 1.76 seconds
Started Jul 19 05:02:57 PM PDT 24
Finished Jul 19 05:03:02 PM PDT 24
Peak memory 217716 kb
Host smart-5d664204-1a92-4bea-bc5f-2131712875c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454218257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1454218257
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1006560484
Short name T417
Test name
Test status
Simulation time 345488050 ps
CPU time 10.78 seconds
Started Jul 19 05:03:08 PM PDT 24
Finished Jul 19 05:03:21 PM PDT 24
Peak memory 218452 kb
Host smart-9ad1efe6-6f87-415d-b860-eec25247888c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006560484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1006560484
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2810041559
Short name T722
Test name
Test status
Simulation time 1013518320 ps
CPU time 20.6 seconds
Started Jul 19 05:03:08 PM PDT 24
Finished Jul 19 05:03:32 PM PDT 24
Peak memory 225496 kb
Host smart-37108d72-cb6d-46a3-aef3-f065a326e016
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810041559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2810041559
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3631567663
Short name T583
Test name
Test status
Simulation time 162188443 ps
CPU time 5.82 seconds
Started Jul 19 05:03:05 PM PDT 24
Finished Jul 19 05:03:13 PM PDT 24
Peak memory 225536 kb
Host smart-93956526-bce1-4cbd-813a-c1278d1754ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631567663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3631567663
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2794260151
Short name T329
Test name
Test status
Simulation time 215733542 ps
CPU time 8.41 seconds
Started Jul 19 05:02:57 PM PDT 24
Finished Jul 19 05:03:08 PM PDT 24
Peak memory 217824 kb
Host smart-f13d90fd-0009-49d5-b06a-3e28dcbb2312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794260151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2794260151
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1097741519
Short name T391
Test name
Test status
Simulation time 60604980 ps
CPU time 1.96 seconds
Started Jul 19 05:02:57 PM PDT 24
Finished Jul 19 05:03:02 PM PDT 24
Peak memory 217228 kb
Host smart-3d1932ec-147e-4f42-8f13-8fd815cf857d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097741519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1097741519
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3259000798
Short name T373
Test name
Test status
Simulation time 556374657 ps
CPU time 24.93 seconds
Started Jul 19 05:02:58 PM PDT 24
Finished Jul 19 05:03:26 PM PDT 24
Peak memory 250448 kb
Host smart-3ade84f9-8599-48b3-852f-bbbd1cfca8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259000798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3259000798
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2614749969
Short name T503
Test name
Test status
Simulation time 233753005 ps
CPU time 2.9 seconds
Started Jul 19 05:02:58 PM PDT 24
Finished Jul 19 05:03:04 PM PDT 24
Peak memory 217740 kb
Host smart-669276d6-9fa9-45e7-91f9-edcd2ef7f312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614749969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2614749969
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2771416940
Short name T859
Test name
Test status
Simulation time 11994635384 ps
CPU time 107.61 seconds
Started Jul 19 05:03:07 PM PDT 24
Finished Jul 19 05:04:58 PM PDT 24
Peak memory 250612 kb
Host smart-80aa35bb-dc6c-4c0d-98b6-19f4564794ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771416940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2771416940
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1616435425
Short name T72
Test name
Test status
Simulation time 21506347 ps
CPU time 1.13 seconds
Started Jul 19 05:03:02 PM PDT 24
Finished Jul 19 05:03:06 PM PDT 24
Peak memory 211392 kb
Host smart-870d7388-9160-43ad-8ce9-b826eb219933
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616435425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1616435425
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2026219974
Short name T233
Test name
Test status
Simulation time 21492213 ps
CPU time 0.93 seconds
Started Jul 19 05:03:05 PM PDT 24
Finished Jul 19 05:03:09 PM PDT 24
Peak memory 208308 kb
Host smart-12a7a55c-bb46-4325-9ec5-0213e6a096f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026219974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2026219974
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1049833669
Short name T478
Test name
Test status
Simulation time 331706851 ps
CPU time 10.83 seconds
Started Jul 19 05:03:04 PM PDT 24
Finished Jul 19 05:03:17 PM PDT 24
Peak memory 217884 kb
Host smart-81d47421-2373-43f9-b0a1-a40e8011a177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049833669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1049833669
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2590786888
Short name T7
Test name
Test status
Simulation time 404178441 ps
CPU time 11.49 seconds
Started Jul 19 05:03:08 PM PDT 24
Finished Jul 19 05:03:23 PM PDT 24
Peak memory 217228 kb
Host smart-c8d942fa-c292-4c67-b758-1168ae50e211
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590786888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2590786888
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.580818224
Short name T446
Test name
Test status
Simulation time 74234351 ps
CPU time 3.02 seconds
Started Jul 19 05:03:05 PM PDT 24
Finished Jul 19 05:03:10 PM PDT 24
Peak memory 217800 kb
Host smart-691e636f-7ad5-488d-b451-dd975e4beeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580818224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.580818224
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3784935877
Short name T299
Test name
Test status
Simulation time 285974838 ps
CPU time 12.35 seconds
Started Jul 19 05:03:05 PM PDT 24
Finished Jul 19 05:03:21 PM PDT 24
Peak memory 225584 kb
Host smart-d7af8f4c-74c9-41d5-a2d5-cb4f8a49bf9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784935877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3784935877
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1583545470
Short name T286
Test name
Test status
Simulation time 691971569 ps
CPU time 11.24 seconds
Started Jul 19 05:03:04 PM PDT 24
Finished Jul 19 05:03:17 PM PDT 24
Peak memory 225548 kb
Host smart-aafe7e0b-e23f-4a62-b6f0-25a4aee034c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583545470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1583545470
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3082892139
Short name T322
Test name
Test status
Simulation time 383743755 ps
CPU time 14.32 seconds
Started Jul 19 05:03:09 PM PDT 24
Finished Jul 19 05:03:26 PM PDT 24
Peak memory 225448 kb
Host smart-6d7c2c8c-a2f4-467d-81f7-720dd156b32a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082892139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3082892139
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.468213329
Short name T374
Test name
Test status
Simulation time 388861591 ps
CPU time 14.49 seconds
Started Jul 19 05:03:07 PM PDT 24
Finished Jul 19 05:03:24 PM PDT 24
Peak memory 217884 kb
Host smart-23ca1967-4b9c-45f7-b08d-959f43e96cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468213329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.468213329
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3877855147
Short name T801
Test name
Test status
Simulation time 190183591 ps
CPU time 3.07 seconds
Started Jul 19 05:03:04 PM PDT 24
Finished Jul 19 05:03:08 PM PDT 24
Peak memory 217196 kb
Host smart-61234931-9198-408c-9c75-89cf7d1eece1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877855147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3877855147
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.4219798690
Short name T756
Test name
Test status
Simulation time 461662744 ps
CPU time 24.58 seconds
Started Jul 19 05:03:08 PM PDT 24
Finished Jul 19 05:03:36 PM PDT 24
Peak memory 250544 kb
Host smart-6ed36e7a-2e51-4065-b090-38aa84dcfb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219798690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.4219798690
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3650461851
Short name T316
Test name
Test status
Simulation time 919693835 ps
CPU time 6.31 seconds
Started Jul 19 05:03:05 PM PDT 24
Finished Jul 19 05:03:15 PM PDT 24
Peak memory 246636 kb
Host smart-17c3f95a-3d99-44f8-9442-e2ef9cb4852c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650461851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3650461851
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.3095947054
Short name T667
Test name
Test status
Simulation time 49311504302 ps
CPU time 200.99 seconds
Started Jul 19 05:03:09 PM PDT 24
Finished Jul 19 05:06:33 PM PDT 24
Peak memory 283276 kb
Host smart-23132cec-a362-48a2-84ae-1ce7e1fae4c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095947054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.3095947054
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2398377042
Short name T772
Test name
Test status
Simulation time 290450934873 ps
CPU time 962.36 seconds
Started Jul 19 05:03:06 PM PDT 24
Finished Jul 19 05:19:12 PM PDT 24
Peak memory 447280 kb
Host smart-dcc3d512-8cdc-498b-ae54-25ebedba7292
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2398377042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.2398377042
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2278516557
Short name T703
Test name
Test status
Simulation time 44193313 ps
CPU time 1.01 seconds
Started Jul 19 05:03:05 PM PDT 24
Finished Jul 19 05:03:07 PM PDT 24
Peak memory 217404 kb
Host smart-bad4f87f-cd01-48fe-8f74-6e399f3363e7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278516557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2278516557
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.555598602
Short name T507
Test name
Test status
Simulation time 36572628 ps
CPU time 1.12 seconds
Started Jul 19 05:03:07 PM PDT 24
Finished Jul 19 05:03:11 PM PDT 24
Peak memory 208440 kb
Host smart-e11c8875-3e9e-458a-9b9e-97d79c7fbb34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555598602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.555598602
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1078141697
Short name T224
Test name
Test status
Simulation time 366001483 ps
CPU time 7.64 seconds
Started Jul 19 05:03:07 PM PDT 24
Finished Jul 19 05:03:18 PM PDT 24
Peak memory 217948 kb
Host smart-61dc9f40-7e23-446a-bf72-c4eb59b183fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078141697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1078141697
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1510646820
Short name T796
Test name
Test status
Simulation time 63777893 ps
CPU time 1.4 seconds
Started Jul 19 05:03:04 PM PDT 24
Finished Jul 19 05:03:07 PM PDT 24
Peak memory 216532 kb
Host smart-6e15d53b-24ed-4bc4-b8f6-2a57484f0acd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510646820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1510646820
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1381599467
Short name T229
Test name
Test status
Simulation time 108923910 ps
CPU time 1.83 seconds
Started Jul 19 05:03:08 PM PDT 24
Finished Jul 19 05:03:13 PM PDT 24
Peak memory 217816 kb
Host smart-00e5e0fd-d5a9-4264-aab7-565cb07a6319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381599467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1381599467
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1018272568
Short name T589
Test name
Test status
Simulation time 477755425 ps
CPU time 12.99 seconds
Started Jul 19 05:03:08 PM PDT 24
Finished Jul 19 05:03:24 PM PDT 24
Peak memory 218476 kb
Host smart-ba81bd91-2996-4ab8-8d63-9592bfa06467
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018272568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1018272568
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.376422099
Short name T225
Test name
Test status
Simulation time 606630027 ps
CPU time 13.1 seconds
Started Jul 19 05:03:06 PM PDT 24
Finished Jul 19 05:03:22 PM PDT 24
Peak memory 217760 kb
Host smart-6dc97827-223e-4fd9-8541-54cd995eff5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376422099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.376422099
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3769885277
Short name T400
Test name
Test status
Simulation time 413933085 ps
CPU time 10.1 seconds
Started Jul 19 05:03:08 PM PDT 24
Finished Jul 19 05:03:21 PM PDT 24
Peak memory 225536 kb
Host smart-6ba06a96-43bc-4ae3-bbca-cdeefffa9624
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769885277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3769885277
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3540872354
Short name T536
Test name
Test status
Simulation time 1226086100 ps
CPU time 14.13 seconds
Started Jul 19 05:03:05 PM PDT 24
Finished Jul 19 05:03:22 PM PDT 24
Peak memory 217828 kb
Host smart-b91df708-3b43-4965-9c67-da2375014b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540872354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3540872354
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2626035436
Short name T397
Test name
Test status
Simulation time 35447166 ps
CPU time 2.58 seconds
Started Jul 19 05:03:06 PM PDT 24
Finished Jul 19 05:03:12 PM PDT 24
Peak memory 214264 kb
Host smart-1b0dabdb-dde0-45a3-99cd-3ba4327bf9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626035436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2626035436
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.312661077
Short name T274
Test name
Test status
Simulation time 1664206432 ps
CPU time 32.14 seconds
Started Jul 19 05:03:05 PM PDT 24
Finished Jul 19 05:03:40 PM PDT 24
Peak memory 250620 kb
Host smart-982693bf-c978-4307-a834-c97cf2647d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312661077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.312661077
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2573664910
Short name T800
Test name
Test status
Simulation time 110024625 ps
CPU time 7.43 seconds
Started Jul 19 05:03:06 PM PDT 24
Finished Jul 19 05:03:16 PM PDT 24
Peak memory 249992 kb
Host smart-e0644726-35c1-4bdf-a8e0-16352145a3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573664910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2573664910
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.673053417
Short name T593
Test name
Test status
Simulation time 5098934640 ps
CPU time 116.97 seconds
Started Jul 19 05:03:07 PM PDT 24
Finished Jul 19 05:05:07 PM PDT 24
Peak memory 283116 kb
Host smart-a8ec6eee-604b-4a33-9ce9-1940c3b00512
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673053417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.673053417
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.427160498
Short name T344
Test name
Test status
Simulation time 46139547 ps
CPU time 0.95 seconds
Started Jul 19 05:03:06 PM PDT 24
Finished Jul 19 05:03:10 PM PDT 24
Peak memory 211484 kb
Host smart-7381351c-d06c-43a1-bcdd-bd5e175535a0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427160498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct
rl_volatile_unlock_smoke.427160498
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.4005927279
Short name T175
Test name
Test status
Simulation time 40300369 ps
CPU time 1.17 seconds
Started Jul 19 05:03:16 PM PDT 24
Finished Jul 19 05:03:19 PM PDT 24
Peak memory 208436 kb
Host smart-688e7d44-41cd-4cbb-bddc-73242bb102d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005927279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.4005927279
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2458100980
Short name T829
Test name
Test status
Simulation time 455735045 ps
CPU time 15.66 seconds
Started Jul 19 05:03:16 PM PDT 24
Finished Jul 19 05:03:34 PM PDT 24
Peak memory 217768 kb
Host smart-44586a0c-2875-46a5-9958-f8b9911b9f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458100980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2458100980
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1116314606
Short name T32
Test name
Test status
Simulation time 1050544386 ps
CPU time 10.84 seconds
Started Jul 19 05:03:17 PM PDT 24
Finished Jul 19 05:03:30 PM PDT 24
Peak memory 216660 kb
Host smart-bb34401e-8f96-410f-a2d3-f8cd5f744a92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116314606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1116314606
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.4274715957
Short name T173
Test name
Test status
Simulation time 45779061 ps
CPU time 1.51 seconds
Started Jul 19 05:03:16 PM PDT 24
Finished Jul 19 05:03:19 PM PDT 24
Peak memory 221456 kb
Host smart-16be8e9c-bac4-4c3f-b1bc-b9f063000c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274715957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.4274715957
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2957718319
Short name T420
Test name
Test status
Simulation time 4272528691 ps
CPU time 10.06 seconds
Started Jul 19 05:03:18 PM PDT 24
Finished Jul 19 05:03:30 PM PDT 24
Peak memory 217824 kb
Host smart-6c9cbcaa-e289-4dc2-a820-8db4b3883e00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957718319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2957718319
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2495957903
Short name T345
Test name
Test status
Simulation time 255412521 ps
CPU time 10.26 seconds
Started Jul 19 05:03:18 PM PDT 24
Finished Jul 19 05:03:30 PM PDT 24
Peak memory 225496 kb
Host smart-099722f1-af6a-44e1-97eb-c3c93179b31c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495957903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2495957903
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2189358012
Short name T684
Test name
Test status
Simulation time 1510292195 ps
CPU time 11.07 seconds
Started Jul 19 05:03:13 PM PDT 24
Finished Jul 19 05:03:25 PM PDT 24
Peak memory 217876 kb
Host smart-6c5a48ce-efc8-4b10-9b1d-661b8b1a94c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189358012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2189358012
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1834241526
Short name T409
Test name
Test status
Simulation time 46269889 ps
CPU time 2.69 seconds
Started Jul 19 05:03:06 PM PDT 24
Finished Jul 19 05:03:12 PM PDT 24
Peak memory 217212 kb
Host smart-017186e0-eb6a-4258-87a7-3ea68f2becec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834241526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1834241526
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.4241135375
Short name T474
Test name
Test status
Simulation time 265202028 ps
CPU time 25.92 seconds
Started Jul 19 05:03:16 PM PDT 24
Finished Jul 19 05:03:43 PM PDT 24
Peak memory 250528 kb
Host smart-8e1cc9ca-c34c-4585-af55-576324386bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241135375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.4241135375
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2940107251
Short name T491
Test name
Test status
Simulation time 458119633 ps
CPU time 3.53 seconds
Started Jul 19 05:03:17 PM PDT 24
Finished Jul 19 05:03:22 PM PDT 24
Peak memory 222152 kb
Host smart-0655a45d-cc0a-4ace-a075-1c5bf47b4824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940107251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2940107251
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.782492345
Short name T467
Test name
Test status
Simulation time 1438511003 ps
CPU time 62.18 seconds
Started Jul 19 05:03:19 PM PDT 24
Finished Jul 19 05:04:22 PM PDT 24
Peak memory 271016 kb
Host smart-695b9312-347c-4d78-9fe8-e4b7eb2e2add
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782492345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.782492345
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.2058198648
Short name T149
Test name
Test status
Simulation time 97944731360 ps
CPU time 1345.65 seconds
Started Jul 19 05:03:17 PM PDT 24
Finished Jul 19 05:25:45 PM PDT 24
Peak memory 316200 kb
Host smart-94bb1e16-781a-4ef9-9cee-d257a28d3e1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2058198648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.2058198648
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.353514447
Short name T808
Test name
Test status
Simulation time 49300426 ps
CPU time 0.99 seconds
Started Jul 19 05:03:18 PM PDT 24
Finished Jul 19 05:03:21 PM PDT 24
Peak memory 211420 kb
Host smart-f1b317e6-fabd-40f1-a6a5-1524982d9625
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353514447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.353514447
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.824398346
Short name T270
Test name
Test status
Simulation time 20018938 ps
CPU time 0.97 seconds
Started Jul 19 05:03:16 PM PDT 24
Finished Jul 19 05:03:19 PM PDT 24
Peak memory 208336 kb
Host smart-beda8a22-16d0-4245-b78a-57d2bbc463fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824398346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.824398346
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2033335433
Short name T497
Test name
Test status
Simulation time 187696509 ps
CPU time 10.2 seconds
Started Jul 19 05:03:16 PM PDT 24
Finished Jul 19 05:03:28 PM PDT 24
Peak memory 217856 kb
Host smart-4e1cdb49-4c91-4c33-9c06-2a51550234a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033335433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2033335433
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2409114187
Short name T626
Test name
Test status
Simulation time 2438660026 ps
CPU time 2.2 seconds
Started Jul 19 05:03:19 PM PDT 24
Finished Jul 19 05:03:22 PM PDT 24
Peak memory 216596 kb
Host smart-12423607-e066-495a-8a16-9c69e3ec0b7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409114187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2409114187
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3580339157
Short name T347
Test name
Test status
Simulation time 42667205 ps
CPU time 2.11 seconds
Started Jul 19 05:03:19 PM PDT 24
Finished Jul 19 05:03:23 PM PDT 24
Peak memory 217732 kb
Host smart-d16cd24e-e2f7-4905-adc0-720d7ffc057d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580339157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3580339157
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.4101201125
Short name T495
Test name
Test status
Simulation time 1736532352 ps
CPU time 19.42 seconds
Started Jul 19 05:03:15 PM PDT 24
Finished Jul 19 05:03:36 PM PDT 24
Peak memory 225340 kb
Host smart-773df9b8-9d1e-4a73-bb74-c32438955de4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101201125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.4101201125
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1198114580
Short name T661
Test name
Test status
Simulation time 853509397 ps
CPU time 10.45 seconds
Started Jul 19 05:03:14 PM PDT 24
Finished Jul 19 05:03:26 PM PDT 24
Peak memory 225536 kb
Host smart-39650c0d-58c7-40bb-af30-831c75eefac2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198114580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1198114580
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2190491667
Short name T631
Test name
Test status
Simulation time 870309534 ps
CPU time 12.78 seconds
Started Jul 19 05:03:16 PM PDT 24
Finished Jul 19 05:03:30 PM PDT 24
Peak memory 217832 kb
Host smart-7990d51c-266f-4472-a501-b1aa6e83541c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190491667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2190491667
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.40166593
Short name T844
Test name
Test status
Simulation time 23569307 ps
CPU time 1.21 seconds
Started Jul 19 05:03:17 PM PDT 24
Finished Jul 19 05:03:20 PM PDT 24
Peak memory 217208 kb
Host smart-51ff38a7-1353-4912-b85b-c613e67ab3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40166593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.40166593
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2492755005
Short name T696
Test name
Test status
Simulation time 262744114 ps
CPU time 28.52 seconds
Started Jul 19 05:03:14 PM PDT 24
Finished Jul 19 05:03:44 PM PDT 24
Peak memory 245920 kb
Host smart-64046e7c-299f-4b6e-86ae-04127146302c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492755005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2492755005
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.680367298
Short name T729
Test name
Test status
Simulation time 188350706 ps
CPU time 3.49 seconds
Started Jul 19 05:03:18 PM PDT 24
Finished Jul 19 05:03:23 PM PDT 24
Peak memory 222124 kb
Host smart-f28005a1-1428-4ed2-ae08-77eddcf60325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680367298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.680367298
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3546508475
Short name T63
Test name
Test status
Simulation time 3367656914 ps
CPU time 68.21 seconds
Started Jul 19 05:03:18 PM PDT 24
Finished Jul 19 05:04:28 PM PDT 24
Peak memory 225628 kb
Host smart-0020ef7d-7834-46ad-bdb9-5a4b6f97c66f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546508475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3546508475
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.4279313798
Short name T582
Test name
Test status
Simulation time 11900253 ps
CPU time 0.94 seconds
Started Jul 19 05:03:16 PM PDT 24
Finished Jul 19 05:03:18 PM PDT 24
Peak memory 208416 kb
Host smart-a1387e82-39a2-4fbd-b18a-1940152cbc2f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279313798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.4279313798
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3502011704
Short name T500
Test name
Test status
Simulation time 22759988 ps
CPU time 1.05 seconds
Started Jul 19 05:03:25 PM PDT 24
Finished Jul 19 05:03:28 PM PDT 24
Peak memory 208592 kb
Host smart-93fbec84-50d0-4f8b-88e2-fb4b50696d81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502011704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3502011704
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1957724323
Short name T494
Test name
Test status
Simulation time 972374015 ps
CPU time 7.61 seconds
Started Jul 19 05:03:24 PM PDT 24
Finished Jul 19 05:03:33 PM PDT 24
Peak memory 217836 kb
Host smart-28b0f5f0-2444-45c2-8b09-5245558e3ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957724323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1957724323
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1544717097
Short name T850
Test name
Test status
Simulation time 491587005 ps
CPU time 2.18 seconds
Started Jul 19 05:03:34 PM PDT 24
Finished Jul 19 05:03:38 PM PDT 24
Peak memory 216608 kb
Host smart-7b9b82f2-cee6-4521-8aac-bfbf4095cb6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544717097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1544717097
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1151662297
Short name T702
Test name
Test status
Simulation time 89875641 ps
CPU time 2.15 seconds
Started Jul 19 05:03:23 PM PDT 24
Finished Jul 19 05:03:27 PM PDT 24
Peak memory 221832 kb
Host smart-b50c3a65-dd94-424d-88fc-67a5330ad7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151662297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1151662297
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3102122907
Short name T47
Test name
Test status
Simulation time 467429157 ps
CPU time 15.96 seconds
Started Jul 19 05:03:25 PM PDT 24
Finished Jul 19 05:03:43 PM PDT 24
Peak memory 218412 kb
Host smart-00917661-cf3f-4044-a0c9-b7b0befe16b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102122907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3102122907
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.960123455
Short name T358
Test name
Test status
Simulation time 6872151047 ps
CPU time 21.82 seconds
Started Jul 19 05:03:21 PM PDT 24
Finished Jul 19 05:03:44 PM PDT 24
Peak memory 217756 kb
Host smart-bfa10d96-ab5e-4487-88f3-0071c75987f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960123455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.960123455
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.4279536853
Short name T695
Test name
Test status
Simulation time 2848971183 ps
CPU time 11.89 seconds
Started Jul 19 05:03:34 PM PDT 24
Finished Jul 19 05:03:47 PM PDT 24
Peak memory 225608 kb
Host smart-5f0fda70-9109-4049-ad7a-c1057a680f2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279536853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
4279536853
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2041690878
Short name T568
Test name
Test status
Simulation time 1918920544 ps
CPU time 10.5 seconds
Started Jul 19 05:03:23 PM PDT 24
Finished Jul 19 05:03:35 PM PDT 24
Peak memory 217800 kb
Host smart-c2f52b90-8512-4469-acc1-593b4aac0f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041690878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2041690878
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1281483485
Short name T776
Test name
Test status
Simulation time 29305959 ps
CPU time 1.27 seconds
Started Jul 19 05:03:27 PM PDT 24
Finished Jul 19 05:03:30 PM PDT 24
Peak memory 217260 kb
Host smart-ab196231-c776-43b2-80b7-94e2a0316569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281483485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1281483485
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.734050044
Short name T424
Test name
Test status
Simulation time 1754698848 ps
CPU time 29.69 seconds
Started Jul 19 05:03:23 PM PDT 24
Finished Jul 19 05:03:55 PM PDT 24
Peak memory 250492 kb
Host smart-0da75bcf-a7d2-4746-a445-90afc6d10616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734050044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.734050044
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.1277765669
Short name T351
Test name
Test status
Simulation time 996660885 ps
CPU time 9.28 seconds
Started Jul 19 05:03:26 PM PDT 24
Finished Jul 19 05:03:36 PM PDT 24
Peak memory 250548 kb
Host smart-a91facd6-fdbb-4a95-bfea-b2136103da6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277765669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.1277765669
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3429225168
Short name T581
Test name
Test status
Simulation time 11034413596 ps
CPU time 268.21 seconds
Started Jul 19 05:03:27 PM PDT 24
Finished Jul 19 05:07:57 PM PDT 24
Peak memory 283048 kb
Host smart-9f728abd-f03f-44ea-bc0e-96893f77f052
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429225168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3429225168
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.4246740829
Short name T559
Test name
Test status
Simulation time 98782037 ps
CPU time 1.08 seconds
Started Jul 19 05:03:34 PM PDT 24
Finished Jul 19 05:03:36 PM PDT 24
Peak memory 211400 kb
Host smart-0821ad34-5202-4267-89c2-cdaa6e44de8b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246740829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.4246740829
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3155895790
Short name T557
Test name
Test status
Simulation time 43819912 ps
CPU time 0.94 seconds
Started Jul 19 05:03:24 PM PDT 24
Finished Jul 19 05:03:27 PM PDT 24
Peak memory 208420 kb
Host smart-1d8dc5f7-55d5-4ba8-aa7c-6642eae375f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155895790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3155895790
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2998826416
Short name T835
Test name
Test status
Simulation time 327648219 ps
CPU time 15.62 seconds
Started Jul 19 05:03:25 PM PDT 24
Finished Jul 19 05:03:42 PM PDT 24
Peak memory 217948 kb
Host smart-94dabe5c-08e4-4fe1-a34a-990f4be31e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998826416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2998826416
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.363992361
Short name T35
Test name
Test status
Simulation time 1951814787 ps
CPU time 11.73 seconds
Started Jul 19 05:03:27 PM PDT 24
Finished Jul 19 05:03:40 PM PDT 24
Peak memory 216960 kb
Host smart-5aef42cf-1aad-4166-883e-182820512367
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363992361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.363992361
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.89543254
Short name T841
Test name
Test status
Simulation time 185554106 ps
CPU time 3.34 seconds
Started Jul 19 05:03:21 PM PDT 24
Finished Jul 19 05:03:26 PM PDT 24
Peak memory 217756 kb
Host smart-6f6005a3-ebb9-4f25-9895-fc76c00b43a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89543254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.89543254
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.594527491
Short name T516
Test name
Test status
Simulation time 1285537249 ps
CPU time 11.52 seconds
Started Jul 19 05:03:23 PM PDT 24
Finished Jul 19 05:03:36 PM PDT 24
Peak memory 218400 kb
Host smart-21b42321-c6af-411f-940a-0bbad4646087
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594527491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.594527491
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3172126623
Short name T411
Test name
Test status
Simulation time 3838298087 ps
CPU time 13.56 seconds
Started Jul 19 05:03:24 PM PDT 24
Finished Jul 19 05:03:40 PM PDT 24
Peak memory 218444 kb
Host smart-f0e3005d-8021-4938-a931-b58f05d93972
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172126623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3172126623
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.381435507
Short name T839
Test name
Test status
Simulation time 4690100208 ps
CPU time 9.53 seconds
Started Jul 19 05:03:22 PM PDT 24
Finished Jul 19 05:03:33 PM PDT 24
Peak memory 225544 kb
Host smart-b9c22a7b-8706-42fe-9294-94ec6a9597ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381435507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.381435507
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.4241828915
Short name T346
Test name
Test status
Simulation time 2685552966 ps
CPU time 10.57 seconds
Started Jul 19 05:03:27 PM PDT 24
Finished Jul 19 05:03:39 PM PDT 24
Peak memory 217980 kb
Host smart-869cdd7b-78e9-4267-b01c-f7735fcf5452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241828915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.4241828915
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2856478256
Short name T250
Test name
Test status
Simulation time 25662218 ps
CPU time 1.04 seconds
Started Jul 19 05:03:22 PM PDT 24
Finished Jul 19 05:03:24 PM PDT 24
Peak memory 211696 kb
Host smart-b3485ce8-3bde-4296-a61d-324ee9010d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856478256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2856478256
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.4168648532
Short name T643
Test name
Test status
Simulation time 825268759 ps
CPU time 25.34 seconds
Started Jul 19 05:03:22 PM PDT 24
Finished Jul 19 05:03:49 PM PDT 24
Peak memory 250528 kb
Host smart-052f56a4-7a27-40cf-ac8b-60f6b6a9bbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168648532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.4168648532
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.74053501
Short name T379
Test name
Test status
Simulation time 69014804 ps
CPU time 11.02 seconds
Started Jul 19 05:03:21 PM PDT 24
Finished Jul 19 05:03:34 PM PDT 24
Peak memory 250628 kb
Host smart-7675b0ed-d449-4e41-b257-3f9b8d23e523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74053501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.74053501
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.134089851
Short name T387
Test name
Test status
Simulation time 8075066681 ps
CPU time 156.21 seconds
Started Jul 19 05:03:23 PM PDT 24
Finished Jul 19 05:06:00 PM PDT 24
Peak memory 311052 kb
Host smart-5117b455-ac80-4d6e-934e-e2e7804965e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134089851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.134089851
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2900645147
Short name T860
Test name
Test status
Simulation time 15295867 ps
CPU time 0.91 seconds
Started Jul 19 05:03:26 PM PDT 24
Finished Jul 19 05:03:28 PM PDT 24
Peak memory 208392 kb
Host smart-8b16343a-e2ba-4d5e-ad46-8217f8420f0b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900645147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2900645147
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3968382901
Short name T249
Test name
Test status
Simulation time 55882106 ps
CPU time 0.88 seconds
Started Jul 19 05:03:31 PM PDT 24
Finished Jul 19 05:03:34 PM PDT 24
Peak memory 208244 kb
Host smart-27cd4572-88f2-40cd-99a7-1a7f4608f275
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968382901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3968382901
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3725596951
Short name T378
Test name
Test status
Simulation time 226336192 ps
CPU time 11.93 seconds
Started Jul 19 05:03:29 PM PDT 24
Finished Jul 19 05:03:43 PM PDT 24
Peak memory 217832 kb
Host smart-5263256e-46d2-411f-a8ba-c29fc94aff8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725596951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3725596951
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3240440423
Short name T457
Test name
Test status
Simulation time 104018110 ps
CPU time 1.51 seconds
Started Jul 19 05:03:30 PM PDT 24
Finished Jul 19 05:03:34 PM PDT 24
Peak memory 216752 kb
Host smart-045eceea-550a-42ad-a703-66bc8943691c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240440423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3240440423
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1128754624
Short name T537
Test name
Test status
Simulation time 280536131 ps
CPU time 3.21 seconds
Started Jul 19 05:03:34 PM PDT 24
Finished Jul 19 05:03:39 PM PDT 24
Peak memory 217792 kb
Host smart-c21dff0b-c15e-43cc-b5ad-c8344d9248ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128754624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1128754624
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.1779330856
Short name T41
Test name
Test status
Simulation time 853812613 ps
CPU time 11.19 seconds
Started Jul 19 05:03:30 PM PDT 24
Finished Jul 19 05:03:43 PM PDT 24
Peak memory 217996 kb
Host smart-793840b6-f0aa-4b02-ae68-0408aa28cdce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779330856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1779330856
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1047945667
Short name T578
Test name
Test status
Simulation time 878724611 ps
CPU time 7.32 seconds
Started Jul 19 05:03:30 PM PDT 24
Finished Jul 19 05:03:39 PM PDT 24
Peak memory 217820 kb
Host smart-de27263d-2ced-40ec-b1e0-29b6465d6baa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047945667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1047945667
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.685343996
Short name T805
Test name
Test status
Simulation time 469087843 ps
CPU time 7.85 seconds
Started Jul 19 05:03:30 PM PDT 24
Finished Jul 19 05:03:40 PM PDT 24
Peak memory 225536 kb
Host smart-a76e3b17-850a-41ba-bd4b-3ca4cd929da7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685343996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.685343996
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3357356741
Short name T803
Test name
Test status
Simulation time 1829611782 ps
CPU time 10.8 seconds
Started Jul 19 05:03:32 PM PDT 24
Finished Jul 19 05:03:45 PM PDT 24
Peak memory 225552 kb
Host smart-37c10e4f-a073-4e69-ba0b-85c6652b023b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357356741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3357356741
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3173957254
Short name T484
Test name
Test status
Simulation time 182705307 ps
CPU time 2.36 seconds
Started Jul 19 05:03:22 PM PDT 24
Finished Jul 19 05:03:25 PM PDT 24
Peak memory 213896 kb
Host smart-0ba8aa5f-00d7-4324-a4d1-729cbaf4cbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173957254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3173957254
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2562620616
Short name T293
Test name
Test status
Simulation time 253084093 ps
CPU time 33.34 seconds
Started Jul 19 05:03:32 PM PDT 24
Finished Jul 19 05:04:08 PM PDT 24
Peak memory 250508 kb
Host smart-674fa924-3b76-426a-b521-2b35f870b6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562620616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2562620616
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3783003324
Short name T459
Test name
Test status
Simulation time 221391549 ps
CPU time 6.86 seconds
Started Jul 19 05:03:30 PM PDT 24
Finished Jul 19 05:03:38 PM PDT 24
Peak memory 250032 kb
Host smart-a10c4312-9740-4e43-83ab-e9eeb9c16b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783003324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3783003324
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2153546768
Short name T189
Test name
Test status
Simulation time 11358670603 ps
CPU time 109.56 seconds
Started Jul 19 05:03:31 PM PDT 24
Finished Jul 19 05:05:22 PM PDT 24
Peak memory 217328 kb
Host smart-584bd2d0-79e0-44d0-9bae-b2b11bf81a39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153546768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2153546768
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3733563444
Short name T297
Test name
Test status
Simulation time 14767273 ps
CPU time 0.96 seconds
Started Jul 19 05:03:33 PM PDT 24
Finished Jul 19 05:03:36 PM PDT 24
Peak memory 211356 kb
Host smart-34cf254f-2c66-4f8d-9c09-92dabe61de8a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733563444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3733563444
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1402784898
Short name T164
Test name
Test status
Simulation time 39356725 ps
CPU time 0.95 seconds
Started Jul 19 05:03:30 PM PDT 24
Finished Jul 19 05:03:32 PM PDT 24
Peak memory 208412 kb
Host smart-098bb04b-87f9-42ce-a4bf-cd91af6726e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402784898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1402784898
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2848685724
Short name T317
Test name
Test status
Simulation time 2258379217 ps
CPU time 14.08 seconds
Started Jul 19 05:03:31 PM PDT 24
Finished Jul 19 05:03:47 PM PDT 24
Peak memory 217832 kb
Host smart-8d7aea30-3b12-4e6e-9c19-c72bfec61850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848685724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2848685724
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2009464398
Short name T606
Test name
Test status
Simulation time 2272237114 ps
CPU time 13.17 seconds
Started Jul 19 05:03:33 PM PDT 24
Finished Jul 19 05:03:48 PM PDT 24
Peak memory 217028 kb
Host smart-ad49230d-39ed-449a-9aae-36dfc23c2fd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009464398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2009464398
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.52262648
Short name T328
Test name
Test status
Simulation time 59774144 ps
CPU time 1.46 seconds
Started Jul 19 05:03:29 PM PDT 24
Finished Jul 19 05:03:32 PM PDT 24
Peak memory 217804 kb
Host smart-0a1b432f-9aec-48ee-aed3-1cd66067ddc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52262648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.52262648
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3772242807
Short name T443
Test name
Test status
Simulation time 528382252 ps
CPU time 10.1 seconds
Started Jul 19 05:03:31 PM PDT 24
Finished Jul 19 05:03:43 PM PDT 24
Peak memory 225552 kb
Host smart-fe4876a9-33b5-4875-afb5-3ae7dc15135b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772242807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3772242807
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.727334950
Short name T161
Test name
Test status
Simulation time 9822245760 ps
CPU time 19.04 seconds
Started Jul 19 05:03:31 PM PDT 24
Finished Jul 19 05:03:52 PM PDT 24
Peak memory 217880 kb
Host smart-1866174d-32dc-4990-b6a6-15516794703d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727334950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.727334950
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2896236765
Short name T294
Test name
Test status
Simulation time 1277389045 ps
CPU time 13.58 seconds
Started Jul 19 05:03:36 PM PDT 24
Finished Jul 19 05:03:51 PM PDT 24
Peak memory 225544 kb
Host smart-023b0c6a-9802-4147-9fc7-602f6cf48cdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896236765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2896236765
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2341913168
Short name T609
Test name
Test status
Simulation time 793173665 ps
CPU time 8.59 seconds
Started Jul 19 05:03:31 PM PDT 24
Finished Jul 19 05:03:42 PM PDT 24
Peak memory 217820 kb
Host smart-b4ecc223-e2c3-40a0-89b1-397d22fd6f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341913168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2341913168
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.242842046
Short name T38
Test name
Test status
Simulation time 37286086 ps
CPU time 1.98 seconds
Started Jul 19 05:03:36 PM PDT 24
Finished Jul 19 05:03:39 PM PDT 24
Peak memory 222892 kb
Host smart-d0afeef5-5d57-4533-909d-2e6e4b9fe5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242842046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.242842046
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.4010319794
Short name T864
Test name
Test status
Simulation time 264257550 ps
CPU time 24.3 seconds
Started Jul 19 05:03:30 PM PDT 24
Finished Jul 19 05:03:56 PM PDT 24
Peak memory 250500 kb
Host smart-98f38680-b47f-4cba-830f-1448e617a3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010319794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.4010319794
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.4087588561
Short name T825
Test name
Test status
Simulation time 88633448 ps
CPU time 3.65 seconds
Started Jul 19 05:03:32 PM PDT 24
Finished Jul 19 05:03:38 PM PDT 24
Peak memory 225968 kb
Host smart-4a09950e-2a76-44be-8cae-5dd776a7aae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087588561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.4087588561
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1990302673
Short name T86
Test name
Test status
Simulation time 1939917900 ps
CPU time 22.72 seconds
Started Jul 19 05:03:32 PM PDT 24
Finished Jul 19 05:03:57 PM PDT 24
Peak memory 225564 kb
Host smart-b5f41617-0325-484e-ab52-d0a48f6e79ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990302673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1990302673
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.438676915
Short name T147
Test name
Test status
Simulation time 41279265681 ps
CPU time 683.79 seconds
Started Jul 19 05:03:31 PM PDT 24
Finished Jul 19 05:14:57 PM PDT 24
Peak memory 276484 kb
Host smart-5b90e0a2-3b77-4f60-8ded-18b29fbe0302
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=438676915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.438676915
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3385420247
Short name T705
Test name
Test status
Simulation time 80126557 ps
CPU time 0.78 seconds
Started Jul 19 05:03:29 PM PDT 24
Finished Jul 19 05:03:30 PM PDT 24
Peak memory 208492 kb
Host smart-b3eb1724-6eec-4985-aaa3-2d77763e63b9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385420247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3385420247
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.710902851
Short name T298
Test name
Test status
Simulation time 315835589 ps
CPU time 13.06 seconds
Started Jul 19 05:03:31 PM PDT 24
Finished Jul 19 05:03:47 PM PDT 24
Peak memory 217656 kb
Host smart-aafed7e8-d5cf-4c96-a2bc-8c7f4bd7b873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710902851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.710902851
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.3142364979
Short name T271
Test name
Test status
Simulation time 1562453997 ps
CPU time 3.58 seconds
Started Jul 19 05:03:37 PM PDT 24
Finished Jul 19 05:03:41 PM PDT 24
Peak memory 216712 kb
Host smart-9069e486-a1d2-4644-bef5-d1778784f75d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142364979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3142364979
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2122181666
Short name T727
Test name
Test status
Simulation time 912329842 ps
CPU time 13.97 seconds
Started Jul 19 05:03:30 PM PDT 24
Finished Jul 19 05:03:46 PM PDT 24
Peak memory 225596 kb
Host smart-1b064c54-8f17-4e34-9eb3-aa05fa219f69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122181666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2122181666
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.3071002739
Short name T240
Test name
Test status
Simulation time 735315298 ps
CPU time 9.96 seconds
Started Jul 19 05:03:32 PM PDT 24
Finished Jul 19 05:03:44 PM PDT 24
Peak memory 217860 kb
Host smart-30f1858d-e4d2-4189-92c6-b019e23e9663
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071002739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.3071002739
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.510367157
Short name T574
Test name
Test status
Simulation time 322458160 ps
CPU time 11.68 seconds
Started Jul 19 05:03:36 PM PDT 24
Finished Jul 19 05:03:49 PM PDT 24
Peak memory 225548 kb
Host smart-5bff7fdb-b1d2-43ac-84cb-218c1460a966
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510367157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.510367157
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2602137943
Short name T219
Test name
Test status
Simulation time 928068134 ps
CPU time 7.15 seconds
Started Jul 19 05:03:32 PM PDT 24
Finished Jul 19 05:03:41 PM PDT 24
Peak memory 217816 kb
Host smart-d9edbc50-7a8b-43d6-a511-aad9b88aa487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602137943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2602137943
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3877340493
Short name T284
Test name
Test status
Simulation time 160836736 ps
CPU time 2.32 seconds
Started Jul 19 05:03:29 PM PDT 24
Finished Jul 19 05:03:34 PM PDT 24
Peak memory 217168 kb
Host smart-b53e9d1f-9c0d-4792-8a2d-9b977542a480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877340493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3877340493
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1167443823
Short name T50
Test name
Test status
Simulation time 449488320 ps
CPU time 22.03 seconds
Started Jul 19 05:03:29 PM PDT 24
Finished Jul 19 05:03:52 PM PDT 24
Peak memory 246184 kb
Host smart-1b280d48-e4bd-4d6a-887e-9c6ce672a437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167443823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1167443823
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1124912671
Short name T154
Test name
Test status
Simulation time 115347340 ps
CPU time 8.79 seconds
Started Jul 19 05:03:32 PM PDT 24
Finished Jul 19 05:03:43 PM PDT 24
Peak memory 250416 kb
Host smart-1bd14673-cb7e-45b3-b1d5-73d2d34fab08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124912671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1124912671
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3174945535
Short name T639
Test name
Test status
Simulation time 14834472235 ps
CPU time 291.56 seconds
Started Jul 19 05:03:37 PM PDT 24
Finished Jul 19 05:08:29 PM PDT 24
Peak memory 266940 kb
Host smart-c2247110-5f86-458a-a032-6b13dd2bd6c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174945535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3174945535
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.1376327060
Short name T155
Test name
Test status
Simulation time 85859797339 ps
CPU time 371.53 seconds
Started Jul 19 05:03:43 PM PDT 24
Finished Jul 19 05:09:55 PM PDT 24
Peak memory 496440 kb
Host smart-bc61fc02-9424-4f6b-ab62-fc96f4b1c581
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1376327060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.1376327060
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2901835566
Short name T575
Test name
Test status
Simulation time 18708291 ps
CPU time 0.89 seconds
Started Jul 19 05:03:29 PM PDT 24
Finished Jul 19 05:03:31 PM PDT 24
Peak memory 208492 kb
Host smart-1361c650-e2fd-45aa-bf81-24dad70a86ec
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901835566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2901835566
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1994773091
Short name T520
Test name
Test status
Simulation time 69177814 ps
CPU time 0.91 seconds
Started Jul 19 05:00:37 PM PDT 24
Finished Jul 19 05:00:42 PM PDT 24
Peak memory 208348 kb
Host smart-33bd121b-6958-4f3b-8e77-5d5a34b1f72f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994773091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1994773091
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3833862182
Short name T214
Test name
Test status
Simulation time 39628906 ps
CPU time 0.85 seconds
Started Jul 19 05:00:34 PM PDT 24
Finished Jul 19 05:00:38 PM PDT 24
Peak memory 208464 kb
Host smart-30fd00de-7aa3-4b31-8e66-d56a6c5cf298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833862182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3833862182
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.750167089
Short name T264
Test name
Test status
Simulation time 374586291 ps
CPU time 12.48 seconds
Started Jul 19 05:00:35 PM PDT 24
Finished Jul 19 05:00:51 PM PDT 24
Peak memory 217768 kb
Host smart-57797d57-3182-4be3-8eb4-2bb62af3f192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750167089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.750167089
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1373233854
Short name T564
Test name
Test status
Simulation time 402217916 ps
CPU time 3.77 seconds
Started Jul 19 05:00:36 PM PDT 24
Finished Jul 19 05:00:43 PM PDT 24
Peak memory 216708 kb
Host smart-b752d927-cb16-4579-862e-dd431e8b7577
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373233854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1373233854
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.3835347748
Short name T349
Test name
Test status
Simulation time 3336975108 ps
CPU time 28.78 seconds
Started Jul 19 05:00:34 PM PDT 24
Finished Jul 19 05:01:06 PM PDT 24
Peak memory 218044 kb
Host smart-7c27b148-38ca-4107-a029-f240fa1819d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835347748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.3835347748
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.393652726
Short name T826
Test name
Test status
Simulation time 551267739 ps
CPU time 7.85 seconds
Started Jul 19 05:00:40 PM PDT 24
Finished Jul 19 05:00:50 PM PDT 24
Peak memory 217292 kb
Host smart-d199cdcf-cab1-454e-9548-5b6706d9a144
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393652726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.393652726
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3700573592
Short name T628
Test name
Test status
Simulation time 168362484 ps
CPU time 2.14 seconds
Started Jul 19 05:00:35 PM PDT 24
Finished Jul 19 05:00:40 PM PDT 24
Peak memory 221112 kb
Host smart-58126efd-341a-4a76-9a3b-90ca688c7d0c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700573592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3700573592
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3072069868
Short name T641
Test name
Test status
Simulation time 1138354241 ps
CPU time 16.33 seconds
Started Jul 19 05:00:37 PM PDT 24
Finished Jul 19 05:00:56 PM PDT 24
Peak memory 217156 kb
Host smart-70494bdf-1642-4dc3-91c8-6c520c7ec992
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072069868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3072069868
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1042068281
Short name T502
Test name
Test status
Simulation time 800896158 ps
CPU time 8.08 seconds
Started Jul 19 05:00:40 PM PDT 24
Finished Jul 19 05:00:51 PM PDT 24
Peak memory 217088 kb
Host smart-882cab51-dbcf-4e84-9160-c2f91978129b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042068281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1042068281
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1335703246
Short name T518
Test name
Test status
Simulation time 1457408126 ps
CPU time 65.2 seconds
Started Jul 19 05:00:41 PM PDT 24
Finished Jul 19 05:01:48 PM PDT 24
Peak memory 250492 kb
Host smart-a0ae7b3e-cd55-4d84-b560-b44272aa1cb6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335703246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1335703246
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2549132615
Short name T416
Test name
Test status
Simulation time 369201416 ps
CPU time 15.73 seconds
Started Jul 19 05:00:33 PM PDT 24
Finished Jul 19 05:00:52 PM PDT 24
Peak memory 250276 kb
Host smart-0364ae33-33f6-499a-bdb4-bd3240fcf262
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549132615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2549132615
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.4184631164
Short name T464
Test name
Test status
Simulation time 201100396 ps
CPU time 2.49 seconds
Started Jul 19 05:00:36 PM PDT 24
Finished Jul 19 05:00:42 PM PDT 24
Peak memory 217752 kb
Host smart-6d2be5f0-0bed-4e01-bbd6-8f976cd4e33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184631164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.4184631164
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.511406160
Short name T669
Test name
Test status
Simulation time 265128071 ps
CPU time 17.93 seconds
Started Jul 19 05:00:35 PM PDT 24
Finished Jul 19 05:00:57 PM PDT 24
Peak memory 214208 kb
Host smart-835f90c0-08ca-4270-993e-2746f9c79696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511406160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.511406160
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.307072648
Short name T636
Test name
Test status
Simulation time 316732575 ps
CPU time 9.26 seconds
Started Jul 19 05:00:49 PM PDT 24
Finished Jul 19 05:01:00 PM PDT 24
Peak memory 218532 kb
Host smart-ab4062e2-97e1-484d-8c7d-7d40f335f2aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307072648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.307072648
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.101220336
Short name T778
Test name
Test status
Simulation time 2867795348 ps
CPU time 12.85 seconds
Started Jul 19 05:00:35 PM PDT 24
Finished Jul 19 05:00:52 PM PDT 24
Peak memory 217800 kb
Host smart-ce0cee2b-6db6-4f53-a7b1-652c09245d03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101220336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.101220336
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3606496911
Short name T736
Test name
Test status
Simulation time 283727975 ps
CPU time 9.05 seconds
Started Jul 19 05:00:49 PM PDT 24
Finished Jul 19 05:00:59 PM PDT 24
Peak memory 225548 kb
Host smart-b8e3cad8-2fa0-4484-9ca5-1c60dd0755eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606496911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
606496911
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1822869379
Short name T330
Test name
Test status
Simulation time 266283949 ps
CPU time 10.23 seconds
Started Jul 19 05:00:37 PM PDT 24
Finished Jul 19 05:00:50 PM PDT 24
Peak memory 217840 kb
Host smart-b04e9b55-1c1e-4483-a4fa-852ffc2b57fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822869379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1822869379
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3249097549
Short name T79
Test name
Test status
Simulation time 22504551 ps
CPU time 1.59 seconds
Started Jul 19 05:00:36 PM PDT 24
Finished Jul 19 05:00:41 PM PDT 24
Peak memory 213512 kb
Host smart-a3a54ab7-bfa8-4b09-bf8d-e5092c1ec74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249097549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3249097549
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.4015345114
Short name T614
Test name
Test status
Simulation time 194545112 ps
CPU time 21.06 seconds
Started Jul 19 05:00:34 PM PDT 24
Finished Jul 19 05:00:58 PM PDT 24
Peak memory 250448 kb
Host smart-990ec3f7-af72-408f-b181-eac9901b131e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015345114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.4015345114
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.4268530002
Short name T185
Test name
Test status
Simulation time 66058567 ps
CPU time 8.71 seconds
Started Jul 19 05:00:49 PM PDT 24
Finished Jul 19 05:00:59 PM PDT 24
Peak memory 243824 kb
Host smart-2e310431-5199-471b-88b1-0513507114a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268530002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.4268530002
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2056362627
Short name T486
Test name
Test status
Simulation time 2822260178 ps
CPU time 130.88 seconds
Started Jul 19 05:00:41 PM PDT 24
Finished Jul 19 05:02:54 PM PDT 24
Peak memory 267992 kb
Host smart-d6b8f744-2749-4921-ab44-e2a7abe3f600
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056362627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2056362627
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.507571817
Short name T25
Test name
Test status
Simulation time 34704690 ps
CPU time 1 seconds
Started Jul 19 05:00:35 PM PDT 24
Finished Jul 19 05:00:40 PM PDT 24
Peak memory 211364 kb
Host smart-b5121968-9835-4444-a075-cab2aa615a9a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507571817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.507571817
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.649497307
Short name T658
Test name
Test status
Simulation time 45529781 ps
CPU time 1 seconds
Started Jul 19 05:00:41 PM PDT 24
Finished Jul 19 05:00:45 PM PDT 24
Peak memory 208392 kb
Host smart-bed638e8-e436-4bbe-8861-02b5878f17b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649497307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.649497307
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.676739738
Short name T646
Test name
Test status
Simulation time 10615165 ps
CPU time 0.95 seconds
Started Jul 19 05:00:35 PM PDT 24
Finished Jul 19 05:00:39 PM PDT 24
Peak memory 208324 kb
Host smart-5f826724-d01b-4bc4-9424-131764a53c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676739738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.676739738
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2467208191
Short name T53
Test name
Test status
Simulation time 1503116653 ps
CPU time 15.74 seconds
Started Jul 19 05:00:34 PM PDT 24
Finished Jul 19 05:00:53 PM PDT 24
Peak memory 217788 kb
Host smart-c1e4fb0f-bfe5-41c8-9073-7ff122a6704a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467208191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2467208191
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1300416571
Short name T333
Test name
Test status
Simulation time 5346007586 ps
CPU time 11.8 seconds
Started Jul 19 05:02:29 PM PDT 24
Finished Jul 19 05:02:42 PM PDT 24
Peak memory 217084 kb
Host smart-d7ccf31f-868f-48c2-88f7-c6d6225f99b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300416571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1300416571
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3913624890
Short name T797
Test name
Test status
Simulation time 2044091649 ps
CPU time 63.17 seconds
Started Jul 19 05:00:42 PM PDT 24
Finished Jul 19 05:01:48 PM PDT 24
Peak memory 225540 kb
Host smart-47fa9095-9afa-45c2-81d7-e9aee557d02c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913624890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3913624890
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1506382304
Short name T544
Test name
Test status
Simulation time 389869178 ps
CPU time 9.68 seconds
Started Jul 19 05:00:43 PM PDT 24
Finished Jul 19 05:00:55 PM PDT 24
Peak memory 217304 kb
Host smart-3122620d-64c9-4243-a60e-ebfc091616a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506382304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
506382304
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3409819152
Short name T287
Test name
Test status
Simulation time 971228899 ps
CPU time 25.06 seconds
Started Jul 19 05:00:50 PM PDT 24
Finished Jul 19 05:01:17 PM PDT 24
Peak memory 224528 kb
Host smart-8e8d2b6e-19d8-4672-af50-c53f71a9819b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409819152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3409819152
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2736024758
Short name T80
Test name
Test status
Simulation time 1038606959 ps
CPU time 16.82 seconds
Started Jul 19 05:00:44 PM PDT 24
Finished Jul 19 05:01:03 PM PDT 24
Peak memory 217248 kb
Host smart-63103cff-b399-4705-9eda-b8a44058ef30
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736024758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2736024758
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.513326479
Short name T404
Test name
Test status
Simulation time 1207869601 ps
CPU time 7.88 seconds
Started Jul 19 05:00:41 PM PDT 24
Finished Jul 19 05:00:51 PM PDT 24
Peak memory 217092 kb
Host smart-cdccf982-b374-4538-a557-3527c08cd369
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513326479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.513326479
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2050578256
Short name T554
Test name
Test status
Simulation time 3975648879 ps
CPU time 51.09 seconds
Started Jul 19 05:00:37 PM PDT 24
Finished Jul 19 05:01:32 PM PDT 24
Peak memory 250544 kb
Host smart-e8de3efb-edb3-4d5b-8dad-a3c2ab7cc3b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050578256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2050578256
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2934002821
Short name T792
Test name
Test status
Simulation time 1250382706 ps
CPU time 12.26 seconds
Started Jul 19 05:00:42 PM PDT 24
Finished Jul 19 05:00:57 PM PDT 24
Peak memory 250460 kb
Host smart-be0392dd-2918-4207-99d4-1d052d9c731c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934002821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2934002821
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.4041301474
Short name T485
Test name
Test status
Simulation time 88862221 ps
CPU time 2.97 seconds
Started Jul 19 05:00:36 PM PDT 24
Finished Jul 19 05:00:42 PM PDT 24
Peak memory 217772 kb
Host smart-445f5f90-ede9-434b-acb4-525445d896e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041301474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.4041301474
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1300380835
Short name T394
Test name
Test status
Simulation time 231866917 ps
CPU time 9.03 seconds
Started Jul 19 05:00:38 PM PDT 24
Finished Jul 19 05:00:50 PM PDT 24
Peak memory 217216 kb
Host smart-08968a81-fbba-4975-bcb8-bc5b79701deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300380835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1300380835
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3671770238
Short name T862
Test name
Test status
Simulation time 937945991 ps
CPU time 11.01 seconds
Started Jul 19 05:00:43 PM PDT 24
Finished Jul 19 05:00:57 PM PDT 24
Peak memory 217792 kb
Host smart-7aa86213-f572-4ce8-b067-67ab1471fbcd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671770238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3671770238
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2081430133
Short name T558
Test name
Test status
Simulation time 1409176968 ps
CPU time 7.9 seconds
Started Jul 19 05:00:41 PM PDT 24
Finished Jul 19 05:00:52 PM PDT 24
Peak memory 225612 kb
Host smart-349248c7-ac7f-40e1-bb43-72c692e0cb50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081430133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
081430133
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1031518238
Short name T92
Test name
Test status
Simulation time 378696570 ps
CPU time 10.24 seconds
Started Jul 19 05:00:36 PM PDT 24
Finished Jul 19 05:00:50 PM PDT 24
Peak memory 217832 kb
Host smart-e1156fe9-4000-4d64-ba63-9f92b3b457c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031518238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1031518238
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.791879322
Short name T433
Test name
Test status
Simulation time 268502238 ps
CPU time 3.38 seconds
Started Jul 19 05:00:37 PM PDT 24
Finished Jul 19 05:00:43 PM PDT 24
Peak memory 214088 kb
Host smart-455fd43b-1675-4a16-82bb-46f9d5c99123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791879322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.791879322
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.4119748314
Short name T418
Test name
Test status
Simulation time 632185446 ps
CPU time 18.55 seconds
Started Jul 19 05:00:49 PM PDT 24
Finished Jul 19 05:01:09 PM PDT 24
Peak memory 250560 kb
Host smart-6170ec53-77bb-4b20-babe-ebf64f90b8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119748314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.4119748314
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.52863044
Short name T713
Test name
Test status
Simulation time 876689558 ps
CPU time 8.3 seconds
Started Jul 19 05:00:49 PM PDT 24
Finished Jul 19 05:00:59 PM PDT 24
Peak memory 250564 kb
Host smart-37ef32e6-6614-4963-93de-f8fab52486ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52863044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.52863044
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.3499069628
Short name T453
Test name
Test status
Simulation time 12976889221 ps
CPU time 149.88 seconds
Started Jul 19 05:00:50 PM PDT 24
Finished Jul 19 05:03:21 PM PDT 24
Peak memory 277204 kb
Host smart-5f578037-52fb-4d64-a09d-a9b506085180
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499069628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.3499069628
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3548596297
Short name T842
Test name
Test status
Simulation time 23562930 ps
CPU time 1.02 seconds
Started Jul 19 05:00:35 PM PDT 24
Finished Jul 19 05:00:40 PM PDT 24
Peak memory 208612 kb
Host smart-8bd430aa-c71f-4afe-ab52-5e5a94a30567
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548596297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3548596297
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1014459565
Short name T782
Test name
Test status
Simulation time 28311826 ps
CPU time 0.99 seconds
Started Jul 19 05:00:52 PM PDT 24
Finished Jul 19 05:00:55 PM PDT 24
Peak memory 208412 kb
Host smart-adc7e776-dc9a-4add-b8ad-bad53a947745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014459565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1014459565
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2935868097
Short name T733
Test name
Test status
Simulation time 28268613 ps
CPU time 0.91 seconds
Started Jul 19 05:00:41 PM PDT 24
Finished Jul 19 05:00:44 PM PDT 24
Peak memory 208180 kb
Host smart-4a7ef126-b47e-4ac5-88d7-49a63db702aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935868097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2935868097
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.241615251
Short name T622
Test name
Test status
Simulation time 1819604163 ps
CPU time 13.25 seconds
Started Jul 19 05:00:50 PM PDT 24
Finished Jul 19 05:01:05 PM PDT 24
Peak memory 217824 kb
Host smart-9460b879-fb6e-4cfb-94b4-e0cd80ea84ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241615251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.241615251
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2901526103
Short name T33
Test name
Test status
Simulation time 1767959530 ps
CPU time 7.43 seconds
Started Jul 19 05:00:51 PM PDT 24
Finished Jul 19 05:01:01 PM PDT 24
Peak memory 216924 kb
Host smart-c026c0e0-a197-413b-8574-9100facd420a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901526103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2901526103
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.4060027834
Short name T534
Test name
Test status
Simulation time 9689705374 ps
CPU time 39.17 seconds
Started Jul 19 05:00:50 PM PDT 24
Finished Jul 19 05:01:30 PM PDT 24
Peak memory 218164 kb
Host smart-9f3bf20d-6930-40c6-9b42-64b6d7014d2c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060027834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.4060027834
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3344484808
Short name T307
Test name
Test status
Simulation time 4789231297 ps
CPU time 7.04 seconds
Started Jul 19 05:00:52 PM PDT 24
Finished Jul 19 05:01:01 PM PDT 24
Peak memory 217344 kb
Host smart-e8c863c1-6e34-4417-a323-86395c9212b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344484808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
344484808
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1466971041
Short name T221
Test name
Test status
Simulation time 60751844 ps
CPU time 2.64 seconds
Started Jul 19 05:00:50 PM PDT 24
Finished Jul 19 05:00:55 PM PDT 24
Peak memory 221060 kb
Host smart-76a5c475-a3f7-4727-b0d3-3d89769d2063
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466971041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1466971041
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3866916432
Short name T180
Test name
Test status
Simulation time 4209763269 ps
CPU time 14.1 seconds
Started Jul 19 05:00:53 PM PDT 24
Finished Jul 19 05:01:10 PM PDT 24
Peak memory 217176 kb
Host smart-0e77d6c7-c318-492a-b14d-bc9723381a12
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866916432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3866916432
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3414218341
Short name T612
Test name
Test status
Simulation time 514353103 ps
CPU time 12.82 seconds
Started Jul 19 05:00:50 PM PDT 24
Finished Jul 19 05:01:05 PM PDT 24
Peak memory 216532 kb
Host smart-14c2816c-0674-420f-935e-372ac6c8fd24
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414218341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3414218341
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1430577923
Short name T275
Test name
Test status
Simulation time 1437053348 ps
CPU time 63.61 seconds
Started Jul 19 05:02:31 PM PDT 24
Finished Jul 19 05:03:37 PM PDT 24
Peak memory 273788 kb
Host smart-2c39152a-6900-41ab-ae71-55272282deac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430577923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1430577923
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3477420530
Short name T244
Test name
Test status
Simulation time 2303224353 ps
CPU time 12.41 seconds
Started Jul 19 05:02:31 PM PDT 24
Finished Jul 19 05:02:45 PM PDT 24
Peak memory 247160 kb
Host smart-a850cc6c-bd1d-4181-8378-c3ea12b29784
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477420530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3477420530
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.320916818
Short name T769
Test name
Test status
Simulation time 40300933 ps
CPU time 2.11 seconds
Started Jul 19 05:00:42 PM PDT 24
Finished Jul 19 05:00:46 PM PDT 24
Peak memory 217884 kb
Host smart-721f3a7b-bb84-4a42-bb9e-1c0869e25f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320916818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.320916818
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1562893349
Short name T369
Test name
Test status
Simulation time 1165632203 ps
CPU time 7.4 seconds
Started Jul 19 05:00:44 PM PDT 24
Finished Jul 19 05:00:53 PM PDT 24
Peak memory 217180 kb
Host smart-85d93c28-a590-4a01-b476-63bc057ec98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562893349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1562893349
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2402914026
Short name T52
Test name
Test status
Simulation time 342636794 ps
CPU time 11.54 seconds
Started Jul 19 05:00:54 PM PDT 24
Finished Jul 19 05:01:08 PM PDT 24
Peak memory 225584 kb
Host smart-96af7b7f-8765-4398-8369-fa0193233ce3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402914026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2402914026
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.688695406
Short name T819
Test name
Test status
Simulation time 758316566 ps
CPU time 10.98 seconds
Started Jul 19 05:00:51 PM PDT 24
Finished Jul 19 05:01:04 PM PDT 24
Peak memory 217788 kb
Host smart-f62bf8d1-ac38-4083-bf1c-675d331acd58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688695406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.688695406
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.619593500
Short name T395
Test name
Test status
Simulation time 323869243 ps
CPU time 9.15 seconds
Started Jul 19 05:00:53 PM PDT 24
Finished Jul 19 05:01:05 PM PDT 24
Peak memory 217728 kb
Host smart-b33b5b22-058b-413d-8c0f-8215f2e874c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619593500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.619593500
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.3430302552
Short name T492
Test name
Test status
Simulation time 174945656 ps
CPU time 7.8 seconds
Started Jul 19 05:00:41 PM PDT 24
Finished Jul 19 05:00:51 PM PDT 24
Peak memory 217884 kb
Host smart-15612c9e-448c-4b6a-b4b1-242e12a055fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430302552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3430302552
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1853942776
Short name T718
Test name
Test status
Simulation time 113317836 ps
CPU time 2.76 seconds
Started Jul 19 05:02:18 PM PDT 24
Finished Jul 19 05:02:25 PM PDT 24
Peak memory 216240 kb
Host smart-48ea2aca-fd46-4b02-9f43-c8b358abba3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853942776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1853942776
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1877243178
Short name T176
Test name
Test status
Simulation time 193369312 ps
CPU time 25.19 seconds
Started Jul 19 05:00:43 PM PDT 24
Finished Jul 19 05:01:11 PM PDT 24
Peak memory 250624 kb
Host smart-76414007-f098-47fe-8a4d-79c8127ffa51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877243178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1877243178
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2337785372
Short name T541
Test name
Test status
Simulation time 357232745 ps
CPU time 8.82 seconds
Started Jul 19 05:00:40 PM PDT 24
Finished Jul 19 05:00:52 PM PDT 24
Peak memory 250552 kb
Host smart-86b588fd-6812-4447-94e6-625550352c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337785372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2337785372
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.187817023
Short name T496
Test name
Test status
Simulation time 39271896979 ps
CPU time 290.02 seconds
Started Jul 19 05:00:55 PM PDT 24
Finished Jul 19 05:05:46 PM PDT 24
Peak memory 307968 kb
Host smart-5bbd6dc1-37d8-464f-a246-26e4f2b45e69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187817023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.187817023
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.4253626696
Short name T108
Test name
Test status
Simulation time 7785415164 ps
CPU time 218.55 seconds
Started Jul 19 05:00:51 PM PDT 24
Finished Jul 19 05:04:32 PM PDT 24
Peak memory 348896 kb
Host smart-0f4d32ae-2e67-4da5-8a4d-535f918280cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4253626696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.4253626696
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.849462045
Short name T257
Test name
Test status
Simulation time 116460104 ps
CPU time 1.08 seconds
Started Jul 19 05:00:42 PM PDT 24
Finished Jul 19 05:00:46 PM PDT 24
Peak memory 217196 kb
Host smart-896f6d33-ddff-424d-9046-d9e03e8015ac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849462045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.849462045
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.644778663
Short name T857
Test name
Test status
Simulation time 50682326 ps
CPU time 0.8 seconds
Started Jul 19 05:00:53 PM PDT 24
Finished Jul 19 05:00:56 PM PDT 24
Peak memory 208164 kb
Host smart-6b19cc66-5188-41ff-9e6d-d380f19e6cae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644778663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.644778663
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.2846196875
Short name T522
Test name
Test status
Simulation time 957610526 ps
CPU time 14.82 seconds
Started Jul 19 05:00:51 PM PDT 24
Finished Jul 19 05:01:08 PM PDT 24
Peak memory 217824 kb
Host smart-fdc5cc5b-a410-4068-8795-ec8796224d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846196875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2846196875
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1321827318
Short name T435
Test name
Test status
Simulation time 1104613675 ps
CPU time 7.89 seconds
Started Jul 19 05:00:52 PM PDT 24
Finished Jul 19 05:01:02 PM PDT 24
Peak memory 216940 kb
Host smart-9b984c07-266a-4b64-99e1-721c4ea0e4dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321827318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1321827318
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1454844417
Short name T54
Test name
Test status
Simulation time 1874858907 ps
CPU time 32.54 seconds
Started Jul 19 05:00:54 PM PDT 24
Finished Jul 19 05:01:28 PM PDT 24
Peak memory 217796 kb
Host smart-342dc883-0e79-42b2-a1ce-ac0cb42dcaad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454844417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1454844417
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2721703006
Short name T336
Test name
Test status
Simulation time 3015390881 ps
CPU time 6.24 seconds
Started Jul 19 05:00:54 PM PDT 24
Finished Jul 19 05:01:02 PM PDT 24
Peak memory 217316 kb
Host smart-6b0052f7-71d1-493a-b679-a9fbad4106e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721703006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
721703006
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.560176498
Short name T638
Test name
Test status
Simulation time 926589083 ps
CPU time 8.23 seconds
Started Jul 19 05:00:51 PM PDT 24
Finished Jul 19 05:01:02 PM PDT 24
Peak memory 222628 kb
Host smart-4a79c5a4-0642-48a9-9882-500907ed0d4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560176498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.560176498
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2097914954
Short name T791
Test name
Test status
Simulation time 1222859761 ps
CPU time 8.38 seconds
Started Jul 19 05:00:52 PM PDT 24
Finished Jul 19 05:01:03 PM PDT 24
Peak memory 217104 kb
Host smart-8d437499-0c3a-4809-9e18-c7b6dcda69a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097914954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2097914954
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1833598232
Short name T649
Test name
Test status
Simulation time 11885702846 ps
CPU time 55.64 seconds
Started Jul 19 05:00:50 PM PDT 24
Finished Jul 19 05:01:48 PM PDT 24
Peak memory 277240 kb
Host smart-cf131e0c-7392-4030-bf06-3d6182fa3e0f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833598232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1833598232
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1404367
Short name T732
Test name
Test status
Simulation time 1300333921 ps
CPU time 11.94 seconds
Started Jul 19 05:00:52 PM PDT 24
Finished Jul 19 05:01:07 PM PDT 24
Peak memory 249988 kb
Host smart-0bb491d8-3e8a-4b44-90e3-8be27e7c0f8b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_st
ate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_post_trans.1404367
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.51860000
Short name T263
Test name
Test status
Simulation time 19004852 ps
CPU time 1.75 seconds
Started Jul 19 05:00:53 PM PDT 24
Finished Jul 19 05:00:57 PM PDT 24
Peak memory 217752 kb
Host smart-a70571dc-dced-4121-9e77-dc27b7d221d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51860000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.51860000
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1844780761
Short name T295
Test name
Test status
Simulation time 1100274284 ps
CPU time 10.47 seconds
Started Jul 19 05:00:54 PM PDT 24
Finished Jul 19 05:01:06 PM PDT 24
Peak memory 213616 kb
Host smart-9f44a379-b0f4-46db-b18b-fffa7aabbff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844780761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1844780761
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.1472119209
Short name T235
Test name
Test status
Simulation time 360663716 ps
CPU time 17.36 seconds
Started Jul 19 05:00:53 PM PDT 24
Finished Jul 19 05:01:13 PM PDT 24
Peak memory 218524 kb
Host smart-52849932-201f-4ca8-b475-c590ccda2524
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472119209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1472119209
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3120921649
Short name T540
Test name
Test status
Simulation time 1207189466 ps
CPU time 10.98 seconds
Started Jul 19 05:00:52 PM PDT 24
Finished Jul 19 05:01:06 PM PDT 24
Peak memory 217776 kb
Host smart-3c620a86-5953-4bbf-878b-3c71a9bbee41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120921649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3120921649
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.4198831576
Short name T306
Test name
Test status
Simulation time 989783189 ps
CPU time 8.02 seconds
Started Jul 19 05:00:53 PM PDT 24
Finished Jul 19 05:01:04 PM PDT 24
Peak memory 225528 kb
Host smart-2f5cafb3-b5ab-4858-871c-d4d4fd1ec68d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198831576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.4
198831576
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3055009893
Short name T748
Test name
Test status
Simulation time 228314941 ps
CPU time 7.13 seconds
Started Jul 19 05:00:51 PM PDT 24
Finished Jul 19 05:00:59 PM PDT 24
Peak memory 217824 kb
Host smart-821b58b7-4510-42dd-8b3e-a8fdbed4f2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055009893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3055009893
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3753148307
Short name T361
Test name
Test status
Simulation time 33961501 ps
CPU time 1.64 seconds
Started Jul 19 05:00:53 PM PDT 24
Finished Jul 19 05:00:57 PM PDT 24
Peak memory 213492 kb
Host smart-ed0f3077-cb91-4dd6-97c4-c5303903cf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753148307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3753148307
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.4075539066
Short name T555
Test name
Test status
Simulation time 642932662 ps
CPU time 31.59 seconds
Started Jul 19 05:00:52 PM PDT 24
Finished Jul 19 05:01:26 PM PDT 24
Peak memory 250516 kb
Host smart-f65f3228-42fc-4f61-b432-b47f53088932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075539066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.4075539066
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3735203233
Short name T553
Test name
Test status
Simulation time 1159705756 ps
CPU time 8.95 seconds
Started Jul 19 05:00:53 PM PDT 24
Finished Jul 19 05:01:04 PM PDT 24
Peak memory 250688 kb
Host smart-bc5677f6-b4f0-4396-bea8-f33a199fe737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735203233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3735203233
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.739024403
Short name T579
Test name
Test status
Simulation time 3180611836 ps
CPU time 84.69 seconds
Started Jul 19 05:00:50 PM PDT 24
Finished Jul 19 05:02:17 PM PDT 24
Peak memory 267084 kb
Host smart-61b55400-8ee9-4d3d-8725-e12fbd5af824
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739024403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.739024403
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.87996577
Short name T563
Test name
Test status
Simulation time 12855036 ps
CPU time 0.95 seconds
Started Jul 19 05:00:53 PM PDT 24
Finished Jul 19 05:00:56 PM PDT 24
Peak memory 208504 kb
Host smart-cccddd67-ccc0-40b9-ac77-6d19c23a5a92
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87996577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_volatile_unlock_smoke.87996577
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3099550021
Short name T187
Test name
Test status
Simulation time 102153450 ps
CPU time 1.31 seconds
Started Jul 19 05:00:59 PM PDT 24
Finished Jul 19 05:01:01 PM PDT 24
Peak memory 208496 kb
Host smart-85c3fed3-2a3d-4d12-a4a6-82b1ae6b04fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099550021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3099550021
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1271483306
Short name T215
Test name
Test status
Simulation time 11932446 ps
CPU time 0.88 seconds
Started Jul 19 05:01:00 PM PDT 24
Finished Jul 19 05:01:02 PM PDT 24
Peak memory 208208 kb
Host smart-99b23db1-5910-430a-9ace-55e5b9235375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271483306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1271483306
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.20189072
Short name T26
Test name
Test status
Simulation time 1118752631 ps
CPU time 11.12 seconds
Started Jul 19 05:00:58 PM PDT 24
Finished Jul 19 05:01:10 PM PDT 24
Peak memory 217808 kb
Host smart-2acd4f70-bdac-490e-b89b-69907c3030bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20189072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.20189072
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.2435087206
Short name T506
Test name
Test status
Simulation time 688085868 ps
CPU time 5.1 seconds
Started Jul 19 05:01:04 PM PDT 24
Finished Jul 19 05:01:11 PM PDT 24
Peak memory 216568 kb
Host smart-4c9614c8-3c2f-4539-ad99-1e332b9d2030
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435087206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2435087206
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.4183533669
Short name T592
Test name
Test status
Simulation time 2563465711 ps
CPU time 35.83 seconds
Started Jul 19 05:01:00 PM PDT 24
Finished Jul 19 05:01:37 PM PDT 24
Peak memory 217812 kb
Host smart-cdcd3155-170d-4162-94ef-67245b72d98e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183533669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.4183533669
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2233140460
Short name T188
Test name
Test status
Simulation time 2239987177 ps
CPU time 3.79 seconds
Started Jul 19 05:00:59 PM PDT 24
Finished Jul 19 05:01:04 PM PDT 24
Peak memory 217252 kb
Host smart-f8464364-ec19-4351-afeb-0928b4ed574b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233140460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
233140460
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2527587377
Short name T362
Test name
Test status
Simulation time 554557076 ps
CPU time 7.72 seconds
Started Jul 19 05:01:01 PM PDT 24
Finished Jul 19 05:01:11 PM PDT 24
Peak memory 222780 kb
Host smart-ed97dc49-fbf1-4c8a-810d-38d62cb5709a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527587377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2527587377
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2354561268
Short name T763
Test name
Test status
Simulation time 3701158534 ps
CPU time 27.61 seconds
Started Jul 19 05:00:58 PM PDT 24
Finished Jul 19 05:01:27 PM PDT 24
Peak memory 217232 kb
Host smart-fea0f104-ffc0-4edd-b5fc-d2366f01494d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354561268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2354561268
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3874974307
Short name T380
Test name
Test status
Simulation time 157787437 ps
CPU time 5.41 seconds
Started Jul 19 05:00:59 PM PDT 24
Finished Jul 19 05:01:06 PM PDT 24
Peak memory 217044 kb
Host smart-fedde813-ee2a-4851-853c-b1395f0df0ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874974307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3874974307
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1423724947
Short name T824
Test name
Test status
Simulation time 2620581894 ps
CPU time 41.07 seconds
Started Jul 19 05:00:59 PM PDT 24
Finished Jul 19 05:01:42 PM PDT 24
Peak memory 266984 kb
Host smart-e1fcb08b-ee70-4d12-9ef6-1acf9fa641af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423724947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1423724947
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1183835493
Short name T670
Test name
Test status
Simulation time 369651380 ps
CPU time 11.89 seconds
Started Jul 19 05:01:01 PM PDT 24
Finished Jul 19 05:01:14 PM PDT 24
Peak memory 245832 kb
Host smart-a41c4e29-3f91-47d7-a9b0-666de9667f86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183835493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1183835493
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3803192474
Short name T847
Test name
Test status
Simulation time 72963920 ps
CPU time 2.98 seconds
Started Jul 19 05:00:58 PM PDT 24
Finished Jul 19 05:01:02 PM PDT 24
Peak memory 217812 kb
Host smart-f93962fa-10db-4600-aac1-4aaec01c9d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803192474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3803192474
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2035789642
Short name T629
Test name
Test status
Simulation time 1013702834 ps
CPU time 10.17 seconds
Started Jul 19 05:01:03 PM PDT 24
Finished Jul 19 05:01:16 PM PDT 24
Peak memory 217164 kb
Host smart-03ca93e4-0d63-4343-877d-7e00b11ca2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035789642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2035789642
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.4012092762
Short name T538
Test name
Test status
Simulation time 2105904085 ps
CPU time 12.13 seconds
Started Jul 19 05:01:01 PM PDT 24
Finished Jul 19 05:01:15 PM PDT 24
Peak memory 225560 kb
Host smart-7008aeae-5fc8-4070-83a6-63df6d92da9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012092762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.4012092762
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3896688883
Short name T29
Test name
Test status
Simulation time 491359284 ps
CPU time 9.04 seconds
Started Jul 19 05:01:00 PM PDT 24
Finished Jul 19 05:01:11 PM PDT 24
Peak memory 217800 kb
Host smart-d4115322-a9f4-4f27-8774-63bf251c70d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896688883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3896688883
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3956847480
Short name T447
Test name
Test status
Simulation time 3397441062 ps
CPU time 7.38 seconds
Started Jul 19 05:01:01 PM PDT 24
Finished Jul 19 05:01:10 PM PDT 24
Peak memory 225596 kb
Host smart-7450844a-ed5e-4551-87d2-a3ae939194f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956847480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
956847480
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3991183706
Short name T832
Test name
Test status
Simulation time 281213489 ps
CPU time 7.58 seconds
Started Jul 19 05:01:01 PM PDT 24
Finished Jul 19 05:01:11 PM PDT 24
Peak memory 224656 kb
Host smart-165eab19-b84e-420b-a57b-e7304372b583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991183706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3991183706
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.785369553
Short name T624
Test name
Test status
Simulation time 14472958 ps
CPU time 1 seconds
Started Jul 19 05:00:54 PM PDT 24
Finished Jul 19 05:00:57 PM PDT 24
Peak memory 211452 kb
Host smart-8b7d00b1-0d59-4ae8-873c-67c07c849fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785369553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.785369553
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3801865097
Short name T480
Test name
Test status
Simulation time 2539084037 ps
CPU time 17.61 seconds
Started Jul 19 05:01:01 PM PDT 24
Finished Jul 19 05:01:20 PM PDT 24
Peak memory 250752 kb
Host smart-0aa2c550-0828-45be-82f2-17d652c0111a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801865097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3801865097
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.234506021
Short name T49
Test name
Test status
Simulation time 337412538 ps
CPU time 3.04 seconds
Started Jul 19 05:01:01 PM PDT 24
Finished Jul 19 05:01:06 PM PDT 24
Peak memory 222120 kb
Host smart-be197aad-6ab2-40bc-8810-777b1970027d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234506021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.234506021
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.854710973
Short name T65
Test name
Test status
Simulation time 7528228776 ps
CPU time 170.45 seconds
Started Jul 19 05:01:01 PM PDT 24
Finished Jul 19 05:03:53 PM PDT 24
Peak memory 275792 kb
Host smart-d262ab22-61ac-4268-9063-19744fa2e87d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854710973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.854710973
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.191248149
Short name T285
Test name
Test status
Simulation time 76356166 ps
CPU time 1.29 seconds
Started Jul 19 05:00:58 PM PDT 24
Finished Jul 19 05:01:00 PM PDT 24
Peak memory 217220 kb
Host smart-e464e87f-f8d6-4b73-a735-09ea5247dcb9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191248149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.191248149
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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