Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86196186

1

T1

38306

T2

1376

T3

1458

auto[1]

1299138

1

T4

8164

T5

297

T6

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86181919

1

T1

38306

T2

1376

T3

1458

auto[1]

1313405

1

T4

8426

T5

198

T6

495

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6564942	1			T1	80		T2	93		T3	69
auto[IdleSt]	19315546	1			T1	38226		T2	161		T3	153
auto[ClkMuxSt]	31601	1			T2	1		T3	1		T4	68
auto[CntIncrSt]	31397	1			T2	1		T3	1		T4	66
auto[CntProgSt]	1334133	1			T2	286		T3	5		T4	121
auto[TransCheckSt]	24441	1			T2	1		T3	1		T4	47
auto[TokenHashSt]	30583700	1			T2	10		T3	14		T4	316
auto[FlashRmaSt]	30740	1			T2	1		T3	1		T4	55
auto[TokenCheck0St]	10728	1			T2	1		T3	1		T4	18
auto[TokenCheck1St]	7888	1			T2	1		T3	1		T4	18
auto[TransProgSt]	270293	1			T2	124		T3	3		T4	32
auto[PostTransSt]	11634934	1			T2	696		T3	1208		T12	725
auto[ScrapSt]	185599	1			T20	351		T41	9		T42	392
auto[EscalateSt]	6366777	1			T4	12821		T5	1228		T6	933
auto[InvalidSt]	11100737	1			T5	683		T16	1745		T18	1126

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1868	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11100737	1			T5	683		T16	1745		T18	1126
EscalateSt	6366777	1			T4	12821		T5	1228		T6	933
ScrapSt	185599	1			T20	351		T41	9		T42	392
PostTransSt	11634934	1			T2	696		T3	1208		T12	725
TransProgSt	270293	1			T2	124		T3	3		T4	32
TokenCheck1St	7888	1			T2	1		T3	1		T4	18
TokenCheck0St	10728	1			T2	1		T3	1		T4	18
FlashRmaSt	30740	1			T2	1		T3	1		T4	55
TokenHashSt	30583700	1			T2	10		T3	14		T4	316
TransCheckSt	24441	1			T2	1		T3	1		T4	47
CntProgSt	1334133	1			T2	286		T3	5		T4	121
CntIncrSt	31397	1			T2	1		T3	1		T4	66
ClkMuxSt	31601	1			T2	1		T3	1		T4	68
IdleSt	19315546	1			T1	38226		T2	161		T3	153
ResetSt	6564942	1			T1	80		T2	93		T3	69
arcs[ResetSt=>IdleSt]	48592	1			T1	1		T2	1		T3	1
arcs[IdleSt=>ScrapSt]	256	1			T20	1		T41	3		T42	1
arcs[IdleSt=>ClkMuxSt]	31465	1			T2	1		T3	1		T4	68
arcs[ClkMuxSt=>CntIncrSt]	31397	1			T2	1		T3	1		T4	66
arcs[CntIncrSt=>PostTransSt]	1552	1			T6	10		T11	12		T32	8
arcs[CntIncrSt=>CntProgSt]	29778	1			T2	1		T3	1		T4	63
arcs[CntProgSt=>PostTransSt]	4355	1			T6	7		T15	7		T7	12
arcs[CntProgSt=>TransCheckSt]	24441	1			T2	1		T3	1		T4	47
arcs[TransCheckSt=>PostTransSt]	3395	1			T6	18		T11	10		T32	5
arcs[TransCheckSt=>TokenHashSt]	20879	1			T2	1		T3	1		T4	42
arcs[TokenHashSt=>PostTransSt]	9278	1			T6	43		T16	7		T19	10
arcs[TokenHashSt=>FlashRmaSt]	10832	1			T2	1		T3	1		T4	22
arcs[FlashRmaSt=>TokenCheck0St]	10728	1			T2	1		T3	1		T4	18
arcs[TokenCheck0St=>PostTransSt]	2813	1			T6	5		T16	12		T19	17
arcs[TokenCheck0St=>TokenCheck1St]	7888	1			T2	1		T3	1		T4	18
arcs[TokenCheck1St=>PostTransSt]	556	1			T11	1		T32	1		T37	7
arcs[TransProgSt=>PostTransSt]	6514	1			T2	1		T3	1		T4	7
arcs[IdleSt=>EscalateSt]	164	1			T41	6		T51	3		T53	8
arcs[ClkMuxSt=>EscalateSt]	68	1			T4	2		T41	1		T51	3
arcs[CntIncrSt=>EscalateSt]	67	1			T4	3		T51	1		T52	1
arcs[CntProgSt=>EscalateSt]	982	1			T4	16		T41	14		T51	21
arcs[TransCheckSt=>EscalateSt]	167	1			T4	5		T53	6		T58	6
arcs[TokenHashSt=>EscalateSt]	769	1			T4	20		T41	5		T51	8
arcs[FlashRmaSt=>EscalateSt]	104	1			T4	4		T41	1		T51	1
arcs[TokenCheck0St=>EscalateSt]	27	1			T55	1		T56	2		T57	2
arcs[TokenCheck1St=>EscalateSt]	127	1			T41	2		T53	2		T52	3
arcs[TransProgSt=>EscalateSt]	691	1			T4	11		T41	17		T51	15
arcs[PostTransSt=>EscalateSt]	4643	1			T4	7		T6	7		T15	7
arcs[InvalidSt=>EscalateSt]	12825	1			T5	5		T16	9		T18	6

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6564764	1			T1	80		T2	93		T3	69
auto[0]	auto[IdleSt]	19315445	1			T1	38226		T2	161		T3	153
auto[0]	auto[ClkMuxSt]	31556	1			T2	1		T3	1		T4	67
auto[0]	auto[CntIncrSt]	31353	1			T2	1		T3	1		T4	64
auto[0]	auto[CntProgSt]	1333470	1			T2	286		T3	5		T4	108
auto[0]	auto[TransCheckSt]	24327	1			T2	1		T3	1		T4	44
auto[0]	auto[TokenHashSt]	30583220	1			T2	10		T3	14		T4	303
auto[0]	auto[FlashRmaSt]	30675	1			T2	1		T3	1		T4	54
auto[0]	auto[TokenCheck0St]	10711	1			T2	1		T3	1		T4	18
auto[0]	auto[TokenCheck1St]	7800	1			T2	1		T3	1		T4	18
auto[0]	auto[TransProgSt]	269829	1			T2	124		T3	3		T4	27
auto[0]	auto[PostTransSt]	11632592	1			T2	696		T3	1208		T12	725
auto[0]	auto[ScrapSt]	185541	1			T20	351		T41	8		T42	392
auto[0]	auto[EscalateSt]	5078729	1			T4	4706		T5	934		T6	737
auto[0]	auto[InvalidSt]	11094306	1			T5	680		T16	1741		T18	1124
auto[1]	auto[ResetSt]	178	1			T4	6		T41	2		T51	2
auto[1]	auto[IdleSt]	101	1			T41	3		T51	2		T53	4
auto[1]	auto[ClkMuxSt]	45	1			T4	1		T41	1		T51	2
auto[1]	auto[CntIncrSt]	44	1			T4	2		T51	1		T211	1
auto[1]	auto[CntProgSt]	663	1			T4	13		T41	9		T51	14
auto[1]	auto[TransCheckSt]	114	1			T4	3		T53	4		T58	4
auto[1]	auto[TokenHashSt]	480	1			T4	13		T41	2		T51	2
auto[1]	auto[FlashRmaSt]	65	1			T4	1		T41	1		T51	1
auto[1]	auto[TokenCheck0St]	17	1			T56	1		T57	1		T212	1
auto[1]	auto[TokenCheck1St]	88	1			T41	2		T53	2		T52	3
auto[1]	auto[TransProgSt]	464	1			T4	5		T41	9		T51	11
auto[1]	auto[PostTransSt]	2342	1			T4	5		T6	2		T15	2
auto[1]	auto[ScrapSt]	58	1			T41	1		T51	1		T53	1
auto[1]	auto[EscalateSt]	1288048	1			T4	8115		T5	294		T6	196
auto[1]	auto[InvalidSt]	6431	1			T5	3		T16	4		T18	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6564749	1			T1	80		T2	93		T3	69
auto[0]	auto[IdleSt]	19315433	1			T1	38226		T2	161		T3	153
auto[0]	auto[ClkMuxSt]	31556	1			T2	1		T3	1		T4	67
auto[0]	auto[CntIncrSt]	31352	1			T2	1		T3	1		T4	64
auto[0]	auto[CntProgSt]	1333484	1			T2	286		T3	5		T4	111
auto[0]	auto[TransCheckSt]	24332	1			T2	1		T3	1		T4	43
auto[0]	auto[TokenHashSt]	30583164	1			T2	10		T3	14		T4	304
auto[0]	auto[FlashRmaSt]	30669	1			T2	1		T3	1		T4	52
auto[0]	auto[TokenCheck0St]	10709	1			T2	1		T3	1		T4	18
auto[0]	auto[TokenCheck1St]	7806	1			T2	1		T3	1		T4	18
auto[0]	auto[TransProgSt]	269826	1			T2	124		T3	3		T4	24
auto[0]	auto[PostTransSt]	11632547	1			T2	696		T3	1208		T12	725
auto[0]	auto[ScrapSt]	185540	1			T20	351		T41	6		T42	392
auto[0]	auto[EscalateSt]	5064541	1			T4	4444		T5	1032		T6	443
auto[0]	auto[InvalidSt]	11094343	1			T5	681		T16	1740		T18	1122
auto[1]	auto[ResetSt]	193	1			T4	5		T41	3		T51	3
auto[1]	auto[IdleSt]	113	1			T41	4		T51	2		T53	7
auto[1]	auto[ClkMuxSt]	45	1			T4	1		T41	1		T51	3
auto[1]	auto[CntIncrSt]	45	1			T4	2		T51	1		T52	1
auto[1]	auto[CntProgSt]	649	1			T4	10		T41	9		T51	10
auto[1]	auto[TransCheckSt]	109	1			T4	4		T53	5		T58	5
auto[1]	auto[TokenHashSt]	536	1			T4	12		T41	4		T51	6
auto[1]	auto[FlashRmaSt]	71	1			T4	3		T51	1		T52	2
auto[1]	auto[TokenCheck0St]	19	1			T55	1		T56	2		T57	1
auto[1]	auto[TokenCheck1St]	82	1			T41	1		T52	2		T58	3
auto[1]	auto[TransProgSt]	467	1			T4	8		T41	13		T51	11
auto[1]	auto[PostTransSt]	2387	1			T4	4		T6	5		T15	5
auto[1]	auto[ScrapSt]	59	1			T41	3		T53	3		T52	3
auto[1]	auto[EscalateSt]	1302236	1			T4	8377		T5	196		T6	490
auto[1]	auto[InvalidSt]	6394	1			T5	2		T16	5		T18	4