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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.25 97.99 96.22 93.40 100.00 98.55 98.51 96.11


Total test records in report: 977
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T810 /workspace/coverage/default/21.lc_ctrl_state_failure.139010881 Jul 20 04:37:57 PM PDT 24 Jul 20 04:38:21 PM PDT 24 387808632 ps
T811 /workspace/coverage/default/29.lc_ctrl_stress_all.391612332 Jul 20 04:38:28 PM PDT 24 Jul 20 04:38:58 PM PDT 24 973051579 ps
T812 /workspace/coverage/default/17.lc_ctrl_sec_mubi.1187499523 Jul 20 04:37:46 PM PDT 24 Jul 20 04:38:04 PM PDT 24 354186332 ps
T73 /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3742061637 Jul 20 04:37:33 PM PDT 24 Jul 20 04:37:41 PM PDT 24 1269829050 ps
T813 /workspace/coverage/default/41.lc_ctrl_stress_all.1697992549 Jul 20 04:38:53 PM PDT 24 Jul 20 04:40:05 PM PDT 24 9301306276 ps
T814 /workspace/coverage/default/36.lc_ctrl_stress_all.1448420463 Jul 20 04:38:36 PM PDT 24 Jul 20 04:39:33 PM PDT 24 1831892396 ps
T815 /workspace/coverage/default/42.lc_ctrl_smoke.2257717033 Jul 20 04:38:47 PM PDT 24 Jul 20 04:38:51 PM PDT 24 34131147 ps
T816 /workspace/coverage/default/36.lc_ctrl_sec_token_mux.4114432909 Jul 20 04:38:37 PM PDT 24 Jul 20 04:38:52 PM PDT 24 1340119992 ps
T817 /workspace/coverage/default/26.lc_ctrl_jtag_access.1859560650 Jul 20 04:38:15 PM PDT 24 Jul 20 04:38:20 PM PDT 24 207656615 ps
T818 /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2972213246 Jul 20 04:37:56 PM PDT 24 Jul 20 04:37:57 PM PDT 24 11395731 ps
T819 /workspace/coverage/default/38.lc_ctrl_errors.565160417 Jul 20 04:38:47 PM PDT 24 Jul 20 04:39:04 PM PDT 24 1782466234 ps
T820 /workspace/coverage/default/46.lc_ctrl_sec_mubi.2414429530 Jul 20 04:39:04 PM PDT 24 Jul 20 04:39:18 PM PDT 24 429345692 ps
T821 /workspace/coverage/default/48.lc_ctrl_stress_all.91788623 Jul 20 04:39:05 PM PDT 24 Jul 20 04:41:05 PM PDT 24 7040933058 ps
T822 /workspace/coverage/default/11.lc_ctrl_alert_test.894940537 Jul 20 04:37:32 PM PDT 24 Jul 20 04:37:35 PM PDT 24 109117171 ps
T823 /workspace/coverage/default/49.lc_ctrl_sec_token_digest.210858963 Jul 20 04:39:04 PM PDT 24 Jul 20 04:39:17 PM PDT 24 1401629783 ps
T824 /workspace/coverage/default/23.lc_ctrl_security_escalation.2264478364 Jul 20 04:38:09 PM PDT 24 Jul 20 04:38:21 PM PDT 24 521207933 ps
T825 /workspace/coverage/default/13.lc_ctrl_jtag_access.2263519485 Jul 20 04:37:37 PM PDT 24 Jul 20 04:37:49 PM PDT 24 382100423 ps
T826 /workspace/coverage/default/36.lc_ctrl_sec_mubi.4043730270 Jul 20 04:38:37 PM PDT 24 Jul 20 04:38:54 PM PDT 24 388609705 ps
T827 /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2191939213 Jul 20 04:37:02 PM PDT 24 Jul 20 04:37:04 PM PDT 24 38748276 ps
T828 /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1309719729 Jul 20 04:37:39 PM PDT 24 Jul 20 04:37:55 PM PDT 24 6445418445 ps
T829 /workspace/coverage/default/41.lc_ctrl_jtag_access.1004120565 Jul 20 04:38:54 PM PDT 24 Jul 20 04:39:02 PM PDT 24 3374167560 ps
T830 /workspace/coverage/default/21.lc_ctrl_security_escalation.3794737689 Jul 20 04:37:57 PM PDT 24 Jul 20 04:38:12 PM PDT 24 1439743196 ps
T831 /workspace/coverage/default/33.lc_ctrl_stress_all.2539749797 Jul 20 04:38:33 PM PDT 24 Jul 20 04:41:34 PM PDT 24 23280557759 ps
T832 /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3071866038 Jul 20 04:37:23 PM PDT 24 Jul 20 04:37:25 PM PDT 24 33127824 ps
T833 /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1809923051 Jul 20 04:37:50 PM PDT 24 Jul 20 04:37:52 PM PDT 24 28866965 ps
T834 /workspace/coverage/default/32.lc_ctrl_errors.2363843122 Jul 20 04:38:26 PM PDT 24 Jul 20 04:38:43 PM PDT 24 665852617 ps
T835 /workspace/coverage/default/33.lc_ctrl_prog_failure.4053284233 Jul 20 04:38:28 PM PDT 24 Jul 20 04:38:35 PM PDT 24 622481172 ps
T836 /workspace/coverage/default/23.lc_ctrl_prog_failure.1646383560 Jul 20 04:38:07 PM PDT 24 Jul 20 04:38:13 PM PDT 24 280457674 ps
T837 /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.3462417615 Jul 20 04:38:53 PM PDT 24 Jul 20 04:49:18 PM PDT 24 66837864924 ps
T838 /workspace/coverage/default/23.lc_ctrl_alert_test.3987987567 Jul 20 04:38:05 PM PDT 24 Jul 20 04:38:08 PM PDT 24 41995335 ps
T839 /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.4047821444 Jul 20 04:38:54 PM PDT 24 Jul 20 04:38:57 PM PDT 24 19115478 ps
T840 /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1787225307 Jul 20 04:37:42 PM PDT 24 Jul 20 04:37:53 PM PDT 24 335958760 ps
T841 /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2392392366 Jul 20 04:37:26 PM PDT 24 Jul 20 04:38:06 PM PDT 24 2903245417 ps
T111 /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.3224089618 Jul 20 04:38:52 PM PDT 24 Jul 20 04:45:34 PM PDT 24 85092674122 ps
T842 /workspace/coverage/default/38.lc_ctrl_state_post_trans.4149348924 Jul 20 04:38:46 PM PDT 24 Jul 20 04:38:55 PM PDT 24 112473826 ps
T843 /workspace/coverage/default/14.lc_ctrl_jtag_errors.4123426838 Jul 20 04:37:38 PM PDT 24 Jul 20 04:38:16 PM PDT 24 6908797683 ps
T844 /workspace/coverage/default/27.lc_ctrl_stress_all.1330147916 Jul 20 04:38:15 PM PDT 24 Jul 20 04:39:00 PM PDT 24 1465596922 ps
T845 /workspace/coverage/default/16.lc_ctrl_smoke.1159134627 Jul 20 04:37:42 PM PDT 24 Jul 20 04:37:46 PM PDT 24 50337576 ps
T846 /workspace/coverage/default/1.lc_ctrl_errors.2641410479 Jul 20 04:36:36 PM PDT 24 Jul 20 04:36:53 PM PDT 24 1302932278 ps
T847 /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2799444849 Jul 20 04:38:47 PM PDT 24 Jul 20 04:38:59 PM PDT 24 509136218 ps
T848 /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1686468695 Jul 20 04:37:40 PM PDT 24 Jul 20 04:37:53 PM PDT 24 3418740417 ps
T849 /workspace/coverage/default/44.lc_ctrl_state_post_trans.4048055127 Jul 20 04:38:54 PM PDT 24 Jul 20 04:39:00 PM PDT 24 44274131 ps
T113 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3875950571 Jul 20 05:00:48 PM PDT 24 Jul 20 05:00:53 PM PDT 24 48041459 ps
T119 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.804027592 Jul 20 05:00:06 PM PDT 24 Jul 20 05:00:10 PM PDT 24 96334770 ps
T120 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.597845334 Jul 20 05:00:39 PM PDT 24 Jul 20 05:00:41 PM PDT 24 20298162 ps
T121 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1597322783 Jul 20 05:00:38 PM PDT 24 Jul 20 05:01:02 PM PDT 24 1010450528 ps
T116 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1134030994 Jul 20 05:00:58 PM PDT 24 Jul 20 05:01:00 PM PDT 24 51757412 ps
T145 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2461820812 Jul 20 05:00:12 PM PDT 24 Jul 20 05:00:14 PM PDT 24 107736426 ps
T850 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.231232806 Jul 20 05:00:28 PM PDT 24 Jul 20 05:00:33 PM PDT 24 734866632 ps
T851 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.125477039 Jul 20 05:00:05 PM PDT 24 Jul 20 05:00:13 PM PDT 24 1330912745 ps
T147 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3462060066 Jul 20 05:00:37 PM PDT 24 Jul 20 05:00:38 PM PDT 24 47198741 ps
T114 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1945331053 Jul 20 05:00:50 PM PDT 24 Jul 20 05:00:58 PM PDT 24 221403730 ps
T140 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1148036704 Jul 20 05:00:40 PM PDT 24 Jul 20 05:00:42 PM PDT 24 90445459 ps
T852 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3969894183 Jul 20 05:00:48 PM PDT 24 Jul 20 05:00:52 PM PDT 24 14623930 ps
T853 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1060144177 Jul 20 05:00:30 PM PDT 24 Jul 20 05:00:32 PM PDT 24 67031993 ps
T854 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3191855570 Jul 20 05:00:38 PM PDT 24 Jul 20 05:00:44 PM PDT 24 202811355 ps
T163 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.396378346 Jul 20 05:00:13 PM PDT 24 Jul 20 05:00:16 PM PDT 24 440491055 ps
T855 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1473813141 Jul 20 05:00:13 PM PDT 24 Jul 20 05:00:15 PM PDT 24 67787065 ps
T856 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.319525328 Jul 20 05:00:05 PM PDT 24 Jul 20 05:00:07 PM PDT 24 60565949 ps
T857 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1351050673 Jul 20 05:00:20 PM PDT 24 Jul 20 05:00:21 PM PDT 24 19400311 ps
T115 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4134899138 Jul 20 05:00:29 PM PDT 24 Jul 20 05:00:32 PM PDT 24 203245260 ps
T188 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.431408965 Jul 20 05:00:47 PM PDT 24 Jul 20 05:00:50 PM PDT 24 67562652 ps
T200 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1989281597 Jul 20 05:00:38 PM PDT 24 Jul 20 05:00:40 PM PDT 24 37809128 ps
T858 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.802063151 Jul 20 05:00:23 PM PDT 24 Jul 20 05:00:25 PM PDT 24 19054326 ps
T201 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3592681501 Jul 20 05:00:07 PM PDT 24 Jul 20 05:00:10 PM PDT 24 42085041 ps
T117 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1748305238 Jul 20 05:00:02 PM PDT 24 Jul 20 05:00:05 PM PDT 24 573789515 ps
T159 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.274272908 Jul 20 05:00:47 PM PDT 24 Jul 20 05:00:50 PM PDT 24 17779860 ps
T859 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.4280112043 Jul 20 05:00:30 PM PDT 24 Jul 20 05:00:32 PM PDT 24 132970751 ps
T118 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1701283715 Jul 20 05:00:23 PM PDT 24 Jul 20 05:00:27 PM PDT 24 57092779 ps
T129 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2314119982 Jul 20 05:00:47 PM PDT 24 Jul 20 05:00:52 PM PDT 24 263428068 ps
T860 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2854770044 Jul 20 05:00:15 PM PDT 24 Jul 20 05:00:17 PM PDT 24 30960198 ps
T122 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3410283175 Jul 20 05:00:49 PM PDT 24 Jul 20 05:00:53 PM PDT 24 82379483 ps
T127 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3651549550 Jul 20 05:00:23 PM PDT 24 Jul 20 05:00:28 PM PDT 24 127105664 ps
T138 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2803492012 Jul 20 05:00:45 PM PDT 24 Jul 20 05:00:49 PM PDT 24 285061355 ps
T202 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1916898406 Jul 20 05:00:48 PM PDT 24 Jul 20 05:00:52 PM PDT 24 16886153 ps
T189 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3952808314 Jul 20 05:00:14 PM PDT 24 Jul 20 05:00:17 PM PDT 24 12468228 ps
T861 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3962191224 Jul 20 05:00:38 PM PDT 24 Jul 20 05:00:40 PM PDT 24 30105975 ps
T862 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3074412190 Jul 20 05:00:44 PM PDT 24 Jul 20 05:00:46 PM PDT 24 52517062 ps
T863 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.258591895 Jul 20 05:00:15 PM PDT 24 Jul 20 05:00:21 PM PDT 24 1225864093 ps
T203 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3156973125 Jul 20 05:00:45 PM PDT 24 Jul 20 05:00:47 PM PDT 24 75162760 ps
T864 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2713999035 Jul 20 05:00:15 PM PDT 24 Jul 20 05:00:17 PM PDT 24 15272976 ps
T123 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.80774027 Jul 20 05:00:43 PM PDT 24 Jul 20 05:00:45 PM PDT 24 268448098 ps
T865 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3709730635 Jul 20 05:00:35 PM PDT 24 Jul 20 05:00:41 PM PDT 24 546554730 ps
T204 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3146517803 Jul 20 05:00:48 PM PDT 24 Jul 20 05:00:52 PM PDT 24 19265799 ps
T205 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.643809770 Jul 20 05:00:16 PM PDT 24 Jul 20 05:00:19 PM PDT 24 22178537 ps
T866 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3392823169 Jul 20 05:00:36 PM PDT 24 Jul 20 05:00:42 PM PDT 24 902712135 ps
T867 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3837483438 Jul 20 05:00:38 PM PDT 24 Jul 20 05:00:48 PM PDT 24 878546920 ps
T206 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2310163910 Jul 20 05:00:46 PM PDT 24 Jul 20 05:00:50 PM PDT 24 84979631 ps
T128 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2246249567 Jul 20 05:00:35 PM PDT 24 Jul 20 05:00:39 PM PDT 24 451554661 ps
T124 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2817628970 Jul 20 05:00:47 PM PDT 24 Jul 20 05:00:52 PM PDT 24 222229238 ps
T126 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.47379377 Jul 20 05:00:30 PM PDT 24 Jul 20 05:00:34 PM PDT 24 2096874836 ps
T868 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1749785101 Jul 20 05:00:28 PM PDT 24 Jul 20 05:00:33 PM PDT 24 272518467 ps
T137 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.4135666933 Jul 20 05:00:46 PM PDT 24 Jul 20 05:00:53 PM PDT 24 119278695 ps
T869 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.420809062 Jul 20 05:00:43 PM PDT 24 Jul 20 05:00:55 PM PDT 24 1245431860 ps
T870 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2628294236 Jul 20 05:00:43 PM PDT 24 Jul 20 05:00:44 PM PDT 24 173206288 ps
T871 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2810812674 Jul 20 05:00:15 PM PDT 24 Jul 20 05:00:19 PM PDT 24 79754137 ps
T872 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.667947313 Jul 20 05:00:46 PM PDT 24 Jul 20 05:00:48 PM PDT 24 16488219 ps
T873 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1389072529 Jul 20 05:00:15 PM PDT 24 Jul 20 05:00:18 PM PDT 24 367237097 ps
T874 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2342784316 Jul 20 05:00:36 PM PDT 24 Jul 20 05:00:38 PM PDT 24 20396553 ps
T139 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1921216145 Jul 20 05:00:45 PM PDT 24 Jul 20 05:00:50 PM PDT 24 773709225 ps
T875 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.462127778 Jul 20 05:00:40 PM PDT 24 Jul 20 05:00:51 PM PDT 24 425729812 ps
T876 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1344108939 Jul 20 05:00:15 PM PDT 24 Jul 20 05:00:20 PM PDT 24 169823351 ps
T130 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3306610906 Jul 20 05:00:44 PM PDT 24 Jul 20 05:00:50 PM PDT 24 114063687 ps
T877 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2759848322 Jul 20 05:00:49 PM PDT 24 Jul 20 05:00:54 PM PDT 24 172616055 ps
T878 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1567182854 Jul 20 05:00:31 PM PDT 24 Jul 20 05:00:38 PM PDT 24 1040697100 ps
T131 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.43114397 Jul 20 05:00:06 PM PDT 24 Jul 20 05:00:11 PM PDT 24 665853590 ps
T879 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2923839935 Jul 20 05:00:36 PM PDT 24 Jul 20 05:00:49 PM PDT 24 491532107 ps
T880 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1583359390 Jul 20 05:00:37 PM PDT 24 Jul 20 05:00:40 PM PDT 24 150699535 ps
T881 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.676718350 Jul 20 05:00:47 PM PDT 24 Jul 20 05:00:51 PM PDT 24 118194804 ps
T882 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.670629588 Jul 20 05:00:23 PM PDT 24 Jul 20 05:00:27 PM PDT 24 65419968 ps
T190 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3512671221 Jul 20 05:00:05 PM PDT 24 Jul 20 05:00:07 PM PDT 24 18622164 ps
T207 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2657261174 Jul 20 05:00:45 PM PDT 24 Jul 20 05:00:48 PM PDT 24 11488912 ps
T141 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4196504734 Jul 20 05:00:51 PM PDT 24 Jul 20 05:00:56 PM PDT 24 490488523 ps
T883 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.973146643 Jul 20 05:00:16 PM PDT 24 Jul 20 05:00:18 PM PDT 24 20314995 ps
T884 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1454278193 Jul 20 05:00:44 PM PDT 24 Jul 20 05:00:47 PM PDT 24 162788708 ps
T885 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2794835281 Jul 20 05:00:36 PM PDT 24 Jul 20 05:00:38 PM PDT 24 26760177 ps
T160 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3832574387 Jul 20 05:00:23 PM PDT 24 Jul 20 05:00:27 PM PDT 24 376495963 ps
T886 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.291745938 Jul 20 05:00:48 PM PDT 24 Jul 20 05:00:53 PM PDT 24 39203315 ps
T887 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.625755290 Jul 20 05:00:46 PM PDT 24 Jul 20 05:00:53 PM PDT 24 251603357 ps
T888 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2041219028 Jul 20 05:00:08 PM PDT 24 Jul 20 05:00:14 PM PDT 24 1120602064 ps
T191 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.425953654 Jul 20 05:00:44 PM PDT 24 Jul 20 05:00:46 PM PDT 24 18000266 ps
T889 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1795642586 Jul 20 05:00:48 PM PDT 24 Jul 20 05:00:52 PM PDT 24 78983516 ps
T133 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1677698651 Jul 20 05:00:12 PM PDT 24 Jul 20 05:00:15 PM PDT 24 78749638 ps
T890 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3563136690 Jul 20 05:00:39 PM PDT 24 Jul 20 05:00:41 PM PDT 24 159383090 ps
T891 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3627278669 Jul 20 05:00:38 PM PDT 24 Jul 20 05:00:41 PM PDT 24 44839069 ps
T892 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3149463040 Jul 20 05:00:07 PM PDT 24 Jul 20 05:00:24 PM PDT 24 4001228134 ps
T893 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1017902284 Jul 20 05:00:36 PM PDT 24 Jul 20 05:00:40 PM PDT 24 413410454 ps
T894 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4162745914 Jul 20 05:00:39 PM PDT 24 Jul 20 05:00:42 PM PDT 24 50492651 ps
T135 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.465316971 Jul 20 05:00:48 PM PDT 24 Jul 20 05:00:54 PM PDT 24 209611718 ps
T895 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3949770453 Jul 20 05:00:21 PM PDT 24 Jul 20 05:00:24 PM PDT 24 116656336 ps
T896 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3859526693 Jul 20 05:00:22 PM PDT 24 Jul 20 05:00:24 PM PDT 24 17684100 ps
T897 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1553878009 Jul 20 05:00:48 PM PDT 24 Jul 20 05:00:52 PM PDT 24 20390748 ps
T898 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1151980657 Jul 20 05:00:06 PM PDT 24 Jul 20 05:00:20 PM PDT 24 1102152146 ps
T899 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1006278408 Jul 20 05:00:50 PM PDT 24 Jul 20 05:00:53 PM PDT 24 46502421 ps
T900 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.995172377 Jul 20 05:00:49 PM PDT 24 Jul 20 05:00:53 PM PDT 24 39327591 ps
T901 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2188483948 Jul 20 05:00:23 PM PDT 24 Jul 20 05:00:26 PM PDT 24 98005285 ps
T902 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3702044496 Jul 20 05:00:43 PM PDT 24 Jul 20 05:00:46 PM PDT 24 54093313 ps
T144 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.804571989 Jul 20 05:00:45 PM PDT 24 Jul 20 05:00:48 PM PDT 24 247371769 ps
T903 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2059296843 Jul 20 05:00:50 PM PDT 24 Jul 20 05:00:55 PM PDT 24 203990496 ps
T904 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2006122318 Jul 20 05:00:44 PM PDT 24 Jul 20 05:00:58 PM PDT 24 1161206900 ps
T905 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1126414653 Jul 20 05:00:36 PM PDT 24 Jul 20 05:00:38 PM PDT 24 127565753 ps
T906 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1748344753 Jul 20 05:00:15 PM PDT 24 Jul 20 05:00:17 PM PDT 24 39301135 ps
T907 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.476209358 Jul 20 05:00:38 PM PDT 24 Jul 20 05:00:42 PM PDT 24 75262858 ps
T908 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.415263539 Jul 20 05:00:46 PM PDT 24 Jul 20 05:00:49 PM PDT 24 15736340 ps
T909 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.854778840 Jul 20 05:00:48 PM PDT 24 Jul 20 05:00:52 PM PDT 24 14150204 ps
T192 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.747447465 Jul 20 05:00:22 PM PDT 24 Jul 20 05:00:24 PM PDT 24 32820870 ps
T193 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3115702775 Jul 20 05:00:39 PM PDT 24 Jul 20 05:00:41 PM PDT 24 53319294 ps
T910 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3398732687 Jul 20 05:01:02 PM PDT 24 Jul 20 05:01:04 PM PDT 24 64682794 ps
T911 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.789710966 Jul 20 05:00:22 PM PDT 24 Jul 20 05:00:24 PM PDT 24 28770785 ps
T912 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2671888034 Jul 20 05:00:21 PM PDT 24 Jul 20 05:00:23 PM PDT 24 181801628 ps
T913 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3592134037 Jul 20 05:00:40 PM PDT 24 Jul 20 05:00:42 PM PDT 24 104040982 ps
T132 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2485039624 Jul 20 05:00:48 PM PDT 24 Jul 20 05:00:53 PM PDT 24 40987754 ps
T914 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2205608573 Jul 20 05:00:31 PM PDT 24 Jul 20 05:00:33 PM PDT 24 1459535874 ps
T915 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1677864034 Jul 20 05:00:29 PM PDT 24 Jul 20 05:00:31 PM PDT 24 107450906 ps
T194 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1771853556 Jul 20 05:00:22 PM PDT 24 Jul 20 05:00:24 PM PDT 24 13840758 ps
T916 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4184540822 Jul 20 05:00:21 PM PDT 24 Jul 20 05:00:24 PM PDT 24 160708628 ps
T917 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1495200885 Jul 20 05:00:45 PM PDT 24 Jul 20 05:00:48 PM PDT 24 20253509 ps
T918 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1843018939 Jul 20 05:00:39 PM PDT 24 Jul 20 05:00:42 PM PDT 24 65986179 ps
T919 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1825105308 Jul 20 05:00:29 PM PDT 24 Jul 20 05:00:31 PM PDT 24 99662353 ps
T920 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1901752322 Jul 20 05:00:30 PM PDT 24 Jul 20 05:00:35 PM PDT 24 200797552 ps
T921 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3252383115 Jul 20 05:00:23 PM PDT 24 Jul 20 05:00:25 PM PDT 24 65073367 ps
T922 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.527600443 Jul 20 05:00:12 PM PDT 24 Jul 20 05:00:14 PM PDT 24 64970081 ps
T923 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3582312929 Jul 20 05:00:42 PM PDT 24 Jul 20 05:00:44 PM PDT 24 29257451 ps
T924 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2898470867 Jul 20 05:00:23 PM PDT 24 Jul 20 05:00:26 PM PDT 24 24611266 ps
T925 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.30781321 Jul 20 05:00:13 PM PDT 24 Jul 20 05:00:20 PM PDT 24 422425316 ps
T926 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1015903703 Jul 20 05:00:11 PM PDT 24 Jul 20 05:00:13 PM PDT 24 57439730 ps
T927 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2369641970 Jul 20 05:00:41 PM PDT 24 Jul 20 05:00:44 PM PDT 24 39714175 ps
T928 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3179354670 Jul 20 05:00:21 PM PDT 24 Jul 20 05:00:55 PM PDT 24 6007535194 ps
T929 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.4227632866 Jul 20 05:00:49 PM PDT 24 Jul 20 05:00:52 PM PDT 24 39334601 ps
T930 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4277513131 Jul 20 05:00:44 PM PDT 24 Jul 20 05:00:46 PM PDT 24 128109129 ps
T931 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.377562275 Jul 20 05:00:16 PM PDT 24 Jul 20 05:00:24 PM PDT 24 632328688 ps
T932 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.716865651 Jul 20 05:00:38 PM PDT 24 Jul 20 05:00:41 PM PDT 24 93336904 ps
T933 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.536857552 Jul 20 05:00:06 PM PDT 24 Jul 20 05:00:08 PM PDT 24 67558416 ps
T934 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1643721973 Jul 20 05:00:21 PM PDT 24 Jul 20 05:00:22 PM PDT 24 259310319 ps
T935 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1000098409 Jul 20 05:00:46 PM PDT 24 Jul 20 05:00:49 PM PDT 24 93891225 ps
T936 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.750080162 Jul 20 05:00:30 PM PDT 24 Jul 20 05:00:31 PM PDT 24 65256583 ps
T937 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2212198529 Jul 20 05:00:15 PM PDT 24 Jul 20 05:00:18 PM PDT 24 75392747 ps
T938 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1000334445 Jul 20 05:00:07 PM PDT 24 Jul 20 05:00:09 PM PDT 24 84202364 ps
T939 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4150714191 Jul 20 05:00:37 PM PDT 24 Jul 20 05:00:41 PM PDT 24 112148703 ps
T142 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.951057890 Jul 20 05:00:20 PM PDT 24 Jul 20 05:00:22 PM PDT 24 52683710 ps
T940 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.971238219 Jul 20 05:00:05 PM PDT 24 Jul 20 05:00:08 PM PDT 24 1021737364 ps
T941 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3048552194 Jul 20 05:00:23 PM PDT 24 Jul 20 05:00:26 PM PDT 24 51661017 ps
T942 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.49855614 Jul 20 05:00:13 PM PDT 24 Jul 20 05:00:15 PM PDT 24 20647361 ps
T943 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1357344555 Jul 20 05:00:36 PM PDT 24 Jul 20 05:00:38 PM PDT 24 40442010 ps
T944 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.288862854 Jul 20 05:00:04 PM PDT 24 Jul 20 05:00:06 PM PDT 24 73432315 ps
T945 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.560913920 Jul 20 05:00:48 PM PDT 24 Jul 20 05:00:52 PM PDT 24 55305275 ps
T946 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3723352501 Jul 20 05:00:47 PM PDT 24 Jul 20 05:00:52 PM PDT 24 109401383 ps
T947 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.23211739 Jul 20 05:00:04 PM PDT 24 Jul 20 05:00:06 PM PDT 24 62456593 ps
T195 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.363590023 Jul 20 05:00:12 PM PDT 24 Jul 20 05:00:14 PM PDT 24 20606845 ps
T948 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4048186022 Jul 20 05:00:48 PM PDT 24 Jul 20 05:00:53 PM PDT 24 515552586 ps
T949 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2098114496 Jul 20 05:00:05 PM PDT 24 Jul 20 05:00:07 PM PDT 24 47080875 ps
T950 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2760695540 Jul 20 05:00:21 PM PDT 24 Jul 20 05:00:23 PM PDT 24 16357759 ps
T951 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3889445734 Jul 20 05:00:15 PM PDT 24 Jul 20 05:00:18 PM PDT 24 164441388 ps
T952 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1888535008 Jul 20 05:00:23 PM PDT 24 Jul 20 05:00:28 PM PDT 24 124713226 ps
T953 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1175382760 Jul 20 05:00:50 PM PDT 24 Jul 20 05:00:53 PM PDT 24 15923003 ps
T954 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.4154082281 Jul 20 05:00:22 PM PDT 24 Jul 20 05:00:24 PM PDT 24 34639503 ps
T196 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.141667885 Jul 20 05:00:15 PM PDT 24 Jul 20 05:00:18 PM PDT 24 19670933 ps
T955 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3642055479 Jul 20 05:00:44 PM PDT 24 Jul 20 05:00:47 PM PDT 24 58418143 ps
T956 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3520564253 Jul 20 05:00:37 PM PDT 24 Jul 20 05:00:40 PM PDT 24 44364070 ps
T957 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.936252464 Jul 20 05:00:05 PM PDT 24 Jul 20 05:00:09 PM PDT 24 1201811895 ps
T125 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2591698060 Jul 20 05:00:47 PM PDT 24 Jul 20 05:00:52 PM PDT 24 113152386 ps
T134 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1440589312 Jul 20 05:00:27 PM PDT 24 Jul 20 05:00:30 PM PDT 24 140327101 ps
T197 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3014656776 Jul 20 05:00:49 PM PDT 24 Jul 20 05:00:53 PM PDT 24 27902106 ps
T958 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1795512953 Jul 20 05:00:05 PM PDT 24 Jul 20 05:00:08 PM PDT 24 362148185 ps
T199 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3838134109 Jul 20 05:00:04 PM PDT 24 Jul 20 05:00:06 PM PDT 24 69605403 ps
T959 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.435080611 Jul 20 05:00:06 PM PDT 24 Jul 20 05:00:08 PM PDT 24 136667483 ps
T960 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1416685084 Jul 20 05:00:46 PM PDT 24 Jul 20 05:00:49 PM PDT 24 55225267 ps
T961 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.774685927 Jul 20 05:00:48 PM PDT 24 Jul 20 05:00:52 PM PDT 24 73365716 ps
T962 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.480991334 Jul 20 05:00:47 PM PDT 24 Jul 20 05:00:51 PM PDT 24 29871716 ps
T198 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3796315480 Jul 20 05:00:05 PM PDT 24 Jul 20 05:00:07 PM PDT 24 33882152 ps
T963 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.855688334 Jul 20 05:00:45 PM PDT 24 Jul 20 05:00:48 PM PDT 24 14143184 ps
T964 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2762905984 Jul 20 05:00:05 PM PDT 24 Jul 20 05:00:07 PM PDT 24 36314327 ps
T965 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3816168875 Jul 20 05:00:48 PM PDT 24 Jul 20 05:00:52 PM PDT 24 36765457 ps
T966 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1234252225 Jul 20 05:00:11 PM PDT 24 Jul 20 05:00:27 PM PDT 24 1451398071 ps
T967 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.4159368208 Jul 20 05:00:45 PM PDT 24 Jul 20 05:00:49 PM PDT 24 58749984 ps
T968 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.932820928 Jul 20 05:00:06 PM PDT 24 Jul 20 05:00:09 PM PDT 24 26893349 ps
T969 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.270969787 Jul 20 05:00:39 PM PDT 24 Jul 20 05:00:41 PM PDT 24 46290875 ps
T143 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1349267685 Jul 20 05:00:36 PM PDT 24 Jul 20 05:00:40 PM PDT 24 659665946 ps
T970 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.949999538 Jul 20 05:00:07 PM PDT 24 Jul 20 05:00:10 PM PDT 24 94342164 ps
T971 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2045541743 Jul 20 05:00:35 PM PDT 24 Jul 20 05:00:37 PM PDT 24 24877002 ps
T136 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.59819538 Jul 20 05:00:46 PM PDT 24 Jul 20 05:00:51 PM PDT 24 220917656 ps
T972 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1213747214 Jul 20 05:00:15 PM PDT 24 Jul 20 05:00:17 PM PDT 24 22329239 ps
T973 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.257521652 Jul 20 05:00:04 PM PDT 24 Jul 20 05:00:05 PM PDT 24 182866005 ps
T974 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1874534893 Jul 20 05:00:28 PM PDT 24 Jul 20 05:00:35 PM PDT 24 227568680 ps
T975 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1011861959 Jul 20 05:00:48 PM PDT 24 Jul 20 05:00:56 PM PDT 24 136747295 ps
T976 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2924109726 Jul 20 05:00:46 PM PDT 24 Jul 20 05:00:50 PM PDT 24 27241334 ps
T977 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2468963485 Jul 20 05:00:07 PM PDT 24 Jul 20 05:00:10 PM PDT 24 65786901 ps

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.1142791038
Short name T4
Test name
Test status
Simulation time 237497248 ps
CPU time 10.53 seconds
Started Jul 20 04:37:30 PM PDT 24
Finished Jul 20 04:37:42 PM PDT 24
Peak memory 217768 kb
Host smart-0108dea5-c652-41ee-8918-06cf4adf12ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142791038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1142791038
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.4253034580
Short name T20
Test name
Test status
Simulation time 5109864175 ps
CPU time 122.69 seconds
Started Jul 20 04:38:28 PM PDT 24
Finished Jul 20 04:40:33 PM PDT 24
Peak memory 271256 kb
Host smart-6e7861d8-b411-42fc-9cbf-b7181470a07e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253034580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.4253034580
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.389455522
Short name T16
Test name
Test status
Simulation time 1803483363 ps
CPU time 9.25 seconds
Started Jul 20 04:36:54 PM PDT 24
Finished Jul 20 04:37:05 PM PDT 24
Peak memory 218380 kb
Host smart-6f087ca3-975d-4226-b152-bfb12c1c82df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389455522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.389455522
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3759276236
Short name T40
Test name
Test status
Simulation time 12631499834 ps
CPU time 129.39 seconds
Started Jul 20 04:38:09 PM PDT 24
Finished Jul 20 04:40:19 PM PDT 24
Peak memory 270616 kb
Host smart-b3e3f29d-0628-4953-afe1-ba1182cfecb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759276236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3759276236
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3091039221
Short name T55
Test name
Test status
Simulation time 346526638 ps
CPU time 8.74 seconds
Started Jul 20 04:36:42 PM PDT 24
Finished Jul 20 04:36:53 PM PDT 24
Peak memory 217808 kb
Host smart-7e3624b5-c451-49b1-93de-fe73126a9349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091039221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3091039221
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.4007420556
Short name T14
Test name
Test status
Simulation time 71794867 ps
CPU time 0.86 seconds
Started Jul 20 04:38:05 PM PDT 24
Finished Jul 20 04:38:07 PM PDT 24
Peak memory 208292 kb
Host smart-37a259de-182a-4ab3-a04f-0fd40ff3fe52
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007420556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.4007420556
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3875950571
Short name T113
Test name
Test status
Simulation time 48041459 ps
CPU time 1.71 seconds
Started Jul 20 05:00:48 PM PDT 24
Finished Jul 20 05:00:53 PM PDT 24
Peak memory 217892 kb
Host smart-616f2859-b0d4-4120-ad4c-fe39a863801e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875950571 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3875950571
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1057406909
Short name T1
Test name
Test status
Simulation time 2016258793 ps
CPU time 10.63 seconds
Started Jul 20 04:37:15 PM PDT 24
Finished Jul 20 04:37:28 PM PDT 24
Peak memory 216820 kb
Host smart-9f55b1dc-9458-4d47-a968-8b147693219e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057406909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1057406909
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3873277589
Short name T54
Test name
Test status
Simulation time 133662385 ps
CPU time 25.79 seconds
Started Jul 20 04:36:53 PM PDT 24
Finished Jul 20 04:37:20 PM PDT 24
Peak memory 268988 kb
Host smart-591aaab4-d3ad-4165-afe9-a7690a668cb8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873277589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3873277589
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3980643477
Short name T112
Test name
Test status
Simulation time 131487641523 ps
CPU time 1166.73 seconds
Started Jul 20 04:37:25 PM PDT 24
Finished Jul 20 04:56:54 PM PDT 24
Peak memory 276524 kb
Host smart-dbaf67d8-3fcc-43e6-80a7-e997f2b97af7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3980643477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3980643477
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.4152495301
Short name T37
Test name
Test status
Simulation time 624447296 ps
CPU time 8.68 seconds
Started Jul 20 04:38:56 PM PDT 24
Finished Jul 20 04:39:07 PM PDT 24
Peak memory 225472 kb
Host smart-05b472ee-3f0b-4594-bac2-82b669a56173
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152495301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
4152495301
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2803492012
Short name T138
Test name
Test status
Simulation time 285061355 ps
CPU time 2.63 seconds
Started Jul 20 05:00:45 PM PDT 24
Finished Jul 20 05:00:49 PM PDT 24
Peak memory 222528 kb
Host smart-fd71bca6-de0f-46aa-a24b-73e4a540bd39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803492012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2803492012
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.22477737
Short name T85
Test name
Test status
Simulation time 56793232539 ps
CPU time 1040.02 seconds
Started Jul 20 04:38:36 PM PDT 24
Finished Jul 20 04:55:58 PM PDT 24
Peak memory 512776 kb
Host smart-53eeddb9-f501-4bc4-897e-3b4c7fb1008c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=22477737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.22477737
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.501275847
Short name T161
Test name
Test status
Simulation time 862377161 ps
CPU time 12.21 seconds
Started Jul 20 04:37:04 PM PDT 24
Finished Jul 20 04:37:18 PM PDT 24
Peak memory 218076 kb
Host smart-ae8db9ed-d2ec-4e32-b19e-40c5320b16f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501275847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.501275847
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1729045241
Short name T290
Test name
Test status
Simulation time 144088564 ps
CPU time 0.9 seconds
Started Jul 20 04:37:29 PM PDT 24
Finished Jul 20 04:37:31 PM PDT 24
Peak memory 208276 kb
Host smart-a7074a42-e77e-40d4-9ff2-42300071efa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729045241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1729045241
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.431408965
Short name T188
Test name
Test status
Simulation time 67562652 ps
CPU time 0.84 seconds
Started Jul 20 05:00:47 PM PDT 24
Finished Jul 20 05:00:50 PM PDT 24
Peak memory 209540 kb
Host smart-7b0bc9e9-062a-4ae7-9a8b-447efafde271
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431408965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.431408965
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.804027592
Short name T119
Test name
Test status
Simulation time 96334770 ps
CPU time 2.71 seconds
Started Jul 20 05:00:06 PM PDT 24
Finished Jul 20 05:00:10 PM PDT 24
Peak memory 209584 kb
Host smart-a37ebc22-8288-4e41-8460-ec0878b85efe
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804027592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.804027592
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.610931566
Short name T39
Test name
Test status
Simulation time 91570082 ps
CPU time 2.48 seconds
Started Jul 20 04:38:16 PM PDT 24
Finished Jul 20 04:38:21 PM PDT 24
Peak memory 213620 kb
Host smart-63115d84-c20c-44c2-829a-bb4b958e5621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610931566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.610931566
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3410283175
Short name T122
Test name
Test status
Simulation time 82379483 ps
CPU time 1.64 seconds
Started Jul 20 05:00:49 PM PDT 24
Finished Jul 20 05:00:53 PM PDT 24
Peak memory 217968 kb
Host smart-89eaf20b-9581-47cb-9e37-0478f51e2d67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410283175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3410283175
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3306610906
Short name T130
Test name
Test status
Simulation time 114063687 ps
CPU time 4.03 seconds
Started Jul 20 05:00:44 PM PDT 24
Finished Jul 20 05:00:50 PM PDT 24
Peak memory 217856 kb
Host smart-2471f62e-a898-4bc0-a9e1-6fa333766184
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306610906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3306610906
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.587646640
Short name T5
Test name
Test status
Simulation time 474778649 ps
CPU time 6.44 seconds
Started Jul 20 04:36:36 PM PDT 24
Finished Jul 20 04:36:44 PM PDT 24
Peak memory 245932 kb
Host smart-cb66687f-beb8-4785-8a02-ab23ace77510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587646640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.587646640
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4134899138
Short name T115
Test name
Test status
Simulation time 203245260 ps
CPU time 2.97 seconds
Started Jul 20 05:00:29 PM PDT 24
Finished Jul 20 05:00:32 PM PDT 24
Peak memory 213604 kb
Host smart-f71aece7-a3fb-40b2-b812-0aef7e3f3847
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134899138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.4134899138
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4196504734
Short name T141
Test name
Test status
Simulation time 490488523 ps
CPU time 3.02 seconds
Started Jul 20 05:00:51 PM PDT 24
Finished Jul 20 05:00:56 PM PDT 24
Peak memory 217884 kb
Host smart-4fdb5a76-6bfa-49c9-b9f1-825d493c8cf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196504734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.4196504734
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.465316971
Short name T135
Test name
Test status
Simulation time 209611718 ps
CPU time 2.98 seconds
Started Jul 20 05:00:48 PM PDT 24
Finished Jul 20 05:00:54 PM PDT 24
Peak memory 222648 kb
Host smart-4441ba0c-ba2d-41fd-8b63-34fd07db6d33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465316971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.465316971
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2861854673
Short name T50
Test name
Test status
Simulation time 1020798305 ps
CPU time 11.65 seconds
Started Jul 20 04:36:46 PM PDT 24
Finished Jul 20 04:36:58 PM PDT 24
Peak memory 217624 kb
Host smart-8252c595-a0a1-4f7d-96f8-b4197368944b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861854673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2861854673
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.4046515437
Short name T109
Test name
Test status
Simulation time 13398437297 ps
CPU time 216.16 seconds
Started Jul 20 04:37:33 PM PDT 24
Finished Jul 20 04:41:11 PM PDT 24
Peak memory 316060 kb
Host smart-be2a77e9-f4ef-4cf2-af17-08d01af5bd59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046515437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.4046515437
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.951057890
Short name T142
Test name
Test status
Simulation time 52683710 ps
CPU time 2.04 seconds
Started Jul 20 05:00:20 PM PDT 24
Finished Jul 20 05:00:22 PM PDT 24
Peak memory 222556 kb
Host smart-f715a2f6-f45c-4b2c-a4a3-97b69ee9a6d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951057890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e
rr.951057890
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1626963862
Short name T19
Test name
Test status
Simulation time 2278889402 ps
CPU time 15.78 seconds
Started Jul 20 04:38:06 PM PDT 24
Finished Jul 20 04:38:24 PM PDT 24
Peak memory 218404 kb
Host smart-9dcf68d2-940c-4e3f-9d75-568ac10a6457
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626963862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1626963862
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1424568844
Short name T214
Test name
Test status
Simulation time 285758247 ps
CPU time 32.67 seconds
Started Jul 20 04:38:57 PM PDT 24
Finished Jul 20 04:39:31 PM PDT 24
Peak memory 250440 kb
Host smart-11098740-ab3e-4acb-b22f-0657e012b92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424568844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1424568844
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3651549550
Short name T127
Test name
Test status
Simulation time 127105664 ps
CPU time 3.46 seconds
Started Jul 20 05:00:23 PM PDT 24
Finished Jul 20 05:00:28 PM PDT 24
Peak memory 217736 kb
Host smart-f5d58035-058f-4e16-9970-4ac59025069a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651549550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3651549550
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.107737814
Short name T210
Test name
Test status
Simulation time 12197267 ps
CPU time 0.97 seconds
Started Jul 20 04:36:47 PM PDT 24
Finished Jul 20 04:36:49 PM PDT 24
Peak memory 208232 kb
Host smart-d3d7075a-8b3b-4dc9-b1f8-a97b68c57044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107737814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.107737814
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.36298007
Short name T476
Test name
Test status
Simulation time 269137012 ps
CPU time 8.18 seconds
Started Jul 20 04:37:22 PM PDT 24
Finished Jul 20 04:37:31 PM PDT 24
Peak memory 217740 kb
Host smart-4012e66d-0aa3-4775-bca6-b41e17c503d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36298007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.36298007
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1642811875
Short name T103
Test name
Test status
Simulation time 29947729 ps
CPU time 0.81 seconds
Started Jul 20 04:36:58 PM PDT 24
Finished Jul 20 04:37:00 PM PDT 24
Peak memory 208456 kb
Host smart-08a81339-e5da-4914-bfe0-47f9a6905b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642811875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1642811875
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1539567982
Short name T209
Test name
Test status
Simulation time 22181090 ps
CPU time 0.87 seconds
Started Jul 20 04:37:04 PM PDT 24
Finished Jul 20 04:37:06 PM PDT 24
Peak memory 208072 kb
Host smart-555b1d16-0c3a-4071-8cae-b19bbb805c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539567982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1539567982
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2591698060
Short name T125
Test name
Test status
Simulation time 113152386 ps
CPU time 2.01 seconds
Started Jul 20 05:00:47 PM PDT 24
Finished Jul 20 05:00:52 PM PDT 24
Peak memory 222132 kb
Host smart-995dd9c1-2762-48ae-81a9-42d0cba8cd98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591698060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2591698060
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1921216145
Short name T139
Test name
Test status
Simulation time 773709225 ps
CPU time 2.88 seconds
Started Jul 20 05:00:45 PM PDT 24
Finished Jul 20 05:00:50 PM PDT 24
Peak memory 222488 kb
Host smart-46711767-e46b-4b81-94bf-83aaacc0a74b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921216145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1921216145
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1349267685
Short name T143
Test name
Test status
Simulation time 659665946 ps
CPU time 3.47 seconds
Started Jul 20 05:00:36 PM PDT 24
Finished Jul 20 05:00:40 PM PDT 24
Peak memory 222740 kb
Host smart-98ab9ce8-4037-4209-9a85-e20787830356
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349267685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1349267685
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2246249567
Short name T128
Test name
Test status
Simulation time 451554661 ps
CPU time 2.9 seconds
Started Jul 20 05:00:35 PM PDT 24
Finished Jul 20 05:00:39 PM PDT 24
Peak memory 222516 kb
Host smart-db941c2a-d257-4f5c-9549-33c978e95327
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246249567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2246249567
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.4044702938
Short name T49
Test name
Test status
Simulation time 122350670059 ps
CPU time 4209.3 seconds
Started Jul 20 04:37:34 PM PDT 24
Finished Jul 20 05:47:45 PM PDT 24
Peak memory 922384 kb
Host smart-27e3a206-7550-4661-8790-bfdc3c8ada18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4044702938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.4044702938
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.929633754
Short name T23
Test name
Test status
Simulation time 11366993923 ps
CPU time 73.2 seconds
Started Jul 20 04:37:30 PM PDT 24
Finished Jul 20 04:38:45 PM PDT 24
Peak memory 218236 kb
Host smart-56c57830-f0fd-46ea-bab4-5058fe5fe754
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929633754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er
rors.929633754
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.536857552
Short name T933
Test name
Test status
Simulation time 67558416 ps
CPU time 1.29 seconds
Started Jul 20 05:00:06 PM PDT 24
Finished Jul 20 05:00:08 PM PDT 24
Peak memory 209612 kb
Host smart-74edd33d-42cf-4688-840a-fdc8881172f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536857552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.536857552
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.949999538
Short name T970
Test name
Test status
Simulation time 94342164 ps
CPU time 1.95 seconds
Started Jul 20 05:00:07 PM PDT 24
Finished Jul 20 05:00:10 PM PDT 24
Peak memory 208876 kb
Host smart-07c1a9ac-3ace-4608-a494-99074af89d11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949999538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash
.949999538
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3838134109
Short name T199
Test name
Test status
Simulation time 69605403 ps
CPU time 1.07 seconds
Started Jul 20 05:00:04 PM PDT 24
Finished Jul 20 05:00:06 PM PDT 24
Peak memory 218396 kb
Host smart-e58647d4-9c03-4b45-a1a7-827599a9fcef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838134109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3838134109
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.23211739
Short name T947
Test name
Test status
Simulation time 62456593 ps
CPU time 0.96 seconds
Started Jul 20 05:00:04 PM PDT 24
Finished Jul 20 05:00:06 PM PDT 24
Peak memory 217984 kb
Host smart-124f67b0-c345-4430-99b0-c027d6d4af9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23211739 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.23211739
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3512671221
Short name T190
Test name
Test status
Simulation time 18622164 ps
CPU time 0.86 seconds
Started Jul 20 05:00:05 PM PDT 24
Finished Jul 20 05:00:07 PM PDT 24
Peak memory 209504 kb
Host smart-449f1437-6e09-49e7-a7f7-a56b4fa31567
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512671221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3512671221
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.319525328
Short name T856
Test name
Test status
Simulation time 60565949 ps
CPU time 1.47 seconds
Started Jul 20 05:00:05 PM PDT 24
Finished Jul 20 05:00:07 PM PDT 24
Peak memory 208384 kb
Host smart-d7ee9630-9843-4880-b4b4-980bb098d788
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319525328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.319525328
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2041219028
Short name T888
Test name
Test status
Simulation time 1120602064 ps
CPU time 5.86 seconds
Started Jul 20 05:00:08 PM PDT 24
Finished Jul 20 05:00:14 PM PDT 24
Peak memory 208840 kb
Host smart-54b1e46d-45f8-4eea-88c0-b5329716f119
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041219028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2041219028
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1151980657
Short name T898
Test name
Test status
Simulation time 1102152146 ps
CPU time 12.38 seconds
Started Jul 20 05:00:06 PM PDT 24
Finished Jul 20 05:00:20 PM PDT 24
Peak memory 208872 kb
Host smart-a3889abe-f231-40e8-9a30-e1386d8f9f1a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151980657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1151980657
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.435080611
Short name T959
Test name
Test status
Simulation time 136667483 ps
CPU time 2.01 seconds
Started Jul 20 05:00:06 PM PDT 24
Finished Jul 20 05:00:08 PM PDT 24
Peak memory 211352 kb
Host smart-9d022564-1962-400b-88c0-0a431f16f11b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435080611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.435080611
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.971238219
Short name T940
Test name
Test status
Simulation time 1021737364 ps
CPU time 1.75 seconds
Started Jul 20 05:00:05 PM PDT 24
Finished Jul 20 05:00:08 PM PDT 24
Peak memory 217936 kb
Host smart-61c9b622-1569-40fa-9465-0565ad1d1a99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971238
219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.971238219
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1000334445
Short name T938
Test name
Test status
Simulation time 84202364 ps
CPU time 1.56 seconds
Started Jul 20 05:00:07 PM PDT 24
Finished Jul 20 05:00:09 PM PDT 24
Peak memory 209572 kb
Host smart-0ac0f0de-fa15-46f3-93cc-4aebbeff12d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000334445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1000334445
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2098114496
Short name T949
Test name
Test status
Simulation time 47080875 ps
CPU time 1.06 seconds
Started Jul 20 05:00:05 PM PDT 24
Finished Jul 20 05:00:07 PM PDT 24
Peak memory 209660 kb
Host smart-c501112e-e16c-45d9-9d9d-1246359b21ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098114496 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2098114496
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3592681501
Short name T201
Test name
Test status
Simulation time 42085041 ps
CPU time 1.86 seconds
Started Jul 20 05:00:07 PM PDT 24
Finished Jul 20 05:00:10 PM PDT 24
Peak memory 209592 kb
Host smart-ca001227-e5b1-4845-a463-5ee72cf229db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592681501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3592681501
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.936252464
Short name T957
Test name
Test status
Simulation time 1201811895 ps
CPU time 3.27 seconds
Started Jul 20 05:00:05 PM PDT 24
Finished Jul 20 05:00:09 PM PDT 24
Peak memory 217824 kb
Host smart-6007b41e-0eaa-47e7-8874-9862b229c05d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936252464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.936252464
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.43114397
Short name T131
Test name
Test status
Simulation time 665853590 ps
CPU time 3.02 seconds
Started Jul 20 05:00:06 PM PDT 24
Finished Jul 20 05:00:11 PM PDT 24
Peak memory 222272 kb
Host smart-09b3366f-e591-457b-a47a-619eb75c048c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43114397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_er
r.43114397
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2713999035
Short name T864
Test name
Test status
Simulation time 15272976 ps
CPU time 1.14 seconds
Started Jul 20 05:00:15 PM PDT 24
Finished Jul 20 05:00:17 PM PDT 24
Peak memory 209752 kb
Host smart-aeecff0b-b1c7-40be-b004-49477151b836
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713999035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.2713999035
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.973146643
Short name T883
Test name
Test status
Simulation time 20314995 ps
CPU time 1.38 seconds
Started Jul 20 05:00:16 PM PDT 24
Finished Jul 20 05:00:18 PM PDT 24
Peak memory 209492 kb
Host smart-5a187bcc-575f-46ef-9af5-1fe2fc6efedf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973146643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.973146643
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3796315480
Short name T198
Test name
Test status
Simulation time 33882152 ps
CPU time 0.94 seconds
Started Jul 20 05:00:05 PM PDT 24
Finished Jul 20 05:00:07 PM PDT 24
Peak memory 209880 kb
Host smart-41460730-0eb2-4fbd-8bd0-c88f7992ff30
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796315480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3796315480
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1213747214
Short name T972
Test name
Test status
Simulation time 22329239 ps
CPU time 1.24 seconds
Started Jul 20 05:00:15 PM PDT 24
Finished Jul 20 05:00:17 PM PDT 24
Peak memory 218264 kb
Host smart-68906341-74a8-478a-af73-9a88954b5cf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213747214 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1213747214
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2762905984
Short name T964
Test name
Test status
Simulation time 36314327 ps
CPU time 0.95 seconds
Started Jul 20 05:00:05 PM PDT 24
Finished Jul 20 05:00:07 PM PDT 24
Peak memory 209460 kb
Host smart-70ce0b04-7a6a-4eb4-b376-55377c347152
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762905984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2762905984
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.257521652
Short name T973
Test name
Test status
Simulation time 182866005 ps
CPU time 1.11 seconds
Started Jul 20 05:00:04 PM PDT 24
Finished Jul 20 05:00:05 PM PDT 24
Peak memory 209564 kb
Host smart-e6e5ccf7-9454-4358-be1d-7de98bf303c2
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257521652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.257521652
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.125477039
Short name T851
Test name
Test status
Simulation time 1330912745 ps
CPU time 6.75 seconds
Started Jul 20 05:00:05 PM PDT 24
Finished Jul 20 05:00:13 PM PDT 24
Peak memory 208172 kb
Host smart-1a511cbd-9f7e-4905-9b56-0580033ec500
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125477039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.125477039
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3149463040
Short name T892
Test name
Test status
Simulation time 4001228134 ps
CPU time 16.78 seconds
Started Jul 20 05:00:07 PM PDT 24
Finished Jul 20 05:00:24 PM PDT 24
Peak memory 209704 kb
Host smart-d04c1852-fda8-4446-8869-a8d735ebb8c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149463040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3149463040
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1795512953
Short name T958
Test name
Test status
Simulation time 362148185 ps
CPU time 1.95 seconds
Started Jul 20 05:00:05 PM PDT 24
Finished Jul 20 05:00:08 PM PDT 24
Peak memory 211384 kb
Host smart-17c841cc-e8e8-4f14-a48b-100a4c819db4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795512953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1795512953
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2468963485
Short name T977
Test name
Test status
Simulation time 65786901 ps
CPU time 1.68 seconds
Started Jul 20 05:00:07 PM PDT 24
Finished Jul 20 05:00:10 PM PDT 24
Peak memory 217972 kb
Host smart-6eb15766-472b-427a-b16a-7a4663fe7b6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246896
3485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2468963485
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.288862854
Short name T944
Test name
Test status
Simulation time 73432315 ps
CPU time 1.29 seconds
Started Jul 20 05:00:04 PM PDT 24
Finished Jul 20 05:00:06 PM PDT 24
Peak memory 209684 kb
Host smart-c146ead6-fdd0-447d-8151-e16f74480894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288862854 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.288862854
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1015903703
Short name T926
Test name
Test status
Simulation time 57439730 ps
CPU time 1.1 seconds
Started Jul 20 05:00:11 PM PDT 24
Finished Jul 20 05:00:13 PM PDT 24
Peak memory 209808 kb
Host smart-574bb4c5-bc32-4ad4-9eca-36c6bdc2f390
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015903703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1015903703
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.932820928
Short name T968
Test name
Test status
Simulation time 26893349 ps
CPU time 1.86 seconds
Started Jul 20 05:00:06 PM PDT 24
Finished Jul 20 05:00:09 PM PDT 24
Peak memory 218212 kb
Host smart-670024eb-e989-415e-ab9e-a5a464e1d42c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932820928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.932820928
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1748305238
Short name T117
Test name
Test status
Simulation time 573789515 ps
CPU time 1.83 seconds
Started Jul 20 05:00:02 PM PDT 24
Finished Jul 20 05:00:05 PM PDT 24
Peak memory 222020 kb
Host smart-5ae6fee8-9f5f-407e-8faa-15e10a3260d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748305238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1748305238
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1134030994
Short name T116
Test name
Test status
Simulation time 51757412 ps
CPU time 1.76 seconds
Started Jul 20 05:00:58 PM PDT 24
Finished Jul 20 05:01:00 PM PDT 24
Peak memory 217912 kb
Host smart-9ea4d72f-1b11-4f92-b5c8-7adbb696ebfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134030994 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1134030994
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1416685084
Short name T960
Test name
Test status
Simulation time 55225267 ps
CPU time 0.87 seconds
Started Jul 20 05:00:46 PM PDT 24
Finished Jul 20 05:00:49 PM PDT 24
Peak memory 209552 kb
Host smart-e08e051d-f997-4993-9721-35debf9d001d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416685084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1416685084
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3398732687
Short name T910
Test name
Test status
Simulation time 64682794 ps
CPU time 1.4 seconds
Started Jul 20 05:01:02 PM PDT 24
Finished Jul 20 05:01:04 PM PDT 24
Peak memory 211616 kb
Host smart-d0856a9d-be77-486c-acef-101d5c7eb2aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398732687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3398732687
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3723352501
Short name T946
Test name
Test status
Simulation time 109401383 ps
CPU time 2 seconds
Started Jul 20 05:00:47 PM PDT 24
Finished Jul 20 05:00:52 PM PDT 24
Peak memory 217820 kb
Host smart-8fcac43c-a9a5-44a7-a142-e82726610d02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723352501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3723352501
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.4135666933
Short name T137
Test name
Test status
Simulation time 119278695 ps
CPU time 4.19 seconds
Started Jul 20 05:00:46 PM PDT 24
Finished Jul 20 05:00:53 PM PDT 24
Peak memory 217852 kb
Host smart-ce6221d3-3645-476a-944d-6d3927b3c339
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135666933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.4135666933
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.855688334
Short name T963
Test name
Test status
Simulation time 14143184 ps
CPU time 1.2 seconds
Started Jul 20 05:00:45 PM PDT 24
Finished Jul 20 05:00:48 PM PDT 24
Peak memory 218004 kb
Host smart-0a445259-19b1-4e6a-bb1b-0a0f5b2c3c77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855688334 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.855688334
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3146517803
Short name T204
Test name
Test status
Simulation time 19265799 ps
CPU time 1.26 seconds
Started Jul 20 05:00:48 PM PDT 24
Finished Jul 20 05:00:52 PM PDT 24
Peak memory 211664 kb
Host smart-e8b4d3b4-4657-4c06-9725-4d4b2f495766
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146517803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.3146517803
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4048186022
Short name T948
Test name
Test status
Simulation time 515552586 ps
CPU time 2.41 seconds
Started Jul 20 05:00:48 PM PDT 24
Finished Jul 20 05:00:53 PM PDT 24
Peak memory 218824 kb
Host smart-a08adc60-50e8-4a5d-9d21-f72e18e6ea74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048186022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.4048186022
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.480991334
Short name T962
Test name
Test status
Simulation time 29871716 ps
CPU time 1.16 seconds
Started Jul 20 05:00:47 PM PDT 24
Finished Jul 20 05:00:51 PM PDT 24
Peak memory 217924 kb
Host smart-71a6a714-fc82-4358-9a72-4f9886bd67ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480991334 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.480991334
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.676718350
Short name T881
Test name
Test status
Simulation time 118194804 ps
CPU time 0.85 seconds
Started Jul 20 05:00:47 PM PDT 24
Finished Jul 20 05:00:51 PM PDT 24
Peak memory 209112 kb
Host smart-6435fac3-6b62-4e69-861d-f9124b58b9c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676718350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.676718350
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3816168875
Short name T965
Test name
Test status
Simulation time 36765457 ps
CPU time 1.79 seconds
Started Jul 20 05:00:48 PM PDT 24
Finished Jul 20 05:00:52 PM PDT 24
Peak memory 217856 kb
Host smart-d09ff7fa-2f85-4d9d-8451-ee02534c7543
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816168875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3816168875
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2059296843
Short name T903
Test name
Test status
Simulation time 203990496 ps
CPU time 3.21 seconds
Started Jul 20 05:00:50 PM PDT 24
Finished Jul 20 05:00:55 PM PDT 24
Peak memory 217864 kb
Host smart-d9b0bf82-2a21-4bd0-bba8-95dc9f153fa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059296843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2059296843
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2485039624
Short name T132
Test name
Test status
Simulation time 40987754 ps
CPU time 1.78 seconds
Started Jul 20 05:00:48 PM PDT 24
Finished Jul 20 05:00:53 PM PDT 24
Peak memory 221940 kb
Host smart-841535e4-77f3-4e9f-8a87-4b0e5ce37bd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485039624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2485039624
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.995172377
Short name T900
Test name
Test status
Simulation time 39327591 ps
CPU time 1.49 seconds
Started Jul 20 05:00:49 PM PDT 24
Finished Jul 20 05:00:53 PM PDT 24
Peak memory 217980 kb
Host smart-6171f323-2da8-4bf1-b451-c17230f674d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995172377 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.995172377
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1175382760
Short name T953
Test name
Test status
Simulation time 15923003 ps
CPU time 0.89 seconds
Started Jul 20 05:00:50 PM PDT 24
Finished Jul 20 05:00:53 PM PDT 24
Peak memory 209612 kb
Host smart-f62d0556-a091-49c4-978d-0a20aa65934b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175382760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1175382760
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1495200885
Short name T917
Test name
Test status
Simulation time 20253509 ps
CPU time 1.24 seconds
Started Jul 20 05:00:45 PM PDT 24
Finished Jul 20 05:00:48 PM PDT 24
Peak memory 209656 kb
Host smart-ffc3ca0e-779f-4636-8be9-7568f4659016
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495200885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1495200885
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.80774027
Short name T123
Test name
Test status
Simulation time 268448098 ps
CPU time 1.3 seconds
Started Jul 20 05:00:43 PM PDT 24
Finished Jul 20 05:00:45 PM PDT 24
Peak memory 217972 kb
Host smart-c4e038a9-bedd-4646-909d-55456b5f0996
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80774027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.80774027
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1000098409
Short name T935
Test name
Test status
Simulation time 93891225 ps
CPU time 1.72 seconds
Started Jul 20 05:00:46 PM PDT 24
Finished Jul 20 05:00:49 PM PDT 24
Peak memory 218100 kb
Host smart-7dd8060b-a77c-41a4-a1a3-01dd409b925a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000098409 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1000098409
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2657261174
Short name T207
Test name
Test status
Simulation time 11488912 ps
CPU time 0.88 seconds
Started Jul 20 05:00:45 PM PDT 24
Finished Jul 20 05:00:48 PM PDT 24
Peak memory 209668 kb
Host smart-ecf86a0c-6005-4d85-937b-aa64236d0f4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657261174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2657261174
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2310163910
Short name T206
Test name
Test status
Simulation time 84979631 ps
CPU time 1.03 seconds
Started Jul 20 05:00:46 PM PDT 24
Finished Jul 20 05:00:50 PM PDT 24
Peak memory 209504 kb
Host smart-7dee482c-9fc5-4e1c-8759-99ba4e45a849
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310163910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2310163910
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1011861959
Short name T975
Test name
Test status
Simulation time 136747295 ps
CPU time 5.2 seconds
Started Jul 20 05:00:48 PM PDT 24
Finished Jul 20 05:00:56 PM PDT 24
Peak memory 217864 kb
Host smart-0ceebe82-e9f0-419c-8c90-bb28a935f347
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011861959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1011861959
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1945331053
Short name T114
Test name
Test status
Simulation time 221403730 ps
CPU time 6.05 seconds
Started Jul 20 05:00:50 PM PDT 24
Finished Jul 20 05:00:58 PM PDT 24
Peak memory 217852 kb
Host smart-51c4ff9c-5237-43ad-8829-55e07553f116
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945331053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1945331053
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.560913920
Short name T945
Test name
Test status
Simulation time 55305275 ps
CPU time 1.37 seconds
Started Jul 20 05:00:48 PM PDT 24
Finished Jul 20 05:00:52 PM PDT 24
Peak memory 218032 kb
Host smart-ba15ee91-5a1c-4fc4-b838-f5deac7b086e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560913920 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.560913920
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3969894183
Short name T852
Test name
Test status
Simulation time 14623930 ps
CPU time 1.06 seconds
Started Jul 20 05:00:48 PM PDT 24
Finished Jul 20 05:00:52 PM PDT 24
Peak memory 209644 kb
Host smart-a53af80b-9018-4af0-b520-7d85093809b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969894183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3969894183
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1006278408
Short name T899
Test name
Test status
Simulation time 46502421 ps
CPU time 1.02 seconds
Started Jul 20 05:00:50 PM PDT 24
Finished Jul 20 05:00:53 PM PDT 24
Peak memory 209716 kb
Host smart-30b1d737-83bf-4c7e-83d5-de81258a23ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006278408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1006278408
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.625755290
Short name T887
Test name
Test status
Simulation time 251603357 ps
CPU time 4.81 seconds
Started Jul 20 05:00:46 PM PDT 24
Finished Jul 20 05:00:53 PM PDT 24
Peak memory 217856 kb
Host smart-7718e56a-de11-4b27-ae6a-6d5556c0fb07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625755290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.625755290
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2759848322
Short name T877
Test name
Test status
Simulation time 172616055 ps
CPU time 2.11 seconds
Started Jul 20 05:00:49 PM PDT 24
Finished Jul 20 05:00:54 PM PDT 24
Peak memory 217912 kb
Host smart-025c84f1-13eb-44a5-ab55-e47611a76574
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759848322 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2759848322
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.415263539
Short name T908
Test name
Test status
Simulation time 15736340 ps
CPU time 0.88 seconds
Started Jul 20 05:00:46 PM PDT 24
Finished Jul 20 05:00:49 PM PDT 24
Peak memory 209648 kb
Host smart-1ee3714a-8528-497c-8a7e-c2eab9db0363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415263539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.415263539
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1795642586
Short name T889
Test name
Test status
Simulation time 78983516 ps
CPU time 1.25 seconds
Started Jul 20 05:00:48 PM PDT 24
Finished Jul 20 05:00:52 PM PDT 24
Peak memory 211640 kb
Host smart-4c03be64-ccba-4ca4-9547-c9e8780bb3c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795642586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1795642586
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2314119982
Short name T129
Test name
Test status
Simulation time 263428068 ps
CPU time 2.13 seconds
Started Jul 20 05:00:47 PM PDT 24
Finished Jul 20 05:00:52 PM PDT 24
Peak memory 217788 kb
Host smart-4240e307-db08-46f8-8c54-8ebf092cace8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314119982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2314119982
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.804571989
Short name T144
Test name
Test status
Simulation time 247371769 ps
CPU time 2.09 seconds
Started Jul 20 05:00:45 PM PDT 24
Finished Jul 20 05:00:48 PM PDT 24
Peak memory 217832 kb
Host smart-827851b8-f5b5-4342-9928-d061dbb44708
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804571989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.804571989
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2924109726
Short name T976
Test name
Test status
Simulation time 27241334 ps
CPU time 0.84 seconds
Started Jul 20 05:00:46 PM PDT 24
Finished Jul 20 05:00:50 PM PDT 24
Peak memory 209460 kb
Host smart-447f07d3-1be0-4fa4-826e-0885e6f1c79d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924109726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2924109726
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.291745938
Short name T886
Test name
Test status
Simulation time 39203315 ps
CPU time 1.76 seconds
Started Jul 20 05:00:48 PM PDT 24
Finished Jul 20 05:00:53 PM PDT 24
Peak memory 209420 kb
Host smart-2fbc43db-b98c-4412-870b-6cb3911a1f8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291745938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.291745938
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1553878009
Short name T897
Test name
Test status
Simulation time 20390748 ps
CPU time 1.16 seconds
Started Jul 20 05:00:48 PM PDT 24
Finished Jul 20 05:00:52 PM PDT 24
Peak memory 217988 kb
Host smart-538c64aa-784d-41e1-b967-ecd5881db014
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553878009 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1553878009
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3014656776
Short name T197
Test name
Test status
Simulation time 27902106 ps
CPU time 0.89 seconds
Started Jul 20 05:00:49 PM PDT 24
Finished Jul 20 05:00:53 PM PDT 24
Peak memory 209592 kb
Host smart-bf3708d7-59ff-47e0-a582-c77d49c00aa2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014656776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3014656776
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.774685927
Short name T961
Test name
Test status
Simulation time 73365716 ps
CPU time 1 seconds
Started Jul 20 05:00:48 PM PDT 24
Finished Jul 20 05:00:52 PM PDT 24
Peak memory 209664 kb
Host smart-d361d4b5-f77f-407b-b213-46316034f189
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774685927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.774685927
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.4159368208
Short name T967
Test name
Test status
Simulation time 58749984 ps
CPU time 1.93 seconds
Started Jul 20 05:00:45 PM PDT 24
Finished Jul 20 05:00:49 PM PDT 24
Peak memory 217904 kb
Host smart-f8476cda-b972-41b0-beb6-1fa388ffa729
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159368208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.4159368208
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.274272908
Short name T159
Test name
Test status
Simulation time 17779860 ps
CPU time 1.24 seconds
Started Jul 20 05:00:47 PM PDT 24
Finished Jul 20 05:00:50 PM PDT 24
Peak memory 218236 kb
Host smart-5cb85263-523e-45fd-8e14-a920020de7dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274272908 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.274272908
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.4227632866
Short name T929
Test name
Test status
Simulation time 39334601 ps
CPU time 0.88 seconds
Started Jul 20 05:00:49 PM PDT 24
Finished Jul 20 05:00:52 PM PDT 24
Peak memory 209556 kb
Host smart-905de873-608b-4434-850c-6ddf18034004
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227632866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.4227632866
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3156973125
Short name T203
Test name
Test status
Simulation time 75162760 ps
CPU time 1.19 seconds
Started Jul 20 05:00:45 PM PDT 24
Finished Jul 20 05:00:47 PM PDT 24
Peak memory 209588 kb
Host smart-813bbc36-a673-4c44-b388-4636681724c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156973125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3156973125
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2817628970
Short name T124
Test name
Test status
Simulation time 222229238 ps
CPU time 3.1 seconds
Started Jul 20 05:00:47 PM PDT 24
Finished Jul 20 05:00:52 PM PDT 24
Peak memory 218020 kb
Host smart-03c624e7-5a8c-473b-88d9-1f4ec03cbc8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817628970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2817628970
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.363590023
Short name T195
Test name
Test status
Simulation time 20606845 ps
CPU time 1.44 seconds
Started Jul 20 05:00:12 PM PDT 24
Finished Jul 20 05:00:14 PM PDT 24
Peak memory 209728 kb
Host smart-83626c85-5a8b-4e1c-8601-228081f34265
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363590023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.363590023
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1473813141
Short name T855
Test name
Test status
Simulation time 67787065 ps
CPU time 1.95 seconds
Started Jul 20 05:00:13 PM PDT 24
Finished Jul 20 05:00:15 PM PDT 24
Peak memory 209616 kb
Host smart-e3a2a128-22e9-416e-a8be-e2b0f37e45bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473813141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1473813141
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.141667885
Short name T196
Test name
Test status
Simulation time 19670933 ps
CPU time 1.35 seconds
Started Jul 20 05:00:15 PM PDT 24
Finished Jul 20 05:00:18 PM PDT 24
Peak memory 220480 kb
Host smart-e2857996-4fca-4eec-9531-19251056b0e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141667885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset
.141667885
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1748344753
Short name T906
Test name
Test status
Simulation time 39301135 ps
CPU time 1.18 seconds
Started Jul 20 05:00:15 PM PDT 24
Finished Jul 20 05:00:17 PM PDT 24
Peak memory 219312 kb
Host smart-48fe98d7-650c-45c1-8819-4277c88d8535
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748344753 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1748344753
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3952808314
Short name T189
Test name
Test status
Simulation time 12468228 ps
CPU time 1 seconds
Started Jul 20 05:00:14 PM PDT 24
Finished Jul 20 05:00:17 PM PDT 24
Peak memory 209644 kb
Host smart-1d577e16-4f7e-4730-951d-1b248141863d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952808314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3952808314
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2854770044
Short name T860
Test name
Test status
Simulation time 30960198 ps
CPU time 1 seconds
Started Jul 20 05:00:15 PM PDT 24
Finished Jul 20 05:00:17 PM PDT 24
Peak memory 209536 kb
Host smart-f8d358eb-8551-40c9-bdff-4479d45cbf24
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854770044 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2854770044
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.258591895
Short name T863
Test name
Test status
Simulation time 1225864093 ps
CPU time 5.02 seconds
Started Jul 20 05:00:15 PM PDT 24
Finished Jul 20 05:00:21 PM PDT 24
Peak memory 209612 kb
Host smart-4dc7384b-d227-4475-a513-6ba221cf9e85
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258591895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.258591895
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.377562275
Short name T931
Test name
Test status
Simulation time 632328688 ps
CPU time 6.82 seconds
Started Jul 20 05:00:16 PM PDT 24
Finished Jul 20 05:00:24 PM PDT 24
Peak memory 208824 kb
Host smart-c193128e-4f7d-4abe-8c62-5b1613b625e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377562275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.377562275
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1389072529
Short name T873
Test name
Test status
Simulation time 367237097 ps
CPU time 1.51 seconds
Started Jul 20 05:00:15 PM PDT 24
Finished Jul 20 05:00:18 PM PDT 24
Peak memory 211084 kb
Host smart-1a762bd5-9949-4f60-b67d-18cae55c33ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389072529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1389072529
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1344108939
Short name T876
Test name
Test status
Simulation time 169823351 ps
CPU time 3.64 seconds
Started Jul 20 05:00:15 PM PDT 24
Finished Jul 20 05:00:20 PM PDT 24
Peak memory 218836 kb
Host smart-73536434-0ac1-41ff-8d14-11be04f12f04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134410
8939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1344108939
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2810812674
Short name T871
Test name
Test status
Simulation time 79754137 ps
CPU time 2.46 seconds
Started Jul 20 05:00:15 PM PDT 24
Finished Jul 20 05:00:19 PM PDT 24
Peak memory 209564 kb
Host smart-74542a09-b027-4c63-9df3-8a50798768fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810812674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2810812674
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.49855614
Short name T942
Test name
Test status
Simulation time 20647361 ps
CPU time 1.28 seconds
Started Jul 20 05:00:13 PM PDT 24
Finished Jul 20 05:00:15 PM PDT 24
Peak memory 217864 kb
Host smart-b32e9578-d6fb-46a8-94a7-a8e91617ce07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49855614 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.49855614
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.527600443
Short name T922
Test name
Test status
Simulation time 64970081 ps
CPU time 1.42 seconds
Started Jul 20 05:00:12 PM PDT 24
Finished Jul 20 05:00:14 PM PDT 24
Peak memory 209880 kb
Host smart-a160c089-7334-4031-a898-e3339f35f181
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527600443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.527600443
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2212198529
Short name T937
Test name
Test status
Simulation time 75392747 ps
CPU time 2.2 seconds
Started Jul 20 05:00:15 PM PDT 24
Finished Jul 20 05:00:18 PM PDT 24
Peak memory 218016 kb
Host smart-c7e8a999-31e7-4513-9a9e-299c0f2174a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212198529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2212198529
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1677698651
Short name T133
Test name
Test status
Simulation time 78749638 ps
CPU time 2.07 seconds
Started Jul 20 05:00:12 PM PDT 24
Finished Jul 20 05:00:15 PM PDT 24
Peak memory 222324 kb
Host smart-b0725bf6-1c46-427e-9c2e-f78bf86bb0a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677698651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1677698651
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1825105308
Short name T919
Test name
Test status
Simulation time 99662353 ps
CPU time 1.3 seconds
Started Jul 20 05:00:29 PM PDT 24
Finished Jul 20 05:00:31 PM PDT 24
Peak memory 209484 kb
Host smart-6da71374-647b-4fb0-8881-48534696c7b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825105308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1825105308
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3832574387
Short name T160
Test name
Test status
Simulation time 376495963 ps
CPU time 2.27 seconds
Started Jul 20 05:00:23 PM PDT 24
Finished Jul 20 05:00:27 PM PDT 24
Peak memory 209600 kb
Host smart-24c318a4-478d-496f-b8f0-1b70346bac47
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832574387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3832574387
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2760695540
Short name T950
Test name
Test status
Simulation time 16357759 ps
CPU time 1.27 seconds
Started Jul 20 05:00:21 PM PDT 24
Finished Jul 20 05:00:23 PM PDT 24
Peak memory 218408 kb
Host smart-64057b43-304a-474f-bbdd-cfe8bbcd029f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760695540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2760695540
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2898470867
Short name T924
Test name
Test status
Simulation time 24611266 ps
CPU time 1.49 seconds
Started Jul 20 05:00:23 PM PDT 24
Finished Jul 20 05:00:26 PM PDT 24
Peak memory 217888 kb
Host smart-d1afa521-525d-4a1d-a89a-36b868f1e031
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898470867 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2898470867
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1771853556
Short name T194
Test name
Test status
Simulation time 13840758 ps
CPU time 0.97 seconds
Started Jul 20 05:00:22 PM PDT 24
Finished Jul 20 05:00:24 PM PDT 24
Peak memory 209656 kb
Host smart-637fb569-fa1f-4cfe-80c2-22aed1572f62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771853556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1771853556
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.789710966
Short name T911
Test name
Test status
Simulation time 28770785 ps
CPU time 1.39 seconds
Started Jul 20 05:00:22 PM PDT 24
Finished Jul 20 05:00:24 PM PDT 24
Peak memory 208272 kb
Host smart-1ff7a8ee-8265-4847-bca9-0af6020de23c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789710966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.789710966
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1234252225
Short name T966
Test name
Test status
Simulation time 1451398071 ps
CPU time 15.75 seconds
Started Jul 20 05:00:11 PM PDT 24
Finished Jul 20 05:00:27 PM PDT 24
Peak memory 208920 kb
Host smart-2ce74625-fb9d-47b5-906d-656affac5622
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234252225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1234252225
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.30781321
Short name T925
Test name
Test status
Simulation time 422425316 ps
CPU time 6.5 seconds
Started Jul 20 05:00:13 PM PDT 24
Finished Jul 20 05:00:20 PM PDT 24
Peak memory 209640 kb
Host smart-c1898fec-a766-4c57-889d-c0362d98a416
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30781321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.30781321
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2461820812
Short name T145
Test name
Test status
Simulation time 107736426 ps
CPU time 1.95 seconds
Started Jul 20 05:00:12 PM PDT 24
Finished Jul 20 05:00:14 PM PDT 24
Peak memory 211404 kb
Host smart-5a5b3cff-69a8-4017-beb0-e139cb7013e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461820812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2461820812
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.396378346
Short name T163
Test name
Test status
Simulation time 440491055 ps
CPU time 2.58 seconds
Started Jul 20 05:00:13 PM PDT 24
Finished Jul 20 05:00:16 PM PDT 24
Peak memory 218032 kb
Host smart-03220659-f858-4431-b7f8-24b26e92e4e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396378
346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.396378346
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3889445734
Short name T951
Test name
Test status
Simulation time 164441388 ps
CPU time 1.59 seconds
Started Jul 20 05:00:15 PM PDT 24
Finished Jul 20 05:00:18 PM PDT 24
Peak memory 209652 kb
Host smart-dd7a8317-7c0b-4451-80a3-a91849674bd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889445734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3889445734
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.643809770
Short name T205
Test name
Test status
Simulation time 22178537 ps
CPU time 1.58 seconds
Started Jul 20 05:00:16 PM PDT 24
Finished Jul 20 05:00:19 PM PDT 24
Peak memory 217760 kb
Host smart-033e033d-77aa-436f-b2e2-c4551185ebb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643809770 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.643809770
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3252383115
Short name T921
Test name
Test status
Simulation time 65073367 ps
CPU time 1.39 seconds
Started Jul 20 05:00:23 PM PDT 24
Finished Jul 20 05:00:25 PM PDT 24
Peak memory 211708 kb
Host smart-d35de89e-6b37-40a6-a175-1c65b1626c63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252383115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3252383115
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.670629588
Short name T882
Test name
Test status
Simulation time 65419968 ps
CPU time 2.03 seconds
Started Jul 20 05:00:23 PM PDT 24
Finished Jul 20 05:00:27 PM PDT 24
Peak memory 218872 kb
Host smart-d16d8ab6-58a7-4bb1-a82f-71804e2a2d72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670629588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.670629588
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.747447465
Short name T192
Test name
Test status
Simulation time 32820870 ps
CPU time 1.23 seconds
Started Jul 20 05:00:22 PM PDT 24
Finished Jul 20 05:00:24 PM PDT 24
Peak memory 209640 kb
Host smart-fc435817-7abe-44ee-a0a9-36b642a0dbac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747447465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing
.747447465
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.802063151
Short name T858
Test name
Test status
Simulation time 19054326 ps
CPU time 1.28 seconds
Started Jul 20 05:00:23 PM PDT 24
Finished Jul 20 05:00:25 PM PDT 24
Peak memory 209592 kb
Host smart-64bab993-5b1a-4898-9800-e69f9d36f6e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802063151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.802063151
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1351050673
Short name T857
Test name
Test status
Simulation time 19400311 ps
CPU time 1.11 seconds
Started Jul 20 05:00:20 PM PDT 24
Finished Jul 20 05:00:21 PM PDT 24
Peak memory 211696 kb
Host smart-a5890b24-66ad-4030-b93e-8078e572a621
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351050673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1351050673
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3859526693
Short name T896
Test name
Test status
Simulation time 17684100 ps
CPU time 1.28 seconds
Started Jul 20 05:00:22 PM PDT 24
Finished Jul 20 05:00:24 PM PDT 24
Peak memory 217972 kb
Host smart-874c5f70-61c8-4413-b0fd-fd30ea6111f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859526693 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3859526693
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.4154082281
Short name T954
Test name
Test status
Simulation time 34639503 ps
CPU time 0.95 seconds
Started Jul 20 05:00:22 PM PDT 24
Finished Jul 20 05:00:24 PM PDT 24
Peak memory 209652 kb
Host smart-811d7f0d-7042-42f2-bdda-d06ba3dbba9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154082281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.4154082281
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3048552194
Short name T941
Test name
Test status
Simulation time 51661017 ps
CPU time 2.03 seconds
Started Jul 20 05:00:23 PM PDT 24
Finished Jul 20 05:00:26 PM PDT 24
Peak memory 209552 kb
Host smart-299cb942-d5d2-4326-aa76-540b8fb76ffc
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048552194 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3048552194
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1874534893
Short name T974
Test name
Test status
Simulation time 227568680 ps
CPU time 5.83 seconds
Started Jul 20 05:00:28 PM PDT 24
Finished Jul 20 05:00:35 PM PDT 24
Peak memory 208696 kb
Host smart-d67fd950-6145-441a-92cb-02cdf8976c64
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874534893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1874534893
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3179354670
Short name T928
Test name
Test status
Simulation time 6007535194 ps
CPU time 34.1 seconds
Started Jul 20 05:00:21 PM PDT 24
Finished Jul 20 05:00:55 PM PDT 24
Peak memory 209644 kb
Host smart-aad35e8c-ebf8-4bcf-aec2-5e1f50dde69c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179354670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3179354670
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1888535008
Short name T952
Test name
Test status
Simulation time 124713226 ps
CPU time 3.62 seconds
Started Jul 20 05:00:23 PM PDT 24
Finished Jul 20 05:00:28 PM PDT 24
Peak memory 209656 kb
Host smart-7bd51a01-229f-473a-ac2f-ff003fa65f76
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888535008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1888535008
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4184540822
Short name T916
Test name
Test status
Simulation time 160708628 ps
CPU time 1.67 seconds
Started Jul 20 05:00:21 PM PDT 24
Finished Jul 20 05:00:24 PM PDT 24
Peak memory 218924 kb
Host smart-d5cd0c2f-fd62-4868-b2d6-7d2d068b879a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418454
0822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4184540822
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3949770453
Short name T895
Test name
Test status
Simulation time 116656336 ps
CPU time 2.18 seconds
Started Jul 20 05:00:21 PM PDT 24
Finished Jul 20 05:00:24 PM PDT 24
Peak memory 209676 kb
Host smart-ba624e1f-7a7e-44dd-a0d1-36e4c563c47d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949770453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3949770453
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2188483948
Short name T901
Test name
Test status
Simulation time 98005285 ps
CPU time 1.1 seconds
Started Jul 20 05:00:23 PM PDT 24
Finished Jul 20 05:00:26 PM PDT 24
Peak memory 209668 kb
Host smart-d59be52d-337d-46cc-827d-668e801f1930
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188483948 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2188483948
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1643721973
Short name T934
Test name
Test status
Simulation time 259310319 ps
CPU time 1.3 seconds
Started Jul 20 05:00:21 PM PDT 24
Finished Jul 20 05:00:22 PM PDT 24
Peak memory 209640 kb
Host smart-1ac0d694-956f-4a5c-a481-55062521221e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643721973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1643721973
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1701283715
Short name T118
Test name
Test status
Simulation time 57092779 ps
CPU time 2.46 seconds
Started Jul 20 05:00:23 PM PDT 24
Finished Jul 20 05:00:27 PM PDT 24
Peak memory 217824 kb
Host smart-6559b50a-6b42-4d7b-a316-bb69fe515063
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701283715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1701283715
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2628294236
Short name T870
Test name
Test status
Simulation time 173206288 ps
CPU time 0.99 seconds
Started Jul 20 05:00:43 PM PDT 24
Finished Jul 20 05:00:44 PM PDT 24
Peak memory 218824 kb
Host smart-2d9e5567-7f14-487f-bf47-816adef3f8ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628294236 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2628294236
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.425953654
Short name T191
Test name
Test status
Simulation time 18000266 ps
CPU time 0.89 seconds
Started Jul 20 05:00:44 PM PDT 24
Finished Jul 20 05:00:46 PM PDT 24
Peak memory 209460 kb
Host smart-eeef0c30-8e76-4ba2-9010-617ce53aac2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425953654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.425953654
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1454278193
Short name T884
Test name
Test status
Simulation time 162788708 ps
CPU time 1.71 seconds
Started Jul 20 05:00:44 PM PDT 24
Finished Jul 20 05:00:47 PM PDT 24
Peak memory 209352 kb
Host smart-e6723bd9-a4c1-412c-af7f-92c0d96f5b68
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454278193 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1454278193
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.231232806
Short name T850
Test name
Test status
Simulation time 734866632 ps
CPU time 3.91 seconds
Started Jul 20 05:00:28 PM PDT 24
Finished Jul 20 05:00:33 PM PDT 24
Peak memory 209340 kb
Host smart-4498887b-0935-4c4d-8775-08b33f5b9066
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231232806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.231232806
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.420809062
Short name T869
Test name
Test status
Simulation time 1245431860 ps
CPU time 11.31 seconds
Started Jul 20 05:00:43 PM PDT 24
Finished Jul 20 05:00:55 PM PDT 24
Peak memory 209292 kb
Host smart-262497a7-5f56-42a8-92a7-ab89fb5e9f37
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420809062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.420809062
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2671888034
Short name T912
Test name
Test status
Simulation time 181801628 ps
CPU time 1.29 seconds
Started Jul 20 05:00:21 PM PDT 24
Finished Jul 20 05:00:23 PM PDT 24
Peak memory 211040 kb
Host smart-86eb865a-74d8-4765-91f6-d94c0e6e2322
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671888034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2671888034
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2205608573
Short name T914
Test name
Test status
Simulation time 1459535874 ps
CPU time 2.21 seconds
Started Jul 20 05:00:31 PM PDT 24
Finished Jul 20 05:00:33 PM PDT 24
Peak memory 217980 kb
Host smart-58dc8f3e-fed8-45b0-9605-fb92ea459cf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220560
8573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2205608573
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.4280112043
Short name T859
Test name
Test status
Simulation time 132970751 ps
CPU time 1.5 seconds
Started Jul 20 05:00:30 PM PDT 24
Finished Jul 20 05:00:32 PM PDT 24
Peak memory 209648 kb
Host smart-19400755-7dd8-4fb6-8842-61971ece4e72
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280112043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.4280112043
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3642055479
Short name T955
Test name
Test status
Simulation time 58418143 ps
CPU time 1.48 seconds
Started Jul 20 05:00:44 PM PDT 24
Finished Jul 20 05:00:47 PM PDT 24
Peak memory 211436 kb
Host smart-2b670863-cbc2-4d50-a923-e342c03c6518
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642055479 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3642055479
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.750080162
Short name T936
Test name
Test status
Simulation time 65256583 ps
CPU time 1.07 seconds
Started Jul 20 05:00:30 PM PDT 24
Finished Jul 20 05:00:31 PM PDT 24
Peak memory 209636 kb
Host smart-d51ec9b8-8f3e-4328-8d00-56f62924581e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750080162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.750080162
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3702044496
Short name T902
Test name
Test status
Simulation time 54093313 ps
CPU time 1.59 seconds
Started Jul 20 05:00:43 PM PDT 24
Finished Jul 20 05:00:46 PM PDT 24
Peak memory 217652 kb
Host smart-cec7cf0c-2f4a-4005-96df-c30bb7f7193f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702044496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3702044496
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1440589312
Short name T134
Test name
Test status
Simulation time 140327101 ps
CPU time 2.75 seconds
Started Jul 20 05:00:27 PM PDT 24
Finished Jul 20 05:00:30 PM PDT 24
Peak memory 222776 kb
Host smart-8e50d4ec-943c-4de7-97ac-1a90bbf6be5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440589312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1440589312
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1357344555
Short name T943
Test name
Test status
Simulation time 40442010 ps
CPU time 1.21 seconds
Started Jul 20 05:00:36 PM PDT 24
Finished Jul 20 05:00:38 PM PDT 24
Peak memory 219012 kb
Host smart-ad339d90-b2fc-4d15-8749-53e19c064214
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357344555 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1357344555
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3074412190
Short name T862
Test name
Test status
Simulation time 52517062 ps
CPU time 0.86 seconds
Started Jul 20 05:00:44 PM PDT 24
Finished Jul 20 05:00:46 PM PDT 24
Peak memory 209420 kb
Host smart-5a64052c-4602-46d7-aa9a-277fc77706f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074412190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3074412190
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1677864034
Short name T915
Test name
Test status
Simulation time 107450906 ps
CPU time 0.93 seconds
Started Jul 20 05:00:29 PM PDT 24
Finished Jul 20 05:00:31 PM PDT 24
Peak memory 209548 kb
Host smart-d9c631eb-005e-4068-b1a5-ad803b54ff77
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677864034 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1677864034
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2006122318
Short name T904
Test name
Test status
Simulation time 1161206900 ps
CPU time 13.19 seconds
Started Jul 20 05:00:44 PM PDT 24
Finished Jul 20 05:00:58 PM PDT 24
Peak memory 209296 kb
Host smart-54b93190-2672-4297-a126-e3042528dbaa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006122318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2006122318
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1567182854
Short name T878
Test name
Test status
Simulation time 1040697100 ps
CPU time 6.16 seconds
Started Jul 20 05:00:31 PM PDT 24
Finished Jul 20 05:00:38 PM PDT 24
Peak memory 208904 kb
Host smart-4134316c-8ed9-4eaf-a9fa-64488574109f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567182854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1567182854
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1749785101
Short name T868
Test name
Test status
Simulation time 272518467 ps
CPU time 3.55 seconds
Started Jul 20 05:00:28 PM PDT 24
Finished Jul 20 05:00:33 PM PDT 24
Peak memory 211160 kb
Host smart-11af5c6e-a634-4044-bbac-da8d1fc11748
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749785101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1749785101
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1901752322
Short name T920
Test name
Test status
Simulation time 200797552 ps
CPU time 3.69 seconds
Started Jul 20 05:00:30 PM PDT 24
Finished Jul 20 05:00:35 PM PDT 24
Peak memory 217856 kb
Host smart-e5c701b5-fa07-4234-8d49-e6930fc0bcfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190175
2322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1901752322
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1060144177
Short name T853
Test name
Test status
Simulation time 67031993 ps
CPU time 1.45 seconds
Started Jul 20 05:00:30 PM PDT 24
Finished Jul 20 05:00:32 PM PDT 24
Peak memory 209460 kb
Host smart-1464c65f-b09e-4bd8-80ef-123c2d6b89a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060144177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1060144177
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4277513131
Short name T930
Test name
Test status
Simulation time 128109129 ps
CPU time 1.33 seconds
Started Jul 20 05:00:44 PM PDT 24
Finished Jul 20 05:00:46 PM PDT 24
Peak memory 211332 kb
Host smart-4bdfeee1-216d-47c3-8120-1cb8fa714fcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277513131 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.4277513131
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1989281597
Short name T200
Test name
Test status
Simulation time 37809128 ps
CPU time 1.9 seconds
Started Jul 20 05:00:38 PM PDT 24
Finished Jul 20 05:00:40 PM PDT 24
Peak memory 211748 kb
Host smart-3fa40060-995b-4f9d-9a9e-d5c882c9785a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989281597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1989281597
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.47379377
Short name T126
Test name
Test status
Simulation time 2096874836 ps
CPU time 3.41 seconds
Started Jul 20 05:00:30 PM PDT 24
Finished Jul 20 05:00:34 PM PDT 24
Peak memory 217728 kb
Host smart-a10cbf25-0c5b-4afc-9d07-838739c285b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47379377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.47379377
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1148036704
Short name T140
Test name
Test status
Simulation time 90445459 ps
CPU time 1.32 seconds
Started Jul 20 05:00:40 PM PDT 24
Finished Jul 20 05:00:42 PM PDT 24
Peak memory 217944 kb
Host smart-7030fa60-5c21-445a-948b-36849194cdf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148036704 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1148036704
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3462060066
Short name T147
Test name
Test status
Simulation time 47198741 ps
CPU time 0.9 seconds
Started Jul 20 05:00:37 PM PDT 24
Finished Jul 20 05:00:38 PM PDT 24
Peak memory 209596 kb
Host smart-93b8cf92-f014-4013-9868-0e4257e3d6f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462060066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3462060066
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4150714191
Short name T939
Test name
Test status
Simulation time 112148703 ps
CPU time 3.25 seconds
Started Jul 20 05:00:37 PM PDT 24
Finished Jul 20 05:00:41 PM PDT 24
Peak memory 209564 kb
Host smart-6ce45b0e-943c-4688-b364-3be87bf496ee
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150714191 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.4150714191
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3709730635
Short name T865
Test name
Test status
Simulation time 546554730 ps
CPU time 4.98 seconds
Started Jul 20 05:00:35 PM PDT 24
Finished Jul 20 05:00:41 PM PDT 24
Peak memory 209544 kb
Host smart-d18d4696-c05a-4ae6-a5c4-bbc6ec923a05
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709730635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3709730635
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.462127778
Short name T875
Test name
Test status
Simulation time 425729812 ps
CPU time 10.67 seconds
Started Jul 20 05:00:40 PM PDT 24
Finished Jul 20 05:00:51 PM PDT 24
Peak memory 209664 kb
Host smart-2e4ad86f-a0e5-470f-910e-3c8b40361775
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462127778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.462127778
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1583359390
Short name T880
Test name
Test status
Simulation time 150699535 ps
CPU time 2.69 seconds
Started Jul 20 05:00:37 PM PDT 24
Finished Jul 20 05:00:40 PM PDT 24
Peak memory 211364 kb
Host smart-48b2f53e-395f-4547-8b87-c8b3c056800c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583359390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1583359390
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4162745914
Short name T894
Test name
Test status
Simulation time 50492651 ps
CPU time 1.57 seconds
Started Jul 20 05:00:39 PM PDT 24
Finished Jul 20 05:00:42 PM PDT 24
Peak memory 217952 kb
Host smart-c1bda0e3-720c-4e20-9931-6418a93eaae9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416274
5914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4162745914
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.476209358
Short name T907
Test name
Test status
Simulation time 75262858 ps
CPU time 2.58 seconds
Started Jul 20 05:00:38 PM PDT 24
Finished Jul 20 05:00:42 PM PDT 24
Peak memory 209548 kb
Host smart-7dfaf150-412b-4966-80fc-cb36e9ea4ad4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476209358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.476209358
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.597845334
Short name T120
Test name
Test status
Simulation time 20298162 ps
CPU time 1.34 seconds
Started Jul 20 05:00:39 PM PDT 24
Finished Jul 20 05:00:41 PM PDT 24
Peak memory 217740 kb
Host smart-84933943-96ef-4020-8b5c-091f50ee83f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597845334 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.597845334
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.716865651
Short name T932
Test name
Test status
Simulation time 93336904 ps
CPU time 1.15 seconds
Started Jul 20 05:00:38 PM PDT 24
Finished Jul 20 05:00:41 PM PDT 24
Peak memory 211668 kb
Host smart-2f272673-9beb-48ce-9d6b-e621daa02db3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716865651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.716865651
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2369641970
Short name T927
Test name
Test status
Simulation time 39714175 ps
CPU time 2.23 seconds
Started Jul 20 05:00:41 PM PDT 24
Finished Jul 20 05:00:44 PM PDT 24
Peak memory 219024 kb
Host smart-b1c494a3-aedb-479a-8e0d-d57c9f9851ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369641970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2369641970
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2342784316
Short name T874
Test name
Test status
Simulation time 20396553 ps
CPU time 1.34 seconds
Started Jul 20 05:00:36 PM PDT 24
Finished Jul 20 05:00:38 PM PDT 24
Peak memory 217976 kb
Host smart-2a3dcb99-2a6b-484e-af19-4bb8ba631eca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342784316 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.2342784316
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3115702775
Short name T193
Test name
Test status
Simulation time 53319294 ps
CPU time 1.07 seconds
Started Jul 20 05:00:39 PM PDT 24
Finished Jul 20 05:00:41 PM PDT 24
Peak memory 209648 kb
Host smart-ec2dc3be-d302-4947-8732-4af3cb548cfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115702775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3115702775
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3582312929
Short name T923
Test name
Test status
Simulation time 29257451 ps
CPU time 1.07 seconds
Started Jul 20 05:00:42 PM PDT 24
Finished Jul 20 05:00:44 PM PDT 24
Peak memory 208256 kb
Host smart-34731206-9ddd-45b1-96c4-4c60e1dd1b06
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582312929 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3582312929
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1597322783
Short name T121
Test name
Test status
Simulation time 1010450528 ps
CPU time 23.23 seconds
Started Jul 20 05:00:38 PM PDT 24
Finished Jul 20 05:01:02 PM PDT 24
Peak memory 208920 kb
Host smart-360faad3-d327-4116-bda8-9ea05b6c1f58
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597322783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1597322783
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3392823169
Short name T866
Test name
Test status
Simulation time 902712135 ps
CPU time 5.63 seconds
Started Jul 20 05:00:36 PM PDT 24
Finished Jul 20 05:00:42 PM PDT 24
Peak memory 209376 kb
Host smart-8eee8569-3ec2-4016-8fa1-a12de34c2d49
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392823169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3392823169
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1017902284
Short name T893
Test name
Test status
Simulation time 413410454 ps
CPU time 3.18 seconds
Started Jul 20 05:00:36 PM PDT 24
Finished Jul 20 05:00:40 PM PDT 24
Peak memory 211148 kb
Host smart-f489d7fa-60ca-42b8-bc8f-bf6869a2eda4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017902284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1017902284
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3592134037
Short name T913
Test name
Test status
Simulation time 104040982 ps
CPU time 1.72 seconds
Started Jul 20 05:00:40 PM PDT 24
Finished Jul 20 05:00:42 PM PDT 24
Peak memory 217824 kb
Host smart-40fc095c-239e-410d-aecf-8b0cdbdde982
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359213
4037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3592134037
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1126414653
Short name T905
Test name
Test status
Simulation time 127565753 ps
CPU time 1.46 seconds
Started Jul 20 05:00:36 PM PDT 24
Finished Jul 20 05:00:38 PM PDT 24
Peak memory 209668 kb
Host smart-198e25cf-b8b5-49c4-8803-7c2f92569458
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126414653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.1126414653
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.270969787
Short name T969
Test name
Test status
Simulation time 46290875 ps
CPU time 1.5 seconds
Started Jul 20 05:00:39 PM PDT 24
Finished Jul 20 05:00:41 PM PDT 24
Peak memory 209592 kb
Host smart-a1961d5d-fb87-473b-9b40-d93e18d6c90a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270969787 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.270969787
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3627278669
Short name T891
Test name
Test status
Simulation time 44839069 ps
CPU time 1.78 seconds
Started Jul 20 05:00:38 PM PDT 24
Finished Jul 20 05:00:41 PM PDT 24
Peak memory 209620 kb
Host smart-0e5702c4-0a37-433b-86a7-67cf123f95b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627278669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3627278669
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3520564253
Short name T956
Test name
Test status
Simulation time 44364070 ps
CPU time 1.89 seconds
Started Jul 20 05:00:37 PM PDT 24
Finished Jul 20 05:00:40 PM PDT 24
Peak memory 217776 kb
Host smart-26fc88ef-005c-435c-bdc2-5ea96591dd2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520564253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3520564253
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.667947313
Short name T872
Test name
Test status
Simulation time 16488219 ps
CPU time 1.2 seconds
Started Jul 20 05:00:46 PM PDT 24
Finished Jul 20 05:00:48 PM PDT 24
Peak memory 218024 kb
Host smart-c8133e75-d863-4220-a6bf-bb14c31d2e14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667947313 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.667947313
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.854778840
Short name T909
Test name
Test status
Simulation time 14150204 ps
CPU time 0.92 seconds
Started Jul 20 05:00:48 PM PDT 24
Finished Jul 20 05:00:52 PM PDT 24
Peak memory 209380 kb
Host smart-e9d7e26f-753a-4515-b60c-efb4ac63c475
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854778840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.854778840
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3962191224
Short name T861
Test name
Test status
Simulation time 30105975 ps
CPU time 1.08 seconds
Started Jul 20 05:00:38 PM PDT 24
Finished Jul 20 05:00:40 PM PDT 24
Peak memory 209660 kb
Host smart-643c5f6b-5792-4508-a44e-fba67cc3d96d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962191224 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3962191224
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3837483438
Short name T867
Test name
Test status
Simulation time 878546920 ps
CPU time 9.61 seconds
Started Jul 20 05:00:38 PM PDT 24
Finished Jul 20 05:00:48 PM PDT 24
Peak memory 208908 kb
Host smart-a3bf7ac4-9665-415f-ab6c-d4a5a2090a66
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837483438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3837483438
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2923839935
Short name T879
Test name
Test status
Simulation time 491532107 ps
CPU time 12.29 seconds
Started Jul 20 05:00:36 PM PDT 24
Finished Jul 20 05:00:49 PM PDT 24
Peak memory 209476 kb
Host smart-2165f97d-c729-4ed6-b076-289169acf272
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923839935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2923839935
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3191855570
Short name T854
Test name
Test status
Simulation time 202811355 ps
CPU time 5.31 seconds
Started Jul 20 05:00:38 PM PDT 24
Finished Jul 20 05:00:44 PM PDT 24
Peak memory 211328 kb
Host smart-2c1b1c0a-2fe8-4cdb-a853-a3413c3d6ecb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191855570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3191855570
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1843018939
Short name T918
Test name
Test status
Simulation time 65986179 ps
CPU time 1.94 seconds
Started Jul 20 05:00:39 PM PDT 24
Finished Jul 20 05:00:42 PM PDT 24
Peak memory 218628 kb
Host smart-e160d1e5-2150-4b98-9766-d8e9c99d9338
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184301
8939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1843018939
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3563136690
Short name T890
Test name
Test status
Simulation time 159383090 ps
CPU time 1.42 seconds
Started Jul 20 05:00:39 PM PDT 24
Finished Jul 20 05:00:41 PM PDT 24
Peak memory 209608 kb
Host smart-1839e244-5348-4c05-a76b-63b591d4ae37
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563136690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3563136690
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2045541743
Short name T971
Test name
Test status
Simulation time 24877002 ps
CPU time 1.38 seconds
Started Jul 20 05:00:35 PM PDT 24
Finished Jul 20 05:00:37 PM PDT 24
Peak memory 209580 kb
Host smart-e39c0400-964e-45fe-85cf-cd16e7e26d20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045541743 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2045541743
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1916898406
Short name T202
Test name
Test status
Simulation time 16886153 ps
CPU time 1.01 seconds
Started Jul 20 05:00:48 PM PDT 24
Finished Jul 20 05:00:52 PM PDT 24
Peak memory 209656 kb
Host smart-1db23fa3-d502-406a-b257-2470efc3aa4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916898406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.1916898406
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2794835281
Short name T885
Test name
Test status
Simulation time 26760177 ps
CPU time 2.06 seconds
Started Jul 20 05:00:36 PM PDT 24
Finished Jul 20 05:00:38 PM PDT 24
Peak memory 218016 kb
Host smart-9e96415b-5e23-43e4-ab64-2f06d164f828
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794835281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2794835281
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.59819538
Short name T136
Test name
Test status
Simulation time 220917656 ps
CPU time 2.83 seconds
Started Jul 20 05:00:46 PM PDT 24
Finished Jul 20 05:00:51 PM PDT 24
Peak memory 222620 kb
Host smart-b947ed0b-d8f9-4c95-8f72-792bf2b83297
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59819538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_er
r.59819538
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.109120792
Short name T542
Test name
Test status
Simulation time 38032109 ps
CPU time 0.85 seconds
Started Jul 20 04:36:41 PM PDT 24
Finished Jul 20 04:36:44 PM PDT 24
Peak memory 208164 kb
Host smart-cb465860-685a-4043-b112-bd1f52ec08ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109120792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.109120792
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2451289765
Short name T425
Test name
Test status
Simulation time 19990004 ps
CPU time 0.89 seconds
Started Jul 20 04:36:39 PM PDT 24
Finished Jul 20 04:36:41 PM PDT 24
Peak memory 208388 kb
Host smart-ba89df5b-bd46-46f3-9fb2-5993077c914f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451289765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2451289765
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.674398833
Short name T219
Test name
Test status
Simulation time 489467506 ps
CPU time 11.83 seconds
Started Jul 20 04:36:46 PM PDT 24
Finished Jul 20 04:36:59 PM PDT 24
Peak memory 217664 kb
Host smart-c53dc211-16ac-4671-9030-cd59e0476c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674398833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.674398833
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3198484162
Short name T602
Test name
Test status
Simulation time 317431780 ps
CPU time 2.36 seconds
Started Jul 20 04:36:39 PM PDT 24
Finished Jul 20 04:36:43 PM PDT 24
Peak memory 216632 kb
Host smart-36b4e305-d1d2-4735-8d62-35761fa6592e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198484162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3198484162
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.4151683505
Short name T238
Test name
Test status
Simulation time 1341149735 ps
CPU time 33.78 seconds
Started Jul 20 04:36:37 PM PDT 24
Finished Jul 20 04:37:12 PM PDT 24
Peak memory 225416 kb
Host smart-b34a5ef4-dfe0-4eeb-9221-6d3a3cf6b2d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151683505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.4151683505
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1548788550
Short name T288
Test name
Test status
Simulation time 1026623492 ps
CPU time 11.75 seconds
Started Jul 20 04:36:42 PM PDT 24
Finished Jul 20 04:36:56 PM PDT 24
Peak memory 217104 kb
Host smart-fc916a5a-5b27-4dea-bf6b-1d632cbff718
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548788550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
548788550
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2892444734
Short name T89
Test name
Test status
Simulation time 2536810538 ps
CPU time 8.91 seconds
Started Jul 20 04:36:46 PM PDT 24
Finished Jul 20 04:36:56 PM PDT 24
Peak memory 223088 kb
Host smart-b79876c8-c16a-4279-8fad-0e10f723db15
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892444734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2892444734
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.127419587
Short name T74
Test name
Test status
Simulation time 1589266584 ps
CPU time 12.97 seconds
Started Jul 20 04:36:38 PM PDT 24
Finished Jul 20 04:36:53 PM PDT 24
Peak memory 217080 kb
Host smart-017dceb7-2a9f-4f6d-ad5f-5c792439a7e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127419587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.127419587
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2686104677
Short name T42
Test name
Test status
Simulation time 1692304739 ps
CPU time 11.93 seconds
Started Jul 20 04:36:41 PM PDT 24
Finished Jul 20 04:36:54 PM PDT 24
Peak memory 216968 kb
Host smart-728c13e6-2d23-4355-90b8-0bf31d2187b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686104677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2686104677
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.281041004
Short name T774
Test name
Test status
Simulation time 2066183795 ps
CPU time 48.25 seconds
Started Jul 20 04:36:39 PM PDT 24
Finished Jul 20 04:37:29 PM PDT 24
Peak memory 278168 kb
Host smart-ae777112-9aa1-4acf-a13e-ef32235b024c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281041004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_state_failure.281041004
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.605722630
Short name T289
Test name
Test status
Simulation time 519795577 ps
CPU time 14.7 seconds
Started Jul 20 04:36:45 PM PDT 24
Finished Jul 20 04:37:01 PM PDT 24
Peak memory 250304 kb
Host smart-21102fd8-7460-4aee-8f17-9e453e4af604
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605722630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.605722630
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.979305557
Short name T670
Test name
Test status
Simulation time 313511661 ps
CPU time 4.15 seconds
Started Jul 20 04:36:42 PM PDT 24
Finished Jul 20 04:36:48 PM PDT 24
Peak memory 217676 kb
Host smart-6fa66106-54da-4e4a-b285-42a73ffd1f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979305557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.979305557
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1107143413
Short name T635
Test name
Test status
Simulation time 322472066 ps
CPU time 21.49 seconds
Started Jul 20 04:36:37 PM PDT 24
Finished Jul 20 04:37:00 PM PDT 24
Peak memory 214168 kb
Host smart-52193c92-6ade-4a4c-9122-ad389b4d46fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107143413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1107143413
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2985389399
Short name T100
Test name
Test status
Simulation time 914754168 ps
CPU time 36.2 seconds
Started Jul 20 04:36:36 PM PDT 24
Finished Jul 20 04:37:13 PM PDT 24
Peak memory 268868 kb
Host smart-f4f3df2d-6ae4-435d-9f1c-3865db0cfa6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985389399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2985389399
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1173499748
Short name T555
Test name
Test status
Simulation time 384556028 ps
CPU time 10.77 seconds
Started Jul 20 04:36:41 PM PDT 24
Finished Jul 20 04:36:54 PM PDT 24
Peak memory 217908 kb
Host smart-d25bc547-d523-49f9-8823-d9e709c09dd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173499748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1173499748
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2763084998
Short name T281
Test name
Test status
Simulation time 1632752143 ps
CPU time 9.69 seconds
Started Jul 20 04:36:40 PM PDT 24
Finished Jul 20 04:36:51 PM PDT 24
Peak memory 225440 kb
Host smart-6b1b586d-f0c3-41ca-b90d-85b944484d79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763084998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
763084998
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2251222145
Short name T681
Test name
Test status
Simulation time 223792923 ps
CPU time 2.87 seconds
Started Jul 20 04:36:38 PM PDT 24
Finished Jul 20 04:36:42 PM PDT 24
Peak memory 217036 kb
Host smart-6bb5cb79-6ee7-43c4-a7bd-8faac0d32924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251222145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2251222145
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2691282371
Short name T596
Test name
Test status
Simulation time 2102907137 ps
CPU time 27.26 seconds
Started Jul 20 04:36:36 PM PDT 24
Finished Jul 20 04:37:04 PM PDT 24
Peak memory 250400 kb
Host smart-0901cf05-0404-422e-9995-9a82f15bf925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691282371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2691282371
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.678556634
Short name T350
Test name
Test status
Simulation time 27140896 ps
CPU time 0.71 seconds
Started Jul 20 04:36:37 PM PDT 24
Finished Jul 20 04:36:40 PM PDT 24
Peak memory 206488 kb
Host smart-353c5c8d-acdd-4bbd-837b-0b30526a2b3b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678556634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.678556634
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1834388142
Short name T535
Test name
Test status
Simulation time 109793573 ps
CPU time 1.17 seconds
Started Jul 20 04:36:51 PM PDT 24
Finished Jul 20 04:36:53 PM PDT 24
Peak memory 208364 kb
Host smart-7c480732-e6d5-4be5-980a-2c9b8ef0d1ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834388142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1834388142
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2641410479
Short name T846
Test name
Test status
Simulation time 1302932278 ps
CPU time 15.94 seconds
Started Jul 20 04:36:36 PM PDT 24
Finished Jul 20 04:36:53 PM PDT 24
Peak memory 217764 kb
Host smart-ed9e06e6-b9ca-4e12-bae9-4b70b7ad4bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641410479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2641410479
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1490616069
Short name T29
Test name
Test status
Simulation time 692652221 ps
CPU time 2.76 seconds
Started Jul 20 04:36:49 PM PDT 24
Finished Jul 20 04:36:53 PM PDT 24
Peak memory 216500 kb
Host smart-348f07ff-5e1b-42a4-b4b3-f3cc00ad00df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490616069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1490616069
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1530455907
Short name T413
Test name
Test status
Simulation time 21263007481 ps
CPU time 40.49 seconds
Started Jul 20 04:36:45 PM PDT 24
Finished Jul 20 04:37:26 PM PDT 24
Peak memory 218320 kb
Host smart-3daef301-5ceb-4efe-b5a6-8ebe584a6e8f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530455907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1530455907
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2799038302
Short name T179
Test name
Test status
Simulation time 81835885 ps
CPU time 1.72 seconds
Started Jul 20 04:36:47 PM PDT 24
Finished Jul 20 04:36:50 PM PDT 24
Peak memory 217144 kb
Host smart-f0014408-ea46-4d60-8eb8-43e8cafc430d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799038302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
799038302
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.599642777
Short name T736
Test name
Test status
Simulation time 998409507 ps
CPU time 15 seconds
Started Jul 20 04:36:44 PM PDT 24
Finished Jul 20 04:37:00 PM PDT 24
Peak memory 217584 kb
Host smart-3f5f5d47-0108-4c88-a121-3f4449362499
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599642777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.599642777
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1929611178
Short name T101
Test name
Test status
Simulation time 1454778186 ps
CPU time 14.23 seconds
Started Jul 20 04:36:47 PM PDT 24
Finished Jul 20 04:37:02 PM PDT 24
Peak memory 217004 kb
Host smart-74971b37-5b67-46a0-b881-c478054fdfb2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929611178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1929611178
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3889288351
Short name T392
Test name
Test status
Simulation time 244103407 ps
CPU time 3.99 seconds
Started Jul 20 04:36:50 PM PDT 24
Finished Jul 20 04:36:55 PM PDT 24
Peak memory 217052 kb
Host smart-cedcf28b-9298-492b-8fbe-6aa746504d24
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889288351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3889288351
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3949782433
Short name T250
Test name
Test status
Simulation time 1223045779 ps
CPU time 54.61 seconds
Started Jul 20 04:36:45 PM PDT 24
Finished Jul 20 04:37:41 PM PDT 24
Peak memory 274948 kb
Host smart-70d005e1-4f67-4afd-85ce-98f6120d9ee6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949782433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3949782433
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1793964412
Short name T222
Test name
Test status
Simulation time 355051693 ps
CPU time 11.55 seconds
Started Jul 20 04:36:43 PM PDT 24
Finished Jul 20 04:36:56 PM PDT 24
Peak memory 222496 kb
Host smart-6f3f8e9d-6244-4363-af12-1bd76de22b62
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793964412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1793964412
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.491996009
Short name T722
Test name
Test status
Simulation time 126089582 ps
CPU time 5.2 seconds
Started Jul 20 04:36:45 PM PDT 24
Finished Jul 20 04:36:51 PM PDT 24
Peak memory 217652 kb
Host smart-72ba053b-d513-4859-9d48-07133e0417e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491996009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.491996009
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.441925024
Short name T86
Test name
Test status
Simulation time 170097434 ps
CPU time 9.41 seconds
Started Jul 20 04:36:45 PM PDT 24
Finished Jul 20 04:36:55 PM PDT 24
Peak memory 217120 kb
Host smart-486888a3-0092-4ef0-bf3f-26296f392567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441925024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.441925024
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2759624978
Short name T84
Test name
Test status
Simulation time 1241095575 ps
CPU time 27.83 seconds
Started Jul 20 04:36:46 PM PDT 24
Finished Jul 20 04:37:14 PM PDT 24
Peak memory 281636 kb
Host smart-a2dda1ee-0731-4d3b-8710-c2c43bed04ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759624978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2759624978
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3839156773
Short name T449
Test name
Test status
Simulation time 1055443690 ps
CPU time 13.84 seconds
Started Jul 20 04:36:46 PM PDT 24
Finished Jul 20 04:37:01 PM PDT 24
Peak memory 225492 kb
Host smart-5e18905f-8709-47df-967f-068e91c58955
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839156773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3839156773
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2556206323
Short name T419
Test name
Test status
Simulation time 368774627 ps
CPU time 15.35 seconds
Started Jul 20 04:36:48 PM PDT 24
Finished Jul 20 04:37:04 PM PDT 24
Peak memory 217676 kb
Host smart-bccfb7cc-ce20-4574-bb20-059c4b5ebfa6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556206323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2556206323
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.624575349
Short name T688
Test name
Test status
Simulation time 258975582 ps
CPU time 7.42 seconds
Started Jul 20 04:36:46 PM PDT 24
Finished Jul 20 04:36:55 PM PDT 24
Peak memory 225404 kb
Host smart-0e935f03-08a7-4340-b129-2d6b792d6ab3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624575349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.624575349
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3325002949
Short name T744
Test name
Test status
Simulation time 393290134 ps
CPU time 6.84 seconds
Started Jul 20 04:36:49 PM PDT 24
Finished Jul 20 04:36:57 PM PDT 24
Peak memory 224692 kb
Host smart-97a890c3-d36e-498d-8ef5-49c31dea7998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325002949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3325002949
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1660626535
Short name T665
Test name
Test status
Simulation time 100201362 ps
CPU time 1.18 seconds
Started Jul 20 04:36:42 PM PDT 24
Finished Jul 20 04:36:45 PM PDT 24
Peak memory 217092 kb
Host smart-168bfee8-9f16-434b-9228-9d805c160b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660626535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1660626535
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2485663131
Short name T232
Test name
Test status
Simulation time 1691538631 ps
CPU time 27.1 seconds
Started Jul 20 04:36:42 PM PDT 24
Finished Jul 20 04:37:11 PM PDT 24
Peak memory 250384 kb
Host smart-9397b643-b8ec-4c0b-9421-bf16bf89cbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485663131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2485663131
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.93500833
Short name T723
Test name
Test status
Simulation time 90958550 ps
CPU time 8.62 seconds
Started Jul 20 04:36:38 PM PDT 24
Finished Jul 20 04:36:48 PM PDT 24
Peak memory 250336 kb
Host smart-9fbe04b6-4577-4699-825e-75f3e2556963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93500833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.93500833
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2513551034
Short name T162
Test name
Test status
Simulation time 26978215918 ps
CPU time 236.22 seconds
Started Jul 20 04:36:46 PM PDT 24
Finished Jul 20 04:40:43 PM PDT 24
Peak memory 275024 kb
Host smart-282e9633-c49a-4291-a272-480d1521d545
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513551034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2513551034
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.133456122
Short name T97
Test name
Test status
Simulation time 5749839269 ps
CPU time 226.38 seconds
Started Jul 20 04:36:53 PM PDT 24
Finished Jul 20 04:40:40 PM PDT 24
Peak memory 283336 kb
Host smart-a16ec6d8-ad05-4cc7-9af1-0099178d8a5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=133456122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.133456122
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3799151262
Short name T157
Test name
Test status
Simulation time 41260019 ps
CPU time 0.76 seconds
Started Jul 20 04:36:41 PM PDT 24
Finished Jul 20 04:36:44 PM PDT 24
Peak memory 208240 kb
Host smart-3ffb6429-b32f-4606-9963-8284b559bd03
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799151262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3799151262
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1555424189
Short name T519
Test name
Test status
Simulation time 1335530132 ps
CPU time 15.06 seconds
Started Jul 20 04:37:24 PM PDT 24
Finished Jul 20 04:37:42 PM PDT 24
Peak memory 217404 kb
Host smart-ed0640a6-c281-46df-a2a2-1a53a102fb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555424189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1555424189
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.578124483
Short name T10
Test name
Test status
Simulation time 392512032 ps
CPU time 5.34 seconds
Started Jul 20 04:37:24 PM PDT 24
Finished Jul 20 04:37:32 PM PDT 24
Peak memory 216672 kb
Host smart-0bf47c59-d189-49cd-93a0-b16537717dc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578124483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.578124483
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1978371230
Short name T799
Test name
Test status
Simulation time 4545877138 ps
CPU time 34.19 seconds
Started Jul 20 04:37:24 PM PDT 24
Finished Jul 20 04:38:00 PM PDT 24
Peak memory 218204 kb
Host smart-23efa835-f930-4106-ab54-41c0b081e5e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978371230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1978371230
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.733824057
Short name T340
Test name
Test status
Simulation time 228924099 ps
CPU time 5.08 seconds
Started Jul 20 04:37:22 PM PDT 24
Finished Jul 20 04:37:28 PM PDT 24
Peak memory 217544 kb
Host smart-ac99a2e1-f9c8-4289-ba22-16ee4f88ea4a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733824057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_prog_failure.733824057
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.822048113
Short name T608
Test name
Test status
Simulation time 794122192 ps
CPU time 9.23 seconds
Started Jul 20 04:37:22 PM PDT 24
Finished Jul 20 04:37:33 PM PDT 24
Peak memory 217044 kb
Host smart-c1516dcb-39ea-463f-a349-d3b47b347b8a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822048113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.
822048113
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1161578302
Short name T443
Test name
Test status
Simulation time 8411314481 ps
CPU time 45.42 seconds
Started Jul 20 04:37:23 PM PDT 24
Finished Jul 20 04:38:10 PM PDT 24
Peak memory 276152 kb
Host smart-37a01c77-f415-46cd-9fd6-c76a79a88482
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161578302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1161578302
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3074099863
Short name T737
Test name
Test status
Simulation time 485944611 ps
CPU time 11.83 seconds
Started Jul 20 04:37:21 PM PDT 24
Finished Jul 20 04:37:34 PM PDT 24
Peak memory 245812 kb
Host smart-e9075b6e-654f-48cd-802f-4c56c2a888be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074099863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3074099863
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.1861670439
Short name T456
Test name
Test status
Simulation time 144130390 ps
CPU time 2.2 seconds
Started Jul 20 04:37:26 PM PDT 24
Finished Jul 20 04:37:30 PM PDT 24
Peak memory 217708 kb
Host smart-1002632f-9eb6-41b1-a8be-e4f39a1f4bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861670439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1861670439
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.996778714
Short name T441
Test name
Test status
Simulation time 390760662 ps
CPU time 9.32 seconds
Started Jul 20 04:37:29 PM PDT 24
Finished Jul 20 04:37:39 PM PDT 24
Peak memory 218404 kb
Host smart-2d1c3864-145f-46a3-b886-964854e65a48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996778714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.996778714
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.795855951
Short name T389
Test name
Test status
Simulation time 294545763 ps
CPU time 9.99 seconds
Started Jul 20 04:37:26 PM PDT 24
Finished Jul 20 04:37:37 PM PDT 24
Peak memory 217616 kb
Host smart-f02741f6-0493-44df-b7b5-30128ac4bfeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795855951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.795855951
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2429925286
Short name T621
Test name
Test status
Simulation time 2491306036 ps
CPU time 18.81 seconds
Started Jul 20 04:37:24 PM PDT 24
Finished Jul 20 04:37:45 PM PDT 24
Peak memory 225488 kb
Host smart-0620fd38-ca88-4df8-8c2b-4dc88581f7aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429925286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2429925286
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1569469412
Short name T634
Test name
Test status
Simulation time 2014353530 ps
CPU time 10.91 seconds
Started Jul 20 04:37:24 PM PDT 24
Finished Jul 20 04:37:37 PM PDT 24
Peak memory 217692 kb
Host smart-311feece-c3f2-4248-8fe4-a549d6f259aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569469412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1569469412
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1543054037
Short name T81
Test name
Test status
Simulation time 78073842 ps
CPU time 1.35 seconds
Started Jul 20 04:37:29 PM PDT 24
Finished Jul 20 04:37:32 PM PDT 24
Peak memory 213168 kb
Host smart-5c20c717-f720-44b4-ae72-93c816725630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543054037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1543054037
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.293420992
Short name T743
Test name
Test status
Simulation time 4313610196 ps
CPU time 32.85 seconds
Started Jul 20 04:37:24 PM PDT 24
Finished Jul 20 04:38:00 PM PDT 24
Peak memory 250480 kb
Host smart-110d2adb-b05f-4744-bad1-88798f59bf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293420992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.293420992
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.935185996
Short name T575
Test name
Test status
Simulation time 75281062 ps
CPU time 4.04 seconds
Started Jul 20 04:37:22 PM PDT 24
Finished Jul 20 04:37:28 PM PDT 24
Peak memory 222280 kb
Host smart-b8616497-916b-426d-93e7-c4eb62059e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935185996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.935185996
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1482481027
Short name T438
Test name
Test status
Simulation time 12453425777 ps
CPU time 68.57 seconds
Started Jul 20 04:37:24 PM PDT 24
Finished Jul 20 04:38:35 PM PDT 24
Peak memory 275084 kb
Host smart-be79a795-a3c7-4d70-9936-bde7a77bc10b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482481027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1482481027
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.858260752
Short name T408
Test name
Test status
Simulation time 17198112 ps
CPU time 1.07 seconds
Started Jul 20 04:37:21 PM PDT 24
Finished Jul 20 04:37:22 PM PDT 24
Peak memory 211412 kb
Host smart-d99adc42-f1dd-43ea-ac46-903912cb1a84
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858260752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.858260752
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.894940537
Short name T822
Test name
Test status
Simulation time 109117171 ps
CPU time 1.48 seconds
Started Jul 20 04:37:32 PM PDT 24
Finished Jul 20 04:37:35 PM PDT 24
Peak memory 208468 kb
Host smart-3225e342-eaa0-4af9-8d05-ccddae024397
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894940537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.894940537
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.36408005
Short name T754
Test name
Test status
Simulation time 990382688 ps
CPU time 10.27 seconds
Started Jul 20 04:37:26 PM PDT 24
Finished Jul 20 04:37:38 PM PDT 24
Peak memory 218012 kb
Host smart-6f4e9f98-2b48-4c53-a6c3-4e97b437836e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36408005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.36408005
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.481776507
Short name T8
Test name
Test status
Simulation time 66892802 ps
CPU time 1.64 seconds
Started Jul 20 04:37:30 PM PDT 24
Finished Jul 20 04:37:33 PM PDT 24
Peak memory 216496 kb
Host smart-58df2cee-f29e-450a-9876-eb1edd148144
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481776507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.481776507
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2604564659
Short name T371
Test name
Test status
Simulation time 354610490 ps
CPU time 7.68 seconds
Started Jul 20 04:37:32 PM PDT 24
Finished Jul 20 04:37:42 PM PDT 24
Peak memory 222612 kb
Host smart-f6de3435-90c7-49bf-99ea-984639d01e5c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604564659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2604564659
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.879529002
Short name T524
Test name
Test status
Simulation time 702725289 ps
CPU time 9.98 seconds
Started Jul 20 04:37:20 PM PDT 24
Finished Jul 20 04:37:31 PM PDT 24
Peak memory 217284 kb
Host smart-aba9835b-77e6-44b5-b0db-9d400635e05d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879529002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
879529002
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2392392366
Short name T841
Test name
Test status
Simulation time 2903245417 ps
CPU time 38.52 seconds
Started Jul 20 04:37:26 PM PDT 24
Finished Jul 20 04:38:06 PM PDT 24
Peak memory 275256 kb
Host smart-1462cf80-d2a7-466f-bb45-f575360e59aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392392366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2392392366
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3483809583
Short name T782
Test name
Test status
Simulation time 753497174 ps
CPU time 16.08 seconds
Started Jul 20 04:37:28 PM PDT 24
Finished Jul 20 04:37:45 PM PDT 24
Peak memory 250368 kb
Host smart-5752e8fa-75b3-4b41-b985-196079dae893
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483809583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3483809583
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3330882111
Short name T796
Test name
Test status
Simulation time 507810535 ps
CPU time 2.74 seconds
Started Jul 20 04:37:22 PM PDT 24
Finished Jul 20 04:37:26 PM PDT 24
Peak memory 221828 kb
Host smart-8fa50dd2-a97d-418e-a800-378824d990bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330882111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3330882111
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.980496600
Short name T434
Test name
Test status
Simulation time 1336772053 ps
CPU time 12.23 seconds
Started Jul 20 04:37:33 PM PDT 24
Finished Jul 20 04:37:47 PM PDT 24
Peak memory 225488 kb
Host smart-60b86311-10a7-4783-b422-8bd134d5d75d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980496600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.980496600
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.590820258
Short name T305
Test name
Test status
Simulation time 1781889500 ps
CPU time 11.6 seconds
Started Jul 20 04:37:34 PM PDT 24
Finished Jul 20 04:37:47 PM PDT 24
Peak memory 217728 kb
Host smart-0e67cdf0-5e3d-4fe2-bb85-9a3e4d217c2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590820258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_di
gest.590820258
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3095042151
Short name T65
Test name
Test status
Simulation time 581736410 ps
CPU time 11.94 seconds
Started Jul 20 04:37:30 PM PDT 24
Finished Jul 20 04:37:43 PM PDT 24
Peak memory 225388 kb
Host smart-57021cf9-1379-4710-bf76-27647c8b7a6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095042151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3095042151
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.4292128441
Short name T545
Test name
Test status
Simulation time 25724499 ps
CPU time 1.24 seconds
Started Jul 20 04:37:22 PM PDT 24
Finished Jul 20 04:37:25 PM PDT 24
Peak memory 213084 kb
Host smart-71709764-24ff-4e83-91cd-adb870f3a3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292128441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.4292128441
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1124741925
Short name T556
Test name
Test status
Simulation time 336245405 ps
CPU time 22.59 seconds
Started Jul 20 04:37:23 PM PDT 24
Finished Jul 20 04:37:47 PM PDT 24
Peak memory 250364 kb
Host smart-7bb2c3e8-66b9-434b-ba95-7769a01ba3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124741925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1124741925
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2415566134
Short name T601
Test name
Test status
Simulation time 368958889 ps
CPU time 6.86 seconds
Started Jul 20 04:37:24 PM PDT 24
Finished Jul 20 04:37:34 PM PDT 24
Peak memory 250036 kb
Host smart-07ee7090-a062-4d8c-8b6a-1057b26b19be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415566134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2415566134
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2097801186
Short name T562
Test name
Test status
Simulation time 4276284304 ps
CPU time 46.57 seconds
Started Jul 20 04:37:33 PM PDT 24
Finished Jul 20 04:38:21 PM PDT 24
Peak memory 246604 kb
Host smart-407eb0f1-8a62-4a57-874a-27eaaf89053e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097801186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2097801186
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.158982271
Short name T228
Test name
Test status
Simulation time 15417624 ps
CPU time 0.81 seconds
Started Jul 20 04:37:24 PM PDT 24
Finished Jul 20 04:37:28 PM PDT 24
Peak memory 208012 kb
Host smart-18eea23b-f1da-4ba6-b131-5c4d043f2c26
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158982271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_volatile_unlock_smoke.158982271
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.2808097976
Short name T526
Test name
Test status
Simulation time 22146266 ps
CPU time 1.17 seconds
Started Jul 20 04:37:30 PM PDT 24
Finished Jul 20 04:37:33 PM PDT 24
Peak memory 208372 kb
Host smart-4299c8e6-5ae1-4995-9ec7-052ad681a858
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808097976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2808097976
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2388532794
Short name T32
Test name
Test status
Simulation time 277327973 ps
CPU time 9.45 seconds
Started Jul 20 04:37:30 PM PDT 24
Finished Jul 20 04:37:41 PM PDT 24
Peak memory 217776 kb
Host smart-c011beaa-e2eb-4add-9471-666d089c893a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388532794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2388532794
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.4276951758
Short name T185
Test name
Test status
Simulation time 1048247272 ps
CPU time 8.74 seconds
Started Jul 20 04:37:34 PM PDT 24
Finished Jul 20 04:37:45 PM PDT 24
Peak memory 216808 kb
Host smart-b73ad938-bb14-4f0d-9ed8-ea6c7cf400cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276951758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.4276951758
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3957412792
Short name T304
Test name
Test status
Simulation time 4124410600 ps
CPU time 63.96 seconds
Started Jul 20 04:37:33 PM PDT 24
Finished Jul 20 04:38:39 PM PDT 24
Peak memory 225480 kb
Host smart-09a6568e-0032-4b59-8944-1cf899d71752
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957412792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3957412792
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.789011995
Short name T7
Test name
Test status
Simulation time 569710559 ps
CPU time 15.1 seconds
Started Jul 20 04:37:32 PM PDT 24
Finished Jul 20 04:37:49 PM PDT 24
Peak memory 223892 kb
Host smart-41925306-9afe-41de-9774-9fc929138b53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789011995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.789011995
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2853446805
Short name T216
Test name
Test status
Simulation time 844284021 ps
CPU time 4.65 seconds
Started Jul 20 04:37:32 PM PDT 24
Finished Jul 20 04:37:39 PM PDT 24
Peak memory 216976 kb
Host smart-2228ac75-81ef-43fa-9344-681194e121ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853446805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2853446805
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3878542253
Short name T451
Test name
Test status
Simulation time 10558287670 ps
CPU time 39.23 seconds
Started Jul 20 04:37:32 PM PDT 24
Finished Jul 20 04:38:13 PM PDT 24
Peak memory 275076 kb
Host smart-a9ab7033-8ec0-4c42-b333-e0a93c9ad58b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878542253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3878542253
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1953080840
Short name T740
Test name
Test status
Simulation time 459212915 ps
CPU time 18.25 seconds
Started Jul 20 04:37:32 PM PDT 24
Finished Jul 20 04:37:52 PM PDT 24
Peak memory 245816 kb
Host smart-ec2b0e5a-aafb-4694-b48a-ec0ad0ca5734
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953080840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1953080840
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3658470058
Short name T481
Test name
Test status
Simulation time 53751915 ps
CPU time 2.1 seconds
Started Jul 20 04:37:33 PM PDT 24
Finished Jul 20 04:37:37 PM PDT 24
Peak memory 221432 kb
Host smart-96a71c4c-2d52-42f5-9a97-a19fd54c350f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658470058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3658470058
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1532500010
Short name T334
Test name
Test status
Simulation time 264760836 ps
CPU time 9.37 seconds
Started Jul 20 04:37:31 PM PDT 24
Finished Jul 20 04:37:42 PM PDT 24
Peak memory 217680 kb
Host smart-daea1fdb-9836-448b-8731-2d7243fbbc1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532500010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1532500010
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.4117456683
Short name T426
Test name
Test status
Simulation time 744816305 ps
CPU time 9.24 seconds
Started Jul 20 04:37:31 PM PDT 24
Finished Jul 20 04:37:41 PM PDT 24
Peak memory 225424 kb
Host smart-005a94bd-2c49-4b4c-9593-832f108d6a15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117456683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
4117456683
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2494101330
Short name T212
Test name
Test status
Simulation time 957038035 ps
CPU time 7.22 seconds
Started Jul 20 04:37:33 PM PDT 24
Finished Jul 20 04:37:42 PM PDT 24
Peak memory 217756 kb
Host smart-c84f48e6-ae9d-49e0-9d0a-b6e93b9f2814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494101330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2494101330
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3194311374
Short name T328
Test name
Test status
Simulation time 100922140 ps
CPU time 2.37 seconds
Started Jul 20 04:37:32 PM PDT 24
Finished Jul 20 04:37:36 PM PDT 24
Peak memory 213788 kb
Host smart-923faa5e-af54-40a9-983a-5b009de5e6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194311374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3194311374
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.3234424484
Short name T672
Test name
Test status
Simulation time 1050483070 ps
CPU time 28.02 seconds
Started Jul 20 04:37:33 PM PDT 24
Finished Jul 20 04:38:02 PM PDT 24
Peak memory 250484 kb
Host smart-76ba7015-96fd-4814-9572-026542f81d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234424484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3234424484
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1601636882
Short name T291
Test name
Test status
Simulation time 75894924 ps
CPU time 9.71 seconds
Started Jul 20 04:37:34 PM PDT 24
Finished Jul 20 04:37:45 PM PDT 24
Peak memory 250420 kb
Host smart-c41283f1-3dfe-4eb3-86c1-0f1a48195f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601636882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1601636882
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.50824808
Short name T702
Test name
Test status
Simulation time 51754327 ps
CPU time 0.87 seconds
Started Jul 20 04:37:34 PM PDT 24
Finished Jul 20 04:37:36 PM PDT 24
Peak memory 211396 kb
Host smart-d00e744b-0ade-4171-98c2-8022661a0e62
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50824808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_volatile_unlock_smoke.50824808
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3273185504
Short name T96
Test name
Test status
Simulation time 20641856 ps
CPU time 1.05 seconds
Started Jul 20 04:37:39 PM PDT 24
Finished Jul 20 04:37:42 PM PDT 24
Peak memory 208292 kb
Host smart-f13b7da9-0fd6-4ee4-9659-5f163612ce0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273185504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3273185504
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3308842801
Short name T809
Test name
Test status
Simulation time 207206695 ps
CPU time 10.14 seconds
Started Jul 20 04:37:33 PM PDT 24
Finished Jul 20 04:37:45 PM PDT 24
Peak memory 217700 kb
Host smart-3f4c534b-86a4-4322-943b-e65c54aa63ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308842801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3308842801
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2263519485
Short name T825
Test name
Test status
Simulation time 382100423 ps
CPU time 10.58 seconds
Started Jul 20 04:37:37 PM PDT 24
Finished Jul 20 04:37:49 PM PDT 24
Peak memory 216680 kb
Host smart-1bb2c2db-39a3-405b-9f8d-92ef91e5e8a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263519485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2263519485
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.516171347
Short name T680
Test name
Test status
Simulation time 3956382392 ps
CPU time 51.17 seconds
Started Jul 20 04:37:38 PM PDT 24
Finished Jul 20 04:38:30 PM PDT 24
Peak memory 225468 kb
Host smart-b4d2a617-f3bd-4b0f-89b6-a03ff9f2bb2b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516171347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.516171347
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3172558091
Short name T644
Test name
Test status
Simulation time 1704428057 ps
CPU time 13.02 seconds
Started Jul 20 04:37:38 PM PDT 24
Finished Jul 20 04:37:53 PM PDT 24
Peak memory 222688 kb
Host smart-b939e8ff-421f-4bd3-a389-35ad19ba22e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172558091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3172558091
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3742061637
Short name T73
Test name
Test status
Simulation time 1269829050 ps
CPU time 6.41 seconds
Started Jul 20 04:37:33 PM PDT 24
Finished Jul 20 04:37:41 PM PDT 24
Peak memory 217088 kb
Host smart-453a1b9b-5d39-4ab0-bc58-4e1037543a31
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742061637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3742061637
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3177955186
Short name T108
Test name
Test status
Simulation time 3293734331 ps
CPU time 36.29 seconds
Started Jul 20 04:37:38 PM PDT 24
Finished Jul 20 04:38:16 PM PDT 24
Peak memory 275420 kb
Host smart-d3a59a57-0eee-4e4f-ac29-19913efaa3f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177955186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3177955186
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3756249987
Short name T444
Test name
Test status
Simulation time 1521884129 ps
CPU time 22.15 seconds
Started Jul 20 04:37:40 PM PDT 24
Finished Jul 20 04:38:04 PM PDT 24
Peak memory 224888 kb
Host smart-2d316061-07f6-476d-8393-9ac1a2d34b64
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756249987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3756249987
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2315782414
Short name T446
Test name
Test status
Simulation time 365512722 ps
CPU time 3.42 seconds
Started Jul 20 04:37:32 PM PDT 24
Finished Jul 20 04:37:37 PM PDT 24
Peak memory 217648 kb
Host smart-6752badc-255e-4dd5-b8b7-5e1753a4a76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315782414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2315782414
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3867275797
Short name T156
Test name
Test status
Simulation time 1539491128 ps
CPU time 10.46 seconds
Started Jul 20 04:37:38 PM PDT 24
Finished Jul 20 04:37:50 PM PDT 24
Peak memory 218340 kb
Host smart-d5610718-86d3-429d-9b95-6744e44012e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867275797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3867275797
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1469589506
Short name T404
Test name
Test status
Simulation time 845459793 ps
CPU time 16.4 seconds
Started Jul 20 04:37:41 PM PDT 24
Finished Jul 20 04:38:00 PM PDT 24
Peak memory 217708 kb
Host smart-a4864a46-fbdf-47d9-a3ca-de91aaefd931
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469589506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1469589506
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1787225307
Short name T840
Test name
Test status
Simulation time 335958760 ps
CPU time 9.45 seconds
Started Jul 20 04:37:42 PM PDT 24
Finished Jul 20 04:37:53 PM PDT 24
Peak memory 225428 kb
Host smart-ed74e8db-ddcd-4901-8db1-e3a7b5fde9ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787225307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1787225307
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2352508388
Short name T707
Test name
Test status
Simulation time 103228805 ps
CPU time 3.11 seconds
Started Jul 20 04:37:33 PM PDT 24
Finished Jul 20 04:37:38 PM PDT 24
Peak memory 214436 kb
Host smart-400b648e-23e4-43aa-a869-3f12b85bca41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352508388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2352508388
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2757112578
Short name T478
Test name
Test status
Simulation time 894263651 ps
CPU time 19.51 seconds
Started Jul 20 04:37:33 PM PDT 24
Finished Jul 20 04:37:55 PM PDT 24
Peak memory 250484 kb
Host smart-2871599b-d3da-46f6-bf13-ee6585aacd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757112578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2757112578
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2282507099
Short name T242
Test name
Test status
Simulation time 252321076 ps
CPU time 7.19 seconds
Started Jul 20 04:37:31 PM PDT 24
Finished Jul 20 04:37:40 PM PDT 24
Peak memory 250328 kb
Host smart-1163ec05-fd65-4c98-befe-0c945ec24c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282507099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2282507099
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.192852755
Short name T552
Test name
Test status
Simulation time 5277973556 ps
CPU time 57.83 seconds
Started Jul 20 04:37:47 PM PDT 24
Finished Jul 20 04:38:47 PM PDT 24
Peak memory 269840 kb
Host smart-f0313d0b-48d4-41f7-84b5-2368b4595c35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192852755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.192852755
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3033474672
Short name T618
Test name
Test status
Simulation time 22948979 ps
CPU time 0.78 seconds
Started Jul 20 04:37:35 PM PDT 24
Finished Jul 20 04:37:37 PM PDT 24
Peak memory 208452 kb
Host smart-5e3cfa73-c48e-4a73-ba61-4978141e495c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033474672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3033474672
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1082070921
Short name T95
Test name
Test status
Simulation time 58528753 ps
CPU time 1.1 seconds
Started Jul 20 04:37:41 PM PDT 24
Finished Jul 20 04:37:44 PM PDT 24
Peak memory 208384 kb
Host smart-5a15a273-6414-4565-9326-0320c2070f3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082070921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1082070921
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1385139392
Short name T248
Test name
Test status
Simulation time 1229178331 ps
CPU time 10.6 seconds
Started Jul 20 04:37:40 PM PDT 24
Finished Jul 20 04:37:53 PM PDT 24
Peak memory 217744 kb
Host smart-6d876752-424f-4d2e-87dc-9e66d302b07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385139392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1385139392
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2204880942
Short name T383
Test name
Test status
Simulation time 56491085 ps
CPU time 1.36 seconds
Started Jul 20 04:37:46 PM PDT 24
Finished Jul 20 04:37:50 PM PDT 24
Peak memory 216424 kb
Host smart-511b974d-905e-4822-af28-f5e9a366059e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204880942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2204880942
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.4123426838
Short name T843
Test name
Test status
Simulation time 6908797683 ps
CPU time 36.75 seconds
Started Jul 20 04:37:38 PM PDT 24
Finished Jul 20 04:38:16 PM PDT 24
Peak memory 218340 kb
Host smart-be0304ac-0e4c-47b5-8346-5f9ab68edc09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123426838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.4123426838
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1686468695
Short name T848
Test name
Test status
Simulation time 3418740417 ps
CPU time 10.75 seconds
Started Jul 20 04:37:40 PM PDT 24
Finished Jul 20 04:37:53 PM PDT 24
Peak memory 225204 kb
Host smart-ace4c91d-83fc-477f-a97a-9c2594cbca40
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686468695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1686468695
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1281571410
Short name T591
Test name
Test status
Simulation time 214467462 ps
CPU time 3.29 seconds
Started Jul 20 04:37:38 PM PDT 24
Finished Jul 20 04:37:43 PM PDT 24
Peak memory 217060 kb
Host smart-a9c8b958-1398-4ab1-8d8c-7e58adc38f8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281571410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1281571410
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2316143933
Short name T584
Test name
Test status
Simulation time 3815520376 ps
CPU time 89.33 seconds
Started Jul 20 04:37:37 PM PDT 24
Finished Jul 20 04:39:07 PM PDT 24
Peak memory 276932 kb
Host smart-4219dfc7-02b3-4c16-82ee-5e29a35795ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316143933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2316143933
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.4244511995
Short name T385
Test name
Test status
Simulation time 1558905386 ps
CPU time 26.86 seconds
Started Jul 20 04:37:43 PM PDT 24
Finished Jul 20 04:38:11 PM PDT 24
Peak memory 250040 kb
Host smart-89562a2c-4946-4dba-835b-09d145429346
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244511995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.4244511995
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2011224894
Short name T220
Test name
Test status
Simulation time 59489451 ps
CPU time 2.21 seconds
Started Jul 20 04:37:37 PM PDT 24
Finished Jul 20 04:37:40 PM PDT 24
Peak memory 217628 kb
Host smart-73731d08-e5b1-45a6-bc13-ef9c5220e540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011224894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2011224894
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.121109370
Short name T66
Test name
Test status
Simulation time 310247912 ps
CPU time 17.44 seconds
Started Jul 20 04:37:39 PM PDT 24
Finished Jul 20 04:37:59 PM PDT 24
Peak memory 218328 kb
Host smart-b0d1baf3-d46a-4cba-88e5-f8ab1410f8dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121109370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.121109370
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2315835397
Short name T278
Test name
Test status
Simulation time 198537179 ps
CPU time 7.53 seconds
Started Jul 20 04:37:39 PM PDT 24
Finished Jul 20 04:37:49 PM PDT 24
Peak memory 217768 kb
Host smart-1be3fa47-6487-468c-aeeb-a193e715fdcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315835397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2315835397
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3107730290
Short name T336
Test name
Test status
Simulation time 1404614312 ps
CPU time 12.81 seconds
Started Jul 20 04:37:38 PM PDT 24
Finished Jul 20 04:37:51 PM PDT 24
Peak memory 225420 kb
Host smart-bc60f984-171b-485a-b34f-842b95692e45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107730290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3107730290
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3716774341
Short name T423
Test name
Test status
Simulation time 298480032 ps
CPU time 8.28 seconds
Started Jul 20 04:37:39 PM PDT 24
Finished Jul 20 04:37:49 PM PDT 24
Peak memory 217796 kb
Host smart-336a6fc5-d7dd-4e75-aead-a9c8e029c541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716774341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3716774341
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.407327791
Short name T284
Test name
Test status
Simulation time 31024092 ps
CPU time 1.3 seconds
Started Jul 20 04:37:46 PM PDT 24
Finished Jul 20 04:37:49 PM PDT 24
Peak memory 213080 kb
Host smart-87845a4d-a9ed-4095-9664-8962228ef8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407327791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.407327791
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2934483191
Short name T604
Test name
Test status
Simulation time 145539623 ps
CPU time 21.64 seconds
Started Jul 20 04:37:42 PM PDT 24
Finished Jul 20 04:38:05 PM PDT 24
Peak memory 250436 kb
Host smart-12f1f8d4-d8da-4540-ac8a-c76c4a15b5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934483191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2934483191
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.172464447
Short name T374
Test name
Test status
Simulation time 435644252 ps
CPU time 7.91 seconds
Started Jul 20 04:37:43 PM PDT 24
Finished Jul 20 04:37:52 PM PDT 24
Peak memory 250372 kb
Host smart-05011c70-8773-4162-a65c-fba7dd08c8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172464447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.172464447
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2515700893
Short name T587
Test name
Test status
Simulation time 30610871964 ps
CPU time 155.35 seconds
Started Jul 20 04:37:38 PM PDT 24
Finished Jul 20 04:40:15 PM PDT 24
Peak memory 267752 kb
Host smart-108d374a-8ecd-46fc-981c-194f5df2a1b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515700893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2515700893
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3211746927
Short name T67
Test name
Test status
Simulation time 229181024 ps
CPU time 0.91 seconds
Started Jul 20 04:37:42 PM PDT 24
Finished Jul 20 04:37:45 PM PDT 24
Peak memory 211284 kb
Host smart-214da03c-bf29-4f3b-96db-99303fec052f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211746927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3211746927
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2158748937
Short name T728
Test name
Test status
Simulation time 54832197 ps
CPU time 1.27 seconds
Started Jul 20 04:37:41 PM PDT 24
Finished Jul 20 04:37:44 PM PDT 24
Peak memory 208492 kb
Host smart-9a923b55-60fa-463d-9296-f50d4ae9422f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158748937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2158748937
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2716038540
Short name T585
Test name
Test status
Simulation time 287706135 ps
CPU time 11.85 seconds
Started Jul 20 04:37:40 PM PDT 24
Finished Jul 20 04:37:55 PM PDT 24
Peak memory 217676 kb
Host smart-acf28c40-128b-46bb-8c41-90c99e737e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716038540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2716038540
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.491796371
Short name T362
Test name
Test status
Simulation time 1641130929 ps
CPU time 6.71 seconds
Started Jul 20 04:37:45 PM PDT 24
Finished Jul 20 04:37:52 PM PDT 24
Peak memory 216812 kb
Host smart-2ac91a09-d8f9-45fb-8981-8e6cc23d7fa1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491796371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.491796371
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1982445082
Short name T464
Test name
Test status
Simulation time 6440286031 ps
CPU time 95.54 seconds
Started Jul 20 04:37:46 PM PDT 24
Finished Jul 20 04:39:24 PM PDT 24
Peak memory 218328 kb
Host smart-aa3202ea-c6cd-410d-8472-885bdd61bc72
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982445082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1982445082
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.589187463
Short name T24
Test name
Test status
Simulation time 160586537 ps
CPU time 3.49 seconds
Started Jul 20 04:37:41 PM PDT 24
Finished Jul 20 04:37:47 PM PDT 24
Peak memory 221292 kb
Host smart-a53ec2b8-4a27-4cee-9c4a-b714fbc752d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589187463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.589187463
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1195885396
Short name T571
Test name
Test status
Simulation time 811699015 ps
CPU time 3.94 seconds
Started Jul 20 04:37:41 PM PDT 24
Finished Jul 20 04:37:47 PM PDT 24
Peak memory 217044 kb
Host smart-f6ce2acb-4cb9-497e-a08d-381a0efc1d1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195885396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1195885396
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.456724780
Short name T775
Test name
Test status
Simulation time 24816578091 ps
CPU time 99.58 seconds
Started Jul 20 04:37:40 PM PDT 24
Finished Jul 20 04:39:22 PM PDT 24
Peak memory 283164 kb
Host smart-15793b97-a093-4f81-a275-0a84b235c6f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456724780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.456724780
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.403906678
Short name T512
Test name
Test status
Simulation time 422039052 ps
CPU time 12.81 seconds
Started Jul 20 04:37:42 PM PDT 24
Finished Jul 20 04:37:57 PM PDT 24
Peak memory 250392 kb
Host smart-fe56bd8b-9257-4200-8b0e-fca9a6b214e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403906678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.403906678
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.4109313003
Short name T301
Test name
Test status
Simulation time 96645516 ps
CPU time 2 seconds
Started Jul 20 04:37:38 PM PDT 24
Finished Jul 20 04:37:42 PM PDT 24
Peak memory 221436 kb
Host smart-042aa36a-4484-4339-8f62-24e06b32ac7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109313003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.4109313003
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2823767487
Short name T280
Test name
Test status
Simulation time 381793511 ps
CPU time 11.78 seconds
Started Jul 20 04:37:47 PM PDT 24
Finished Jul 20 04:38:01 PM PDT 24
Peak memory 217816 kb
Host smart-828bdefd-2b07-448d-b0dd-360008c37cf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823767487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2823767487
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2148185652
Short name T277
Test name
Test status
Simulation time 667276499 ps
CPU time 18.37 seconds
Started Jul 20 04:37:40 PM PDT 24
Finished Jul 20 04:38:00 PM PDT 24
Peak memory 217688 kb
Host smart-b275a9cb-a377-410a-827d-8f622a1d6a14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148185652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2148185652
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1025876203
Short name T64
Test name
Test status
Simulation time 327172750 ps
CPU time 9.36 seconds
Started Jul 20 04:37:41 PM PDT 24
Finished Jul 20 04:37:53 PM PDT 24
Peak memory 225432 kb
Host smart-032cbea9-0ce4-4be4-a791-7046bc550db5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025876203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1025876203
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2550478394
Short name T568
Test name
Test status
Simulation time 641286319 ps
CPU time 9.98 seconds
Started Jul 20 04:37:40 PM PDT 24
Finished Jul 20 04:37:53 PM PDT 24
Peak memory 225452 kb
Host smart-d1ea9ac2-8408-4821-a4fb-b8309468a5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550478394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2550478394
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2236586053
Short name T561
Test name
Test status
Simulation time 28211685 ps
CPU time 2.05 seconds
Started Jul 20 04:37:42 PM PDT 24
Finished Jul 20 04:37:46 PM PDT 24
Peak memory 217104 kb
Host smart-34d85e4e-39ae-4990-be0c-3ee93bbc8e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236586053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2236586053
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3067770423
Short name T106
Test name
Test status
Simulation time 344425298 ps
CPU time 31.4 seconds
Started Jul 20 04:37:40 PM PDT 24
Finished Jul 20 04:38:14 PM PDT 24
Peak memory 250476 kb
Host smart-ff705ad1-db69-4c0a-9e62-0b1874d0f7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067770423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3067770423
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1620839785
Short name T563
Test name
Test status
Simulation time 223758632 ps
CPU time 10.18 seconds
Started Jul 20 04:37:40 PM PDT 24
Finished Jul 20 04:37:53 PM PDT 24
Peak memory 250480 kb
Host smart-4e1c3386-2f14-4d18-b337-2de853637866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620839785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1620839785
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3176857925
Short name T172
Test name
Test status
Simulation time 3401662127 ps
CPU time 88.47 seconds
Started Jul 20 04:37:38 PM PDT 24
Finished Jul 20 04:39:08 PM PDT 24
Peak memory 283256 kb
Host smart-72e989a7-3e6c-4fa8-af9e-1e82f303ec61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176857925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3176857925
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.1314961508
Short name T98
Test name
Test status
Simulation time 185857928317 ps
CPU time 648.16 seconds
Started Jul 20 04:37:41 PM PDT 24
Finished Jul 20 04:48:31 PM PDT 24
Peak memory 308028 kb
Host smart-9264cb42-334f-492e-9f6f-e647d5f3f097
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1314961508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.1314961508
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.404193815
Short name T713
Test name
Test status
Simulation time 27661526 ps
CPU time 1.11 seconds
Started Jul 20 04:37:44 PM PDT 24
Finished Jul 20 04:37:46 PM PDT 24
Peak memory 211300 kb
Host smart-87b9eb8f-4b3c-4c6f-b00d-3e51e7dffdf6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404193815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.404193815
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2935561413
Short name T693
Test name
Test status
Simulation time 20414144 ps
CPU time 1.09 seconds
Started Jul 20 04:37:49 PM PDT 24
Finished Jul 20 04:37:52 PM PDT 24
Peak memory 208308 kb
Host smart-e9fb98a9-d8e9-4629-8c42-fb857de60c27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935561413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2935561413
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1724000207
Short name T105
Test name
Test status
Simulation time 326390095 ps
CPU time 11.27 seconds
Started Jul 20 04:37:39 PM PDT 24
Finished Jul 20 04:37:52 PM PDT 24
Peak memory 217692 kb
Host smart-f645bec7-b3dd-489e-b361-53a603247b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724000207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1724000207
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3339646401
Short name T479
Test name
Test status
Simulation time 5021955363 ps
CPU time 7.81 seconds
Started Jul 20 04:37:46 PM PDT 24
Finished Jul 20 04:37:55 PM PDT 24
Peak memory 217176 kb
Host smart-2d357292-e329-4907-aec5-2b97d1c9236b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339646401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3339646401
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.4190913861
Short name T749
Test name
Test status
Simulation time 4354940733 ps
CPU time 21.16 seconds
Started Jul 20 04:37:47 PM PDT 24
Finished Jul 20 04:38:10 PM PDT 24
Peak memory 218304 kb
Host smart-a0fe761c-82bc-4388-8269-1ab860d70435
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190913861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.4190913861
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1309719729
Short name T828
Test name
Test status
Simulation time 6445418445 ps
CPU time 14.58 seconds
Started Jul 20 04:37:39 PM PDT 24
Finished Jul 20 04:37:55 PM PDT 24
Peak memory 223420 kb
Host smart-9f48200a-1194-42df-9f44-420078f3bfa8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309719729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1309719729
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2991237415
Short name T487
Test name
Test status
Simulation time 913978520 ps
CPU time 10.52 seconds
Started Jul 20 04:37:39 PM PDT 24
Finished Jul 20 04:37:51 PM PDT 24
Peak memory 217160 kb
Host smart-7d100d89-e091-4e3b-9572-ff7759908440
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991237415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2991237415
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1727709318
Short name T530
Test name
Test status
Simulation time 1696275464 ps
CPU time 46.01 seconds
Started Jul 20 04:37:39 PM PDT 24
Finished Jul 20 04:38:27 PM PDT 24
Peak memory 267584 kb
Host smart-e3fcbc4e-0f0f-49b5-9f04-900d2d1f7e79
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727709318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1727709318
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2497895377
Short name T494
Test name
Test status
Simulation time 438879073 ps
CPU time 10.11 seconds
Started Jul 20 04:37:41 PM PDT 24
Finished Jul 20 04:37:54 PM PDT 24
Peak memory 222524 kb
Host smart-ed9b8326-6751-4e69-9227-b458efbb761c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497895377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.2497895377
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1543783562
Short name T783
Test name
Test status
Simulation time 52298980 ps
CPU time 3.05 seconds
Started Jul 20 04:37:43 PM PDT 24
Finished Jul 20 04:37:47 PM PDT 24
Peak memory 217692 kb
Host smart-0dff7db9-d780-40e4-958a-329760a87cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543783562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1543783562
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3298151825
Short name T805
Test name
Test status
Simulation time 1200689439 ps
CPU time 10.09 seconds
Started Jul 20 04:37:46 PM PDT 24
Finished Jul 20 04:37:58 PM PDT 24
Peak memory 218388 kb
Host smart-f568cb6e-cc65-4cb5-a820-bf9c2f5a38f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298151825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3298151825
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2156867133
Short name T352
Test name
Test status
Simulation time 1158851642 ps
CPU time 10.61 seconds
Started Jul 20 04:37:47 PM PDT 24
Finished Jul 20 04:38:00 PM PDT 24
Peak memory 217748 kb
Host smart-b5f2cc6c-2f67-478f-91ad-8767e298b01b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156867133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2156867133
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1768760476
Short name T692
Test name
Test status
Simulation time 186443071 ps
CPU time 7.27 seconds
Started Jul 20 04:37:52 PM PDT 24
Finished Jul 20 04:38:00 PM PDT 24
Peak memory 225416 kb
Host smart-dd324205-6ce7-44ba-a99d-258f0b45ae49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768760476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
1768760476
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1363561876
Short name T790
Test name
Test status
Simulation time 1676757481 ps
CPU time 9.73 seconds
Started Jul 20 04:37:37 PM PDT 24
Finished Jul 20 04:37:48 PM PDT 24
Peak memory 217764 kb
Host smart-6cd3b8f5-f05f-4b94-a12f-baef94d79a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363561876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1363561876
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1159134627
Short name T845
Test name
Test status
Simulation time 50337576 ps
CPU time 1.96 seconds
Started Jul 20 04:37:42 PM PDT 24
Finished Jul 20 04:37:46 PM PDT 24
Peak memory 213652 kb
Host smart-ed2c9d21-7b71-4071-9d59-7b59e18ac497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159134627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1159134627
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.4129349270
Short name T317
Test name
Test status
Simulation time 146840194 ps
CPU time 19.2 seconds
Started Jul 20 04:37:48 PM PDT 24
Finished Jul 20 04:38:09 PM PDT 24
Peak memory 250200 kb
Host smart-6a7ebb95-fd28-4e32-9936-1f61b1ef520c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129349270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.4129349270
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.1480856356
Short name T658
Test name
Test status
Simulation time 172646634 ps
CPU time 7.21 seconds
Started Jul 20 04:37:47 PM PDT 24
Finished Jul 20 04:37:57 PM PDT 24
Peak memory 250436 kb
Host smart-5537624f-975c-4e8b-91b3-874812dfc4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480856356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1480856356
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.3698679748
Short name T452
Test name
Test status
Simulation time 2886430599 ps
CPU time 112.86 seconds
Started Jul 20 04:37:47 PM PDT 24
Finished Jul 20 04:39:42 PM PDT 24
Peak memory 258688 kb
Host smart-6da12c3a-986c-44d5-85ae-c15a49f69a81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698679748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.3698679748
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.546345904
Short name T557
Test name
Test status
Simulation time 41374350 ps
CPU time 0.84 seconds
Started Jul 20 04:37:39 PM PDT 24
Finished Jul 20 04:37:41 PM PDT 24
Peak memory 208148 kb
Host smart-e9e33515-a09a-413a-be84-1fafd31f65e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546345904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.546345904
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.4000617152
Short name T539
Test name
Test status
Simulation time 143363830 ps
CPU time 1.01 seconds
Started Jul 20 04:37:50 PM PDT 24
Finished Jul 20 04:37:52 PM PDT 24
Peak memory 208272 kb
Host smart-c6baea6b-ff1c-43a1-8e7d-672484d48eeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000617152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.4000617152
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3541826785
Short name T612
Test name
Test status
Simulation time 1486852873 ps
CPU time 11.38 seconds
Started Jul 20 04:37:49 PM PDT 24
Finished Jul 20 04:38:02 PM PDT 24
Peak memory 217700 kb
Host smart-923002fe-ad64-44ea-b69c-e5e39e25ba70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541826785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3541826785
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2691634332
Short name T682
Test name
Test status
Simulation time 2973921885 ps
CPU time 12.95 seconds
Started Jul 20 04:37:47 PM PDT 24
Finished Jul 20 04:38:02 PM PDT 24
Peak memory 217288 kb
Host smart-52b2df7b-8361-4c54-a175-7ce197f0111d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691634332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2691634332
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.4201820583
Short name T643
Test name
Test status
Simulation time 3150118495 ps
CPU time 91.34 seconds
Started Jul 20 04:37:47 PM PDT 24
Finished Jul 20 04:39:21 PM PDT 24
Peak memory 225592 kb
Host smart-7617db4b-4592-47f6-a884-b70dc6e8d48f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201820583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.4201820583
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2863505509
Short name T21
Test name
Test status
Simulation time 537732580 ps
CPU time 5.09 seconds
Started Jul 20 04:37:46 PM PDT 24
Finished Jul 20 04:37:53 PM PDT 24
Peak memory 221180 kb
Host smart-1201bf5d-8327-480d-a1b6-56d3e76918e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863505509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2863505509
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3237477416
Short name T411
Test name
Test status
Simulation time 3818083565 ps
CPU time 10.53 seconds
Started Jul 20 04:37:49 PM PDT 24
Finished Jul 20 04:38:01 PM PDT 24
Peak memory 217108 kb
Host smart-da6143dd-5038-4cb7-a2b3-11ca3af9ac68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237477416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3237477416
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2987371987
Short name T632
Test name
Test status
Simulation time 5632336954 ps
CPU time 34.91 seconds
Started Jul 20 04:37:48 PM PDT 24
Finished Jul 20 04:38:25 PM PDT 24
Peak memory 266840 kb
Host smart-751ad570-07e2-43bb-b0f1-a8df7807ad25
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987371987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2987371987
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2112076738
Short name T735
Test name
Test status
Simulation time 1902040321 ps
CPU time 12.38 seconds
Started Jul 20 04:37:46 PM PDT 24
Finished Jul 20 04:38:00 PM PDT 24
Peak memory 250240 kb
Host smart-db072628-d8e4-4b73-85cc-84be5c1ccb24
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112076738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2112076738
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.4246973562
Short name T661
Test name
Test status
Simulation time 409662462 ps
CPU time 3.16 seconds
Started Jul 20 04:37:47 PM PDT 24
Finished Jul 20 04:37:53 PM PDT 24
Peak memory 217748 kb
Host smart-50a3521a-3b66-419d-b219-bed0c08cf731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246973562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.4246973562
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1187499523
Short name T812
Test name
Test status
Simulation time 354186332 ps
CPU time 15.98 seconds
Started Jul 20 04:37:46 PM PDT 24
Finished Jul 20 04:38:04 PM PDT 24
Peak memory 225484 kb
Host smart-9a6040e4-bfdf-4ff7-83d0-da230f267bab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187499523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1187499523
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1292642735
Short name T36
Test name
Test status
Simulation time 486864731 ps
CPU time 15.31 seconds
Started Jul 20 04:37:47 PM PDT 24
Finished Jul 20 04:38:04 PM PDT 24
Peak memory 217636 kb
Host smart-a0fabc3a-edf9-4a4f-a0a1-55a0356fc759
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292642735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1292642735
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2550843692
Short name T675
Test name
Test status
Simulation time 1256902727 ps
CPU time 9.41 seconds
Started Jul 20 04:37:49 PM PDT 24
Finished Jul 20 04:38:00 PM PDT 24
Peak memory 225420 kb
Host smart-0ae63480-0f54-4ab5-b921-25a787a55edc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550843692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2550843692
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.729460650
Short name T581
Test name
Test status
Simulation time 1618169052 ps
CPU time 11.51 seconds
Started Jul 20 04:37:46 PM PDT 24
Finished Jul 20 04:38:00 PM PDT 24
Peak memory 217776 kb
Host smart-79045ed2-f5dd-4102-a1ae-806536553921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729460650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.729460650
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3626162092
Short name T768
Test name
Test status
Simulation time 102364872 ps
CPU time 3.31 seconds
Started Jul 20 04:37:46 PM PDT 24
Finished Jul 20 04:37:52 PM PDT 24
Peak memory 217088 kb
Host smart-b2dcefd0-8c6b-4750-bc64-d8d4cceaa21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626162092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3626162092
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.61125178
Short name T99
Test name
Test status
Simulation time 437644234 ps
CPU time 18.66 seconds
Started Jul 20 04:37:47 PM PDT 24
Finished Jul 20 04:38:08 PM PDT 24
Peak memory 250448 kb
Host smart-806fdd0c-baa1-4456-8ded-bc759c785344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61125178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.61125178
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3622845075
Short name T758
Test name
Test status
Simulation time 240130289 ps
CPU time 9.32 seconds
Started Jul 20 04:37:50 PM PDT 24
Finished Jul 20 04:38:01 PM PDT 24
Peak memory 250428 kb
Host smart-473337a8-2978-41e8-af68-e18f9d8e6ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622845075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3622845075
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.628321723
Short name T759
Test name
Test status
Simulation time 67662307935 ps
CPU time 492.3 seconds
Started Jul 20 04:37:46 PM PDT 24
Finished Jul 20 04:46:01 PM PDT 24
Peak memory 332148 kb
Host smart-9cd988a1-c2cf-4f78-aae7-7ef1a1da9487
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628321723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.628321723
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.4206207422
Short name T266
Test name
Test status
Simulation time 43897208 ps
CPU time 0.77 seconds
Started Jul 20 04:37:45 PM PDT 24
Finished Jul 20 04:37:46 PM PDT 24
Peak memory 208132 kb
Host smart-6741d77e-3548-4c25-a7c5-6100513e5aae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206207422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.4206207422
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1569386604
Short name T94
Test name
Test status
Simulation time 28933487 ps
CPU time 1.04 seconds
Started Jul 20 04:38:00 PM PDT 24
Finished Jul 20 04:38:03 PM PDT 24
Peak memory 208288 kb
Host smart-63f5a85a-3a0d-4160-96c4-d7ddee8887e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569386604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1569386604
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.4269747651
Short name T696
Test name
Test status
Simulation time 1185211101 ps
CPU time 14.36 seconds
Started Jul 20 04:37:48 PM PDT 24
Finished Jul 20 04:38:04 PM PDT 24
Peak memory 217748 kb
Host smart-268b2cbb-7c76-4d89-b69b-d7d257c5f7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269747651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.4269747651
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.4046786244
Short name T599
Test name
Test status
Simulation time 2139697658 ps
CPU time 4 seconds
Started Jul 20 04:37:46 PM PDT 24
Finished Jul 20 04:37:51 PM PDT 24
Peak memory 216500 kb
Host smart-4bd10e08-5862-46ef-95c1-63345dd4167b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046786244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.4046786244
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.49651376
Short name T718
Test name
Test status
Simulation time 54343375540 ps
CPU time 90.24 seconds
Started Jul 20 04:37:46 PM PDT 24
Finished Jul 20 04:39:19 PM PDT 24
Peak memory 218168 kb
Host smart-dda68a5e-e6e7-4557-81ea-2d2771500520
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49651376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_err
ors.49651376
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3821678595
Short name T353
Test name
Test status
Simulation time 2033420844 ps
CPU time 14.17 seconds
Started Jul 20 04:37:47 PM PDT 24
Finished Jul 20 04:38:03 PM PDT 24
Peak memory 222832 kb
Host smart-9651716f-d5cd-44ac-9fe5-9829ed032765
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821678595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3821678595
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3499671206
Short name T773
Test name
Test status
Simulation time 1061314020 ps
CPU time 4.27 seconds
Started Jul 20 04:37:47 PM PDT 24
Finished Jul 20 04:37:54 PM PDT 24
Peak memory 217032 kb
Host smart-ff3a2976-6ef8-47b0-9736-d173dc92dcac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499671206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3499671206
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.654351875
Short name T366
Test name
Test status
Simulation time 19772598986 ps
CPU time 55.76 seconds
Started Jul 20 04:37:45 PM PDT 24
Finished Jul 20 04:38:42 PM PDT 24
Peak memory 278204 kb
Host smart-748b4b44-e09b-479c-a8f3-993bdc80dcc1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654351875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.654351875
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.46853793
Short name T794
Test name
Test status
Simulation time 5180367565 ps
CPU time 7.41 seconds
Started Jul 20 04:37:48 PM PDT 24
Finished Jul 20 04:37:58 PM PDT 24
Peak memory 225476 kb
Host smart-e9f5b96c-c48c-44d6-9110-8e00dd714b7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46853793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_j
tag_state_post_trans.46853793
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.153436889
Short name T88
Test name
Test status
Simulation time 123731447 ps
CPU time 3.38 seconds
Started Jul 20 04:37:47 PM PDT 24
Finished Jul 20 04:37:53 PM PDT 24
Peak memory 222000 kb
Host smart-70b2c08f-e8f8-459f-8e79-fd7e2135ccc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153436889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.153436889
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.360087416
Short name T154
Test name
Test status
Simulation time 1316062952 ps
CPU time 10.55 seconds
Started Jul 20 04:37:59 PM PDT 24
Finished Jul 20 04:38:12 PM PDT 24
Peak memory 217676 kb
Host smart-322b96f2-9055-4274-882c-928433bfc20b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360087416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.360087416
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.583045198
Short name T447
Test name
Test status
Simulation time 552329053 ps
CPU time 11.07 seconds
Started Jul 20 04:37:57 PM PDT 24
Finished Jul 20 04:38:11 PM PDT 24
Peak memory 225428 kb
Host smart-fb1ba90e-6642-403e-b2a0-83ffee119069
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583045198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.583045198
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1096902381
Short name T559
Test name
Test status
Simulation time 2029700140 ps
CPU time 10.14 seconds
Started Jul 20 04:37:47 PM PDT 24
Finished Jul 20 04:38:00 PM PDT 24
Peak memory 217764 kb
Host smart-c7ff74ca-d531-418d-bfaf-2602f0957874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096902381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1096902381
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1191696953
Short name T68
Test name
Test status
Simulation time 42783864 ps
CPU time 2.44 seconds
Started Jul 20 04:37:46 PM PDT 24
Finished Jul 20 04:37:49 PM PDT 24
Peak memory 213656 kb
Host smart-3c668c4a-963f-4fb0-b34d-726adc61ecfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191696953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1191696953
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2493740915
Short name T279
Test name
Test status
Simulation time 297833674 ps
CPU time 20.64 seconds
Started Jul 20 04:37:48 PM PDT 24
Finished Jul 20 04:38:11 PM PDT 24
Peak memory 245836 kb
Host smart-56ba3393-515a-4256-b63b-bcd22640e479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493740915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2493740915
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.453067470
Short name T788
Test name
Test status
Simulation time 474050242 ps
CPU time 7.63 seconds
Started Jul 20 04:37:46 PM PDT 24
Finished Jul 20 04:37:56 PM PDT 24
Peak memory 250388 kb
Host smart-43713134-2117-47af-95d0-852d8a4404d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453067470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.453067470
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2437798640
Short name T606
Test name
Test status
Simulation time 14789435461 ps
CPU time 226.51 seconds
Started Jul 20 04:37:56 PM PDT 24
Finished Jul 20 04:41:45 PM PDT 24
Peak memory 282624 kb
Host smart-c04033ca-1fc3-4f8a-a9f7-5c3b216cb148
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437798640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2437798640
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1809923051
Short name T833
Test name
Test status
Simulation time 28866965 ps
CPU time 0.76 seconds
Started Jul 20 04:37:50 PM PDT 24
Finished Jul 20 04:37:52 PM PDT 24
Peak memory 208184 kb
Host smart-628b4e29-ca4b-4d7c-affa-c1399718b09a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809923051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.1809923051
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1989594637
Short name T664
Test name
Test status
Simulation time 15390098 ps
CPU time 1.06 seconds
Started Jul 20 04:37:58 PM PDT 24
Finished Jul 20 04:38:01 PM PDT 24
Peak memory 208316 kb
Host smart-4f720c06-8c9b-40fc-82af-fb69c6249352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989594637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1989594637
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.497552036
Short name T627
Test name
Test status
Simulation time 615962003 ps
CPU time 14.46 seconds
Started Jul 20 04:38:02 PM PDT 24
Finished Jul 20 04:38:17 PM PDT 24
Peak memory 217700 kb
Host smart-30c67a9d-1152-49b6-80ba-e1ec3e577e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497552036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.497552036
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.804574461
Short name T427
Test name
Test status
Simulation time 541959549 ps
CPU time 6.61 seconds
Started Jul 20 04:37:56 PM PDT 24
Finished Jul 20 04:38:03 PM PDT 24
Peak memory 217088 kb
Host smart-215cc712-779a-4051-9301-66de2504d083
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804574461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.804574461
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1108784714
Short name T771
Test name
Test status
Simulation time 13276803045 ps
CPU time 43.46 seconds
Started Jul 20 04:37:59 PM PDT 24
Finished Jul 20 04:38:45 PM PDT 24
Peak memory 219164 kb
Host smart-028058fc-99bf-41b5-9590-b35b74863310
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108784714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1108784714
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2114698787
Short name T218
Test name
Test status
Simulation time 825423699 ps
CPU time 7.01 seconds
Started Jul 20 04:37:57 PM PDT 24
Finished Jul 20 04:38:05 PM PDT 24
Peak memory 222652 kb
Host smart-0136654a-d131-4c68-92e1-eac97f2f1e4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114698787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2114698787
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3345072555
Short name T407
Test name
Test status
Simulation time 754526836 ps
CPU time 5.03 seconds
Started Jul 20 04:37:59 PM PDT 24
Finished Jul 20 04:38:07 PM PDT 24
Peak memory 217024 kb
Host smart-cc88b146-4212-473b-88cd-39c85f9de863
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345072555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3345072555
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.4205474570
Short name T236
Test name
Test status
Simulation time 3911457468 ps
CPU time 33.56 seconds
Started Jul 20 04:37:56 PM PDT 24
Finished Jul 20 04:38:31 PM PDT 24
Peak memory 250720 kb
Host smart-ba439b51-7bc6-4bcb-b934-94b0e66b1c3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205474570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.4205474570
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3555067214
Short name T104
Test name
Test status
Simulation time 1304347121 ps
CPU time 10.24 seconds
Started Jul 20 04:37:55 PM PDT 24
Finished Jul 20 04:38:06 PM PDT 24
Peak memory 249492 kb
Host smart-75f66172-e1d7-425a-a85d-8fd9fcd2fa11
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555067214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.3555067214
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3511392697
Short name T158
Test name
Test status
Simulation time 390451034 ps
CPU time 3.82 seconds
Started Jul 20 04:37:58 PM PDT 24
Finished Jul 20 04:38:05 PM PDT 24
Peak memory 217692 kb
Host smart-708d7164-6623-4a7b-9813-1b9edfd55d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511392697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3511392697
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.4221775207
Short name T667
Test name
Test status
Simulation time 442794552 ps
CPU time 15.3 seconds
Started Jul 20 04:37:56 PM PDT 24
Finished Jul 20 04:38:13 PM PDT 24
Peak memory 217776 kb
Host smart-745e7df0-1a2b-4705-a11e-e925dcbad3fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221775207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.4221775207
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1964214268
Short name T588
Test name
Test status
Simulation time 2070703729 ps
CPU time 12.38 seconds
Started Jul 20 04:37:58 PM PDT 24
Finished Jul 20 04:38:13 PM PDT 24
Peak memory 225432 kb
Host smart-793cac6d-05cb-482e-8c15-901e5a753662
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964214268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1964214268
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.185864969
Short name T516
Test name
Test status
Simulation time 1533109287 ps
CPU time 18.52 seconds
Started Jul 20 04:37:57 PM PDT 24
Finished Jul 20 04:38:17 PM PDT 24
Peak memory 225416 kb
Host smart-c0c50e3e-4552-4f50-8ff3-618e42407ef9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185864969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.185864969
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2944860105
Short name T169
Test name
Test status
Simulation time 821005089 ps
CPU time 9.12 seconds
Started Jul 20 04:37:59 PM PDT 24
Finished Jul 20 04:38:10 PM PDT 24
Peak memory 225496 kb
Host smart-59636bae-10b6-400c-9bfa-85857adb4b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944860105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2944860105
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1459708776
Short name T62
Test name
Test status
Simulation time 52805593 ps
CPU time 3.15 seconds
Started Jul 20 04:37:55 PM PDT 24
Finished Jul 20 04:37:59 PM PDT 24
Peak memory 217112 kb
Host smart-367dcea8-5d69-45e7-a300-a6d1d1b4706d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459708776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1459708776
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3186710608
Short name T666
Test name
Test status
Simulation time 388200297 ps
CPU time 27.12 seconds
Started Jul 20 04:37:58 PM PDT 24
Finished Jul 20 04:38:27 PM PDT 24
Peak memory 250560 kb
Host smart-a5a5094f-edd9-44d4-8975-50e4930256d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186710608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3186710608
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.4186558588
Short name T769
Test name
Test status
Simulation time 268306944 ps
CPU time 9.22 seconds
Started Jul 20 04:37:56 PM PDT 24
Finished Jul 20 04:38:07 PM PDT 24
Peak memory 250484 kb
Host smart-b89ab271-2b76-4232-bbca-edb42a018fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186558588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.4186558588
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.4238208404
Short name T614
Test name
Test status
Simulation time 9922190802 ps
CPU time 88.52 seconds
Started Jul 20 04:37:58 PM PDT 24
Finished Jul 20 04:39:30 PM PDT 24
Peak memory 268276 kb
Host smart-c034969f-308f-4586-a2fb-f8e4925b0b21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238208404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.4238208404
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.1477739521
Short name T152
Test name
Test status
Simulation time 28588711593 ps
CPU time 689.25 seconds
Started Jul 20 04:37:58 PM PDT 24
Finished Jul 20 04:49:30 PM PDT 24
Peak memory 496356 kb
Host smart-51ff8742-5afa-494d-8e33-4cefd5f82527
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1477739521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.1477739521
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.454012386
Short name T498
Test name
Test status
Simulation time 16090756 ps
CPU time 1.14 seconds
Started Jul 20 04:37:57 PM PDT 24
Finished Jul 20 04:38:00 PM PDT 24
Peak memory 211388 kb
Host smart-8a3ce26a-6c58-4010-a1e5-e52b2188379a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454012386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.454012386
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2388992991
Short name T393
Test name
Test status
Simulation time 145309299 ps
CPU time 0.91 seconds
Started Jul 20 04:36:48 PM PDT 24
Finished Jul 20 04:36:51 PM PDT 24
Peak memory 208268 kb
Host smart-2bbe16c2-9368-45a0-a0be-01799f4dec26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388992991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2388992991
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2948346709
Short name T302
Test name
Test status
Simulation time 33994154 ps
CPU time 0.89 seconds
Started Jul 20 04:36:49 PM PDT 24
Finished Jul 20 04:36:51 PM PDT 24
Peak memory 208184 kb
Host smart-9d47696d-9604-419b-9171-9e04fba94383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948346709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2948346709
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2902732710
Short name T337
Test name
Test status
Simulation time 185142200 ps
CPU time 3.05 seconds
Started Jul 20 04:36:49 PM PDT 24
Finished Jul 20 04:36:54 PM PDT 24
Peak memory 216496 kb
Host smart-f6aba293-0301-4c65-952f-0abe56a9270f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902732710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2902732710
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2263586891
Short name T418
Test name
Test status
Simulation time 35360162633 ps
CPU time 105.12 seconds
Started Jul 20 04:36:48 PM PDT 24
Finished Jul 20 04:38:35 PM PDT 24
Peak memory 225464 kb
Host smart-d2008418-6666-4197-b0ec-a63d89c5a637
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263586891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2263586891
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.451276510
Short name T224
Test name
Test status
Simulation time 3043230539 ps
CPU time 7.87 seconds
Started Jul 20 04:36:49 PM PDT 24
Finished Jul 20 04:36:59 PM PDT 24
Peak memory 217236 kb
Host smart-59c9d780-2505-425d-81f8-a5c04aebb319
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451276510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.451276510
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.840660395
Short name T686
Test name
Test status
Simulation time 2805433613 ps
CPU time 13.35 seconds
Started Jul 20 04:36:49 PM PDT 24
Finished Jul 20 04:37:04 PM PDT 24
Peak memory 225220 kb
Host smart-81e87336-44f4-45c7-ae49-37e975257ef5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840660395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
prog_failure.840660395
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2351689083
Short name T762
Test name
Test status
Simulation time 14468735166 ps
CPU time 36.16 seconds
Started Jul 20 04:36:47 PM PDT 24
Finished Jul 20 04:37:25 PM PDT 24
Peak memory 217056 kb
Host smart-21d3d0f4-ce44-48de-8995-5a924385a66f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351689083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2351689083
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3493303160
Short name T656
Test name
Test status
Simulation time 441183046 ps
CPU time 3.96 seconds
Started Jul 20 04:36:51 PM PDT 24
Finished Jul 20 04:36:56 PM PDT 24
Peak memory 217076 kb
Host smart-13df93ef-d5c0-41dc-9f3d-7d6d8f7daa94
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493303160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3493303160
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2606855406
Short name T391
Test name
Test status
Simulation time 1501572493 ps
CPU time 69.03 seconds
Started Jul 20 04:36:46 PM PDT 24
Finished Jul 20 04:37:57 PM PDT 24
Peak memory 277320 kb
Host smart-1424baab-f9e0-41d4-9aac-88358e5fec48
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606855406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2606855406
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3417680021
Short name T166
Test name
Test status
Simulation time 4433051440 ps
CPU time 36.2 seconds
Started Jul 20 04:36:51 PM PDT 24
Finished Jul 20 04:37:28 PM PDT 24
Peak memory 225740 kb
Host smart-b5c6767b-55a9-4da3-9489-07fea00be58d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417680021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3417680021
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1935091409
Short name T593
Test name
Test status
Simulation time 61052989 ps
CPU time 2.46 seconds
Started Jul 20 04:36:51 PM PDT 24
Finished Jul 20 04:36:54 PM PDT 24
Peak memory 217684 kb
Host smart-8eb65153-b61a-49f5-97c4-73e31627b8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935091409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1935091409
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2132126985
Short name T346
Test name
Test status
Simulation time 3439244708 ps
CPU time 10.92 seconds
Started Jul 20 04:36:47 PM PDT 24
Finished Jul 20 04:36:59 PM PDT 24
Peak memory 223176 kb
Host smart-4d553a63-5544-413b-99cd-cc900520e4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132126985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2132126985
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1803780038
Short name T92
Test name
Test status
Simulation time 492061054 ps
CPU time 22.63 seconds
Started Jul 20 04:36:49 PM PDT 24
Finished Jul 20 04:37:13 PM PDT 24
Peak memory 268380 kb
Host smart-d5110525-6f34-48f2-8c03-9e4467f24bce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803780038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1803780038
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1663393816
Short name T701
Test name
Test status
Simulation time 831964412 ps
CPU time 12.74 seconds
Started Jul 20 04:36:48 PM PDT 24
Finished Jul 20 04:37:02 PM PDT 24
Peak memory 218404 kb
Host smart-6080d1b7-4d40-4ded-ae6d-0bc3b97c1416
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663393816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1663393816
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.4213832785
Short name T226
Test name
Test status
Simulation time 1119439108 ps
CPU time 10.15 seconds
Started Jul 20 04:36:47 PM PDT 24
Finished Jul 20 04:36:58 PM PDT 24
Peak memory 217628 kb
Host smart-30365033-4272-4a25-858b-3cc2d5341f87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213832785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.4213832785
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3705607759
Short name T572
Test name
Test status
Simulation time 503198830 ps
CPU time 7.74 seconds
Started Jul 20 04:36:48 PM PDT 24
Finished Jul 20 04:36:57 PM PDT 24
Peak memory 225412 kb
Host smart-fdbd33fb-af02-4bf2-8c7e-ce494386fcd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705607759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
705607759
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1778844586
Short name T537
Test name
Test status
Simulation time 212877082 ps
CPU time 7.96 seconds
Started Jul 20 04:36:48 PM PDT 24
Finished Jul 20 04:36:57 PM PDT 24
Peak memory 217760 kb
Host smart-5bfbabd8-0ba8-4317-8d5b-848080b84172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778844586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1778844586
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2593869397
Short name T448
Test name
Test status
Simulation time 109799037 ps
CPU time 1.74 seconds
Started Jul 20 04:36:51 PM PDT 24
Finished Jul 20 04:36:53 PM PDT 24
Peak memory 217128 kb
Host smart-c85d7ae2-b681-436a-8a8f-bb7ddd3caef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593869397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2593869397
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1799235685
Short name T344
Test name
Test status
Simulation time 542828397 ps
CPU time 33.59 seconds
Started Jul 20 04:36:49 PM PDT 24
Finished Jul 20 04:37:24 PM PDT 24
Peak memory 250404 kb
Host smart-bff60e9d-8880-437c-9bc0-b4a113d68e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799235685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1799235685
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.875406856
Short name T797
Test name
Test status
Simulation time 474941177 ps
CPU time 7.3 seconds
Started Jul 20 04:36:50 PM PDT 24
Finished Jul 20 04:36:58 PM PDT 24
Peak memory 250424 kb
Host smart-09b537d2-1110-4b4b-a5f0-f3c16e8e5243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875406856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.875406856
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.3525335747
Short name T269
Test name
Test status
Simulation time 13293388965 ps
CPU time 109.09 seconds
Started Jul 20 04:36:46 PM PDT 24
Finished Jul 20 04:38:37 PM PDT 24
Peak memory 276084 kb
Host smart-0f73649e-8e54-4d35-900c-980f80e26fcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525335747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.3525335747
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1882293949
Short name T388
Test name
Test status
Simulation time 23224857 ps
CPU time 0.93 seconds
Started Jul 20 04:36:49 PM PDT 24
Finished Jul 20 04:36:51 PM PDT 24
Peak memory 208332 kb
Host smart-1adff5d0-ebb6-47b1-b127-232d33a48b9e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882293949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1882293949
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1287579777
Short name T683
Test name
Test status
Simulation time 28819040 ps
CPU time 1.38 seconds
Started Jul 20 04:37:58 PM PDT 24
Finished Jul 20 04:38:02 PM PDT 24
Peak memory 208416 kb
Host smart-2f19ef7a-b702-4ea3-be5c-40cfaeb92074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287579777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1287579777
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3792643696
Short name T343
Test name
Test status
Simulation time 259293068 ps
CPU time 12.73 seconds
Started Jul 20 04:37:57 PM PDT 24
Finished Jul 20 04:38:12 PM PDT 24
Peak memory 217752 kb
Host smart-027939a8-1972-452c-9efd-66b3b681c866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792643696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3792643696
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.1125766086
Short name T499
Test name
Test status
Simulation time 45452804 ps
CPU time 1.27 seconds
Started Jul 20 04:37:58 PM PDT 24
Finished Jul 20 04:38:01 PM PDT 24
Peak memory 216840 kb
Host smart-cafab19a-3d9b-42a0-a9d0-f8441f39c3d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125766086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1125766086
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1903385020
Short name T181
Test name
Test status
Simulation time 51441234 ps
CPU time 2.58 seconds
Started Jul 20 04:37:56 PM PDT 24
Finished Jul 20 04:38:01 PM PDT 24
Peak memory 217960 kb
Host smart-36306f1a-227c-4174-8a68-1ebbef96f305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903385020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1903385020
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.288091545
Short name T307
Test name
Test status
Simulation time 1337960654 ps
CPU time 16.07 seconds
Started Jul 20 04:37:58 PM PDT 24
Finished Jul 20 04:38:16 PM PDT 24
Peak memory 218324 kb
Host smart-f9aa8661-8e82-4973-9b79-ab6cfcbaee96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288091545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.288091545
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2516664156
Short name T271
Test name
Test status
Simulation time 15489251278 ps
CPU time 18.51 seconds
Started Jul 20 04:37:58 PM PDT 24
Finished Jul 20 04:38:19 PM PDT 24
Peak memory 217736 kb
Host smart-0d5228e5-40a9-478f-a8c0-983d292d5b5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516664156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2516664156
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.4035413539
Short name T462
Test name
Test status
Simulation time 1743647644 ps
CPU time 8.44 seconds
Started Jul 20 04:37:56 PM PDT 24
Finished Jul 20 04:38:05 PM PDT 24
Peak memory 225428 kb
Host smart-693e5bc6-7f85-440d-a6d1-c4739019ce5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035413539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
4035413539
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3878661949
Short name T685
Test name
Test status
Simulation time 624074729 ps
CPU time 10.45 seconds
Started Jul 20 04:37:58 PM PDT 24
Finished Jul 20 04:38:11 PM PDT 24
Peak memory 225488 kb
Host smart-5b98ac13-2de1-4133-abc0-a027968cd5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878661949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3878661949
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2484780612
Short name T798
Test name
Test status
Simulation time 23533032 ps
CPU time 1.6 seconds
Started Jul 20 04:37:54 PM PDT 24
Finished Jul 20 04:37:57 PM PDT 24
Peak memory 217116 kb
Host smart-7c485890-c25c-46eb-a53f-cd8f6c1c7865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484780612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2484780612
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3471787341
Short name T756
Test name
Test status
Simulation time 350627187 ps
CPU time 34.38 seconds
Started Jul 20 04:37:58 PM PDT 24
Finished Jul 20 04:38:35 PM PDT 24
Peak memory 250432 kb
Host smart-1d80f16f-d662-4e02-a8b2-c35cae482657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471787341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3471787341
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.4241251973
Short name T787
Test name
Test status
Simulation time 216078436 ps
CPU time 7.84 seconds
Started Jul 20 04:37:58 PM PDT 24
Finished Jul 20 04:38:09 PM PDT 24
Peak memory 250436 kb
Host smart-a1488f7c-ce04-450d-a883-47b79361593d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241251973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.4241251973
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2398737617
Short name T597
Test name
Test status
Simulation time 49103051590 ps
CPU time 436.21 seconds
Started Jul 20 04:37:57 PM PDT 24
Finished Jul 20 04:45:15 PM PDT 24
Peak memory 272112 kb
Host smart-357d12df-6e5e-417b-86f7-1eb9e9ee08f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398737617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2398737617
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2972213246
Short name T818
Test name
Test status
Simulation time 11395731 ps
CPU time 0.78 seconds
Started Jul 20 04:37:56 PM PDT 24
Finished Jul 20 04:37:57 PM PDT 24
Peak memory 208268 kb
Host smart-46a60472-2cc2-4f19-962f-2a8f8590f0b6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972213246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2972213246
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3280011135
Short name T323
Test name
Test status
Simulation time 15380792 ps
CPU time 0.85 seconds
Started Jul 20 04:38:07 PM PDT 24
Finished Jul 20 04:38:09 PM PDT 24
Peak memory 208108 kb
Host smart-79308ea6-f633-4742-9626-9368890082c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280011135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3280011135
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.196642260
Short name T770
Test name
Test status
Simulation time 345738230 ps
CPU time 15.7 seconds
Started Jul 20 04:37:57 PM PDT 24
Finished Jul 20 04:38:14 PM PDT 24
Peak memory 218016 kb
Host smart-9478a487-7534-4dca-8034-79a5c714bd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196642260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.196642260
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3316840262
Short name T433
Test name
Test status
Simulation time 857787660 ps
CPU time 6.42 seconds
Started Jul 20 04:37:58 PM PDT 24
Finished Jul 20 04:38:07 PM PDT 24
Peak memory 216500 kb
Host smart-b8749774-9af2-4877-bb6a-ebc1715afaa7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316840262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3316840262
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2409917586
Short name T225
Test name
Test status
Simulation time 65252049 ps
CPU time 3.31 seconds
Started Jul 20 04:37:56 PM PDT 24
Finished Jul 20 04:38:01 PM PDT 24
Peak memory 217740 kb
Host smart-b985bf33-05d2-40e4-8028-0fd5bdd5f5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409917586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2409917586
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.179397852
Short name T364
Test name
Test status
Simulation time 508407867 ps
CPU time 21.71 seconds
Started Jul 20 04:38:09 PM PDT 24
Finished Jul 20 04:38:32 PM PDT 24
Peak memory 225540 kb
Host smart-03d8a564-6d1f-44cc-af7c-9ee6bce77f6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179397852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.179397852
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2969709572
Short name T274
Test name
Test status
Simulation time 1075461974 ps
CPU time 11.21 seconds
Started Jul 20 04:38:06 PM PDT 24
Finished Jul 20 04:38:19 PM PDT 24
Peak memory 217568 kb
Host smart-01ecd142-0faa-4d66-8e25-1a3839ac84c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969709572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2969709572
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3260924063
Short name T292
Test name
Test status
Simulation time 1376439309 ps
CPU time 9.37 seconds
Started Jul 20 04:38:09 PM PDT 24
Finished Jul 20 04:38:19 PM PDT 24
Peak memory 225472 kb
Host smart-aad5becf-41aa-41e2-b3ac-6ae5dd3fc446
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260924063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3260924063
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3794737689
Short name T830
Test name
Test status
Simulation time 1439743196 ps
CPU time 12.41 seconds
Started Jul 20 04:37:57 PM PDT 24
Finished Jul 20 04:38:12 PM PDT 24
Peak memory 217760 kb
Host smart-410f57d2-763a-4dd8-9823-f1b68d0e4879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794737689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3794737689
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.687449479
Short name T331
Test name
Test status
Simulation time 67227330 ps
CPU time 3.11 seconds
Started Jul 20 04:37:58 PM PDT 24
Finished Jul 20 04:38:04 PM PDT 24
Peak memory 217152 kb
Host smart-6c151a5d-0d45-4d3b-b90d-188834268b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687449479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.687449479
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.139010881
Short name T810
Test name
Test status
Simulation time 387808632 ps
CPU time 21.27 seconds
Started Jul 20 04:37:57 PM PDT 24
Finished Jul 20 04:38:21 PM PDT 24
Peak memory 250488 kb
Host smart-2e7105e1-0d17-473b-a93a-f48d90b14baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139010881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.139010881
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.428590629
Short name T259
Test name
Test status
Simulation time 1257176701 ps
CPU time 6.87 seconds
Started Jul 20 04:37:58 PM PDT 24
Finished Jul 20 04:38:07 PM PDT 24
Peak memory 245924 kb
Host smart-a8b77817-9b4c-474a-bbb3-3b3b1297dd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428590629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.428590629
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.1531593664
Short name T150
Test name
Test status
Simulation time 281243235198 ps
CPU time 655.1 seconds
Started Jul 20 04:38:05 PM PDT 24
Finished Jul 20 04:49:01 PM PDT 24
Peak memory 512788 kb
Host smart-a601b1f8-98bc-44c2-8fae-80c40a9acfa2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1531593664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.1531593664
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2383775830
Short name T802
Test name
Test status
Simulation time 39126651 ps
CPU time 0.96 seconds
Started Jul 20 04:37:58 PM PDT 24
Finished Jul 20 04:38:01 PM PDT 24
Peak memory 217116 kb
Host smart-b1e00840-46d9-4541-995e-02d1d10cb9df
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383775830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2383775830
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2305730927
Short name T359
Test name
Test status
Simulation time 49826704 ps
CPU time 1.07 seconds
Started Jul 20 04:38:04 PM PDT 24
Finished Jul 20 04:38:06 PM PDT 24
Peak memory 208416 kb
Host smart-cbcd5079-5f03-4773-8ca5-3a60756bff72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305730927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2305730927
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2262077944
Short name T439
Test name
Test status
Simulation time 326451533 ps
CPU time 11.93 seconds
Started Jul 20 04:38:06 PM PDT 24
Finished Jul 20 04:38:20 PM PDT 24
Peak memory 217768 kb
Host smart-f5528a7a-37de-4ec0-ade7-11fe7cec222f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262077944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2262077944
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3741446937
Short name T455
Test name
Test status
Simulation time 289098488 ps
CPU time 7.38 seconds
Started Jul 20 04:38:10 PM PDT 24
Finished Jul 20 04:38:18 PM PDT 24
Peak memory 216768 kb
Host smart-985afeeb-42af-45cb-809e-f4d34cee751f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741446937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3741446937
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3700655785
Short name T807
Test name
Test status
Simulation time 112866448 ps
CPU time 1.75 seconds
Started Jul 20 04:38:05 PM PDT 24
Finished Jul 20 04:38:09 PM PDT 24
Peak memory 217748 kb
Host smart-5e8da200-22bb-4e0d-bd77-7b57ac05badc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700655785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3700655785
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1594373455
Short name T642
Test name
Test status
Simulation time 602523140 ps
CPU time 20.01 seconds
Started Jul 20 04:38:04 PM PDT 24
Finished Jul 20 04:38:24 PM PDT 24
Peak memory 217684 kb
Host smart-98ee6e6a-2225-4c42-8c32-df8511686873
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594373455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1594373455
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3202974101
Short name T229
Test name
Test status
Simulation time 828759880 ps
CPU time 15.22 seconds
Started Jul 20 04:38:06 PM PDT 24
Finished Jul 20 04:38:23 PM PDT 24
Peak memory 224932 kb
Host smart-8596616f-292b-41b6-8f02-f9986eb6c9c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202974101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3202974101
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.4001796369
Short name T409
Test name
Test status
Simulation time 5758509395 ps
CPU time 10.9 seconds
Started Jul 20 04:38:09 PM PDT 24
Finished Jul 20 04:38:21 PM PDT 24
Peak memory 217184 kb
Host smart-44c476e3-c4c2-46da-ad24-ce0c4b295eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001796369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.4001796369
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3226665404
Short name T102
Test name
Test status
Simulation time 175372574 ps
CPU time 3 seconds
Started Jul 20 04:38:04 PM PDT 24
Finished Jul 20 04:38:08 PM PDT 24
Peak memory 217108 kb
Host smart-65c8ed49-5423-482e-8ae9-4b471059675f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226665404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3226665404
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1707312785
Short name T808
Test name
Test status
Simulation time 3055973377 ps
CPU time 25.73 seconds
Started Jul 20 04:38:09 PM PDT 24
Finished Jul 20 04:38:36 PM PDT 24
Peak memory 250548 kb
Host smart-c53ba3e0-e26d-43dc-969a-a252bb2a8ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707312785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1707312785
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2268928802
Short name T495
Test name
Test status
Simulation time 141495582 ps
CPU time 7.4 seconds
Started Jul 20 04:38:04 PM PDT 24
Finished Jul 20 04:38:12 PM PDT 24
Peak memory 250464 kb
Host smart-99b34a77-cf81-48d2-ace4-20c23121d4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268928802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2268928802
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1137468
Short name T110
Test name
Test status
Simulation time 1878797834 ps
CPU time 86.3 seconds
Started Jul 20 04:38:10 PM PDT 24
Finished Jul 20 04:39:37 PM PDT 24
Peak memory 250484 kb
Host smart-6c1f18bd-efda-4137-9132-01f5d9730c47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TE
ST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.lc_ctrl_stress_all.1137468
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.256880049
Short name T2
Test name
Test status
Simulation time 28691856 ps
CPU time 1.11 seconds
Started Jul 20 04:38:08 PM PDT 24
Finished Jul 20 04:38:11 PM PDT 24
Peak memory 217268 kb
Host smart-6b65a601-dd9a-4ab4-86c7-580143398225
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256880049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.256880049
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3987987567
Short name T838
Test name
Test status
Simulation time 41995335 ps
CPU time 0.9 seconds
Started Jul 20 04:38:05 PM PDT 24
Finished Jul 20 04:38:08 PM PDT 24
Peak memory 208312 kb
Host smart-e85a1e82-3b52-48b0-817e-3afc651d1edf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987987567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3987987567
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3987122498
Short name T175
Test name
Test status
Simulation time 402028778 ps
CPU time 8.15 seconds
Started Jul 20 04:38:07 PM PDT 24
Finished Jul 20 04:38:16 PM PDT 24
Peak memory 217744 kb
Host smart-5c7a7d5f-b758-4ded-a55d-a94e7671afe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987122498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3987122498
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3029153163
Short name T9
Test name
Test status
Simulation time 687346984 ps
CPU time 2.74 seconds
Started Jul 20 04:38:05 PM PDT 24
Finished Jul 20 04:38:09 PM PDT 24
Peak memory 216564 kb
Host smart-e50460d1-6d2e-4b15-b7f2-d93696196df8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029153163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3029153163
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1646383560
Short name T836
Test name
Test status
Simulation time 280457674 ps
CPU time 4.62 seconds
Started Jul 20 04:38:07 PM PDT 24
Finished Jul 20 04:38:13 PM PDT 24
Peak memory 222200 kb
Host smart-0634ee91-199e-4c3d-8ca3-3176f855ec5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646383560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1646383560
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1282527642
Short name T617
Test name
Test status
Simulation time 325092023 ps
CPU time 9.56 seconds
Started Jul 20 04:38:05 PM PDT 24
Finished Jul 20 04:38:16 PM PDT 24
Peak memory 224920 kb
Host smart-47f25386-90b2-4428-8bb3-999273ac4d50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282527642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1282527642
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.4093677023
Short name T490
Test name
Test status
Simulation time 364030532 ps
CPU time 10.28 seconds
Started Jul 20 04:38:05 PM PDT 24
Finished Jul 20 04:38:16 PM PDT 24
Peak memory 225428 kb
Host smart-62efeaf0-072c-473b-ad97-231fc46ab6ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093677023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
4093677023
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2264478364
Short name T824
Test name
Test status
Simulation time 521207933 ps
CPU time 10.93 seconds
Started Jul 20 04:38:09 PM PDT 24
Finished Jul 20 04:38:21 PM PDT 24
Peak memory 224644 kb
Host smart-50886b26-1090-4c23-bbe4-e2ba2b3b33b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264478364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2264478364
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1699924945
Short name T502
Test name
Test status
Simulation time 73457043 ps
CPU time 1.67 seconds
Started Jul 20 04:38:05 PM PDT 24
Finished Jul 20 04:38:09 PM PDT 24
Peak memory 217056 kb
Host smart-49d14913-cbdd-444b-949a-5d06446b53a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699924945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1699924945
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3333522360
Short name T303
Test name
Test status
Simulation time 337364361 ps
CPU time 33.92 seconds
Started Jul 20 04:38:06 PM PDT 24
Finished Jul 20 04:38:41 PM PDT 24
Peak memory 250424 kb
Host smart-f24dca66-1add-41ea-acb7-ce6a6a20d321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333522360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3333522360
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3347205529
Short name T432
Test name
Test status
Simulation time 349471262 ps
CPU time 3.14 seconds
Started Jul 20 04:38:05 PM PDT 24
Finished Jul 20 04:38:10 PM PDT 24
Peak memory 221900 kb
Host smart-fb0e07d5-d446-4a57-8d40-7be35829e557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347205529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3347205529
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.184780828
Short name T474
Test name
Test status
Simulation time 2698690433 ps
CPU time 84.42 seconds
Started Jul 20 04:38:04 PM PDT 24
Finished Jul 20 04:39:29 PM PDT 24
Peak memory 270256 kb
Host smart-65090680-9285-40c6-bd4e-bb21a7b65b29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184780828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.184780828
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.221157214
Short name T312
Test name
Test status
Simulation time 12418508 ps
CPU time 0.85 seconds
Started Jul 20 04:38:05 PM PDT 24
Finished Jul 20 04:38:08 PM PDT 24
Peak memory 208188 kb
Host smart-cc01e08b-ebff-4470-92c5-2eb26e6291ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221157214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.221157214
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2570290346
Short name T567
Test name
Test status
Simulation time 953951526 ps
CPU time 9.01 seconds
Started Jul 20 04:38:07 PM PDT 24
Finished Jul 20 04:38:17 PM PDT 24
Peak memory 217800 kb
Host smart-625f1991-cdf6-4ade-b1be-d00974e17fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570290346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2570290346
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2356913692
Short name T625
Test name
Test status
Simulation time 275255104 ps
CPU time 2.07 seconds
Started Jul 20 04:38:08 PM PDT 24
Finished Jul 20 04:38:11 PM PDT 24
Peak memory 216568 kb
Host smart-6041e967-7880-44f1-9219-c6dca89529c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356913692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2356913692
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1843137462
Short name T576
Test name
Test status
Simulation time 26866671 ps
CPU time 1.75 seconds
Started Jul 20 04:38:03 PM PDT 24
Finished Jul 20 04:38:05 PM PDT 24
Peak memory 221544 kb
Host smart-a4d8326a-6ae9-4459-a192-f7112abcf064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843137462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1843137462
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.902542750
Short name T355
Test name
Test status
Simulation time 995782360 ps
CPU time 13.43 seconds
Started Jul 20 04:38:09 PM PDT 24
Finished Jul 20 04:38:23 PM PDT 24
Peak memory 217804 kb
Host smart-21716b12-0c11-4369-b447-9b3df3801f2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902542750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.902542750
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2108914446
Short name T437
Test name
Test status
Simulation time 2083352999 ps
CPU time 8.93 seconds
Started Jul 20 04:38:03 PM PDT 24
Finished Jul 20 04:38:13 PM PDT 24
Peak memory 217744 kb
Host smart-a45fc23e-31ce-41c1-b801-109aa40b7703
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108914446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2108914446
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2547453042
Short name T240
Test name
Test status
Simulation time 203646322 ps
CPU time 6.39 seconds
Started Jul 20 04:38:07 PM PDT 24
Finished Jul 20 04:38:15 PM PDT 24
Peak memory 225404 kb
Host smart-ddb3f72e-a090-450a-9554-11f891d8752f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547453042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2547453042
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2568828670
Short name T41
Test name
Test status
Simulation time 5225484371 ps
CPU time 7.49 seconds
Started Jul 20 04:38:08 PM PDT 24
Finished Jul 20 04:38:17 PM PDT 24
Peak memory 217824 kb
Host smart-ba7b2ab8-5dcb-4517-ba24-bfec8b584e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568828670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2568828670
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1887758273
Short name T700
Test name
Test status
Simulation time 31877195 ps
CPU time 1.52 seconds
Started Jul 20 04:38:09 PM PDT 24
Finished Jul 20 04:38:11 PM PDT 24
Peak memory 217100 kb
Host smart-349e4cc7-3b79-4f8d-ad33-36377074f9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887758273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1887758273
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3357847174
Short name T295
Test name
Test status
Simulation time 268054785 ps
CPU time 33.91 seconds
Started Jul 20 04:38:10 PM PDT 24
Finished Jul 20 04:38:45 PM PDT 24
Peak memory 250492 kb
Host smart-bc135c2b-bbe6-4390-9a49-c8e76466c95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357847174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3357847174
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1469679966
Short name T90
Test name
Test status
Simulation time 366359136 ps
CPU time 7.61 seconds
Started Jul 20 04:38:06 PM PDT 24
Finished Jul 20 04:38:15 PM PDT 24
Peak memory 250420 kb
Host smart-bef027d6-b569-4d46-a3a0-2b3095ad70f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469679966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1469679966
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2095879811
Short name T183
Test name
Test status
Simulation time 29925805217 ps
CPU time 247.69 seconds
Started Jul 20 04:38:06 PM PDT 24
Finished Jul 20 04:42:15 PM PDT 24
Peak memory 258620 kb
Host smart-72c10458-c19c-4651-92ad-4999cad08e7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095879811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2095879811
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1576504129
Short name T77
Test name
Test status
Simulation time 156868043 ps
CPU time 0.93 seconds
Started Jul 20 04:38:03 PM PDT 24
Finished Jul 20 04:38:05 PM PDT 24
Peak memory 211208 kb
Host smart-1ec61e87-6d35-4089-a4bd-ffcddcb5c64a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576504129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1576504129
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1433234764
Short name T313
Test name
Test status
Simulation time 152438225 ps
CPU time 0.82 seconds
Started Jul 20 04:38:16 PM PDT 24
Finished Jul 20 04:38:19 PM PDT 24
Peak memory 208132 kb
Host smart-c9c2973e-f6ed-498f-a0da-bc2148281c5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433234764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1433234764
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2880258732
Short name T417
Test name
Test status
Simulation time 252983615 ps
CPU time 9.25 seconds
Started Jul 20 04:38:16 PM PDT 24
Finished Jul 20 04:38:28 PM PDT 24
Peak memory 217812 kb
Host smart-822b380d-a671-416d-9d48-b6ff88e6853c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880258732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2880258732
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3373106972
Short name T528
Test name
Test status
Simulation time 4685121004 ps
CPU time 4.91 seconds
Started Jul 20 04:38:14 PM PDT 24
Finished Jul 20 04:38:21 PM PDT 24
Peak memory 217120 kb
Host smart-2a69a2f4-7533-48a6-83d0-c5bc58e70477
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373106972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3373106972
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.779149677
Short name T283
Test name
Test status
Simulation time 133961634 ps
CPU time 2.83 seconds
Started Jul 20 04:38:15 PM PDT 24
Finished Jul 20 04:38:20 PM PDT 24
Peak memory 217636 kb
Host smart-b5e80b44-0d98-4832-8d49-67646017b6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779149677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.779149677
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.3259983394
Short name T781
Test name
Test status
Simulation time 289016927 ps
CPU time 10.14 seconds
Started Jul 20 04:38:14 PM PDT 24
Finished Jul 20 04:38:25 PM PDT 24
Peak memory 225492 kb
Host smart-198ad870-fa0a-453b-997b-64237b18333d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259983394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3259983394
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.265918010
Short name T282
Test name
Test status
Simulation time 806488483 ps
CPU time 9.27 seconds
Started Jul 20 04:38:15 PM PDT 24
Finished Jul 20 04:38:26 PM PDT 24
Peak memory 217696 kb
Host smart-9bd4e6d1-64f6-428a-bf11-291eeffc15b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265918010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.265918010
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1964650607
Short name T534
Test name
Test status
Simulation time 1470269576 ps
CPU time 8 seconds
Started Jul 20 04:38:14 PM PDT 24
Finished Jul 20 04:38:23 PM PDT 24
Peak memory 225376 kb
Host smart-f0d4734a-6203-42c7-9f59-30da3cc6eeca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964650607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1964650607
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2724785857
Short name T659
Test name
Test status
Simulation time 559672480 ps
CPU time 8.86 seconds
Started Jul 20 04:38:15 PM PDT 24
Finished Jul 20 04:38:26 PM PDT 24
Peak memory 217716 kb
Host smart-6eead309-6c00-44f9-84a9-99ebb3b9803e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724785857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2724785857
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1895426728
Short name T687
Test name
Test status
Simulation time 283902000 ps
CPU time 24.39 seconds
Started Jul 20 04:38:17 PM PDT 24
Finished Jul 20 04:38:44 PM PDT 24
Peak memory 250332 kb
Host smart-faec8fa6-79fe-4ba3-9069-740bbcacab49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895426728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1895426728
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.2116170852
Short name T730
Test name
Test status
Simulation time 47669135 ps
CPU time 5.8 seconds
Started Jul 20 04:38:16 PM PDT 24
Finished Jul 20 04:38:24 PM PDT 24
Peak memory 250012 kb
Host smart-cf950bd5-484c-4a3d-9c03-6ca2c6ee9f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116170852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2116170852
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.153813166
Short name T48
Test name
Test status
Simulation time 3515231179 ps
CPU time 66.2 seconds
Started Jul 20 04:38:14 PM PDT 24
Finished Jul 20 04:39:21 PM PDT 24
Peak memory 250500 kb
Host smart-69fc44dd-0326-48bc-bd87-bac0500f250d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153813166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.153813166
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.136212155
Short name T673
Test name
Test status
Simulation time 128739530 ps
CPU time 1.16 seconds
Started Jul 20 04:38:14 PM PDT 24
Finished Jul 20 04:38:16 PM PDT 24
Peak memory 217088 kb
Host smart-68d507a2-a893-496a-beab-badb138b08d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136212155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.136212155
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.3849348510
Short name T354
Test name
Test status
Simulation time 22015284 ps
CPU time 0.82 seconds
Started Jul 20 04:38:15 PM PDT 24
Finished Jul 20 04:38:18 PM PDT 24
Peak memory 208024 kb
Host smart-b78e8183-7265-42d3-9771-37664b447b5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849348510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.3849348510
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.2558540256
Short name T429
Test name
Test status
Simulation time 2128233418 ps
CPU time 11.91 seconds
Started Jul 20 04:38:16 PM PDT 24
Finished Jul 20 04:38:30 PM PDT 24
Peak memory 217772 kb
Host smart-283404c4-2cab-4c28-941d-0a5e1f24e4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558540256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2558540256
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1859560650
Short name T817
Test name
Test status
Simulation time 207656615 ps
CPU time 2.83 seconds
Started Jul 20 04:38:15 PM PDT 24
Finished Jul 20 04:38:20 PM PDT 24
Peak memory 216840 kb
Host smart-a8c6c30c-318a-473a-9cec-c74142bf3af5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859560650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1859560650
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.2192473345
Short name T15
Test name
Test status
Simulation time 53641620 ps
CPU time 2.43 seconds
Started Jul 20 04:38:17 PM PDT 24
Finished Jul 20 04:38:22 PM PDT 24
Peak memory 221584 kb
Host smart-f63e7138-1172-466a-a2fc-fc65e08c7a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192473345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2192473345
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.690555124
Short name T739
Test name
Test status
Simulation time 267710942 ps
CPU time 12.26 seconds
Started Jul 20 04:38:15 PM PDT 24
Finished Jul 20 04:38:30 PM PDT 24
Peak memory 225544 kb
Host smart-99ec361d-5e2d-4753-b039-07404367b672
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690555124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.690555124
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3988822792
Short name T764
Test name
Test status
Simulation time 809212127 ps
CPU time 15.85 seconds
Started Jul 20 04:38:17 PM PDT 24
Finished Jul 20 04:38:35 PM PDT 24
Peak memory 217664 kb
Host smart-b0c24344-0fae-4459-a14c-aeab2862dd31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988822792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3988822792
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3474068971
Short name T734
Test name
Test status
Simulation time 902571302 ps
CPU time 16.1 seconds
Started Jul 20 04:38:13 PM PDT 24
Finished Jul 20 04:38:30 PM PDT 24
Peak memory 225468 kb
Host smart-c33ab597-60e4-475c-990d-c9e6a9c7b4bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474068971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3474068971
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2686275198
Short name T616
Test name
Test status
Simulation time 808510024 ps
CPU time 8.73 seconds
Started Jul 20 04:38:17 PM PDT 24
Finished Jul 20 04:38:28 PM PDT 24
Peak memory 217672 kb
Host smart-999ddaf1-63eb-4a79-8a95-fdd7c18282bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686275198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2686275198
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.626359118
Short name T497
Test name
Test status
Simulation time 121630386 ps
CPU time 2.29 seconds
Started Jul 20 04:38:15 PM PDT 24
Finished Jul 20 04:38:20 PM PDT 24
Peak memory 213916 kb
Host smart-802a40ba-45dc-4609-888e-4162f795d4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626359118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.626359118
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.194725726
Short name T500
Test name
Test status
Simulation time 1417679509 ps
CPU time 31.07 seconds
Started Jul 20 04:38:14 PM PDT 24
Finished Jul 20 04:38:46 PM PDT 24
Peak memory 250480 kb
Host smart-2a33a9d4-158b-4853-855e-69a675ab10eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194725726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.194725726
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.4178198607
Short name T532
Test name
Test status
Simulation time 250269606 ps
CPU time 9.32 seconds
Started Jul 20 04:38:17 PM PDT 24
Finished Jul 20 04:38:29 PM PDT 24
Peak memory 250440 kb
Host smart-b7b86135-dfa3-4f53-8b4e-2901d49f6aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178198607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.4178198607
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.4062490241
Short name T365
Test name
Test status
Simulation time 918473599 ps
CPU time 26.03 seconds
Started Jul 20 04:38:13 PM PDT 24
Finished Jul 20 04:38:40 PM PDT 24
Peak memory 250472 kb
Host smart-3157b1b2-661f-4acd-8712-f99ce62d3c65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062490241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.4062490241
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.3532091204
Short name T151
Test name
Test status
Simulation time 22680802953 ps
CPU time 422.6 seconds
Started Jul 20 04:38:17 PM PDT 24
Finished Jul 20 04:45:22 PM PDT 24
Peak memory 283436 kb
Host smart-c910fd5d-765f-4712-b614-e281ba011069
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3532091204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.3532091204
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2710449601
Short name T44
Test name
Test status
Simulation time 24781959 ps
CPU time 0.85 seconds
Started Jul 20 04:38:16 PM PDT 24
Finished Jul 20 04:38:19 PM PDT 24
Peak memory 208476 kb
Host smart-d4b9c830-7f80-46e0-bd2b-9736ea265bbc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710449601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2710449601
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2353237644
Short name T624
Test name
Test status
Simulation time 15558467 ps
CPU time 1.12 seconds
Started Jul 20 04:38:16 PM PDT 24
Finished Jul 20 04:38:19 PM PDT 24
Peak memory 208360 kb
Host smart-3a1cab01-712a-44b0-a40b-804b56df855c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353237644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2353237644
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2774979379
Short name T488
Test name
Test status
Simulation time 316668065 ps
CPU time 10.74 seconds
Started Jul 20 04:38:15 PM PDT 24
Finished Jul 20 04:38:28 PM PDT 24
Peak memory 217696 kb
Host smart-2e04f6f3-6d6b-4b1d-9519-af283922c6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774979379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2774979379
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.3954851311
Short name T184
Test name
Test status
Simulation time 916858555 ps
CPU time 4.84 seconds
Started Jul 20 04:38:16 PM PDT 24
Finished Jul 20 04:38:23 PM PDT 24
Peak memory 216664 kb
Host smart-b967a675-cbdc-4a40-9713-9a03c7fead3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954851311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.3954851311
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.2468190261
Short name T398
Test name
Test status
Simulation time 178663816 ps
CPU time 2.26 seconds
Started Jul 20 04:38:13 PM PDT 24
Finished Jul 20 04:38:17 PM PDT 24
Peak memory 217928 kb
Host smart-89f5661c-fc3c-46d9-bacd-173a444aa952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468190261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2468190261
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.349276984
Short name T708
Test name
Test status
Simulation time 274379452 ps
CPU time 10.03 seconds
Started Jul 20 04:38:13 PM PDT 24
Finished Jul 20 04:38:24 PM PDT 24
Peak memory 217748 kb
Host smart-5be925ef-f181-4bce-b9ef-a53ebf284fda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349276984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di
gest.349276984
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2255781926
Short name T308
Test name
Test status
Simulation time 1618615146 ps
CPU time 16.51 seconds
Started Jul 20 04:38:16 PM PDT 24
Finished Jul 20 04:38:35 PM PDT 24
Peak memory 225420 kb
Host smart-15915169-94a3-4920-8a46-46038346f0ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255781926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2255781926
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1622066581
Short name T709
Test name
Test status
Simulation time 1475601543 ps
CPU time 10.29 seconds
Started Jul 20 04:38:13 PM PDT 24
Finished Jul 20 04:38:24 PM PDT 24
Peak memory 217764 kb
Host smart-637986ab-02c5-40f1-b1f8-5ca2b809b984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622066581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1622066581
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1215062439
Short name T789
Test name
Test status
Simulation time 20862168 ps
CPU time 1.51 seconds
Started Jul 20 04:38:17 PM PDT 24
Finished Jul 20 04:38:20 PM PDT 24
Peak memory 213436 kb
Host smart-f16fa714-3a3a-478d-9c2f-4911e3735b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215062439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1215062439
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3127688504
Short name T777
Test name
Test status
Simulation time 302987566 ps
CPU time 21.99 seconds
Started Jul 20 04:38:17 PM PDT 24
Finished Jul 20 04:38:41 PM PDT 24
Peak memory 250328 kb
Host smart-99875a39-cbc6-4d92-b5a9-1bbf25b0a5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127688504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3127688504
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.2229471770
Short name T262
Test name
Test status
Simulation time 245096717 ps
CPU time 8.36 seconds
Started Jul 20 04:38:16 PM PDT 24
Finished Jul 20 04:38:27 PM PDT 24
Peak memory 250348 kb
Host smart-77fa576a-b1e4-405e-bd54-fdc2ad21742e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229471770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2229471770
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1330147916
Short name T844
Test name
Test status
Simulation time 1465596922 ps
CPU time 42.27 seconds
Started Jul 20 04:38:15 PM PDT 24
Finished Jul 20 04:39:00 PM PDT 24
Peak memory 250380 kb
Host smart-6e88583c-a01a-4433-8d5a-c7880a23b6d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330147916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1330147916
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2186505827
Short name T60
Test name
Test status
Simulation time 135594425 ps
CPU time 0.93 seconds
Started Jul 20 04:38:16 PM PDT 24
Finished Jul 20 04:38:20 PM PDT 24
Peak memory 211308 kb
Host smart-22e02da6-20c2-4f47-ac8f-441d38056d15
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186505827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2186505827
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.198204156
Short name T637
Test name
Test status
Simulation time 24934819 ps
CPU time 0.95 seconds
Started Jul 20 04:38:28 PM PDT 24
Finished Jul 20 04:38:32 PM PDT 24
Peak memory 208352 kb
Host smart-a0455c87-511f-488b-9063-117bab62eeef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198204156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.198204156
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.1545016771
Short name T517
Test name
Test status
Simulation time 167827569 ps
CPU time 8.4 seconds
Started Jul 20 04:38:14 PM PDT 24
Finished Jul 20 04:38:23 PM PDT 24
Peak memory 217724 kb
Host smart-212fbdff-d5f2-40b3-96f1-6dfbcf8f12ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545016771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.1545016771
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3303184683
Short name T611
Test name
Test status
Simulation time 3498260292 ps
CPU time 7.52 seconds
Started Jul 20 04:38:13 PM PDT 24
Finished Jul 20 04:38:22 PM PDT 24
Peak memory 217028 kb
Host smart-740b1458-db73-421c-af43-bee6aa89f64e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303184683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3303184683
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.4170447015
Short name T628
Test name
Test status
Simulation time 407880778 ps
CPU time 3.27 seconds
Started Jul 20 04:38:16 PM PDT 24
Finished Jul 20 04:38:22 PM PDT 24
Peak memory 221732 kb
Host smart-385dc14f-9efe-4825-adb1-31eb6579bf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170447015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.4170447015
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3890574789
Short name T330
Test name
Test status
Simulation time 696953597 ps
CPU time 17.74 seconds
Started Jul 20 04:38:28 PM PDT 24
Finished Jul 20 04:38:48 PM PDT 24
Peak memory 217688 kb
Host smart-5b891f8e-ab2b-443a-b103-1abdb9cde2c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890574789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3890574789
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3390340073
Short name T306
Test name
Test status
Simulation time 724345557 ps
CPU time 9.43 seconds
Started Jul 20 04:38:28 PM PDT 24
Finished Jul 20 04:38:40 PM PDT 24
Peak memory 225428 kb
Host smart-21f9479a-271f-43f3-8b9b-ab6ab5320358
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390340073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3390340073
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.55633334
Short name T623
Test name
Test status
Simulation time 356417734 ps
CPU time 14.7 seconds
Started Jul 20 04:38:17 PM PDT 24
Finished Jul 20 04:38:34 PM PDT 24
Peak memory 217800 kb
Host smart-a2cb2362-45b6-40ca-a81e-0f8b0a855f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55633334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.55633334
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1060236502
Short name T215
Test name
Test status
Simulation time 70768351 ps
CPU time 4.54 seconds
Started Jul 20 04:38:17 PM PDT 24
Finished Jul 20 04:38:24 PM PDT 24
Peak memory 217156 kb
Host smart-0ea49d6b-670f-4885-be51-e90e1c01f91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060236502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1060236502
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.560016594
Short name T729
Test name
Test status
Simulation time 818318976 ps
CPU time 22.43 seconds
Started Jul 20 04:38:13 PM PDT 24
Finished Jul 20 04:38:37 PM PDT 24
Peak memory 250456 kb
Host smart-8312e67c-cf44-4886-b026-5a0ad2ebb0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560016594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.560016594
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3724434605
Short name T453
Test name
Test status
Simulation time 272549541 ps
CPU time 6.35 seconds
Started Jul 20 04:38:14 PM PDT 24
Finished Jul 20 04:38:21 PM PDT 24
Peak memory 245548 kb
Host smart-3a75e77f-d833-4f78-92aa-2a28d31e4cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724434605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3724434605
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.4294032653
Short name T13
Test name
Test status
Simulation time 67768780 ps
CPU time 0.79 seconds
Started Jul 20 04:38:13 PM PDT 24
Finished Jul 20 04:38:15 PM PDT 24
Peak memory 208220 kb
Host smart-4d7e9f5b-fb2e-42d6-bdcb-9fb70dd55b47
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294032653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.4294032653
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3063423905
Short name T394
Test name
Test status
Simulation time 14236259 ps
CPU time 0.95 seconds
Started Jul 20 04:38:32 PM PDT 24
Finished Jul 20 04:38:34 PM PDT 24
Peak memory 208312 kb
Host smart-7e977cee-bc0c-4a19-bf31-eae8621270e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063423905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3063423905
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1184923006
Short name T361
Test name
Test status
Simulation time 185022374 ps
CPU time 9.49 seconds
Started Jul 20 04:38:26 PM PDT 24
Finished Jul 20 04:38:37 PM PDT 24
Peak memory 217772 kb
Host smart-8c4ef1e9-159c-4d4d-ab42-097ff1992048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184923006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1184923006
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2588031228
Short name T25
Test name
Test status
Simulation time 3065593902 ps
CPU time 19.96 seconds
Started Jul 20 04:38:30 PM PDT 24
Finished Jul 20 04:38:52 PM PDT 24
Peak memory 217172 kb
Host smart-5189abdf-4764-4a07-92e4-002f770ea825
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588031228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2588031228
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1124461964
Short name T731
Test name
Test status
Simulation time 244065671 ps
CPU time 2.56 seconds
Started Jul 20 04:38:28 PM PDT 24
Finished Jul 20 04:38:34 PM PDT 24
Peak memory 221756 kb
Host smart-d95957c3-381e-4d09-a4d3-4a199e6553b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124461964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1124461964
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3597345478
Short name T472
Test name
Test status
Simulation time 500750936 ps
CPU time 10.75 seconds
Started Jul 20 04:38:29 PM PDT 24
Finished Jul 20 04:38:42 PM PDT 24
Peak memory 218380 kb
Host smart-89126373-5967-45a0-883f-0dd9bbfed572
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597345478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3597345478
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1357386100
Short name T475
Test name
Test status
Simulation time 2377821452 ps
CPU time 10.57 seconds
Started Jul 20 04:38:28 PM PDT 24
Finished Jul 20 04:38:41 PM PDT 24
Peak memory 225488 kb
Host smart-07478160-4010-4c48-82a0-a2990dac6ab2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357386100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1357386100
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.350166096
Short name T484
Test name
Test status
Simulation time 298871664 ps
CPU time 7.71 seconds
Started Jul 20 04:38:29 PM PDT 24
Finished Jul 20 04:38:39 PM PDT 24
Peak memory 225676 kb
Host smart-3bf9ca50-f5b5-4df1-82f3-5c05cd929324
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350166096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.350166096
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2172956968
Short name T316
Test name
Test status
Simulation time 328300499 ps
CPU time 9.13 seconds
Started Jul 20 04:38:25 PM PDT 24
Finished Jul 20 04:38:35 PM PDT 24
Peak memory 225544 kb
Host smart-43516fb5-250c-49c9-8f36-a4483dd36d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172956968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2172956968
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2109967603
Short name T501
Test name
Test status
Simulation time 153309902 ps
CPU time 1.82 seconds
Started Jul 20 04:38:28 PM PDT 24
Finished Jul 20 04:38:32 PM PDT 24
Peak memory 213556 kb
Host smart-0cc198f5-9b65-4e53-899c-123bf405f430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109967603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2109967603
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.987591733
Short name T276
Test name
Test status
Simulation time 1333175492 ps
CPU time 29.78 seconds
Started Jul 20 04:38:27 PM PDT 24
Finished Jul 20 04:38:59 PM PDT 24
Peak memory 246964 kb
Host smart-431a6321-5856-4386-97ec-e8d91ee106d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987591733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.987591733
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.4249146648
Short name T379
Test name
Test status
Simulation time 166046861 ps
CPU time 6.68 seconds
Started Jul 20 04:38:29 PM PDT 24
Finished Jul 20 04:38:38 PM PDT 24
Peak memory 250364 kb
Host smart-8b88bb24-6980-46e1-bf45-16f12a0abee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249146648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.4249146648
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.391612332
Short name T811
Test name
Test status
Simulation time 973051579 ps
CPU time 27.53 seconds
Started Jul 20 04:38:28 PM PDT 24
Finished Jul 20 04:38:58 PM PDT 24
Peak memory 226800 kb
Host smart-c9f8a05e-a4e8-4d47-aafa-93433eae9e9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391612332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.391612332
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.442170848
Short name T223
Test name
Test status
Simulation time 152572765 ps
CPU time 0.92 seconds
Started Jul 20 04:38:29 PM PDT 24
Finished Jul 20 04:38:33 PM PDT 24
Peak memory 211284 kb
Host smart-77321fde-6a80-4250-9e99-f47520cdc4c2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442170848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.442170848
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1287810884
Short name T272
Test name
Test status
Simulation time 44853987 ps
CPU time 1.03 seconds
Started Jul 20 04:36:55 PM PDT 24
Finished Jul 20 04:36:58 PM PDT 24
Peak memory 208340 kb
Host smart-260db6ce-e14a-4658-b5a8-102699d609f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287810884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1287810884
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2485896337
Short name T410
Test name
Test status
Simulation time 306183256 ps
CPU time 14.29 seconds
Started Jul 20 04:36:51 PM PDT 24
Finished Jul 20 04:37:06 PM PDT 24
Peak memory 217760 kb
Host smart-80319cd5-1c45-41c6-8dd9-2101fec7f001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485896337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2485896337
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.118524413
Short name T178
Test name
Test status
Simulation time 261967602 ps
CPU time 4.35 seconds
Started Jul 20 04:36:55 PM PDT 24
Finished Jul 20 04:37:01 PM PDT 24
Peak memory 216692 kb
Host smart-d248dc56-92ea-4e89-9725-53fe9f35e77f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118524413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.118524413
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2629554187
Short name T11
Test name
Test status
Simulation time 5830219164 ps
CPU time 43.05 seconds
Started Jul 20 04:36:53 PM PDT 24
Finished Jul 20 04:37:37 PM PDT 24
Peak memory 218592 kb
Host smart-6eeac561-47d5-42df-bcb4-79136a70105f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629554187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2629554187
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.59010613
Short name T776
Test name
Test status
Simulation time 188824950 ps
CPU time 1.33 seconds
Started Jul 20 04:36:54 PM PDT 24
Finished Jul 20 04:36:58 PM PDT 24
Peak memory 217148 kb
Host smart-1d739fe3-c9b1-4ca3-8412-e707ac00a0c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59010613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.59010613
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.711979021
Short name T582
Test name
Test status
Simulation time 1482491442 ps
CPU time 14.62 seconds
Started Jul 20 04:37:01 PM PDT 24
Finished Jul 20 04:37:16 PM PDT 24
Peak memory 223748 kb
Host smart-289ad98e-01f5-4725-933c-41cd7074fa50
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711979021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
prog_failure.711979021
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.398872495
Short name T800
Test name
Test status
Simulation time 4300968317 ps
CPU time 16.55 seconds
Started Jul 20 04:36:56 PM PDT 24
Finished Jul 20 04:37:14 PM PDT 24
Peak memory 217084 kb
Host smart-fbf31d63-1522-409d-bb63-39e3804d743c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398872495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_regwen_during_op.398872495
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2228554143
Short name T654
Test name
Test status
Simulation time 317751614 ps
CPU time 4.71 seconds
Started Jul 20 04:36:54 PM PDT 24
Finished Jul 20 04:37:00 PM PDT 24
Peak memory 217096 kb
Host smart-dfadefc5-38e9-4407-b63a-130971669103
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228554143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2228554143
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2555465245
Short name T698
Test name
Test status
Simulation time 18957917356 ps
CPU time 72.56 seconds
Started Jul 20 04:36:58 PM PDT 24
Finished Jul 20 04:38:12 PM PDT 24
Peak memory 282632 kb
Host smart-77a7a78b-6784-4220-b534-aa033b504a7b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555465245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2555465245
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.344091472
Short name T249
Test name
Test status
Simulation time 2649512784 ps
CPU time 12.42 seconds
Started Jul 20 04:36:54 PM PDT 24
Finished Jul 20 04:37:09 PM PDT 24
Peak memory 246860 kb
Host smart-816a8a0a-c055-40a8-b0a1-799dbf12d86c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344091472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.344091472
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1043365174
Short name T592
Test name
Test status
Simulation time 158293081 ps
CPU time 2.61 seconds
Started Jul 20 04:36:51 PM PDT 24
Finished Jul 20 04:36:54 PM PDT 24
Peak memory 217668 kb
Host smart-5896edce-7d23-467b-ac96-4fdfdf7e9195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043365174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1043365174
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.709196731
Short name T483
Test name
Test status
Simulation time 6501324667 ps
CPU time 22.02 seconds
Started Jul 20 04:36:55 PM PDT 24
Finished Jul 20 04:37:19 PM PDT 24
Peak memory 217168 kb
Host smart-395c786f-3ef1-40b8-8cec-9d5b3dbd5a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709196731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.709196731
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1341330607
Short name T93
Test name
Test status
Simulation time 2322790732 ps
CPU time 40.18 seconds
Started Jul 20 04:36:58 PM PDT 24
Finished Jul 20 04:37:40 PM PDT 24
Peak memory 270728 kb
Host smart-044220b0-28a0-41d1-97c4-65128fc432c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341330607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1341330607
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3739580151
Short name T428
Test name
Test status
Simulation time 1926160736 ps
CPU time 16.49 seconds
Started Jul 20 04:36:56 PM PDT 24
Finished Jul 20 04:37:14 PM PDT 24
Peak memory 217568 kb
Host smart-b9dfea9c-9e19-4a7e-bfa1-77d9cc1475c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739580151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3739580151
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3809593342
Short name T320
Test name
Test status
Simulation time 336499674 ps
CPU time 9.88 seconds
Started Jul 20 04:36:58 PM PDT 24
Finished Jul 20 04:37:10 PM PDT 24
Peak memory 225172 kb
Host smart-41733459-0d07-4d09-8ffd-479cd54c33fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809593342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3
809593342
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2392764184
Short name T335
Test name
Test status
Simulation time 677980269 ps
CPU time 9.64 seconds
Started Jul 20 04:36:47 PM PDT 24
Finished Jul 20 04:36:58 PM PDT 24
Peak memory 217764 kb
Host smart-7fdfdc1e-8c5f-4371-ad18-d1b88cccda93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392764184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2392764184
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.831599302
Short name T503
Test name
Test status
Simulation time 131936991 ps
CPU time 5.82 seconds
Started Jul 20 04:36:46 PM PDT 24
Finished Jul 20 04:36:53 PM PDT 24
Peak memory 222796 kb
Host smart-87914f46-0ccb-4578-9c5b-c8945316497c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831599302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.831599302
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3163759900
Short name T155
Test name
Test status
Simulation time 478881902 ps
CPU time 25.53 seconds
Started Jul 20 04:36:49 PM PDT 24
Finished Jul 20 04:37:16 PM PDT 24
Peak memory 250400 kb
Host smart-58217c78-a4ee-4589-95b4-34c19302a875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163759900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3163759900
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3546857071
Short name T772
Test name
Test status
Simulation time 208160530 ps
CPU time 8.12 seconds
Started Jul 20 04:36:52 PM PDT 24
Finished Jul 20 04:37:01 PM PDT 24
Peak memory 250440 kb
Host smart-02d88b38-9210-4ee0-b7a5-7d66953e2d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546857071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3546857071
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1813444077
Short name T360
Test name
Test status
Simulation time 3713884718 ps
CPU time 89.18 seconds
Started Jul 20 04:36:56 PM PDT 24
Finished Jul 20 04:38:27 PM PDT 24
Peak memory 273384 kb
Host smart-c9e915ff-ac79-4b52-89f6-5f2630e3b258
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813444077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1813444077
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.4293034989
Short name T69
Test name
Test status
Simulation time 39524828 ps
CPU time 1 seconds
Started Jul 20 04:36:49 PM PDT 24
Finished Jul 20 04:36:52 PM PDT 24
Peak memory 211332 kb
Host smart-535ae83c-fbcb-4145-8663-4b6d2cb772f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293034989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.4293034989
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1113756061
Short name T580
Test name
Test status
Simulation time 35089488 ps
CPU time 1 seconds
Started Jul 20 04:38:27 PM PDT 24
Finished Jul 20 04:38:31 PM PDT 24
Peak memory 208360 kb
Host smart-4e2d040f-b21b-4cf1-b252-880d600ef436
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113756061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1113756061
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.4736906
Short name T260
Test name
Test status
Simulation time 261921195 ps
CPU time 10.07 seconds
Started Jul 20 04:38:24 PM PDT 24
Finished Jul 20 04:38:35 PM PDT 24
Peak memory 217636 kb
Host smart-4cd106e8-91c1-47b6-ada5-2836cb48d97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4736906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.4736906
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2602780333
Short name T493
Test name
Test status
Simulation time 3397240832 ps
CPU time 13.17 seconds
Started Jul 20 04:38:25 PM PDT 24
Finished Jul 20 04:38:39 PM PDT 24
Peak memory 217200 kb
Host smart-4377817c-9023-4e56-aaca-7eb049f1be97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602780333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2602780333
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.715072869
Short name T631
Test name
Test status
Simulation time 204538591 ps
CPU time 3.25 seconds
Started Jul 20 04:38:25 PM PDT 24
Finished Jul 20 04:38:29 PM PDT 24
Peak memory 217688 kb
Host smart-4a9fd031-76e6-45a5-8216-4b0189b7bfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715072869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.715072869
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1863367687
Short name T689
Test name
Test status
Simulation time 1486238044 ps
CPU time 22.34 seconds
Started Jul 20 04:38:26 PM PDT 24
Finished Jul 20 04:38:49 PM PDT 24
Peak memory 219460 kb
Host smart-1f14ab08-ed90-42fb-bc2a-93bf47b37c8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863367687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1863367687
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2248645023
Short name T170
Test name
Test status
Simulation time 911460743 ps
CPU time 17.85 seconds
Started Jul 20 04:38:27 PM PDT 24
Finished Jul 20 04:38:48 PM PDT 24
Peak memory 217712 kb
Host smart-8ff67fef-b0f1-42c4-abff-80ebf1d5cdd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248645023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2248645023
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2330582941
Short name T165
Test name
Test status
Simulation time 814054057 ps
CPU time 9.24 seconds
Started Jul 20 04:38:27 PM PDT 24
Finished Jul 20 04:38:38 PM PDT 24
Peak memory 225408 kb
Host smart-6a961059-8169-48eb-a974-84e90ed72642
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330582941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2330582941
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.932628095
Short name T518
Test name
Test status
Simulation time 4139676413 ps
CPU time 7.91 seconds
Started Jul 20 04:38:27 PM PDT 24
Finished Jul 20 04:38:36 PM PDT 24
Peak memory 217828 kb
Host smart-46f6acc3-3d96-4259-87f2-441f70868db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932628095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.932628095
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1455462697
Short name T268
Test name
Test status
Simulation time 38274859 ps
CPU time 1.67 seconds
Started Jul 20 04:38:31 PM PDT 24
Finished Jul 20 04:38:34 PM PDT 24
Peak memory 217104 kb
Host smart-ccdac5ec-5e07-4609-9994-cb056a748e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455462697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1455462697
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3729991732
Short name T264
Test name
Test status
Simulation time 286104448 ps
CPU time 27.61 seconds
Started Jul 20 04:38:27 PM PDT 24
Finished Jul 20 04:38:57 PM PDT 24
Peak memory 250496 kb
Host smart-1d6701a1-b8ae-4ade-831a-ef411a26e1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729991732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3729991732
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3520982059
Short name T691
Test name
Test status
Simulation time 65761529 ps
CPU time 3.16 seconds
Started Jul 20 04:38:25 PM PDT 24
Finished Jul 20 04:38:29 PM PDT 24
Peak memory 225900 kb
Host smart-bba25292-d440-4ba0-a611-05d1686427fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520982059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3520982059
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3793055759
Short name T803
Test name
Test status
Simulation time 5041302335 ps
CPU time 85.4 seconds
Started Jul 20 04:38:25 PM PDT 24
Finished Jul 20 04:39:51 PM PDT 24
Peak memory 280820 kb
Host smart-bc87a641-74aa-4c58-b789-bd77cf7e2604
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793055759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3793055759
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3242875964
Short name T431
Test name
Test status
Simulation time 20430515 ps
CPU time 1.03 seconds
Started Jul 20 04:38:26 PM PDT 24
Finished Jul 20 04:38:28 PM PDT 24
Peak memory 217244 kb
Host smart-8b0aab90-2640-440a-83e7-2e2e656d13b0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242875964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3242875964
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2860322703
Short name T779
Test name
Test status
Simulation time 97240272 ps
CPU time 1 seconds
Started Jul 20 04:38:26 PM PDT 24
Finished Jul 20 04:38:28 PM PDT 24
Peak memory 208296 kb
Host smart-78594047-a7a4-46cb-8f5f-ffb1205166df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860322703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2860322703
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.54538357
Short name T87
Test name
Test status
Simulation time 540621662 ps
CPU time 15.32 seconds
Started Jul 20 04:38:28 PM PDT 24
Finished Jul 20 04:38:45 PM PDT 24
Peak memory 225496 kb
Host smart-ed78995a-68c3-4af7-a0bc-607c450d4e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54538357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.54538357
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1208201132
Short name T30
Test name
Test status
Simulation time 1623937737 ps
CPU time 3.81 seconds
Started Jul 20 04:38:28 PM PDT 24
Finished Jul 20 04:38:35 PM PDT 24
Peak memory 216528 kb
Host smart-280e6649-1ffa-4518-a79a-7f78d9eda71b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208201132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1208201132
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.616514075
Short name T321
Test name
Test status
Simulation time 71599911 ps
CPU time 3.21 seconds
Started Jul 20 04:38:24 PM PDT 24
Finished Jul 20 04:38:28 PM PDT 24
Peak memory 217736 kb
Host smart-d83f1e14-7d86-46ec-9c2c-edc5358fed6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616514075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.616514075
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2036607475
Short name T543
Test name
Test status
Simulation time 1846068461 ps
CPU time 19.15 seconds
Started Jul 20 04:38:30 PM PDT 24
Finished Jul 20 04:38:51 PM PDT 24
Peak memory 219408 kb
Host smart-b7db2aac-345d-46b2-91e6-b6cd399a26ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036607475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2036607475
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3018293869
Short name T565
Test name
Test status
Simulation time 1581463278 ps
CPU time 10.44 seconds
Started Jul 20 04:38:28 PM PDT 24
Finished Jul 20 04:38:41 PM PDT 24
Peak memory 217712 kb
Host smart-8c78261d-4764-45dd-866f-f54268a239d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018293869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3018293869
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2852071218
Short name T620
Test name
Test status
Simulation time 660726247 ps
CPU time 11.61 seconds
Started Jul 20 04:38:26 PM PDT 24
Finished Jul 20 04:38:39 PM PDT 24
Peak memory 217572 kb
Host smart-d6451aae-6424-42c6-9d2b-aeab734da712
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852071218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2852071218
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.838861097
Short name T703
Test name
Test status
Simulation time 1492046993 ps
CPU time 14.17 seconds
Started Jul 20 04:38:26 PM PDT 24
Finished Jul 20 04:38:42 PM PDT 24
Peak memory 217832 kb
Host smart-cbc64420-afa1-405d-b9e3-46d692790ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838861097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.838861097
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3907220896
Short name T649
Test name
Test status
Simulation time 16741600 ps
CPU time 1.42 seconds
Started Jul 20 04:38:26 PM PDT 24
Finished Jul 20 04:38:28 PM PDT 24
Peak memory 222228 kb
Host smart-8369fb4c-c830-4e3e-9c49-08f83c2fcbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907220896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3907220896
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.4032623863
Short name T345
Test name
Test status
Simulation time 314063099 ps
CPU time 17.67 seconds
Started Jul 20 04:38:26 PM PDT 24
Finished Jul 20 04:38:46 PM PDT 24
Peak memory 250412 kb
Host smart-c249aa37-7bed-4208-9234-405852bc155e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032623863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.4032623863
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3376725941
Short name T554
Test name
Test status
Simulation time 526565172 ps
CPU time 7.81 seconds
Started Jul 20 04:38:31 PM PDT 24
Finished Jul 20 04:38:40 PM PDT 24
Peak memory 250480 kb
Host smart-4914061e-288f-424e-a437-efaffe4a7fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376725941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3376725941
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.863737837
Short name T256
Test name
Test status
Simulation time 8526528150 ps
CPU time 146.41 seconds
Started Jul 20 04:38:28 PM PDT 24
Finished Jul 20 04:40:57 PM PDT 24
Peak memory 250484 kb
Host smart-3ac7d7d9-3e1e-4846-b300-41b3c11fa15e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863737837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.863737837
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1656616846
Short name T43
Test name
Test status
Simulation time 11178725 ps
CPU time 0.8 seconds
Started Jul 20 04:38:28 PM PDT 24
Finished Jul 20 04:38:32 PM PDT 24
Peak memory 208248 kb
Host smart-fb72f9b4-0934-4b7b-8267-18d81aa33f1d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656616846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1656616846
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.474508269
Short name T372
Test name
Test status
Simulation time 21733066 ps
CPU time 1.31 seconds
Started Jul 20 04:38:28 PM PDT 24
Finished Jul 20 04:38:32 PM PDT 24
Peak memory 208492 kb
Host smart-6a1c9841-6d16-493f-8bd2-43eab388c2a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474508269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.474508269
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2363843122
Short name T834
Test name
Test status
Simulation time 665852617 ps
CPU time 15.55 seconds
Started Jul 20 04:38:26 PM PDT 24
Finished Jul 20 04:38:43 PM PDT 24
Peak memory 217592 kb
Host smart-89625db1-ad82-4a6e-9531-cec5bad0509c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363843122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2363843122
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.755354158
Short name T59
Test name
Test status
Simulation time 506492294 ps
CPU time 2.57 seconds
Started Jul 20 04:38:28 PM PDT 24
Finished Jul 20 04:38:33 PM PDT 24
Peak memory 217084 kb
Host smart-666d0e55-49e5-400e-a3d3-5c9959d5b0cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755354158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.755354158
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.68604783
Short name T522
Test name
Test status
Simulation time 250886005 ps
CPU time 3.2 seconds
Started Jul 20 04:38:26 PM PDT 24
Finished Jul 20 04:38:30 PM PDT 24
Peak memory 217696 kb
Host smart-4656aa5b-5dd2-4712-bccc-8a719fe18ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68604783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.68604783
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3245332939
Short name T34
Test name
Test status
Simulation time 1356304472 ps
CPU time 14.01 seconds
Started Jul 20 04:38:28 PM PDT 24
Finished Jul 20 04:38:45 PM PDT 24
Peak memory 218440 kb
Host smart-74c3b141-46af-489a-a8f0-8f8f60e123f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245332939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3245332939
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.583011784
Short name T286
Test name
Test status
Simulation time 913229070 ps
CPU time 9.06 seconds
Started Jul 20 04:38:25 PM PDT 24
Finished Jul 20 04:38:34 PM PDT 24
Peak memory 217792 kb
Host smart-1e3adcd5-966b-44ea-950e-1e7d995c0dfe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583011784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.583011784
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.3306138074
Short name T509
Test name
Test status
Simulation time 213620816 ps
CPU time 8.48 seconds
Started Jul 20 04:38:23 PM PDT 24
Finished Jul 20 04:38:32 PM PDT 24
Peak memory 225432 kb
Host smart-46c25509-0e86-4cac-bdb2-0c9d4cb807d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306138074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
3306138074
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.4114245297
Short name T57
Test name
Test status
Simulation time 298260749 ps
CPU time 11.07 seconds
Started Jul 20 04:38:30 PM PDT 24
Finished Jul 20 04:38:43 PM PDT 24
Peak memory 225480 kb
Host smart-d0e7ab15-dc01-4723-8f6d-5354e015ea4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114245297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.4114245297
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2461928257
Short name T715
Test name
Test status
Simulation time 103307492 ps
CPU time 3.31 seconds
Started Jul 20 04:38:29 PM PDT 24
Finished Jul 20 04:38:35 PM PDT 24
Peak memory 217120 kb
Host smart-ecabaf69-aa17-43e1-ab96-1bdb9ad76a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461928257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2461928257
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1482431281
Short name T247
Test name
Test status
Simulation time 545524704 ps
CPU time 26.49 seconds
Started Jul 20 04:38:27 PM PDT 24
Finished Jul 20 04:38:56 PM PDT 24
Peak memory 250388 kb
Host smart-1c7cdb01-d306-4982-9a13-3469e181ab62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482431281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1482431281
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.90646499
Short name T329
Test name
Test status
Simulation time 91280869 ps
CPU time 6.28 seconds
Started Jul 20 04:38:28 PM PDT 24
Finished Jul 20 04:38:37 PM PDT 24
Peak memory 250204 kb
Host smart-223e07b5-e3a3-4bba-9e0d-ea276f926856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90646499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.90646499
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3864542023
Short name T33
Test name
Test status
Simulation time 8698420863 ps
CPU time 125.21 seconds
Started Jul 20 04:38:28 PM PDT 24
Finished Jul 20 04:40:36 PM PDT 24
Peak memory 258796 kb
Host smart-c1f83e11-ee6b-4053-8b3a-ec5197e87993
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864542023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3864542023
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2064094062
Short name T146
Test name
Test status
Simulation time 23312556872 ps
CPU time 796.06 seconds
Started Jul 20 04:38:31 PM PDT 24
Finished Jul 20 04:51:49 PM PDT 24
Peak memory 285008 kb
Host smart-128222cb-443b-486a-a5f0-dc368a92df3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2064094062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.2064094062
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1060289798
Short name T395
Test name
Test status
Simulation time 13197982 ps
CPU time 0.99 seconds
Started Jul 20 04:38:24 PM PDT 24
Finished Jul 20 04:38:25 PM PDT 24
Peak memory 208340 kb
Host smart-b3377be2-4f78-4af1-9e4a-f6b538506986
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060289798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1060289798
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.342804921
Short name T489
Test name
Test status
Simulation time 39972261 ps
CPU time 1.08 seconds
Started Jul 20 04:38:35 PM PDT 24
Finished Jul 20 04:38:38 PM PDT 24
Peak memory 208404 kb
Host smart-8473c8c4-98ad-4d33-b8c9-2602e54c43b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342804921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.342804921
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3743488304
Short name T684
Test name
Test status
Simulation time 2229691777 ps
CPU time 11.25 seconds
Started Jul 20 04:38:31 PM PDT 24
Finished Jul 20 04:38:44 PM PDT 24
Peak memory 217816 kb
Host smart-2e3486f1-5765-4dde-b6a9-f3a4a397bfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743488304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3743488304
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.54252198
Short name T492
Test name
Test status
Simulation time 117471941 ps
CPU time 1.87 seconds
Started Jul 20 04:38:37 PM PDT 24
Finished Jul 20 04:38:42 PM PDT 24
Peak memory 216992 kb
Host smart-18b020fe-ff12-4240-820d-25c67b709ec7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54252198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.54252198
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.4053284233
Short name T835
Test name
Test status
Simulation time 622481172 ps
CPU time 4.18 seconds
Started Jul 20 04:38:28 PM PDT 24
Finished Jul 20 04:38:35 PM PDT 24
Peak memory 222228 kb
Host smart-25eebed7-11a6-4d66-8777-ea664becbd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053284233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.4053284233
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1516050724
Short name T176
Test name
Test status
Simulation time 231055588 ps
CPU time 8.82 seconds
Started Jul 20 04:38:39 PM PDT 24
Finished Jul 20 04:38:50 PM PDT 24
Peak memory 217712 kb
Host smart-f5d734bb-4f8d-4ab1-9173-198278193eb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516050724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1516050724
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1607949204
Short name T600
Test name
Test status
Simulation time 299693591 ps
CPU time 11.48 seconds
Started Jul 20 04:38:35 PM PDT 24
Finished Jul 20 04:38:49 PM PDT 24
Peak memory 225476 kb
Host smart-6731666d-bece-4fef-a86b-a09d36d0a7f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607949204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1607949204
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.4051626419
Short name T52
Test name
Test status
Simulation time 726017243 ps
CPU time 17.21 seconds
Started Jul 20 04:38:36 PM PDT 24
Finished Jul 20 04:38:56 PM PDT 24
Peak memory 217756 kb
Host smart-af88965f-adaa-476d-a76e-e23e3efb1295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051626419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.4051626419
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3416207259
Short name T751
Test name
Test status
Simulation time 120931147 ps
CPU time 2.88 seconds
Started Jul 20 04:38:30 PM PDT 24
Finished Jul 20 04:38:35 PM PDT 24
Peak memory 217100 kb
Host smart-d4dc796e-836b-43b3-93a5-a17ffdf5e3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416207259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3416207259
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3523076472
Short name T578
Test name
Test status
Simulation time 685677426 ps
CPU time 26.33 seconds
Started Jul 20 04:38:29 PM PDT 24
Finished Jul 20 04:38:58 PM PDT 24
Peak memory 250440 kb
Host smart-e22cbfe4-c2d7-4d50-803c-0be6d3e635ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523076472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3523076472
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.452448304
Short name T607
Test name
Test status
Simulation time 1407296764 ps
CPU time 8.69 seconds
Started Jul 20 04:38:29 PM PDT 24
Finished Jul 20 04:38:40 PM PDT 24
Peak memory 250696 kb
Host smart-547eab2d-7e46-4802-8644-72cad0f38c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452448304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.452448304
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2539749797
Short name T831
Test name
Test status
Simulation time 23280557759 ps
CPU time 180.42 seconds
Started Jul 20 04:38:33 PM PDT 24
Finished Jul 20 04:41:34 PM PDT 24
Peak memory 275248 kb
Host smart-6318c927-5990-4869-94c7-73179918e25d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539749797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2539749797
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.480269229
Short name T706
Test name
Test status
Simulation time 24021265 ps
CPU time 1.08 seconds
Started Jul 20 04:38:26 PM PDT 24
Finished Jul 20 04:38:29 PM PDT 24
Peak memory 211356 kb
Host smart-1bb77316-7d9f-4b52-8aa1-891f44c3371e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480269229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.480269229
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2836642259
Short name T553
Test name
Test status
Simulation time 13733904 ps
CPU time 1.02 seconds
Started Jul 20 04:38:34 PM PDT 24
Finished Jul 20 04:38:37 PM PDT 24
Peak memory 208352 kb
Host smart-52a530a6-821d-4687-8fa0-c7c4f8d07e8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836642259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2836642259
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2548986927
Short name T712
Test name
Test status
Simulation time 2206555519 ps
CPU time 10.42 seconds
Started Jul 20 04:38:35 PM PDT 24
Finished Jul 20 04:38:47 PM PDT 24
Peak memory 217768 kb
Host smart-7368855b-76fd-4fc7-bdc1-aff41b74af52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548986927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2548986927
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.838085389
Short name T550
Test name
Test status
Simulation time 2740890780 ps
CPU time 5.4 seconds
Started Jul 20 04:38:38 PM PDT 24
Finished Jul 20 04:38:46 PM PDT 24
Peak memory 217068 kb
Host smart-fc7366d4-b425-4c62-9ac6-fabf38183688
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838085389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.838085389
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.275529781
Short name T533
Test name
Test status
Simulation time 146741460 ps
CPU time 2.46 seconds
Started Jul 20 04:38:39 PM PDT 24
Finished Jul 20 04:38:43 PM PDT 24
Peak memory 221668 kb
Host smart-469d616f-cf1f-47bd-898c-536ea8a81967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275529781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.275529781
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3855007948
Short name T525
Test name
Test status
Simulation time 396485548 ps
CPU time 14.91 seconds
Started Jul 20 04:38:36 PM PDT 24
Finished Jul 20 04:38:53 PM PDT 24
Peak memory 225528 kb
Host smart-0bff6fc2-8e11-4e83-b830-5a68e977a253
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855007948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3855007948
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.58203263
Short name T806
Test name
Test status
Simulation time 2576578848 ps
CPU time 15.89 seconds
Started Jul 20 04:38:37 PM PDT 24
Finished Jul 20 04:38:55 PM PDT 24
Peak memory 218336 kb
Host smart-25cb7a30-7819-4048-8863-74af74488c19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58203263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_dig
est.58203263
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.26141549
Short name T622
Test name
Test status
Simulation time 537088432 ps
CPU time 13.55 seconds
Started Jul 20 04:38:37 PM PDT 24
Finished Jul 20 04:38:53 PM PDT 24
Peak memory 225428 kb
Host smart-4089a0da-d299-4c23-a8c7-6334a39e6fdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26141549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.26141549
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.984903008
Short name T704
Test name
Test status
Simulation time 284375010 ps
CPU time 6.92 seconds
Started Jul 20 04:38:36 PM PDT 24
Finished Jul 20 04:38:45 PM PDT 24
Peak memory 217808 kb
Host smart-836f35b5-1524-4543-9baf-6cecbebea502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984903008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.984903008
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2556837985
Short name T349
Test name
Test status
Simulation time 262708332 ps
CPU time 2.7 seconds
Started Jul 20 04:38:37 PM PDT 24
Finished Jul 20 04:38:43 PM PDT 24
Peak memory 213724 kb
Host smart-234a004a-c2d4-4e3d-ad25-e48974117af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556837985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2556837985
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.3165365034
Short name T511
Test name
Test status
Simulation time 318809426 ps
CPU time 33.94 seconds
Started Jul 20 04:38:36 PM PDT 24
Finished Jul 20 04:39:13 PM PDT 24
Peak memory 250428 kb
Host smart-d512bf57-8fec-4848-a2ea-57e36661c4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165365034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3165365034
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.245852802
Short name T91
Test name
Test status
Simulation time 100718177 ps
CPU time 6.02 seconds
Started Jul 20 04:38:35 PM PDT 24
Finished Jul 20 04:38:43 PM PDT 24
Peak memory 246508 kb
Host smart-67678e90-9e3f-4507-ae6f-d7a53e7aa529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245852802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.245852802
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3626216010
Short name T536
Test name
Test status
Simulation time 10025137085 ps
CPU time 315.83 seconds
Started Jul 20 04:38:37 PM PDT 24
Finished Jul 20 04:43:55 PM PDT 24
Peak memory 309764 kb
Host smart-4f5155e7-dcf1-4cf8-b51b-c52db138b116
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626216010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3626216010
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2432716083
Short name T38
Test name
Test status
Simulation time 34908729 ps
CPU time 0.98 seconds
Started Jul 20 04:38:34 PM PDT 24
Finished Jul 20 04:38:37 PM PDT 24
Peak memory 211292 kb
Host smart-a9c7fa20-9ba2-424a-9989-f7ca082877ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432716083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2432716083
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.841904191
Short name T529
Test name
Test status
Simulation time 35274517 ps
CPU time 1.18 seconds
Started Jul 20 04:38:37 PM PDT 24
Finished Jul 20 04:38:41 PM PDT 24
Peak memory 208420 kb
Host smart-48b708d7-dd5a-417b-8bdc-d0cb434166b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841904191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.841904191
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3442916756
Short name T507
Test name
Test status
Simulation time 320904272 ps
CPU time 13.05 seconds
Started Jul 20 04:38:38 PM PDT 24
Finished Jul 20 04:38:54 PM PDT 24
Peak memory 217692 kb
Host smart-abbe11fd-db1a-4fd3-8e4f-becbcbc45d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442916756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3442916756
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.677739901
Short name T187
Test name
Test status
Simulation time 287723413 ps
CPU time 2.43 seconds
Started Jul 20 04:38:36 PM PDT 24
Finished Jul 20 04:38:41 PM PDT 24
Peak memory 216572 kb
Host smart-e29f9fac-b8a1-4e34-a96e-1f4db081355a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677739901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.677739901
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.253635581
Short name T314
Test name
Test status
Simulation time 55147675 ps
CPU time 2.97 seconds
Started Jul 20 04:38:35 PM PDT 24
Finished Jul 20 04:38:39 PM PDT 24
Peak memory 217688 kb
Host smart-6f85a0c5-79dd-41a2-9315-ab2dcd7f4acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253635581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.253635581
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3530004830
Short name T338
Test name
Test status
Simulation time 261593730 ps
CPU time 9.56 seconds
Started Jul 20 04:38:34 PM PDT 24
Finished Jul 20 04:38:44 PM PDT 24
Peak memory 217672 kb
Host smart-3a49796f-018f-406d-8fbb-2aebfedd70c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530004830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3530004830
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.601562904
Short name T342
Test name
Test status
Simulation time 457117415 ps
CPU time 6.71 seconds
Started Jul 20 04:38:37 PM PDT 24
Finished Jul 20 04:38:46 PM PDT 24
Peak memory 225152 kb
Host smart-992a4433-e7be-49aa-9bdd-178ab2265a95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601562904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.601562904
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3649329837
Short name T467
Test name
Test status
Simulation time 251774845 ps
CPU time 11.36 seconds
Started Jul 20 04:38:36 PM PDT 24
Finished Jul 20 04:38:49 PM PDT 24
Peak memory 217764 kb
Host smart-bfced558-7a0c-4c45-8e16-fa943a77a813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649329837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3649329837
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3734208999
Short name T267
Test name
Test status
Simulation time 38888291 ps
CPU time 2.37 seconds
Started Jul 20 04:38:39 PM PDT 24
Finished Jul 20 04:38:43 PM PDT 24
Peak memory 217276 kb
Host smart-f02e3f39-c39c-4602-bb5a-d03247d15bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734208999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3734208999
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2954623289
Short name T669
Test name
Test status
Simulation time 309051906 ps
CPU time 20.39 seconds
Started Jul 20 04:38:34 PM PDT 24
Finished Jul 20 04:38:56 PM PDT 24
Peak memory 250440 kb
Host smart-09acbbde-d66d-488a-8482-686adec104be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954623289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2954623289
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1165526932
Short name T239
Test name
Test status
Simulation time 56575724 ps
CPU time 9.02 seconds
Started Jul 20 04:38:36 PM PDT 24
Finished Jul 20 04:38:48 PM PDT 24
Peak memory 244328 kb
Host smart-869c2ddf-878d-40b4-b932-1d36e1c67126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165526932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1165526932
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1651458181
Short name T549
Test name
Test status
Simulation time 11151905282 ps
CPU time 361.74 seconds
Started Jul 20 04:38:37 PM PDT 24
Finished Jul 20 04:44:42 PM PDT 24
Peak memory 247460 kb
Host smart-5da835f0-a9f3-453a-bf40-1cf6358476aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651458181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1651458181
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.4100727162
Short name T638
Test name
Test status
Simulation time 70592188 ps
CPU time 1.2 seconds
Started Jul 20 04:38:35 PM PDT 24
Finished Jul 20 04:38:38 PM PDT 24
Peak memory 217196 kb
Host smart-d9c3d4be-a5b0-4109-beab-bc07476c6d1a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100727162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.4100727162
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.436965666
Short name T690
Test name
Test status
Simulation time 34358818 ps
CPU time 0.94 seconds
Started Jul 20 04:38:37 PM PDT 24
Finished Jul 20 04:38:40 PM PDT 24
Peak memory 208252 kb
Host smart-18bad081-1cbc-4795-8664-73bfb200cb9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436965666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.436965666
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2624703177
Short name T720
Test name
Test status
Simulation time 279742451 ps
CPU time 9.78 seconds
Started Jul 20 04:38:36 PM PDT 24
Finished Jul 20 04:38:49 PM PDT 24
Peak memory 217752 kb
Host smart-600bccd0-28cb-4218-bc6e-79682cba0e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624703177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2624703177
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.453562044
Short name T412
Test name
Test status
Simulation time 2585996287 ps
CPU time 6.07 seconds
Started Jul 20 04:38:38 PM PDT 24
Finished Jul 20 04:38:46 PM PDT 24
Peak memory 216956 kb
Host smart-ace87831-f9ed-48ee-9fa1-8d9f32ca45ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453562044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.453562044
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1210796963
Short name T233
Test name
Test status
Simulation time 30750675 ps
CPU time 2.23 seconds
Started Jul 20 04:38:36 PM PDT 24
Finished Jul 20 04:38:41 PM PDT 24
Peak memory 217752 kb
Host smart-c7daf5d9-2ea6-4539-8c2f-5c4704961265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210796963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1210796963
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.4043730270
Short name T826
Test name
Test status
Simulation time 388609705 ps
CPU time 14.25 seconds
Started Jul 20 04:38:37 PM PDT 24
Finished Jul 20 04:38:54 PM PDT 24
Peak memory 218584 kb
Host smart-8a7e4cd1-7a6b-4d3d-b679-a6f02f54b06f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043730270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.4043730270
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3252527462
Short name T473
Test name
Test status
Simulation time 220142901 ps
CPU time 8.44 seconds
Started Jul 20 04:38:39 PM PDT 24
Finished Jul 20 04:38:50 PM PDT 24
Peak memory 217800 kb
Host smart-68dbf8f0-c262-4f84-afd7-f70cf8d6fd5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252527462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3252527462
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.4114432909
Short name T816
Test name
Test status
Simulation time 1340119992 ps
CPU time 12.4 seconds
Started Jul 20 04:38:37 PM PDT 24
Finished Jul 20 04:38:52 PM PDT 24
Peak memory 225428 kb
Host smart-28e9cc2e-5164-4a04-8f5f-dd4b56aa81ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114432909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
4114432909
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.2886363645
Short name T53
Test name
Test status
Simulation time 1035034500 ps
CPU time 9.94 seconds
Started Jul 20 04:38:35 PM PDT 24
Finished Jul 20 04:38:47 PM PDT 24
Peak memory 217800 kb
Host smart-0dec4ec4-db2f-4f98-84f1-47e001f3bb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886363645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2886363645
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2293550360
Short name T636
Test name
Test status
Simulation time 15520767 ps
CPU time 1.31 seconds
Started Jul 20 04:38:39 PM PDT 24
Finished Jul 20 04:38:42 PM PDT 24
Peak memory 222440 kb
Host smart-9ae75e6c-a8b5-417a-992a-6e40319283b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293550360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2293550360
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.61348459
Short name T234
Test name
Test status
Simulation time 239145744 ps
CPU time 26.17 seconds
Started Jul 20 04:38:38 PM PDT 24
Finished Jul 20 04:39:07 PM PDT 24
Peak memory 246908 kb
Host smart-9bdbc618-9e1e-4c50-b18e-cfe9e1bf9f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61348459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.61348459
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.238533122
Short name T603
Test name
Test status
Simulation time 248263937 ps
CPU time 7.87 seconds
Started Jul 20 04:38:37 PM PDT 24
Finished Jul 20 04:38:47 PM PDT 24
Peak memory 250480 kb
Host smart-5baa1f04-9c2b-47c7-97d8-eb0ff19a3a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238533122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.238533122
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1448420463
Short name T814
Test name
Test status
Simulation time 1831892396 ps
CPU time 53.96 seconds
Started Jul 20 04:38:36 PM PDT 24
Finished Jul 20 04:39:33 PM PDT 24
Peak memory 275056 kb
Host smart-c0187e25-2a8c-4964-9780-5175663c46fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448420463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1448420463
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2659017483
Short name T3
Test name
Test status
Simulation time 15048856 ps
CPU time 1.13 seconds
Started Jul 20 04:38:36 PM PDT 24
Finished Jul 20 04:38:40 PM PDT 24
Peak memory 211304 kb
Host smart-0b5928ab-e308-40a8-8999-4e0eeb24a06e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659017483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2659017483
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3671876766
Short name T678
Test name
Test status
Simulation time 58707471 ps
CPU time 0.9 seconds
Started Jul 20 04:38:46 PM PDT 24
Finished Jul 20 04:38:49 PM PDT 24
Peak memory 208248 kb
Host smart-239114fa-9bcc-4c82-b2e0-be2c3f7dd6a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671876766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3671876766
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1566027817
Short name T646
Test name
Test status
Simulation time 216443015 ps
CPU time 9.91 seconds
Started Jul 20 04:38:40 PM PDT 24
Finished Jul 20 04:38:52 PM PDT 24
Peak memory 217768 kb
Host smart-2da5edab-20ef-4b72-9d53-3a17550e0b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566027817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1566027817
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.430741798
Short name T416
Test name
Test status
Simulation time 4917976081 ps
CPU time 16.95 seconds
Started Jul 20 04:38:41 PM PDT 24
Finished Jul 20 04:38:59 PM PDT 24
Peak memory 217132 kb
Host smart-2fe93a51-2aa1-4aa2-82c2-436d9d78f4d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430741798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.430741798
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.1143157554
Short name T436
Test name
Test status
Simulation time 209583893 ps
CPU time 3.09 seconds
Started Jul 20 04:38:39 PM PDT 24
Finished Jul 20 04:38:44 PM PDT 24
Peak memory 221828 kb
Host smart-26301eae-fbed-4e56-a80d-34ecfcc13745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143157554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1143157554
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2508271018
Short name T333
Test name
Test status
Simulation time 418110481 ps
CPU time 14.58 seconds
Started Jul 20 04:38:34 PM PDT 24
Finished Jul 20 04:38:51 PM PDT 24
Peak memory 217748 kb
Host smart-f0dc0124-46c4-48a9-ad98-bfc3deb86693
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508271018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2508271018
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1498001004
Short name T793
Test name
Test status
Simulation time 1229797424 ps
CPU time 11.23 seconds
Started Jul 20 04:38:40 PM PDT 24
Finished Jul 20 04:38:53 PM PDT 24
Peak memory 225368 kb
Host smart-17d08085-7853-441b-94c9-68f70dadc8e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498001004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1498001004
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1854689727
Short name T51
Test name
Test status
Simulation time 690924401 ps
CPU time 7.95 seconds
Started Jul 20 04:38:34 PM PDT 24
Finished Jul 20 04:38:43 PM PDT 24
Peak memory 217748 kb
Host smart-a756e476-d0e5-4196-a201-950228a3b104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854689727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1854689727
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2892725204
Short name T630
Test name
Test status
Simulation time 31548019 ps
CPU time 1.17 seconds
Started Jul 20 04:38:37 PM PDT 24
Finished Jul 20 04:38:40 PM PDT 24
Peak memory 211580 kb
Host smart-a032df27-cdc3-4598-90e9-f151cee5898c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892725204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2892725204
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1453292555
Short name T655
Test name
Test status
Simulation time 338703126 ps
CPU time 30.11 seconds
Started Jul 20 04:38:40 PM PDT 24
Finished Jul 20 04:39:12 PM PDT 24
Peak memory 250376 kb
Host smart-a76c63c1-c0e3-42c4-a51b-0b4b16aaf0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453292555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1453292555
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1109756895
Short name T765
Test name
Test status
Simulation time 215417711 ps
CPU time 5.14 seconds
Started Jul 20 04:38:39 PM PDT 24
Finished Jul 20 04:38:46 PM PDT 24
Peak memory 221440 kb
Host smart-d6032a02-28e6-4ba9-8d66-75ea01824c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109756895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1109756895
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2144963216
Short name T244
Test name
Test status
Simulation time 47077184468 ps
CPU time 355.64 seconds
Started Jul 20 04:38:41 PM PDT 24
Finished Jul 20 04:44:38 PM PDT 24
Peak memory 250504 kb
Host smart-d102e8d6-eab8-4297-aacc-3b2375c9ebbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144963216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2144963216
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1762886552
Short name T80
Test name
Test status
Simulation time 15450271 ps
CPU time 1.14 seconds
Started Jul 20 04:38:38 PM PDT 24
Finished Jul 20 04:38:41 PM PDT 24
Peak memory 211356 kb
Host smart-c682dbd8-c572-4c31-971e-ecffad1c47b2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762886552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1762886552
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2284353906
Short name T583
Test name
Test status
Simulation time 16440829 ps
CPU time 0.92 seconds
Started Jul 20 04:38:50 PM PDT 24
Finished Jul 20 04:38:52 PM PDT 24
Peak memory 208292 kb
Host smart-ad7a3e8c-d494-406b-b2d8-a2ff7c29b5f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284353906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2284353906
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.565160417
Short name T819
Test name
Test status
Simulation time 1782466234 ps
CPU time 15.54 seconds
Started Jul 20 04:38:47 PM PDT 24
Finished Jul 20 04:39:04 PM PDT 24
Peak memory 217604 kb
Host smart-7858b45c-909e-44bb-b3fb-53fd57d88a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565160417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.565160417
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1478258830
Short name T347
Test name
Test status
Simulation time 339069820 ps
CPU time 1.99 seconds
Started Jul 20 04:38:46 PM PDT 24
Finished Jul 20 04:38:50 PM PDT 24
Peak memory 216380 kb
Host smart-27d89eb4-6d8c-42c3-bf80-e6ca2ae28749
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478258830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1478258830
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2897926022
Short name T663
Test name
Test status
Simulation time 24653766 ps
CPU time 1.73 seconds
Started Jul 20 04:38:49 PM PDT 24
Finished Jul 20 04:38:53 PM PDT 24
Peak memory 217684 kb
Host smart-b64639ed-5598-412c-bbb1-e47096dfdbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897926022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2897926022
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1605888803
Short name T299
Test name
Test status
Simulation time 585631057 ps
CPU time 10.02 seconds
Started Jul 20 04:38:49 PM PDT 24
Finished Jul 20 04:39:01 PM PDT 24
Peak memory 217680 kb
Host smart-88aafd1f-8c70-43ea-9f1c-33ae34df2d2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605888803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1605888803
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3071513676
Short name T674
Test name
Test status
Simulation time 684391349 ps
CPU time 12.97 seconds
Started Jul 20 04:38:46 PM PDT 24
Finished Jul 20 04:39:01 PM PDT 24
Peak memory 225688 kb
Host smart-b7105990-f21b-4274-8dd8-d70c12850f77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071513676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3071513676
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.896765066
Short name T760
Test name
Test status
Simulation time 586716862 ps
CPU time 7.68 seconds
Started Jul 20 04:38:48 PM PDT 24
Finished Jul 20 04:38:57 PM PDT 24
Peak memory 225468 kb
Host smart-c2cf24c0-1b7f-438b-82c6-9ae4c7b96bd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896765066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.896765066
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.4179325333
Short name T422
Test name
Test status
Simulation time 320322596 ps
CPU time 10.7 seconds
Started Jul 20 04:38:47 PM PDT 24
Finished Jul 20 04:39:00 PM PDT 24
Peak memory 217768 kb
Host smart-4d6ebfe2-6184-4db6-99a7-a1683dbd57cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179325333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.4179325333
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2675913076
Short name T406
Test name
Test status
Simulation time 643723916 ps
CPU time 3.44 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:38:59 PM PDT 24
Peak memory 214480 kb
Host smart-fca14fa9-60d3-4541-9c28-09ce9e0915ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675913076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2675913076
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.449543932
Short name T311
Test name
Test status
Simulation time 888588131 ps
CPU time 24.24 seconds
Started Jul 20 04:38:49 PM PDT 24
Finished Jul 20 04:39:15 PM PDT 24
Peak memory 250440 kb
Host smart-587ed59e-35d7-4f2d-adbf-dd50db226f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449543932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.449543932
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.4149348924
Short name T842
Test name
Test status
Simulation time 112473826 ps
CPU time 7.72 seconds
Started Jul 20 04:38:46 PM PDT 24
Finished Jul 20 04:38:55 PM PDT 24
Peak memory 250396 kb
Host smart-2432fee1-fc83-4697-8f34-b2cdc381f93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149348924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.4149348924
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.80155618
Short name T76
Test name
Test status
Simulation time 22517652 ps
CPU time 1.02 seconds
Started Jul 20 04:38:45 PM PDT 24
Finished Jul 20 04:38:47 PM PDT 24
Peak memory 211440 kb
Host smart-9f593388-06ff-45e7-ba8c-32745dbd123a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80155618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctr
l_volatile_unlock_smoke.80155618
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.2681920843
Short name T332
Test name
Test status
Simulation time 36628901 ps
CPU time 0.84 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:38:58 PM PDT 24
Peak memory 208092 kb
Host smart-4cc7745a-8542-4635-9fad-b59cd6ac2e2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681920843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2681920843
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2374302099
Short name T471
Test name
Test status
Simulation time 380986407 ps
CPU time 12.13 seconds
Started Jul 20 04:38:45 PM PDT 24
Finished Jul 20 04:38:59 PM PDT 24
Peak memory 217712 kb
Host smart-d8784413-ca71-4141-b26f-c52a3145e8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374302099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2374302099
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1607298139
Short name T504
Test name
Test status
Simulation time 1719441731 ps
CPU time 20.11 seconds
Started Jul 20 04:38:46 PM PDT 24
Finished Jul 20 04:39:08 PM PDT 24
Peak memory 216852 kb
Host smart-8a52794f-17a8-4db4-b040-c84871f29a08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607298139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1607298139
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1407244486
Short name T173
Test name
Test status
Simulation time 29635456 ps
CPU time 1.67 seconds
Started Jul 20 04:38:48 PM PDT 24
Finished Jul 20 04:38:52 PM PDT 24
Peak memory 217604 kb
Host smart-90a94adc-7580-4a06-96c6-67cc56ef8335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407244486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1407244486
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1863397059
Short name T463
Test name
Test status
Simulation time 1469735397 ps
CPU time 13.29 seconds
Started Jul 20 04:38:46 PM PDT 24
Finished Jul 20 04:39:01 PM PDT 24
Peak memory 225488 kb
Host smart-0c969f4e-2ccc-4ed8-bc08-e2cdb3b9e426
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863397059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1863397059
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.588952634
Short name T480
Test name
Test status
Simulation time 300130250 ps
CPU time 10.69 seconds
Started Jul 20 04:38:49 PM PDT 24
Finished Jul 20 04:39:02 PM PDT 24
Peak memory 225412 kb
Host smart-7ce1a9a9-5dd2-4860-8e0b-b8cece3e2125
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588952634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.588952634
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.964056112
Short name T380
Test name
Test status
Simulation time 1199121120 ps
CPU time 8.8 seconds
Started Jul 20 04:38:53 PM PDT 24
Finished Jul 20 04:39:04 PM PDT 24
Peak memory 225424 kb
Host smart-322e1f46-846a-4572-92c3-3e3b187de595
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964056112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.964056112
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.1116160759
Short name T785
Test name
Test status
Simulation time 1717059043 ps
CPU time 13.26 seconds
Started Jul 20 04:38:47 PM PDT 24
Finished Jul 20 04:39:02 PM PDT 24
Peak memory 217728 kb
Host smart-b16e8c69-60a4-4681-b6fc-40ee5b11122b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116160759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1116160759
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1329545827
Short name T523
Test name
Test status
Simulation time 62297347 ps
CPU time 3.86 seconds
Started Jul 20 04:38:44 PM PDT 24
Finished Jul 20 04:38:49 PM PDT 24
Peak memory 217132 kb
Host smart-a5546568-a094-4e5e-b6ee-d58fb5ffd0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329545827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1329545827
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.647145918
Short name T513
Test name
Test status
Simulation time 1129214382 ps
CPU time 37.24 seconds
Started Jul 20 04:38:48 PM PDT 24
Finished Jul 20 04:39:27 PM PDT 24
Peak memory 250312 kb
Host smart-ca7e0a35-eaae-45dd-86e8-2ab839e65aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647145918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.647145918
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3370935823
Short name T315
Test name
Test status
Simulation time 77961772 ps
CPU time 6.51 seconds
Started Jul 20 04:38:49 PM PDT 24
Finished Jul 20 04:38:58 PM PDT 24
Peak memory 250436 kb
Host smart-03e00aa0-c813-429a-bdb0-38a2abcf4ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370935823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3370935823
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.73838915
Short name T46
Test name
Test status
Simulation time 20053976435 ps
CPU time 155.67 seconds
Started Jul 20 04:38:44 PM PDT 24
Finished Jul 20 04:41:20 PM PDT 24
Peak memory 225596 kb
Host smart-1b8dc2c3-4ede-4841-b09f-2b94d830000f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73838915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.lc_ctrl_stress_all.73838915
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.774803560
Short name T753
Test name
Test status
Simulation time 19622823 ps
CPU time 0.94 seconds
Started Jul 20 04:38:52 PM PDT 24
Finished Jul 20 04:38:54 PM PDT 24
Peak memory 208392 kb
Host smart-e12c5f4a-cc35-4786-8e66-763a39b4d5d3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774803560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct
rl_volatile_unlock_smoke.774803560
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2546142489
Short name T71
Test name
Test status
Simulation time 201962905 ps
CPU time 1.09 seconds
Started Jul 20 04:36:54 PM PDT 24
Finished Jul 20 04:36:57 PM PDT 24
Peak memory 208344 kb
Host smart-96030aae-5a0a-45f9-b2f9-408d748e254b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546142489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2546142489
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1461709016
Short name T801
Test name
Test status
Simulation time 15086507 ps
CPU time 0.88 seconds
Started Jul 20 04:36:55 PM PDT 24
Finished Jul 20 04:36:58 PM PDT 24
Peak memory 207976 kb
Host smart-bf51cb68-ac4d-4c1d-af03-9b0a42238169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461709016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1461709016
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3454639025
Short name T784
Test name
Test status
Simulation time 875700688 ps
CPU time 14.96 seconds
Started Jul 20 04:37:01 PM PDT 24
Finished Jul 20 04:37:17 PM PDT 24
Peak memory 217640 kb
Host smart-3f4a4780-ccf0-4a3d-9b4a-89d44dbc664d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454639025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3454639025
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.4122418424
Short name T208
Test name
Test status
Simulation time 549230045 ps
CPU time 3.83 seconds
Started Jul 20 04:36:53 PM PDT 24
Finished Jul 20 04:36:59 PM PDT 24
Peak memory 216616 kb
Host smart-65be8cae-1c6c-4c95-9b7d-951a7a7c61fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122418424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.4122418424
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.350095691
Short name T579
Test name
Test status
Simulation time 5919073771 ps
CPU time 50.79 seconds
Started Jul 20 04:37:01 PM PDT 24
Finished Jul 20 04:37:53 PM PDT 24
Peak memory 225480 kb
Host smart-37ed49a6-1c73-46ad-bb8b-c2b0e20e515e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350095691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.350095691
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.551416945
Short name T699
Test name
Test status
Simulation time 322647131 ps
CPU time 1.8 seconds
Started Jul 20 04:36:55 PM PDT 24
Finished Jul 20 04:36:58 PM PDT 24
Peak memory 217164 kb
Host smart-12d90250-f9e3-4bbf-b634-78dfa56326c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551416945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.551416945
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1814373820
Short name T752
Test name
Test status
Simulation time 478365026 ps
CPU time 3.61 seconds
Started Jul 20 04:36:54 PM PDT 24
Finished Jul 20 04:36:59 PM PDT 24
Peak memory 221340 kb
Host smart-69258c9e-0995-4809-a2b5-0b75f05f2792
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814373820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1814373820
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2280747344
Short name T70
Test name
Test status
Simulation time 1158578275 ps
CPU time 16.24 seconds
Started Jul 20 04:36:57 PM PDT 24
Finished Jul 20 04:37:14 PM PDT 24
Peak memory 216992 kb
Host smart-defb2709-d8e5-4d22-b086-16a22b5ecdca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280747344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2280747344
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.579904709
Short name T458
Test name
Test status
Simulation time 584436138 ps
CPU time 14.42 seconds
Started Jul 20 04:37:01 PM PDT 24
Finished Jul 20 04:37:17 PM PDT 24
Peak memory 217040 kb
Host smart-d98ad252-d4dc-480b-86e1-3b8ceed1828f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579904709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.579904709
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2942484545
Short name T378
Test name
Test status
Simulation time 1265194042 ps
CPU time 44.29 seconds
Started Jul 20 04:36:55 PM PDT 24
Finished Jul 20 04:37:41 PM PDT 24
Peak memory 275672 kb
Host smart-2eb7c24b-cd2c-4c29-93d0-d1ce540a2263
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942484545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2942484545
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2237681149
Short name T613
Test name
Test status
Simulation time 504894963 ps
CPU time 18.05 seconds
Started Jul 20 04:36:55 PM PDT 24
Finished Jul 20 04:37:14 PM PDT 24
Peak memory 246736 kb
Host smart-a2081416-16e9-477d-9dfb-1a7d0a5c374e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237681149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2237681149
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2859569846
Short name T653
Test name
Test status
Simulation time 200386984 ps
CPU time 2.79 seconds
Started Jul 20 04:36:53 PM PDT 24
Finished Jul 20 04:36:56 PM PDT 24
Peak memory 217744 kb
Host smart-0e864f28-a653-4b13-aad8-20b83736fd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859569846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2859569846
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2014453904
Short name T639
Test name
Test status
Simulation time 2744017953 ps
CPU time 11.12 seconds
Started Jul 20 04:36:53 PM PDT 24
Finished Jul 20 04:37:06 PM PDT 24
Peak memory 213396 kb
Host smart-86a27656-eb44-48b4-b10f-c11f0aaf42ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014453904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2014453904
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.86136103
Short name T265
Test name
Test status
Simulation time 347430430 ps
CPU time 10.96 seconds
Started Jul 20 04:36:53 PM PDT 24
Finished Jul 20 04:37:05 PM PDT 24
Peak memory 217668 kb
Host smart-7919e175-2bed-46b2-9d46-796ba6eb41be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86136103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dige
st.86136103
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.653763218
Short name T167
Test name
Test status
Simulation time 1797929592 ps
CPU time 8.68 seconds
Started Jul 20 04:36:55 PM PDT 24
Finished Jul 20 04:37:06 PM PDT 24
Peak memory 225416 kb
Host smart-0e65a65e-0ebe-4d5f-a75e-0fcc25eafcc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653763218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.653763218
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1334446339
Short name T594
Test name
Test status
Simulation time 232609552 ps
CPU time 7.33 seconds
Started Jul 20 04:36:54 PM PDT 24
Finished Jul 20 04:37:03 PM PDT 24
Peak memory 224376 kb
Host smart-0931a374-5c91-4321-a30d-4afc26d480f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334446339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1334446339
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.2514861100
Short name T61
Test name
Test status
Simulation time 41285248 ps
CPU time 1.48 seconds
Started Jul 20 04:36:55 PM PDT 24
Finished Jul 20 04:36:59 PM PDT 24
Peak memory 213328 kb
Host smart-52a1db32-7f3e-4afc-8843-736cfbdd895c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514861100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.2514861100
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.462700514
Short name T373
Test name
Test status
Simulation time 685792556 ps
CPU time 25.9 seconds
Started Jul 20 04:36:58 PM PDT 24
Finished Jul 20 04:37:26 PM PDT 24
Peak memory 250256 kb
Host smart-4baf96c6-cf7d-41b4-9439-a721c0b91a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462700514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.462700514
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.958891721
Short name T514
Test name
Test status
Simulation time 50696683 ps
CPU time 2.49 seconds
Started Jul 20 04:36:53 PM PDT 24
Finished Jul 20 04:36:56 PM PDT 24
Peak memory 217692 kb
Host smart-1e9563f4-6a57-482d-ac67-18e75cf51b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958891721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.958891721
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3617076976
Short name T243
Test name
Test status
Simulation time 14705209298 ps
CPU time 139.58 seconds
Started Jul 20 04:36:56 PM PDT 24
Finished Jul 20 04:39:17 PM PDT 24
Peak memory 278948 kb
Host smart-bb47e35e-70a8-4b8a-a175-f2630f9334b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617076976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3617076976
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1362098686
Short name T694
Test name
Test status
Simulation time 17742598 ps
CPU time 1.44 seconds
Started Jul 20 04:36:55 PM PDT 24
Finished Jul 20 04:36:58 PM PDT 24
Peak memory 217164 kb
Host smart-ebcea93c-df78-481f-a833-7d1bbd70d774
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362098686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1362098686
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3042708730
Short name T468
Test name
Test status
Simulation time 29577565 ps
CPU time 0.93 seconds
Started Jul 20 04:38:46 PM PDT 24
Finished Jul 20 04:38:49 PM PDT 24
Peak memory 208236 kb
Host smart-cdb4a5a5-735c-4ea1-8f0d-5aa08477e66f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042708730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3042708730
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1639579014
Short name T396
Test name
Test status
Simulation time 316734583 ps
CPU time 13.8 seconds
Started Jul 20 04:38:49 PM PDT 24
Finished Jul 20 04:39:05 PM PDT 24
Peak memory 217744 kb
Host smart-9746924b-01e4-42b0-881a-98394916d1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639579014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1639579014
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1162114619
Short name T505
Test name
Test status
Simulation time 387599513 ps
CPU time 10.74 seconds
Started Jul 20 04:38:47 PM PDT 24
Finished Jul 20 04:39:00 PM PDT 24
Peak memory 217112 kb
Host smart-08f02b9d-c394-4a38-9ba5-e3d5ac449c13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162114619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1162114619
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3706346948
Short name T466
Test name
Test status
Simulation time 64906379 ps
CPU time 2.31 seconds
Started Jul 20 04:38:48 PM PDT 24
Finished Jul 20 04:38:53 PM PDT 24
Peak memory 217668 kb
Host smart-65791e01-50e0-4762-b2b1-c069d23d2371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706346948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3706346948
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.868054018
Short name T589
Test name
Test status
Simulation time 426321935 ps
CPU time 18.69 seconds
Started Jul 20 04:38:45 PM PDT 24
Finished Jul 20 04:39:05 PM PDT 24
Peak memory 225432 kb
Host smart-228132c6-7eb7-4b64-9951-5c4d787c3d32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868054018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.868054018
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.875601146
Short name T245
Test name
Test status
Simulation time 1065376943 ps
CPU time 11.91 seconds
Started Jul 20 04:38:51 PM PDT 24
Finished Jul 20 04:39:04 PM PDT 24
Peak memory 217664 kb
Host smart-921e687d-c896-4bd4-9bea-c7c07760f539
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875601146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_di
gest.875601146
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2323407874
Short name T609
Test name
Test status
Simulation time 627009433 ps
CPU time 11.96 seconds
Started Jul 20 04:38:49 PM PDT 24
Finished Jul 20 04:39:03 PM PDT 24
Peak memory 225192 kb
Host smart-896b2a9b-5f68-43a4-a4bc-978ff8a4608f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323407874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
2323407874
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2558880394
Short name T56
Test name
Test status
Simulation time 231947188 ps
CPU time 9.75 seconds
Started Jul 20 04:38:47 PM PDT 24
Finished Jul 20 04:38:58 PM PDT 24
Peak memory 217760 kb
Host smart-98950aef-2996-42a0-859a-4a0f8f108a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558880394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2558880394
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.168922478
Short name T182
Test name
Test status
Simulation time 65527090 ps
CPU time 1.08 seconds
Started Jul 20 04:38:46 PM PDT 24
Finished Jul 20 04:38:49 PM PDT 24
Peak memory 211664 kb
Host smart-7154728f-7cc2-4194-ada3-540a7cb5dd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168922478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.168922478
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.4189199445
Short name T705
Test name
Test status
Simulation time 1577232249 ps
CPU time 24.1 seconds
Started Jul 20 04:38:49 PM PDT 24
Finished Jul 20 04:39:15 PM PDT 24
Peak memory 250424 kb
Host smart-a6e6ecb2-58b4-40a6-8fcf-1b9f995b830e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189199445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.4189199445
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1214109134
Short name T515
Test name
Test status
Simulation time 213438647 ps
CPU time 3.23 seconds
Started Jul 20 04:38:45 PM PDT 24
Finished Jul 20 04:38:49 PM PDT 24
Peak memory 217624 kb
Host smart-bbe96b74-5c38-44c0-9e08-eb470a7e50b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214109134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1214109134
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.158079061
Short name T804
Test name
Test status
Simulation time 3450783657 ps
CPU time 146.66 seconds
Started Jul 20 04:38:48 PM PDT 24
Finished Jul 20 04:41:17 PM PDT 24
Peak memory 273140 kb
Host smart-10d43628-db1f-4686-af79-60dd4dfc1d70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158079061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.158079061
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.3224089618
Short name T111
Test name
Test status
Simulation time 85092674122 ps
CPU time 400.72 seconds
Started Jul 20 04:38:52 PM PDT 24
Finished Jul 20 04:45:34 PM PDT 24
Peak memory 299656 kb
Host smart-fe02c256-ae51-4722-a316-320825b6e4c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3224089618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.3224089618
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2445588400
Short name T671
Test name
Test status
Simulation time 104919865 ps
CPU time 0.98 seconds
Started Jul 20 04:38:44 PM PDT 24
Finished Jul 20 04:38:45 PM PDT 24
Peak memory 217052 kb
Host smart-784935c6-af2b-4177-baee-729be8ee0f7f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445588400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2445588400
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2939258325
Short name T270
Test name
Test status
Simulation time 43909865 ps
CPU time 1.08 seconds
Started Jul 20 04:38:48 PM PDT 24
Finished Jul 20 04:38:51 PM PDT 24
Peak memory 208388 kb
Host smart-5993a382-58f7-4fab-a22d-cab9e893343f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939258325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2939258325
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2736070329
Short name T6
Test name
Test status
Simulation time 752418625 ps
CPU time 16.25 seconds
Started Jul 20 04:38:47 PM PDT 24
Finished Jul 20 04:39:05 PM PDT 24
Peak memory 217704 kb
Host smart-0a5ff32d-7455-4322-a447-a18447cbf163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736070329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2736070329
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1004120565
Short name T829
Test name
Test status
Simulation time 3374167560 ps
CPU time 5.84 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:39:02 PM PDT 24
Peak memory 217160 kb
Host smart-7a80034a-4379-4df0-ae82-ff2d2e7654d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004120565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1004120565
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2756951983
Short name T263
Test name
Test status
Simulation time 103046965 ps
CPU time 2.03 seconds
Started Jul 20 04:38:49 PM PDT 24
Finished Jul 20 04:38:53 PM PDT 24
Peak memory 217260 kb
Host smart-5e27e4ca-359e-49d3-9477-08eca9792ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756951983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2756951983
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3349563829
Short name T574
Test name
Test status
Simulation time 1408474511 ps
CPU time 14.39 seconds
Started Jul 20 04:38:47 PM PDT 24
Finished Jul 20 04:39:04 PM PDT 24
Peak memory 217736 kb
Host smart-056fcc8d-9bcf-42b5-9ccd-705598dbafb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349563829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.3349563829
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2799444849
Short name T847
Test name
Test status
Simulation time 509136218 ps
CPU time 9.25 seconds
Started Jul 20 04:38:47 PM PDT 24
Finished Jul 20 04:38:59 PM PDT 24
Peak memory 217568 kb
Host smart-db9f4d4f-9813-42f9-879c-340376efc1bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799444849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2799444849
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.2568994280
Short name T541
Test name
Test status
Simulation time 949682822 ps
CPU time 9.65 seconds
Started Jul 20 04:38:49 PM PDT 24
Finished Jul 20 04:39:01 PM PDT 24
Peak memory 225484 kb
Host smart-a99f1dbf-cbeb-4f1d-be26-d9e5d76f52f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568994280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2568994280
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3945381895
Short name T520
Test name
Test status
Simulation time 100480719 ps
CPU time 2.1 seconds
Started Jul 20 04:38:46 PM PDT 24
Finished Jul 20 04:38:49 PM PDT 24
Peak memory 213892 kb
Host smart-7d1a3379-be47-4aa7-b7e2-834b7af9ff9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945381895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3945381895
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.3633311401
Short name T570
Test name
Test status
Simulation time 6090087093 ps
CPU time 28.26 seconds
Started Jul 20 04:38:52 PM PDT 24
Finished Jul 20 04:39:22 PM PDT 24
Peak memory 250328 kb
Host smart-c38709ae-8abb-465c-8381-0ed7ed865f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633311401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3633311401
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1167484806
Short name T18
Test name
Test status
Simulation time 290411070 ps
CPU time 7.31 seconds
Started Jul 20 04:38:48 PM PDT 24
Finished Jul 20 04:38:57 PM PDT 24
Peak memory 246784 kb
Host smart-3e0d837e-f9ba-4878-b3cd-72471c88280b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167484806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1167484806
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1697992549
Short name T813
Test name
Test status
Simulation time 9301306276 ps
CPU time 70.77 seconds
Started Jul 20 04:38:53 PM PDT 24
Finished Jul 20 04:40:05 PM PDT 24
Peak memory 274296 kb
Host smart-9f253c12-32f0-4523-ae18-b1e279ba553c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697992549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1697992549
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.170408459
Short name T148
Test name
Test status
Simulation time 58255617169 ps
CPU time 320.44 seconds
Started Jul 20 04:38:47 PM PDT 24
Finished Jul 20 04:44:09 PM PDT 24
Peak memory 275376 kb
Host smart-71a22936-b2c0-4e83-a931-1505ffd167a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=170408459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.170408459
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2501370309
Short name T254
Test name
Test status
Simulation time 23825943 ps
CPU time 0.91 seconds
Started Jul 20 04:38:49 PM PDT 24
Finished Jul 20 04:38:52 PM PDT 24
Peak memory 211524 kb
Host smart-4efb0305-bb49-4973-8fa3-a7354bb3d319
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501370309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2501370309
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3050175727
Short name T227
Test name
Test status
Simulation time 69576668 ps
CPU time 1.08 seconds
Started Jul 20 04:38:53 PM PDT 24
Finished Jul 20 04:38:56 PM PDT 24
Peak memory 208308 kb
Host smart-38565d26-eb29-4b18-9163-5b95e08f20f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050175727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3050175727
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1092915461
Short name T786
Test name
Test status
Simulation time 9909283167 ps
CPU time 14.32 seconds
Started Jul 20 04:38:53 PM PDT 24
Finished Jul 20 04:39:09 PM PDT 24
Peak memory 225496 kb
Host smart-88339887-f8b2-4353-90b1-23af68009ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092915461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1092915461
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3576736320
Short name T31
Test name
Test status
Simulation time 1869174614 ps
CPU time 7.21 seconds
Started Jul 20 04:38:53 PM PDT 24
Finished Jul 20 04:39:01 PM PDT 24
Peak memory 216844 kb
Host smart-eed7c242-7873-4de4-a705-cf6ee83618cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576736320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3576736320
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2525165485
Short name T629
Test name
Test status
Simulation time 450403829 ps
CPU time 4.4 seconds
Started Jul 20 04:38:45 PM PDT 24
Finished Jul 20 04:38:50 PM PDT 24
Peak memory 217696 kb
Host smart-96bb41d9-6b11-45a9-a934-774782c84783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525165485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2525165485
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2415188293
Short name T626
Test name
Test status
Simulation time 500319157 ps
CPU time 14.22 seconds
Started Jul 20 04:38:56 PM PDT 24
Finished Jul 20 04:39:12 PM PDT 24
Peak memory 225468 kb
Host smart-411ec8c4-5417-49fe-b075-65096b65dd45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415188293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2415188293
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2461761268
Short name T527
Test name
Test status
Simulation time 4421220212 ps
CPU time 14.82 seconds
Started Jul 20 04:38:57 PM PDT 24
Finished Jul 20 04:39:13 PM PDT 24
Peak memory 217716 kb
Host smart-4474626f-1a0a-4cd8-bb3a-619348d51b12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461761268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2461761268
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.428741292
Short name T310
Test name
Test status
Simulation time 504339013 ps
CPU time 18.82 seconds
Started Jul 20 04:38:53 PM PDT 24
Finished Jul 20 04:39:14 PM PDT 24
Peak memory 225472 kb
Host smart-71384210-0140-4172-b64c-7c28c66d68b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428741292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.428741292
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2257717033
Short name T815
Test name
Test status
Simulation time 34131147 ps
CPU time 1.98 seconds
Started Jul 20 04:38:47 PM PDT 24
Finished Jul 20 04:38:51 PM PDT 24
Peak memory 217188 kb
Host smart-f1f93d45-97c6-44ff-bb15-6f2387c4016c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257717033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2257717033
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3035052539
Short name T750
Test name
Test status
Simulation time 685581850 ps
CPU time 26.05 seconds
Started Jul 20 04:38:51 PM PDT 24
Finished Jul 20 04:39:18 PM PDT 24
Peak memory 250392 kb
Host smart-e9b5e1df-da35-43ac-a23d-dc0cafbb3730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035052539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3035052539
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.863858203
Short name T727
Test name
Test status
Simulation time 422100604 ps
CPU time 3.66 seconds
Started Jul 20 04:38:51 PM PDT 24
Finished Jul 20 04:38:56 PM PDT 24
Peak memory 221676 kb
Host smart-07e8ecb0-63c9-4fc7-949d-b49b5fe35130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863858203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.863858203
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2951581419
Short name T420
Test name
Test status
Simulation time 1973360865 ps
CPU time 31.37 seconds
Started Jul 20 04:38:51 PM PDT 24
Finished Jul 20 04:39:24 PM PDT 24
Peak memory 250440 kb
Host smart-5a5a73a9-449b-40a0-a3a2-89c970950c55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951581419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2951581419
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.386191764
Short name T235
Test name
Test status
Simulation time 47495574 ps
CPU time 0.97 seconds
Started Jul 20 04:38:47 PM PDT 24
Finished Jul 20 04:38:50 PM PDT 24
Peak memory 208384 kb
Host smart-03cbf010-9301-4e37-8106-6c08667f2249
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386191764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct
rl_volatile_unlock_smoke.386191764
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.6097414
Short name T679
Test name
Test status
Simulation time 14557905 ps
CPU time 0.93 seconds
Started Jul 20 04:38:52 PM PDT 24
Finished Jul 20 04:38:54 PM PDT 24
Peak memory 208296 kb
Host smart-a5e3c8ae-3269-49ff-8058-ffb7d2deb9bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6097414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.6097414
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2931448380
Short name T454
Test name
Test status
Simulation time 264103799 ps
CPU time 10.73 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:39:08 PM PDT 24
Peak memory 217632 kb
Host smart-b89a0ea4-bb45-426a-91be-aa53866f944e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931448380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2931448380
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.819789496
Short name T275
Test name
Test status
Simulation time 37470483 ps
CPU time 1.65 seconds
Started Jul 20 04:38:59 PM PDT 24
Finished Jul 20 04:39:01 PM PDT 24
Peak memory 216540 kb
Host smart-27635f51-fd82-4f8e-85f5-901fcc158900
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819789496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.819789496
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2279257484
Short name T168
Test name
Test status
Simulation time 213585028 ps
CPU time 2.99 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:38:59 PM PDT 24
Peak memory 217696 kb
Host smart-e472ebb6-a144-4901-b3d6-d023e849a27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279257484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2279257484
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.579626954
Short name T258
Test name
Test status
Simulation time 1415632377 ps
CPU time 12.19 seconds
Started Jul 20 04:38:53 PM PDT 24
Finished Jul 20 04:39:06 PM PDT 24
Peak memory 218360 kb
Host smart-53d0cbbf-b778-471c-a919-3137b3b7fb1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579626954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.579626954
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3006051524
Short name T558
Test name
Test status
Simulation time 1152413077 ps
CPU time 10.27 seconds
Started Jul 20 04:38:53 PM PDT 24
Finished Jul 20 04:39:06 PM PDT 24
Peak memory 217684 kb
Host smart-a682e5d8-da8d-4b09-bed0-af4329168e80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006051524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3006051524
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.353267195
Short name T246
Test name
Test status
Simulation time 2135888817 ps
CPU time 9.88 seconds
Started Jul 20 04:38:53 PM PDT 24
Finished Jul 20 04:39:05 PM PDT 24
Peak memory 217772 kb
Host smart-47fedf46-3053-4bb5-aa95-2951d589751c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353267195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.353267195
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1294383904
Short name T384
Test name
Test status
Simulation time 416809342 ps
CPU time 2.99 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:38:59 PM PDT 24
Peak memory 217104 kb
Host smart-6d0b863b-2f8d-4a07-94bc-ef9c080d8bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294383904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1294383904
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.1541819425
Short name T648
Test name
Test status
Simulation time 2719732451 ps
CPU time 25.95 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:39:23 PM PDT 24
Peak memory 250488 kb
Host smart-1e3ffee6-986e-46f3-8322-ca7d137b5e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541819425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1541819425
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3775748862
Short name T566
Test name
Test status
Simulation time 397686877 ps
CPU time 9.1 seconds
Started Jul 20 04:38:56 PM PDT 24
Finished Jul 20 04:39:07 PM PDT 24
Peak memory 250404 kb
Host smart-224fb73e-c657-4d7c-b12f-980bce7f49bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775748862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3775748862
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2847936715
Short name T485
Test name
Test status
Simulation time 6775997256 ps
CPU time 218.33 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:42:35 PM PDT 24
Peak memory 275832 kb
Host smart-e844c226-fb9c-4614-8f97-daaf00f2f751
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847936715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2847936715
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.3462417615
Short name T837
Test name
Test status
Simulation time 66837864924 ps
CPU time 623.15 seconds
Started Jul 20 04:38:53 PM PDT 24
Finished Jul 20 04:49:18 PM PDT 24
Peak memory 528432 kb
Host smart-fa369edc-c704-4b9f-a30d-ee928e98ecba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3462417615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.3462417615
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3363728024
Short name T721
Test name
Test status
Simulation time 119144999 ps
CPU time 1.01 seconds
Started Jul 20 04:38:55 PM PDT 24
Finished Jul 20 04:38:59 PM PDT 24
Peak memory 211360 kb
Host smart-2f86adcb-11c8-4b97-8418-09d6c411cb42
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363728024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3363728024
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1369309072
Short name T231
Test name
Test status
Simulation time 26101846 ps
CPU time 1.36 seconds
Started Jul 20 04:38:53 PM PDT 24
Finished Jul 20 04:38:55 PM PDT 24
Peak memory 208408 kb
Host smart-f68930df-b6fd-4730-b9cb-9f4c2953fda6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369309072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1369309072
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2459372
Short name T375
Test name
Test status
Simulation time 384495336 ps
CPU time 11.3 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:39:08 PM PDT 24
Peak memory 217696 kb
Host smart-9910f7c7-49a5-4204-beca-ff79e3e204a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2459372
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.4280484077
Short name T27
Test name
Test status
Simulation time 834712878 ps
CPU time 11.51 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:39:08 PM PDT 24
Peak memory 217052 kb
Host smart-5d9ecfe1-860e-47f8-85ab-9b9829cd89ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280484077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.4280484077
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2518647488
Short name T253
Test name
Test status
Simulation time 414831019 ps
CPU time 2.55 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:38:59 PM PDT 24
Peak memory 221664 kb
Host smart-0a224c83-0ae0-4ca7-8851-90ccef1ee9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518647488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2518647488
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3914984878
Short name T273
Test name
Test status
Simulation time 704057246 ps
CPU time 11.53 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:39:08 PM PDT 24
Peak memory 218388 kb
Host smart-a60884c9-f04f-4223-9c10-ccb2116b4b5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914984878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3914984878
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1310502559
Short name T732
Test name
Test status
Simulation time 555791067 ps
CPU time 19.74 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:39:17 PM PDT 24
Peak memory 225432 kb
Host smart-8db1ae79-6a0b-40e7-bbf3-e0a3abe7ec91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310502559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1310502559
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.347364742
Short name T287
Test name
Test status
Simulation time 277777690 ps
CPU time 11.79 seconds
Started Jul 20 04:38:55 PM PDT 24
Finished Jul 20 04:39:09 PM PDT 24
Peak memory 225408 kb
Host smart-bd551cb9-504f-4efa-bb16-b0208e0d3f04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347364742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.347364742
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.333518069
Short name T778
Test name
Test status
Simulation time 2167001116 ps
CPU time 6.3 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:39:03 PM PDT 24
Peak memory 217836 kb
Host smart-68f339b5-cb48-42b6-9169-f401f4c67ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333518069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.333518069
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.716597180
Short name T482
Test name
Test status
Simulation time 113930004 ps
CPU time 1.94 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:38:59 PM PDT 24
Peak memory 213616 kb
Host smart-27af0381-04c5-4e58-90a9-ee63fe1d5ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716597180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.716597180
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.4048055127
Short name T849
Test name
Test status
Simulation time 44274131 ps
CPU time 3.1 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:39:00 PM PDT 24
Peak memory 221872 kb
Host smart-a2b13707-c3da-4dfb-ab15-cf550add6409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048055127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.4048055127
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.968930846
Short name T676
Test name
Test status
Simulation time 3357641579 ps
CPU time 112.45 seconds
Started Jul 20 04:38:56 PM PDT 24
Finished Jul 20 04:40:50 PM PDT 24
Peak memory 275136 kb
Host smart-dbb809db-9d05-422e-8850-055c632fe338
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968930846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.968930846
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.4047821444
Short name T839
Test name
Test status
Simulation time 19115478 ps
CPU time 0.97 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:38:57 PM PDT 24
Peak memory 211276 kb
Host smart-28670597-9b49-4f70-9049-8269272319fe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047821444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.4047821444
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3562465733
Short name T397
Test name
Test status
Simulation time 23853868 ps
CPU time 1.39 seconds
Started Jul 20 04:38:57 PM PDT 24
Finished Jul 20 04:39:00 PM PDT 24
Peak memory 208400 kb
Host smart-83c6921b-4a47-4a8b-bfd8-be26cfdd68a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562465733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3562465733
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3276643964
Short name T322
Test name
Test status
Simulation time 1368514785 ps
CPU time 11.1 seconds
Started Jul 20 04:38:59 PM PDT 24
Finished Jul 20 04:39:10 PM PDT 24
Peak memory 217816 kb
Host smart-7840c771-4144-4b54-afbf-788d4044755f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276643964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3276643964
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3455608132
Short name T650
Test name
Test status
Simulation time 936563674 ps
CPU time 4.58 seconds
Started Jul 20 04:38:53 PM PDT 24
Finished Jul 20 04:39:00 PM PDT 24
Peak memory 216664 kb
Host smart-8e394e52-2de9-4d27-9c93-8eb10a5718f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455608132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3455608132
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2651990410
Short name T660
Test name
Test status
Simulation time 244234554 ps
CPU time 1.54 seconds
Started Jul 20 04:38:59 PM PDT 24
Finished Jul 20 04:39:01 PM PDT 24
Peak memory 217340 kb
Host smart-97aa7d74-add0-41d9-bee9-b9f9facb2003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651990410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2651990410
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.434472283
Short name T491
Test name
Test status
Simulation time 344627915 ps
CPU time 13.3 seconds
Started Jul 20 04:38:52 PM PDT 24
Finished Jul 20 04:39:06 PM PDT 24
Peak memory 225424 kb
Host smart-4f7097aa-2a7c-4b41-a2f0-2e4d930d7401
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434472283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.434472283
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2502415482
Short name T177
Test name
Test status
Simulation time 1410788358 ps
CPU time 8.06 seconds
Started Jul 20 04:38:53 PM PDT 24
Finished Jul 20 04:39:04 PM PDT 24
Peak memory 225468 kb
Host smart-b4c9b162-09f4-4c7b-a3c5-0963d7b421a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502415482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2502415482
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1929447598
Short name T297
Test name
Test status
Simulation time 1236790410 ps
CPU time 11.87 seconds
Started Jul 20 04:38:51 PM PDT 24
Finished Jul 20 04:39:04 PM PDT 24
Peak memory 217808 kb
Host smart-dff5cf8e-66e8-40dc-aaaa-e282e61dc8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929447598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1929447598
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2671590297
Short name T75
Test name
Test status
Simulation time 36678598 ps
CPU time 2.3 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:38:59 PM PDT 24
Peak memory 217144 kb
Host smart-716ce2b8-b6da-4f64-998e-f1d6e58baa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671590297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2671590297
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.4160816287
Short name T217
Test name
Test status
Simulation time 549066934 ps
CPU time 25.25 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:39:22 PM PDT 24
Peak memory 250404 kb
Host smart-a51e8221-0e30-4373-a410-240f85e23d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160816287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.4160816287
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3717747773
Short name T726
Test name
Test status
Simulation time 758054809 ps
CPU time 10.05 seconds
Started Jul 20 04:38:55 PM PDT 24
Finished Jul 20 04:39:08 PM PDT 24
Peak memory 250436 kb
Host smart-781a0090-8a73-49e1-9e06-7c53d939eb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717747773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3717747773
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.4270072971
Short name T761
Test name
Test status
Simulation time 23160814234 ps
CPU time 113.72 seconds
Started Jul 20 04:38:54 PM PDT 24
Finished Jul 20 04:40:51 PM PDT 24
Peak memory 269880 kb
Host smart-cf724b31-91a7-447e-9adc-e7aaf10c4503
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270072971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.4270072971
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1813379589
Short name T795
Test name
Test status
Simulation time 42754786 ps
CPU time 0.76 seconds
Started Jul 20 04:38:53 PM PDT 24
Finished Jul 20 04:38:55 PM PDT 24
Peak memory 208220 kb
Host smart-02cf7a29-af4b-4eec-9a37-690b472be830
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813379589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1813379589
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2702296794
Short name T356
Test name
Test status
Simulation time 62498991 ps
CPU time 0.89 seconds
Started Jul 20 04:39:06 PM PDT 24
Finished Jul 20 04:39:10 PM PDT 24
Peak memory 208256 kb
Host smart-ce54b7fb-12ab-45c3-97d8-6fde7d2f613d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702296794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2702296794
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2043476440
Short name T763
Test name
Test status
Simulation time 721334539 ps
CPU time 26.56 seconds
Started Jul 20 04:39:01 PM PDT 24
Finished Jul 20 04:39:28 PM PDT 24
Peak memory 217700 kb
Host smart-cedf35ce-d517-4339-a1db-cded5950726b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043476440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2043476440
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1133220453
Short name T26
Test name
Test status
Simulation time 253437411 ps
CPU time 2.6 seconds
Started Jul 20 04:39:03 PM PDT 24
Finished Jul 20 04:39:07 PM PDT 24
Peak memory 216492 kb
Host smart-fbb7cfca-ee76-407a-9b0d-2e9edd509da3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133220453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1133220453
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2837527669
Short name T564
Test name
Test status
Simulation time 28221684 ps
CPU time 1.94 seconds
Started Jul 20 04:39:04 PM PDT 24
Finished Jul 20 04:39:09 PM PDT 24
Peak memory 217724 kb
Host smart-5ba11bcc-674e-4da9-9d3a-6b4b87e45e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837527669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2837527669
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2414429530
Short name T820
Test name
Test status
Simulation time 429345692 ps
CPU time 11.15 seconds
Started Jul 20 04:39:04 PM PDT 24
Finished Jul 20 04:39:18 PM PDT 24
Peak memory 218336 kb
Host smart-2801f53b-bdc7-455a-bd5a-e209c6d200a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414429530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2414429530
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2786177677
Short name T35
Test name
Test status
Simulation time 1348107377 ps
CPU time 22.59 seconds
Started Jul 20 04:39:07 PM PDT 24
Finished Jul 20 04:39:32 PM PDT 24
Peak memory 225364 kb
Host smart-a6e7955c-aa02-4c04-86b1-5ebc5e122c4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786177677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2786177677
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3754660262
Short name T319
Test name
Test status
Simulation time 598662541 ps
CPU time 7.46 seconds
Started Jul 20 04:39:04 PM PDT 24
Finished Jul 20 04:39:13 PM PDT 24
Peak memory 225428 kb
Host smart-d54f7de5-a9d0-4b62-9355-638e64e9ad4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754660262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3754660262
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1787870738
Short name T645
Test name
Test status
Simulation time 337484522 ps
CPU time 12.19 seconds
Started Jul 20 04:39:03 PM PDT 24
Finished Jul 20 04:39:16 PM PDT 24
Peak memory 225460 kb
Host smart-8cc43144-a1ba-42d5-8b83-6d1057736346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787870738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1787870738
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1248548830
Short name T767
Test name
Test status
Simulation time 47595900 ps
CPU time 3.11 seconds
Started Jul 20 04:39:02 PM PDT 24
Finished Jul 20 04:39:06 PM PDT 24
Peak memory 217216 kb
Host smart-63e62ee5-1d39-4253-9078-eea97ae849d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248548830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1248548830
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2887967279
Short name T677
Test name
Test status
Simulation time 790783198 ps
CPU time 21.29 seconds
Started Jul 20 04:39:02 PM PDT 24
Finished Jul 20 04:39:24 PM PDT 24
Peak memory 250552 kb
Host smart-e75dfa35-c030-4ac6-a674-a25ca7ec923c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887967279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2887967279
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3248797116
Short name T460
Test name
Test status
Simulation time 147827485 ps
CPU time 6.78 seconds
Started Jul 20 04:39:02 PM PDT 24
Finished Jul 20 04:39:10 PM PDT 24
Peak memory 249912 kb
Host smart-ff9d46eb-2cae-457b-85e3-e9c7a0e2e22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248797116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3248797116
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2474002153
Short name T324
Test name
Test status
Simulation time 991487274 ps
CPU time 20.18 seconds
Started Jul 20 04:39:05 PM PDT 24
Finished Jul 20 04:39:28 PM PDT 24
Peak memory 250436 kb
Host smart-050606c9-08c5-40bc-9b99-9c1439f309be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474002153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2474002153
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1821500511
Short name T399
Test name
Test status
Simulation time 14201895 ps
CPU time 1.17 seconds
Started Jul 20 04:39:03 PM PDT 24
Finished Jul 20 04:39:05 PM PDT 24
Peak memory 211408 kb
Host smart-4c5c9c58-8f4c-4bab-b46f-4cb3e897dc41
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821500511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1821500511
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3488957267
Short name T610
Test name
Test status
Simulation time 32565087 ps
CPU time 1.41 seconds
Started Jul 20 04:39:04 PM PDT 24
Finished Jul 20 04:39:07 PM PDT 24
Peak memory 208388 kb
Host smart-ded8a509-c4ef-4fb9-bafb-7840482ea102
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488957267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3488957267
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2409279126
Short name T442
Test name
Test status
Simulation time 1143469216 ps
CPU time 11.46 seconds
Started Jul 20 04:39:01 PM PDT 24
Finished Jul 20 04:39:13 PM PDT 24
Peak memory 217612 kb
Host smart-f9c5362f-c026-49be-8a56-9709879af5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409279126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2409279126
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2248006977
Short name T598
Test name
Test status
Simulation time 92185606 ps
CPU time 1.88 seconds
Started Jul 20 04:39:05 PM PDT 24
Finished Jul 20 04:39:09 PM PDT 24
Peak memory 216672 kb
Host smart-8dcbdb85-a1b0-4e35-b8b1-e540f62cd3af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248006977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2248006977
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.4084079645
Short name T573
Test name
Test status
Simulation time 586769752 ps
CPU time 2.54 seconds
Started Jul 20 04:39:04 PM PDT 24
Finished Jul 20 04:39:09 PM PDT 24
Peak memory 217700 kb
Host smart-6fc165ba-77e5-416b-99c5-12e211c0bf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084079645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.4084079645
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.500692595
Short name T257
Test name
Test status
Simulation time 2454915278 ps
CPU time 15.31 seconds
Started Jul 20 04:39:03 PM PDT 24
Finished Jul 20 04:39:21 PM PDT 24
Peak memory 218476 kb
Host smart-3bc19d53-7be5-41c3-8d26-47821af691df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500692595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.500692595
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.983798555
Short name T510
Test name
Test status
Simulation time 1283125319 ps
CPU time 8.38 seconds
Started Jul 20 04:39:04 PM PDT 24
Finished Jul 20 04:39:15 PM PDT 24
Peak memory 217936 kb
Host smart-9e1bc679-a1b1-48d2-abf3-4ebfce06bf8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983798555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.983798555
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3987049370
Short name T326
Test name
Test status
Simulation time 425463712 ps
CPU time 7.91 seconds
Started Jul 20 04:39:03 PM PDT 24
Finished Jul 20 04:39:12 PM PDT 24
Peak memory 225472 kb
Host smart-d1dffc13-91e0-42f3-bac6-fed107e4ebbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987049370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3987049370
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1395717378
Short name T363
Test name
Test status
Simulation time 167022432 ps
CPU time 6.89 seconds
Started Jul 20 04:39:05 PM PDT 24
Finished Jul 20 04:39:15 PM PDT 24
Peak memory 217752 kb
Host smart-036fe961-06a2-43b8-9dae-017ba663245f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395717378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1395717378
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.606770238
Short name T469
Test name
Test status
Simulation time 53467127 ps
CPU time 3.83 seconds
Started Jul 20 04:39:02 PM PDT 24
Finished Jul 20 04:39:07 PM PDT 24
Peak memory 214596 kb
Host smart-c233de56-2258-4cb9-8d04-fe537966adfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606770238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.606770238
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1510790079
Short name T506
Test name
Test status
Simulation time 1473948454 ps
CPU time 23.94 seconds
Started Jul 20 04:39:01 PM PDT 24
Finished Jul 20 04:39:26 PM PDT 24
Peak memory 250444 kb
Host smart-d88e8730-caa8-41a9-a9b3-04385ccd9895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510790079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1510790079
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1959765521
Short name T237
Test name
Test status
Simulation time 90943860 ps
CPU time 7.54 seconds
Started Jul 20 04:39:05 PM PDT 24
Finished Jul 20 04:39:15 PM PDT 24
Peak memory 245908 kb
Host smart-d04325ad-98b1-4671-9e68-72a72c712c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959765521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1959765521
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3938663066
Short name T370
Test name
Test status
Simulation time 141154371574 ps
CPU time 203.83 seconds
Started Jul 20 04:39:11 PM PDT 24
Finished Jul 20 04:42:35 PM PDT 24
Peak memory 421480 kb
Host smart-1a061772-e4c7-49a5-a244-038b4e0338da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938663066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3938663066
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1971640571
Short name T424
Test name
Test status
Simulation time 17071529 ps
CPU time 0.94 seconds
Started Jul 20 04:39:02 PM PDT 24
Finished Jul 20 04:39:04 PM PDT 24
Peak memory 208516 kb
Host smart-ca15e905-5a9c-41fe-8eea-de3381d110f0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971640571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1971640571
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2270992322
Short name T748
Test name
Test status
Simulation time 45815914 ps
CPU time 1.27 seconds
Started Jul 20 04:39:04 PM PDT 24
Finished Jul 20 04:39:07 PM PDT 24
Peak memory 208440 kb
Host smart-4841eceb-73dc-475a-9874-4821f7b155ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270992322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2270992322
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1664375748
Short name T358
Test name
Test status
Simulation time 787527438 ps
CPU time 22.3 seconds
Started Jul 20 04:39:02 PM PDT 24
Finished Jul 20 04:39:25 PM PDT 24
Peak memory 217708 kb
Host smart-f025711f-b742-40c3-97fd-e74314b4391e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664375748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1664375748
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.4060692512
Short name T186
Test name
Test status
Simulation time 782575758 ps
CPU time 9.7 seconds
Started Jul 20 04:39:04 PM PDT 24
Finished Jul 20 04:39:16 PM PDT 24
Peak memory 216828 kb
Host smart-3b4946b9-fa94-4e78-808b-26d359955dd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060692512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.4060692512
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1598362451
Short name T17
Test name
Test status
Simulation time 61162357 ps
CPU time 1.92 seconds
Started Jul 20 04:39:07 PM PDT 24
Finished Jul 20 04:39:11 PM PDT 24
Peak memory 221620 kb
Host smart-c611fc6b-2175-49c3-ab95-df19a75a6b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598362451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1598362451
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2685039287
Short name T544
Test name
Test status
Simulation time 385551570 ps
CPU time 10.77 seconds
Started Jul 20 04:39:06 PM PDT 24
Finished Jul 20 04:39:19 PM PDT 24
Peak memory 225488 kb
Host smart-6b51e57c-3da2-45da-b5a3-75f7b67de4d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685039287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2685039287
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.841302932
Short name T213
Test name
Test status
Simulation time 247026733 ps
CPU time 9.94 seconds
Started Jul 20 04:39:04 PM PDT 24
Finished Jul 20 04:39:16 PM PDT 24
Peak memory 225144 kb
Host smart-d2c60e78-d587-47cc-81ea-b9bd24bcc887
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841302932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.841302932
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1641574695
Short name T716
Test name
Test status
Simulation time 531882633 ps
CPU time 7.78 seconds
Started Jul 20 04:39:03 PM PDT 24
Finished Jul 20 04:39:13 PM PDT 24
Peak memory 225428 kb
Host smart-cd590daf-6c0a-4fc9-af3a-a67575511a27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641574695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1641574695
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.534144363
Short name T348
Test name
Test status
Simulation time 7387681080 ps
CPU time 10.62 seconds
Started Jul 20 04:39:04 PM PDT 24
Finished Jul 20 04:39:17 PM PDT 24
Peak memory 217828 kb
Host smart-d98292c5-fa9d-45cb-8c8b-4a26be613eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534144363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.534144363
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2471437193
Short name T382
Test name
Test status
Simulation time 407647878 ps
CPU time 3.44 seconds
Started Jul 20 04:39:04 PM PDT 24
Finished Jul 20 04:39:10 PM PDT 24
Peak memory 217148 kb
Host smart-bbc18e5b-0e5e-478d-886c-da14829fa03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471437193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2471437193
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2350328398
Short name T615
Test name
Test status
Simulation time 237295697 ps
CPU time 20.26 seconds
Started Jul 20 04:39:07 PM PDT 24
Finished Jul 20 04:39:29 PM PDT 24
Peak memory 250488 kb
Host smart-56cfb120-2c97-4ff4-99bf-532d65e3c881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350328398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2350328398
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3467038390
Short name T251
Test name
Test status
Simulation time 281824173 ps
CPU time 7.19 seconds
Started Jul 20 04:39:05 PM PDT 24
Finished Jul 20 04:39:15 PM PDT 24
Peak memory 250420 kb
Host smart-100a34a0-60ab-4ef9-99f5-5ca17268bbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467038390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3467038390
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.91788623
Short name T821
Test name
Test status
Simulation time 7040933058 ps
CPU time 117.14 seconds
Started Jul 20 04:39:05 PM PDT 24
Finished Jul 20 04:41:05 PM PDT 24
Peak memory 250504 kb
Host smart-a2574468-c4d6-4b29-be8b-22cbd832b568
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91788623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.lc_ctrl_stress_all.91788623
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3901406143
Short name T12
Test name
Test status
Simulation time 41251280 ps
CPU time 1.01 seconds
Started Jul 20 04:39:05 PM PDT 24
Finished Jul 20 04:39:09 PM PDT 24
Peak memory 208360 kb
Host smart-b69a822a-8c0f-4272-913e-6603d0f54df4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901406143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3901406143
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2331687068
Short name T477
Test name
Test status
Simulation time 23299952 ps
CPU time 1.25 seconds
Started Jul 20 04:39:08 PM PDT 24
Finished Jul 20 04:39:11 PM PDT 24
Peak memory 208372 kb
Host smart-cd29ac16-3b43-40ad-9d6a-1024d9ca3df1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331687068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2331687068
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3457944309
Short name T414
Test name
Test status
Simulation time 1869244008 ps
CPU time 14.89 seconds
Started Jul 20 04:39:05 PM PDT 24
Finished Jul 20 04:39:22 PM PDT 24
Peak memory 217816 kb
Host smart-f497dca9-e3bc-4d48-b91b-172517d3a0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457944309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3457944309
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.3966969486
Short name T521
Test name
Test status
Simulation time 114041611 ps
CPU time 1.61 seconds
Started Jul 20 04:39:03 PM PDT 24
Finished Jul 20 04:39:07 PM PDT 24
Peak memory 216516 kb
Host smart-c47236f5-30d5-492e-be50-dbb1d80a3601
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966969486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3966969486
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1947299356
Short name T296
Test name
Test status
Simulation time 108524741 ps
CPU time 4.93 seconds
Started Jul 20 04:39:05 PM PDT 24
Finished Jul 20 04:39:12 PM PDT 24
Peak memory 217696 kb
Host smart-e13d2ee6-4217-412f-ba86-a118e26150bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947299356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1947299356
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.210858963
Short name T823
Test name
Test status
Simulation time 1401629783 ps
CPU time 10.69 seconds
Started Jul 20 04:39:04 PM PDT 24
Finished Jul 20 04:39:17 PM PDT 24
Peak memory 224960 kb
Host smart-ee995b1d-d42b-44db-bdb6-0311977adb3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210858963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.210858963
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2768291722
Short name T386
Test name
Test status
Simulation time 408472699 ps
CPU time 10.52 seconds
Started Jul 20 04:39:03 PM PDT 24
Finished Jul 20 04:39:16 PM PDT 24
Peak memory 225368 kb
Host smart-4929c981-3e5f-4002-8ff1-25c4aa8f11dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768291722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2768291722
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.4222702126
Short name T465
Test name
Test status
Simulation time 259134746 ps
CPU time 10.37 seconds
Started Jul 20 04:39:05 PM PDT 24
Finished Jul 20 04:39:19 PM PDT 24
Peak memory 217820 kb
Host smart-7ba15eff-3de1-47ac-ab80-7e713dd776b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222702126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.4222702126
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3007085218
Short name T83
Test name
Test status
Simulation time 78371045 ps
CPU time 3.04 seconds
Started Jul 20 04:39:06 PM PDT 24
Finished Jul 20 04:39:12 PM PDT 24
Peak memory 213864 kb
Host smart-90de974d-84cf-4345-8757-aa39b21c92f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007085218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3007085218
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1644302510
Short name T445
Test name
Test status
Simulation time 292923073 ps
CPU time 29.68 seconds
Started Jul 20 04:39:02 PM PDT 24
Finished Jul 20 04:39:32 PM PDT 24
Peak memory 250472 kb
Host smart-61b6bc77-d272-4366-9ceb-677cc98196e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644302510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1644302510
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1390641998
Short name T746
Test name
Test status
Simulation time 58195423 ps
CPU time 3.07 seconds
Started Jul 20 04:39:05 PM PDT 24
Finished Jul 20 04:39:10 PM PDT 24
Peak memory 217688 kb
Host smart-6865a923-46ff-474f-af31-db69e49d60a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390641998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1390641998
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3527764746
Short name T82
Test name
Test status
Simulation time 994916952 ps
CPU time 21.61 seconds
Started Jul 20 04:39:08 PM PDT 24
Finished Jul 20 04:39:31 PM PDT 24
Peak memory 225444 kb
Host smart-eaad1881-b707-4955-8d8f-047fb4821882
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527764746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3527764746
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.302288947
Short name T153
Test name
Test status
Simulation time 81563364028 ps
CPU time 1352.04 seconds
Started Jul 20 04:39:04 PM PDT 24
Finished Jul 20 05:01:39 PM PDT 24
Peak memory 309292 kb
Host smart-adad6a82-296a-4136-a276-f6d8f2e20f57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=302288947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.302288947
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.568216207
Short name T171
Test name
Test status
Simulation time 16629049 ps
CPU time 0.82 seconds
Started Jul 20 04:39:03 PM PDT 24
Finished Jul 20 04:39:05 PM PDT 24
Peak memory 208316 kb
Host smart-48332fa0-b28d-411d-b837-082f700ef4e5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568216207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.568216207
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3087279727
Short name T745
Test name
Test status
Simulation time 34482688 ps
CPU time 1.22 seconds
Started Jul 20 04:37:06 PM PDT 24
Finished Jul 20 04:37:08 PM PDT 24
Peak memory 208372 kb
Host smart-640bf2e3-25f5-4e08-a13b-8f5947faeb8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087279727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3087279727
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1142380809
Short name T741
Test name
Test status
Simulation time 216049292 ps
CPU time 6.56 seconds
Started Jul 20 04:37:04 PM PDT 24
Finished Jul 20 04:37:12 PM PDT 24
Peak memory 216612 kb
Host smart-814dd34a-15de-44c9-8f2e-9059c184870a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142380809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1142380809
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1801561857
Short name T377
Test name
Test status
Simulation time 9171490373 ps
CPU time 115.39 seconds
Started Jul 20 04:37:04 PM PDT 24
Finished Jul 20 04:39:01 PM PDT 24
Peak memory 219348 kb
Host smart-4837a3b7-86dc-49a8-8dc6-7e2c396c7117
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801561857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1801561857
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2507606485
Short name T547
Test name
Test status
Simulation time 154036246 ps
CPU time 4.82 seconds
Started Jul 20 04:37:02 PM PDT 24
Finished Jul 20 04:37:08 PM PDT 24
Peak memory 217164 kb
Host smart-8ee87fec-dcc7-47de-93b1-e157d46358b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507606485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
507606485
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.4271257313
Short name T339
Test name
Test status
Simulation time 10112230153 ps
CPU time 14.04 seconds
Started Jul 20 04:37:05 PM PDT 24
Finished Jul 20 04:37:20 PM PDT 24
Peak memory 225444 kb
Host smart-c1c30427-d8ca-42fa-9506-fb2ea1b5292b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271257313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.4271257313
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3545763273
Short name T633
Test name
Test status
Simulation time 934644523 ps
CPU time 12.17 seconds
Started Jul 20 04:37:02 PM PDT 24
Finished Jul 20 04:37:15 PM PDT 24
Peak memory 217052 kb
Host smart-35ea0744-6fe8-42e1-951a-8c790edd458c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545763273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3545763273
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1800222628
Short name T174
Test name
Test status
Simulation time 352966718 ps
CPU time 1.95 seconds
Started Jul 20 04:37:05 PM PDT 24
Finished Jul 20 04:37:08 PM PDT 24
Peak memory 217036 kb
Host smart-78e3fdea-2576-4063-9c02-205f1071c298
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800222628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1800222628
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2462194118
Short name T325
Test name
Test status
Simulation time 4685303600 ps
CPU time 63.93 seconds
Started Jul 20 04:37:04 PM PDT 24
Finished Jul 20 04:38:09 PM PDT 24
Peak memory 275072 kb
Host smart-e1c0db7b-1e6a-4664-aafa-648f97ce11fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462194118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2462194118
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1311020085
Short name T496
Test name
Test status
Simulation time 1112911350 ps
CPU time 9.01 seconds
Started Jul 20 04:37:07 PM PDT 24
Finished Jul 20 04:37:16 PM PDT 24
Peak memory 245260 kb
Host smart-c18ba06b-94ac-4572-83cc-9afedbc6b615
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311020085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.1311020085
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3233372372
Short name T430
Test name
Test status
Simulation time 287806343 ps
CPU time 2.9 seconds
Started Jul 20 04:37:04 PM PDT 24
Finished Jul 20 04:37:08 PM PDT 24
Peak memory 222016 kb
Host smart-0b246829-71b4-49b1-aa5d-ce0676754a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233372372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3233372372
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2675085238
Short name T421
Test name
Test status
Simulation time 305523723 ps
CPU time 12.76 seconds
Started Jul 20 04:37:04 PM PDT 24
Finished Jul 20 04:37:18 PM PDT 24
Peak memory 214092 kb
Host smart-f9860af4-a456-4113-9f85-7efbb1d13131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675085238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2675085238
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3849901089
Short name T230
Test name
Test status
Simulation time 1798102678 ps
CPU time 17.9 seconds
Started Jul 20 04:37:04 PM PDT 24
Finished Jul 20 04:37:23 PM PDT 24
Peak memory 217796 kb
Host smart-ec8bdbe7-35cd-442e-9ad6-3a758feb4d62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849901089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3849901089
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2098167032
Short name T309
Test name
Test status
Simulation time 755692766 ps
CPU time 7.94 seconds
Started Jul 20 04:37:04 PM PDT 24
Finished Jul 20 04:37:14 PM PDT 24
Peak memory 225412 kb
Host smart-6c46ccbf-f224-421d-adc0-3b5a0d940171
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098167032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
098167032
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3355808023
Short name T381
Test name
Test status
Simulation time 691024290 ps
CPU time 5.82 seconds
Started Jul 20 04:37:02 PM PDT 24
Finished Jul 20 04:37:09 PM PDT 24
Peak memory 225484 kb
Host smart-a745fde4-b0ba-4a10-9171-4b9e75c07582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355808023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3355808023
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.853881262
Short name T435
Test name
Test status
Simulation time 229868995 ps
CPU time 2.89 seconds
Started Jul 20 04:36:55 PM PDT 24
Finished Jul 20 04:36:59 PM PDT 24
Peak memory 214372 kb
Host smart-cdbe74f0-8b51-4ef3-a43c-d6610eb85972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853881262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.853881262
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1062837829
Short name T619
Test name
Test status
Simulation time 568741701 ps
CPU time 39.61 seconds
Started Jul 20 04:37:06 PM PDT 24
Finished Jul 20 04:37:46 PM PDT 24
Peak memory 250484 kb
Host smart-6f6eba7f-f1a8-4c50-9f73-bc188e0c3fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062837829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1062837829
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3411444289
Short name T367
Test name
Test status
Simulation time 159475325 ps
CPU time 9.86 seconds
Started Jul 20 04:37:03 PM PDT 24
Finished Jul 20 04:37:14 PM PDT 24
Peak memory 250332 kb
Host smart-7a1d6d0c-bec1-43b4-8ae3-82c265e0fcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411444289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3411444289
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1706051030
Short name T766
Test name
Test status
Simulation time 114996679126 ps
CPU time 250.61 seconds
Started Jul 20 04:37:04 PM PDT 24
Finished Jul 20 04:41:16 PM PDT 24
Peak memory 278296 kb
Host smart-2e1ec98a-a4d3-4455-9fc5-09f1e02eda72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706051030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1706051030
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2191939213
Short name T827
Test name
Test status
Simulation time 38748276 ps
CPU time 0.75 seconds
Started Jul 20 04:37:02 PM PDT 24
Finished Jul 20 04:37:04 PM PDT 24
Peak memory 208316 kb
Host smart-f70cabab-2e4d-4d72-ad68-0a39ad765c9b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191939213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2191939213
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.528052501
Short name T402
Test name
Test status
Simulation time 65269036 ps
CPU time 0.95 seconds
Started Jul 20 04:37:12 PM PDT 24
Finished Jul 20 04:37:14 PM PDT 24
Peak memory 208220 kb
Host smart-98659d3c-a8f0-41bd-9ded-bdf1f9398252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528052501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.528052501
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.526298291
Short name T285
Test name
Test status
Simulation time 18206565 ps
CPU time 0.83 seconds
Started Jul 20 04:37:12 PM PDT 24
Finished Jul 20 04:37:13 PM PDT 24
Peak memory 208388 kb
Host smart-62fbdd4c-e49f-4cdf-b64e-1d36cbb0cd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526298291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.526298291
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3036137109
Short name T719
Test name
Test status
Simulation time 646484994 ps
CPU time 15.06 seconds
Started Jul 20 04:37:03 PM PDT 24
Finished Jul 20 04:37:19 PM PDT 24
Peak memory 217768 kb
Host smart-c5c1bf8a-c4e4-4850-a626-da50640e319c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036137109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3036137109
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2176401536
Short name T531
Test name
Test status
Simulation time 6928095920 ps
CPU time 53.89 seconds
Started Jul 20 04:37:12 PM PDT 24
Finished Jul 20 04:38:06 PM PDT 24
Peak memory 218572 kb
Host smart-6fa404cc-f5b7-49c9-b051-0e399a007ff8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176401536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2176401536
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.4027121628
Short name T351
Test name
Test status
Simulation time 1439801440 ps
CPU time 18.21 seconds
Started Jul 20 04:37:13 PM PDT 24
Finished Jul 20 04:37:33 PM PDT 24
Peak memory 217168 kb
Host smart-332bf238-ec4f-4bb8-bc3f-4a14a36be253
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027121628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.4
027121628
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2589758950
Short name T595
Test name
Test status
Simulation time 2746220337 ps
CPU time 10.78 seconds
Started Jul 20 04:37:15 PM PDT 24
Finished Jul 20 04:37:27 PM PDT 24
Peak memory 225504 kb
Host smart-580d1606-e82e-415b-a63d-62f740a90e99
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589758950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2589758950
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.4092503098
Short name T440
Test name
Test status
Simulation time 3999632455 ps
CPU time 16.41 seconds
Started Jul 20 04:37:11 PM PDT 24
Finished Jul 20 04:37:29 PM PDT 24
Peak memory 217052 kb
Host smart-7fb939d4-0275-43c0-9a0f-326430f29915
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092503098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.4092503098
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1972382754
Short name T401
Test name
Test status
Simulation time 94740245 ps
CPU time 3.4 seconds
Started Jul 20 04:37:13 PM PDT 24
Finished Jul 20 04:37:18 PM PDT 24
Peak memory 217032 kb
Host smart-b6ade305-e0e0-4ccc-8f95-9aa00d0ee0b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972382754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1972382754
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3627617357
Short name T221
Test name
Test status
Simulation time 54138260635 ps
CPU time 61.52 seconds
Started Jul 20 04:37:13 PM PDT 24
Finished Jul 20 04:38:16 PM PDT 24
Peak memory 281864 kb
Host smart-206dd2c3-9689-4c0d-a5b1-cea2a78bb9e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627617357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3627617357
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.768835272
Short name T725
Test name
Test status
Simulation time 2233784795 ps
CPU time 19.87 seconds
Started Jul 20 04:37:15 PM PDT 24
Finished Jul 20 04:37:37 PM PDT 24
Peak memory 250476 kb
Host smart-12f8c820-9163-452d-ba28-1d7b4c82de26
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768835272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.768835272
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1549733276
Short name T641
Test name
Test status
Simulation time 101151671 ps
CPU time 2.51 seconds
Started Jul 20 04:37:05 PM PDT 24
Finished Jul 20 04:37:09 PM PDT 24
Peak memory 221780 kb
Host smart-6d271495-52c6-405a-babf-ca1b597375ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549733276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1549733276
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2476972225
Short name T747
Test name
Test status
Simulation time 483063196 ps
CPU time 9.29 seconds
Started Jul 20 04:37:09 PM PDT 24
Finished Jul 20 04:37:19 PM PDT 24
Peak memory 213396 kb
Host smart-4c6169d9-fad4-4cd0-b96d-9052f13b5297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476972225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2476972225
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3980077462
Short name T757
Test name
Test status
Simulation time 1427763175 ps
CPU time 15.55 seconds
Started Jul 20 04:37:12 PM PDT 24
Finished Jul 20 04:37:28 PM PDT 24
Peak memory 225732 kb
Host smart-c96f6687-efa0-4255-b91f-2f8a56175052
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980077462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3980077462
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.896131875
Short name T255
Test name
Test status
Simulation time 1289012713 ps
CPU time 9.5 seconds
Started Jul 20 04:37:15 PM PDT 24
Finished Jul 20 04:37:27 PM PDT 24
Peak memory 217616 kb
Host smart-06ba8f52-c5a9-4455-9a15-08b007322942
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896131875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.896131875
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.915752472
Short name T405
Test name
Test status
Simulation time 964027544 ps
CPU time 6.46 seconds
Started Jul 20 04:37:13 PM PDT 24
Finished Jul 20 04:37:21 PM PDT 24
Peak memory 225468 kb
Host smart-d5b39205-34a0-4fd9-a451-a054e77050a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915752472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.915752472
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2346440621
Short name T211
Test name
Test status
Simulation time 304612929 ps
CPU time 11.14 seconds
Started Jul 20 04:37:07 PM PDT 24
Finished Jul 20 04:37:19 PM PDT 24
Peak memory 225492 kb
Host smart-bf370efd-6b68-4ff0-8dc4-fc69701ff00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346440621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2346440621
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1033254249
Short name T72
Test name
Test status
Simulation time 128475835 ps
CPU time 7.07 seconds
Started Jul 20 04:37:04 PM PDT 24
Finished Jul 20 04:37:13 PM PDT 24
Peak memory 217112 kb
Host smart-1f196b8f-74e8-48d7-9a48-49f080a5c127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033254249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1033254249
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3590479812
Short name T546
Test name
Test status
Simulation time 425651492 ps
CPU time 27.36 seconds
Started Jul 20 04:37:04 PM PDT 24
Finished Jul 20 04:37:33 PM PDT 24
Peak memory 250460 kb
Host smart-12034794-6106-49a7-92f3-913c2f7ee478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590479812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3590479812
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2878463842
Short name T390
Test name
Test status
Simulation time 60078415 ps
CPU time 7.02 seconds
Started Jul 20 04:37:03 PM PDT 24
Finished Jul 20 04:37:11 PM PDT 24
Peak memory 250040 kb
Host smart-da831963-7d4d-4278-9de9-86620f36b89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878463842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2878463842
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1115981243
Short name T47
Test name
Test status
Simulation time 28022630440 ps
CPU time 243.79 seconds
Started Jul 20 04:37:15 PM PDT 24
Finished Jul 20 04:41:21 PM PDT 24
Peak memory 271596 kb
Host smart-050d89a7-815e-4566-9ed5-a2ae7d238629
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115981243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1115981243
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.2451096255
Short name T149
Test name
Test status
Simulation time 94161461513 ps
CPU time 819.76 seconds
Started Jul 20 04:37:14 PM PDT 24
Finished Jul 20 04:50:55 PM PDT 24
Peak memory 372272 kb
Host smart-2c578b0b-0527-438a-bd27-9828c79e11cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2451096255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.2451096255
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2645806185
Short name T293
Test name
Test status
Simulation time 56536330 ps
CPU time 0.94 seconds
Started Jul 20 04:37:03 PM PDT 24
Finished Jul 20 04:37:05 PM PDT 24
Peak memory 208304 kb
Host smart-1f61782c-cad6-42a3-8936-b7c50b7ba7dd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645806185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2645806185
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.4183987904
Short name T403
Test name
Test status
Simulation time 228227641 ps
CPU time 1.7 seconds
Started Jul 20 04:37:15 PM PDT 24
Finished Jul 20 04:37:18 PM PDT 24
Peak memory 208348 kb
Host smart-75582f18-fc0e-4c22-ab93-418e739cd5a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183987904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.4183987904
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2762808220
Short name T647
Test name
Test status
Simulation time 38445608 ps
CPU time 0.88 seconds
Started Jul 20 04:37:15 PM PDT 24
Finished Jul 20 04:37:18 PM PDT 24
Peak memory 208140 kb
Host smart-fb5df8ec-c39a-4c9c-9c30-332872c1e511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762808220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2762808220
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2207061825
Short name T327
Test name
Test status
Simulation time 406648648 ps
CPU time 16.46 seconds
Started Jul 20 04:37:19 PM PDT 24
Finished Jul 20 04:37:36 PM PDT 24
Peak memory 217804 kb
Host smart-32e1b0d2-7a59-4370-8840-95635d5ba28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207061825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2207061825
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.4208633424
Short name T28
Test name
Test status
Simulation time 749215987 ps
CPU time 18.04 seconds
Started Jul 20 04:37:15 PM PDT 24
Finished Jul 20 04:37:35 PM PDT 24
Peak memory 216856 kb
Host smart-ef731a2e-a177-4f87-af19-356cd86a6c4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208633424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.4208633424
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.641186380
Short name T577
Test name
Test status
Simulation time 8533081688 ps
CPU time 62.5 seconds
Started Jul 20 04:37:13 PM PDT 24
Finished Jul 20 04:38:16 PM PDT 24
Peak memory 218352 kb
Host smart-712a8c73-e8cb-4455-a95a-a46ba2a589bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641186380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_err
ors.641186380
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2975506975
Short name T560
Test name
Test status
Simulation time 1268007175 ps
CPU time 7.82 seconds
Started Jul 20 04:37:16 PM PDT 24
Finished Jul 20 04:37:26 PM PDT 24
Peak memory 217224 kb
Host smart-4de1069d-9c1a-448c-ac40-84c095222e1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975506975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
975506975
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3361144039
Short name T717
Test name
Test status
Simulation time 623387007 ps
CPU time 5.2 seconds
Started Jul 20 04:37:15 PM PDT 24
Finished Jul 20 04:37:23 PM PDT 24
Peak memory 221208 kb
Host smart-54af3f33-e12b-49bc-bed9-bcad8e19344b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361144039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.3361144039
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1795456163
Short name T738
Test name
Test status
Simulation time 6991803031 ps
CPU time 23.76 seconds
Started Jul 20 04:37:14 PM PDT 24
Finished Jul 20 04:37:39 PM PDT 24
Peak memory 217228 kb
Host smart-c3dd861b-af3c-47e2-8aa5-4387c09f461c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795456163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1795456163
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1850184862
Short name T79
Test name
Test status
Simulation time 165137788 ps
CPU time 3.77 seconds
Started Jul 20 04:37:12 PM PDT 24
Finished Jul 20 04:37:17 PM PDT 24
Peak memory 217036 kb
Host smart-242e82f5-973d-47ac-9ac7-d8a6fa38d9f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850184862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1850184862
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2733325682
Short name T368
Test name
Test status
Simulation time 12986209848 ps
CPU time 36.42 seconds
Started Jul 20 04:37:12 PM PDT 24
Finished Jul 20 04:37:49 PM PDT 24
Peak memory 250536 kb
Host smart-b3f2f76d-0562-4fd9-a4c4-a71e1d502f8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733325682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2733325682
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2420474808
Short name T415
Test name
Test status
Simulation time 5650224439 ps
CPU time 11.5 seconds
Started Jul 20 04:37:15 PM PDT 24
Finished Jul 20 04:37:29 PM PDT 24
Peak memory 250020 kb
Host smart-3c18d15e-7de4-46a4-ae53-6e1355831f6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420474808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2420474808
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3931876493
Short name T538
Test name
Test status
Simulation time 418558533 ps
CPU time 3.12 seconds
Started Jul 20 04:37:12 PM PDT 24
Finished Jul 20 04:37:17 PM PDT 24
Peak memory 217696 kb
Host smart-daab8840-490e-4561-a0bf-748451959bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931876493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3931876493
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1051336174
Short name T63
Test name
Test status
Simulation time 1566515397 ps
CPU time 21.3 seconds
Started Jul 20 04:37:16 PM PDT 24
Finished Jul 20 04:37:39 PM PDT 24
Peak memory 214268 kb
Host smart-ed5cd22c-ceec-4e50-9625-f001d5f91815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051336174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1051336174
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1445264661
Short name T755
Test name
Test status
Simulation time 382672410 ps
CPU time 13.58 seconds
Started Jul 20 04:37:14 PM PDT 24
Finished Jul 20 04:37:29 PM PDT 24
Peak memory 218296 kb
Host smart-4c147976-0165-4eed-8879-2364b0471150
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445264661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1445264661
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2255107877
Short name T298
Test name
Test status
Simulation time 1019918284 ps
CPU time 23.76 seconds
Started Jul 20 04:37:16 PM PDT 24
Finished Jul 20 04:37:42 PM PDT 24
Peak memory 217728 kb
Host smart-22dc6f74-4b06-41ec-8478-95130e771739
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255107877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2255107877
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2196905870
Short name T357
Test name
Test status
Simulation time 6349205558 ps
CPU time 11.51 seconds
Started Jul 20 04:37:16 PM PDT 24
Finished Jul 20 04:37:29 PM PDT 24
Peak memory 217656 kb
Host smart-d0d37b0f-37b5-4fab-a8f0-6c88fa0ad30b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196905870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
196905870
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.4611081
Short name T457
Test name
Test status
Simulation time 278335962 ps
CPU time 9.06 seconds
Started Jul 20 04:37:12 PM PDT 24
Finished Jul 20 04:37:21 PM PDT 24
Peak memory 217768 kb
Host smart-12120a57-e7ce-4778-89de-5c1ae0dcb547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4611081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.4611081
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.603260013
Short name T241
Test name
Test status
Simulation time 23897129 ps
CPU time 1.89 seconds
Started Jul 20 04:37:16 PM PDT 24
Finished Jul 20 04:37:20 PM PDT 24
Peak memory 213452 kb
Host smart-4462bb8b-fc12-4471-a379-2caaebcd7403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603260013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.603260013
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.655707213
Short name T486
Test name
Test status
Simulation time 2427090368 ps
CPU time 26.12 seconds
Started Jul 20 04:37:13 PM PDT 24
Finished Jul 20 04:37:40 PM PDT 24
Peak memory 250536 kb
Host smart-e8fd9b80-f37f-4e33-b622-fb5f3e893636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655707213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.655707213
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.251091159
Short name T605
Test name
Test status
Simulation time 73026980 ps
CPU time 7.4 seconds
Started Jul 20 04:37:15 PM PDT 24
Finished Jul 20 04:37:24 PM PDT 24
Peak memory 250400 kb
Host smart-a0d21f73-496c-4bce-a52b-5d47424506b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251091159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.251091159
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2237508786
Short name T318
Test name
Test status
Simulation time 9287442493 ps
CPU time 117.05 seconds
Started Jul 20 04:37:12 PM PDT 24
Finished Jul 20 04:39:10 PM PDT 24
Peak memory 332252 kb
Host smart-8c740c78-a8d0-46ff-afce-79de6ebc852c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237508786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2237508786
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.341928252
Short name T714
Test name
Test status
Simulation time 43764672 ps
CPU time 0.78 seconds
Started Jul 20 04:37:14 PM PDT 24
Finished Jul 20 04:37:16 PM PDT 24
Peak memory 208496 kb
Host smart-9231c664-1b9d-4afc-97fc-7196c3e17678
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341928252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.341928252
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2919843393
Short name T508
Test name
Test status
Simulation time 51186700 ps
CPU time 1.02 seconds
Started Jul 20 04:37:23 PM PDT 24
Finished Jul 20 04:37:27 PM PDT 24
Peak memory 208348 kb
Host smart-15bc41e6-8b4b-4a30-ace1-4d9a86cd0dd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919843393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2919843393
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3071866038
Short name T832
Test name
Test status
Simulation time 33127824 ps
CPU time 0.91 seconds
Started Jul 20 04:37:23 PM PDT 24
Finished Jul 20 04:37:25 PM PDT 24
Peak memory 208152 kb
Host smart-4e238875-df30-485e-98c1-f25e2abdd699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071866038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3071866038
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1029263095
Short name T791
Test name
Test status
Simulation time 159487055 ps
CPU time 8.34 seconds
Started Jul 20 04:37:13 PM PDT 24
Finished Jul 20 04:37:22 PM PDT 24
Peak memory 217760 kb
Host smart-7996635d-dd28-4408-9d40-d75dff81b837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029263095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1029263095
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2520549078
Short name T459
Test name
Test status
Simulation time 1187896536 ps
CPU time 19.45 seconds
Started Jul 20 04:37:21 PM PDT 24
Finished Jul 20 04:37:41 PM PDT 24
Peak memory 217096 kb
Host smart-b8bfddf0-10f9-48ce-bd0e-eeeb5e2c08b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520549078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2520549078
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.882248452
Short name T710
Test name
Test status
Simulation time 2483996607 ps
CPU time 24.19 seconds
Started Jul 20 04:37:32 PM PDT 24
Finished Jul 20 04:37:58 PM PDT 24
Peak memory 218332 kb
Host smart-8e894239-5ed5-4bad-b380-7a95b10e08d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882248452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_err
ors.882248452
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.3935882211
Short name T164
Test name
Test status
Simulation time 220837895 ps
CPU time 3.1 seconds
Started Jul 20 04:37:29 PM PDT 24
Finished Jul 20 04:37:33 PM PDT 24
Peak memory 217132 kb
Host smart-92839860-6c1c-4948-870a-5a2b89004ba1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935882211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.3
935882211
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3997334056
Short name T711
Test name
Test status
Simulation time 6243602514 ps
CPU time 10.04 seconds
Started Jul 20 04:37:26 PM PDT 24
Finished Jul 20 04:37:38 PM PDT 24
Peak memory 223276 kb
Host smart-0ba8caaf-5b41-4c8a-8c13-037585be5001
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997334056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3997334056
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2361568936
Short name T540
Test name
Test status
Simulation time 932325852 ps
CPU time 13.96 seconds
Started Jul 20 04:37:23 PM PDT 24
Finished Jul 20 04:37:39 PM PDT 24
Peak memory 217012 kb
Host smart-863969dc-031e-431b-8198-6d14938431dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361568936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2361568936
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1400140453
Short name T551
Test name
Test status
Simulation time 369596475 ps
CPU time 3.41 seconds
Started Jul 20 04:37:24 PM PDT 24
Finished Jul 20 04:37:30 PM PDT 24
Peak memory 217096 kb
Host smart-d072ff44-466c-4378-9a9e-32f7c71fa93a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400140453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1400140453
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3437682029
Short name T387
Test name
Test status
Simulation time 3151144417 ps
CPU time 40.85 seconds
Started Jul 20 04:37:22 PM PDT 24
Finished Jul 20 04:38:05 PM PDT 24
Peak memory 257188 kb
Host smart-49331221-70da-4afb-bf3c-87e0674b5a3b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437682029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3437682029
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3425099186
Short name T586
Test name
Test status
Simulation time 2979219411 ps
CPU time 13.18 seconds
Started Jul 20 04:37:22 PM PDT 24
Finished Jul 20 04:37:38 PM PDT 24
Peak memory 250480 kb
Host smart-a334200b-e0f0-42f0-b8ac-0ed3bdf6bac7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425099186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3425099186
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3596173668
Short name T470
Test name
Test status
Simulation time 38671584 ps
CPU time 1.57 seconds
Started Jul 20 04:37:15 PM PDT 24
Finished Jul 20 04:37:18 PM PDT 24
Peak memory 217744 kb
Host smart-c4fa512b-d72c-46ed-a29a-b78b49e35b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596173668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3596173668
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3735000459
Short name T376
Test name
Test status
Simulation time 270592176 ps
CPU time 7.67 seconds
Started Jul 20 04:37:15 PM PDT 24
Finished Jul 20 04:37:25 PM PDT 24
Peak memory 214036 kb
Host smart-412dc2ec-2a75-40fd-b107-f9e88b7392aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735000459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3735000459
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.4273255090
Short name T651
Test name
Test status
Simulation time 4090176705 ps
CPU time 13.79 seconds
Started Jul 20 04:37:21 PM PDT 24
Finished Jul 20 04:37:36 PM PDT 24
Peak memory 225548 kb
Host smart-c0f6d734-1288-4f98-aaae-df1b4ece81f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273255090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.4273255090
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2567966282
Short name T180
Test name
Test status
Simulation time 249416051 ps
CPU time 11.63 seconds
Started Jul 20 04:37:23 PM PDT 24
Finished Jul 20 04:37:36 PM PDT 24
Peak memory 217628 kb
Host smart-a4701c20-9784-47fe-be4b-118542e2e9e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567966282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2567966282
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3049187540
Short name T640
Test name
Test status
Simulation time 325964025 ps
CPU time 12.23 seconds
Started Jul 20 04:37:24 PM PDT 24
Finished Jul 20 04:37:39 PM PDT 24
Peak memory 225484 kb
Host smart-8ebf6221-8a11-4911-b126-2594f969c74f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049187540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
049187540
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2712598595
Short name T58
Test name
Test status
Simulation time 242788233 ps
CPU time 6.73 seconds
Started Jul 20 04:37:14 PM PDT 24
Finished Jul 20 04:37:22 PM PDT 24
Peak memory 217824 kb
Host smart-0c717cab-db31-4280-a63a-5f1b257147f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712598595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2712598595
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3389807119
Short name T742
Test name
Test status
Simulation time 163313187 ps
CPU time 3.02 seconds
Started Jul 20 04:37:15 PM PDT 24
Finished Jul 20 04:37:20 PM PDT 24
Peak memory 223480 kb
Host smart-0ff2bd07-5a50-46fe-b271-5e17167e151f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389807119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3389807119
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2294217243
Short name T300
Test name
Test status
Simulation time 375589532 ps
CPU time 21.04 seconds
Started Jul 20 04:37:11 PM PDT 24
Finished Jul 20 04:37:32 PM PDT 24
Peak memory 250428 kb
Host smart-ca8ab6cd-5119-4fba-bbd6-79d507820f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294217243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2294217243
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.4197886144
Short name T780
Test name
Test status
Simulation time 63541247 ps
CPU time 6.61 seconds
Started Jul 20 04:37:15 PM PDT 24
Finished Jul 20 04:37:23 PM PDT 24
Peak memory 246364 kb
Host smart-d638d864-28fb-47af-89d7-8ceefe6916ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197886144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.4197886144
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2751612341
Short name T662
Test name
Test status
Simulation time 1511283636 ps
CPU time 63.24 seconds
Started Jul 20 04:37:30 PM PDT 24
Finished Jul 20 04:38:35 PM PDT 24
Peak memory 249780 kb
Host smart-14928b28-4e5e-46fe-9b5b-eb604e3852ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751612341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2751612341
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2810514815
Short name T400
Test name
Test status
Simulation time 63331966 ps
CPU time 1.15 seconds
Started Jul 20 04:37:12 PM PDT 24
Finished Jul 20 04:37:14 PM PDT 24
Peak memory 216988 kb
Host smart-e23e404a-7cb7-40f9-98e9-c4836c1a6917
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810514815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2810514815
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3944932326
Short name T733
Test name
Test status
Simulation time 20733700 ps
CPU time 0.95 seconds
Started Jul 20 04:37:20 PM PDT 24
Finished Jul 20 04:37:22 PM PDT 24
Peak memory 208368 kb
Host smart-ff1609f5-440d-459e-8cd0-9dd37f7e5327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944932326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3944932326
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2906261331
Short name T107
Test name
Test status
Simulation time 13244029 ps
CPU time 0.82 seconds
Started Jul 20 04:37:23 PM PDT 24
Finished Jul 20 04:37:26 PM PDT 24
Peak memory 207968 kb
Host smart-a8349433-34fc-4ed7-b4c3-ed3d993d8ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906261331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2906261331
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.145831666
Short name T461
Test name
Test status
Simulation time 229333869 ps
CPU time 9.69 seconds
Started Jul 20 04:37:23 PM PDT 24
Finished Jul 20 04:37:34 PM PDT 24
Peak memory 217776 kb
Host smart-0c8dada8-f346-4ac2-aaa1-0aecb5def19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145831666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.145831666
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3739569394
Short name T697
Test name
Test status
Simulation time 354744216 ps
CPU time 9.34 seconds
Started Jul 20 04:37:29 PM PDT 24
Finished Jul 20 04:37:40 PM PDT 24
Peak memory 216792 kb
Host smart-017ee9ce-0351-4a39-a961-37deac48b82e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739569394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3739569394
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1747510422
Short name T668
Test name
Test status
Simulation time 5562902860 ps
CPU time 67.92 seconds
Started Jul 20 04:37:23 PM PDT 24
Finished Jul 20 04:38:32 PM PDT 24
Peak memory 218320 kb
Host smart-bc7c7fa5-dec4-48ee-bb5f-270d6fbd0578
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747510422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1747510422
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2946322295
Short name T548
Test name
Test status
Simulation time 689521875 ps
CPU time 6.04 seconds
Started Jul 20 04:37:24 PM PDT 24
Finished Jul 20 04:37:33 PM PDT 24
Peak memory 217148 kb
Host smart-23c17c31-67d2-48b0-8b4c-aee605afe8e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946322295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
946322295
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2136549893
Short name T369
Test name
Test status
Simulation time 1668205156 ps
CPU time 16.72 seconds
Started Jul 20 04:37:22 PM PDT 24
Finished Jul 20 04:37:40 PM PDT 24
Peak memory 225072 kb
Host smart-95d8a333-745a-4a58-8070-6b6b95bd21e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136549893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2136549893
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.343321481
Short name T78
Test name
Test status
Simulation time 4623714645 ps
CPU time 16.46 seconds
Started Jul 20 04:37:27 PM PDT 24
Finished Jul 20 04:37:45 PM PDT 24
Peak memory 217144 kb
Host smart-369ea228-bec2-4eea-8c2c-3b85e39424be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343321481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.343321481
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1679345589
Short name T652
Test name
Test status
Simulation time 500179572 ps
CPU time 11.87 seconds
Started Jul 20 04:37:22 PM PDT 24
Finished Jul 20 04:37:35 PM PDT 24
Peak memory 217036 kb
Host smart-68582ea0-fb00-4b4d-9f97-74d6884b9b9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679345589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1679345589
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.605242574
Short name T792
Test name
Test status
Simulation time 3628683255 ps
CPU time 50.96 seconds
Started Jul 20 04:37:30 PM PDT 24
Finished Jul 20 04:38:22 PM PDT 24
Peak memory 250448 kb
Host smart-31dc9567-236a-4642-a58f-163bcbf877b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605242574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.605242574
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.860473036
Short name T22
Test name
Test status
Simulation time 1332296238 ps
CPU time 11.27 seconds
Started Jul 20 04:37:25 PM PDT 24
Finished Jul 20 04:37:39 PM PDT 24
Peak memory 250372 kb
Host smart-1ccd7b0a-f9b3-4a4b-9c54-fe7298f071b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860473036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.860473036
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3146478632
Short name T724
Test name
Test status
Simulation time 123544652 ps
CPU time 1.43 seconds
Started Jul 20 04:37:24 PM PDT 24
Finished Jul 20 04:37:29 PM PDT 24
Peak memory 217692 kb
Host smart-3db48e3b-3ecd-4089-b0e1-2144878ccd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146478632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3146478632
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1985974823
Short name T450
Test name
Test status
Simulation time 1039067718 ps
CPU time 14.15 seconds
Started Jul 20 04:37:25 PM PDT 24
Finished Jul 20 04:37:41 PM PDT 24
Peak memory 217112 kb
Host smart-2267a96e-ddb7-434c-9765-f5ab7c49e1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985974823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1985974823
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.2543300405
Short name T45
Test name
Test status
Simulation time 271702760 ps
CPU time 9.12 seconds
Started Jul 20 04:37:22 PM PDT 24
Finished Jul 20 04:37:32 PM PDT 24
Peak memory 225480 kb
Host smart-0bd1f70a-4dbd-425a-a316-81bd3836cd0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543300405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2543300405
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2749234807
Short name T695
Test name
Test status
Simulation time 320334404 ps
CPU time 12.3 seconds
Started Jul 20 04:37:22 PM PDT 24
Finished Jul 20 04:37:36 PM PDT 24
Peak memory 217668 kb
Host smart-617b2469-1304-4734-840a-d5f257c6cd24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749234807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2749234807
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2964022447
Short name T657
Test name
Test status
Simulation time 202165135 ps
CPU time 5.51 seconds
Started Jul 20 04:37:24 PM PDT 24
Finished Jul 20 04:37:33 PM PDT 24
Peak memory 224388 kb
Host smart-3af9883e-89d1-42d5-9b8c-36fb3af8cedb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964022447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
964022447
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3257057026
Short name T569
Test name
Test status
Simulation time 275417981 ps
CPU time 7.64 seconds
Started Jul 20 04:37:23 PM PDT 24
Finished Jul 20 04:37:32 PM PDT 24
Peak memory 225532 kb
Host smart-91cc6568-a2a2-4614-8f43-9cdb1888f08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257057026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3257057026
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1086078015
Short name T294
Test name
Test status
Simulation time 96437966 ps
CPU time 1.51 seconds
Started Jul 20 04:37:26 PM PDT 24
Finished Jul 20 04:37:29 PM PDT 24
Peak memory 213344 kb
Host smart-fe60784c-3e81-4829-b075-299fa983916d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086078015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1086078015
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2473386548
Short name T261
Test name
Test status
Simulation time 256831501 ps
CPU time 24.56 seconds
Started Jul 20 04:37:28 PM PDT 24
Finished Jul 20 04:37:54 PM PDT 24
Peak memory 250364 kb
Host smart-88d829a8-73f0-43e8-b73c-6e537a0ab6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473386548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2473386548
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.520713374
Short name T590
Test name
Test status
Simulation time 561850505 ps
CPU time 3.44 seconds
Started Jul 20 04:37:23 PM PDT 24
Finished Jul 20 04:37:29 PM PDT 24
Peak memory 217592 kb
Host smart-362c948a-6371-4346-8484-28e369204402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520713374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.520713374
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3438065212
Short name T341
Test name
Test status
Simulation time 4714054591 ps
CPU time 22.75 seconds
Started Jul 20 04:37:25 PM PDT 24
Finished Jul 20 04:37:50 PM PDT 24
Peak memory 225504 kb
Host smart-f4217d01-d6af-4173-80e3-63b577456a5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438065212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3438065212
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.308255150
Short name T252
Test name
Test status
Simulation time 12213988 ps
CPU time 1 seconds
Started Jul 20 04:37:29 PM PDT 24
Finished Jul 20 04:37:31 PM PDT 24
Peak memory 208356 kb
Host smart-4d16d626-fe13-4dda-bdef-24aff2ddcffe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308255150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.308255150
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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