Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52287 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
68 |
auto[1] |
1651 |
1 |
|
|
T5 |
3 |
|
T10 |
9 |
|
T11 |
9 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53274 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
68 |
auto[1] |
664 |
1 |
|
|
T26 |
21 |
|
T44 |
11 |
|
T59 |
10 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51841 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
68 |
auto[1] |
2097 |
1 |
|
|
T15 |
14 |
|
T17 |
10 |
|
T18 |
38 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51832 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
68 |
auto[1] |
2106 |
1 |
|
|
T15 |
3 |
|
T27 |
1 |
|
T17 |
12 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51840 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
68 |
auto[1] |
2098 |
1 |
|
|
T6 |
1 |
|
T15 |
11 |
|
T17 |
11 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
49087 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
15 |
no_err_inj |
4851 |
1 |
|
|
T4 |
53 |
|
T6 |
7 |
|
T12 |
17 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52231 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
68 |
auto[1] |
1707 |
1 |
|
|
T5 |
4 |
|
T10 |
3 |
|
T11 |
11 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53298 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
68 |
auto[1] |
640 |
1 |
|
|
T26 |
14 |
|
T44 |
23 |
|
T59 |
11 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37450 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[1] |
16488 |
1 |
|
|
T4 |
10 |
|
T5 |
54 |
|
T6 |
14 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51836 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
67 |
auto[1] |
2102 |
1 |
|
|
T4 |
1 |
|
T6 |
2 |
|
T15 |
11 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51959 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
67 |
auto[1] |
1979 |
1 |
|
|
T4 |
1 |
|
T15 |
8 |
|
T17 |
12 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51785 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
67 |
auto[1] |
2153 |
1 |
|
|
T4 |
1 |
|
T6 |
1 |
|
T15 |
8 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52159 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
68 |
auto[1] |
1779 |
1 |
|
|
T5 |
11 |
|
T10 |
12 |
|
T11 |
12 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51677 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[1] |
2261 |
1 |
|
|
T4 |
10 |
|
T14 |
5 |
|
T28 |
20 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53266 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
68 |
auto[1] |
672 |
1 |
|
|
T26 |
25 |
|
T44 |
13 |
|
T59 |
14 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53333 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
68 |
auto[1] |
605 |
1 |
|
|
T26 |
19 |
|
T44 |
15 |
|
T59 |
15 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53273 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
68 |
auto[1] |
665 |
1 |
|
|
T26 |
20 |
|
T44 |
18 |
|
T59 |
14 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51123 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[1] |
2815 |
1 |
|
|
T4 |
10 |
|
T6 |
14 |
|
T15 |
10 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50131 |
1 |
|
|
T3 |
68 |
|
T4 |
68 |
|
T5 |
54 |
auto[1] |
3807 |
1 |
|
|
T2 |
98 |
|
T31 |
67 |
|
T38 |
69 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51915 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
66 |
auto[1] |
2023 |
1 |
|
|
T4 |
2 |
|
T6 |
1 |
|
T15 |
7 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51948 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
68 |
auto[1] |
1990 |
1 |
|
|
T6 |
1 |
|
T15 |
9 |
|
T17 |
5 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51939 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
68 |
auto[1] |
1999 |
1 |
|
|
T6 |
1 |
|
T15 |
11 |
|
T17 |
11 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52212 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
68 |
auto[1] |
1726 |
1 |
|
|
T5 |
9 |
|
T10 |
12 |
|
T11 |
8 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48275 |
1 |
|
|
T2 |
98 |
|
T4 |
68 |
|
T5 |
49 |
auto[1] |
5663 |
1 |
|
|
T3 |
68 |
|
T5 |
5 |
|
T10 |
11 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50350 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
68 |
auto[1] |
3588 |
1 |
|
|
T50 |
77 |
|
T60 |
98 |
|
T61 |
90 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53938 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
68 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52267 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
68 |
auto[1] |
1671 |
1 |
|
|
T5 |
9 |
|
T10 |
8 |
|
T11 |
8 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52258 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
68 |
auto[1] |
1680 |
1 |
|
|
T5 |
8 |
|
T10 |
8 |
|
T11 |
13 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52177 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
68 |
auto[1] |
1761 |
1 |
|
|
T5 |
5 |
|
T10 |
8 |
|
T11 |
11 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
47637 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
10 |
auto[0] |
no_err_inj |
3486 |
1 |
|
|
T4 |
48 |
|
T12 |
17 |
|
T15 |
13 |
auto[1] |
err_inj |
1450 |
1 |
|
|
T4 |
5 |
|
T6 |
7 |
|
T15 |
7 |
auto[1] |
no_err_inj |
1365 |
1 |
|
|
T4 |
5 |
|
T6 |
7 |
|
T15 |
3 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49321 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[0] |
auto[1] |
1802 |
1 |
|
|
T15 |
9 |
|
T17 |
3 |
|
T18 |
42 |
auto[1] |
auto[0] |
2627 |
1 |
|
|
T4 |
10 |
|
T6 |
13 |
|
T15 |
10 |
auto[1] |
auto[1] |
188 |
1 |
|
|
T6 |
1 |
|
T17 |
2 |
|
T18 |
12 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49300 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[0] |
auto[1] |
1823 |
1 |
|
|
T15 |
7 |
|
T17 |
10 |
|
T18 |
31 |
auto[1] |
auto[0] |
2659 |
1 |
|
|
T4 |
9 |
|
T6 |
14 |
|
T15 |
9 |
auto[1] |
auto[1] |
156 |
1 |
|
|
T4 |
1 |
|
T15 |
1 |
|
T17 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49278 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[0] |
auto[1] |
1845 |
1 |
|
|
T15 |
10 |
|
T17 |
11 |
|
T18 |
41 |
auto[1] |
auto[0] |
2661 |
1 |
|
|
T4 |
10 |
|
T6 |
13 |
|
T15 |
9 |
auto[1] |
auto[1] |
154 |
1 |
|
|
T6 |
1 |
|
T15 |
1 |
|
T18 |
8 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49158 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[0] |
auto[1] |
1965 |
1 |
|
|
T15 |
3 |
|
T17 |
11 |
|
T18 |
33 |
auto[1] |
auto[0] |
2674 |
1 |
|
|
T4 |
10 |
|
T6 |
14 |
|
T15 |
10 |
auto[1] |
auto[1] |
141 |
1 |
|
|
T27 |
1 |
|
T17 |
1 |
|
T18 |
5 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49186 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[0] |
auto[1] |
1937 |
1 |
|
|
T15 |
10 |
|
T17 |
11 |
|
T18 |
34 |
auto[1] |
auto[0] |
2654 |
1 |
|
|
T4 |
10 |
|
T6 |
13 |
|
T15 |
9 |
auto[1] |
auto[1] |
161 |
1 |
|
|
T6 |
1 |
|
T15 |
1 |
|
T18 |
4 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49178 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[0] |
auto[1] |
1945 |
1 |
|
|
T15 |
13 |
|
T17 |
9 |
|
T18 |
28 |
auto[1] |
auto[0] |
2663 |
1 |
|
|
T4 |
10 |
|
T6 |
14 |
|
T15 |
9 |
auto[1] |
auto[1] |
152 |
1 |
|
|
T15 |
1 |
|
T17 |
1 |
|
T18 |
10 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36514 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[0] |
auto[1] |
936 |
1 |
|
|
T15 |
11 |
|
T33 |
6 |
|
T17 |
6 |
auto[1] |
auto[0] |
15773 |
1 |
|
|
T4 |
10 |
|
T5 |
51 |
|
T6 |
14 |
auto[1] |
auto[1] |
715 |
1 |
|
|
T5 |
3 |
|
T10 |
9 |
|
T11 |
9 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36483 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[0] |
auto[1] |
967 |
1 |
|
|
T15 |
10 |
|
T33 |
9 |
|
T17 |
15 |
auto[1] |
auto[0] |
15748 |
1 |
|
|
T4 |
10 |
|
T5 |
50 |
|
T6 |
14 |
auto[1] |
auto[1] |
740 |
1 |
|
|
T5 |
4 |
|
T10 |
3 |
|
T11 |
11 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36222 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
48 |
auto[0] |
auto[1] |
1228 |
1 |
|
|
T4 |
10 |
|
T14 |
5 |
|
T28 |
20 |
auto[1] |
auto[0] |
15455 |
1 |
|
|
T4 |
10 |
|
T5 |
54 |
|
T6 |
14 |
auto[1] |
auto[1] |
1033 |
1 |
|
|
T16 |
18 |
|
T18 |
39 |
|
T215 |
9 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36456 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[0] |
auto[1] |
994 |
1 |
|
|
T15 |
16 |
|
T33 |
7 |
|
T17 |
18 |
auto[1] |
auto[0] |
15703 |
1 |
|
|
T4 |
10 |
|
T5 |
43 |
|
T6 |
14 |
auto[1] |
auto[1] |
785 |
1 |
|
|
T5 |
11 |
|
T10 |
12 |
|
T11 |
12 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32509 |
1 |
|
|
T2 |
98 |
|
T4 |
58 |
|
T12 |
17 |
auto[0] |
auto[1] |
4941 |
1 |
|
|
T3 |
68 |
|
T15 |
11 |
|
T29 |
98 |
auto[1] |
auto[0] |
15766 |
1 |
|
|
T4 |
10 |
|
T5 |
49 |
|
T6 |
14 |
auto[1] |
auto[1] |
722 |
1 |
|
|
T5 |
5 |
|
T10 |
11 |
|
T11 |
7 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36300 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[0] |
auto[1] |
1150 |
1 |
|
|
T15 |
9 |
|
T17 |
5 |
|
T18 |
37 |
auto[1] |
auto[0] |
15648 |
1 |
|
|
T4 |
10 |
|
T5 |
54 |
|
T6 |
13 |
auto[1] |
auto[1] |
840 |
1 |
|
|
T6 |
1 |
|
T18 |
17 |
|
T216 |
12 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36220 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[0] |
auto[1] |
1230 |
1 |
|
|
T15 |
7 |
|
T27 |
1 |
|
T17 |
15 |
auto[1] |
auto[0] |
15695 |
1 |
|
|
T4 |
8 |
|
T5 |
54 |
|
T6 |
13 |
auto[1] |
auto[1] |
793 |
1 |
|
|
T4 |
2 |
|
T6 |
1 |
|
T18 |
19 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36266 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[0] |
auto[1] |
1184 |
1 |
|
|
T15 |
7 |
|
T17 |
12 |
|
T18 |
24 |
auto[1] |
auto[0] |
15693 |
1 |
|
|
T4 |
9 |
|
T5 |
54 |
|
T6 |
14 |
auto[1] |
auto[1] |
795 |
1 |
|
|
T4 |
1 |
|
T15 |
1 |
|
T18 |
15 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36170 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[0] |
auto[1] |
1280 |
1 |
|
|
T15 |
8 |
|
T17 |
14 |
|
T18 |
40 |
auto[1] |
auto[0] |
15666 |
1 |
|
|
T4 |
9 |
|
T5 |
54 |
|
T6 |
12 |
auto[1] |
auto[1] |
822 |
1 |
|
|
T4 |
1 |
|
T6 |
2 |
|
T15 |
3 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36196 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[0] |
auto[1] |
1254 |
1 |
|
|
T15 |
3 |
|
T27 |
1 |
|
T17 |
12 |
auto[1] |
auto[0] |
15636 |
1 |
|
|
T4 |
10 |
|
T5 |
54 |
|
T6 |
14 |
auto[1] |
auto[1] |
852 |
1 |
|
|
T18 |
11 |
|
T216 |
14 |
|
T217 |
4 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36201 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[0] |
auto[1] |
1249 |
1 |
|
|
T15 |
13 |
|
T17 |
10 |
|
T18 |
26 |
auto[1] |
auto[0] |
15640 |
1 |
|
|
T4 |
10 |
|
T5 |
54 |
|
T6 |
14 |
auto[1] |
auto[1] |
848 |
1 |
|
|
T15 |
1 |
|
T18 |
12 |
|
T216 |
4 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36432 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[0] |
auto[1] |
1018 |
1 |
|
|
T15 |
13 |
|
T33 |
10 |
|
T17 |
12 |
auto[1] |
auto[0] |
15745 |
1 |
|
|
T4 |
10 |
|
T5 |
49 |
|
T6 |
14 |
auto[1] |
auto[1] |
743 |
1 |
|
|
T5 |
5 |
|
T10 |
8 |
|
T11 |
11 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36481 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[0] |
auto[1] |
969 |
1 |
|
|
T15 |
8 |
|
T33 |
6 |
|
T17 |
16 |
auto[1] |
auto[0] |
15777 |
1 |
|
|
T4 |
10 |
|
T5 |
46 |
|
T6 |
14 |
auto[1] |
auto[1] |
711 |
1 |
|
|
T5 |
8 |
|
T10 |
8 |
|
T11 |
13 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35876 |
1 |
|
|
T2 |
98 |
|
T3 |
68 |
|
T4 |
58 |
auto[0] |
auto[1] |
1574 |
1 |
|
|
T27 |
14 |
|
T17 |
13 |
|
T18 |
32 |
auto[1] |
auto[0] |
15247 |
1 |
|
|
T5 |
54 |
|
T10 |
71 |
|
T11 |
79 |
auto[1] |
auto[1] |
1241 |
1 |
|
|
T4 |
10 |
|
T6 |
14 |
|
T15 |
10 |