Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103979096

1

T1

1264

T2

61219

T3

35976

auto[1]

1443147

1

T2

11386

T4

493

T5

99

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103984812

1

T1

1264

T2

57684

T3

35976

auto[1]

1437431

1

T2

14921

T4

889

T5

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7356375	1			T1	115		T2	8953		T3	7216
auto[IdleSt]	20670552	1			T1	1149		T2	8898		T3	8454
auto[ClkMuxSt]	34332	1			T2	83		T3	68		T4	61
auto[CntIncrSt]	34080	1			T2	81		T3	68		T4	61
auto[CntProgSt]	1492606	1			T2	7646		T3	2952		T4	239
auto[TransCheckSt]	26690	1			T2	55		T3	68		T4	51
auto[TokenHashSt]	43996990	1			T2	26373		T3	3885		T4	173653
auto[FlashRmaSt]	34985	1			T2	144		T4	164		T5	88
auto[TokenCheck0St]	12344	1			T2	34		T4	51		T5	15
auto[TokenCheck1St]	9313	1			T2	33		T4	51		T5	11
auto[TransProgSt]	370556	1			T2	276		T4	215		T5	1755
auto[PostTransSt]	12487567	1			T2	6		T3	13265		T4	28253
auto[ScrapSt]	451445	1			T2	3		T4	70		T12	29
auto[EscalateSt]	6848909	1			T2	20020		T4	15334		T5	1271
auto[InvalidSt]	11593438	1			T4	11937		T6	16383		T15	21028

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2061	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11593438	1			T4	11937		T6	16383		T15	21028
EscalateSt	6848909	1			T2	20020		T4	15334		T5	1271
ScrapSt	451445	1			T2	3		T4	70		T12	29
PostTransSt	12487567	1			T2	6		T3	13265		T4	28253
TransProgSt	370556	1			T2	276		T4	215		T5	1755
TokenCheck1St	9313	1			T2	33		T4	51		T5	11
TokenCheck0St	12344	1			T2	34		T4	51		T5	15
FlashRmaSt	34985	1			T2	144		T4	164		T5	88
TokenHashSt	43996990	1			T2	26373		T3	3885		T4	173653
TransCheckSt	26690	1			T2	55		T3	68		T4	51
CntProgSt	1492606	1			T2	7646		T3	2952		T4	239
CntIncrSt	34080	1			T2	81		T3	68		T4	61
ClkMuxSt	34332	1			T2	83		T3	68		T4	61
IdleSt	20670552	1			T1	1149		T2	8898		T3	8454
ResetSt	7356375	1			T1	115		T2	8953		T3	7216
arcs[ResetSt=>IdleSt]	54020	1			T1	1		T2	94		T3	69
arcs[IdleSt=>ScrapSt]	330	1			T2	1		T4	2		T12	2
arcs[IdleSt=>ClkMuxSt]	34152	1			T2	83		T3	68		T4	61
arcs[ClkMuxSt=>CntIncrSt]	34080	1			T2	81		T3	68		T4	61
arcs[CntIncrSt=>PostTransSt]	1681	1			T5	8		T10	8		T11	13
arcs[CntIncrSt=>CntProgSt]	32339	1			T2	81		T3	68		T4	61
arcs[CntProgSt=>PostTransSt]	4546	1			T4	10		T5	3		T10	9
arcs[CntProgSt=>TransCheckSt]	26690	1			T2	55		T3	68		T4	51
arcs[TransCheckSt=>PostTransSt]	3569	1			T5	5		T10	8		T11	11
arcs[TransCheckSt=>TokenHashSt]	23007	1			T2	54		T3	68		T4	51
arcs[TokenHashSt=>PostTransSt]	9888	1			T3	68		T5	23		T10	31
arcs[TokenHashSt=>FlashRmaSt]	12451	1			T2	41		T4	51		T5	15
arcs[FlashRmaSt=>TokenCheck0St]	12344	1			T2	34		T4	51		T5	15
arcs[TokenCheck0St=>PostTransSt]	3002	1			T5	4		T10	3		T11	11
arcs[TokenCheck0St=>TokenCheck1St]	9313	1			T2	33		T4	51		T5	11
arcs[TokenCheck1St=>PostTransSt]	617	1			T15	2		T17	3		T18	3
arcs[TransProgSt=>PostTransSt]	7768	1			T2	2		T4	51		T5	11
arcs[IdleSt=>EscalateSt]	178	1			T2	9		T54	2		T51	3
arcs[ClkMuxSt=>EscalateSt]	72	1			T2	2		T31	2		T38	1
arcs[CntIncrSt=>EscalateSt]	60	1			T51	2		T52	1		T53	2
arcs[CntProgSt=>EscalateSt]	1103	1			T2	26		T31	10		T38	24
arcs[TransCheckSt=>EscalateSt]	114	1			T2	1		T31	5		T51	6
arcs[TokenHashSt=>EscalateSt]	668	1			T2	13		T31	26		T38	12
arcs[FlashRmaSt=>EscalateSt]	107	1			T2	7		T31	1		T38	3
arcs[TokenCheck0St=>EscalateSt]	29	1			T2	1		T31	1		T38	1
arcs[TokenCheck1St=>EscalateSt]	156	1			T2	2		T31	2		T38	2
arcs[TransProgSt=>EscalateSt]	772	1			T2	29		T31	4		T38	22
arcs[PostTransSt=>EscalateSt]	4811	1			T2	2		T4	10		T5	3
arcs[InvalidSt=>EscalateSt]	15014	1			T4	4		T6	5		T15	63

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7356205	1			T1	115		T2	8950		T3	7216
auto[0]	auto[IdleSt]	20670430	1			T1	1149		T2	8890		T3	8454
auto[0]	auto[ClkMuxSt]	34278	1			T2	82		T3	68		T4	61
auto[0]	auto[CntIncrSt]	34043	1			T2	81		T3	68		T4	61
auto[0]	auto[CntProgSt]	1491877	1			T2	7637		T3	2952		T4	239
auto[0]	auto[TransCheckSt]	26618	1			T2	55		T3	68		T4	51
auto[0]	auto[TokenHashSt]	43996555	1			T2	26365		T3	3885		T4	173653
auto[0]	auto[FlashRmaSt]	34919	1			T2	140		T4	164		T5	88
auto[0]	auto[TokenCheck0St]	12324	1			T2	34		T4	51		T5	15
auto[0]	auto[TokenCheck1St]	9210	1			T2	32		T4	51		T5	11
auto[0]	auto[TransProgSt]	370028	1			T2	257		T4	215		T5	1755
auto[0]	auto[PostTransSt]	12485144	1			T2	4		T3	13265		T4	28250
auto[0]	auto[ScrapSt]	451403	1			T2	2		T4	70		T12	29
auto[0]	auto[EscalateSt]	5418091	1			T2	8690		T4	14846		T5	1173
auto[0]	auto[InvalidSt]	11585910	1			T4	11935		T6	16382		T15	20995
auto[1]	auto[ResetSt]	170	1			T2	3		T31	2		T38	1
auto[1]	auto[IdleSt]	122	1			T2	8		T54	1		T51	1
auto[1]	auto[ClkMuxSt]	54	1			T2	1		T31	2		T38	1
auto[1]	auto[CntIncrSt]	37	1			T51	2		T53	2		T213	1
auto[1]	auto[CntProgSt]	729	1			T2	9		T31	9		T38	15
auto[1]	auto[TransCheckSt]	72	1			T31	2		T51	6		T52	2
auto[1]	auto[TokenHashSt]	435	1			T2	8		T31	20		T38	9
auto[1]	auto[FlashRmaSt]	66	1			T2	4		T31	1		T38	3
auto[1]	auto[TokenCheck0St]	20	1			T31	1		T51	1		T214	3
auto[1]	auto[TokenCheck1St]	103	1			T2	1		T31	2		T38	2
auto[1]	auto[TransProgSt]	528	1			T2	19		T31	3		T38	15
auto[1]	auto[PostTransSt]	2423	1			T2	2		T4	3		T5	1
auto[1]	auto[ScrapSt]	42	1			T2	1		T31	1		T38	1
auto[1]	auto[EscalateSt]	1430818	1			T2	11330		T4	488		T5	98
auto[1]	auto[InvalidSt]	7528	1			T4	2		T6	1		T15	33

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7356217	1			T1	115		T2	8949		T3	7216
auto[0]	auto[IdleSt]	20670435	1			T1	1149		T2	8893		T3	8454
auto[0]	auto[ClkMuxSt]	34283	1			T2	82		T3	68		T4	61
auto[0]	auto[CntIncrSt]	34040	1			T2	81		T3	68		T4	61
auto[0]	auto[CntProgSt]	1491888	1			T2	7623		T3	2952		T4	239
auto[0]	auto[TransCheckSt]	26612	1			T2	54		T3	68		T4	51
auto[0]	auto[TokenHashSt]	43996551	1			T2	26363		T3	3885		T4	173653
auto[0]	auto[FlashRmaSt]	34914	1			T2	138		T4	164		T5	88
auto[0]	auto[TokenCheck0St]	12327	1			T2	33		T4	51		T5	15
auto[0]	auto[TokenCheck1St]	9210	1			T2	32		T4	51		T5	11
auto[0]	auto[TransProgSt]	370036	1			T2	257		T4	215		T5	1755
auto[0]	auto[PostTransSt]	12485091	1			T2	5		T3	13265		T4	28246
auto[0]	auto[ScrapSt]	451400	1			T2	2		T4	70		T12	29
auto[0]	auto[EscalateSt]	5423795	1			T2	5172		T4	14454		T5	1075
auto[0]	auto[InvalidSt]	11585952	1			T4	11935		T6	16379		T15	20998
auto[1]	auto[ResetSt]	158	1			T2	4		T31	2		T38	2
auto[1]	auto[IdleSt]	117	1			T2	5		T54	1		T51	2
auto[1]	auto[ClkMuxSt]	49	1			T2	1		T31	1		T54	1
auto[1]	auto[CntIncrSt]	40	1			T51	1		T52	1		T214	1
auto[1]	auto[CntProgSt]	718	1			T2	23		T31	4		T38	17
auto[1]	auto[TransCheckSt]	78	1			T2	1		T31	5		T51	3
auto[1]	auto[TokenHashSt]	439	1			T2	10		T31	15		T38	7
auto[1]	auto[FlashRmaSt]	71	1			T2	6		T31	1		T38	1
auto[1]	auto[TokenCheck0St]	17	1			T2	1		T31	1		T38	1
auto[1]	auto[TokenCheck1St]	103	1			T2	1		T31	2		T38	1
auto[1]	auto[TransProgSt]	520	1			T2	19		T31	3		T38	13
auto[1]	auto[PostTransSt]	2476	1			T2	1		T4	7		T5	2
auto[1]	auto[ScrapSt]	45	1			T2	1		T31	2		T38	1
auto[1]	auto[EscalateSt]	1425114	1			T2	14848		T4	880		T5	196
auto[1]	auto[InvalidSt]	7486	1			T4	2		T6	4		T15	30