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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.27 97.99 95.95 93.40 100.00 98.55 98.51 96.47


Total test records in report: 990
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T808 /workspace/coverage/default/3.lc_ctrl_alert_test.803159114 Jul 21 07:01:38 PM PDT 24 Jul 21 07:01:39 PM PDT 24 73202879 ps
T809 /workspace/coverage/default/28.lc_ctrl_state_post_trans.1015494572 Jul 21 07:02:31 PM PDT 24 Jul 21 07:02:35 PM PDT 24 240250198 ps
T810 /workspace/coverage/default/0.lc_ctrl_smoke.2725746677 Jul 21 07:01:00 PM PDT 24 Jul 21 07:01:07 PM PDT 24 51536277 ps
T811 /workspace/coverage/default/32.lc_ctrl_alert_test.1712356786 Jul 21 07:02:37 PM PDT 24 Jul 21 07:02:38 PM PDT 24 20905658 ps
T812 /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.4221889498 Jul 21 07:02:51 PM PDT 24 Jul 21 07:10:31 PM PDT 24 16766771910 ps
T209 /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2401841605 Jul 21 07:01:05 PM PDT 24 Jul 21 07:01:12 PM PDT 24 37678615 ps
T813 /workspace/coverage/default/35.lc_ctrl_state_failure.931628429 Jul 21 07:02:52 PM PDT 24 Jul 21 07:03:12 PM PDT 24 153460414 ps
T814 /workspace/coverage/default/29.lc_ctrl_stress_all.1831226798 Jul 21 07:02:38 PM PDT 24 Jul 21 07:08:06 PM PDT 24 41351646144 ps
T815 /workspace/coverage/default/31.lc_ctrl_smoke.3875439439 Jul 21 07:02:43 PM PDT 24 Jul 21 07:02:48 PM PDT 24 422471115 ps
T816 /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1091745948 Jul 21 07:01:45 PM PDT 24 Jul 21 07:01:49 PM PDT 24 872988903 ps
T817 /workspace/coverage/default/26.lc_ctrl_errors.46586151 Jul 21 07:02:33 PM PDT 24 Jul 21 07:02:42 PM PDT 24 212777928 ps
T818 /workspace/coverage/default/35.lc_ctrl_sec_mubi.4063059693 Jul 21 07:02:39 PM PDT 24 Jul 21 07:02:54 PM PDT 24 289236775 ps
T819 /workspace/coverage/default/18.lc_ctrl_state_failure.1803100152 Jul 21 07:02:01 PM PDT 24 Jul 21 07:02:30 PM PDT 24 242643440 ps
T820 /workspace/coverage/default/14.lc_ctrl_stress_all.2496323754 Jul 21 07:01:56 PM PDT 24 Jul 21 07:05:23 PM PDT 24 23533546118 ps
T821 /workspace/coverage/default/45.lc_ctrl_state_post_trans.3637434293 Jul 21 07:02:55 PM PDT 24 Jul 21 07:03:03 PM PDT 24 446717299 ps
T170 /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.527214715 Jul 21 07:01:31 PM PDT 24 Jul 21 07:09:46 PM PDT 24 23921370832 ps
T822 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.4034098450 Jul 21 07:02:59 PM PDT 24 Jul 21 07:03:18 PM PDT 24 4804931240 ps
T823 /workspace/coverage/default/11.lc_ctrl_state_failure.3119362426 Jul 21 07:02:03 PM PDT 24 Jul 21 07:02:28 PM PDT 24 1213995694 ps
T824 /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1562815635 Jul 21 07:01:48 PM PDT 24 Jul 21 07:01:58 PM PDT 24 619633902 ps
T207 /workspace/coverage/default/5.lc_ctrl_claim_transition_if.4063354064 Jul 21 07:01:26 PM PDT 24 Jul 21 07:01:27 PM PDT 24 13387893 ps
T825 /workspace/coverage/default/11.lc_ctrl_smoke.1863042542 Jul 21 07:01:55 PM PDT 24 Jul 21 07:01:59 PM PDT 24 33516671 ps
T826 /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1397784000 Jul 21 07:01:59 PM PDT 24 Jul 21 07:02:56 PM PDT 24 2477010208 ps
T827 /workspace/coverage/default/19.lc_ctrl_stress_all.415457630 Jul 21 07:02:00 PM PDT 24 Jul 21 07:12:19 PM PDT 24 18135374559 ps
T828 /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2451888863 Jul 21 07:01:48 PM PDT 24 Jul 21 07:02:00 PM PDT 24 2788641860 ps
T829 /workspace/coverage/default/14.lc_ctrl_jtag_errors.244639245 Jul 21 07:01:59 PM PDT 24 Jul 21 07:03:07 PM PDT 24 17989967321 ps
T830 /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3771857763 Jul 21 07:01:04 PM PDT 24 Jul 21 07:01:10 PM PDT 24 418150439 ps
T831 /workspace/coverage/default/42.lc_ctrl_alert_test.1348198409 Jul 21 07:02:55 PM PDT 24 Jul 21 07:02:57 PM PDT 24 30615107 ps
T832 /workspace/coverage/default/36.lc_ctrl_smoke.1759463932 Jul 21 07:02:48 PM PDT 24 Jul 21 07:02:56 PM PDT 24 343718257 ps
T833 /workspace/coverage/default/19.lc_ctrl_errors.2870219493 Jul 21 07:02:00 PM PDT 24 Jul 21 07:02:18 PM PDT 24 627285052 ps
T834 /workspace/coverage/default/20.lc_ctrl_sec_token_mux.430314913 Jul 21 07:02:00 PM PDT 24 Jul 21 07:02:11 PM PDT 24 235871337 ps
T835 /workspace/coverage/default/3.lc_ctrl_state_failure.2406890216 Jul 21 07:01:25 PM PDT 24 Jul 21 07:01:55 PM PDT 24 687280625 ps
T836 /workspace/coverage/default/5.lc_ctrl_prog_failure.1328402864 Jul 21 07:01:48 PM PDT 24 Jul 21 07:01:52 PM PDT 24 46514423 ps
T837 /workspace/coverage/default/0.lc_ctrl_prog_failure.553851488 Jul 21 07:01:02 PM PDT 24 Jul 21 07:01:09 PM PDT 24 88474208 ps
T838 /workspace/coverage/default/11.lc_ctrl_prog_failure.922969357 Jul 21 07:01:55 PM PDT 24 Jul 21 07:02:00 PM PDT 24 101288188 ps
T839 /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1573831308 Jul 21 07:01:16 PM PDT 24 Jul 21 07:02:06 PM PDT 24 5896518865 ps
T840 /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.64052313 Jul 21 07:01:53 PM PDT 24 Jul 21 07:03:28 PM PDT 24 7659004933 ps
T841 /workspace/coverage/default/4.lc_ctrl_prog_failure.1713957903 Jul 21 07:01:42 PM PDT 24 Jul 21 07:01:46 PM PDT 24 106280950 ps
T842 /workspace/coverage/default/23.lc_ctrl_security_escalation.2080566965 Jul 21 07:02:27 PM PDT 24 Jul 21 07:02:40 PM PDT 24 353526540 ps
T843 /workspace/coverage/default/40.lc_ctrl_security_escalation.254689912 Jul 21 07:02:52 PM PDT 24 Jul 21 07:03:09 PM PDT 24 878012315 ps
T48 /workspace/coverage/default/19.lc_ctrl_jtag_errors.2699023756 Jul 21 07:02:16 PM PDT 24 Jul 21 07:03:00 PM PDT 24 7009151137 ps
T844 /workspace/coverage/default/25.lc_ctrl_prog_failure.77815872 Jul 21 07:02:22 PM PDT 24 Jul 21 07:02:26 PM PDT 24 194913860 ps
T845 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.894399404 Jul 21 07:02:56 PM PDT 24 Jul 21 07:02:58 PM PDT 24 14032099 ps
T846 /workspace/coverage/default/13.lc_ctrl_alert_test.158408236 Jul 21 07:02:02 PM PDT 24 Jul 21 07:02:05 PM PDT 24 51102663 ps
T847 /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3197365424 Jul 21 07:01:43 PM PDT 24 Jul 21 07:01:46 PM PDT 24 2058382175 ps
T848 /workspace/coverage/default/29.lc_ctrl_smoke.2559264821 Jul 21 07:02:40 PM PDT 24 Jul 21 07:02:42 PM PDT 24 100449563 ps
T849 /workspace/coverage/default/9.lc_ctrl_state_post_trans.3992264924 Jul 21 07:01:43 PM PDT 24 Jul 21 07:01:54 PM PDT 24 70947535 ps
T850 /workspace/coverage/default/49.lc_ctrl_alert_test.3539581586 Jul 21 07:03:24 PM PDT 24 Jul 21 07:03:25 PM PDT 24 16741113 ps
T851 /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2151433277 Jul 21 07:02:33 PM PDT 24 Jul 21 07:02:45 PM PDT 24 653481627 ps
T852 /workspace/coverage/default/30.lc_ctrl_state_post_trans.4034824458 Jul 21 07:02:41 PM PDT 24 Jul 21 07:02:48 PM PDT 24 125352406 ps
T853 /workspace/coverage/default/10.lc_ctrl_state_post_trans.1584553513 Jul 21 07:01:48 PM PDT 24 Jul 21 07:01:53 PM PDT 24 245974801 ps
T854 /workspace/coverage/default/22.lc_ctrl_stress_all.3337078373 Jul 21 07:02:04 PM PDT 24 Jul 21 07:06:51 PM PDT 24 9064224978 ps
T855 /workspace/coverage/default/19.lc_ctrl_state_failure.4192251110 Jul 21 07:02:11 PM PDT 24 Jul 21 07:02:42 PM PDT 24 7344220867 ps
T856 /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2814358373 Jul 21 07:01:12 PM PDT 24 Jul 21 07:01:23 PM PDT 24 1120956154 ps
T857 /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3064801885 Jul 21 07:01:48 PM PDT 24 Jul 21 07:01:58 PM PDT 24 983438501 ps
T858 /workspace/coverage/default/15.lc_ctrl_state_post_trans.272878001 Jul 21 07:02:06 PM PDT 24 Jul 21 07:02:16 PM PDT 24 399512796 ps
T123 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2227053078 Jul 21 04:52:39 PM PDT 24 Jul 21 04:52:41 PM PDT 24 76332983 ps
T110 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1723266932 Jul 21 04:52:31 PM PDT 24 Jul 21 04:52:35 PM PDT 24 1609739930 ps
T124 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2267300487 Jul 21 04:52:44 PM PDT 24 Jul 21 04:52:46 PM PDT 24 19970735 ps
T859 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1950375019 Jul 21 04:52:40 PM PDT 24 Jul 21 04:52:42 PM PDT 24 17473907 ps
T147 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.814386774 Jul 21 04:52:56 PM PDT 24 Jul 21 04:52:59 PM PDT 24 156218845 ps
T118 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2032256504 Jul 21 04:53:19 PM PDT 24 Jul 21 04:53:21 PM PDT 24 16292182 ps
T145 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2150604887 Jul 21 04:52:54 PM PDT 24 Jul 21 04:52:59 PM PDT 24 141027357 ps
T119 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1360495017 Jul 21 04:53:12 PM PDT 24 Jul 21 04:53:13 PM PDT 24 328971094 ps
T148 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.52222930 Jul 21 04:52:45 PM PDT 24 Jul 21 04:52:48 PM PDT 24 94410648 ps
T159 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3863455008 Jul 21 04:53:08 PM PDT 24 Jul 21 04:53:09 PM PDT 24 28042687 ps
T860 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1552364840 Jul 21 04:52:47 PM PDT 24 Jul 21 04:52:50 PM PDT 24 18109891 ps
T111 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.508327513 Jul 21 04:53:06 PM PDT 24 Jul 21 04:53:11 PM PDT 24 545938155 ps
T146 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2632268953 Jul 21 04:53:11 PM PDT 24 Jul 21 04:53:13 PM PDT 24 134558093 ps
T143 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3258176742 Jul 21 04:52:56 PM PDT 24 Jul 21 04:53:01 PM PDT 24 82134616 ps
T116 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1776776532 Jul 21 04:52:52 PM PDT 24 Jul 21 04:52:56 PM PDT 24 578267993 ps
T144 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.804094379 Jul 21 04:52:49 PM PDT 24 Jul 21 04:52:52 PM PDT 24 290211002 ps
T198 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.590818736 Jul 21 04:53:02 PM PDT 24 Jul 21 04:53:05 PM PDT 24 23239672 ps
T861 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2866542636 Jul 21 04:52:54 PM PDT 24 Jul 21 04:52:57 PM PDT 24 21057734 ps
T112 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.4086574496 Jul 21 04:52:58 PM PDT 24 Jul 21 04:53:04 PM PDT 24 124330690 ps
T114 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1767863217 Jul 21 04:53:05 PM PDT 24 Jul 21 04:53:09 PM PDT 24 75332642 ps
T117 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2938569228 Jul 21 04:52:45 PM PDT 24 Jul 21 04:52:49 PM PDT 24 536166617 ps
T862 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.644892028 Jul 21 04:53:04 PM PDT 24 Jul 21 04:53:26 PM PDT 24 952675418 ps
T199 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2503049663 Jul 21 04:52:52 PM PDT 24 Jul 21 04:52:54 PM PDT 24 33150804 ps
T863 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3239798399 Jul 21 04:52:58 PM PDT 24 Jul 21 04:53:01 PM PDT 24 417340841 ps
T864 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4162946297 Jul 21 04:52:50 PM PDT 24 Jul 21 04:52:52 PM PDT 24 246740734 ps
T120 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.462991799 Jul 21 04:53:15 PM PDT 24 Jul 21 04:53:23 PM PDT 24 29381969 ps
T865 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3043261330 Jul 21 04:52:57 PM PDT 24 Jul 21 04:53:01 PM PDT 24 727400838 ps
T171 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.220472553 Jul 21 04:52:56 PM PDT 24 Jul 21 04:52:59 PM PDT 24 20256152 ps
T866 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2418649666 Jul 21 04:53:05 PM PDT 24 Jul 21 04:53:06 PM PDT 24 14649489 ps
T867 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1742495495 Jul 21 04:52:52 PM PDT 24 Jul 21 04:52:54 PM PDT 24 44964586 ps
T868 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2910867080 Jul 21 04:52:45 PM PDT 24 Jul 21 04:52:48 PM PDT 24 20547736 ps
T121 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.252021156 Jul 21 04:53:02 PM PDT 24 Jul 21 04:53:06 PM PDT 24 112404755 ps
T200 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1398848142 Jul 21 04:52:53 PM PDT 24 Jul 21 04:52:56 PM PDT 24 121441968 ps
T115 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3797991895 Jul 21 04:52:59 PM PDT 24 Jul 21 04:53:03 PM PDT 24 475652484 ps
T201 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1672891274 Jul 21 04:53:14 PM PDT 24 Jul 21 04:53:17 PM PDT 24 108300714 ps
T128 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.301905641 Jul 21 04:52:53 PM PDT 24 Jul 21 04:52:56 PM PDT 24 355889788 ps
T130 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4020233652 Jul 21 04:53:02 PM PDT 24 Jul 21 04:53:06 PM PDT 24 39374109 ps
T869 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.746197737 Jul 21 04:53:08 PM PDT 24 Jul 21 04:53:09 PM PDT 24 15732096 ps
T870 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2377825080 Jul 21 04:52:59 PM PDT 24 Jul 21 04:53:01 PM PDT 24 45084622 ps
T202 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.529681500 Jul 21 04:53:20 PM PDT 24 Jul 21 04:53:22 PM PDT 24 215663356 ps
T871 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.535242394 Jul 21 04:53:14 PM PDT 24 Jul 21 04:53:17 PM PDT 24 24499371 ps
T872 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3883424467 Jul 21 04:53:00 PM PDT 24 Jul 21 04:53:02 PM PDT 24 28507976 ps
T873 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1405929585 Jul 21 04:53:15 PM PDT 24 Jul 21 04:53:16 PM PDT 24 55040246 ps
T874 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3763030461 Jul 21 04:52:54 PM PDT 24 Jul 21 04:52:58 PM PDT 24 246499974 ps
T203 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2910041258 Jul 21 04:53:13 PM PDT 24 Jul 21 04:53:15 PM PDT 24 29962936 ps
T137 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.72713986 Jul 21 04:52:50 PM PDT 24 Jul 21 04:52:53 PM PDT 24 469660010 ps
T204 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.125005621 Jul 21 04:52:54 PM PDT 24 Jul 21 04:52:56 PM PDT 24 84519447 ps
T205 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.747749226 Jul 21 04:53:00 PM PDT 24 Jul 21 04:53:02 PM PDT 24 25110146 ps
T133 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3002515796 Jul 21 04:52:52 PM PDT 24 Jul 21 04:52:55 PM PDT 24 611697959 ps
T875 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1244606202 Jul 21 04:53:03 PM PDT 24 Jul 21 04:53:11 PM PDT 24 2647630263 ps
T876 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.373327018 Jul 21 04:52:44 PM PDT 24 Jul 21 04:52:46 PM PDT 24 133315855 ps
T877 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3358483324 Jul 21 04:52:59 PM PDT 24 Jul 21 04:53:01 PM PDT 24 29498741 ps
T131 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2220933843 Jul 21 04:52:56 PM PDT 24 Jul 21 04:53:01 PM PDT 24 207087731 ps
T878 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4239297310 Jul 21 04:53:20 PM PDT 24 Jul 21 04:53:27 PM PDT 24 21831379 ps
T879 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.73893129 Jul 21 04:52:57 PM PDT 24 Jul 21 04:53:00 PM PDT 24 84996884 ps
T880 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2487972061 Jul 21 04:53:14 PM PDT 24 Jul 21 04:53:16 PM PDT 24 347635061 ps
T881 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4195746942 Jul 21 04:52:58 PM PDT 24 Jul 21 04:53:01 PM PDT 24 20875240 ps
T882 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3781093186 Jul 21 04:52:45 PM PDT 24 Jul 21 04:52:47 PM PDT 24 35423674 ps
T883 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2477613990 Jul 21 04:52:39 PM PDT 24 Jul 21 04:52:41 PM PDT 24 85998601 ps
T884 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.939614747 Jul 21 04:52:46 PM PDT 24 Jul 21 04:52:48 PM PDT 24 87932981 ps
T885 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3832916827 Jul 21 04:52:38 PM PDT 24 Jul 21 04:52:40 PM PDT 24 44685881 ps
T134 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.586609565 Jul 21 04:52:57 PM PDT 24 Jul 21 04:53:02 PM PDT 24 251342951 ps
T886 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1096546477 Jul 21 04:52:51 PM PDT 24 Jul 21 04:52:53 PM PDT 24 33970364 ps
T887 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1342289729 Jul 21 04:52:51 PM PDT 24 Jul 21 04:52:53 PM PDT 24 35994926 ps
T888 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1445961605 Jul 21 04:52:32 PM PDT 24 Jul 21 04:52:33 PM PDT 24 48152776 ps
T889 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.799768500 Jul 21 04:52:56 PM PDT 24 Jul 21 04:52:59 PM PDT 24 41144731 ps
T890 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.753352464 Jul 21 04:52:52 PM PDT 24 Jul 21 04:52:55 PM PDT 24 123360505 ps
T891 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.492828989 Jul 21 04:52:39 PM PDT 24 Jul 21 04:52:41 PM PDT 24 316442814 ps
T892 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1269935816 Jul 21 04:52:49 PM PDT 24 Jul 21 04:53:14 PM PDT 24 9059248637 ps
T127 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2161828036 Jul 21 04:53:17 PM PDT 24 Jul 21 04:53:21 PM PDT 24 356953847 ps
T893 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.368045406 Jul 21 04:52:47 PM PDT 24 Jul 21 04:52:49 PM PDT 24 73367020 ps
T894 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.532887071 Jul 21 04:52:55 PM PDT 24 Jul 21 04:52:59 PM PDT 24 51585735 ps
T895 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4131383377 Jul 21 04:52:37 PM PDT 24 Jul 21 04:52:53 PM PDT 24 1177869321 ps
T896 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.4169602526 Jul 21 04:52:51 PM PDT 24 Jul 21 04:52:54 PM PDT 24 56688078 ps
T132 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3947428308 Jul 21 04:52:52 PM PDT 24 Jul 21 04:52:56 PM PDT 24 118935237 ps
T897 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3022615383 Jul 21 04:52:46 PM PDT 24 Jul 21 04:52:48 PM PDT 24 20291548 ps
T898 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1618913997 Jul 21 04:53:04 PM PDT 24 Jul 21 04:53:12 PM PDT 24 52876083 ps
T899 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4111222456 Jul 21 04:52:50 PM PDT 24 Jul 21 04:52:52 PM PDT 24 20437301 ps
T900 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.518130215 Jul 21 04:53:11 PM PDT 24 Jul 21 04:53:13 PM PDT 24 21347252 ps
T192 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2899754631 Jul 21 04:52:53 PM PDT 24 Jul 21 04:52:55 PM PDT 24 441350910 ps
T901 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.4262711290 Jul 21 04:52:41 PM PDT 24 Jul 21 04:52:45 PM PDT 24 250606360 ps
T902 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3674455277 Jul 21 04:52:40 PM PDT 24 Jul 21 04:52:43 PM PDT 24 155478939 ps
T129 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1815426906 Jul 21 04:53:00 PM PDT 24 Jul 21 04:53:03 PM PDT 24 105842012 ps
T903 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1425226685 Jul 21 04:52:53 PM PDT 24 Jul 21 04:53:03 PM PDT 24 4836662013 ps
T904 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.670672588 Jul 21 04:53:02 PM PDT 24 Jul 21 04:53:05 PM PDT 24 103827503 ps
T905 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2060752242 Jul 21 04:52:46 PM PDT 24 Jul 21 04:52:49 PM PDT 24 48675485 ps
T906 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.810552473 Jul 21 04:53:02 PM PDT 24 Jul 21 04:53:05 PM PDT 24 77137024 ps
T193 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1810041346 Jul 21 04:52:40 PM PDT 24 Jul 21 04:52:42 PM PDT 24 33554932 ps
T907 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2333086848 Jul 21 04:52:33 PM PDT 24 Jul 21 04:52:35 PM PDT 24 58952517 ps
T908 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2579574672 Jul 21 04:53:14 PM PDT 24 Jul 21 04:53:16 PM PDT 24 21064809 ps
T909 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3600423558 Jul 21 04:52:46 PM PDT 24 Jul 21 04:52:48 PM PDT 24 48139681 ps
T910 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1413059080 Jul 21 04:52:58 PM PDT 24 Jul 21 04:53:02 PM PDT 24 44429616 ps
T194 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2920657858 Jul 21 04:52:59 PM PDT 24 Jul 21 04:53:01 PM PDT 24 15451682 ps
T911 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2572905191 Jul 21 04:52:38 PM PDT 24 Jul 21 04:52:40 PM PDT 24 211461568 ps
T912 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3354397737 Jul 21 04:52:46 PM PDT 24 Jul 21 04:53:09 PM PDT 24 1935636944 ps
T913 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3782313136 Jul 21 04:53:02 PM PDT 24 Jul 21 04:53:07 PM PDT 24 78931947 ps
T914 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.254876800 Jul 21 04:52:55 PM PDT 24 Jul 21 04:52:59 PM PDT 24 79902984 ps
T915 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1790759091 Jul 21 04:52:54 PM PDT 24 Jul 21 04:52:59 PM PDT 24 45396812 ps
T916 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.4269268978 Jul 21 04:53:04 PM PDT 24 Jul 21 04:53:06 PM PDT 24 80173288 ps
T917 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1674103766 Jul 21 04:52:53 PM PDT 24 Jul 21 04:52:57 PM PDT 24 218307444 ps
T918 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2804959846 Jul 21 04:52:47 PM PDT 24 Jul 21 04:52:50 PM PDT 24 104303317 ps
T919 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.4119075200 Jul 21 04:52:45 PM PDT 24 Jul 21 04:52:47 PM PDT 24 172175037 ps
T920 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2457711269 Jul 21 04:53:02 PM PDT 24 Jul 21 04:53:05 PM PDT 24 244221723 ps
T921 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1787048537 Jul 21 04:52:48 PM PDT 24 Jul 21 04:52:51 PM PDT 24 666407858 ps
T922 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1429965083 Jul 21 04:53:17 PM PDT 24 Jul 21 04:53:22 PM PDT 24 352613680 ps
T923 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2482386991 Jul 21 04:52:56 PM PDT 24 Jul 21 04:53:02 PM PDT 24 207795389 ps
T924 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.346795067 Jul 21 04:52:54 PM PDT 24 Jul 21 04:52:58 PM PDT 24 42177400 ps
T925 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4059862097 Jul 21 04:52:54 PM PDT 24 Jul 21 04:52:57 PM PDT 24 140143034 ps
T926 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3071832073 Jul 21 04:52:37 PM PDT 24 Jul 21 04:52:45 PM PDT 24 6062827021 ps
T927 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3972350001 Jul 21 04:53:09 PM PDT 24 Jul 21 04:53:10 PM PDT 24 79619913 ps
T136 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.678031806 Jul 21 04:53:08 PM PDT 24 Jul 21 04:53:11 PM PDT 24 826251614 ps
T141 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2306943861 Jul 21 04:52:46 PM PDT 24 Jul 21 04:52:50 PM PDT 24 92803816 ps
T928 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.167874989 Jul 21 04:53:03 PM PDT 24 Jul 21 04:53:05 PM PDT 24 477818272 ps
T929 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2124309001 Jul 21 04:53:13 PM PDT 24 Jul 21 04:53:16 PM PDT 24 240884420 ps
T930 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.875765340 Jul 21 04:52:50 PM PDT 24 Jul 21 04:52:53 PM PDT 24 34468808 ps
T931 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3616758161 Jul 21 04:52:46 PM PDT 24 Jul 21 04:52:49 PM PDT 24 30076322 ps
T932 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3510618305 Jul 21 04:52:44 PM PDT 24 Jul 21 04:53:01 PM PDT 24 4133119551 ps
T933 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1299911087 Jul 21 04:52:38 PM PDT 24 Jul 21 04:53:03 PM PDT 24 4402799303 ps
T934 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.222134201 Jul 21 04:53:02 PM PDT 24 Jul 21 04:53:18 PM PDT 24 764117669 ps
T935 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2334759254 Jul 21 04:52:54 PM PDT 24 Jul 21 04:52:59 PM PDT 24 250889802 ps
T936 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3397870952 Jul 21 04:52:59 PM PDT 24 Jul 21 04:53:02 PM PDT 24 85504757 ps
T937 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3429070381 Jul 21 04:52:45 PM PDT 24 Jul 21 04:52:48 PM PDT 24 336976918 ps
T938 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1382012730 Jul 21 04:52:44 PM PDT 24 Jul 21 04:52:47 PM PDT 24 33591915 ps
T939 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2771262180 Jul 21 04:52:51 PM PDT 24 Jul 21 04:52:56 PM PDT 24 2073405919 ps
T940 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.207968578 Jul 21 04:52:56 PM PDT 24 Jul 21 04:53:00 PM PDT 24 232324587 ps
T941 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1457701231 Jul 21 04:52:54 PM PDT 24 Jul 21 04:53:05 PM PDT 24 355241108 ps
T942 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2725677123 Jul 21 04:52:56 PM PDT 24 Jul 21 04:52:59 PM PDT 24 42920956 ps
T943 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2403967542 Jul 21 04:52:46 PM PDT 24 Jul 21 04:52:56 PM PDT 24 1477807984 ps
T944 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.197164465 Jul 21 04:52:54 PM PDT 24 Jul 21 04:52:57 PM PDT 24 47637220 ps
T945 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1862157076 Jul 21 04:52:40 PM PDT 24 Jul 21 04:52:42 PM PDT 24 24818478 ps
T946 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3635782067 Jul 21 04:52:40 PM PDT 24 Jul 21 04:52:44 PM PDT 24 390082037 ps
T947 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.929800550 Jul 21 04:52:54 PM PDT 24 Jul 21 04:52:58 PM PDT 24 46421607 ps
T948 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2802706804 Jul 21 04:53:10 PM PDT 24 Jul 21 04:53:13 PM PDT 24 566544887 ps
T949 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2093117986 Jul 21 04:53:03 PM PDT 24 Jul 21 04:53:07 PM PDT 24 81680617 ps
T950 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1268413928 Jul 21 04:52:26 PM PDT 24 Jul 21 04:52:29 PM PDT 24 709596198 ps
T951 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4049052833 Jul 21 04:52:57 PM PDT 24 Jul 21 04:53:00 PM PDT 24 403142302 ps
T952 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1308527047 Jul 21 04:53:03 PM PDT 24 Jul 21 04:53:09 PM PDT 24 473732487 ps
T953 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1978421159 Jul 21 04:53:02 PM PDT 24 Jul 21 04:53:06 PM PDT 24 166480353 ps
T135 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3978257750 Jul 21 04:52:56 PM PDT 24 Jul 21 04:53:01 PM PDT 24 229179388 ps
T954 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.69897610 Jul 21 04:52:44 PM PDT 24 Jul 21 04:52:46 PM PDT 24 580743584 ps
T955 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2324078498 Jul 21 04:52:45 PM PDT 24 Jul 21 04:52:48 PM PDT 24 130882417 ps
T956 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.884898749 Jul 21 04:52:38 PM PDT 24 Jul 21 04:52:40 PM PDT 24 126655160 ps
T957 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3795546895 Jul 21 04:52:54 PM PDT 24 Jul 21 04:52:59 PM PDT 24 830288031 ps
T958 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1877825635 Jul 21 04:53:03 PM PDT 24 Jul 21 04:53:05 PM PDT 24 36587170 ps
T959 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.291127889 Jul 21 04:53:15 PM PDT 24 Jul 21 04:53:16 PM PDT 24 32041002 ps
T960 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.649393541 Jul 21 04:52:56 PM PDT 24 Jul 21 04:53:00 PM PDT 24 35436935 ps
T961 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.580765039 Jul 21 04:53:24 PM PDT 24 Jul 21 04:53:31 PM PDT 24 262969830 ps
T962 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1847934429 Jul 21 04:52:53 PM PDT 24 Jul 21 04:52:55 PM PDT 24 14451912 ps
T963 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2520065832 Jul 21 04:52:59 PM PDT 24 Jul 21 04:53:01 PM PDT 24 33211369 ps
T964 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.700495842 Jul 21 04:53:04 PM PDT 24 Jul 21 04:53:07 PM PDT 24 41043971 ps
T195 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2303605445 Jul 21 04:52:58 PM PDT 24 Jul 21 04:53:01 PM PDT 24 18336952 ps
T965 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1234447158 Jul 21 04:52:56 PM PDT 24 Jul 21 04:53:00 PM PDT 24 21957264 ps
T966 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.873033313 Jul 21 04:52:54 PM PDT 24 Jul 21 04:52:58 PM PDT 24 16760437 ps
T967 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1780847265 Jul 21 04:52:56 PM PDT 24 Jul 21 04:53:01 PM PDT 24 99664122 ps
T968 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1525306338 Jul 21 04:52:40 PM PDT 24 Jul 21 04:52:49 PM PDT 24 1024469155 ps
T196 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3338894979 Jul 21 04:52:45 PM PDT 24 Jul 21 04:52:48 PM PDT 24 18120913 ps
T969 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3576452888 Jul 21 04:52:41 PM PDT 24 Jul 21 04:52:44 PM PDT 24 62933446 ps
T139 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2682922607 Jul 21 04:52:43 PM PDT 24 Jul 21 04:52:46 PM PDT 24 44824039 ps
T970 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1358921893 Jul 21 04:52:50 PM PDT 24 Jul 21 04:52:52 PM PDT 24 56797353 ps
T971 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3787191263 Jul 21 04:52:50 PM PDT 24 Jul 21 04:52:53 PM PDT 24 107289351 ps
T140 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2746743664 Jul 21 04:52:56 PM PDT 24 Jul 21 04:53:01 PM PDT 24 116774309 ps
T972 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2127352853 Jul 21 04:52:54 PM PDT 24 Jul 21 04:53:00 PM PDT 24 7520889419 ps
T973 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.928473890 Jul 21 04:53:00 PM PDT 24 Jul 21 04:53:04 PM PDT 24 145699303 ps
T974 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.371146354 Jul 21 04:52:44 PM PDT 24 Jul 21 04:52:47 PM PDT 24 120107838 ps
T975 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1756511241 Jul 21 04:53:01 PM PDT 24 Jul 21 04:53:04 PM PDT 24 119596936 ps
T976 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.126271853 Jul 21 04:52:36 PM PDT 24 Jul 21 04:52:37 PM PDT 24 22483824 ps
T977 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.787883003 Jul 21 04:53:10 PM PDT 24 Jul 21 04:53:11 PM PDT 24 98095258 ps
T978 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.392439716 Jul 21 04:53:06 PM PDT 24 Jul 21 04:53:13 PM PDT 24 26478346 ps
T979 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.988394033 Jul 21 04:52:53 PM PDT 24 Jul 21 04:52:56 PM PDT 24 25731954 ps
T980 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1378066142 Jul 21 04:53:00 PM PDT 24 Jul 21 04:53:02 PM PDT 24 107317483 ps
T138 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2719526488 Jul 21 04:52:47 PM PDT 24 Jul 21 04:52:51 PM PDT 24 326026160 ps
T981 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3826698865 Jul 21 04:52:54 PM PDT 24 Jul 21 04:53:04 PM PDT 24 638879100 ps
T982 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2411340864 Jul 21 04:53:11 PM PDT 24 Jul 21 04:53:19 PM PDT 24 1389737155 ps
T983 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3463388184 Jul 21 04:52:45 PM PDT 24 Jul 21 04:52:47 PM PDT 24 57203907 ps
T984 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2765349764 Jul 21 04:52:44 PM PDT 24 Jul 21 04:52:47 PM PDT 24 148196149 ps
T197 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1890056907 Jul 21 04:52:40 PM PDT 24 Jul 21 04:52:42 PM PDT 24 35113530 ps
T985 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.4235429420 Jul 21 04:53:02 PM PDT 24 Jul 21 04:53:06 PM PDT 24 34076199 ps
T986 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.434595889 Jul 21 04:52:46 PM PDT 24 Jul 21 04:52:49 PM PDT 24 100801912 ps
T122 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3566798445 Jul 21 04:53:02 PM PDT 24 Jul 21 04:53:05 PM PDT 24 227549226 ps
T125 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2528303920 Jul 21 04:52:57 PM PDT 24 Jul 21 04:53:02 PM PDT 24 314630580 ps
T126 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3236958897 Jul 21 04:53:09 PM PDT 24 Jul 21 04:53:12 PM PDT 24 73132249 ps
T987 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3024249225 Jul 21 04:52:53 PM PDT 24 Jul 21 04:52:56 PM PDT 24 198984801 ps
T988 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1319479722 Jul 21 04:52:54 PM PDT 24 Jul 21 04:53:14 PM PDT 24 804009305 ps
T989 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1996983324 Jul 21 04:52:38 PM PDT 24 Jul 21 04:52:41 PM PDT 24 166428406 ps
T990 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2766505418 Jul 21 04:52:40 PM PDT 24 Jul 21 04:52:42 PM PDT 24 52425825 ps

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.354472788
Short name T4
Test name
Test status
Simulation time 27020577128 ps
CPU time 54.31 seconds
Started Jul 21 07:01:53 PM PDT 24
Finished Jul 21 07:02:49 PM PDT 24
Peak memory 250612 kb
Host smart-2261116c-70f8-4b54-8998-38525cd6fd09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354472788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.354472788
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.1376568720
Short name T18
Test name
Test status
Simulation time 110428463322 ps
CPU time 797.51 seconds
Started Jul 21 07:02:40 PM PDT 24
Finished Jul 21 07:15:58 PM PDT 24
Peak memory 332748 kb
Host smart-fed0a793-cb8b-4119-a3fa-9a37ad8931f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1376568720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.1376568720
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2043707755
Short name T2
Test name
Test status
Simulation time 3025294731 ps
CPU time 16.2 seconds
Started Jul 21 07:01:54 PM PDT 24
Finished Jul 21 07:02:12 PM PDT 24
Peak memory 225668 kb
Host smart-e2978ed4-1fe2-429a-a37c-1568b0755692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043707755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2043707755
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2343234753
Short name T26
Test name
Test status
Simulation time 306976686 ps
CPU time 15.68 seconds
Started Jul 21 07:03:07 PM PDT 24
Finished Jul 21 07:03:24 PM PDT 24
Peak memory 218488 kb
Host smart-823140c2-dfbe-4a63-85f4-d79c3898bc29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343234753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2343234753
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1860223811
Short name T15
Test name
Test status
Simulation time 205470526837 ps
CPU time 367.68 seconds
Started Jul 21 07:01:29 PM PDT 24
Finished Jul 21 07:07:38 PM PDT 24
Peak memory 278076 kb
Host smart-ab4d997d-5107-4770-b42e-9bbfc9e61b18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860223811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1860223811
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1723266932
Short name T110
Test name
Test status
Simulation time 1609739930 ps
CPU time 2.94 seconds
Started Jul 21 04:52:31 PM PDT 24
Finished Jul 21 04:52:35 PM PDT 24
Peak memory 222528 kb
Host smart-077dd8c1-66a0-4d95-aa20-43d0c3a9e9f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723266932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1723266932
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1183970969
Short name T34
Test name
Test status
Simulation time 14564410 ps
CPU time 0.85 seconds
Started Jul 21 07:01:07 PM PDT 24
Finished Jul 21 07:01:10 PM PDT 24
Peak memory 208624 kb
Host smart-157e93d7-ad91-49d0-9558-18cf2ffd7d2b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183970969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1183970969
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1434432543
Short name T97
Test name
Test status
Simulation time 428319202 ps
CPU time 38.32 seconds
Started Jul 21 07:01:29 PM PDT 24
Finished Jul 21 07:02:07 PM PDT 24
Peak memory 284180 kb
Host smart-87bcdce4-5ae8-4456-9cc1-34bf31ff431f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434432543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1434432543
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3637043045
Short name T51
Test name
Test status
Simulation time 393061162 ps
CPU time 14.57 seconds
Started Jul 21 07:02:12 PM PDT 24
Finished Jul 21 07:02:32 PM PDT 24
Peak memory 217884 kb
Host smart-0681b5da-9077-4fc8-b54d-4ae1beaf236d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637043045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3637043045
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2938569228
Short name T117
Test name
Test status
Simulation time 536166617 ps
CPU time 2.14 seconds
Started Jul 21 04:52:45 PM PDT 24
Finished Jul 21 04:52:49 PM PDT 24
Peak memory 218092 kb
Host smart-2dcc16fd-6909-4660-820d-d6c173954137
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293856
9228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2938569228
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3523741724
Short name T7
Test name
Test status
Simulation time 253830978 ps
CPU time 4.43 seconds
Started Jul 21 07:01:03 PM PDT 24
Finished Jul 21 07:01:11 PM PDT 24
Peak memory 216956 kb
Host smart-370d0594-f8dd-4950-972a-3a5e563ae8fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523741724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3523741724
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3005176084
Short name T169
Test name
Test status
Simulation time 685663454 ps
CPU time 7.79 seconds
Started Jul 21 07:02:37 PM PDT 24
Finished Jul 21 07:02:45 PM PDT 24
Peak memory 217828 kb
Host smart-2870eae0-3550-41d5-8c52-7ff390a4462c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005176084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3005176084
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1612343277
Short name T1
Test name
Test status
Simulation time 115054756 ps
CPU time 1.02 seconds
Started Jul 21 07:01:28 PM PDT 24
Finished Jul 21 07:01:29 PM PDT 24
Peak memory 208432 kb
Host smart-0a1c18a1-74a7-437e-b4ec-a3fbb41bb5ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612343277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1612343277
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2748533517
Short name T50
Test name
Test status
Simulation time 4609293495 ps
CPU time 10.16 seconds
Started Jul 21 07:02:00 PM PDT 24
Finished Jul 21 07:02:13 PM PDT 24
Peak memory 225560 kb
Host smart-a1bb544e-27a1-40be-b2dd-ece84bf356ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748533517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2748533517
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1810041346
Short name T193
Test name
Test status
Simulation time 33554932 ps
CPU time 1.25 seconds
Started Jul 21 04:52:40 PM PDT 24
Finished Jul 21 04:52:42 PM PDT 24
Peak memory 209580 kb
Host smart-273bcb6b-e247-4751-ab02-a2f378527b49
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810041346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1810041346
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.2006904136
Short name T94
Test name
Test status
Simulation time 33970773379 ps
CPU time 810.42 seconds
Started Jul 21 07:02:56 PM PDT 24
Finished Jul 21 07:16:33 PM PDT 24
Peak memory 529364 kb
Host smart-c4a14ec8-8814-497e-8607-24b1a9906e57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2006904136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.2006904136
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3236958897
Short name T126
Test name
Test status
Simulation time 73132249 ps
CPU time 2.78 seconds
Started Jul 21 04:53:09 PM PDT 24
Finished Jul 21 04:53:12 PM PDT 24
Peak memory 222440 kb
Host smart-255ae7bf-fd97-4ab4-86c0-b9aff154fb56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236958897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3236958897
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1767863217
Short name T114
Test name
Test status
Simulation time 75332642 ps
CPU time 3.35 seconds
Started Jul 21 04:53:05 PM PDT 24
Finished Jul 21 04:53:09 PM PDT 24
Peak memory 222316 kb
Host smart-07ca019e-5ac8-4aa6-bf6c-85244b671d09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767863217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1767863217
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2349712227
Short name T12
Test name
Test status
Simulation time 194214183 ps
CPU time 3.11 seconds
Started Jul 21 07:01:58 PM PDT 24
Finished Jul 21 07:02:03 PM PDT 24
Peak memory 213824 kb
Host smart-4e60738d-9867-4abe-9bff-1a9c03b9a596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349712227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2349712227
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.4262711290
Short name T901
Test name
Test status
Simulation time 250606360 ps
CPU time 3 seconds
Started Jul 21 04:52:41 PM PDT 24
Finished Jul 21 04:52:45 PM PDT 24
Peak memory 217736 kb
Host smart-172f5601-fa84-4026-9a61-83c19253b988
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262711290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.4262711290
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2161828036
Short name T127
Test name
Test status
Simulation time 356953847 ps
CPU time 3.81 seconds
Started Jul 21 04:53:17 PM PDT 24
Finished Jul 21 04:53:21 PM PDT 24
Peak memory 222492 kb
Host smart-d6727047-c435-4cdc-9b3a-39eefa360817
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161828036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2161828036
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3566798445
Short name T122
Test name
Test status
Simulation time 227549226 ps
CPU time 1.97 seconds
Started Jul 21 04:53:02 PM PDT 24
Finished Jul 21 04:53:05 PM PDT 24
Peak memory 221928 kb
Host smart-5ae56833-73fe-4bbf-adfd-1924f60683d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566798445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3566798445
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1360495017
Short name T119
Test name
Test status
Simulation time 328971094 ps
CPU time 1.01 seconds
Started Jul 21 04:53:12 PM PDT 24
Finished Jul 21 04:53:13 PM PDT 24
Peak memory 209476 kb
Host smart-2fb8f2e8-8202-4b1a-b055-a7fdc4e2c6c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360495017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.1360495017
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.4211778435
Short name T142
Test name
Test status
Simulation time 36086119 ps
CPU time 0.86 seconds
Started Jul 21 07:01:51 PM PDT 24
Finished Jul 21 07:01:54 PM PDT 24
Peak memory 208168 kb
Host smart-7a3bcbd2-6d32-474f-be3e-0b7c0e66f67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211778435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.4211778435
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.586609565
Short name T134
Test name
Test status
Simulation time 251342951 ps
CPU time 2.87 seconds
Started Jul 21 04:52:57 PM PDT 24
Finished Jul 21 04:53:02 PM PDT 24
Peak memory 222280 kb
Host smart-362906c1-6dc0-4225-99c4-23be3f23a603
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586609565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_
err.586609565
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2306943861
Short name T141
Test name
Test status
Simulation time 92803816 ps
CPU time 2.75 seconds
Started Jul 21 04:52:46 PM PDT 24
Finished Jul 21 04:52:50 PM PDT 24
Peak memory 222508 kb
Host smart-4047ff77-272b-4bdd-a9c4-923b5f51efb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306943861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2306943861
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1809217964
Short name T208
Test name
Test status
Simulation time 63521037 ps
CPU time 0.76 seconds
Started Jul 21 07:01:06 PM PDT 24
Finished Jul 21 07:01:09 PM PDT 24
Peak memory 208508 kb
Host smart-55119d79-a39b-4ba2-99d3-0c35417fd6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809217964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1809217964
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2401841605
Short name T209
Test name
Test status
Simulation time 37678615 ps
CPU time 0.77 seconds
Started Jul 21 07:01:05 PM PDT 24
Finished Jul 21 07:01:12 PM PDT 24
Peak memory 208588 kb
Host smart-324ce05c-facc-48eb-a667-7ec58559933d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401841605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2401841605
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2343519679
Short name T211
Test name
Test status
Simulation time 34829993 ps
CPU time 0.91 seconds
Started Jul 21 07:01:18 PM PDT 24
Finished Jul 21 07:01:19 PM PDT 24
Peak memory 208220 kb
Host smart-5c85e4bb-8156-4c25-9b0f-f13fbb86bdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343519679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2343519679
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3949406071
Short name T212
Test name
Test status
Simulation time 13518406 ps
CPU time 0.91 seconds
Started Jul 21 07:01:45 PM PDT 24
Finished Jul 21 07:01:47 PM PDT 24
Peak memory 208152 kb
Host smart-dd9f958f-3e62-434a-a677-564ce8d53367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949406071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3949406071
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1765027289
Short name T29
Test name
Test status
Simulation time 639505233 ps
CPU time 14.17 seconds
Started Jul 21 07:02:39 PM PDT 24
Finished Jul 21 07:02:54 PM PDT 24
Peak memory 225496 kb
Host smart-653689e6-e7cd-443b-8e10-5d3d22cf1d13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765027289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1765027289
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1445961605
Short name T888
Test name
Test status
Simulation time 48152776 ps
CPU time 1.12 seconds
Started Jul 21 04:52:32 PM PDT 24
Finished Jul 21 04:52:33 PM PDT 24
Peak memory 209424 kb
Host smart-da7431fb-469b-47e6-ba86-9ffb3cda30e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445961605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1445961605
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2220933843
Short name T131
Test name
Test status
Simulation time 207087731 ps
CPU time 2.65 seconds
Started Jul 21 04:52:56 PM PDT 24
Finished Jul 21 04:53:01 PM PDT 24
Peak memory 217684 kb
Host smart-694573e1-5fa0-4d2a-8bbb-58427d35467b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220933843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2220933843
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3002515796
Short name T133
Test name
Test status
Simulation time 611697959 ps
CPU time 3.04 seconds
Started Jul 21 04:52:52 PM PDT 24
Finished Jul 21 04:52:55 PM PDT 24
Peak memory 222424 kb
Host smart-86e6ffbe-c318-4ded-aa3b-be3c6ebb6a81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002515796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3002515796
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.678031806
Short name T136
Test name
Test status
Simulation time 826251614 ps
CPU time 3.08 seconds
Started Jul 21 04:53:08 PM PDT 24
Finished Jul 21 04:53:11 PM PDT 24
Peak memory 222548 kb
Host smart-da3d6685-bc2e-41bf-9a34-c3d551218ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678031806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.678031806
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1141547170
Short name T47
Test name
Test status
Simulation time 6177786280 ps
CPU time 49.81 seconds
Started Jul 21 07:01:59 PM PDT 24
Finished Jul 21 07:02:51 PM PDT 24
Peak memory 225608 kb
Host smart-4693678d-6bb6-4ba2-8d62-229f0bccbefc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141547170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1141547170
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3172347449
Short name T16
Test name
Test status
Simulation time 2939321134 ps
CPU time 10.86 seconds
Started Jul 21 07:02:04 PM PDT 24
Finished Jul 21 07:02:18 PM PDT 24
Peak memory 225584 kb
Host smart-81790d71-4f75-4085-a7f5-38424748dc99
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172347449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3172347449
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.371146354
Short name T974
Test name
Test status
Simulation time 120107838 ps
CPU time 1.71 seconds
Started Jul 21 04:52:44 PM PDT 24
Finished Jul 21 04:52:47 PM PDT 24
Peak memory 208432 kb
Host smart-1ea372f6-f1f7-4148-bab8-f93ccb6aba96
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371146354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash
.371146354
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.126271853
Short name T976
Test name
Test status
Simulation time 22483824 ps
CPU time 1.09 seconds
Started Jul 21 04:52:36 PM PDT 24
Finished Jul 21 04:52:37 PM PDT 24
Peak memory 211648 kb
Host smart-b8228509-61bc-465f-96c6-a11f1e9e5797
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126271853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.126271853
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2333086848
Short name T907
Test name
Test status
Simulation time 58952517 ps
CPU time 1.07 seconds
Started Jul 21 04:52:33 PM PDT 24
Finished Jul 21 04:52:35 PM PDT 24
Peak memory 218724 kb
Host smart-1c578766-6732-43b1-a56e-c719935aadd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333086848 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2333086848
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2227053078
Short name T123
Test name
Test status
Simulation time 76332983 ps
CPU time 0.99 seconds
Started Jul 21 04:52:39 PM PDT 24
Finished Jul 21 04:52:41 PM PDT 24
Peak memory 209508 kb
Host smart-a9c27c7b-c2a2-4313-8183-ff6138188a4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227053078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2227053078
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.492828989
Short name T891
Test name
Test status
Simulation time 316442814 ps
CPU time 1.51 seconds
Started Jul 21 04:52:39 PM PDT 24
Finished Jul 21 04:52:41 PM PDT 24
Peak memory 208092 kb
Host smart-ff51eb0a-bc5c-415b-ab56-dedbe885399b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492828989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.492828989
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3071832073
Short name T926
Test name
Test status
Simulation time 6062827021 ps
CPU time 8.04 seconds
Started Jul 21 04:52:37 PM PDT 24
Finished Jul 21 04:52:45 PM PDT 24
Peak memory 208820 kb
Host smart-bea857c3-4c86-48fc-8f5d-d385dd4be8ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071832073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3071832073
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1299911087
Short name T933
Test name
Test status
Simulation time 4402799303 ps
CPU time 24.23 seconds
Started Jul 21 04:52:38 PM PDT 24
Finished Jul 21 04:53:03 PM PDT 24
Peak memory 209576 kb
Host smart-4f9f224d-da09-4ce7-ae0f-27a69885e326
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299911087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1299911087
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1268413928
Short name T950
Test name
Test status
Simulation time 709596198 ps
CPU time 1.99 seconds
Started Jul 21 04:52:26 PM PDT 24
Finished Jul 21 04:52:29 PM PDT 24
Peak memory 211168 kb
Host smart-ce5e77ed-25d6-477f-a4ed-89e7aa81d148
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268413928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1268413928
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2572905191
Short name T911
Test name
Test status
Simulation time 211461568 ps
CPU time 1.54 seconds
Started Jul 21 04:52:38 PM PDT 24
Finished Jul 21 04:52:40 PM PDT 24
Peak memory 217964 kb
Host smart-cc759203-8e99-4a73-967f-ef5a1859a180
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257290
5191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2572905191
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2477613990
Short name T883
Test name
Test status
Simulation time 85998601 ps
CPU time 1.44 seconds
Started Jul 21 04:52:39 PM PDT 24
Finished Jul 21 04:52:41 PM PDT 24
Peak memory 209324 kb
Host smart-ed7fe844-bb88-4372-9935-4bdd16e0bcd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477613990 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2477613990
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3832916827
Short name T885
Test name
Test status
Simulation time 44685881 ps
CPU time 1.11 seconds
Started Jul 21 04:52:38 PM PDT 24
Finished Jul 21 04:52:40 PM PDT 24
Peak memory 209580 kb
Host smart-aec144c2-1f9f-4754-98d5-4e59674cbc55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832916827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3832916827
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1996983324
Short name T989
Test name
Test status
Simulation time 166428406 ps
CPU time 2.29 seconds
Started Jul 21 04:52:38 PM PDT 24
Finished Jul 21 04:52:41 PM PDT 24
Peak memory 217556 kb
Host smart-548878b0-2491-4fe6-82a3-94acd68b5a63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996983324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1996983324
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3338894979
Short name T196
Test name
Test status
Simulation time 18120913 ps
CPU time 1.38 seconds
Started Jul 21 04:52:45 PM PDT 24
Finished Jul 21 04:52:48 PM PDT 24
Peak memory 209640 kb
Host smart-84fce4d3-42c7-498d-aa34-8a091a10ba3d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338894979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3338894979
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3674455277
Short name T902
Test name
Test status
Simulation time 155478939 ps
CPU time 1.84 seconds
Started Jul 21 04:52:40 PM PDT 24
Finished Jul 21 04:52:43 PM PDT 24
Peak memory 208748 kb
Host smart-3c64e47a-e2d0-448e-8f75-3913b3779ab2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674455277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3674455277
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1890056907
Short name T197
Test name
Test status
Simulation time 35113530 ps
CPU time 1.07 seconds
Started Jul 21 04:52:40 PM PDT 24
Finished Jul 21 04:52:42 PM PDT 24
Peak memory 211040 kb
Host smart-7290a0b2-3f1c-4d4d-bc1e-193d8a1995db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890056907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1890056907
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3576452888
Short name T969
Test name
Test status
Simulation time 62933446 ps
CPU time 2.07 seconds
Started Jul 21 04:52:41 PM PDT 24
Finished Jul 21 04:52:44 PM PDT 24
Peak memory 217924 kb
Host smart-93b053b9-fae9-46e4-9816-367a74b36e74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576452888 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3576452888
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1950375019
Short name T859
Test name
Test status
Simulation time 17473907 ps
CPU time 1.11 seconds
Started Jul 21 04:52:40 PM PDT 24
Finished Jul 21 04:52:42 PM PDT 24
Peak memory 209320 kb
Host smart-ad9a8541-b13f-47b7-9b73-abc66682981c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950375019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1950375019
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.4119075200
Short name T919
Test name
Test status
Simulation time 172175037 ps
CPU time 1.16 seconds
Started Jul 21 04:52:45 PM PDT 24
Finished Jul 21 04:52:47 PM PDT 24
Peak memory 209384 kb
Host smart-63635b23-0ec0-4f0a-80e1-76df6e6b95be
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119075200 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.4119075200
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1525306338
Short name T968
Test name
Test status
Simulation time 1024469155 ps
CPU time 7.44 seconds
Started Jul 21 04:52:40 PM PDT 24
Finished Jul 21 04:52:49 PM PDT 24
Peak memory 209268 kb
Host smart-cb953a7a-9dbd-4a60-8a1f-48b8b604db0b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525306338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1525306338
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4131383377
Short name T895
Test name
Test status
Simulation time 1177869321 ps
CPU time 14.48 seconds
Started Jul 21 04:52:37 PM PDT 24
Finished Jul 21 04:52:53 PM PDT 24
Peak memory 209496 kb
Host smart-36b62cf3-09ab-41fb-a9b2-5f55d14fc76c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131383377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.4131383377
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.884898749
Short name T956
Test name
Test status
Simulation time 126655160 ps
CPU time 1.51 seconds
Started Jul 21 04:52:38 PM PDT 24
Finished Jul 21 04:52:40 PM PDT 24
Peak memory 210996 kb
Host smart-d22512e4-dffe-4e6b-ba88-67c4d6fe1b56
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884898749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.884898749
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.373327018
Short name T876
Test name
Test status
Simulation time 133315855 ps
CPU time 2.39 seconds
Started Jul 21 04:52:44 PM PDT 24
Finished Jul 21 04:52:46 PM PDT 24
Peak memory 217788 kb
Host smart-7b71c7a1-292c-4800-8868-fc66aed515dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373327
018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.373327018
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3781093186
Short name T882
Test name
Test status
Simulation time 35423674 ps
CPU time 1.47 seconds
Started Jul 21 04:52:45 PM PDT 24
Finished Jul 21 04:52:47 PM PDT 24
Peak memory 209556 kb
Host smart-1ee7e7ff-d2a8-4f04-bf43-90dcca273bd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781093186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3781093186
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1862157076
Short name T945
Test name
Test status
Simulation time 24818478 ps
CPU time 1.07 seconds
Started Jul 21 04:52:40 PM PDT 24
Finished Jul 21 04:52:42 PM PDT 24
Peak memory 209532 kb
Host smart-bdda3e96-0fa0-4c32-8733-833241ef52cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862157076 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1862157076
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2766505418
Short name T990
Test name
Test status
Simulation time 52425825 ps
CPU time 1.39 seconds
Started Jul 21 04:52:40 PM PDT 24
Finished Jul 21 04:52:42 PM PDT 24
Peak memory 209496 kb
Host smart-c1035d2f-93b8-454c-af19-785fc197a04a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766505418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2766505418
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2682922607
Short name T139
Test name
Test status
Simulation time 44824039 ps
CPU time 2.56 seconds
Started Jul 21 04:52:43 PM PDT 24
Finished Jul 21 04:52:46 PM PDT 24
Peak memory 222460 kb
Host smart-0f087403-12ec-471d-afbe-0500eec3a72f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682922607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2682922607
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.167874989
Short name T928
Test name
Test status
Simulation time 477818272 ps
CPU time 1.24 seconds
Started Jul 21 04:53:03 PM PDT 24
Finished Jul 21 04:53:05 PM PDT 24
Peak memory 218860 kb
Host smart-98464edd-e1fe-42eb-bac7-519926e8283f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167874989 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.167874989
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1877825635
Short name T958
Test name
Test status
Simulation time 36587170 ps
CPU time 0.84 seconds
Started Jul 21 04:53:03 PM PDT 24
Finished Jul 21 04:53:05 PM PDT 24
Peak memory 209444 kb
Host smart-5f12a647-175a-45b3-ab63-5dec71a12d07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877825635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1877825635
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1790759091
Short name T915
Test name
Test status
Simulation time 45396812 ps
CPU time 2.67 seconds
Started Jul 21 04:52:54 PM PDT 24
Finished Jul 21 04:52:59 PM PDT 24
Peak memory 217684 kb
Host smart-6f7ea0ce-2f07-4966-b04c-73c583a4bdaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790759091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1790759091
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4195746942
Short name T881
Test name
Test status
Simulation time 20875240 ps
CPU time 1.02 seconds
Started Jul 21 04:52:58 PM PDT 24
Finished Jul 21 04:53:01 PM PDT 24
Peak memory 219268 kb
Host smart-bca6c977-de86-4e88-8d82-76ae75ccedaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195746942 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.4195746942
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2303605445
Short name T195
Test name
Test status
Simulation time 18336952 ps
CPU time 0.95 seconds
Started Jul 21 04:52:58 PM PDT 24
Finished Jul 21 04:53:01 PM PDT 24
Peak memory 209476 kb
Host smart-920a474a-d6d7-4cac-8f64-690f2101e254
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303605445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2303605445
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2579574672
Short name T908
Test name
Test status
Simulation time 21064809 ps
CPU time 1.47 seconds
Started Jul 21 04:53:14 PM PDT 24
Finished Jul 21 04:53:16 PM PDT 24
Peak memory 211920 kb
Host smart-58ae6ca5-8d20-4380-8206-99e11916736e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579574672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.2579574672
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1618913997
Short name T898
Test name
Test status
Simulation time 52876083 ps
CPU time 2.11 seconds
Started Jul 21 04:53:04 PM PDT 24
Finished Jul 21 04:53:12 PM PDT 24
Peak memory 218028 kb
Host smart-58a57823-637d-43c8-8c7e-7ee0995fb989
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618913997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1618913997
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2528303920
Short name T125
Test name
Test status
Simulation time 314630580 ps
CPU time 2.69 seconds
Started Jul 21 04:52:57 PM PDT 24
Finished Jul 21 04:53:02 PM PDT 24
Peak memory 222240 kb
Host smart-3037a30a-0e56-4d2e-a2cf-b3284ee07ed2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528303920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2528303920
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2487972061
Short name T880
Test name
Test status
Simulation time 347635061 ps
CPU time 1.37 seconds
Started Jul 21 04:53:14 PM PDT 24
Finished Jul 21 04:53:16 PM PDT 24
Peak memory 217816 kb
Host smart-b3fffd1a-3b65-4976-bc48-a0d85ce5f6d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487972061 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2487972061
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2520065832
Short name T963
Test name
Test status
Simulation time 33211369 ps
CPU time 0.91 seconds
Started Jul 21 04:52:59 PM PDT 24
Finished Jul 21 04:53:01 PM PDT 24
Peak memory 209520 kb
Host smart-ebd0b1ae-d366-46e7-b5d5-49cbc3d6c58d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520065832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2520065832
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.518130215
Short name T900
Test name
Test status
Simulation time 21347252 ps
CPU time 1.52 seconds
Started Jul 21 04:53:11 PM PDT 24
Finished Jul 21 04:53:13 PM PDT 24
Peak memory 211592 kb
Host smart-9b5bace1-995d-406f-9243-3644dab9d1f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518130215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.518130215
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3782313136
Short name T913
Test name
Test status
Simulation time 78931947 ps
CPU time 2.58 seconds
Started Jul 21 04:53:02 PM PDT 24
Finished Jul 21 04:53:07 PM PDT 24
Peak memory 217852 kb
Host smart-c87c6d43-f7ef-4679-83ab-424540dd1a93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782313136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3782313136
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3978257750
Short name T135
Test name
Test status
Simulation time 229179388 ps
CPU time 2.58 seconds
Started Jul 21 04:52:56 PM PDT 24
Finished Jul 21 04:53:01 PM PDT 24
Peak memory 217692 kb
Host smart-4559e26f-9b63-4be4-a4aa-c7731ea2cd3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978257750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3978257750
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3358483324
Short name T877
Test name
Test status
Simulation time 29498741 ps
CPU time 1.83 seconds
Started Jul 21 04:52:59 PM PDT 24
Finished Jul 21 04:53:01 PM PDT 24
Peak memory 219856 kb
Host smart-f0b35eb6-993e-45ce-a5a6-5bd4a2585050
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358483324 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3358483324
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2418649666
Short name T866
Test name
Test status
Simulation time 14649489 ps
CPU time 0.86 seconds
Started Jul 21 04:53:05 PM PDT 24
Finished Jul 21 04:53:06 PM PDT 24
Peak memory 209448 kb
Host smart-a3c299e7-6018-4c3b-8a8b-9824579154ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418649666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2418649666
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3972350001
Short name T927
Test name
Test status
Simulation time 79619913 ps
CPU time 0.96 seconds
Started Jul 21 04:53:09 PM PDT 24
Finished Jul 21 04:53:10 PM PDT 24
Peak memory 209452 kb
Host smart-15b30cb4-4a28-4537-9f29-b62ff8756066
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972350001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3972350001
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.252021156
Short name T121
Test name
Test status
Simulation time 112404755 ps
CPU time 2.79 seconds
Started Jul 21 04:53:02 PM PDT 24
Finished Jul 21 04:53:06 PM PDT 24
Peak memory 218856 kb
Host smart-3b72d248-3700-4925-b43a-579c3dba9d9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252021156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.252021156
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.649393541
Short name T960
Test name
Test status
Simulation time 35436935 ps
CPU time 1.43 seconds
Started Jul 21 04:52:56 PM PDT 24
Finished Jul 21 04:53:00 PM PDT 24
Peak memory 219324 kb
Host smart-17dfcd27-541a-4a60-aefa-d40cce40e998
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649393541 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.649393541
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2920657858
Short name T194
Test name
Test status
Simulation time 15451682 ps
CPU time 1.07 seconds
Started Jul 21 04:52:59 PM PDT 24
Finished Jul 21 04:53:01 PM PDT 24
Peak memory 209320 kb
Host smart-b3a61a78-e0a2-4f55-814e-7213aca5737c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920657858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2920657858
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2124309001
Short name T929
Test name
Test status
Simulation time 240884420 ps
CPU time 1.86 seconds
Started Jul 21 04:53:13 PM PDT 24
Finished Jul 21 04:53:16 PM PDT 24
Peak memory 209488 kb
Host smart-b799384b-1a8f-4b36-bbb2-d1dad511a811
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124309001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2124309001
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4020233652
Short name T130
Test name
Test status
Simulation time 39374109 ps
CPU time 2.28 seconds
Started Jul 21 04:53:02 PM PDT 24
Finished Jul 21 04:53:06 PM PDT 24
Peak memory 218080 kb
Host smart-89568d9d-f494-4e19-891a-f9259e9a192a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020233652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.4020233652
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2377825080
Short name T870
Test name
Test status
Simulation time 45084622 ps
CPU time 1.25 seconds
Started Jul 21 04:52:59 PM PDT 24
Finished Jul 21 04:53:01 PM PDT 24
Peak memory 220564 kb
Host smart-5b357d06-5d1c-4975-a39d-0044e1518cd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377825080 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2377825080
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.291127889
Short name T959
Test name
Test status
Simulation time 32041002 ps
CPU time 0.86 seconds
Started Jul 21 04:53:15 PM PDT 24
Finished Jul 21 04:53:16 PM PDT 24
Peak memory 209472 kb
Host smart-cf3f76a6-1b4f-400f-b905-708712bbba41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291127889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.291127889
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.4269268978
Short name T916
Test name
Test status
Simulation time 80173288 ps
CPU time 1.06 seconds
Started Jul 21 04:53:04 PM PDT 24
Finished Jul 21 04:53:06 PM PDT 24
Peak memory 209484 kb
Host smart-829d0a2a-b081-4381-bc08-aed70e21fe5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269268978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.4269268978
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1413059080
Short name T910
Test name
Test status
Simulation time 44429616 ps
CPU time 2.79 seconds
Started Jul 21 04:52:58 PM PDT 24
Finished Jul 21 04:53:02 PM PDT 24
Peak memory 217732 kb
Host smart-45eae88d-73bd-422d-87a7-f35f4fb88826
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413059080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1413059080
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2746743664
Short name T140
Test name
Test status
Simulation time 116774309 ps
CPU time 2.76 seconds
Started Jul 21 04:52:56 PM PDT 24
Finished Jul 21 04:53:01 PM PDT 24
Peak memory 217668 kb
Host smart-d9887581-a953-406b-a671-058ca9e1c186
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746743664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2746743664
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.392439716
Short name T978
Test name
Test status
Simulation time 26478346 ps
CPU time 1.52 seconds
Started Jul 21 04:53:06 PM PDT 24
Finished Jul 21 04:53:13 PM PDT 24
Peak memory 217844 kb
Host smart-f42670a7-5c40-45d1-bb6e-44da5706d8b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392439716 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.392439716
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3863455008
Short name T159
Test name
Test status
Simulation time 28042687 ps
CPU time 1.1 seconds
Started Jul 21 04:53:08 PM PDT 24
Finished Jul 21 04:53:09 PM PDT 24
Peak memory 209512 kb
Host smart-a9d89711-1c5f-4bdd-bd33-6a1b84c6ec9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863455008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3863455008
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1672891274
Short name T201
Test name
Test status
Simulation time 108300714 ps
CPU time 1.43 seconds
Started Jul 21 04:53:14 PM PDT 24
Finished Jul 21 04:53:17 PM PDT 24
Peak memory 211236 kb
Host smart-927cd1d2-ef1f-4a38-a941-dc9a0dd249ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672891274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1672891274
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.4086574496
Short name T112
Test name
Test status
Simulation time 124330690 ps
CPU time 5.01 seconds
Started Jul 21 04:52:58 PM PDT 24
Finished Jul 21 04:53:04 PM PDT 24
Peak memory 217992 kb
Host smart-b233f403-4771-40a0-b9ac-882ec5728087
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086574496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.4086574496
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2457711269
Short name T920
Test name
Test status
Simulation time 244221723 ps
CPU time 2.03 seconds
Started Jul 21 04:53:02 PM PDT 24
Finished Jul 21 04:53:05 PM PDT 24
Peak memory 221656 kb
Host smart-e76fde12-dfbc-49e7-b419-da2ea0097e5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457711269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2457711269
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.700495842
Short name T964
Test name
Test status
Simulation time 41043971 ps
CPU time 1.44 seconds
Started Jul 21 04:53:04 PM PDT 24
Finished Jul 21 04:53:07 PM PDT 24
Peak memory 218972 kb
Host smart-5794ffac-be9e-4937-a37d-fe61eac25545
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700495842 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.700495842
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.746197737
Short name T869
Test name
Test status
Simulation time 15732096 ps
CPU time 1.07 seconds
Started Jul 21 04:53:08 PM PDT 24
Finished Jul 21 04:53:09 PM PDT 24
Peak memory 209236 kb
Host smart-ff569c00-123f-4a68-9e06-9898a201748c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746197737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.746197737
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.670672588
Short name T904
Test name
Test status
Simulation time 103827503 ps
CPU time 1.35 seconds
Started Jul 21 04:53:02 PM PDT 24
Finished Jul 21 04:53:05 PM PDT 24
Peak memory 217820 kb
Host smart-16b35153-4b6f-4165-a3d5-2cc150758e1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670672588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.670672588
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3397870952
Short name T936
Test name
Test status
Simulation time 85504757 ps
CPU time 2.28 seconds
Started Jul 21 04:52:59 PM PDT 24
Finished Jul 21 04:53:02 PM PDT 24
Peak memory 217688 kb
Host smart-616a9f83-3969-4ea2-a6c6-ce8de4379672
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397870952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3397870952
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.928473890
Short name T973
Test name
Test status
Simulation time 145699303 ps
CPU time 2.16 seconds
Started Jul 21 04:53:00 PM PDT 24
Finished Jul 21 04:53:04 PM PDT 24
Peak memory 219060 kb
Host smart-5a1c0801-da61-4f26-9681-c7b49ce5ee2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928473890 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.928473890
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2910041258
Short name T203
Test name
Test status
Simulation time 29962936 ps
CPU time 0.83 seconds
Started Jul 21 04:53:13 PM PDT 24
Finished Jul 21 04:53:15 PM PDT 24
Peak memory 209752 kb
Host smart-60a332ca-ed79-4f00-9695-b16fccdbcf64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910041258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2910041258
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.580765039
Short name T961
Test name
Test status
Simulation time 262969830 ps
CPU time 1.35 seconds
Started Jul 21 04:53:24 PM PDT 24
Finished Jul 21 04:53:31 PM PDT 24
Peak memory 211644 kb
Host smart-811dcabf-ecc5-4097-8253-0af7973be07f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580765039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.580765039
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.535242394
Short name T871
Test name
Test status
Simulation time 24499371 ps
CPU time 1.48 seconds
Started Jul 21 04:53:14 PM PDT 24
Finished Jul 21 04:53:17 PM PDT 24
Peak memory 219812 kb
Host smart-f6b40f8c-8021-4bfd-916a-ae79ac0fa241
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535242394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.535242394
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1978421159
Short name T953
Test name
Test status
Simulation time 166480353 ps
CPU time 2.14 seconds
Started Jul 21 04:53:02 PM PDT 24
Finished Jul 21 04:53:06 PM PDT 24
Peak memory 219568 kb
Host smart-a64bba67-1399-4def-9a90-99c8166fd8ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978421159 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1978421159
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2032256504
Short name T118
Test name
Test status
Simulation time 16292182 ps
CPU time 1.08 seconds
Started Jul 21 04:53:19 PM PDT 24
Finished Jul 21 04:53:21 PM PDT 24
Peak memory 209472 kb
Host smart-5230d780-339d-421a-83c8-8a2c891ce782
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032256504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2032256504
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.810552473
Short name T906
Test name
Test status
Simulation time 77137024 ps
CPU time 1.34 seconds
Started Jul 21 04:53:02 PM PDT 24
Finished Jul 21 04:53:05 PM PDT 24
Peak memory 211556 kb
Host smart-8127656e-5084-4722-9b4f-7916f2f96e72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810552473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.810552473
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.4235429420
Short name T985
Test name
Test status
Simulation time 34076199 ps
CPU time 2.54 seconds
Started Jul 21 04:53:02 PM PDT 24
Finished Jul 21 04:53:06 PM PDT 24
Peak memory 217696 kb
Host smart-1999241b-8d26-4ea9-b262-d0a61040ece7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235429420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.4235429420
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3600423558
Short name T909
Test name
Test status
Simulation time 48139681 ps
CPU time 1.15 seconds
Started Jul 21 04:52:46 PM PDT 24
Finished Jul 21 04:52:48 PM PDT 24
Peak memory 209440 kb
Host smart-e0d8a87c-6c07-4ec8-9c7e-aeb9fb3b9afb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600423558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3600423558
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3429070381
Short name T937
Test name
Test status
Simulation time 336976918 ps
CPU time 1.82 seconds
Started Jul 21 04:52:45 PM PDT 24
Finished Jul 21 04:52:48 PM PDT 24
Peak memory 209492 kb
Host smart-da02f8bb-81b0-415d-ac57-f3bd088e6a9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429070381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3429070381
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3463388184
Short name T983
Test name
Test status
Simulation time 57203907 ps
CPU time 1.13 seconds
Started Jul 21 04:52:45 PM PDT 24
Finished Jul 21 04:52:47 PM PDT 24
Peak memory 210088 kb
Host smart-e9881a1a-d01b-4a99-af4d-f7537af1938a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463388184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3463388184
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3022615383
Short name T897
Test name
Test status
Simulation time 20291548 ps
CPU time 1.13 seconds
Started Jul 21 04:52:46 PM PDT 24
Finished Jul 21 04:52:48 PM PDT 24
Peak memory 217860 kb
Host smart-1383b344-ad73-4c85-bffc-b16418bac36b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022615383 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3022615383
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1552364840
Short name T860
Test name
Test status
Simulation time 18109891 ps
CPU time 1.04 seconds
Started Jul 21 04:52:47 PM PDT 24
Finished Jul 21 04:52:50 PM PDT 24
Peak memory 209464 kb
Host smart-d5d0c26a-e7bb-4fb9-8455-6300f9c93260
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552364840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1552364840
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1358921893
Short name T970
Test name
Test status
Simulation time 56797353 ps
CPU time 1.41 seconds
Started Jul 21 04:52:50 PM PDT 24
Finished Jul 21 04:52:52 PM PDT 24
Peak memory 208176 kb
Host smart-f5cc5156-d194-4d5e-98ee-659bcaeaf82d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358921893 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1358921893
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3510618305
Short name T932
Test name
Test status
Simulation time 4133119551 ps
CPU time 16.36 seconds
Started Jul 21 04:52:44 PM PDT 24
Finished Jul 21 04:53:01 PM PDT 24
Peak memory 209584 kb
Host smart-d0dc5070-0f20-43a6-8637-cb2a9f8a4bec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510618305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3510618305
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1269935816
Short name T892
Test name
Test status
Simulation time 9059248637 ps
CPU time 23.94 seconds
Started Jul 21 04:52:49 PM PDT 24
Finished Jul 21 04:53:14 PM PDT 24
Peak memory 209492 kb
Host smart-bb129a88-35f1-48f1-bb4d-42459a16177f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269935816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1269935816
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3635782067
Short name T946
Test name
Test status
Simulation time 390082037 ps
CPU time 3 seconds
Started Jul 21 04:52:40 PM PDT 24
Finished Jul 21 04:52:44 PM PDT 24
Peak memory 211328 kb
Host smart-70c9bd86-1ddf-4801-a473-7b2b381355d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635782067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3635782067
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1787048537
Short name T921
Test name
Test status
Simulation time 666407858 ps
CPU time 1.9 seconds
Started Jul 21 04:52:48 PM PDT 24
Finished Jul 21 04:52:51 PM PDT 24
Peak memory 217744 kb
Host smart-0d81fbab-d4cb-4ec3-8e54-8c647e0b5897
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178704
8537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1787048537
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2765349764
Short name T984
Test name
Test status
Simulation time 148196149 ps
CPU time 1.56 seconds
Started Jul 21 04:52:44 PM PDT 24
Finished Jul 21 04:52:47 PM PDT 24
Peak memory 209424 kb
Host smart-2eda290b-1d76-4c72-9bed-7664f73bf6ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765349764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2765349764
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.434595889
Short name T986
Test name
Test status
Simulation time 100801912 ps
CPU time 2.34 seconds
Started Jul 21 04:52:46 PM PDT 24
Finished Jul 21 04:52:49 PM PDT 24
Peak memory 217692 kb
Host smart-b7c2d657-63c9-40b8-a059-78bc05b8d26e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434595889 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.434595889
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4111222456
Short name T899
Test name
Test status
Simulation time 20437301 ps
CPU time 1.24 seconds
Started Jul 21 04:52:50 PM PDT 24
Finished Jul 21 04:52:52 PM PDT 24
Peak memory 211504 kb
Host smart-b3c556fb-18a0-40eb-8f64-e392855df336
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111222456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.4111222456
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.4169602526
Short name T896
Test name
Test status
Simulation time 56688078 ps
CPU time 1.89 seconds
Started Jul 21 04:52:51 PM PDT 24
Finished Jul 21 04:52:54 PM PDT 24
Peak memory 217720 kb
Host smart-10222938-ffff-4bdb-8b3f-2a5e5257992e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169602526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.4169602526
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4059862097
Short name T925
Test name
Test status
Simulation time 140143034 ps
CPU time 1.28 seconds
Started Jul 21 04:52:54 PM PDT 24
Finished Jul 21 04:52:57 PM PDT 24
Peak memory 209020 kb
Host smart-cde038e6-93f7-4bf2-8ddc-e09009d54209
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059862097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.4059862097
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2866542636
Short name T861
Test name
Test status
Simulation time 21057734 ps
CPU time 1.22 seconds
Started Jul 21 04:52:54 PM PDT 24
Finished Jul 21 04:52:57 PM PDT 24
Peak memory 208688 kb
Host smart-80cb055f-68dc-4bad-a401-075dc4080f32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866542636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2866542636
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2910867080
Short name T868
Test name
Test status
Simulation time 20547736 ps
CPU time 1.32 seconds
Started Jul 21 04:52:45 PM PDT 24
Finished Jul 21 04:52:48 PM PDT 24
Peak memory 218356 kb
Host smart-167e49e1-f7d3-4a61-827f-73317d2dab60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910867080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2910867080
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2804959846
Short name T918
Test name
Test status
Simulation time 104303317 ps
CPU time 2.09 seconds
Started Jul 21 04:52:47 PM PDT 24
Finished Jul 21 04:52:50 PM PDT 24
Peak memory 217840 kb
Host smart-066aea2b-9aee-4d2d-81b8-36ff5f73acc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804959846 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2804959846
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.939614747
Short name T884
Test name
Test status
Simulation time 87932981 ps
CPU time 0.85 seconds
Started Jul 21 04:52:46 PM PDT 24
Finished Jul 21 04:52:48 PM PDT 24
Peak memory 208896 kb
Host smart-4540a71c-9420-4607-a88f-1356b2534e95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939614747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.939614747
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.368045406
Short name T893
Test name
Test status
Simulation time 73367020 ps
CPU time 0.95 seconds
Started Jul 21 04:52:47 PM PDT 24
Finished Jul 21 04:52:49 PM PDT 24
Peak memory 209368 kb
Host smart-ba73d9aa-42fe-4257-8ff3-5f497598e902
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368045406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.368045406
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1319479722
Short name T988
Test name
Test status
Simulation time 804009305 ps
CPU time 18.72 seconds
Started Jul 21 04:52:54 PM PDT 24
Finished Jul 21 04:53:14 PM PDT 24
Peak memory 208776 kb
Host smart-35873bfd-a4d5-449d-aec2-5fab8c7df931
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319479722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1319479722
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2403967542
Short name T943
Test name
Test status
Simulation time 1477807984 ps
CPU time 9.55 seconds
Started Jul 21 04:52:46 PM PDT 24
Finished Jul 21 04:52:56 PM PDT 24
Peak memory 209452 kb
Host smart-47b50c17-6b4c-4094-b971-674335114486
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403967542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2403967542
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.69897610
Short name T954
Test name
Test status
Simulation time 580743584 ps
CPU time 1.98 seconds
Started Jul 21 04:52:44 PM PDT 24
Finished Jul 21 04:52:46 PM PDT 24
Peak memory 211028 kb
Host smart-2e8f4f35-8e2e-42ad-a9a8-3b5a53de9936
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69897610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.69897610
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2060752242
Short name T905
Test name
Test status
Simulation time 48675485 ps
CPU time 2.23 seconds
Started Jul 21 04:52:46 PM PDT 24
Finished Jul 21 04:52:49 PM PDT 24
Peak memory 217768 kb
Host smart-b2778bcf-65a0-4683-b4ba-f83aac5edc77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206075
2242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2060752242
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2324078498
Short name T955
Test name
Test status
Simulation time 130882417 ps
CPU time 2.08 seconds
Started Jul 21 04:52:45 PM PDT 24
Finished Jul 21 04:52:48 PM PDT 24
Peak memory 209524 kb
Host smart-51e844bc-3fda-4336-b36f-e3031b9efbed
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324078498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2324078498
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.346795067
Short name T924
Test name
Test status
Simulation time 42177400 ps
CPU time 1.36 seconds
Started Jul 21 04:52:54 PM PDT 24
Finished Jul 21 04:52:58 PM PDT 24
Peak memory 209264 kb
Host smart-d4951eef-410e-4891-a6c2-625df6fc3189
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346795067 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.346795067
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.875765340
Short name T930
Test name
Test status
Simulation time 34468808 ps
CPU time 1.67 seconds
Started Jul 21 04:52:50 PM PDT 24
Finished Jul 21 04:52:53 PM PDT 24
Peak memory 209468 kb
Host smart-cb8affab-7ad3-4944-be76-834dbaeb8a14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875765340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.875765340
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.929800550
Short name T947
Test name
Test status
Simulation time 46421607 ps
CPU time 1.58 seconds
Started Jul 21 04:52:54 PM PDT 24
Finished Jul 21 04:52:58 PM PDT 24
Peak memory 217636 kb
Host smart-c502b365-1498-4dd5-a7e4-6be3cbd652c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929800550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.929800550
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2719526488
Short name T138
Test name
Test status
Simulation time 326026160 ps
CPU time 3.69 seconds
Started Jul 21 04:52:47 PM PDT 24
Finished Jul 21 04:52:51 PM PDT 24
Peak memory 217716 kb
Host smart-37edb803-74f9-4173-875e-622e227d9075
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719526488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2719526488
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2899754631
Short name T192
Test name
Test status
Simulation time 441350910 ps
CPU time 1.3 seconds
Started Jul 21 04:52:53 PM PDT 24
Finished Jul 21 04:52:55 PM PDT 24
Peak memory 209512 kb
Host smart-d2153685-87d9-404b-a71e-36a6507ae9f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899754631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2899754631
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4049052833
Short name T951
Test name
Test status
Simulation time 403142302 ps
CPU time 2.02 seconds
Started Jul 21 04:52:57 PM PDT 24
Finished Jul 21 04:53:00 PM PDT 24
Peak memory 209636 kb
Host smart-764a1fa6-600a-471c-8654-d2dfb1b332a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049052833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.4049052833
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3616758161
Short name T931
Test name
Test status
Simulation time 30076322 ps
CPU time 1.07 seconds
Started Jul 21 04:52:46 PM PDT 24
Finished Jul 21 04:52:49 PM PDT 24
Peak memory 211476 kb
Host smart-0b855e6c-68f3-476c-860e-77373aa07ea5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616758161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3616758161
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.220472553
Short name T171
Test name
Test status
Simulation time 20256152 ps
CPU time 1.06 seconds
Started Jul 21 04:52:56 PM PDT 24
Finished Jul 21 04:52:59 PM PDT 24
Peak memory 217688 kb
Host smart-2d1dea62-c596-49df-8d35-256e3e022fc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220472553 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.220472553
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.747749226
Short name T205
Test name
Test status
Simulation time 25110146 ps
CPU time 1.04 seconds
Started Jul 21 04:53:00 PM PDT 24
Finished Jul 21 04:53:02 PM PDT 24
Peak memory 209472 kb
Host smart-ce12b402-f24e-444d-a37d-2e071a1b994b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747749226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.747749226
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.52222930
Short name T148
Test name
Test status
Simulation time 94410648 ps
CPU time 1.5 seconds
Started Jul 21 04:52:45 PM PDT 24
Finished Jul 21 04:52:48 PM PDT 24
Peak memory 209416 kb
Host smart-c299b7c9-844a-43fb-be9c-238ca2113107
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52222930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_alert_test.52222930
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3826698865
Short name T981
Test name
Test status
Simulation time 638879100 ps
CPU time 7.73 seconds
Started Jul 21 04:52:54 PM PDT 24
Finished Jul 21 04:53:04 PM PDT 24
Peak memory 208576 kb
Host smart-70e0a258-0734-4013-9b58-39eb97cff5eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826698865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3826698865
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3354397737
Short name T912
Test name
Test status
Simulation time 1935636944 ps
CPU time 22.16 seconds
Started Jul 21 04:52:46 PM PDT 24
Finished Jul 21 04:53:09 PM PDT 24
Peak memory 209336 kb
Host smart-2ad3c7c5-35ff-4def-9803-49dcc6f02572
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354397737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3354397737
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3787191263
Short name T971
Test name
Test status
Simulation time 107289351 ps
CPU time 2.24 seconds
Started Jul 21 04:52:50 PM PDT 24
Finished Jul 21 04:52:53 PM PDT 24
Peak memory 211340 kb
Host smart-66d8e721-d8f9-48f9-9ad4-a3d2c04daa8d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787191263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3787191263
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1096546477
Short name T886
Test name
Test status
Simulation time 33970364 ps
CPU time 1.21 seconds
Started Jul 21 04:52:51 PM PDT 24
Finished Jul 21 04:52:53 PM PDT 24
Peak memory 208312 kb
Host smart-05766fb6-11ab-4cdf-aca9-3d3296c44bf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096546477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1096546477
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2267300487
Short name T124
Test name
Test status
Simulation time 19970735 ps
CPU time 1.48 seconds
Started Jul 21 04:52:44 PM PDT 24
Finished Jul 21 04:52:46 PM PDT 24
Peak memory 209464 kb
Host smart-c1895f9f-1918-46dc-afcb-8a4afeba4bb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267300487 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2267300487
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.529681500
Short name T202
Test name
Test status
Simulation time 215663356 ps
CPU time 1.34 seconds
Started Jul 21 04:53:20 PM PDT 24
Finished Jul 21 04:53:22 PM PDT 24
Peak memory 211616 kb
Host smart-bd4fbc38-e170-4934-a2bd-71bbf2be2fce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529681500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.529681500
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1382012730
Short name T938
Test name
Test status
Simulation time 33591915 ps
CPU time 2.56 seconds
Started Jul 21 04:52:44 PM PDT 24
Finished Jul 21 04:52:47 PM PDT 24
Peak memory 217700 kb
Host smart-c2b02c00-375f-48a0-89e6-06726b3c39ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382012730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1382012730
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1815426906
Short name T129
Test name
Test status
Simulation time 105842012 ps
CPU time 2.82 seconds
Started Jul 21 04:53:00 PM PDT 24
Finished Jul 21 04:53:03 PM PDT 24
Peak memory 217672 kb
Host smart-554599f4-6cbd-48aa-acda-c29a3c4fc4ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815426906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1815426906
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.873033313
Short name T966
Test name
Test status
Simulation time 16760437 ps
CPU time 1.24 seconds
Started Jul 21 04:52:54 PM PDT 24
Finished Jul 21 04:52:58 PM PDT 24
Peak memory 217820 kb
Host smart-95018a2b-6fcf-4125-9009-d71bf1f5fc51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873033313 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.873033313
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1405929585
Short name T873
Test name
Test status
Simulation time 55040246 ps
CPU time 0.85 seconds
Started Jul 21 04:53:15 PM PDT 24
Finished Jul 21 04:53:16 PM PDT 24
Peak memory 209508 kb
Host smart-e7260947-c581-446e-bf25-e83e336d3783
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405929585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1405929585
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.814386774
Short name T147
Test name
Test status
Simulation time 156218845 ps
CPU time 1.31 seconds
Started Jul 21 04:52:56 PM PDT 24
Finished Jul 21 04:52:59 PM PDT 24
Peak memory 209444 kb
Host smart-2be58cf6-3cf1-4c59-b678-3f916a8831e8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814386774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.lc_ctrl_jtag_alert_test.814386774
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2127352853
Short name T972
Test name
Test status
Simulation time 7520889419 ps
CPU time 5.03 seconds
Started Jul 21 04:52:54 PM PDT 24
Finished Jul 21 04:53:00 PM PDT 24
Peak memory 209616 kb
Host smart-18756c8b-5b74-4be6-8c8a-826ec2a678dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127352853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2127352853
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1425226685
Short name T903
Test name
Test status
Simulation time 4836662013 ps
CPU time 8.85 seconds
Started Jul 21 04:52:53 PM PDT 24
Finished Jul 21 04:53:03 PM PDT 24
Peak memory 209716 kb
Host smart-15f6aa0f-0f6f-4936-ab57-08d9aacd8301
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425226685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1425226685
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2632268953
Short name T146
Test name
Test status
Simulation time 134558093 ps
CPU time 1.83 seconds
Started Jul 21 04:53:11 PM PDT 24
Finished Jul 21 04:53:13 PM PDT 24
Peak memory 211064 kb
Host smart-e732a975-51d7-46f5-91f2-34a3d9544754
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632268953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2632268953
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3763030461
Short name T874
Test name
Test status
Simulation time 246499974 ps
CPU time 2.41 seconds
Started Jul 21 04:52:54 PM PDT 24
Finished Jul 21 04:52:58 PM PDT 24
Peak memory 218544 kb
Host smart-7de2682a-3224-4b5c-ae5b-a517fc499d0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376303
0461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3763030461
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1756511241
Short name T975
Test name
Test status
Simulation time 119596936 ps
CPU time 1.17 seconds
Started Jul 21 04:53:01 PM PDT 24
Finished Jul 21 04:53:04 PM PDT 24
Peak memory 209472 kb
Host smart-2778550c-b6a1-43c4-a7f9-b4fed1573713
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756511241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1756511241
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.799768500
Short name T889
Test name
Test status
Simulation time 41144731 ps
CPU time 1.51 seconds
Started Jul 21 04:52:56 PM PDT 24
Finished Jul 21 04:52:59 PM PDT 24
Peak memory 211720 kb
Host smart-820a3799-ece1-4004-b332-a8891bf9b039
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799768500 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.799768500
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.125005621
Short name T204
Test name
Test status
Simulation time 84519447 ps
CPU time 1.15 seconds
Started Jul 21 04:52:54 PM PDT 24
Finished Jul 21 04:52:56 PM PDT 24
Peak memory 209420 kb
Host smart-7abe1578-833c-48d3-b720-ab8865fc3eb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125005621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.125005621
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.301905641
Short name T128
Test name
Test status
Simulation time 355889788 ps
CPU time 2.1 seconds
Started Jul 21 04:52:53 PM PDT 24
Finished Jul 21 04:52:56 PM PDT 24
Peak memory 218592 kb
Host smart-a011e822-69ab-45de-99a4-f9a8390a431c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301905641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.301905641
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3947428308
Short name T132
Test name
Test status
Simulation time 118935237 ps
CPU time 3.13 seconds
Started Jul 21 04:52:52 PM PDT 24
Finished Jul 21 04:52:56 PM PDT 24
Peak memory 222548 kb
Host smart-c8abc3a9-8de2-4e21-8c86-6d62e1813fa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947428308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3947428308
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.254876800
Short name T914
Test name
Test status
Simulation time 79902984 ps
CPU time 1.41 seconds
Started Jul 21 04:52:55 PM PDT 24
Finished Jul 21 04:52:59 PM PDT 24
Peak memory 217808 kb
Host smart-86d408c4-e6d4-4309-ab2d-52e2c352e098
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254876800 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.254876800
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1847934429
Short name T962
Test name
Test status
Simulation time 14451912 ps
CPU time 0.95 seconds
Started Jul 21 04:52:53 PM PDT 24
Finished Jul 21 04:52:55 PM PDT 24
Peak memory 209472 kb
Host smart-c759a7b2-eba2-4324-8c04-53bc3415cd15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847934429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1847934429
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3239798399
Short name T863
Test name
Test status
Simulation time 417340841 ps
CPU time 1.85 seconds
Started Jul 21 04:52:58 PM PDT 24
Finished Jul 21 04:53:01 PM PDT 24
Peak memory 209060 kb
Host smart-55d79a0e-3404-4fb2-9723-62f9b8460616
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239798399 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3239798399
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2771262180
Short name T939
Test name
Test status
Simulation time 2073405919 ps
CPU time 4.78 seconds
Started Jul 21 04:52:51 PM PDT 24
Finished Jul 21 04:52:56 PM PDT 24
Peak memory 208712 kb
Host smart-0bd8d8d3-7ce3-42ad-a10a-9c93627d1573
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771262180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2771262180
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1429965083
Short name T922
Test name
Test status
Simulation time 352613680 ps
CPU time 4.65 seconds
Started Jul 21 04:53:17 PM PDT 24
Finished Jul 21 04:53:22 PM PDT 24
Peak memory 208724 kb
Host smart-74dd61c1-c357-4858-b606-53b27f56c503
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429965083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1429965083
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1674103766
Short name T917
Test name
Test status
Simulation time 218307444 ps
CPU time 2.95 seconds
Started Jul 21 04:52:53 PM PDT 24
Finished Jul 21 04:52:57 PM PDT 24
Peak memory 211128 kb
Host smart-bc8a5245-c620-49af-b96a-9b98d7ad67cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674103766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1674103766
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2482386991
Short name T923
Test name
Test status
Simulation time 207795389 ps
CPU time 3.33 seconds
Started Jul 21 04:52:56 PM PDT 24
Finished Jul 21 04:53:02 PM PDT 24
Peak memory 219076 kb
Host smart-ee485c4f-90fb-4376-b90a-7dc255278e62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248238
6991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2482386991
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.197164465
Short name T944
Test name
Test status
Simulation time 47637220 ps
CPU time 1.16 seconds
Started Jul 21 04:52:54 PM PDT 24
Finished Jul 21 04:52:57 PM PDT 24
Peak memory 209660 kb
Host smart-5b234c98-5a58-435a-a73d-19dff852effb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197164465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.197164465
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4239297310
Short name T878
Test name
Test status
Simulation time 21831379 ps
CPU time 1.17 seconds
Started Jul 21 04:53:20 PM PDT 24
Finished Jul 21 04:53:27 PM PDT 24
Peak memory 211668 kb
Host smart-350219b6-81d4-45c3-80ff-9cd41d3852ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239297310 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.4239297310
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2503049663
Short name T199
Test name
Test status
Simulation time 33150804 ps
CPU time 1.24 seconds
Started Jul 21 04:52:52 PM PDT 24
Finished Jul 21 04:52:54 PM PDT 24
Peak memory 209596 kb
Host smart-a39ad44c-7c74-4def-b0fe-c463b6071604
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503049663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2503049663
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.508327513
Short name T111
Test name
Test status
Simulation time 545938155 ps
CPU time 3.9 seconds
Started Jul 21 04:53:06 PM PDT 24
Finished Jul 21 04:53:11 PM PDT 24
Peak memory 217724 kb
Host smart-24b2f078-c9b3-43c7-9fcf-10c8e1437836
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508327513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.508327513
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.207968578
Short name T940
Test name
Test status
Simulation time 232324587 ps
CPU time 1.68 seconds
Started Jul 21 04:52:56 PM PDT 24
Finished Jul 21 04:53:00 PM PDT 24
Peak memory 218924 kb
Host smart-d829e005-8c1d-4f22-9220-dca509e1b6c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207968578 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.207968578
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.988394033
Short name T979
Test name
Test status
Simulation time 25731954 ps
CPU time 1.05 seconds
Started Jul 21 04:52:53 PM PDT 24
Finished Jul 21 04:52:56 PM PDT 24
Peak memory 209460 kb
Host smart-4a2acb54-2a2c-409c-9a09-e9bfd17233aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988394033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.988394033
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4162946297
Short name T864
Test name
Test status
Simulation time 246740734 ps
CPU time 0.88 seconds
Started Jul 21 04:52:50 PM PDT 24
Finished Jul 21 04:52:52 PM PDT 24
Peak memory 208044 kb
Host smart-33f861b2-190b-4f35-8da1-c88524b14805
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162946297 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.4162946297
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2411340864
Short name T982
Test name
Test status
Simulation time 1389737155 ps
CPU time 6.94 seconds
Started Jul 21 04:53:11 PM PDT 24
Finished Jul 21 04:53:19 PM PDT 24
Peak memory 208252 kb
Host smart-14b943e3-d719-42b9-b5e7-005535c410c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411340864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2411340864
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1457701231
Short name T941
Test name
Test status
Simulation time 355241108 ps
CPU time 9.14 seconds
Started Jul 21 04:52:54 PM PDT 24
Finished Jul 21 04:53:05 PM PDT 24
Peak memory 209376 kb
Host smart-c423e4d1-286e-4fdc-9d9f-65977a9f9831
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457701231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1457701231
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1742495495
Short name T867
Test name
Test status
Simulation time 44964586 ps
CPU time 1.21 seconds
Started Jul 21 04:52:52 PM PDT 24
Finished Jul 21 04:52:54 PM PDT 24
Peak memory 210932 kb
Host smart-ee0fc08d-0583-400e-8afa-9d0f348c1b12
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742495495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1742495495
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1776776532
Short name T116
Test name
Test status
Simulation time 578267993 ps
CPU time 2.51 seconds
Started Jul 21 04:52:52 PM PDT 24
Finished Jul 21 04:52:56 PM PDT 24
Peak memory 218812 kb
Host smart-9b0f0536-3948-4dbd-974b-489c28ea856d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177677
6532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1776776532
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.804094379
Short name T144
Test name
Test status
Simulation time 290211002 ps
CPU time 2.35 seconds
Started Jul 21 04:52:49 PM PDT 24
Finished Jul 21 04:52:52 PM PDT 24
Peak memory 209468 kb
Host smart-45dce9fd-a2d9-4039-8c69-872ccc54b513
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804094379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.804094379
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1378066142
Short name T980
Test name
Test status
Simulation time 107317483 ps
CPU time 1.11 seconds
Started Jul 21 04:53:00 PM PDT 24
Finished Jul 21 04:53:02 PM PDT 24
Peak memory 209480 kb
Host smart-f52802d1-e723-4f11-baff-c6eef96bf194
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378066142 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1378066142
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1342289729
Short name T887
Test name
Test status
Simulation time 35994926 ps
CPU time 1.29 seconds
Started Jul 21 04:52:51 PM PDT 24
Finished Jul 21 04:52:53 PM PDT 24
Peak memory 209476 kb
Host smart-16efb998-a225-4ea4-b473-d59613751603
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342289729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1342289729
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2334759254
Short name T935
Test name
Test status
Simulation time 250889802 ps
CPU time 2.31 seconds
Started Jul 21 04:52:54 PM PDT 24
Finished Jul 21 04:52:59 PM PDT 24
Peak memory 217700 kb
Host smart-5a3ccaf8-a7e1-4304-a96f-3144df1465b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334759254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2334759254
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.72713986
Short name T137
Test name
Test status
Simulation time 469660010 ps
CPU time 2.37 seconds
Started Jul 21 04:52:50 PM PDT 24
Finished Jul 21 04:52:53 PM PDT 24
Peak memory 217680 kb
Host smart-3724779f-9430-4f20-a639-89aa27f0ed56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72713986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_er
r.72713986
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.753352464
Short name T890
Test name
Test status
Simulation time 123360505 ps
CPU time 1.84 seconds
Started Jul 21 04:52:52 PM PDT 24
Finished Jul 21 04:52:55 PM PDT 24
Peak memory 225464 kb
Host smart-b3311505-8d0a-4687-b332-348c38600a61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753352464 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.753352464
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3883424467
Short name T872
Test name
Test status
Simulation time 28507976 ps
CPU time 1.08 seconds
Started Jul 21 04:53:00 PM PDT 24
Finished Jul 21 04:53:02 PM PDT 24
Peak memory 217672 kb
Host smart-42bd9219-77fe-4215-9cde-49f6901f242b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883424467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3883424467
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2725677123
Short name T942
Test name
Test status
Simulation time 42920956 ps
CPU time 1.03 seconds
Started Jul 21 04:52:56 PM PDT 24
Finished Jul 21 04:52:59 PM PDT 24
Peak memory 208016 kb
Host smart-4186cc66-1ea2-424d-9ef9-d074696b27fe
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725677123 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2725677123
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.644892028
Short name T862
Test name
Test status
Simulation time 952675418 ps
CPU time 21.15 seconds
Started Jul 21 04:53:04 PM PDT 24
Finished Jul 21 04:53:26 PM PDT 24
Peak memory 209328 kb
Host smart-6957b560-b6c5-4acd-a7ce-3ef1b1df8333
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644892028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.644892028
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1244606202
Short name T875
Test name
Test status
Simulation time 2647630263 ps
CPU time 7.29 seconds
Started Jul 21 04:53:03 PM PDT 24
Finished Jul 21 04:53:11 PM PDT 24
Peak memory 209556 kb
Host smart-e9e1450a-788b-4704-b097-bcda5ed81e6b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244606202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1244606202
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3258176742
Short name T143
Test name
Test status
Simulation time 82134616 ps
CPU time 2.69 seconds
Started Jul 21 04:52:56 PM PDT 24
Finished Jul 21 04:53:01 PM PDT 24
Peak memory 211220 kb
Host smart-90fc8db4-39d0-4984-9848-0c8ea3669efc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258176742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3258176742
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2150604887
Short name T145
Test name
Test status
Simulation time 141027357 ps
CPU time 3.6 seconds
Started Jul 21 04:52:54 PM PDT 24
Finished Jul 21 04:52:59 PM PDT 24
Peak memory 221780 kb
Host smart-1b7c9dbf-571e-4815-8969-8963c255805f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215060
4887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2150604887
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3043261330
Short name T865
Test name
Test status
Simulation time 727400838 ps
CPU time 1.76 seconds
Started Jul 21 04:52:57 PM PDT 24
Finished Jul 21 04:53:01 PM PDT 24
Peak memory 209608 kb
Host smart-64091cf5-6d5c-42ef-99c0-fedad9b0642f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043261330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3043261330
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.590818736
Short name T198
Test name
Test status
Simulation time 23239672 ps
CPU time 1.24 seconds
Started Jul 21 04:53:02 PM PDT 24
Finished Jul 21 04:53:05 PM PDT 24
Peak memory 209540 kb
Host smart-5eaddbb5-9bf9-4884-ab4b-896706616933
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590818736 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.590818736
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.73893129
Short name T879
Test name
Test status
Simulation time 84996884 ps
CPU time 1.11 seconds
Started Jul 21 04:52:57 PM PDT 24
Finished Jul 21 04:53:00 PM PDT 24
Peak memory 209640 kb
Host smart-9caacea3-35a2-48f9-a4a3-643c5f1986aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73893129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_s
ame_csr_outstanding.73893129
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1780847265
Short name T967
Test name
Test status
Simulation time 99664122 ps
CPU time 2.35 seconds
Started Jul 21 04:52:56 PM PDT 24
Finished Jul 21 04:53:01 PM PDT 24
Peak memory 217684 kb
Host smart-7a619fda-4a41-40cc-b197-531d7031151b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780847265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1780847265
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3797991895
Short name T115
Test name
Test status
Simulation time 475652484 ps
CPU time 2.65 seconds
Started Jul 21 04:52:59 PM PDT 24
Finished Jul 21 04:53:03 PM PDT 24
Peak memory 222092 kb
Host smart-f76f7793-5904-4438-8129-631d597dfbf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797991895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3797991895
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.462991799
Short name T120
Test name
Test status
Simulation time 29381969 ps
CPU time 2.31 seconds
Started Jul 21 04:53:15 PM PDT 24
Finished Jul 21 04:53:23 PM PDT 24
Peak memory 219984 kb
Host smart-c5087eae-a34d-4ebd-8eca-4b09c1c855ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462991799 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.462991799
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.787883003
Short name T977
Test name
Test status
Simulation time 98095258 ps
CPU time 0.98 seconds
Started Jul 21 04:53:10 PM PDT 24
Finished Jul 21 04:53:11 PM PDT 24
Peak memory 209312 kb
Host smart-58344474-613d-43b0-9aff-4cb5e339e9d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787883003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.787883003
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3024249225
Short name T987
Test name
Test status
Simulation time 198984801 ps
CPU time 1.28 seconds
Started Jul 21 04:52:53 PM PDT 24
Finished Jul 21 04:52:56 PM PDT 24
Peak memory 208052 kb
Host smart-b932d064-7452-4b13-a95d-0c4b88bbf439
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024249225 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3024249225
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3795546895
Short name T957
Test name
Test status
Simulation time 830288031 ps
CPU time 3.16 seconds
Started Jul 21 04:52:54 PM PDT 24
Finished Jul 21 04:52:59 PM PDT 24
Peak memory 208740 kb
Host smart-3dab049b-ff1a-4310-bb2f-20680905ffc6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795546895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3795546895
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.222134201
Short name T934
Test name
Test status
Simulation time 764117669 ps
CPU time 10.17 seconds
Started Jul 21 04:53:02 PM PDT 24
Finished Jul 21 04:53:18 PM PDT 24
Peak memory 208392 kb
Host smart-f1bb2fb4-d7ab-48a2-a6c9-bab98d6edc91
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222134201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.222134201
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.532887071
Short name T894
Test name
Test status
Simulation time 51585735 ps
CPU time 1.96 seconds
Started Jul 21 04:52:55 PM PDT 24
Finished Jul 21 04:52:59 PM PDT 24
Peak memory 209496 kb
Host smart-2fd75dc0-89bc-4319-8da6-8406ba7f5a3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532887071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.532887071
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1308527047
Short name T952
Test name
Test status
Simulation time 473732487 ps
CPU time 4.24 seconds
Started Jul 21 04:53:03 PM PDT 24
Finished Jul 21 04:53:09 PM PDT 24
Peak memory 217784 kb
Host smart-ab1de9d0-1e01-4ab0-b801-360b9532b210
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130852
7047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1308527047
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2093117986
Short name T949
Test name
Test status
Simulation time 81680617 ps
CPU time 2.62 seconds
Started Jul 21 04:53:03 PM PDT 24
Finished Jul 21 04:53:07 PM PDT 24
Peak memory 209520 kb
Host smart-61938bfe-c208-4b6b-85c5-632aba94828b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093117986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.2093117986
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1234447158
Short name T965
Test name
Test status
Simulation time 21957264 ps
CPU time 1.21 seconds
Started Jul 21 04:52:56 PM PDT 24
Finished Jul 21 04:53:00 PM PDT 24
Peak memory 209580 kb
Host smart-0f2b90c1-bbab-450b-b692-d2cf74b44bab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234447158 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1234447158
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1398848142
Short name T200
Test name
Test status
Simulation time 121441968 ps
CPU time 1.3 seconds
Started Jul 21 04:52:53 PM PDT 24
Finished Jul 21 04:52:56 PM PDT 24
Peak memory 209464 kb
Host smart-01b94ba1-0d4b-43b6-a11d-b06bf898a491
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398848142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.1398848142
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2802706804
Short name T948
Test name
Test status
Simulation time 566544887 ps
CPU time 3.15 seconds
Started Jul 21 04:53:10 PM PDT 24
Finished Jul 21 04:53:13 PM PDT 24
Peak memory 217756 kb
Host smart-45e55107-f2fd-4a7f-9264-a7de31b78454
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802706804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2802706804
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1054728539
Short name T678
Test name
Test status
Simulation time 12417937 ps
CPU time 0.98 seconds
Started Jul 21 07:01:08 PM PDT 24
Finished Jul 21 07:01:11 PM PDT 24
Peak memory 208240 kb
Host smart-6e7d0e03-b93b-447a-bae2-5d570d74caa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054728539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1054728539
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1367783080
Short name T805
Test name
Test status
Simulation time 1055725134 ps
CPU time 8.92 seconds
Started Jul 21 07:01:04 PM PDT 24
Finished Jul 21 07:01:15 PM PDT 24
Peak memory 217788 kb
Host smart-73c2b93e-0172-4bee-9791-4d5c65e6b081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367783080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1367783080
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.383278028
Short name T5
Test name
Test status
Simulation time 5355708938 ps
CPU time 21.29 seconds
Started Jul 21 07:01:10 PM PDT 24
Finished Jul 21 07:01:32 PM PDT 24
Peak memory 217856 kb
Host smart-974629d1-a72d-4d2d-a596-a3325fe294fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383278028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.383278028
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1112472010
Short name T49
Test name
Test status
Simulation time 1180721671 ps
CPU time 7.81 seconds
Started Jul 21 07:01:13 PM PDT 24
Finished Jul 21 07:01:21 PM PDT 24
Peak memory 217224 kb
Host smart-84ae5223-4d33-42b1-a57c-3e0a6ac367e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112472010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
112472010
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3771857763
Short name T830
Test name
Test status
Simulation time 418150439 ps
CPU time 3.03 seconds
Started Jul 21 07:01:04 PM PDT 24
Finished Jul 21 07:01:10 PM PDT 24
Peak memory 221288 kb
Host smart-01bfa87f-7686-4895-ba3f-bb3e87c780eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771857763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3771857763
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.615499965
Short name T561
Test name
Test status
Simulation time 1134230364 ps
CPU time 13.26 seconds
Started Jul 21 07:01:10 PM PDT 24
Finished Jul 21 07:01:24 PM PDT 24
Peak memory 217156 kb
Host smart-41b2e0e6-4d10-4373-8901-d79bb1a2d74a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615499965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.615499965
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1590183831
Short name T622
Test name
Test status
Simulation time 1517699784 ps
CPU time 10.75 seconds
Started Jul 21 07:01:02 PM PDT 24
Finished Jul 21 07:01:16 PM PDT 24
Peak memory 217164 kb
Host smart-94e31a36-6e7c-43a9-a1a3-1f5e7eb713fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590183831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1590183831
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1212593934
Short name T278
Test name
Test status
Simulation time 3453513951 ps
CPU time 113.97 seconds
Started Jul 21 07:01:01 PM PDT 24
Finished Jul 21 07:02:58 PM PDT 24
Peak memory 283256 kb
Host smart-b83fcb65-9dca-481c-9442-f5b075e0ca0e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212593934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1212593934
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.934684940
Short name T335
Test name
Test status
Simulation time 481312641 ps
CPU time 14.54 seconds
Started Jul 21 07:01:02 PM PDT 24
Finished Jul 21 07:01:20 PM PDT 24
Peak memory 250508 kb
Host smart-17c0bd8d-4442-4eb5-ad5d-6a6154886295
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934684940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.934684940
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.553851488
Short name T837
Test name
Test status
Simulation time 88474208 ps
CPU time 4.34 seconds
Started Jul 21 07:01:02 PM PDT 24
Finished Jul 21 07:01:09 PM PDT 24
Peak memory 217812 kb
Host smart-a460e964-2ed0-4bbc-8cdd-8fcc6bba8139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553851488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.553851488
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2822881875
Short name T518
Test name
Test status
Simulation time 1473444687 ps
CPU time 6.54 seconds
Started Jul 21 07:01:13 PM PDT 24
Finished Jul 21 07:01:20 PM PDT 24
Peak memory 217216 kb
Host smart-f86e5bfc-ab2c-49b4-b2d7-6f61e2c87c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822881875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2822881875
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1914446010
Short name T55
Test name
Test status
Simulation time 468165873 ps
CPU time 22.04 seconds
Started Jul 21 07:01:09 PM PDT 24
Finished Jul 21 07:01:33 PM PDT 24
Peak memory 268456 kb
Host smart-eedb060d-0edc-4750-b67e-98a1ef370741
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914446010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1914446010
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1464359968
Short name T665
Test name
Test status
Simulation time 408582931 ps
CPU time 12.15 seconds
Started Jul 21 07:01:12 PM PDT 24
Finished Jul 21 07:01:24 PM PDT 24
Peak memory 225628 kb
Host smart-9b1107b4-9a2f-4899-89d7-fe80f501d7fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464359968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1464359968
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2814358373
Short name T856
Test name
Test status
Simulation time 1120956154 ps
CPU time 10.38 seconds
Started Jul 21 07:01:12 PM PDT 24
Finished Jul 21 07:01:23 PM PDT 24
Peak memory 217744 kb
Host smart-9386ef21-e1d7-49ec-a1af-03fd47314b69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814358373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2814358373
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3732306618
Short name T315
Test name
Test status
Simulation time 1054662518 ps
CPU time 5.72 seconds
Started Jul 21 07:01:04 PM PDT 24
Finished Jul 21 07:01:16 PM PDT 24
Peak memory 224332 kb
Host smart-dbaf5c7a-592e-4b17-b4f3-c206e3ccbdef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732306618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
732306618
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3838206298
Short name T411
Test name
Test status
Simulation time 1402615958 ps
CPU time 8.37 seconds
Started Jul 21 07:01:01 PM PDT 24
Finished Jul 21 07:01:12 PM PDT 24
Peak memory 225584 kb
Host smart-afd050e7-37e3-4050-80a1-6df8de48958d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838206298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3838206298
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2725746677
Short name T810
Test name
Test status
Simulation time 51536277 ps
CPU time 3.11 seconds
Started Jul 21 07:01:00 PM PDT 24
Finished Jul 21 07:01:07 PM PDT 24
Peak memory 214292 kb
Host smart-af602ec6-0a96-4baf-b085-13f51ed4b018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725746677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2725746677
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2589740880
Short name T429
Test name
Test status
Simulation time 430729584 ps
CPU time 27.82 seconds
Started Jul 21 07:01:01 PM PDT 24
Finished Jul 21 07:01:32 PM PDT 24
Peak memory 250692 kb
Host smart-618e6c68-900a-4043-8809-739527376093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589740880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2589740880
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2027617082
Short name T418
Test name
Test status
Simulation time 283355442 ps
CPU time 6.42 seconds
Started Jul 21 07:01:01 PM PDT 24
Finished Jul 21 07:01:11 PM PDT 24
Peak memory 246664 kb
Host smart-5256395a-4498-4558-9d33-60431c876c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027617082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2027617082
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.167819941
Short name T324
Test name
Test status
Simulation time 2883925290 ps
CPU time 94.11 seconds
Started Jul 21 07:01:05 PM PDT 24
Finished Jul 21 07:02:42 PM PDT 24
Peak memory 250552 kb
Host smart-30cd1141-0d93-42ac-aa8d-6236368daf9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167819941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.167819941
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.2162704971
Short name T748
Test name
Test status
Simulation time 164417895334 ps
CPU time 2774.39 seconds
Started Jul 21 07:01:11 PM PDT 24
Finished Jul 21 07:47:27 PM PDT 24
Peak memory 1504456 kb
Host smart-fafb6346-6507-4397-a62d-05f736d5ed1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2162704971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.2162704971
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3329339155
Short name T760
Test name
Test status
Simulation time 23987590 ps
CPU time 1.02 seconds
Started Jul 21 07:01:00 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 211420 kb
Host smart-e2c9a83a-114e-4bad-a802-578baf3e4052
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329339155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3329339155
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2306197775
Short name T290
Test name
Test status
Simulation time 88165872 ps
CPU time 0.94 seconds
Started Jul 21 07:01:08 PM PDT 24
Finished Jul 21 07:01:11 PM PDT 24
Peak memory 208372 kb
Host smart-591fffb0-36b4-4fca-9307-91e13b2be9c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306197775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2306197775
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.4013704649
Short name T713
Test name
Test status
Simulation time 296636529 ps
CPU time 4.5 seconds
Started Jul 21 07:01:04 PM PDT 24
Finished Jul 21 07:01:11 PM PDT 24
Peak memory 216808 kb
Host smart-bb7ed551-27a0-4fdf-94bd-79aa736659da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013704649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.4013704649
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.385477062
Short name T484
Test name
Test status
Simulation time 14995641619 ps
CPU time 50.51 seconds
Started Jul 21 07:01:09 PM PDT 24
Finished Jul 21 07:02:01 PM PDT 24
Peak memory 219512 kb
Host smart-21453a93-934a-40c3-afb5-257d95422525
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385477062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.385477062
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.1293027823
Short name T553
Test name
Test status
Simulation time 1788934315 ps
CPU time 19.95 seconds
Started Jul 21 07:01:08 PM PDT 24
Finished Jul 21 07:01:29 PM PDT 24
Peak memory 217212 kb
Host smart-7a4a46dd-e4a5-4302-af37-0dbb9f594be8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293027823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.1
293027823
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.581829120
Short name T250
Test name
Test status
Simulation time 136610211 ps
CPU time 3.19 seconds
Started Jul 21 07:01:13 PM PDT 24
Finished Jul 21 07:01:16 PM PDT 24
Peak memory 221348 kb
Host smart-67c0066a-7a91-4d3d-b296-ff4abd4b1d3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581829120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.581829120
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3003523016
Short name T339
Test name
Test status
Simulation time 5955166727 ps
CPU time 9.14 seconds
Started Jul 21 07:01:08 PM PDT 24
Finished Jul 21 07:01:19 PM PDT 24
Peak memory 217204 kb
Host smart-7e733bd3-9da1-488d-a01c-ee2340acc8f6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003523016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3003523016
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2458390038
Short name T787
Test name
Test status
Simulation time 507291716 ps
CPU time 4.69 seconds
Started Jul 21 07:01:10 PM PDT 24
Finished Jul 21 07:01:16 PM PDT 24
Peak memory 217148 kb
Host smart-68c8a533-2311-48af-9a93-9a8447f9a8b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458390038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2458390038
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.308825509
Short name T624
Test name
Test status
Simulation time 6230741699 ps
CPU time 93.03 seconds
Started Jul 21 07:01:07 PM PDT 24
Finished Jul 21 07:02:42 PM PDT 24
Peak memory 275808 kb
Host smart-4528484f-54b7-4734-9ed1-eadcffb10fc0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308825509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.308825509
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3954977421
Short name T576
Test name
Test status
Simulation time 1324103120 ps
CPU time 11.91 seconds
Started Jul 21 07:01:05 PM PDT 24
Finished Jul 21 07:01:19 PM PDT 24
Peak memory 250076 kb
Host smart-b2892907-310e-48c0-a205-b2dec44b7baf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954977421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3954977421
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1300646753
Short name T603
Test name
Test status
Simulation time 323133651 ps
CPU time 2.91 seconds
Started Jul 21 07:01:06 PM PDT 24
Finished Jul 21 07:01:11 PM PDT 24
Peak memory 217812 kb
Host smart-d4ea69fd-fb6b-4ccb-86fc-40aa2f37d92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300646753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1300646753
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3356312889
Short name T177
Test name
Test status
Simulation time 234585375 ps
CPU time 15.4 seconds
Started Jul 21 07:01:08 PM PDT 24
Finished Jul 21 07:01:25 PM PDT 24
Peak memory 214072 kb
Host smart-31db60ec-dec3-4846-9cca-5bb4be651c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356312889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3356312889
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1021703415
Short name T57
Test name
Test status
Simulation time 1245186827 ps
CPU time 35.3 seconds
Started Jul 21 07:01:13 PM PDT 24
Finished Jul 21 07:01:49 PM PDT 24
Peak memory 281848 kb
Host smart-cc12a6f2-3d8d-4192-aded-18d289bba854
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021703415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1021703415
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1929578052
Short name T559
Test name
Test status
Simulation time 1144447504 ps
CPU time 15.03 seconds
Started Jul 21 07:01:05 PM PDT 24
Finished Jul 21 07:01:23 PM PDT 24
Peak memory 218084 kb
Host smart-b5bb89f8-2077-4187-8dcf-7d18707e7706
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929578052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1929578052
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2715772501
Short name T102
Test name
Test status
Simulation time 278629343 ps
CPU time 12.48 seconds
Started Jul 21 07:01:11 PM PDT 24
Finished Jul 21 07:01:24 PM PDT 24
Peak memory 217856 kb
Host smart-401c571b-4029-4d59-8e6d-a67fa8176e09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715772501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2715772501
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.4115742297
Short name T711
Test name
Test status
Simulation time 1142079465 ps
CPU time 11.98 seconds
Started Jul 21 07:01:04 PM PDT 24
Finished Jul 21 07:01:20 PM PDT 24
Peak memory 225556 kb
Host smart-e31dbdb7-8f1b-4ebc-851b-f08f0623f458
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115742297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.4
115742297
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.247012436
Short name T759
Test name
Test status
Simulation time 325778756 ps
CPU time 8.43 seconds
Started Jul 21 07:01:06 PM PDT 24
Finished Jul 21 07:01:16 PM PDT 24
Peak memory 217884 kb
Host smart-bfc0c5cc-43b5-4cd6-9429-22a59b51cca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247012436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.247012436
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.781187192
Short name T68
Test name
Test status
Simulation time 152771291 ps
CPU time 1.36 seconds
Started Jul 21 07:01:07 PM PDT 24
Finished Jul 21 07:01:10 PM PDT 24
Peak memory 221568 kb
Host smart-523df195-c416-4c30-9400-64a70a6793a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781187192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.781187192
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3114392617
Short name T504
Test name
Test status
Simulation time 718770510 ps
CPU time 28.49 seconds
Started Jul 21 07:01:08 PM PDT 24
Finished Jul 21 07:01:38 PM PDT 24
Peak memory 250436 kb
Host smart-a9e87591-ad55-4b47-8db0-90c2812d810c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114392617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3114392617
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2321122882
Short name T354
Test name
Test status
Simulation time 640765395 ps
CPU time 8.22 seconds
Started Jul 21 07:01:14 PM PDT 24
Finished Jul 21 07:01:23 PM PDT 24
Peak memory 250548 kb
Host smart-13f7de5f-f2c0-44da-8406-c6f3f6024b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321122882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2321122882
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3802739633
Short name T508
Test name
Test status
Simulation time 3941655457 ps
CPU time 104.59 seconds
Started Jul 21 07:01:12 PM PDT 24
Finished Jul 21 07:02:58 PM PDT 24
Peak memory 267308 kb
Host smart-be843a00-214d-446f-9c8a-2cf0da1695ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802739633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3802739633
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3694425006
Short name T387
Test name
Test status
Simulation time 31272983 ps
CPU time 1.04 seconds
Started Jul 21 07:01:50 PM PDT 24
Finished Jul 21 07:01:53 PM PDT 24
Peak memory 208500 kb
Host smart-dfa252ae-491e-4b66-a501-83a8661a060c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694425006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3694425006
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.645237657
Short name T677
Test name
Test status
Simulation time 823266240 ps
CPU time 10.26 seconds
Started Jul 21 07:01:48 PM PDT 24
Finished Jul 21 07:01:59 PM PDT 24
Peak memory 217844 kb
Host smart-b0d2e127-f88e-461d-a48d-619a2d9dafbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645237657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.645237657
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.371212714
Short name T798
Test name
Test status
Simulation time 1502886614 ps
CPU time 6.22 seconds
Started Jul 21 07:01:50 PM PDT 24
Finished Jul 21 07:01:58 PM PDT 24
Peak memory 217040 kb
Host smart-2b67e3f3-57ee-4789-831f-b3623e10288b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371212714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.371212714
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2104403603
Short name T505
Test name
Test status
Simulation time 7270926274 ps
CPU time 46.09 seconds
Started Jul 21 07:01:53 PM PDT 24
Finished Jul 21 07:02:42 PM PDT 24
Peak memory 217848 kb
Host smart-3c4c2826-ae71-46b9-b051-0287a5e2bab6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104403603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2104403603
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.4090366434
Short name T679
Test name
Test status
Simulation time 3304435689 ps
CPU time 3.64 seconds
Started Jul 21 07:01:41 PM PDT 24
Finished Jul 21 07:01:45 PM PDT 24
Peak memory 223164 kb
Host smart-d4ead847-2ca9-4bdc-a685-fa8e2faee3ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090366434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.4090366434
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3197365424
Short name T847
Test name
Test status
Simulation time 2058382175 ps
CPU time 2.85 seconds
Started Jul 21 07:01:43 PM PDT 24
Finished Jul 21 07:01:46 PM PDT 24
Peak memory 217144 kb
Host smart-d4234bfb-60fa-489e-93fd-4eea4115ea01
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197365424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3197365424
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3719324282
Short name T95
Test name
Test status
Simulation time 8322008888 ps
CPU time 119.17 seconds
Started Jul 21 07:01:51 PM PDT 24
Finished Jul 21 07:03:52 PM PDT 24
Peak memory 282460 kb
Host smart-f155fd6e-4cb7-45e7-943b-a72664a5a57c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719324282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3719324282
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1976122579
Short name T467
Test name
Test status
Simulation time 3231392987 ps
CPU time 23.13 seconds
Started Jul 21 07:01:43 PM PDT 24
Finished Jul 21 07:02:06 PM PDT 24
Peak memory 245772 kb
Host smart-656f4d89-420b-43de-8d1b-1a3619d10e88
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976122579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1976122579
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.507163630
Short name T569
Test name
Test status
Simulation time 47618629 ps
CPU time 1.96 seconds
Started Jul 21 07:01:50 PM PDT 24
Finished Jul 21 07:01:54 PM PDT 24
Peak memory 217828 kb
Host smart-cffbb70a-26c2-4a67-a1c9-e72a7e515bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507163630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.507163630
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3021022628
Short name T427
Test name
Test status
Simulation time 236024546 ps
CPU time 10.63 seconds
Started Jul 21 07:01:54 PM PDT 24
Finished Jul 21 07:02:07 PM PDT 24
Peak memory 217932 kb
Host smart-f3981e1a-ff21-4992-9418-d9b8bc8c459e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021022628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3021022628
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3119420752
Short name T309
Test name
Test status
Simulation time 1411815111 ps
CPU time 17.37 seconds
Started Jul 21 07:01:43 PM PDT 24
Finished Jul 21 07:02:01 PM PDT 24
Peak memory 225540 kb
Host smart-ee71b91f-9b81-418e-a94a-904d76fbdfb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119420752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3119420752
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.599329614
Short name T555
Test name
Test status
Simulation time 292229633 ps
CPU time 10.62 seconds
Started Jul 21 07:01:46 PM PDT 24
Finished Jul 21 07:01:58 PM PDT 24
Peak memory 225488 kb
Host smart-4e6d791d-db0d-4e1f-bc88-a1b6c16530a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599329614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.599329614
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.4151412018
Short name T401
Test name
Test status
Simulation time 894672109 ps
CPU time 16.7 seconds
Started Jul 21 07:01:55 PM PDT 24
Finished Jul 21 07:02:14 PM PDT 24
Peak memory 225148 kb
Host smart-8c21182a-1750-44a9-a592-eeb615a65c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151412018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.4151412018
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1196238505
Short name T70
Test name
Test status
Simulation time 106672870 ps
CPU time 3.35 seconds
Started Jul 21 07:01:59 PM PDT 24
Finished Jul 21 07:02:04 PM PDT 24
Peak memory 217248 kb
Host smart-6b3dd29c-a337-4e69-94d0-4680078fbbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196238505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1196238505
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1315664805
Short name T627
Test name
Test status
Simulation time 355550563 ps
CPU time 38.08 seconds
Started Jul 21 07:01:50 PM PDT 24
Finished Jul 21 07:02:30 PM PDT 24
Peak memory 250556 kb
Host smart-52388408-43a7-4801-b192-e3f840764590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315664805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1315664805
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1584553513
Short name T853
Test name
Test status
Simulation time 245974801 ps
CPU time 3.75 seconds
Started Jul 21 07:01:48 PM PDT 24
Finished Jul 21 07:01:53 PM PDT 24
Peak memory 221864 kb
Host smart-bdd297f3-6b3b-45d0-a325-36784654cd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584553513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1584553513
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3493731332
Short name T109
Test name
Test status
Simulation time 34823882394 ps
CPU time 147.35 seconds
Started Jul 21 07:01:59 PM PDT 24
Finished Jul 21 07:04:29 PM PDT 24
Peak memory 275216 kb
Host smart-6ef19a26-5b8e-47e6-8411-6d5504277c9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493731332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3493731332
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2472071511
Short name T520
Test name
Test status
Simulation time 49669976 ps
CPU time 1.02 seconds
Started Jul 21 07:01:52 PM PDT 24
Finished Jul 21 07:01:56 PM PDT 24
Peak memory 211428 kb
Host smart-e667308e-c55a-4151-afe3-9113660961eb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472071511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2472071511
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.4184950141
Short name T440
Test name
Test status
Simulation time 14972554 ps
CPU time 0.86 seconds
Started Jul 21 07:01:54 PM PDT 24
Finished Jul 21 07:01:57 PM PDT 24
Peak memory 208384 kb
Host smart-4dce5602-16d3-454a-b82c-89f48363831b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184950141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.4184950141
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.934784323
Short name T499
Test name
Test status
Simulation time 2042283418 ps
CPU time 20.91 seconds
Started Jul 21 07:01:47 PM PDT 24
Finished Jul 21 07:02:09 PM PDT 24
Peak memory 217852 kb
Host smart-f62c71dd-0373-491a-9436-ac2e43e44534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934784323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.934784323
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.425456255
Short name T397
Test name
Test status
Simulation time 393107357 ps
CPU time 5.91 seconds
Started Jul 21 07:01:55 PM PDT 24
Finished Jul 21 07:02:03 PM PDT 24
Peak memory 216736 kb
Host smart-68f9f6a5-2806-4751-a17c-ac1391c51109
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425456255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.425456255
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.103876221
Short name T165
Test name
Test status
Simulation time 7335519110 ps
CPU time 32.48 seconds
Started Jul 21 07:01:56 PM PDT 24
Finished Jul 21 07:02:37 PM PDT 24
Peak memory 218208 kb
Host smart-e2a1093c-10b1-4f8c-baa9-259072d3b932
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103876221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er
rors.103876221
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.499274699
Short name T580
Test name
Test status
Simulation time 945578413 ps
CPU time 8.39 seconds
Started Jul 21 07:01:49 PM PDT 24
Finished Jul 21 07:01:59 PM PDT 24
Peak memory 222772 kb
Host smart-dab7e05f-ab24-4d69-9e59-ca53a941785f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499274699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.499274699
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2664738939
Short name T723
Test name
Test status
Simulation time 440768753 ps
CPU time 6.56 seconds
Started Jul 21 07:01:48 PM PDT 24
Finished Jul 21 07:01:57 PM PDT 24
Peak memory 217144 kb
Host smart-4609ea98-da36-438a-9e58-5b37dfbcf6d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664738939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2664738939
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2857907878
Short name T583
Test name
Test status
Simulation time 4199816846 ps
CPU time 61.08 seconds
Started Jul 21 07:01:42 PM PDT 24
Finished Jul 21 07:02:43 PM PDT 24
Peak memory 255072 kb
Host smart-da90d89d-f785-4de9-b052-9a94aaaa2c5b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857907878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2857907878
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3690978805
Short name T629
Test name
Test status
Simulation time 439424680 ps
CPU time 11.22 seconds
Started Jul 21 07:01:51 PM PDT 24
Finished Jul 21 07:02:04 PM PDT 24
Peak memory 247204 kb
Host smart-3b1d7a5d-15a6-462d-be86-02334709872d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690978805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3690978805
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.922969357
Short name T838
Test name
Test status
Simulation time 101288188 ps
CPU time 1.73 seconds
Started Jul 21 07:01:55 PM PDT 24
Finished Jul 21 07:02:00 PM PDT 24
Peak memory 217792 kb
Host smart-f5b2606e-4c17-41ff-bf64-e7ffce90db2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922969357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.922969357
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2497167091
Short name T731
Test name
Test status
Simulation time 320996594 ps
CPU time 11.54 seconds
Started Jul 21 07:01:47 PM PDT 24
Finished Jul 21 07:02:00 PM PDT 24
Peak memory 225628 kb
Host smart-34a1f730-6f10-4c7e-ae3e-f4ab14ce64fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497167091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2497167091
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2313549436
Short name T405
Test name
Test status
Simulation time 574784747 ps
CPU time 9.4 seconds
Started Jul 21 07:01:59 PM PDT 24
Finished Jul 21 07:02:11 PM PDT 24
Peak memory 217744 kb
Host smart-4f57cdb9-664d-4217-a24d-ee434eb74999
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313549436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2313549436
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3266776592
Short name T725
Test name
Test status
Simulation time 350615853 ps
CPU time 9.21 seconds
Started Jul 21 07:01:50 PM PDT 24
Finished Jul 21 07:02:00 PM PDT 24
Peak memory 225556 kb
Host smart-5abe5daf-0b1e-440d-94da-25dea4001a85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266776592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3266776592
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1420943628
Short name T749
Test name
Test status
Simulation time 3818510027 ps
CPU time 14.12 seconds
Started Jul 21 07:02:00 PM PDT 24
Finished Jul 21 07:02:17 PM PDT 24
Peak memory 218000 kb
Host smart-8bbe5c8f-1671-4c65-ae67-a37a390064a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420943628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1420943628
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.1863042542
Short name T825
Test name
Test status
Simulation time 33516671 ps
CPU time 2.14 seconds
Started Jul 21 07:01:55 PM PDT 24
Finished Jul 21 07:01:59 PM PDT 24
Peak memory 217208 kb
Host smart-234c648a-b458-40be-9fc3-b37794fbed8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863042542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1863042542
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3119362426
Short name T823
Test name
Test status
Simulation time 1213995694 ps
CPU time 22.37 seconds
Started Jul 21 07:02:03 PM PDT 24
Finished Jul 21 07:02:28 PM PDT 24
Peak memory 250496 kb
Host smart-10b132d8-5ecf-4392-83c5-a20ffa5bca0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119362426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3119362426
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2241189003
Short name T758
Test name
Test status
Simulation time 689015131 ps
CPU time 4.06 seconds
Started Jul 21 07:01:48 PM PDT 24
Finished Jul 21 07:01:54 PM PDT 24
Peak memory 222636 kb
Host smart-378cfd92-e6ee-4053-9a4d-e9d31b37b3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241189003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2241189003
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.600095032
Short name T567
Test name
Test status
Simulation time 14714959934 ps
CPU time 333.61 seconds
Started Jul 21 07:02:02 PM PDT 24
Finished Jul 21 07:07:39 PM PDT 24
Peak memory 270452 kb
Host smart-71016e4b-376f-4727-952e-36d4ef3adc35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600095032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.600095032
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.3193566431
Short name T80
Test name
Test status
Simulation time 29545851901 ps
CPU time 697.82 seconds
Started Jul 21 07:01:52 PM PDT 24
Finished Jul 21 07:13:33 PM PDT 24
Peak memory 332688 kb
Host smart-e20c0879-4df1-4a1c-acd4-afcb03f3b652
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3193566431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.3193566431
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2995804737
Short name T39
Test name
Test status
Simulation time 37935419 ps
CPU time 0.94 seconds
Started Jul 21 07:01:50 PM PDT 24
Finished Jul 21 07:01:53 PM PDT 24
Peak memory 208652 kb
Host smart-41fb7dea-76f9-4c20-a4ec-c014f24a47b1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995804737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2995804737
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.2913799529
Short name T461
Test name
Test status
Simulation time 58930465 ps
CPU time 1.04 seconds
Started Jul 21 07:01:54 PM PDT 24
Finished Jul 21 07:01:57 PM PDT 24
Peak memory 208480 kb
Host smart-ac950c13-46db-4311-a004-89d645dcea92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913799529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2913799529
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1401361294
Short name T347
Test name
Test status
Simulation time 443050385 ps
CPU time 15.22 seconds
Started Jul 21 07:01:51 PM PDT 24
Finished Jul 21 07:02:08 PM PDT 24
Peak memory 217864 kb
Host smart-cf275115-b852-47ac-ada8-77e080e39eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401361294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1401361294
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.4155193488
Short name T540
Test name
Test status
Simulation time 5405216411 ps
CPU time 8.45 seconds
Started Jul 21 07:01:52 PM PDT 24
Finished Jul 21 07:02:03 PM PDT 24
Peak memory 217300 kb
Host smart-75ae97ae-1e63-402a-b5ad-04ed9b2e572c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155193488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.4155193488
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1855056180
Short name T319
Test name
Test status
Simulation time 14973850268 ps
CPU time 30.72 seconds
Started Jul 21 07:02:05 PM PDT 24
Finished Jul 21 07:02:39 PM PDT 24
Peak memory 218456 kb
Host smart-5d3b0d09-3cc4-4b40-9fd3-3c94ec1bc7e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855056180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1855056180
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.785365695
Short name T179
Test name
Test status
Simulation time 169503341 ps
CPU time 3.13 seconds
Started Jul 21 07:02:02 PM PDT 24
Finished Jul 21 07:02:07 PM PDT 24
Peak memory 217168 kb
Host smart-86f36151-68f2-4002-adbf-a2e3cf72ed91
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785365695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.
785365695
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1397784000
Short name T826
Test name
Test status
Simulation time 2477010208 ps
CPU time 53.97 seconds
Started Jul 21 07:01:59 PM PDT 24
Finished Jul 21 07:02:56 PM PDT 24
Peak memory 266952 kb
Host smart-5e711a61-1d5f-45a9-ac66-4a5cb88c901a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397784000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1397784000
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.231370307
Short name T6
Test name
Test status
Simulation time 963174546 ps
CPU time 17.57 seconds
Started Jul 21 07:01:55 PM PDT 24
Finished Jul 21 07:02:16 PM PDT 24
Peak memory 249408 kb
Host smart-2f5af1ea-ebed-4f49-8f4b-5913d4c12998
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231370307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.231370307
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1707357188
Short name T28
Test name
Test status
Simulation time 444720064 ps
CPU time 4.21 seconds
Started Jul 21 07:01:57 PM PDT 24
Finished Jul 21 07:02:04 PM PDT 24
Peak memory 217780 kb
Host smart-c2215745-2e25-4633-a4f7-a2da4317cddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707357188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1707357188
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2519777752
Short name T371
Test name
Test status
Simulation time 416308138 ps
CPU time 13.36 seconds
Started Jul 21 07:01:55 PM PDT 24
Finished Jul 21 07:02:11 PM PDT 24
Peak memory 225608 kb
Host smart-a5a7a391-2baa-4d0f-8f21-0aba223912ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519777752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2519777752
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3498629679
Short name T529
Test name
Test status
Simulation time 4025140471 ps
CPU time 20.44 seconds
Started Jul 21 07:01:58 PM PDT 24
Finished Jul 21 07:02:21 PM PDT 24
Peak memory 217856 kb
Host smart-047e3245-a93c-4f2f-89a7-3434a9a8ef1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498629679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3498629679
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3945617082
Short name T660
Test name
Test status
Simulation time 871254426 ps
CPU time 11.04 seconds
Started Jul 21 07:01:56 PM PDT 24
Finished Jul 21 07:02:10 PM PDT 24
Peak memory 225568 kb
Host smart-021d2aca-b803-4461-b06d-d859407282c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945617082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3945617082
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3703311711
Short name T53
Test name
Test status
Simulation time 3599246458 ps
CPU time 9.67 seconds
Started Jul 21 07:01:59 PM PDT 24
Finished Jul 21 07:02:11 PM PDT 24
Peak memory 217964 kb
Host smart-9e49d978-9106-40d2-95a8-ace8f7a5dbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703311711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3703311711
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1513043840
Short name T699
Test name
Test status
Simulation time 157832040 ps
CPU time 1.36 seconds
Started Jul 21 07:01:55 PM PDT 24
Finished Jul 21 07:01:59 PM PDT 24
Peak memory 213280 kb
Host smart-a67e4f90-39ab-4384-8b87-6fac21e1629b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513043840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1513043840
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.3165473422
Short name T500
Test name
Test status
Simulation time 277242154 ps
CPU time 20.81 seconds
Started Jul 21 07:03:09 PM PDT 24
Finished Jul 21 07:03:31 PM PDT 24
Peak memory 248596 kb
Host smart-21bceffa-bbd1-40e8-b575-55b5f833694e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165473422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3165473422
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2442264002
Short name T226
Test name
Test status
Simulation time 63708949 ps
CPU time 2.91 seconds
Started Jul 21 07:01:52 PM PDT 24
Finished Jul 21 07:01:58 PM PDT 24
Peak memory 217812 kb
Host smart-e4d70946-9895-47e1-862c-86c11aefed78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442264002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2442264002
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2896954804
Short name T530
Test name
Test status
Simulation time 15323287457 ps
CPU time 82.67 seconds
Started Jul 21 07:01:51 PM PDT 24
Finished Jul 21 07:03:15 PM PDT 24
Peak memory 234516 kb
Host smart-c41edaa9-5902-48cc-a0cd-6e50a191ff4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896954804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2896954804
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.2494481379
Short name T152
Test name
Test status
Simulation time 40717676582 ps
CPU time 717.44 seconds
Started Jul 21 07:01:46 PM PDT 24
Finished Jul 21 07:13:43 PM PDT 24
Peak memory 372704 kb
Host smart-721bb73f-ee85-493d-94e4-9a264c2c55b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2494481379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.2494481379
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2930774352
Short name T370
Test name
Test status
Simulation time 36311207 ps
CPU time 0.9 seconds
Started Jul 21 07:02:05 PM PDT 24
Finished Jul 21 07:02:09 PM PDT 24
Peak memory 211444 kb
Host smart-1adf733d-e055-4f0e-a493-00150661ee7f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930774352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.2930774352
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.158408236
Short name T846
Test name
Test status
Simulation time 51102663 ps
CPU time 0.86 seconds
Started Jul 21 07:02:02 PM PDT 24
Finished Jul 21 07:02:05 PM PDT 24
Peak memory 208208 kb
Host smart-dac77c56-59bd-4d79-a1a0-34f6473d0dc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158408236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.158408236
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1125883923
Short name T33
Test name
Test status
Simulation time 1095422508 ps
CPU time 9.97 seconds
Started Jul 21 07:03:10 PM PDT 24
Finished Jul 21 07:03:21 PM PDT 24
Peak memory 217424 kb
Host smart-e44a668a-185b-43b4-8efa-63b5c3235e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125883923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1125883923
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1574841737
Short name T454
Test name
Test status
Simulation time 155350290 ps
CPU time 1.92 seconds
Started Jul 21 07:01:51 PM PDT 24
Finished Jul 21 07:01:56 PM PDT 24
Peak memory 216604 kb
Host smart-65bdce38-4d89-414b-a003-f94d9eb21e84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574841737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1574841737
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1199808927
Short name T799
Test name
Test status
Simulation time 2117134561 ps
CPU time 63.56 seconds
Started Jul 21 07:01:59 PM PDT 24
Finished Jul 21 07:03:05 PM PDT 24
Peak memory 217804 kb
Host smart-93d57a85-8cc1-4cdc-b506-c3575d087033
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199808927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1199808927
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2451888863
Short name T828
Test name
Test status
Simulation time 2788641860 ps
CPU time 10.15 seconds
Started Jul 21 07:01:48 PM PDT 24
Finished Jul 21 07:02:00 PM PDT 24
Peak memory 224300 kb
Host smart-3a64f516-e834-4c8e-a452-0cfbdce0a385
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451888863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2451888863
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.1781228510
Short name T312
Test name
Test status
Simulation time 1620673163 ps
CPU time 5.85 seconds
Started Jul 21 07:02:06 PM PDT 24
Finished Jul 21 07:02:14 PM PDT 24
Peak memory 217164 kb
Host smart-c3e4e591-70ba-4d4e-8fbd-f27474ac8f00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781228510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.1781228510
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1199702744
Short name T216
Test name
Test status
Simulation time 2021030168 ps
CPU time 67.09 seconds
Started Jul 21 07:01:56 PM PDT 24
Finished Jul 21 07:03:06 PM PDT 24
Peak memory 276100 kb
Host smart-f8a684d5-02dc-421e-afa5-7e062d603a37
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199702744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1199702744
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.793725618
Short name T270
Test name
Test status
Simulation time 3807125242 ps
CPU time 12.92 seconds
Started Jul 21 07:01:58 PM PDT 24
Finished Jul 21 07:02:22 PM PDT 24
Peak memory 219624 kb
Host smart-8e42172b-d80c-4085-a3ec-61014c609ffd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793725618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.793725618
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2393954448
Short name T263
Test name
Test status
Simulation time 214565592 ps
CPU time 3.28 seconds
Started Jul 21 07:01:56 PM PDT 24
Finished Jul 21 07:02:02 PM PDT 24
Peak memory 217792 kb
Host smart-7102f521-1e0e-4a3f-a514-10cb65a7e752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393954448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2393954448
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3363932064
Short name T607
Test name
Test status
Simulation time 2952725838 ps
CPU time 25.9 seconds
Started Jul 21 07:01:53 PM PDT 24
Finished Jul 21 07:02:26 PM PDT 24
Peak memory 219912 kb
Host smart-809c850d-b197-433b-9aee-9c11091d78fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363932064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3363932064
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2410152839
Short name T634
Test name
Test status
Simulation time 997961918 ps
CPU time 9.1 seconds
Started Jul 21 07:01:52 PM PDT 24
Finished Jul 21 07:02:03 PM PDT 24
Peak memory 217772 kb
Host smart-9adf9e10-23e9-442b-8da9-c566abf9c8df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410152839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2410152839
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2718667781
Short name T341
Test name
Test status
Simulation time 1586140586 ps
CPU time 9.31 seconds
Started Jul 21 07:02:03 PM PDT 24
Finished Jul 21 07:02:15 PM PDT 24
Peak memory 225544 kb
Host smart-1628ffc3-cb5c-45b0-8033-0896990721a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718667781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2718667781
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1603831075
Short name T654
Test name
Test status
Simulation time 27571388 ps
CPU time 1.52 seconds
Started Jul 21 07:02:01 PM PDT 24
Finished Jul 21 07:02:05 PM PDT 24
Peak memory 222404 kb
Host smart-0fc4bc61-6853-4dd6-83c6-ef1a351a4e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603831075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1603831075
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.512609820
Short name T669
Test name
Test status
Simulation time 297799451 ps
CPU time 26.04 seconds
Started Jul 21 07:02:01 PM PDT 24
Finished Jul 21 07:02:30 PM PDT 24
Peak memory 250552 kb
Host smart-0acbd21d-0177-4302-a7ba-c7abc6c00b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512609820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.512609820
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2093969105
Short name T279
Test name
Test status
Simulation time 448122641 ps
CPU time 9.27 seconds
Started Jul 21 07:02:06 PM PDT 24
Finished Jul 21 07:02:18 PM PDT 24
Peak memory 250556 kb
Host smart-a26bcc5a-8466-4b1c-b6b0-b5742f6e3135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093969105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2093969105
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3333456775
Short name T300
Test name
Test status
Simulation time 8150468349 ps
CPU time 95.6 seconds
Started Jul 21 07:01:55 PM PDT 24
Finished Jul 21 07:03:34 PM PDT 24
Peak memory 267236 kb
Host smart-94ef41e5-889f-469e-b949-90b80c27c697
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333456775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3333456775
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.470513970
Short name T108
Test name
Test status
Simulation time 40804726858 ps
CPU time 321.3 seconds
Started Jul 21 07:02:02 PM PDT 24
Finished Jul 21 07:07:26 PM PDT 24
Peak memory 276184 kb
Host smart-55a9b410-4087-4666-8001-50a168b95661
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=470513970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.470513970
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3938895363
Short name T297
Test name
Test status
Simulation time 80086445 ps
CPU time 0.98 seconds
Started Jul 21 07:02:00 PM PDT 24
Finished Jul 21 07:02:09 PM PDT 24
Peak memory 208468 kb
Host smart-0d37467b-729a-4b06-a327-1cbc557d3fb8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938895363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3938895363
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.520969511
Short name T163
Test name
Test status
Simulation time 23711596 ps
CPU time 0.8 seconds
Started Jul 21 07:01:53 PM PDT 24
Finished Jul 21 07:01:56 PM PDT 24
Peak memory 208240 kb
Host smart-c62aee8c-cec7-46a4-bbde-95a20a734cc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520969511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.520969511
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2371982371
Short name T280
Test name
Test status
Simulation time 1273021106 ps
CPU time 16.32 seconds
Started Jul 21 07:01:54 PM PDT 24
Finished Jul 21 07:02:12 PM PDT 24
Peak memory 217860 kb
Host smart-335ca2c8-9d6b-4136-ac7f-2959ce4d2015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371982371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2371982371
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3126930351
Short name T515
Test name
Test status
Simulation time 100868210 ps
CPU time 2.08 seconds
Started Jul 21 07:02:02 PM PDT 24
Finished Jul 21 07:02:06 PM PDT 24
Peak memory 216540 kb
Host smart-16d9afc0-44ea-4c92-b848-b7b6f4c9492c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126930351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3126930351
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.244639245
Short name T829
Test name
Test status
Simulation time 17989967321 ps
CPU time 65.29 seconds
Started Jul 21 07:01:59 PM PDT 24
Finished Jul 21 07:03:07 PM PDT 24
Peak memory 218436 kb
Host smart-dd728952-8139-4f99-a96e-4fd42674561e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244639245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.244639245
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1562815635
Short name T824
Test name
Test status
Simulation time 619633902 ps
CPU time 8.6 seconds
Started Jul 21 07:01:48 PM PDT 24
Finished Jul 21 07:01:58 PM PDT 24
Peak memory 222632 kb
Host smart-cebfcd2a-ff6d-4fa2-a1a9-bd72a1093b88
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562815635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1562815635
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2028781462
Short name T64
Test name
Test status
Simulation time 858280013 ps
CPU time 5.45 seconds
Started Jul 21 07:01:56 PM PDT 24
Finished Jul 21 07:02:05 PM PDT 24
Peak memory 217176 kb
Host smart-d6bceec3-06ff-4298-9455-d12d5c2fb1b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028781462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2028781462
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.4008894384
Short name T172
Test name
Test status
Simulation time 1985333060 ps
CPU time 45.8 seconds
Started Jul 21 07:01:55 PM PDT 24
Finished Jul 21 07:02:43 PM PDT 24
Peak memory 267136 kb
Host smart-7f15ecd3-05db-4871-b9f8-c9d9087cfcd6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008894384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.4008894384
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.996364590
Short name T338
Test name
Test status
Simulation time 468451867 ps
CPU time 12.24 seconds
Started Jul 21 07:01:51 PM PDT 24
Finished Jul 21 07:02:06 PM PDT 24
Peak memory 244872 kb
Host smart-7a747b5c-6e38-4d29-98f3-87fbf391788b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996364590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.996364590
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2217246508
Short name T480
Test name
Test status
Simulation time 292222820 ps
CPU time 2.73 seconds
Started Jul 21 07:01:55 PM PDT 24
Finished Jul 21 07:02:01 PM PDT 24
Peak memory 217820 kb
Host smart-e363a319-b1e7-469d-8161-ed8d3a1f550e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217246508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2217246508
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.772686151
Short name T59
Test name
Test status
Simulation time 1012933318 ps
CPU time 14.53 seconds
Started Jul 21 07:01:49 PM PDT 24
Finished Jul 21 07:02:05 PM PDT 24
Peak memory 225724 kb
Host smart-04046ddd-5c22-4de4-a7ab-d3479c67a169
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772686151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.772686151
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.984995853
Short name T662
Test name
Test status
Simulation time 425242608 ps
CPU time 11.14 seconds
Started Jul 21 07:02:01 PM PDT 24
Finished Jul 21 07:02:14 PM PDT 24
Peak memory 217836 kb
Host smart-8a1f019d-a078-4bef-8713-0862455a32e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984995853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.984995853
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2942842721
Short name T729
Test name
Test status
Simulation time 753492191 ps
CPU time 14.38 seconds
Started Jul 21 07:01:55 PM PDT 24
Finished Jul 21 07:02:11 PM PDT 24
Peak memory 225544 kb
Host smart-268954a2-d7a6-46ff-bd99-106591a01be9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942842721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2942842721
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1770491023
Short name T289
Test name
Test status
Simulation time 560269033 ps
CPU time 10.81 seconds
Started Jul 21 07:01:55 PM PDT 24
Finished Jul 21 07:02:08 PM PDT 24
Peak memory 217916 kb
Host smart-c9c6636f-9354-48b2-a386-22a9e278e2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770491023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1770491023
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1878743019
Short name T560
Test name
Test status
Simulation time 56982638 ps
CPU time 1.99 seconds
Started Jul 21 07:03:09 PM PDT 24
Finished Jul 21 07:03:12 PM PDT 24
Peak memory 215084 kb
Host smart-b05ff376-d2e4-4c7a-8cde-4313fd16693a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878743019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1878743019
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2552395381
Short name T753
Test name
Test status
Simulation time 242063658 ps
CPU time 15.85 seconds
Started Jul 21 07:01:54 PM PDT 24
Finished Jul 21 07:02:12 PM PDT 24
Peak memory 250556 kb
Host smart-2fef15a0-5933-47f0-8db7-79ea399fa052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552395381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2552395381
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.976475215
Short name T434
Test name
Test status
Simulation time 385653115 ps
CPU time 6.97 seconds
Started Jul 21 07:01:49 PM PDT 24
Finished Jul 21 07:01:57 PM PDT 24
Peak memory 250548 kb
Host smart-743c488b-90d5-4b73-b1af-f9df83b39b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976475215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.976475215
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2496323754
Short name T820
Test name
Test status
Simulation time 23533546118 ps
CPU time 204.53 seconds
Started Jul 21 07:01:56 PM PDT 24
Finished Jul 21 07:05:23 PM PDT 24
Peak memory 258504 kb
Host smart-6c6d2a59-8eb5-4715-8628-e869a70369ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496323754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2496323754
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2831854787
Short name T709
Test name
Test status
Simulation time 19530777 ps
CPU time 0.78 seconds
Started Jul 21 07:01:58 PM PDT 24
Finished Jul 21 07:02:02 PM PDT 24
Peak memory 208412 kb
Host smart-29dd0937-53de-446f-af15-3bbfab370ff2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831854787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2831854787
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.1219597413
Short name T230
Test name
Test status
Simulation time 28312884 ps
CPU time 1.04 seconds
Started Jul 21 07:01:52 PM PDT 24
Finished Jul 21 07:01:56 PM PDT 24
Peak memory 208524 kb
Host smart-913f6f67-2a4c-4193-871d-03dee6e5406f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219597413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.1219597413
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2470093106
Short name T155
Test name
Test status
Simulation time 270985856 ps
CPU time 8.9 seconds
Started Jul 21 07:01:56 PM PDT 24
Finished Jul 21 07:02:08 PM PDT 24
Peak memory 217888 kb
Host smart-4213cd3d-74db-4daf-a688-f50b6b361da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470093106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2470093106
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.4258858681
Short name T191
Test name
Test status
Simulation time 205348978 ps
CPU time 6.08 seconds
Started Jul 21 07:02:05 PM PDT 24
Finished Jul 21 07:02:14 PM PDT 24
Peak memory 216700 kb
Host smart-638afadc-676e-44b8-853f-4a37f53fd380
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258858681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.4258858681
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.4183352622
Short name T11
Test name
Test status
Simulation time 3335690989 ps
CPU time 48.42 seconds
Started Jul 21 07:01:58 PM PDT 24
Finished Jul 21 07:02:49 PM PDT 24
Peak memory 218592 kb
Host smart-b615f461-e58b-4da3-9a48-8d10c07f4cd1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183352622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.4183352622
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2941848328
Short name T311
Test name
Test status
Simulation time 1572216804 ps
CPU time 5.84 seconds
Started Jul 21 07:01:54 PM PDT 24
Finished Jul 21 07:02:02 PM PDT 24
Peak memory 221488 kb
Host smart-952ea859-b58c-487b-85b1-555f796e6bdc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941848328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2941848328
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.92600316
Short name T537
Test name
Test status
Simulation time 1409056464 ps
CPU time 3.1 seconds
Started Jul 21 07:02:01 PM PDT 24
Finished Jul 21 07:02:07 PM PDT 24
Peak memory 217168 kb
Host smart-01c0e5a0-8c80-4af0-b9b2-2c050950fad6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92600316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.92600316
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3209444152
Short name T597
Test name
Test status
Simulation time 3369748906 ps
CPU time 75.49 seconds
Started Jul 21 07:01:54 PM PDT 24
Finished Jul 21 07:03:12 PM PDT 24
Peak memory 266912 kb
Host smart-1a778a1b-49a1-4253-858b-30dd8e568023
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209444152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3209444152
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.413469739
Short name T243
Test name
Test status
Simulation time 717088441 ps
CPU time 11.46 seconds
Started Jul 21 07:02:01 PM PDT 24
Finished Jul 21 07:02:15 PM PDT 24
Peak memory 250088 kb
Host smart-1cc4e8d1-d6bf-4566-b895-a3432ed53a38
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413469739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.413469739
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1002109116
Short name T717
Test name
Test status
Simulation time 34193625 ps
CPU time 2.22 seconds
Started Jul 21 07:01:55 PM PDT 24
Finished Jul 21 07:02:00 PM PDT 24
Peak memory 217828 kb
Host smart-d193e53b-fb7d-4fb7-99df-ff32c5fb5fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002109116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1002109116
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2366543888
Short name T310
Test name
Test status
Simulation time 2077319819 ps
CPU time 15.39 seconds
Started Jul 21 07:01:56 PM PDT 24
Finished Jul 21 07:02:14 PM PDT 24
Peak memory 225572 kb
Host smart-9f0d33b2-239a-4a2c-b64d-6ac68787dd3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366543888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2366543888
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1337203279
Short name T333
Test name
Test status
Simulation time 1420525746 ps
CPU time 11.27 seconds
Started Jul 21 07:02:11 PM PDT 24
Finished Jul 21 07:02:22 PM PDT 24
Peak memory 217748 kb
Host smart-ca35bbd6-96b6-41e4-8ef4-65329b69e35c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337203279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.1337203279
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1333367523
Short name T535
Test name
Test status
Simulation time 472440714 ps
CPU time 9.39 seconds
Started Jul 21 07:02:18 PM PDT 24
Finished Jul 21 07:02:28 PM PDT 24
Peak memory 225548 kb
Host smart-9f0a1c00-9d00-4f3d-be39-346e9bef9da7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333367523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1333367523
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.4240914948
Short name T593
Test name
Test status
Simulation time 2873205773 ps
CPU time 6.55 seconds
Started Jul 21 07:02:05 PM PDT 24
Finished Jul 21 07:02:14 PM PDT 24
Peak memory 225664 kb
Host smart-f4eac8de-8d61-4bcf-93f1-39961b7bb328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240914948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.4240914948
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2583838600
Short name T430
Test name
Test status
Simulation time 306957976 ps
CPU time 4.62 seconds
Started Jul 21 07:01:58 PM PDT 24
Finished Jul 21 07:02:05 PM PDT 24
Peak memory 217284 kb
Host smart-288f6de6-f2fa-4b5f-8fb9-c77d4e4b04e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583838600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2583838600
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.724580347
Short name T517
Test name
Test status
Simulation time 884167022 ps
CPU time 23.19 seconds
Started Jul 21 07:02:12 PM PDT 24
Finished Jul 21 07:02:36 PM PDT 24
Peak memory 250540 kb
Host smart-cbf578de-084f-427c-87d2-eb24f6033009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724580347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.724580347
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.272878001
Short name T858
Test name
Test status
Simulation time 399512796 ps
CPU time 7.84 seconds
Started Jul 21 07:02:06 PM PDT 24
Finished Jul 21 07:02:16 PM PDT 24
Peak memory 247196 kb
Host smart-a4af1936-4843-4875-80f2-308dbf47600b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272878001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.272878001
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.4070248908
Short name T656
Test name
Test status
Simulation time 38906298774 ps
CPU time 193.24 seconds
Started Jul 21 07:03:10 PM PDT 24
Finished Jul 21 07:06:24 PM PDT 24
Peak memory 281348 kb
Host smart-a05e8195-375b-4f2d-a869-d582dac42c67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070248908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.4070248908
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2501539105
Short name T694
Test name
Test status
Simulation time 14959316 ps
CPU time 0.8 seconds
Started Jul 21 07:01:59 PM PDT 24
Finished Jul 21 07:02:03 PM PDT 24
Peak memory 208392 kb
Host smart-7338a09c-6112-4a3d-8679-a4edfaf01ccd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501539105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2501539105
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.4063854448
Short name T464
Test name
Test status
Simulation time 82458644 ps
CPU time 1.09 seconds
Started Jul 21 07:01:55 PM PDT 24
Finished Jul 21 07:01:59 PM PDT 24
Peak memory 208432 kb
Host smart-38035379-277d-4b37-90e3-5ead6ab88286
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063854448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.4063854448
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3757733342
Short name T106
Test name
Test status
Simulation time 1036814149 ps
CPU time 8.98 seconds
Started Jul 21 07:01:57 PM PDT 24
Finished Jul 21 07:02:08 PM PDT 24
Peak memory 217808 kb
Host smart-1bf5b5c7-ab42-47ce-a218-efe351a84c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757733342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3757733342
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3480633653
Short name T739
Test name
Test status
Simulation time 170388074 ps
CPU time 1.16 seconds
Started Jul 21 07:03:09 PM PDT 24
Finished Jul 21 07:03:12 PM PDT 24
Peak memory 214172 kb
Host smart-8c1a8687-c8ab-4941-9110-fb3d60229dc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480633653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3480633653
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3012597270
Short name T451
Test name
Test status
Simulation time 8221465589 ps
CPU time 80.45 seconds
Started Jul 21 07:03:28 PM PDT 24
Finished Jul 21 07:04:49 PM PDT 24
Peak memory 218288 kb
Host smart-b0f3d156-b6c0-4049-9a7c-d39ef683083b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012597270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3012597270
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.2285585328
Short name T671
Test name
Test status
Simulation time 4605657102 ps
CPU time 11.19 seconds
Started Jul 21 07:01:55 PM PDT 24
Finished Jul 21 07:02:08 PM PDT 24
Peak memory 223488 kb
Host smart-d5e91c83-8a1c-4f63-95fe-103b71f591ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285585328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.2285585328
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.234323070
Short name T793
Test name
Test status
Simulation time 1259750631 ps
CPU time 3.47 seconds
Started Jul 21 07:02:07 PM PDT 24
Finished Jul 21 07:02:12 PM PDT 24
Peak memory 217108 kb
Host smart-87209fbf-eead-46d7-85a2-7ef8daaa0c2f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234323070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
234323070
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1689367781
Short name T661
Test name
Test status
Simulation time 3272589617 ps
CPU time 43.18 seconds
Started Jul 21 07:03:10 PM PDT 24
Finished Jul 21 07:03:54 PM PDT 24
Peak memory 266520 kb
Host smart-dfdf90e2-a580-44ea-8627-7e8bdf02217f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689367781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1689367781
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1814415732
Short name T100
Test name
Test status
Simulation time 3516441615 ps
CPU time 26.45 seconds
Started Jul 21 07:02:07 PM PDT 24
Finished Jul 21 07:02:35 PM PDT 24
Peak memory 242316 kb
Host smart-1ed8865e-ec29-4af7-beef-392521279be3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814415732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.1814415732
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.607856572
Short name T683
Test name
Test status
Simulation time 43056835 ps
CPU time 2.53 seconds
Started Jul 21 07:02:10 PM PDT 24
Finished Jul 21 07:02:13 PM PDT 24
Peak memory 217768 kb
Host smart-f66e8ae4-d81e-4cd2-99c0-7aee8debdb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607856572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.607856572
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1845766221
Short name T647
Test name
Test status
Simulation time 1380505439 ps
CPU time 10.44 seconds
Started Jul 21 07:01:59 PM PDT 24
Finished Jul 21 07:02:12 PM PDT 24
Peak memory 218456 kb
Host smart-b5c6f69c-0685-4137-8f19-2bac3623d1b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845766221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1845766221
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1944463381
Short name T804
Test name
Test status
Simulation time 780439296 ps
CPU time 25.04 seconds
Started Jul 21 07:01:56 PM PDT 24
Finished Jul 21 07:02:24 PM PDT 24
Peak memory 217796 kb
Host smart-b81bd744-387e-428b-bfb2-b7a8f9ae1878
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944463381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1944463381
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3008378320
Short name T302
Test name
Test status
Simulation time 849210563 ps
CPU time 14.48 seconds
Started Jul 21 07:01:59 PM PDT 24
Finished Jul 21 07:02:16 PM PDT 24
Peak memory 225560 kb
Host smart-4c9e8c62-9605-4cc6-9d37-fce8cd086c4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008378320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3008378320
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3326278535
Short name T734
Test name
Test status
Simulation time 3564327042 ps
CPU time 12.05 seconds
Started Jul 21 07:01:55 PM PDT 24
Finished Jul 21 07:02:09 PM PDT 24
Peak memory 217956 kb
Host smart-4d9ef523-0ead-4ede-85ef-bba41b728112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326278535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3326278535
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.436858144
Short name T444
Test name
Test status
Simulation time 18740857 ps
CPU time 1.47 seconds
Started Jul 21 07:02:12 PM PDT 24
Finished Jul 21 07:02:14 PM PDT 24
Peak memory 213292 kb
Host smart-1c55575e-323b-4903-b9b0-c2a300ba281b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436858144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.436858144
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2155622031
Short name T423
Test name
Test status
Simulation time 558292213 ps
CPU time 26.74 seconds
Started Jul 21 07:01:53 PM PDT 24
Finished Jul 21 07:02:22 PM PDT 24
Peak memory 250620 kb
Host smart-539e7c48-d8fc-4d30-bde7-72d07c03fb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155622031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2155622031
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3660863586
Short name T358
Test name
Test status
Simulation time 1279900910 ps
CPU time 8.59 seconds
Started Jul 21 07:02:02 PM PDT 24
Finished Jul 21 07:02:14 PM PDT 24
Peak memory 250556 kb
Host smart-8c2d11e4-9d16-4c30-807d-974af85da508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660863586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3660863586
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3839422004
Short name T689
Test name
Test status
Simulation time 14449122 ps
CPU time 0.97 seconds
Started Jul 21 07:02:00 PM PDT 24
Finished Jul 21 07:02:04 PM PDT 24
Peak memory 208380 kb
Host smart-d00b5375-dfe2-4929-b7a5-8b63d288e808
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839422004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3839422004
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1227798807
Short name T93
Test name
Test status
Simulation time 20977251 ps
CPU time 1.25 seconds
Started Jul 21 07:02:06 PM PDT 24
Finished Jul 21 07:02:09 PM PDT 24
Peak memory 208532 kb
Host smart-4cc52155-eea6-4028-a9d7-aaeba710ce55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227798807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1227798807
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3119601534
Short name T584
Test name
Test status
Simulation time 250611075 ps
CPU time 8.12 seconds
Started Jul 21 07:02:14 PM PDT 24
Finished Jul 21 07:02:23 PM PDT 24
Peak memory 217872 kb
Host smart-294442dd-228b-4a39-9074-2a9b06fb0ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119601534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3119601534
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.510318607
Short name T21
Test name
Test status
Simulation time 322302936 ps
CPU time 4.87 seconds
Started Jul 21 07:02:00 PM PDT 24
Finished Jul 21 07:02:08 PM PDT 24
Peak memory 216868 kb
Host smart-842ba134-c81c-4411-a6a3-31060c4d6a5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510318607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.510318607
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.864902302
Short name T696
Test name
Test status
Simulation time 4765775668 ps
CPU time 62.47 seconds
Started Jul 21 07:02:07 PM PDT 24
Finished Jul 21 07:03:11 PM PDT 24
Peak memory 225616 kb
Host smart-f7e1a556-4e26-4c19-85e7-653afb612ec6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864902302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er
rors.864902302
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.686872289
Short name T691
Test name
Test status
Simulation time 128774725 ps
CPU time 3.2 seconds
Started Jul 21 07:01:59 PM PDT 24
Finished Jul 21 07:02:04 PM PDT 24
Peak memory 221556 kb
Host smart-bc8a98dc-8997-4b2b-8194-ede7938d3644
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686872289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.686872289
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1268130609
Short name T613
Test name
Test status
Simulation time 1339923082 ps
CPU time 8.89 seconds
Started Jul 21 07:03:33 PM PDT 24
Finished Jul 21 07:03:42 PM PDT 24
Peak memory 216992 kb
Host smart-7e170289-7535-4c0c-aba4-5c604b734662
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268130609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1268130609
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2790078763
Short name T228
Test name
Test status
Simulation time 23357386069 ps
CPU time 46.75 seconds
Started Jul 21 07:01:55 PM PDT 24
Finished Jul 21 07:02:45 PM PDT 24
Peak memory 266880 kb
Host smart-46ce3aab-b85e-4e58-8e40-a2f912eafb67
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790078763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2790078763
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3068585128
Short name T101
Test name
Test status
Simulation time 764084715 ps
CPU time 11.86 seconds
Started Jul 21 07:02:16 PM PDT 24
Finished Jul 21 07:02:29 PM PDT 24
Peak memory 245888 kb
Host smart-04b1fde6-b56b-4935-b651-1de25abe9f98
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068585128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3068585128
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.4253256327
Short name T601
Test name
Test status
Simulation time 265681485 ps
CPU time 3.06 seconds
Started Jul 21 07:02:07 PM PDT 24
Finished Jul 21 07:02:12 PM PDT 24
Peak memory 217920 kb
Host smart-32ce6f5e-a89f-4807-9a64-3695a7507d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253256327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.4253256327
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3491020856
Short name T652
Test name
Test status
Simulation time 549849067 ps
CPU time 23.03 seconds
Started Jul 21 07:01:59 PM PDT 24
Finished Jul 21 07:02:25 PM PDT 24
Peak memory 217920 kb
Host smart-854a7707-f7da-4b14-ad46-2fe5e2c0d580
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491020856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3491020856
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1010479682
Short name T442
Test name
Test status
Simulation time 1488900327 ps
CPU time 11.72 seconds
Started Jul 21 07:01:53 PM PDT 24
Finished Jul 21 07:02:07 PM PDT 24
Peak memory 217744 kb
Host smart-2d08af89-5b3b-413d-a869-8521f545676f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010479682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1010479682
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1518557772
Short name T393
Test name
Test status
Simulation time 998289271 ps
CPU time 6.69 seconds
Started Jul 21 07:03:09 PM PDT 24
Finished Jul 21 07:03:17 PM PDT 24
Peak memory 223520 kb
Host smart-020f02c2-221b-41c3-a7fe-0af3283b7d3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518557772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
1518557772
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.906665304
Short name T31
Test name
Test status
Simulation time 202330008 ps
CPU time 7.93 seconds
Started Jul 21 07:03:09 PM PDT 24
Finished Jul 21 07:03:18 PM PDT 24
Peak memory 215560 kb
Host smart-8b0bed1b-0428-48db-bb4e-7dd5bd4500e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906665304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.906665304
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.4208852840
Short name T400
Test name
Test status
Simulation time 196585720 ps
CPU time 2.56 seconds
Started Jul 21 07:03:33 PM PDT 24
Finished Jul 21 07:03:36 PM PDT 24
Peak memory 213796 kb
Host smart-142e872d-dfb5-4945-b71b-86fbe2e28f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208852840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.4208852840
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2851300447
Short name T510
Test name
Test status
Simulation time 377226591 ps
CPU time 33.23 seconds
Started Jul 21 07:02:00 PM PDT 24
Finished Jul 21 07:02:36 PM PDT 24
Peak memory 250504 kb
Host smart-920910b6-6f4b-4188-ab8c-6a6454298af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851300447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2851300447
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.1377791940
Short name T174
Test name
Test status
Simulation time 643894753 ps
CPU time 6.17 seconds
Started Jul 21 07:01:50 PM PDT 24
Finished Jul 21 07:01:57 PM PDT 24
Peak memory 246144 kb
Host smart-df12bbd0-1acc-4d24-b7e0-28fb103dac13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377791940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1377791940
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.248514765
Short name T521
Test name
Test status
Simulation time 14647153696 ps
CPU time 486.61 seconds
Started Jul 21 07:02:10 PM PDT 24
Finished Jul 21 07:10:17 PM PDT 24
Peak memory 272464 kb
Host smart-8ae21c39-5d7c-4d64-9503-06da8921ce18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248514765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.248514765
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1210036852
Short name T395
Test name
Test status
Simulation time 60330738 ps
CPU time 0.82 seconds
Started Jul 21 07:02:03 PM PDT 24
Finished Jul 21 07:02:07 PM PDT 24
Peak memory 206788 kb
Host smart-a43df2cd-09c4-4a8c-9fd6-7305147d394a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210036852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1210036852
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.4149277557
Short name T161
Test name
Test status
Simulation time 68477869 ps
CPU time 1.1 seconds
Started Jul 21 07:01:58 PM PDT 24
Finished Jul 21 07:02:01 PM PDT 24
Peak memory 208376 kb
Host smart-e89757fb-7d6b-46c8-8ca4-69a689b3d4df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149277557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.4149277557
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2999307851
Short name T239
Test name
Test status
Simulation time 1012090272 ps
CPU time 15.61 seconds
Started Jul 21 07:02:01 PM PDT 24
Finished Jul 21 07:02:19 PM PDT 24
Peak memory 217796 kb
Host smart-821d4461-84a2-49e5-bde9-fec84e3893c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999307851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2999307851
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3459479363
Short name T623
Test name
Test status
Simulation time 865263639 ps
CPU time 4.53 seconds
Started Jul 21 07:02:01 PM PDT 24
Finished Jul 21 07:02:08 PM PDT 24
Peak memory 216612 kb
Host smart-73f8e26c-a3ba-4d8c-aae7-ea7638d83021
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459479363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3459479363
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2071890826
Short name T232
Test name
Test status
Simulation time 185741423 ps
CPU time 2.47 seconds
Started Jul 21 07:01:54 PM PDT 24
Finished Jul 21 07:01:59 PM PDT 24
Peak memory 221412 kb
Host smart-0e66680c-97c4-403c-8a71-ea558f7b406c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071890826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2071890826
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3010689346
Short name T75
Test name
Test status
Simulation time 92809491 ps
CPU time 2.03 seconds
Started Jul 21 07:01:58 PM PDT 24
Finished Jul 21 07:02:02 PM PDT 24
Peak memory 217172 kb
Host smart-c368dc98-6090-4f86-b0f6-429a449e44fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010689346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3010689346
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.73118771
Short name T357
Test name
Test status
Simulation time 6358091481 ps
CPU time 57.96 seconds
Started Jul 21 07:02:01 PM PDT 24
Finished Jul 21 07:03:02 PM PDT 24
Peak memory 276304 kb
Host smart-443f287f-3c56-4193-88b6-86fc7c136fff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73118771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_state_failure.73118771
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3900741486
Short name T659
Test name
Test status
Simulation time 854825578 ps
CPU time 8.23 seconds
Started Jul 21 07:01:59 PM PDT 24
Finished Jul 21 07:02:10 PM PDT 24
Peak memory 225896 kb
Host smart-4284edae-d0a1-47dc-a50a-8fac85b555b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900741486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3900741486
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2181849695
Short name T648
Test name
Test status
Simulation time 70176923 ps
CPU time 2.83 seconds
Started Jul 21 07:02:05 PM PDT 24
Finished Jul 21 07:02:11 PM PDT 24
Peak memory 221724 kb
Host smart-88529af2-5e0f-48db-8419-87a65592b3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181849695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2181849695
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2439171177
Short name T105
Test name
Test status
Simulation time 830655945 ps
CPU time 14.4 seconds
Started Jul 21 07:02:05 PM PDT 24
Finished Jul 21 07:02:22 PM PDT 24
Peak memory 225640 kb
Host smart-9ddb1bda-7e34-44cd-8517-b32d3e905fd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439171177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2439171177
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3574388249
Short name T3
Test name
Test status
Simulation time 413522986 ps
CPU time 9.56 seconds
Started Jul 21 07:02:05 PM PDT 24
Finished Jul 21 07:02:18 PM PDT 24
Peak memory 217808 kb
Host smart-2c47e41d-bf4b-4b84-bbed-37559834e08f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574388249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3574388249
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2281363007
Short name T314
Test name
Test status
Simulation time 1454663988 ps
CPU time 16.23 seconds
Started Jul 21 07:02:07 PM PDT 24
Finished Jul 21 07:02:25 PM PDT 24
Peak memory 225472 kb
Host smart-ad4943e8-5ddc-487e-8bd9-ce17cc8188a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281363007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2281363007
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3927223185
Short name T779
Test name
Test status
Simulation time 248594826 ps
CPU time 9.32 seconds
Started Jul 21 07:02:03 PM PDT 24
Finished Jul 21 07:02:14 PM PDT 24
Peak memory 217880 kb
Host smart-ce6256d1-529a-4a5c-8d4b-72c3b8be7ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927223185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3927223185
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1803100152
Short name T819
Test name
Test status
Simulation time 242643440 ps
CPU time 24.82 seconds
Started Jul 21 07:02:01 PM PDT 24
Finished Jul 21 07:02:30 PM PDT 24
Peak memory 250452 kb
Host smart-7bda91f9-f8ef-4fa1-a3a6-e148c5f3682e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803100152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1803100152
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3530779149
Short name T331
Test name
Test status
Simulation time 71939673 ps
CPU time 3.16 seconds
Started Jul 21 07:02:01 PM PDT 24
Finished Jul 21 07:02:07 PM PDT 24
Peak memory 222308 kb
Host smart-a444247a-54fe-4dca-9086-cd56d816c31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530779149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3530779149
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3861005199
Short name T336
Test name
Test status
Simulation time 8521360689 ps
CPU time 165.95 seconds
Started Jul 21 07:02:04 PM PDT 24
Finished Jul 21 07:04:52 PM PDT 24
Peak memory 283276 kb
Host smart-e513b7a1-d95c-4274-919e-57f5cba20fdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861005199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3861005199
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1624217065
Short name T551
Test name
Test status
Simulation time 38452195 ps
CPU time 0.81 seconds
Started Jul 21 07:02:06 PM PDT 24
Finished Jul 21 07:02:09 PM PDT 24
Peak memory 208212 kb
Host smart-f744f002-5004-4b19-b1aa-9a7068057a52
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624217065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.1624217065
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2278419609
Short name T272
Test name
Test status
Simulation time 22801651 ps
CPU time 0.97 seconds
Started Jul 21 07:02:09 PM PDT 24
Finished Jul 21 07:02:11 PM PDT 24
Peak memory 208432 kb
Host smart-faa256ed-5a76-47a9-b0f4-f8002a2d245b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278419609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2278419609
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2870219493
Short name T833
Test name
Test status
Simulation time 627285052 ps
CPU time 15.76 seconds
Started Jul 21 07:02:00 PM PDT 24
Finished Jul 21 07:02:18 PM PDT 24
Peak memory 217844 kb
Host smart-1c490eee-3128-4390-8769-88bb48a48111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870219493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2870219493
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1795079415
Short name T452
Test name
Test status
Simulation time 297444907 ps
CPU time 4.02 seconds
Started Jul 21 07:02:15 PM PDT 24
Finished Jul 21 07:02:20 PM PDT 24
Peak memory 216752 kb
Host smart-08dac5ac-8f88-4f53-a3e8-79efad9a3f81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795079415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1795079415
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2699023756
Short name T48
Test name
Test status
Simulation time 7009151137 ps
CPU time 43.8 seconds
Started Jul 21 07:02:16 PM PDT 24
Finished Jul 21 07:03:00 PM PDT 24
Peak memory 225608 kb
Host smart-ec0d12ed-53e8-430b-a9a3-7c91847658b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699023756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2699023756
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.4096337901
Short name T215
Test name
Test status
Simulation time 6227898084 ps
CPU time 7.98 seconds
Started Jul 21 07:02:06 PM PDT 24
Finished Jul 21 07:02:17 PM PDT 24
Peak memory 224420 kb
Host smart-629084c9-d9ec-4e07-b162-23d0f0ed20a2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096337901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.4096337901
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3727204280
Short name T178
Test name
Test status
Simulation time 1151423682 ps
CPU time 1.67 seconds
Started Jul 21 07:02:04 PM PDT 24
Finished Jul 21 07:02:08 PM PDT 24
Peak memory 217192 kb
Host smart-9a5e0295-c991-463c-9bda-b1e487814e1a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727204280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3727204280
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3096043883
Short name T572
Test name
Test status
Simulation time 6161903576 ps
CPU time 30.95 seconds
Started Jul 21 07:02:16 PM PDT 24
Finished Jul 21 07:02:48 PM PDT 24
Peak memory 250680 kb
Host smart-3140e875-7a11-4d3a-b09f-915a21efbadc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096043883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3096043883
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2382351040
Short name T299
Test name
Test status
Simulation time 1023279932 ps
CPU time 21.99 seconds
Started Jul 21 07:02:01 PM PDT 24
Finished Jul 21 07:02:25 PM PDT 24
Peak memory 250456 kb
Host smart-32eb9522-e72a-4b4e-82e8-f90e3c01b7b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382351040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2382351040
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2638917640
Short name T14
Test name
Test status
Simulation time 142133931 ps
CPU time 1.99 seconds
Started Jul 21 07:02:09 PM PDT 24
Finished Jul 21 07:02:12 PM PDT 24
Peak memory 217808 kb
Host smart-508671f4-8f37-4254-92b6-2c41fdd8f45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638917640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2638917640
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3834412767
Short name T390
Test name
Test status
Simulation time 2044662725 ps
CPU time 14.07 seconds
Started Jul 21 07:02:07 PM PDT 24
Finished Jul 21 07:02:23 PM PDT 24
Peak memory 218448 kb
Host smart-19dc72b8-7718-41f7-b56d-05a7c9649351
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834412767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3834412767
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.280778820
Short name T491
Test name
Test status
Simulation time 1254172278 ps
CPU time 12.69 seconds
Started Jul 21 07:02:04 PM PDT 24
Finished Jul 21 07:02:19 PM PDT 24
Peak memory 217812 kb
Host smart-2ab86990-ef9b-4a4d-9643-b6e4774f59d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280778820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_di
gest.280778820
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.484172614
Short name T344
Test name
Test status
Simulation time 349857807 ps
CPU time 8.96 seconds
Started Jul 21 07:02:04 PM PDT 24
Finished Jul 21 07:02:16 PM PDT 24
Peak memory 217880 kb
Host smart-31c45d57-882d-4e19-bf8b-2ee981be1bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484172614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.484172614
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.175127161
Short name T446
Test name
Test status
Simulation time 69402263 ps
CPU time 3.13 seconds
Started Jul 21 07:02:00 PM PDT 24
Finished Jul 21 07:02:06 PM PDT 24
Peak memory 214728 kb
Host smart-6f25ee5e-a901-406e-b42f-585e50640b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175127161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.175127161
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.4192251110
Short name T855
Test name
Test status
Simulation time 7344220867 ps
CPU time 29.71 seconds
Started Jul 21 07:02:11 PM PDT 24
Finished Jul 21 07:02:42 PM PDT 24
Peak memory 247472 kb
Host smart-062682f2-6f67-463f-9615-3f0fe1f9fb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192251110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.4192251110
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2630826953
Short name T503
Test name
Test status
Simulation time 512572338 ps
CPU time 7.78 seconds
Started Jul 21 07:02:05 PM PDT 24
Finished Jul 21 07:02:15 PM PDT 24
Peak memory 250120 kb
Host smart-cf9b0dc1-80bb-46c6-81bf-592e91f46fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630826953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2630826953
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.415457630
Short name T827
Test name
Test status
Simulation time 18135374559 ps
CPU time 616.52 seconds
Started Jul 21 07:02:00 PM PDT 24
Finished Jul 21 07:12:19 PM PDT 24
Peak memory 283260 kb
Host smart-ff54ae0f-3941-48a7-8c1e-ac059ae6b2b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415457630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.415457630
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.248123147
Short name T773
Test name
Test status
Simulation time 24243140 ps
CPU time 0.9 seconds
Started Jul 21 07:02:02 PM PDT 24
Finished Jul 21 07:02:06 PM PDT 24
Peak memory 211464 kb
Host smart-778c225d-50d2-4441-8383-65e85ddfc4c3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248123147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.248123147
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1804754764
Short name T227
Test name
Test status
Simulation time 106481543 ps
CPU time 1.3 seconds
Started Jul 21 07:01:19 PM PDT 24
Finished Jul 21 07:01:21 PM PDT 24
Peak memory 208456 kb
Host smart-b8af7571-c20b-4d12-9947-77a18d89b50e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804754764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1804754764
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3727512335
Short name T801
Test name
Test status
Simulation time 3066743356 ps
CPU time 12.71 seconds
Started Jul 21 07:01:11 PM PDT 24
Finished Jul 21 07:01:24 PM PDT 24
Peak memory 218532 kb
Host smart-7a14d312-8c80-4c8d-801b-cba92c51968d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727512335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3727512335
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.539214121
Short name T604
Test name
Test status
Simulation time 210723905 ps
CPU time 2.04 seconds
Started Jul 21 07:01:17 PM PDT 24
Finished Jul 21 07:01:19 PM PDT 24
Peak memory 216632 kb
Host smart-83f51d56-2f09-4838-934d-615518dc0525
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539214121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.539214121
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2957302609
Short name T10
Test name
Test status
Simulation time 1231578418 ps
CPU time 23.09 seconds
Started Jul 21 07:01:20 PM PDT 24
Finished Jul 21 07:01:44 PM PDT 24
Peak memory 218376 kb
Host smart-c6305b12-aabd-4cb7-9920-14047d51250c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957302609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2957302609
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.687180780
Short name T509
Test name
Test status
Simulation time 1982100236 ps
CPU time 13.39 seconds
Started Jul 21 07:01:08 PM PDT 24
Finished Jul 21 07:01:24 PM PDT 24
Peak memory 224096 kb
Host smart-87cf4b37-9a86-4807-b586-63f65eb84f40
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687180780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
prog_failure.687180780
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1174348531
Short name T86
Test name
Test status
Simulation time 5442123018 ps
CPU time 34.69 seconds
Started Jul 21 07:01:17 PM PDT 24
Finished Jul 21 07:01:52 PM PDT 24
Peak memory 217284 kb
Host smart-4a49cad1-9ec2-4a49-a000-0402cb4e85b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174348531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1174348531
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2949116204
Short name T525
Test name
Test status
Simulation time 1309184622 ps
CPU time 9.96 seconds
Started Jul 21 07:01:07 PM PDT 24
Finished Jul 21 07:01:23 PM PDT 24
Peak memory 217128 kb
Host smart-55e35b4a-37b5-44e7-805e-4331d57d0b05
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949116204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2949116204
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1573831308
Short name T839
Test name
Test status
Simulation time 5896518865 ps
CPU time 50.36 seconds
Started Jul 21 07:01:16 PM PDT 24
Finished Jul 21 07:02:06 PM PDT 24
Peak memory 276516 kb
Host smart-23ccbe2b-b0e8-49a7-b78d-dea2f92bcf85
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573831308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1573831308
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3128171444
Short name T548
Test name
Test status
Simulation time 2222838963 ps
CPU time 22.16 seconds
Started Jul 21 07:01:28 PM PDT 24
Finished Jul 21 07:01:50 PM PDT 24
Peak memory 250564 kb
Host smart-835cbff7-7ab3-479b-ab65-2e191845f1a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128171444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3128171444
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3150414146
Short name T407
Test name
Test status
Simulation time 147323839 ps
CPU time 3.2 seconds
Started Jul 21 07:01:13 PM PDT 24
Finished Jul 21 07:01:17 PM PDT 24
Peak memory 217692 kb
Host smart-3cafd838-a642-4cd4-a74e-ee0efcfdea55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150414146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3150414146
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.646055099
Short name T82
Test name
Test status
Simulation time 982575781 ps
CPU time 11.91 seconds
Started Jul 21 07:01:07 PM PDT 24
Finished Jul 21 07:01:25 PM PDT 24
Peak memory 217356 kb
Host smart-b62a7cd2-50e7-4152-a469-7694f99c0931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646055099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.646055099
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3586754913
Short name T56
Test name
Test status
Simulation time 271852257 ps
CPU time 42.8 seconds
Started Jul 21 07:01:29 PM PDT 24
Finished Jul 21 07:02:12 PM PDT 24
Peak memory 282196 kb
Host smart-6ec9b8b7-7d72-4147-90a2-5e9c1e5aff2c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586754913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3586754913
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1186871157
Short name T416
Test name
Test status
Simulation time 2270775462 ps
CPU time 9.61 seconds
Started Jul 21 07:01:14 PM PDT 24
Finished Jul 21 07:01:24 PM PDT 24
Peak memory 217996 kb
Host smart-5dba1724-a89b-4f89-a7fe-a65f3af5bec9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186871157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1186871157
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2553648872
Short name T614
Test name
Test status
Simulation time 674783009 ps
CPU time 7.3 seconds
Started Jul 21 07:01:08 PM PDT 24
Finished Jul 21 07:01:17 PM PDT 24
Peak memory 217840 kb
Host smart-934448e9-32a5-4084-a615-6d0fe8ac7562
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553648872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2553648872
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.4000491679
Short name T361
Test name
Test status
Simulation time 360509147 ps
CPU time 9.13 seconds
Started Jul 21 07:01:10 PM PDT 24
Finished Jul 21 07:01:21 PM PDT 24
Peak memory 225560 kb
Host smart-ca8927b8-50b2-4c3d-9d55-31f3c76661d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000491679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.4
000491679
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2490432515
Short name T727
Test name
Test status
Simulation time 281701994 ps
CPU time 6.98 seconds
Started Jul 21 07:01:23 PM PDT 24
Finished Jul 21 07:01:30 PM PDT 24
Peak memory 217836 kb
Host smart-04147333-7f0e-49c1-af1d-2ef5d2f7106a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490432515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2490432515
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2732789419
Short name T74
Test name
Test status
Simulation time 36919737 ps
CPU time 1.89 seconds
Started Jul 21 07:01:06 PM PDT 24
Finished Jul 21 07:01:10 PM PDT 24
Peak memory 213452 kb
Host smart-71e625a9-274d-4c74-973b-ed4ddf30ed3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732789419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2732789419
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1271661585
Short name T292
Test name
Test status
Simulation time 1360051966 ps
CPU time 30.15 seconds
Started Jul 21 07:01:10 PM PDT 24
Finished Jul 21 07:01:41 PM PDT 24
Peak memory 250572 kb
Host smart-498bf795-629a-4699-b8cc-169f76fb5461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271661585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1271661585
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3149099056
Short name T790
Test name
Test status
Simulation time 77775018 ps
CPU time 8.8 seconds
Started Jul 21 07:01:11 PM PDT 24
Finished Jul 21 07:01:20 PM PDT 24
Peak memory 250532 kb
Host smart-f6e399bf-77e1-4816-bd15-a1118ba55773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149099056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3149099056
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.424772655
Short name T88
Test name
Test status
Simulation time 53428740315 ps
CPU time 200.08 seconds
Started Jul 21 07:01:23 PM PDT 24
Finished Jul 21 07:04:44 PM PDT 24
Peak memory 282444 kb
Host smart-a832b2f4-1e67-480f-9137-1d1f968a1185
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424772655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.424772655
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3389438719
Short name T653
Test name
Test status
Simulation time 19826854 ps
CPU time 0.8 seconds
Started Jul 21 07:01:03 PM PDT 24
Finished Jul 21 07:01:07 PM PDT 24
Peak memory 208436 kb
Host smart-3aa08203-03bb-4450-bcdf-5d248caa8b85
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389438719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3389438719
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3266113398
Short name T283
Test name
Test status
Simulation time 18554556 ps
CPU time 1 seconds
Started Jul 21 07:02:21 PM PDT 24
Finished Jul 21 07:02:22 PM PDT 24
Peak memory 208436 kb
Host smart-5301fcab-9f54-464d-aa68-3fa727f8da91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266113398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3266113398
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2640430682
Short name T710
Test name
Test status
Simulation time 1371370923 ps
CPU time 14.96 seconds
Started Jul 21 07:02:02 PM PDT 24
Finished Jul 21 07:02:20 PM PDT 24
Peak memory 217860 kb
Host smart-0b5a7e8a-f876-41e6-a23c-97150e33057c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640430682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2640430682
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.621738065
Short name T22
Test name
Test status
Simulation time 453194237 ps
CPU time 12.31 seconds
Started Jul 21 07:02:13 PM PDT 24
Finished Jul 21 07:02:25 PM PDT 24
Peak memory 216992 kb
Host smart-6a809326-5936-416b-b9a9-203d413398a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621738065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.621738065
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.3813977992
Short name T630
Test name
Test status
Simulation time 246634921 ps
CPU time 3.12 seconds
Started Jul 21 07:02:04 PM PDT 24
Finished Jul 21 07:02:10 PM PDT 24
Peak memory 217900 kb
Host smart-7300f82f-5e8e-4025-898c-4ce92a1d2c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813977992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3813977992
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.218062513
Short name T566
Test name
Test status
Simulation time 2050369075 ps
CPU time 13.5 seconds
Started Jul 21 07:02:11 PM PDT 24
Finished Jul 21 07:02:25 PM PDT 24
Peak memory 225648 kb
Host smart-28d9c128-b9d6-4482-88b6-a298b6385443
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218062513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.218062513
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.4196772618
Short name T422
Test name
Test status
Simulation time 170348671 ps
CPU time 7.97 seconds
Started Jul 21 07:02:11 PM PDT 24
Finished Jul 21 07:02:20 PM PDT 24
Peak memory 217872 kb
Host smart-ba32daa8-70d7-4a10-b3ed-3ba59b274932
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196772618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.4196772618
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.430314913
Short name T834
Test name
Test status
Simulation time 235871337 ps
CPU time 8.53 seconds
Started Jul 21 07:02:00 PM PDT 24
Finished Jul 21 07:02:11 PM PDT 24
Peak memory 224332 kb
Host smart-e35f3e82-a132-45d2-9481-404e2e8cd1b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430314913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.430314913
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.4267049406
Short name T366
Test name
Test status
Simulation time 317727593 ps
CPU time 7.12 seconds
Started Jul 21 07:02:00 PM PDT 24
Finished Jul 21 07:02:10 PM PDT 24
Peak memory 217888 kb
Host smart-84d85430-1e70-429f-8517-10b6a89e3b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267049406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.4267049406
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1264525983
Short name T85
Test name
Test status
Simulation time 199106396 ps
CPU time 3.41 seconds
Started Jul 21 07:02:01 PM PDT 24
Finished Jul 21 07:02:07 PM PDT 24
Peak memory 217160 kb
Host smart-25947a67-31b9-4df0-b9c8-d15c881e1ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264525983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1264525983
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2133421586
Short name T323
Test name
Test status
Simulation time 206659804 ps
CPU time 20.93 seconds
Started Jul 21 07:02:00 PM PDT 24
Finished Jul 21 07:02:23 PM PDT 24
Peak memory 250524 kb
Host smart-026fd307-a84b-482f-8167-326a2942cc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133421586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2133421586
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.137569129
Short name T476
Test name
Test status
Simulation time 118110887 ps
CPU time 3.89 seconds
Started Jul 21 07:02:06 PM PDT 24
Finished Jul 21 07:02:12 PM PDT 24
Peak memory 222556 kb
Host smart-d580b357-68a0-43b0-ac46-de2dae6c41bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137569129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.137569129
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2748498281
Short name T189
Test name
Test status
Simulation time 3872939556 ps
CPU time 143.75 seconds
Started Jul 21 07:02:01 PM PDT 24
Finished Jul 21 07:04:27 PM PDT 24
Peak memory 269960 kb
Host smart-e667a60b-12f8-4843-9dbf-a41ad05d38ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748498281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2748498281
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1678099613
Short name T351
Test name
Test status
Simulation time 28162301 ps
CPU time 0.84 seconds
Started Jul 21 07:02:00 PM PDT 24
Finished Jul 21 07:02:03 PM PDT 24
Peak memory 207824 kb
Host smart-1708e8c1-d681-4752-834e-8ae32945b863
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678099613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1678099613
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1989777281
Short name T632
Test name
Test status
Simulation time 19168621 ps
CPU time 0.91 seconds
Started Jul 21 07:02:05 PM PDT 24
Finished Jul 21 07:02:08 PM PDT 24
Peak memory 208392 kb
Host smart-b116b846-f649-4533-89a8-80c398762f29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989777281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1989777281
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.9035079
Short name T46
Test name
Test status
Simulation time 298559974 ps
CPU time 12.25 seconds
Started Jul 21 07:02:09 PM PDT 24
Finished Jul 21 07:02:22 PM PDT 24
Peak memory 217832 kb
Host smart-40966b63-c3e0-44d2-8641-7d4002a605c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9035079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.9035079
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1159520366
Short name T655
Test name
Test status
Simulation time 1029441874 ps
CPU time 4.26 seconds
Started Jul 21 07:02:01 PM PDT 24
Finished Jul 21 07:02:08 PM PDT 24
Peak memory 216724 kb
Host smart-5a90a6e3-1aa5-453b-98df-bd27c38010b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159520366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1159520366
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.442255273
Short name T781
Test name
Test status
Simulation time 690413623 ps
CPU time 3.2 seconds
Started Jul 21 07:02:05 PM PDT 24
Finished Jul 21 07:02:11 PM PDT 24
Peak memory 222196 kb
Host smart-00166475-f365-436a-837a-1784bdd83b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442255273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.442255273
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1499171875
Short name T185
Test name
Test status
Simulation time 825036753 ps
CPU time 10.23 seconds
Started Jul 21 07:02:17 PM PDT 24
Finished Jul 21 07:02:27 PM PDT 24
Peak memory 217784 kb
Host smart-bb136201-6ec2-410b-b86f-dc55b4a59938
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499171875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1499171875
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2668513960
Short name T600
Test name
Test status
Simulation time 296283778 ps
CPU time 11.26 seconds
Started Jul 21 07:02:02 PM PDT 24
Finished Jul 21 07:02:16 PM PDT 24
Peak memory 225516 kb
Host smart-250520f5-11a9-4beb-9aca-2a16c377cb75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668513960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2668513960
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1738544872
Short name T495
Test name
Test status
Simulation time 836206208 ps
CPU time 6.3 seconds
Started Jul 21 07:02:01 PM PDT 24
Finished Jul 21 07:02:11 PM PDT 24
Peak memory 217944 kb
Host smart-8f76a44e-40f3-4b71-9238-15242fd1bb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738544872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1738544872
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1788654583
Short name T87
Test name
Test status
Simulation time 17671647 ps
CPU time 1.3 seconds
Started Jul 21 07:02:11 PM PDT 24
Finished Jul 21 07:02:13 PM PDT 24
Peak memory 217212 kb
Host smart-a25a9515-95e1-456a-b567-06035e08038c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788654583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1788654583
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.608338591
Short name T486
Test name
Test status
Simulation time 1763087347 ps
CPU time 20.91 seconds
Started Jul 21 07:01:59 PM PDT 24
Finished Jul 21 07:02:22 PM PDT 24
Peak memory 250540 kb
Host smart-6c89deaf-bb18-4a39-87cc-29fb54efa091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608338591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.608338591
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.779138729
Short name T27
Test name
Test status
Simulation time 73993563 ps
CPU time 6.97 seconds
Started Jul 21 07:02:06 PM PDT 24
Finished Jul 21 07:02:19 PM PDT 24
Peak memory 246108 kb
Host smart-2ca9e917-cebf-44a3-9440-c90675f8c843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779138729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.779138729
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.813141197
Short name T328
Test name
Test status
Simulation time 42691715254 ps
CPU time 180.69 seconds
Started Jul 21 07:02:16 PM PDT 24
Finished Jul 21 07:05:17 PM PDT 24
Peak memory 250488 kb
Host smart-71ec116e-34d5-4be3-9161-34f30daa1c62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813141197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.813141197
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.609987683
Short name T58
Test name
Test status
Simulation time 30238577318 ps
CPU time 849.61 seconds
Started Jul 21 07:02:14 PM PDT 24
Finished Jul 21 07:16:24 PM PDT 24
Peak memory 414580 kb
Host smart-64f9cc9a-9d38-4d03-b09e-cc608b98d691
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=609987683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.609987683
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.4139178070
Short name T806
Test name
Test status
Simulation time 37749905 ps
CPU time 0.94 seconds
Started Jul 21 07:02:12 PM PDT 24
Finished Jul 21 07:02:14 PM PDT 24
Peak memory 208424 kb
Host smart-574d5a67-75f3-46e2-88c3-0e1f3072a15b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139178070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.4139178070
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2037792957
Short name T71
Test name
Test status
Simulation time 76719732 ps
CPU time 1.01 seconds
Started Jul 21 07:02:13 PM PDT 24
Finished Jul 21 07:02:14 PM PDT 24
Peak memory 208412 kb
Host smart-28cb8807-a60e-4752-aefd-15c5b668fb19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037792957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2037792957
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2557224991
Short name T186
Test name
Test status
Simulation time 550221421 ps
CPU time 16.2 seconds
Started Jul 21 07:02:23 PM PDT 24
Finished Jul 21 07:02:39 PM PDT 24
Peak memory 217820 kb
Host smart-229dea93-7ceb-45b0-87e4-205a7a05138d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557224991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2557224991
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.290478071
Short name T565
Test name
Test status
Simulation time 84744256 ps
CPU time 1.66 seconds
Started Jul 21 07:02:17 PM PDT 24
Finished Jul 21 07:02:19 PM PDT 24
Peak memory 217124 kb
Host smart-e5fd6a26-5128-4ed5-b157-1b3b3fcf20f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290478071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.290478071
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3384901090
Short name T670
Test name
Test status
Simulation time 36267345 ps
CPU time 1.96 seconds
Started Jul 21 07:02:03 PM PDT 24
Finished Jul 21 07:02:07 PM PDT 24
Peak memory 217828 kb
Host smart-af393db3-6852-40cc-9d00-bdc4d957da00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384901090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3384901090
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.3343288975
Short name T45
Test name
Test status
Simulation time 461052819 ps
CPU time 15.31 seconds
Started Jul 21 07:02:14 PM PDT 24
Finished Jul 21 07:02:30 PM PDT 24
Peak memory 219536 kb
Host smart-d518b9f1-94c1-4337-9f60-94af09f6c2a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343288975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3343288975
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2307263385
Short name T721
Test name
Test status
Simulation time 2044842295 ps
CPU time 17.87 seconds
Started Jul 21 07:02:11 PM PDT 24
Finished Jul 21 07:02:30 PM PDT 24
Peak memory 217844 kb
Host smart-1fa24c6a-14c2-4d40-af4e-8d55643fecc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307263385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2307263385
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1108988233
Short name T606
Test name
Test status
Simulation time 819835649 ps
CPU time 7.07 seconds
Started Jul 21 07:02:05 PM PDT 24
Finished Jul 21 07:02:14 PM PDT 24
Peak memory 225520 kb
Host smart-0b420e58-7e51-4dd0-b8ec-1ad459e7432f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108988233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
1108988233
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2296620145
Short name T372
Test name
Test status
Simulation time 74853581 ps
CPU time 2.43 seconds
Started Jul 21 07:02:03 PM PDT 24
Finished Jul 21 07:02:08 PM PDT 24
Peak memory 213648 kb
Host smart-9f5c21c0-7c59-42db-a008-19b7c5306198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296620145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2296620145
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.943348039
Short name T373
Test name
Test status
Simulation time 223062253 ps
CPU time 24.41 seconds
Started Jul 21 07:02:04 PM PDT 24
Finished Jul 21 07:02:31 PM PDT 24
Peak memory 250480 kb
Host smart-a265a5a3-5fb0-4619-b4dd-f938d447b0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943348039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.943348039
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.533527730
Short name T578
Test name
Test status
Simulation time 69753799 ps
CPU time 6.97 seconds
Started Jul 21 07:02:23 PM PDT 24
Finished Jul 21 07:02:31 PM PDT 24
Peak memory 250564 kb
Host smart-f6e48c57-6ab4-415f-a12f-00a517367b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533527730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.533527730
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3337078373
Short name T854
Test name
Test status
Simulation time 9064224978 ps
CPU time 284.51 seconds
Started Jul 21 07:02:04 PM PDT 24
Finished Jul 21 07:06:51 PM PDT 24
Peak memory 250528 kb
Host smart-4b28b251-3a71-47a2-9e36-b249f13f3be6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337078373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3337078373
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.657573574
Short name T234
Test name
Test status
Simulation time 51208740 ps
CPU time 0.95 seconds
Started Jul 21 07:02:23 PM PDT 24
Finished Jul 21 07:02:30 PM PDT 24
Peak memory 208476 kb
Host smart-fe318eef-8106-4ae5-a549-cf9127c86d27
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657573574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.657573574
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2263293919
Short name T743
Test name
Test status
Simulation time 35158669 ps
CPU time 1 seconds
Started Jul 21 07:02:08 PM PDT 24
Finished Jul 21 07:02:10 PM PDT 24
Peak memory 208392 kb
Host smart-bd8fb680-28f8-46cb-89be-f8a548755aa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263293919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2263293919
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3306458721
Short name T419
Test name
Test status
Simulation time 1250646738 ps
CPU time 10.92 seconds
Started Jul 21 07:02:27 PM PDT 24
Finished Jul 21 07:02:39 PM PDT 24
Peak memory 217772 kb
Host smart-a428e7a8-5bed-4d7c-aec9-6babffafe9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306458721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3306458721
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2942428893
Short name T403
Test name
Test status
Simulation time 3109336719 ps
CPU time 19.62 seconds
Started Jul 21 07:02:19 PM PDT 24
Finished Jul 21 07:02:39 PM PDT 24
Peak memory 217288 kb
Host smart-0fe56d90-b77f-4d03-80e2-70c6ef95caa9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942428893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2942428893
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2925171560
Short name T506
Test name
Test status
Simulation time 90693888 ps
CPU time 2.2 seconds
Started Jul 21 07:02:26 PM PDT 24
Finished Jul 21 07:02:29 PM PDT 24
Peak memory 217820 kb
Host smart-48413fe4-a8ee-42d2-aaa7-f57ee6e9bb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925171560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2925171560
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1220048899
Short name T738
Test name
Test status
Simulation time 1484821460 ps
CPU time 9.17 seconds
Started Jul 21 07:02:21 PM PDT 24
Finished Jul 21 07:02:30 PM PDT 24
Peak memory 225272 kb
Host smart-14e8bf26-5361-480e-9906-e3e8f8a92718
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220048899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1220048899
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1721482140
Short name T356
Test name
Test status
Simulation time 1249084451 ps
CPU time 13.7 seconds
Started Jul 21 07:02:21 PM PDT 24
Finished Jul 21 07:02:36 PM PDT 24
Peak memory 225524 kb
Host smart-f1d68ee4-ea2f-4117-8967-b105aaac4e66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721482140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1721482140
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2687647290
Short name T60
Test name
Test status
Simulation time 1860668096 ps
CPU time 14.52 seconds
Started Jul 21 07:02:21 PM PDT 24
Finished Jul 21 07:02:35 PM PDT 24
Peak memory 225580 kb
Host smart-f2487ff2-7e5d-4155-9315-110351bf8669
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687647290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2687647290
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2080566965
Short name T842
Test name
Test status
Simulation time 353526540 ps
CPU time 11.91 seconds
Started Jul 21 07:02:27 PM PDT 24
Finished Jul 21 07:02:40 PM PDT 24
Peak memory 225620 kb
Host smart-796a1652-0006-4334-9863-bf0a59a3780b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080566965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2080566965
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.3755306623
Short name T352
Test name
Test status
Simulation time 278301275 ps
CPU time 2.78 seconds
Started Jul 21 07:02:12 PM PDT 24
Finished Jul 21 07:02:15 PM PDT 24
Peak memory 214264 kb
Host smart-c19e2043-5416-4a60-bd31-d5d1b03fc356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755306623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3755306623
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.4178881163
Short name T259
Test name
Test status
Simulation time 323407598 ps
CPU time 28.95 seconds
Started Jul 21 07:02:18 PM PDT 24
Finished Jul 21 07:02:47 PM PDT 24
Peak memory 250648 kb
Host smart-f1a65bb6-75d9-4788-85f8-468468676d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178881163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.4178881163
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.1448347877
Short name T792
Test name
Test status
Simulation time 178070049 ps
CPU time 6.44 seconds
Started Jul 21 07:02:04 PM PDT 24
Finished Jul 21 07:02:14 PM PDT 24
Peak memory 246656 kb
Host smart-a37db8fa-9449-44ab-b9de-be0200465609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448347877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.1448347877
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2184860605
Short name T441
Test name
Test status
Simulation time 9231902370 ps
CPU time 316.27 seconds
Started Jul 21 07:02:28 PM PDT 24
Finished Jul 21 07:07:45 PM PDT 24
Peak memory 371656 kb
Host smart-3dd01c44-8037-48cb-ac04-011f52bbc819
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184860605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2184860605
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3513075615
Short name T36
Test name
Test status
Simulation time 14593971 ps
CPU time 0.87 seconds
Started Jul 21 07:02:15 PM PDT 24
Finished Jul 21 07:02:17 PM PDT 24
Peak memory 208400 kb
Host smart-8d5afca1-52fc-4027-a228-7ac25b851bd9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513075615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3513075615
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.866566585
Short name T181
Test name
Test status
Simulation time 17643818 ps
CPU time 1.04 seconds
Started Jul 21 07:02:17 PM PDT 24
Finished Jul 21 07:02:19 PM PDT 24
Peak memory 208464 kb
Host smart-5863178f-0b91-4fd9-93c1-fb13101d1c6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866566585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.866566585
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1802768081
Short name T554
Test name
Test status
Simulation time 3698744766 ps
CPU time 18.72 seconds
Started Jul 21 07:02:30 PM PDT 24
Finished Jul 21 07:02:49 PM PDT 24
Peak memory 218452 kb
Host smart-48907c84-9a43-4678-8e35-a6ea84a65da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802768081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1802768081
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.579423132
Short name T692
Test name
Test status
Simulation time 526800965 ps
CPU time 6.92 seconds
Started Jul 21 07:02:25 PM PDT 24
Finished Jul 21 07:02:32 PM PDT 24
Peak memory 216536 kb
Host smart-0a2cc08c-8fbe-4f65-b505-d518b5f70cbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579423132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.579423132
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.2282422892
Short name T365
Test name
Test status
Simulation time 72426003 ps
CPU time 2.62 seconds
Started Jul 21 07:02:21 PM PDT 24
Finished Jul 21 07:02:24 PM PDT 24
Peak memory 221984 kb
Host smart-e6108499-6b63-45cc-8f21-c79663614b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282422892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2282422892
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2380375479
Short name T762
Test name
Test status
Simulation time 803005178 ps
CPU time 18.19 seconds
Started Jul 21 07:02:29 PM PDT 24
Finished Jul 21 07:02:48 PM PDT 24
Peak memory 217908 kb
Host smart-87852ce0-776d-4ae5-807c-83580d12812b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380375479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2380375479
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1062892295
Short name T766
Test name
Test status
Simulation time 1118452751 ps
CPU time 12.93 seconds
Started Jul 21 07:02:21 PM PDT 24
Finished Jul 21 07:02:34 PM PDT 24
Peak memory 217804 kb
Host smart-9efb10a1-48cf-439e-8c15-d0b4942cc2c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062892295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1062892295
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.711485196
Short name T778
Test name
Test status
Simulation time 353937786 ps
CPU time 8.69 seconds
Started Jul 21 07:02:16 PM PDT 24
Finished Jul 21 07:02:25 PM PDT 24
Peak memory 224860 kb
Host smart-98bae241-b965-4423-9851-774b5a8bfa1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711485196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.711485196
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.828947079
Short name T477
Test name
Test status
Simulation time 1697219137 ps
CPU time 11.69 seconds
Started Jul 21 07:02:27 PM PDT 24
Finished Jul 21 07:02:39 PM PDT 24
Peak memory 217900 kb
Host smart-75c3968a-645f-4914-ab5a-24472f0fd00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828947079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.828947079
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2110351260
Short name T680
Test name
Test status
Simulation time 61264327 ps
CPU time 4.45 seconds
Started Jul 21 07:02:19 PM PDT 24
Finished Jul 21 07:02:24 PM PDT 24
Peak memory 217360 kb
Host smart-8f32f96a-3f88-4ba1-882d-b40a8b402b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110351260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2110351260
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3174645132
Short name T236
Test name
Test status
Simulation time 613860827 ps
CPU time 28.91 seconds
Started Jul 21 07:02:32 PM PDT 24
Finished Jul 21 07:03:02 PM PDT 24
Peak memory 250568 kb
Host smart-9cbf9834-a81c-4b22-8bf2-29a7b347f2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174645132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3174645132
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1560346999
Short name T251
Test name
Test status
Simulation time 84909731 ps
CPU time 8.62 seconds
Started Jul 21 07:02:36 PM PDT 24
Finished Jul 21 07:02:46 PM PDT 24
Peak memory 250404 kb
Host smart-60b5ab10-b609-4ef1-833d-193217af76dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560346999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1560346999
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.27798425
Short name T17
Test name
Test status
Simulation time 8488580905 ps
CPU time 69.13 seconds
Started Jul 21 07:02:25 PM PDT 24
Finished Jul 21 07:03:34 PM PDT 24
Peak memory 249172 kb
Host smart-947c88bd-91eb-4a95-bffd-72c27ae966ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27798425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.lc_ctrl_stress_all.27798425
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2463562520
Short name T376
Test name
Test status
Simulation time 28229685 ps
CPU time 0.92 seconds
Started Jul 21 07:02:33 PM PDT 24
Finished Jul 21 07:02:35 PM PDT 24
Peak memory 211388 kb
Host smart-41e3e301-a76b-4dcf-a6b4-575a952883e3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463562520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2463562520
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.25840815
Short name T286
Test name
Test status
Simulation time 194170483 ps
CPU time 1.1 seconds
Started Jul 21 07:02:38 PM PDT 24
Finished Jul 21 07:02:40 PM PDT 24
Peak memory 208492 kb
Host smart-0545f7ed-d000-4f6c-abaa-2d73a499ce56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25840815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.25840815
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3054497565
Short name T391
Test name
Test status
Simulation time 1094027886 ps
CPU time 11.21 seconds
Started Jul 21 07:02:25 PM PDT 24
Finished Jul 21 07:02:37 PM PDT 24
Peak memory 217748 kb
Host smart-a75ccf05-2300-48d4-8897-7261a3f6a227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054497565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3054497565
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2445897081
Short name T287
Test name
Test status
Simulation time 112740245 ps
CPU time 1.35 seconds
Started Jul 21 07:02:15 PM PDT 24
Finished Jul 21 07:02:16 PM PDT 24
Peak memory 216480 kb
Host smart-eec8a426-cb56-4010-9f95-e2ccd2b037a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445897081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2445897081
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.77815872
Short name T844
Test name
Test status
Simulation time 194913860 ps
CPU time 3.62 seconds
Started Jul 21 07:02:22 PM PDT 24
Finished Jul 21 07:02:26 PM PDT 24
Peak memory 217852 kb
Host smart-20a70f81-9962-4ef6-8cf1-360212f45b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77815872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.77815872
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.842526698
Short name T640
Test name
Test status
Simulation time 1663246072 ps
CPU time 17.74 seconds
Started Jul 21 07:02:25 PM PDT 24
Finished Jul 21 07:02:43 PM PDT 24
Peak memory 218460 kb
Host smart-8173d390-425a-4516-a050-8e3436179767
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842526698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.842526698
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.458259122
Short name T261
Test name
Test status
Simulation time 2083915720 ps
CPU time 12.34 seconds
Started Jul 21 07:02:24 PM PDT 24
Finished Jul 21 07:02:37 PM PDT 24
Peak memory 218016 kb
Host smart-06d1ed5c-f28e-4e17-a9da-2973e53a7c2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458259122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.458259122
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1492443821
Short name T465
Test name
Test status
Simulation time 736204182 ps
CPU time 9.07 seconds
Started Jul 21 07:02:26 PM PDT 24
Finished Jul 21 07:02:36 PM PDT 24
Peak memory 225544 kb
Host smart-fde42e3b-5b02-4f91-8c69-f9611f798453
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492443821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1492443821
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1662043468
Short name T383
Test name
Test status
Simulation time 1228315921 ps
CPU time 11.62 seconds
Started Jul 21 07:02:31 PM PDT 24
Finished Jul 21 07:02:44 PM PDT 24
Peak memory 225556 kb
Host smart-7d652d74-b450-416a-88f8-fae6662010be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662043468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1662043468
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.607092940
Short name T332
Test name
Test status
Simulation time 67508464 ps
CPU time 2.94 seconds
Started Jul 21 07:02:33 PM PDT 24
Finished Jul 21 07:02:37 PM PDT 24
Peak memory 217156 kb
Host smart-b5c92ac2-fb68-4adb-8e68-69e5bfd9a842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607092940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.607092940
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3011352166
Short name T645
Test name
Test status
Simulation time 500528723 ps
CPU time 15.22 seconds
Started Jul 21 07:02:21 PM PDT 24
Finished Jul 21 07:02:37 PM PDT 24
Peak memory 250576 kb
Host smart-5459b51c-1dda-4ccb-bdd3-3f04e1c42cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011352166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3011352166
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1818106485
Short name T180
Test name
Test status
Simulation time 67534561 ps
CPU time 7.52 seconds
Started Jul 21 07:02:14 PM PDT 24
Finished Jul 21 07:02:22 PM PDT 24
Peak memory 250500 kb
Host smart-f57826d2-175f-4d22-adf3-a9889a4df178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818106485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1818106485
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1579422098
Short name T78
Test name
Test status
Simulation time 12494536508 ps
CPU time 122.82 seconds
Started Jul 21 07:02:27 PM PDT 24
Finished Jul 21 07:04:31 PM PDT 24
Peak memory 250640 kb
Host smart-70dda866-38ce-4dfa-a0dd-e9f06d7deb3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579422098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1579422098
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.606855997
Short name T408
Test name
Test status
Simulation time 23481031 ps
CPU time 0.97 seconds
Started Jul 21 07:02:22 PM PDT 24
Finished Jul 21 07:02:24 PM PDT 24
Peak memory 208424 kb
Host smart-cdafe5ec-b235-4280-b900-65ba97ceea00
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606855997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.606855997
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1104704179
Short name T544
Test name
Test status
Simulation time 17136761 ps
CPU time 1.13 seconds
Started Jul 21 07:02:28 PM PDT 24
Finished Jul 21 07:02:31 PM PDT 24
Peak memory 208636 kb
Host smart-fab40b9a-e55a-448c-905b-8f8351279625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104704179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1104704179
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.46586151
Short name T817
Test name
Test status
Simulation time 212777928 ps
CPU time 8.54 seconds
Started Jul 21 07:02:33 PM PDT 24
Finished Jul 21 07:02:42 PM PDT 24
Peak memory 217760 kb
Host smart-3966b5b8-4501-47b2-b84b-95b50b17d177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46586151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.46586151
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.4064457421
Short name T794
Test name
Test status
Simulation time 1700843333 ps
CPU time 4.81 seconds
Started Jul 21 07:02:31 PM PDT 24
Finished Jul 21 07:02:36 PM PDT 24
Peak memory 216600 kb
Host smart-a0870250-1774-46b9-8a25-997c8f3e1636
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064457421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.4064457421
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.999774142
Short name T481
Test name
Test status
Simulation time 120892915 ps
CPU time 3.28 seconds
Started Jul 21 07:02:25 PM PDT 24
Finished Jul 21 07:02:29 PM PDT 24
Peak memory 221936 kb
Host smart-7e415a7e-6b04-403c-b2fb-45ccb278e777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999774142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.999774142
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.1171756082
Short name T184
Test name
Test status
Simulation time 1199788214 ps
CPU time 14.55 seconds
Started Jul 21 07:02:37 PM PDT 24
Finished Jul 21 07:02:52 PM PDT 24
Peak memory 218504 kb
Host smart-428962c7-953b-4df8-ad71-6b1e047c4920
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171756082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1171756082
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3137718438
Short name T681
Test name
Test status
Simulation time 476253767 ps
CPU time 11.25 seconds
Started Jul 21 07:02:28 PM PDT 24
Finished Jul 21 07:02:40 PM PDT 24
Peak memory 217820 kb
Host smart-780c8a5f-3193-49c4-b0d7-7a87748e376c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137718438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3137718438
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1890651745
Short name T609
Test name
Test status
Simulation time 668448718 ps
CPU time 10.33 seconds
Started Jul 21 07:02:24 PM PDT 24
Finished Jul 21 07:02:35 PM PDT 24
Peak memory 225488 kb
Host smart-371379e9-cb2b-4c6b-88e3-4fa6862ac259
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890651745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1890651745
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.5346824
Short name T98
Test name
Test status
Simulation time 591326083 ps
CPU time 12.27 seconds
Started Jul 21 07:02:23 PM PDT 24
Finished Jul 21 07:02:36 PM PDT 24
Peak memory 225592 kb
Host smart-39400cd2-51c1-4936-aecb-025d087ef624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5346824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.5346824
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2831793411
Short name T777
Test name
Test status
Simulation time 19890010 ps
CPU time 1.64 seconds
Started Jul 21 07:02:22 PM PDT 24
Finished Jul 21 07:02:24 PM PDT 24
Peak memory 217240 kb
Host smart-0a36676e-e5ed-4209-89cb-af6699318c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831793411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2831793411
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3712977076
Short name T91
Test name
Test status
Simulation time 1057935565 ps
CPU time 26.78 seconds
Started Jul 21 07:02:25 PM PDT 24
Finished Jul 21 07:02:52 PM PDT 24
Peak memory 250536 kb
Host smart-498b327b-5769-4c6a-aa13-5a6e9af5bee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712977076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3712977076
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.445929085
Short name T187
Test name
Test status
Simulation time 151402830 ps
CPU time 7.51 seconds
Started Jul 21 07:02:30 PM PDT 24
Finished Jul 21 07:02:38 PM PDT 24
Peak memory 250540 kb
Host smart-e7b07e14-35d5-45d7-9d0a-e83a19c97bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445929085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.445929085
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1117601465
Short name T284
Test name
Test status
Simulation time 22061051270 ps
CPU time 101.45 seconds
Started Jul 21 07:02:26 PM PDT 24
Finished Jul 21 07:04:08 PM PDT 24
Peak memory 279420 kb
Host smart-05088c73-ef84-4798-ae4e-42f1c9b9b204
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117601465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1117601465
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.362526527
Short name T317
Test name
Test status
Simulation time 20764657 ps
CPU time 1.04 seconds
Started Jul 21 07:02:33 PM PDT 24
Finished Jul 21 07:02:34 PM PDT 24
Peak memory 217260 kb
Host smart-06ccf9a6-1aaf-49c6-97f3-7c1ae1a25f93
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362526527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.362526527
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.84838535
Short name T782
Test name
Test status
Simulation time 52362060 ps
CPU time 0.87 seconds
Started Jul 21 07:02:42 PM PDT 24
Finished Jul 21 07:02:45 PM PDT 24
Peak memory 208308 kb
Host smart-10ff0915-3e20-4232-a12e-cba075e143bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84838535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.84838535
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.427193219
Short name T488
Test name
Test status
Simulation time 483029591 ps
CPU time 11.06 seconds
Started Jul 21 07:02:37 PM PDT 24
Finished Jul 21 07:02:49 PM PDT 24
Peak memory 217832 kb
Host smart-3bfebe1a-360c-4dfe-9c41-b4082f7b0ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427193219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.427193219
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.4000556270
Short name T685
Test name
Test status
Simulation time 158325758 ps
CPU time 1.64 seconds
Started Jul 21 07:02:31 PM PDT 24
Finished Jul 21 07:02:34 PM PDT 24
Peak memory 216612 kb
Host smart-bb1f50bf-4a5a-411d-a314-f3de4cbb8469
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000556270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.4000556270
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.4228024742
Short name T564
Test name
Test status
Simulation time 21946831 ps
CPU time 1.82 seconds
Started Jul 21 07:02:31 PM PDT 24
Finished Jul 21 07:02:34 PM PDT 24
Peak memory 221816 kb
Host smart-b9be1059-a393-409d-b6d4-230c276a9c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228024742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.4228024742
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.1874130873
Short name T44
Test name
Test status
Simulation time 1131896929 ps
CPU time 11.9 seconds
Started Jul 21 07:02:28 PM PDT 24
Finished Jul 21 07:02:41 PM PDT 24
Peak memory 218480 kb
Host smart-ece605c2-dc8e-4118-86af-fddf2b84277f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874130873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.1874130873
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3955277627
Short name T301
Test name
Test status
Simulation time 1811875405 ps
CPU time 20.13 seconds
Started Jul 21 07:02:44 PM PDT 24
Finished Jul 21 07:03:05 PM PDT 24
Peak memory 225560 kb
Host smart-55a45b1f-c424-42ad-9f4a-5bef219f592a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955277627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3955277627
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2151433277
Short name T851
Test name
Test status
Simulation time 653481627 ps
CPU time 10.94 seconds
Started Jul 21 07:02:33 PM PDT 24
Finished Jul 21 07:02:45 PM PDT 24
Peak memory 225540 kb
Host smart-3b19db81-d14c-4707-98b7-92c27b72b5cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151433277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2151433277
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.16985230
Short name T409
Test name
Test status
Simulation time 558091179 ps
CPU time 10.59 seconds
Started Jul 21 07:02:36 PM PDT 24
Finished Jul 21 07:02:47 PM PDT 24
Peak memory 217880 kb
Host smart-679bc22d-7d91-4f43-a231-4d6c350f14fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16985230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.16985230
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3589581056
Short name T76
Test name
Test status
Simulation time 21488948 ps
CPU time 1.49 seconds
Started Jul 21 07:02:25 PM PDT 24
Finished Jul 21 07:02:27 PM PDT 24
Peak memory 222352 kb
Host smart-20ab217c-5402-46cf-a879-d3957bfe518c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589581056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3589581056
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.646234908
Short name T269
Test name
Test status
Simulation time 189073373 ps
CPU time 19.17 seconds
Started Jul 21 07:02:38 PM PDT 24
Finished Jul 21 07:02:58 PM PDT 24
Peak memory 250536 kb
Host smart-afd812c6-1df9-470d-9f8f-64b23a73fbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646234908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.646234908
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1765666669
Short name T780
Test name
Test status
Simulation time 347253271 ps
CPU time 7.64 seconds
Started Jul 21 07:02:38 PM PDT 24
Finished Jul 21 07:02:47 PM PDT 24
Peak memory 250552 kb
Host smart-c2200dfc-f58d-499c-9536-a4c13120f968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765666669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1765666669
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3032190378
Short name T104
Test name
Test status
Simulation time 10285372082 ps
CPU time 77.71 seconds
Started Jul 21 07:02:34 PM PDT 24
Finished Jul 21 07:03:53 PM PDT 24
Peak memory 267084 kb
Host smart-c41a224c-f77f-4d6c-88c1-1ce3eb5776e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032190378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3032190378
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.2200128258
Short name T763
Test name
Test status
Simulation time 104870162436 ps
CPU time 833.08 seconds
Started Jul 21 07:02:32 PM PDT 24
Finished Jul 21 07:16:26 PM PDT 24
Peak memory 342192 kb
Host smart-4297e760-d80f-4b43-885c-6e5901408496
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2200128258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.2200128258
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3940654712
Short name T84
Test name
Test status
Simulation time 15842788 ps
CPU time 1.21 seconds
Started Jul 21 07:02:35 PM PDT 24
Finished Jul 21 07:02:37 PM PDT 24
Peak memory 217184 kb
Host smart-04580ea6-bc94-4fb0-b101-e91b8cc94c78
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940654712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3940654712
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3748320499
Short name T447
Test name
Test status
Simulation time 46349342 ps
CPU time 1 seconds
Started Jul 21 07:02:33 PM PDT 24
Finished Jul 21 07:02:35 PM PDT 24
Peak memory 208440 kb
Host smart-3c76d741-43b7-46bf-b1d3-fed662721be7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748320499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3748320499
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.1026601495
Short name T513
Test name
Test status
Simulation time 297091958 ps
CPU time 14.79 seconds
Started Jul 21 07:02:39 PM PDT 24
Finished Jul 21 07:02:54 PM PDT 24
Peak memory 217804 kb
Host smart-233407b1-110a-4231-82ee-67d9086da3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026601495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.1026601495
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2503591762
Short name T9
Test name
Test status
Simulation time 709431099 ps
CPU time 13.89 seconds
Started Jul 21 07:02:37 PM PDT 24
Finished Jul 21 07:02:52 PM PDT 24
Peak memory 216912 kb
Host smart-a898973c-28f3-472d-a62d-3f396d183657
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503591762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2503591762
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.828720219
Short name T468
Test name
Test status
Simulation time 266274624 ps
CPU time 3.82 seconds
Started Jul 21 07:02:31 PM PDT 24
Finished Jul 21 07:02:35 PM PDT 24
Peak memory 217724 kb
Host smart-91cc0b66-c9cb-4263-9aa7-578382c3b314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828720219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.828720219
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.4067169398
Short name T322
Test name
Test status
Simulation time 526112368 ps
CPU time 23.08 seconds
Started Jul 21 07:02:37 PM PDT 24
Finished Jul 21 07:03:01 PM PDT 24
Peak memory 225616 kb
Host smart-7ab1980c-240c-49b3-95bc-7b565aa80450
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067169398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.4067169398
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2113417400
Short name T295
Test name
Test status
Simulation time 5839099120 ps
CPU time 8.85 seconds
Started Jul 21 07:02:34 PM PDT 24
Finished Jul 21 07:02:44 PM PDT 24
Peak memory 225616 kb
Host smart-be53d4c5-6e69-4317-9f97-9c9a31eee45d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113417400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2113417400
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3699692740
Short name T752
Test name
Test status
Simulation time 272529867 ps
CPU time 9.83 seconds
Started Jul 21 07:02:38 PM PDT 24
Finished Jul 21 07:02:49 PM PDT 24
Peak memory 225568 kb
Host smart-ffe5dd03-ec0a-460d-8788-7b9080c1b685
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699692740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3699692740
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2764813629
Short name T579
Test name
Test status
Simulation time 5307980388 ps
CPU time 11.1 seconds
Started Jul 21 07:02:32 PM PDT 24
Finished Jul 21 07:02:44 PM PDT 24
Peak memory 217992 kb
Host smart-e70da9f5-c1b8-4124-82a9-630a3c077cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764813629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2764813629
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3627926753
Short name T596
Test name
Test status
Simulation time 28316908 ps
CPU time 1.59 seconds
Started Jul 21 07:02:28 PM PDT 24
Finished Jul 21 07:02:31 PM PDT 24
Peak memory 213208 kb
Host smart-2ff68b60-8350-4141-b8b0-dc7dac98599d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627926753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3627926753
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.4035243864
Short name T649
Test name
Test status
Simulation time 1045342390 ps
CPU time 28.94 seconds
Started Jul 21 07:02:30 PM PDT 24
Finished Jul 21 07:03:00 PM PDT 24
Peak memory 250564 kb
Host smart-7b6df004-c1e8-4a92-b088-09dd6b4a9d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035243864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.4035243864
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1015494572
Short name T809
Test name
Test status
Simulation time 240250198 ps
CPU time 3.03 seconds
Started Jul 21 07:02:31 PM PDT 24
Finished Jul 21 07:02:35 PM PDT 24
Peak memory 225916 kb
Host smart-8c68d581-a806-4648-80ad-fbfee23f01aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015494572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1015494572
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1790234330
Short name T590
Test name
Test status
Simulation time 374905445 ps
CPU time 17.93 seconds
Started Jul 21 07:02:33 PM PDT 24
Finished Jul 21 07:02:51 PM PDT 24
Peak memory 244008 kb
Host smart-131b8ae3-519e-403d-822a-79a576b1fc30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790234330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1790234330
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1722009668
Short name T153
Test name
Test status
Simulation time 46282023636 ps
CPU time 210.8 seconds
Started Jul 21 07:02:40 PM PDT 24
Finished Jul 21 07:06:11 PM PDT 24
Peak memory 281660 kb
Host smart-17bbc298-8272-495c-bf2c-02caf1f980e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1722009668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.1722009668
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3004644451
Short name T231
Test name
Test status
Simulation time 15568416 ps
CPU time 0.87 seconds
Started Jul 21 07:02:36 PM PDT 24
Finished Jul 21 07:02:37 PM PDT 24
Peak memory 208608 kb
Host smart-64bee0aa-2689-4dcb-b832-e7f3fc651748
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004644451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3004644451
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.583600924
Short name T188
Test name
Test status
Simulation time 15707857 ps
CPU time 1.04 seconds
Started Jul 21 07:02:36 PM PDT 24
Finished Jul 21 07:02:38 PM PDT 24
Peak memory 208528 kb
Host smart-dd498cad-0161-4495-938d-5f6ed7d73578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583600924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.583600924
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.723336754
Short name T305
Test name
Test status
Simulation time 1105055987 ps
CPU time 12.68 seconds
Started Jul 21 07:02:33 PM PDT 24
Finished Jul 21 07:02:47 PM PDT 24
Peak memory 217748 kb
Host smart-c3369636-7069-4805-955c-098d59e10bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723336754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.723336754
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1998186723
Short name T19
Test name
Test status
Simulation time 517459445 ps
CPU time 4.18 seconds
Started Jul 21 07:02:33 PM PDT 24
Finished Jul 21 07:02:38 PM PDT 24
Peak memory 216884 kb
Host smart-40ca743e-36d8-4ad3-922c-8b27b3a6e6c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998186723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1998186723
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.352228926
Short name T154
Test name
Test status
Simulation time 370611006 ps
CPU time 2.96 seconds
Started Jul 21 07:02:30 PM PDT 24
Finished Jul 21 07:02:34 PM PDT 24
Peak memory 217736 kb
Host smart-43f03da9-125f-4e44-812b-5261f48fdbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352228926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.352228926
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1806602286
Short name T795
Test name
Test status
Simulation time 281310917 ps
CPU time 11.99 seconds
Started Jul 21 07:02:28 PM PDT 24
Finished Jul 21 07:02:41 PM PDT 24
Peak memory 218464 kb
Host smart-585e4fd0-a5b1-49e0-9e49-61b0d1101e6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806602286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1806602286
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1427418042
Short name T726
Test name
Test status
Simulation time 468067893 ps
CPU time 12.49 seconds
Started Jul 21 07:02:36 PM PDT 24
Finished Jul 21 07:02:49 PM PDT 24
Peak memory 217872 kb
Host smart-b663fad8-ef7f-4682-8ca8-4c3c2c3f2882
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427418042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1427418042
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2656214252
Short name T410
Test name
Test status
Simulation time 589711947 ps
CPU time 8.79 seconds
Started Jul 21 07:02:41 PM PDT 24
Finished Jul 21 07:02:51 PM PDT 24
Peak memory 225536 kb
Host smart-75f313ac-067b-4b13-bfac-a238241dceb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656214252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2656214252
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2141797063
Short name T474
Test name
Test status
Simulation time 440450943 ps
CPU time 11.33 seconds
Started Jul 21 07:02:47 PM PDT 24
Finished Jul 21 07:02:58 PM PDT 24
Peak memory 217884 kb
Host smart-b22c4e54-bde9-4222-b1c4-1818b2e6f7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141797063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2141797063
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2559264821
Short name T848
Test name
Test status
Simulation time 100449563 ps
CPU time 1.82 seconds
Started Jul 21 07:02:40 PM PDT 24
Finished Jul 21 07:02:42 PM PDT 24
Peak memory 222720 kb
Host smart-d66241ad-ac4d-415a-b46e-858d78ea408b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559264821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2559264821
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2984903824
Short name T724
Test name
Test status
Simulation time 1473482728 ps
CPU time 32.15 seconds
Started Jul 21 07:02:34 PM PDT 24
Finished Jul 21 07:03:07 PM PDT 24
Peak memory 250452 kb
Host smart-2948ad9c-d1f2-4f12-b44e-b92ea2a4f345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984903824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2984903824
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3626296740
Short name T462
Test name
Test status
Simulation time 328824572 ps
CPU time 5.97 seconds
Started Jul 21 07:02:41 PM PDT 24
Finished Jul 21 07:02:48 PM PDT 24
Peak memory 217808 kb
Host smart-f9b69c2d-b605-4fd4-bbf0-1c0187f32d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626296740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3626296740
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1831226798
Short name T814
Test name
Test status
Simulation time 41351646144 ps
CPU time 327.03 seconds
Started Jul 21 07:02:38 PM PDT 24
Finished Jul 21 07:08:06 PM PDT 24
Peak memory 250676 kb
Host smart-5ce391bf-15d5-46cb-a765-ff6b87a4dde3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831226798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1831226798
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1657537153
Short name T30
Test name
Test status
Simulation time 27705915 ps
CPU time 0.97 seconds
Started Jul 21 07:02:36 PM PDT 24
Finished Jul 21 07:02:38 PM PDT 24
Peak memory 211368 kb
Host smart-aa40c9f5-31c3-4488-8c1c-5a3d8958fe39
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657537153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1657537153
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.803159114
Short name T808
Test name
Test status
Simulation time 73202879 ps
CPU time 0.86 seconds
Started Jul 21 07:01:38 PM PDT 24
Finished Jul 21 07:01:39 PM PDT 24
Peak memory 208344 kb
Host smart-c92666ed-04e1-4fdd-87a1-9cdbdbe9fda8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803159114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.803159114
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3841525548
Short name T406
Test name
Test status
Simulation time 12046038 ps
CPU time 0.78 seconds
Started Jul 21 07:01:33 PM PDT 24
Finished Jul 21 07:01:34 PM PDT 24
Peak memory 208112 kb
Host smart-40891aad-8312-482a-a092-f7d56b715d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841525548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3841525548
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.663875111
Short name T307
Test name
Test status
Simulation time 1037774987 ps
CPU time 12.06 seconds
Started Jul 21 07:01:25 PM PDT 24
Finished Jul 21 07:01:37 PM PDT 24
Peak memory 217884 kb
Host smart-2f81d39e-5ed5-4300-9090-501c8e9c8593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663875111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.663875111
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.229998208
Short name T478
Test name
Test status
Simulation time 146434533 ps
CPU time 1.69 seconds
Started Jul 21 07:01:30 PM PDT 24
Finished Jul 21 07:01:32 PM PDT 24
Peak memory 216668 kb
Host smart-480b0f8e-ad8e-4ac5-81b3-1d7a7cb9f5ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229998208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.229998208
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.4016340419
Short name T592
Test name
Test status
Simulation time 11032012167 ps
CPU time 31.51 seconds
Started Jul 21 07:01:35 PM PDT 24
Finished Jul 21 07:02:07 PM PDT 24
Peak memory 218460 kb
Host smart-a762e6c8-3526-4737-8061-73cc3dcdc40d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016340419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.4016340419
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1454953125
Short name T265
Test name
Test status
Simulation time 563681833 ps
CPU time 1.96 seconds
Started Jul 21 07:01:19 PM PDT 24
Finished Jul 21 07:01:21 PM PDT 24
Peak memory 217364 kb
Host smart-b1975cab-d93e-4008-a270-c27b3f58ca1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454953125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1
454953125
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2244159543
Short name T252
Test name
Test status
Simulation time 7224266288 ps
CPU time 9.25 seconds
Started Jul 21 07:01:25 PM PDT 24
Finished Jul 21 07:01:35 PM PDT 24
Peak memory 224316 kb
Host smart-57b1eced-b127-4a97-a5f3-e36f2986eb73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244159543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2244159543
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1346176462
Short name T745
Test name
Test status
Simulation time 1078011193 ps
CPU time 15.72 seconds
Started Jul 21 07:01:31 PM PDT 24
Finished Jul 21 07:01:47 PM PDT 24
Peak memory 217304 kb
Host smart-00977bb2-779b-40d3-8e70-f12520c687d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346176462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1346176462
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.578503205
Short name T626
Test name
Test status
Simulation time 279584742 ps
CPU time 5.39 seconds
Started Jul 21 07:01:31 PM PDT 24
Finished Jul 21 07:01:37 PM PDT 24
Peak memory 217032 kb
Host smart-da41fef8-ca57-4e51-923c-a478ec7ba383
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578503205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.578503205
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1973862793
Short name T353
Test name
Test status
Simulation time 5224376045 ps
CPU time 45 seconds
Started Jul 21 07:01:25 PM PDT 24
Finished Jul 21 07:02:11 PM PDT 24
Peak memory 250512 kb
Host smart-8af37dcb-1506-48f9-8672-38806d901444
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973862793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1973862793
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.880830667
Short name T424
Test name
Test status
Simulation time 1297757649 ps
CPU time 9.48 seconds
Started Jul 21 07:01:23 PM PDT 24
Finished Jul 21 07:01:33 PM PDT 24
Peak memory 245292 kb
Host smart-6d9baf64-d023-4f0a-b290-92e2bb818873
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880830667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.880830667
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3151562934
Short name T355
Test name
Test status
Simulation time 37159527 ps
CPU time 2.19 seconds
Started Jul 21 07:01:33 PM PDT 24
Finished Jul 21 07:01:36 PM PDT 24
Peak memory 217760 kb
Host smart-b37152a6-0a6f-441f-8605-eba19f5e9269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151562934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3151562934
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2504797036
Short name T63
Test name
Test status
Simulation time 324956019 ps
CPU time 11.58 seconds
Started Jul 21 07:01:43 PM PDT 24
Finished Jul 21 07:01:55 PM PDT 24
Peak memory 214268 kb
Host smart-70b03380-b82b-4186-ada7-27487bf60a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504797036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2504797036
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1062017527
Short name T682
Test name
Test status
Simulation time 444515611 ps
CPU time 12.37 seconds
Started Jul 21 07:01:24 PM PDT 24
Finished Jul 21 07:01:37 PM PDT 24
Peak memory 217740 kb
Host smart-cf6decd7-92e9-4a05-8a35-eab8553832e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062017527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1062017527
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2200877429
Short name T377
Test name
Test status
Simulation time 854182530 ps
CPU time 7.53 seconds
Started Jul 21 07:01:32 PM PDT 24
Finished Jul 21 07:01:40 PM PDT 24
Peak memory 224636 kb
Host smart-e28a07ae-273e-46c0-8e37-ae58f03cab96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200877429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
200877429
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.676350849
Short name T327
Test name
Test status
Simulation time 314778934 ps
CPU time 7.78 seconds
Started Jul 21 07:01:26 PM PDT 24
Finished Jul 21 07:01:34 PM PDT 24
Peak memory 224084 kb
Host smart-6186b14e-5510-4545-9dfd-d0955f659cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676350849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.676350849
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3787393155
Short name T426
Test name
Test status
Simulation time 301630876 ps
CPU time 3.53 seconds
Started Jul 21 07:01:18 PM PDT 24
Finished Jul 21 07:01:22 PM PDT 24
Peak memory 217232 kb
Host smart-168af608-a9e9-41fb-88a6-7b13ff056998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787393155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3787393155
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2406890216
Short name T835
Test name
Test status
Simulation time 687280625 ps
CPU time 29.15 seconds
Started Jul 21 07:01:25 PM PDT 24
Finished Jul 21 07:01:55 PM PDT 24
Peak memory 250504 kb
Host smart-546ed246-f331-4833-9c7d-d18d1451f656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406890216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2406890216
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1511406767
Short name T321
Test name
Test status
Simulation time 334943721 ps
CPU time 8.61 seconds
Started Jul 21 07:01:18 PM PDT 24
Finished Jul 21 07:01:27 PM PDT 24
Peak memory 246784 kb
Host smart-b8d9268c-b0ce-46ec-950f-ffcdf29298f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511406767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1511406767
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3065480026
Short name T364
Test name
Test status
Simulation time 7357599996 ps
CPU time 163.58 seconds
Started Jul 21 07:01:28 PM PDT 24
Finished Jul 21 07:04:12 PM PDT 24
Peak memory 283508 kb
Host smart-dc1bc32d-485f-46f7-984f-921d7e22df25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065480026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3065480026
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.4250636094
Short name T786
Test name
Test status
Simulation time 25049756 ps
CPU time 0.91 seconds
Started Jul 21 07:01:24 PM PDT 24
Finished Jul 21 07:01:26 PM PDT 24
Peak memory 208636 kb
Host smart-5e22665b-27ed-4333-b1d5-8d249a87968a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250636094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.4250636094
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2913368909
Short name T686
Test name
Test status
Simulation time 60822933 ps
CPU time 0.92 seconds
Started Jul 21 07:02:40 PM PDT 24
Finished Jul 21 07:02:41 PM PDT 24
Peak memory 208204 kb
Host smart-7c736d78-20bf-4c24-9f4e-110231c1a991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913368909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2913368909
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.820165736
Short name T533
Test name
Test status
Simulation time 766123132 ps
CPU time 9.45 seconds
Started Jul 21 07:02:40 PM PDT 24
Finished Jul 21 07:02:50 PM PDT 24
Peak memory 217752 kb
Host smart-b2d125d3-30d3-4ed3-af26-dbfd2072cbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820165736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.820165736
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.322669997
Short name T556
Test name
Test status
Simulation time 1298523307 ps
CPU time 11.93 seconds
Started Jul 21 07:02:43 PM PDT 24
Finished Jul 21 07:02:56 PM PDT 24
Peak memory 216800 kb
Host smart-8ba79ba7-ab31-4074-8538-58fdaffd26bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322669997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.322669997
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.827255054
Short name T415
Test name
Test status
Simulation time 200743826 ps
CPU time 3.29 seconds
Started Jul 21 07:02:42 PM PDT 24
Finished Jul 21 07:02:46 PM PDT 24
Peak memory 217828 kb
Host smart-9fb8e91b-3d93-47ea-85b8-4c653d014e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827255054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.827255054
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1050710344
Short name T619
Test name
Test status
Simulation time 460248109 ps
CPU time 12.99 seconds
Started Jul 21 07:02:42 PM PDT 24
Finished Jul 21 07:02:56 PM PDT 24
Peak memory 217916 kb
Host smart-d452f807-4b35-4ab6-94a5-e8edf6205268
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050710344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1050710344
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3360080406
Short name T459
Test name
Test status
Simulation time 626077305 ps
CPU time 10.79 seconds
Started Jul 21 07:02:45 PM PDT 24
Finished Jul 21 07:02:56 PM PDT 24
Peak memory 224452 kb
Host smart-3d9e565d-9ee1-4c62-a0be-3f581d1331e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360080406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3360080406
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.99788501
Short name T54
Test name
Test status
Simulation time 226493444 ps
CPU time 6.07 seconds
Started Jul 21 07:02:38 PM PDT 24
Finished Jul 21 07:02:45 PM PDT 24
Peak memory 224336 kb
Host smart-43c7cb03-808f-47ec-9f19-58bed281b2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99788501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.99788501
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.137104036
Short name T783
Test name
Test status
Simulation time 367953186 ps
CPU time 4.98 seconds
Started Jul 21 07:02:40 PM PDT 24
Finished Jul 21 07:02:46 PM PDT 24
Peak memory 217176 kb
Host smart-4f01b26f-01a4-41ac-9d29-796b7eb21413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137104036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.137104036
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.609400906
Short name T402
Test name
Test status
Simulation time 551215392 ps
CPU time 28.97 seconds
Started Jul 21 07:02:36 PM PDT 24
Finished Jul 21 07:03:06 PM PDT 24
Peak memory 250572 kb
Host smart-8aa3c24a-7a5a-4048-8e36-9aa14cc8e09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609400906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.609400906
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.4034824458
Short name T852
Test name
Test status
Simulation time 125352406 ps
CPU time 6.74 seconds
Started Jul 21 07:02:41 PM PDT 24
Finished Jul 21 07:02:48 PM PDT 24
Peak memory 250128 kb
Host smart-628cd677-2f44-4407-b7ac-464e75848a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034824458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.4034824458
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2270759758
Short name T631
Test name
Test status
Simulation time 3119314903 ps
CPU time 17.84 seconds
Started Jul 21 07:02:39 PM PDT 24
Finished Jul 21 07:02:58 PM PDT 24
Peak memory 250600 kb
Host smart-ed8ca650-eb2c-41ae-9d86-df8545bdd507
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270759758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2270759758
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3600677035
Short name T343
Test name
Test status
Simulation time 18779713 ps
CPU time 1.13 seconds
Started Jul 21 07:02:26 PM PDT 24
Finished Jul 21 07:02:28 PM PDT 24
Peak memory 211464 kb
Host smart-f9fee49e-bf66-498b-80ee-a723fd5adc6a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600677035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3600677035
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.573128994
Short name T574
Test name
Test status
Simulation time 96228722 ps
CPU time 1.2 seconds
Started Jul 21 07:02:37 PM PDT 24
Finished Jul 21 07:02:39 PM PDT 24
Peak memory 208500 kb
Host smart-0bbc166a-7c58-4a99-9238-1c2b40f6af3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573128994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.573128994
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3851571402
Short name T492
Test name
Test status
Simulation time 846322955 ps
CPU time 17.01 seconds
Started Jul 21 07:02:46 PM PDT 24
Finished Jul 21 07:03:03 PM PDT 24
Peak memory 225608 kb
Host smart-35b6b717-d22b-4323-876e-3c60e8c99018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851571402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3851571402
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.495811067
Short name T772
Test name
Test status
Simulation time 846424822 ps
CPU time 11.46 seconds
Started Jul 21 07:02:40 PM PDT 24
Finished Jul 21 07:02:52 PM PDT 24
Peak memory 217004 kb
Host smart-f3c78f28-59ff-47b4-bc8e-cfe1d9fabda1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495811067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.495811067
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3431895551
Short name T362
Test name
Test status
Simulation time 34375346 ps
CPU time 2.38 seconds
Started Jul 21 07:02:43 PM PDT 24
Finished Jul 21 07:02:46 PM PDT 24
Peak memory 217812 kb
Host smart-f0808892-23b0-456c-a151-3fdc70854126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431895551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3431895551
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2235178901
Short name T764
Test name
Test status
Simulation time 956628556 ps
CPU time 11.11 seconds
Started Jul 21 07:02:41 PM PDT 24
Finished Jul 21 07:02:54 PM PDT 24
Peak memory 217860 kb
Host smart-b919e490-085a-4517-83cd-1f3311f0829b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235178901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2235178901
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.235915175
Short name T673
Test name
Test status
Simulation time 1220995246 ps
CPU time 8.63 seconds
Started Jul 21 07:02:42 PM PDT 24
Finished Jul 21 07:02:52 PM PDT 24
Peak memory 225508 kb
Host smart-40962aeb-3e43-412e-9d71-8745a157887f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235915175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.235915175
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2185573021
Short name T737
Test name
Test status
Simulation time 233604591 ps
CPU time 7.79 seconds
Started Jul 21 07:02:42 PM PDT 24
Finished Jul 21 07:02:51 PM PDT 24
Peak memory 217896 kb
Host smart-7a98f2d1-2b5b-4df6-b20d-00e4e42ae5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185573021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2185573021
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3875439439
Short name T815
Test name
Test status
Simulation time 422471115 ps
CPU time 3.11 seconds
Started Jul 21 07:02:43 PM PDT 24
Finished Jul 21 07:02:48 PM PDT 24
Peak memory 214364 kb
Host smart-35e860bf-1ca9-402f-8687-07558059cd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875439439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3875439439
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3177581949
Short name T722
Test name
Test status
Simulation time 621015408 ps
CPU time 31.93 seconds
Started Jul 21 07:02:38 PM PDT 24
Finished Jul 21 07:03:11 PM PDT 24
Peak memory 250480 kb
Host smart-e9446967-f9b6-45be-bd42-e8844f707b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177581949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3177581949
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1583752086
Short name T707
Test name
Test status
Simulation time 52799102 ps
CPU time 5.45 seconds
Started Jul 21 07:02:38 PM PDT 24
Finished Jul 21 07:02:44 PM PDT 24
Peak memory 246324 kb
Host smart-c37a358f-d19b-43dd-8cc1-4d4e0f1034a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583752086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1583752086
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.4223736963
Short name T543
Test name
Test status
Simulation time 26801907923 ps
CPU time 272.24 seconds
Started Jul 21 07:02:39 PM PDT 24
Finished Jul 21 07:07:12 PM PDT 24
Peak memory 250224 kb
Host smart-e9c6f668-ee36-4902-8fb2-1c46ed83368b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223736963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.4223736963
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.2704931868
Short name T158
Test name
Test status
Simulation time 92762784365 ps
CPU time 823.5 seconds
Started Jul 21 07:02:37 PM PDT 24
Finished Jul 21 07:16:21 PM PDT 24
Peak memory 447308 kb
Host smart-495f1115-7892-4594-be55-6846c2d02654
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2704931868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.2704931868
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3980956219
Short name T667
Test name
Test status
Simulation time 14118938 ps
CPU time 1 seconds
Started Jul 21 07:02:44 PM PDT 24
Finished Jul 21 07:02:46 PM PDT 24
Peak memory 211344 kb
Host smart-5196b5db-abcf-4726-beab-6acc0ba9e714
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980956219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3980956219
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1712356786
Short name T811
Test name
Test status
Simulation time 20905658 ps
CPU time 0.94 seconds
Started Jul 21 07:02:37 PM PDT 24
Finished Jul 21 07:02:38 PM PDT 24
Peak memory 208324 kb
Host smart-a54a3060-1f7d-4342-a1b7-f00a8d3187f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712356786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1712356786
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.121316156
Short name T716
Test name
Test status
Simulation time 1841030739 ps
CPU time 18.98 seconds
Started Jul 21 07:02:41 PM PDT 24
Finished Jul 21 07:03:00 PM PDT 24
Peak memory 217908 kb
Host smart-d977f7f0-71d9-43d9-a714-aff78ed672c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121316156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.121316156
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.188726620
Short name T257
Test name
Test status
Simulation time 656459356 ps
CPU time 1.19 seconds
Started Jul 21 07:02:44 PM PDT 24
Finished Jul 21 07:02:46 PM PDT 24
Peak memory 216580 kb
Host smart-2923567a-bb99-46f0-b26b-365d4b909be1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188726620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.188726620
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.2787663709
Short name T260
Test name
Test status
Simulation time 115538040 ps
CPU time 3.32 seconds
Started Jul 21 07:02:38 PM PDT 24
Finished Jul 21 07:02:42 PM PDT 24
Peak memory 217744 kb
Host smart-2e51278c-bdc6-4689-b8ef-1f866edd1a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787663709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2787663709
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3652192391
Short name T674
Test name
Test status
Simulation time 1363610599 ps
CPU time 10.63 seconds
Started Jul 21 07:02:41 PM PDT 24
Finished Jul 21 07:02:53 PM PDT 24
Peak memory 217928 kb
Host smart-f6441123-ac7b-4d62-8aa1-d9b9508c9991
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652192391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3652192391
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.4287171472
Short name T273
Test name
Test status
Simulation time 3146002504 ps
CPU time 15.67 seconds
Started Jul 21 07:02:28 PM PDT 24
Finished Jul 21 07:02:45 PM PDT 24
Peak memory 217784 kb
Host smart-beb0184c-121e-4edf-a21e-c70443481511
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287171472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.4287171472
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.4259541833
Short name T246
Test name
Test status
Simulation time 304743183 ps
CPU time 8.52 seconds
Started Jul 21 07:02:40 PM PDT 24
Finished Jul 21 07:02:49 PM PDT 24
Peak memory 225468 kb
Host smart-d83c9fa7-cfe5-4384-a75a-fadc6ead5de0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259541833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
4259541833
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.62481680
Short name T62
Test name
Test status
Simulation time 120311095 ps
CPU time 2.23 seconds
Started Jul 21 07:02:41 PM PDT 24
Finished Jul 21 07:02:44 PM PDT 24
Peak memory 217244 kb
Host smart-6ddee70a-4c08-4963-a2d9-d1958568dd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62481680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.62481680
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2009824639
Short name T776
Test name
Test status
Simulation time 190683060 ps
CPU time 26.06 seconds
Started Jul 21 07:02:38 PM PDT 24
Finished Jul 21 07:03:05 PM PDT 24
Peak memory 250556 kb
Host smart-6c694bab-665e-4183-bc5e-b94b4b80f437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009824639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2009824639
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.2434431371
Short name T92
Test name
Test status
Simulation time 235727655 ps
CPU time 2.99 seconds
Started Jul 21 07:02:43 PM PDT 24
Finished Jul 21 07:02:47 PM PDT 24
Peak memory 225988 kb
Host smart-f6048112-4c6d-4d04-9a25-e1641e1a8576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434431371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2434431371
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2140014493
Short name T43
Test name
Test status
Simulation time 3946776632 ps
CPU time 40.35 seconds
Started Jul 21 07:02:39 PM PDT 24
Finished Jul 21 07:03:20 PM PDT 24
Peak memory 241800 kb
Host smart-e49a5137-9803-42fd-adab-aa1c2914e66b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140014493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2140014493
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3371567561
Short name T676
Test name
Test status
Simulation time 24791753 ps
CPU time 0.98 seconds
Started Jul 21 07:02:42 PM PDT 24
Finished Jul 21 07:02:44 PM PDT 24
Peak memory 211380 kb
Host smart-58be7d75-76cb-4b19-bf6d-4983cad85f87
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371567561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3371567561
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3580103466
Short name T771
Test name
Test status
Simulation time 64067157 ps
CPU time 0.86 seconds
Started Jul 21 07:02:59 PM PDT 24
Finished Jul 21 07:03:01 PM PDT 24
Peak memory 208340 kb
Host smart-138843f6-82cb-44ba-87b7-356d87257a8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580103466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3580103466
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2459744121
Short name T497
Test name
Test status
Simulation time 1091945983 ps
CPU time 12.76 seconds
Started Jul 21 07:02:42 PM PDT 24
Finished Jul 21 07:02:56 PM PDT 24
Peak memory 217868 kb
Host smart-c68ce192-9bd5-46dc-bcfd-b0d06952679d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459744121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2459744121
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3499416882
Short name T25
Test name
Test status
Simulation time 1661571979 ps
CPU time 3.62 seconds
Started Jul 21 07:02:51 PM PDT 24
Finished Jul 21 07:02:55 PM PDT 24
Peak memory 216752 kb
Host smart-f4eeb52c-631b-4fa1-a9d9-9fa546237cea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499416882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3499416882
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.441983664
Short name T439
Test name
Test status
Simulation time 307588785 ps
CPU time 2.96 seconds
Started Jul 21 07:02:42 PM PDT 24
Finished Jul 21 07:02:46 PM PDT 24
Peak memory 221884 kb
Host smart-9b68dcd8-2754-4fa9-9e42-4ca0a9b9e574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441983664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.441983664
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.33837939
Short name T612
Test name
Test status
Simulation time 461860851 ps
CPU time 14.43 seconds
Started Jul 21 07:02:41 PM PDT 24
Finished Jul 21 07:02:57 PM PDT 24
Peak memory 218460 kb
Host smart-b8340cc9-0aa8-4858-850b-5aa5f05c2417
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33837939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.33837939
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2825022265
Short name T229
Test name
Test status
Simulation time 720437808 ps
CPU time 16.94 seconds
Started Jul 21 07:02:51 PM PDT 24
Finished Jul 21 07:03:08 PM PDT 24
Peak memory 217788 kb
Host smart-b7b8a394-b7e4-49b6-898e-1cc09f6083b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825022265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2825022265
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2882451068
Short name T293
Test name
Test status
Simulation time 1015191947 ps
CPU time 9.53 seconds
Started Jul 21 07:02:43 PM PDT 24
Finished Jul 21 07:02:54 PM PDT 24
Peak memory 225552 kb
Host smart-f00c5ebd-44b5-4ae4-9916-b8cbecff1338
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882451068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2882451068
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.258205741
Short name T213
Test name
Test status
Simulation time 3088546106 ps
CPU time 13.38 seconds
Started Jul 21 07:02:48 PM PDT 24
Finished Jul 21 07:03:02 PM PDT 24
Peak memory 217956 kb
Host smart-00821552-55b8-4b83-8ca8-9673494350ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258205741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.258205741
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.32973823
Short name T83
Test name
Test status
Simulation time 480071240 ps
CPU time 2.82 seconds
Started Jul 21 07:02:46 PM PDT 24
Finished Jul 21 07:02:49 PM PDT 24
Peak memory 214256 kb
Host smart-d8130532-e23c-448a-8935-18cdbc315fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32973823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.32973823
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2485572322
Short name T668
Test name
Test status
Simulation time 1132977180 ps
CPU time 20.01 seconds
Started Jul 21 07:02:50 PM PDT 24
Finished Jul 21 07:03:11 PM PDT 24
Peak memory 250536 kb
Host smart-3896d873-cf73-45ac-bf64-deff2d3b3d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485572322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2485572322
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3016476368
Short name T746
Test name
Test status
Simulation time 409114578 ps
CPU time 7.99 seconds
Started Jul 21 07:02:41 PM PDT 24
Finished Jul 21 07:02:51 PM PDT 24
Peak memory 242364 kb
Host smart-2051a7d0-218e-403c-abf8-2155f00a47b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016476368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3016476368
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1635007985
Short name T313
Test name
Test status
Simulation time 2898168998 ps
CPU time 23.12 seconds
Started Jul 21 07:02:42 PM PDT 24
Finished Jul 21 07:03:06 PM PDT 24
Peak memory 250548 kb
Host smart-654e5bc0-7abb-4f82-9f94-c111f23c53f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635007985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1635007985
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.3337723933
Short name T149
Test name
Test status
Simulation time 80529576047 ps
CPU time 744.99 seconds
Started Jul 21 07:02:47 PM PDT 24
Finished Jul 21 07:15:13 PM PDT 24
Peak memory 283376 kb
Host smart-f91af8a6-bdd8-4701-9361-365d65e84812
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3337723933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.3337723933
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.4261068624
Short name T388
Test name
Test status
Simulation time 49328967 ps
CPU time 1.06 seconds
Started Jul 21 07:02:40 PM PDT 24
Finished Jul 21 07:02:42 PM PDT 24
Peak memory 211388 kb
Host smart-acf2256c-bc0c-4f35-be99-e843ad808be6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261068624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.4261068624
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1941017325
Short name T562
Test name
Test status
Simulation time 38177550 ps
CPU time 0.86 seconds
Started Jul 21 07:02:45 PM PDT 24
Finished Jul 21 07:02:47 PM PDT 24
Peak memory 208252 kb
Host smart-a606674c-7e92-4ac7-8ff0-4110e155f281
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941017325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1941017325
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.3617974611
Short name T755
Test name
Test status
Simulation time 416200893 ps
CPU time 17.75 seconds
Started Jul 21 07:02:46 PM PDT 24
Finished Jul 21 07:03:04 PM PDT 24
Peak memory 217756 kb
Host smart-2cc993b2-db77-4061-be53-061a75bd2696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617974611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3617974611
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.53468646
Short name T473
Test name
Test status
Simulation time 805086639 ps
CPU time 11.96 seconds
Started Jul 21 07:02:42 PM PDT 24
Finished Jul 21 07:02:55 PM PDT 24
Peak memory 217172 kb
Host smart-5e3ba4f0-320c-49e4-972b-0ce37bf3e062
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53468646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.53468646
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.126934909
Short name T516
Test name
Test status
Simulation time 34044467 ps
CPU time 2.12 seconds
Started Jul 21 07:02:45 PM PDT 24
Finished Jul 21 07:02:48 PM PDT 24
Peak memory 217812 kb
Host smart-57925d5b-7c1a-4a6c-8f64-672d0e135fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126934909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.126934909
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.866319261
Short name T550
Test name
Test status
Simulation time 2407756603 ps
CPU time 16.53 seconds
Started Jul 21 07:02:41 PM PDT 24
Finished Jul 21 07:02:59 PM PDT 24
Peak memory 218752 kb
Host smart-503d9d69-b796-436a-9fa2-c1a6191865c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866319261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.866319261
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3462325445
Short name T32
Test name
Test status
Simulation time 2117406850 ps
CPU time 14.35 seconds
Started Jul 21 07:02:43 PM PDT 24
Finished Jul 21 07:02:59 PM PDT 24
Peak memory 217812 kb
Host smart-d95af15c-720a-4245-86f2-742fad4a3604
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462325445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3462325445
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.401240155
Short name T291
Test name
Test status
Simulation time 847462930 ps
CPU time 6.3 seconds
Started Jul 21 07:02:50 PM PDT 24
Finished Jul 21 07:02:56 PM PDT 24
Peak memory 225004 kb
Host smart-5f5a03bd-d79a-445f-a6fb-fe9ab11c5c50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401240155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.401240155
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.4048362418
Short name T363
Test name
Test status
Simulation time 509888589 ps
CPU time 7.25 seconds
Started Jul 21 07:02:43 PM PDT 24
Finished Jul 21 07:02:51 PM PDT 24
Peak memory 217876 kb
Host smart-a7a2b4b7-bec7-4009-83ae-a75b0c467aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048362418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.4048362418
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.775439820
Short name T449
Test name
Test status
Simulation time 183051022 ps
CPU time 2.4 seconds
Started Jul 21 07:02:43 PM PDT 24
Finished Jul 21 07:02:47 PM PDT 24
Peak memory 217212 kb
Host smart-22a05824-70e2-4de6-a487-e731a92fd1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775439820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.775439820
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1022765642
Short name T765
Test name
Test status
Simulation time 189887662 ps
CPU time 25.07 seconds
Started Jul 21 07:02:44 PM PDT 24
Finished Jul 21 07:03:10 PM PDT 24
Peak memory 250536 kb
Host smart-58e597be-9e13-4609-94f4-d33afa41f458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022765642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1022765642
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.12206243
Short name T528
Test name
Test status
Simulation time 62857970 ps
CPU time 7.32 seconds
Started Jul 21 07:02:58 PM PDT 24
Finished Jul 21 07:03:07 PM PDT 24
Peak memory 250504 kb
Host smart-a827525e-1c9e-442f-a482-9ba591aca33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12206243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.12206243
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2122968905
Short name T621
Test name
Test status
Simulation time 58113992167 ps
CPU time 190.16 seconds
Started Jul 21 07:02:46 PM PDT 24
Finished Jul 21 07:05:57 PM PDT 24
Peak memory 267012 kb
Host smart-e82a5a20-3022-4672-98be-312e06f067a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122968905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2122968905
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.4240649741
Short name T206
Test name
Test status
Simulation time 30300992361 ps
CPU time 297.89 seconds
Started Jul 21 07:02:40 PM PDT 24
Finished Jul 21 07:07:38 PM PDT 24
Peak memory 333516 kb
Host smart-558a39f2-27ec-48dc-b000-8067a56c3f4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4240649741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.4240649741
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2588490082
Short name T435
Test name
Test status
Simulation time 15344403 ps
CPU time 1.01 seconds
Started Jul 21 07:02:46 PM PDT 24
Finished Jul 21 07:02:48 PM PDT 24
Peak memory 211384 kb
Host smart-13dc09ce-d8f4-4469-b665-b70c6df6fd1f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588490082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2588490082
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1261364376
Short name T675
Test name
Test status
Simulation time 21801023 ps
CPU time 1.28 seconds
Started Jul 21 07:02:41 PM PDT 24
Finished Jul 21 07:02:43 PM PDT 24
Peak memory 208584 kb
Host smart-05a0c3c6-9199-4d20-a74b-54cbd2b2b9ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261364376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1261364376
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.2385123133
Short name T701
Test name
Test status
Simulation time 489013086 ps
CPU time 11.28 seconds
Started Jul 21 07:02:43 PM PDT 24
Finished Jul 21 07:02:55 PM PDT 24
Peak memory 217820 kb
Host smart-0b0d6c5f-0f16-4d34-9dee-6490500a9ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385123133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2385123133
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3337020377
Short name T585
Test name
Test status
Simulation time 534210998 ps
CPU time 6.34 seconds
Started Jul 21 07:02:41 PM PDT 24
Finished Jul 21 07:02:49 PM PDT 24
Peak memory 216764 kb
Host smart-9d701488-d3c9-4428-9922-fdf1367005fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337020377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3337020377
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.893539191
Short name T275
Test name
Test status
Simulation time 142956176 ps
CPU time 2.14 seconds
Started Jul 21 07:02:44 PM PDT 24
Finished Jul 21 07:02:48 PM PDT 24
Peak memory 221716 kb
Host smart-7a5faf7e-abc8-4b0e-bbb7-9eeabc9a6c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893539191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.893539191
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.4063059693
Short name T818
Test name
Test status
Simulation time 289236775 ps
CPU time 14.15 seconds
Started Jul 21 07:02:39 PM PDT 24
Finished Jul 21 07:02:54 PM PDT 24
Peak memory 217944 kb
Host smart-fd6e64a3-5800-4319-b7b4-87388a8db052
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063059693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.4063059693
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2221129030
Short name T255
Test name
Test status
Simulation time 1686304206 ps
CPU time 10.6 seconds
Started Jul 21 07:02:52 PM PDT 24
Finished Jul 21 07:03:03 PM PDT 24
Peak memory 217756 kb
Host smart-01d3cab1-2cf7-4192-8f7d-e0300ec9dbaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221129030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2221129030
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.553435039
Short name T61
Test name
Test status
Simulation time 360742081 ps
CPU time 13.35 seconds
Started Jul 21 07:02:41 PM PDT 24
Finished Jul 21 07:02:55 PM PDT 24
Peak memory 225528 kb
Host smart-868f716d-6eb5-4a33-9072-d8e49249bce3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553435039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.553435039
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1929539915
Short name T700
Test name
Test status
Simulation time 421340925 ps
CPU time 10.65 seconds
Started Jul 21 07:02:45 PM PDT 24
Finished Jul 21 07:02:56 PM PDT 24
Peak memory 217796 kb
Host smart-7f17a44e-fe21-40fe-8327-d8612e3e5319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929539915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1929539915
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.307778855
Short name T379
Test name
Test status
Simulation time 287174925 ps
CPU time 2.05 seconds
Started Jul 21 07:02:45 PM PDT 24
Finished Jul 21 07:02:48 PM PDT 24
Peak memory 213508 kb
Host smart-1243f876-72ac-4163-9566-a49b704bba77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307778855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.307778855
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.931628429
Short name T813
Test name
Test status
Simulation time 153460414 ps
CPU time 19.23 seconds
Started Jul 21 07:02:52 PM PDT 24
Finished Jul 21 07:03:12 PM PDT 24
Peak memory 250612 kb
Host smart-c84f9355-d29a-4d03-9536-96738ad6ca20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931628429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.931628429
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.860683306
Short name T350
Test name
Test status
Simulation time 211141245 ps
CPU time 6.87 seconds
Started Jul 21 07:02:44 PM PDT 24
Finished Jul 21 07:02:52 PM PDT 24
Peak memory 244132 kb
Host smart-d5ec7c1c-e51e-460f-8e0f-7b334c9c6466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860683306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.860683306
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.547036176
Short name T768
Test name
Test status
Simulation time 3445790959 ps
CPU time 56.87 seconds
Started Jul 21 07:02:43 PM PDT 24
Finished Jul 21 07:03:41 PM PDT 24
Peak memory 250804 kb
Host smart-eff15f30-f581-4050-990d-854916fa32bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547036176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.547036176
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1480294519
Short name T156
Test name
Test status
Simulation time 97505586331 ps
CPU time 2748.16 seconds
Started Jul 21 07:02:40 PM PDT 24
Finished Jul 21 07:48:29 PM PDT 24
Peak memory 607428 kb
Host smart-bc1e547e-32c5-4451-9b4b-005ae73c8091
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1480294519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1480294519
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3450610437
Short name T522
Test name
Test status
Simulation time 27188837 ps
CPU time 0.9 seconds
Started Jul 21 07:02:41 PM PDT 24
Finished Jul 21 07:02:42 PM PDT 24
Peak memory 211392 kb
Host smart-9b61af62-eb59-4417-a892-17314468a489
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450610437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3450610437
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.969581974
Short name T610
Test name
Test status
Simulation time 21514974 ps
CPU time 1.29 seconds
Started Jul 21 07:02:51 PM PDT 24
Finished Jul 21 07:02:53 PM PDT 24
Peak memory 208584 kb
Host smart-32e330ad-4d8c-4cbe-a930-90995a8be0a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969581974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.969581974
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.752514008
Short name T345
Test name
Test status
Simulation time 414642304 ps
CPU time 17.48 seconds
Started Jul 21 07:02:54 PM PDT 24
Finished Jul 21 07:03:16 PM PDT 24
Peak memory 217784 kb
Host smart-600cbe26-6f5b-471a-88b7-2b28c7c63934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752514008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.752514008
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2382811903
Short name T803
Test name
Test status
Simulation time 260909468 ps
CPU time 7.25 seconds
Started Jul 21 07:02:58 PM PDT 24
Finished Jul 21 07:03:07 PM PDT 24
Peak memory 216724 kb
Host smart-e3f89932-7e41-4346-9c8b-9d3cf42b0434
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382811903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2382811903
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3538121346
Short name T633
Test name
Test status
Simulation time 90501131 ps
CPU time 3.11 seconds
Started Jul 21 07:02:54 PM PDT 24
Finished Jul 21 07:02:58 PM PDT 24
Peak memory 217820 kb
Host smart-36b96f0c-0b99-4ada-a361-b12fcc2b5b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538121346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3538121346
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.449665534
Short name T266
Test name
Test status
Simulation time 713614589 ps
CPU time 9.89 seconds
Started Jul 21 07:02:56 PM PDT 24
Finished Jul 21 07:03:08 PM PDT 24
Peak memory 225580 kb
Host smart-502d8b5d-c116-4e1e-b451-c248b757ca7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449665534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.449665534
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2051168719
Short name T173
Test name
Test status
Simulation time 5077004237 ps
CPU time 17.17 seconds
Started Jul 21 07:03:00 PM PDT 24
Finished Jul 21 07:03:19 PM PDT 24
Peak memory 217812 kb
Host smart-d83a3c42-4f30-40e7-b3d4-abceab68d143
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051168719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2051168719
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2129190048
Short name T524
Test name
Test status
Simulation time 960285593 ps
CPU time 7.73 seconds
Started Jul 21 07:02:53 PM PDT 24
Finished Jul 21 07:03:02 PM PDT 24
Peak memory 225556 kb
Host smart-76a464dd-00cb-494d-9557-31d8a4db5e0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129190048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2129190048
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1309200535
Short name T52
Test name
Test status
Simulation time 562822033 ps
CPU time 6.58 seconds
Started Jul 21 07:02:58 PM PDT 24
Finished Jul 21 07:03:06 PM PDT 24
Peak memory 217872 kb
Host smart-43007d0a-0fb5-4d81-872e-d965dc1bbd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309200535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1309200535
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1759463932
Short name T832
Test name
Test status
Simulation time 343718257 ps
CPU time 7.82 seconds
Started Jul 21 07:02:48 PM PDT 24
Finished Jul 21 07:02:56 PM PDT 24
Peak memory 217228 kb
Host smart-0ceb2a30-c5d7-4d6a-8f7b-44ef841d25f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759463932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1759463932
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2173542048
Short name T747
Test name
Test status
Simulation time 1038256330 ps
CPU time 19.37 seconds
Started Jul 21 07:02:52 PM PDT 24
Finished Jul 21 07:03:12 PM PDT 24
Peak memory 250624 kb
Host smart-2f792edd-6d11-4bb8-9a89-2f56a15cc158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173542048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2173542048
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.4211908522
Short name T547
Test name
Test status
Simulation time 159705545 ps
CPU time 10.01 seconds
Started Jul 21 07:02:55 PM PDT 24
Finished Jul 21 07:03:05 PM PDT 24
Peak memory 243836 kb
Host smart-0e9f0ea2-b301-4205-a155-2bb3bf115f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211908522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.4211908522
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.3006966248
Short name T346
Test name
Test status
Simulation time 7384349309 ps
CPU time 38.02 seconds
Started Jul 21 07:02:47 PM PDT 24
Finished Jul 21 07:03:25 PM PDT 24
Peak memory 250372 kb
Host smart-d3a3f84d-a3ba-4296-a023-54a0e7adc721
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006966248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.3006966248
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.379836179
Short name T157
Test name
Test status
Simulation time 70079821541 ps
CPU time 651.52 seconds
Started Jul 21 07:02:51 PM PDT 24
Finished Jul 21 07:13:43 PM PDT 24
Peak memory 693140 kb
Host smart-a6a0e3be-9abb-4a45-8c59-f1c64be28795
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=379836179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.379836179
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3402257107
Short name T41
Test name
Test status
Simulation time 14742923 ps
CPU time 0.97 seconds
Started Jul 21 07:03:00 PM PDT 24
Finished Jul 21 07:03:03 PM PDT 24
Peak memory 208480 kb
Host smart-ff7ca8d8-8970-47d1-9396-87d957ed1a4e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402257107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3402257107
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.915052880
Short name T381
Test name
Test status
Simulation time 74342515 ps
CPU time 0.93 seconds
Started Jul 21 07:03:00 PM PDT 24
Finished Jul 21 07:03:03 PM PDT 24
Peak memory 208364 kb
Host smart-fac0d81c-1ed5-4751-b44c-dda2531bccbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915052880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.915052880
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.931086861
Short name T708
Test name
Test status
Simulation time 948242390 ps
CPU time 10.44 seconds
Started Jul 21 07:02:53 PM PDT 24
Finished Jul 21 07:03:05 PM PDT 24
Peak memory 217868 kb
Host smart-c7b86fb6-915e-4cdd-a5cf-ff119f41604c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931086861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.931086861
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.561004649
Short name T807
Test name
Test status
Simulation time 1158875985 ps
CPU time 3.87 seconds
Started Jul 21 07:02:53 PM PDT 24
Finished Jul 21 07:02:57 PM PDT 24
Peak memory 216700 kb
Host smart-d7d95bbd-542e-48a9-8b75-7220e98c6af1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561004649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.561004649
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2972341595
Short name T573
Test name
Test status
Simulation time 312905209 ps
CPU time 2.07 seconds
Started Jul 21 07:02:53 PM PDT 24
Finished Jul 21 07:02:56 PM PDT 24
Peak memory 221696 kb
Host smart-ffb5c986-68a9-422d-a8db-ddf446a640c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972341595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2972341595
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2235432394
Short name T256
Test name
Test status
Simulation time 892553425 ps
CPU time 13.48 seconds
Started Jul 21 07:02:50 PM PDT 24
Finished Jul 21 07:03:04 PM PDT 24
Peak memory 225612 kb
Host smart-5cd84d45-aefd-419b-beec-3934fa84b843
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235432394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2235432394
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2142813451
Short name T487
Test name
Test status
Simulation time 1147529478 ps
CPU time 11.19 seconds
Started Jul 21 07:02:55 PM PDT 24
Finished Jul 21 07:03:07 PM PDT 24
Peak memory 225064 kb
Host smart-cd46cf3a-75d1-4550-807d-b3f7d9334711
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142813451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2142813451
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3427058000
Short name T254
Test name
Test status
Simulation time 356440273 ps
CPU time 9.02 seconds
Started Jul 21 07:02:56 PM PDT 24
Finished Jul 21 07:03:06 PM PDT 24
Peak memory 225600 kb
Host smart-3adc2a25-854d-4c37-99a7-99a27aea4630
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427058000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3427058000
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.635824784
Short name T602
Test name
Test status
Simulation time 1471851566 ps
CPU time 9.79 seconds
Started Jul 21 07:02:53 PM PDT 24
Finished Jul 21 07:03:04 PM PDT 24
Peak memory 225572 kb
Host smart-2822ecb3-5db2-4558-a78c-c52b7ee9f796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635824784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.635824784
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1205703486
Short name T575
Test name
Test status
Simulation time 114624435 ps
CPU time 3.49 seconds
Started Jul 21 07:02:45 PM PDT 24
Finished Jul 21 07:02:49 PM PDT 24
Peak memory 217236 kb
Host smart-867ac829-7e40-43e0-9f79-f7ff9e9e9667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205703486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1205703486
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1169526649
Short name T608
Test name
Test status
Simulation time 3397347790 ps
CPU time 36.46 seconds
Started Jul 21 07:02:54 PM PDT 24
Finished Jul 21 07:03:31 PM PDT 24
Peak memory 250584 kb
Host smart-3d4b50e0-a3e2-48af-805f-d4bd3de40437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169526649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1169526649
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2394724599
Short name T360
Test name
Test status
Simulation time 66721552 ps
CPU time 7.91 seconds
Started Jul 21 07:02:53 PM PDT 24
Finished Jul 21 07:03:02 PM PDT 24
Peak memory 250568 kb
Host smart-5d30d0d1-2a46-4b98-8a9b-bb554f96642d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394724599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2394724599
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.1670650890
Short name T73
Test name
Test status
Simulation time 15051098826 ps
CPU time 176.63 seconds
Started Jul 21 07:02:50 PM PDT 24
Finished Jul 21 07:05:47 PM PDT 24
Peak memory 249028 kb
Host smart-67f3cb38-0855-41ef-bdc3-fef3dcfd40db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670650890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.1670650890
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.705443287
Short name T482
Test name
Test status
Simulation time 50505769 ps
CPU time 0.91 seconds
Started Jul 21 07:02:56 PM PDT 24
Finished Jul 21 07:03:03 PM PDT 24
Peak memory 208460 kb
Host smart-21236811-a628-452f-8e11-c3ff9cf42102
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705443287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.705443287
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2934728144
Short name T182
Test name
Test status
Simulation time 64690210 ps
CPU time 0.92 seconds
Started Jul 21 07:02:51 PM PDT 24
Finished Jul 21 07:02:52 PM PDT 24
Peak memory 208408 kb
Host smart-5935ee5a-7211-4031-b5c2-5b307fb89717
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934728144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2934728144
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.795800700
Short name T582
Test name
Test status
Simulation time 924419132 ps
CPU time 12.82 seconds
Started Jul 21 07:02:50 PM PDT 24
Finished Jul 21 07:03:03 PM PDT 24
Peak memory 217700 kb
Host smart-547e5578-f022-49c2-b0e3-713b3e1976b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795800700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.795800700
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.773365137
Short name T703
Test name
Test status
Simulation time 1033702882 ps
CPU time 2.83 seconds
Started Jul 21 07:02:55 PM PDT 24
Finished Jul 21 07:02:58 PM PDT 24
Peak memory 217060 kb
Host smart-2d3a6423-ae43-44cc-9ba8-1e06e5ce6859
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773365137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.773365137
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1987552679
Short name T294
Test name
Test status
Simulation time 348045193 ps
CPU time 3.64 seconds
Started Jul 21 07:02:56 PM PDT 24
Finished Jul 21 07:03:01 PM PDT 24
Peak memory 222164 kb
Host smart-f066970c-0585-4859-8b7d-a8097c50f050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987552679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1987552679
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1392926806
Short name T167
Test name
Test status
Simulation time 655707577 ps
CPU time 9.18 seconds
Started Jul 21 07:02:54 PM PDT 24
Finished Jul 21 07:03:04 PM PDT 24
Peak memory 217796 kb
Host smart-59e34cea-e299-4b41-b9ec-abcc36360d4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392926806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1392926806
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3896713105
Short name T382
Test name
Test status
Simulation time 852028971 ps
CPU time 9.91 seconds
Started Jul 21 07:02:56 PM PDT 24
Finished Jul 21 07:03:07 PM PDT 24
Peak memory 225480 kb
Host smart-b68507b1-a7c0-46dc-88b2-3716b9b74ede
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896713105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3896713105
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.291511229
Short name T704
Test name
Test status
Simulation time 364559161 ps
CPU time 12.62 seconds
Started Jul 21 07:03:01 PM PDT 24
Finished Jul 21 07:03:16 PM PDT 24
Peak memory 217840 kb
Host smart-d03c635b-6a5f-4a0b-bbb4-17d6dc0d1123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291511229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.291511229
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3181922078
Short name T248
Test name
Test status
Simulation time 70649558 ps
CPU time 2.49 seconds
Started Jul 21 07:02:44 PM PDT 24
Finished Jul 21 07:02:48 PM PDT 24
Peak memory 217256 kb
Host smart-d258e1b4-96f8-40bc-be8f-9d1cae62c9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181922078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3181922078
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1161677039
Short name T641
Test name
Test status
Simulation time 242711042 ps
CPU time 26.92 seconds
Started Jul 21 07:02:53 PM PDT 24
Finished Jul 21 07:03:20 PM PDT 24
Peak memory 250572 kb
Host smart-05a4e411-db94-48d3-8326-a4d96d48385b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161677039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1161677039
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3761719278
Short name T417
Test name
Test status
Simulation time 220884302 ps
CPU time 8.28 seconds
Started Jul 21 07:02:55 PM PDT 24
Finished Jul 21 07:03:04 PM PDT 24
Peak memory 250492 kb
Host smart-b726f0de-5e0f-4e27-af4f-259449e8707a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761719278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3761719278
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3470506800
Short name T304
Test name
Test status
Simulation time 29452289738 ps
CPU time 216.88 seconds
Started Jul 21 07:02:55 PM PDT 24
Finished Jul 21 07:06:33 PM PDT 24
Peak memory 283496 kb
Host smart-a0b32894-c93f-4b72-a600-ab8a487a0c83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470506800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3470506800
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.4221889498
Short name T812
Test name
Test status
Simulation time 16766771910 ps
CPU time 460.08 seconds
Started Jul 21 07:02:51 PM PDT 24
Finished Jul 21 07:10:31 PM PDT 24
Peak memory 283452 kb
Host smart-cd1c4b98-36e1-41c7-954b-e85a34d4fec0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4221889498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.4221889498
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.591275992
Short name T253
Test name
Test status
Simulation time 15899910 ps
CPU time 0.76 seconds
Started Jul 21 07:02:58 PM PDT 24
Finished Jul 21 07:03:00 PM PDT 24
Peak memory 208256 kb
Host smart-dc64a735-7804-4a38-8b6c-f3f75a39ae5b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591275992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.591275992
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.4265049962
Short name T616
Test name
Test status
Simulation time 23157640 ps
CPU time 1.32 seconds
Started Jul 21 07:02:59 PM PDT 24
Finished Jul 21 07:03:02 PM PDT 24
Peak memory 208536 kb
Host smart-7166107f-f515-4c02-923a-7bcac3109123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265049962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.4265049962
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1322660488
Short name T519
Test name
Test status
Simulation time 261043721 ps
CPU time 8.53 seconds
Started Jul 21 07:02:49 PM PDT 24
Finished Jul 21 07:02:58 PM PDT 24
Peak memory 218072 kb
Host smart-a8a369de-c9ac-4332-b2fd-bf4a7a1448ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322660488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1322660488
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2029248538
Short name T761
Test name
Test status
Simulation time 8349976836 ps
CPU time 20.6 seconds
Started Jul 21 07:02:45 PM PDT 24
Finished Jul 21 07:03:06 PM PDT 24
Peak memory 217232 kb
Host smart-58b3a38a-eb3c-491f-bdd5-8958ac3c10aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029248538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2029248538
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2499904763
Short name T651
Test name
Test status
Simulation time 567424599 ps
CPU time 5.45 seconds
Started Jul 21 07:02:54 PM PDT 24
Finished Jul 21 07:03:00 PM PDT 24
Peak memory 217792 kb
Host smart-5d528bba-d932-4e39-b8a5-5105d9e0559e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499904763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2499904763
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2239209439
Short name T728
Test name
Test status
Simulation time 348767675 ps
CPU time 13.32 seconds
Started Jul 21 07:02:53 PM PDT 24
Finished Jul 21 07:03:11 PM PDT 24
Peak memory 225608 kb
Host smart-d7283ec3-7d63-430a-935d-78b8c87dd4b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239209439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2239209439
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2113141312
Short name T635
Test name
Test status
Simulation time 351326017 ps
CPU time 12.45 seconds
Started Jul 21 07:02:56 PM PDT 24
Finished Jul 21 07:03:10 PM PDT 24
Peak memory 217768 kb
Host smart-edb2e274-fafa-44e5-8214-5affd1bbbc88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113141312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2113141312
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1723582628
Short name T160
Test name
Test status
Simulation time 1241932723 ps
CPU time 7.67 seconds
Started Jul 21 07:02:55 PM PDT 24
Finished Jul 21 07:03:04 PM PDT 24
Peak memory 224292 kb
Host smart-84dfe0b5-a792-43e7-9463-62d14025bfe6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723582628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1723582628
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2230794233
Short name T214
Test name
Test status
Simulation time 1477555915 ps
CPU time 14.18 seconds
Started Jul 21 07:02:53 PM PDT 24
Finished Jul 21 07:03:08 PM PDT 24
Peak memory 217928 kb
Host smart-c98c6aaa-4aeb-44c4-824c-44c947f02b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230794233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2230794233
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2585953491
Short name T687
Test name
Test status
Simulation time 177951710 ps
CPU time 1.96 seconds
Started Jul 21 07:02:50 PM PDT 24
Finished Jul 21 07:02:52 PM PDT 24
Peak memory 213624 kb
Host smart-14ddfd47-ab55-4fc7-a66e-489c6ac35732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585953491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2585953491
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1095620205
Short name T431
Test name
Test status
Simulation time 808224882 ps
CPU time 15.19 seconds
Started Jul 21 07:03:01 PM PDT 24
Finished Jul 21 07:03:18 PM PDT 24
Peak memory 250580 kb
Host smart-7e342dde-e502-48a9-9111-605067ff91b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095620205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1095620205
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3434973214
Short name T663
Test name
Test status
Simulation time 48368016 ps
CPU time 7.73 seconds
Started Jul 21 07:02:56 PM PDT 24
Finished Jul 21 07:03:05 PM PDT 24
Peak memory 250536 kb
Host smart-b63b05a4-804d-40c1-a07f-7f88009cf883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434973214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3434973214
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2232740041
Short name T107
Test name
Test status
Simulation time 45264565498 ps
CPU time 200.72 seconds
Started Jul 21 07:02:58 PM PDT 24
Finished Jul 21 07:06:21 PM PDT 24
Peak memory 277364 kb
Host smart-ade7e69c-0440-4365-8b35-3bf3e8e37ddc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232740041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2232740041
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1485089325
Short name T769
Test name
Test status
Simulation time 102887752 ps
CPU time 1.23 seconds
Started Jul 21 07:02:47 PM PDT 24
Finished Jul 21 07:02:49 PM PDT 24
Peak memory 217336 kb
Host smart-55b70e58-c61d-40ee-9e03-ed1db59483cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485089325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1485089325
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3160928696
Short name T210
Test name
Test status
Simulation time 54697339 ps
CPU time 0.8 seconds
Started Jul 21 07:01:22 PM PDT 24
Finished Jul 21 07:01:23 PM PDT 24
Peak memory 208532 kb
Host smart-0bc670f3-6a70-45d0-a25a-224063d9b819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160928696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3160928696
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.920784448
Short name T538
Test name
Test status
Simulation time 247839529 ps
CPU time 8.4 seconds
Started Jul 21 07:01:29 PM PDT 24
Finished Jul 21 07:01:38 PM PDT 24
Peak memory 217792 kb
Host smart-be005aa9-db8a-4425-be08-ec826c737973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920784448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.920784448
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1675332070
Short name T20
Test name
Test status
Simulation time 4061043489 ps
CPU time 5.35 seconds
Started Jul 21 07:01:35 PM PDT 24
Finished Jul 21 07:01:41 PM PDT 24
Peak memory 217248 kb
Host smart-db6fcdb4-1df6-495f-9bb9-fdb4175a7828
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675332070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1675332070
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.315109171
Short name T460
Test name
Test status
Simulation time 5931078066 ps
CPU time 29.64 seconds
Started Jul 21 07:01:43 PM PDT 24
Finished Jul 21 07:02:13 PM PDT 24
Peak memory 225684 kb
Host smart-3ad16bc8-7907-43b1-b34b-a0161c2475f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315109171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.315109171
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1073235030
Short name T66
Test name
Test status
Simulation time 357847317 ps
CPU time 2.88 seconds
Started Jul 21 07:01:35 PM PDT 24
Finished Jul 21 07:01:39 PM PDT 24
Peak memory 217284 kb
Host smart-f24b8ac5-3238-4d38-9ed3-e702d4d63718
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073235030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
073235030
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.357151791
Short name T541
Test name
Test status
Simulation time 298508326 ps
CPU time 3.34 seconds
Started Jul 21 07:01:37 PM PDT 24
Finished Jul 21 07:01:41 PM PDT 24
Peak memory 221212 kb
Host smart-bfc580cc-1a5d-4019-9480-b09fde04f341
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357151791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.357151791
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3528252350
Short name T587
Test name
Test status
Simulation time 2833579407 ps
CPU time 10.83 seconds
Started Jul 21 07:01:30 PM PDT 24
Finished Jul 21 07:01:42 PM PDT 24
Peak memory 217212 kb
Host smart-70cbbbd0-274c-4c13-b996-1e177eddb8d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528252350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3528252350
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2109523111
Short name T380
Test name
Test status
Simulation time 440405285 ps
CPU time 6.66 seconds
Started Jul 21 07:01:28 PM PDT 24
Finished Jul 21 07:01:35 PM PDT 24
Peak memory 217192 kb
Host smart-06646caa-511d-48ec-8f3e-b57927ac47d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109523111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2109523111
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3566846955
Short name T217
Test name
Test status
Simulation time 883630772 ps
CPU time 37.74 seconds
Started Jul 21 07:01:31 PM PDT 24
Finished Jul 21 07:02:09 PM PDT 24
Peak memory 250520 kb
Host smart-98d9b8bb-a0f7-470e-b7b1-17223ebad412
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566846955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3566846955
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2429673150
Short name T235
Test name
Test status
Simulation time 15401188441 ps
CPU time 18.53 seconds
Started Jul 21 07:01:35 PM PDT 24
Finished Jul 21 07:01:54 PM PDT 24
Peak memory 250124 kb
Host smart-b89716e5-3b48-439c-9d90-d0b124b4fb36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429673150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2429673150
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1713957903
Short name T841
Test name
Test status
Simulation time 106280950 ps
CPU time 3.59 seconds
Started Jul 21 07:01:42 PM PDT 24
Finished Jul 21 07:01:46 PM PDT 24
Peak memory 221876 kb
Host smart-dbe748a1-3869-4855-976b-414cdf8c572c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713957903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1713957903
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.305276879
Short name T425
Test name
Test status
Simulation time 399794385 ps
CPU time 9.69 seconds
Started Jul 21 07:01:26 PM PDT 24
Finished Jul 21 07:01:36 PM PDT 24
Peak memory 214128 kb
Host smart-2ab8eaa8-0263-4c0b-9fd2-9023acaf9ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305276879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.305276879
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1673868286
Short name T96
Test name
Test status
Simulation time 276565950 ps
CPU time 23.14 seconds
Started Jul 21 07:01:41 PM PDT 24
Finished Jul 21 07:02:05 PM PDT 24
Peak memory 269016 kb
Host smart-52a16ad2-5e49-4e61-9e11-6544129abf0f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673868286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1673868286
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1612214338
Short name T697
Test name
Test status
Simulation time 3704560211 ps
CPU time 24.83 seconds
Started Jul 21 07:01:32 PM PDT 24
Finished Jul 21 07:01:58 PM PDT 24
Peak memory 225664 kb
Host smart-21c39186-f6f4-4396-b5db-3614f940fb53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612214338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1612214338
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1650919227
Short name T386
Test name
Test status
Simulation time 858442912 ps
CPU time 10.12 seconds
Started Jul 21 07:01:36 PM PDT 24
Finished Jul 21 07:01:47 PM PDT 24
Peak memory 217788 kb
Host smart-1ef255f5-3347-4d21-a34b-653211c7996d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650919227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1650919227
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.482870767
Short name T267
Test name
Test status
Simulation time 1143709039 ps
CPU time 9.22 seconds
Started Jul 21 07:01:48 PM PDT 24
Finished Jul 21 07:01:58 PM PDT 24
Peak memory 225532 kb
Host smart-9815e649-bb58-4209-9089-05c4f0b1e88c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482870767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.482870767
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2446152718
Short name T598
Test name
Test status
Simulation time 883926426 ps
CPU time 10.88 seconds
Started Jul 21 07:01:29 PM PDT 24
Finished Jul 21 07:01:41 PM PDT 24
Peak memory 217912 kb
Host smart-e413e67c-d084-4936-8b1c-574fa0a4bbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446152718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2446152718
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1344609970
Short name T736
Test name
Test status
Simulation time 639390845 ps
CPU time 4.33 seconds
Started Jul 21 07:01:20 PM PDT 24
Finished Jul 21 07:01:25 PM PDT 24
Peak memory 217232 kb
Host smart-305151a8-322f-47d8-9fdb-79fdda041547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344609970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1344609970
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.2619724095
Short name T740
Test name
Test status
Simulation time 260327637 ps
CPU time 22.1 seconds
Started Jul 21 07:01:31 PM PDT 24
Finished Jul 21 07:01:53 PM PDT 24
Peak memory 250584 kb
Host smart-c495757e-6f4f-4ad1-98bc-0d1e2d9604b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619724095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2619724095
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2611171175
Short name T37
Test name
Test status
Simulation time 287437072 ps
CPU time 3.19 seconds
Started Jul 21 07:01:29 PM PDT 24
Finished Jul 21 07:01:38 PM PDT 24
Peak memory 222392 kb
Host smart-b2910c85-b017-460d-9efa-34535d59f0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611171175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2611171175
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.4153331693
Short name T750
Test name
Test status
Simulation time 19890398078 ps
CPU time 152.68 seconds
Started Jul 21 07:01:32 PM PDT 24
Finished Jul 21 07:04:05 PM PDT 24
Peak memory 267028 kb
Host smart-07b30e20-154b-4b8b-bf55-0dfb06ba7f06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153331693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.4153331693
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2875583445
Short name T316
Test name
Test status
Simulation time 129822541 ps
CPU time 0.73 seconds
Started Jul 21 07:01:34 PM PDT 24
Finished Jul 21 07:01:36 PM PDT 24
Peak memory 208264 kb
Host smart-c99bbc48-9edc-480a-a18a-f8ebdbbe8eed
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875583445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2875583445
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.4006424055
Short name T13
Test name
Test status
Simulation time 16532776 ps
CPU time 0.84 seconds
Started Jul 21 07:02:59 PM PDT 24
Finished Jul 21 07:03:02 PM PDT 24
Peak memory 208396 kb
Host smart-055d0c01-5ae4-488f-bb43-bf92294f659f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006424055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.4006424055
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.828740339
Short name T282
Test name
Test status
Simulation time 883279714 ps
CPU time 17.47 seconds
Started Jul 21 07:02:59 PM PDT 24
Finished Jul 21 07:03:19 PM PDT 24
Peak memory 217832 kb
Host smart-16c1b91e-9681-4b1c-bf84-37d8d2ddcae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828740339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.828740339
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3254565052
Short name T599
Test name
Test status
Simulation time 225473550 ps
CPU time 3.04 seconds
Started Jul 21 07:02:53 PM PDT 24
Finished Jul 21 07:03:01 PM PDT 24
Peak memory 216756 kb
Host smart-cc86af9c-978d-47dc-bbca-bd681156b70d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254565052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3254565052
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.428480545
Short name T643
Test name
Test status
Simulation time 102771014 ps
CPU time 2 seconds
Started Jul 21 07:02:50 PM PDT 24
Finished Jul 21 07:02:53 PM PDT 24
Peak memory 221656 kb
Host smart-a6b88156-9e69-407f-bd5f-ea6e83e38a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428480545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.428480545
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2544114126
Short name T456
Test name
Test status
Simulation time 382191243 ps
CPU time 12.65 seconds
Started Jul 21 07:02:56 PM PDT 24
Finished Jul 21 07:03:10 PM PDT 24
Peak memory 218520 kb
Host smart-ebdbb5f8-4318-436b-b28a-8066e74e2ea1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544114126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2544114126
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3947647399
Short name T496
Test name
Test status
Simulation time 837823124 ps
CPU time 11.07 seconds
Started Jul 21 07:02:55 PM PDT 24
Finished Jul 21 07:03:07 PM PDT 24
Peak memory 217824 kb
Host smart-787f62f4-2363-47fe-901e-f78fc9367bdf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947647399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3947647399
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3906213485
Short name T706
Test name
Test status
Simulation time 200944201 ps
CPU time 7.03 seconds
Started Jul 21 07:02:57 PM PDT 24
Finished Jul 21 07:03:06 PM PDT 24
Peak memory 225544 kb
Host smart-1ab81bbe-1225-4596-9780-670be6c069c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906213485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3906213485
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.254689912
Short name T843
Test name
Test status
Simulation time 878012315 ps
CPU time 10.75 seconds
Started Jul 21 07:02:52 PM PDT 24
Finished Jul 21 07:03:09 PM PDT 24
Peak memory 217888 kb
Host smart-1033cf5e-955d-4778-8293-c5fa14a29fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254689912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.254689912
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.318596039
Short name T69
Test name
Test status
Simulation time 578606555 ps
CPU time 8.06 seconds
Started Jul 21 07:02:53 PM PDT 24
Finished Jul 21 07:03:02 PM PDT 24
Peak memory 217272 kb
Host smart-ee6a78f1-b7bc-4bb5-9d60-a86a4228c196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318596039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.318596039
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.2387134155
Short name T511
Test name
Test status
Simulation time 198374480 ps
CPU time 21.34 seconds
Started Jul 21 07:02:49 PM PDT 24
Finished Jul 21 07:03:11 PM PDT 24
Peak memory 250556 kb
Host smart-537624ee-13a0-49a6-b4e3-d0a7e64cf2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387134155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2387134155
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.985515447
Short name T374
Test name
Test status
Simulation time 446633851 ps
CPU time 9.34 seconds
Started Jul 21 07:02:55 PM PDT 24
Finished Jul 21 07:03:04 PM PDT 24
Peak memory 250580 kb
Host smart-4ee29ad5-d8b3-4362-bdcb-69ef0dbbc581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985515447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.985515447
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.867856983
Short name T79
Test name
Test status
Simulation time 3322762004 ps
CPU time 107.53 seconds
Started Jul 21 07:02:51 PM PDT 24
Finished Jul 21 07:04:39 PM PDT 24
Peak memory 225700 kb
Host smart-f12b576e-9be1-4bd6-873e-be0c85327169
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867856983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.867856983
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1431629568
Short name T40
Test name
Test status
Simulation time 21774269 ps
CPU time 1.02 seconds
Started Jul 21 07:02:52 PM PDT 24
Finished Jul 21 07:02:54 PM PDT 24
Peak memory 211424 kb
Host smart-e94db79d-c919-4ef1-bf25-d994c0734452
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431629568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1431629568
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.710614142
Short name T531
Test name
Test status
Simulation time 21804042 ps
CPU time 0.89 seconds
Started Jul 21 07:03:01 PM PDT 24
Finished Jul 21 07:03:04 PM PDT 24
Peak memory 208364 kb
Host smart-cb4b547b-0fd2-4c97-85d1-7c1954ad8b55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710614142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.710614142
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1538769833
Short name T330
Test name
Test status
Simulation time 415847533 ps
CPU time 18.46 seconds
Started Jul 21 07:02:59 PM PDT 24
Finished Jul 21 07:03:19 PM PDT 24
Peak memory 217876 kb
Host smart-e81ad4f4-2932-4d0d-8bd9-e0185c47be21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538769833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1538769833
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.782358464
Short name T650
Test name
Test status
Simulation time 389552204 ps
CPU time 10.65 seconds
Started Jul 21 07:03:04 PM PDT 24
Finished Jul 21 07:03:16 PM PDT 24
Peak memory 216928 kb
Host smart-c9790adb-9c5a-45dc-b75c-6105c102701f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782358464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.782358464
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1129879238
Short name T589
Test name
Test status
Simulation time 32295845 ps
CPU time 1.94 seconds
Started Jul 21 07:03:00 PM PDT 24
Finished Jul 21 07:03:04 PM PDT 24
Peak memory 217756 kb
Host smart-930b953a-adf0-4fe4-b4a2-5263e565044c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129879238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1129879238
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1843148950
Short name T705
Test name
Test status
Simulation time 180551593 ps
CPU time 9.7 seconds
Started Jul 21 07:02:56 PM PDT 24
Finished Jul 21 07:03:08 PM PDT 24
Peak memory 217768 kb
Host smart-ff4d1d58-6ed4-42af-a279-90206ca497d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843148950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1843148950
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.4269862641
Short name T471
Test name
Test status
Simulation time 532621413 ps
CPU time 13.05 seconds
Started Jul 21 07:02:55 PM PDT 24
Finished Jul 21 07:03:09 PM PDT 24
Peak memory 217828 kb
Host smart-62fcf702-b8a3-47ef-92c4-bd255ab9f447
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269862641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.4269862641
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.711452930
Short name T534
Test name
Test status
Simulation time 1109600939 ps
CPU time 10.97 seconds
Started Jul 21 07:02:59 PM PDT 24
Finished Jul 21 07:03:12 PM PDT 24
Peak memory 225536 kb
Host smart-e7386bde-c4c2-4df0-ab06-28f8f7038659
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711452930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.711452930
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.398556099
Short name T394
Test name
Test status
Simulation time 6376767831 ps
CPU time 14.56 seconds
Started Jul 21 07:02:56 PM PDT 24
Finished Jul 21 07:03:12 PM PDT 24
Peak memory 217948 kb
Host smart-65a882e8-be7b-459c-b0b6-dd9731240a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398556099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.398556099
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3248606004
Short name T72
Test name
Test status
Simulation time 169941628 ps
CPU time 2.09 seconds
Started Jul 21 07:03:05 PM PDT 24
Finished Jul 21 07:03:08 PM PDT 24
Peak memory 213800 kb
Host smart-90916a18-0439-4a84-be05-ea0a9d2dc3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248606004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3248606004
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2787086662
Short name T785
Test name
Test status
Simulation time 707372862 ps
CPU time 36 seconds
Started Jul 21 07:02:57 PM PDT 24
Finished Jul 21 07:03:35 PM PDT 24
Peak memory 250568 kb
Host smart-dde305ea-f36f-4eb3-8cd8-fae8fd6d1221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787086662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2787086662
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.4231950388
Short name T514
Test name
Test status
Simulation time 290784501 ps
CPU time 7.48 seconds
Started Jul 21 07:02:55 PM PDT 24
Finished Jul 21 07:03:12 PM PDT 24
Peak memory 250552 kb
Host smart-741f77bd-3d3c-4e25-a0c4-80a5b8a3dd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231950388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.4231950388
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.3568363187
Short name T281
Test name
Test status
Simulation time 26169771584 ps
CPU time 350.55 seconds
Started Jul 21 07:02:54 PM PDT 24
Finished Jul 21 07:08:45 PM PDT 24
Peak memory 225732 kb
Host smart-192d581d-94cf-4248-8ba5-6154e1a7d4c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568363187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.3568363187
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.771249682
Short name T308
Test name
Test status
Simulation time 12612079 ps
CPU time 0.98 seconds
Started Jul 21 07:03:03 PM PDT 24
Finished Jul 21 07:03:05 PM PDT 24
Peak memory 208536 kb
Host smart-033280d4-7cf9-4d0c-ab37-1c3bddc1d168
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771249682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct
rl_volatile_unlock_smoke.771249682
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1348198409
Short name T831
Test name
Test status
Simulation time 30615107 ps
CPU time 0.85 seconds
Started Jul 21 07:02:55 PM PDT 24
Finished Jul 21 07:02:57 PM PDT 24
Peak memory 208312 kb
Host smart-19681ac5-42d0-4fde-be1f-db9b387ec8c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348198409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1348198409
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3961778233
Short name T715
Test name
Test status
Simulation time 1620270225 ps
CPU time 11.72 seconds
Started Jul 21 07:02:55 PM PDT 24
Finished Jul 21 07:03:07 PM PDT 24
Peak memory 217864 kb
Host smart-c607ad4f-0f52-47bb-a330-d03479b1c539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961778233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3961778233
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.2617469623
Short name T523
Test name
Test status
Simulation time 1052869512 ps
CPU time 13.85 seconds
Started Jul 21 07:02:57 PM PDT 24
Finished Jul 21 07:03:12 PM PDT 24
Peak memory 217044 kb
Host smart-bdced89c-fadf-4902-a630-7b90263e1903
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617469623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.2617469623
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.842066761
Short name T800
Test name
Test status
Simulation time 137850519 ps
CPU time 3.5 seconds
Started Jul 21 07:02:57 PM PDT 24
Finished Jul 21 07:03:02 PM PDT 24
Peak memory 222084 kb
Host smart-2d5897c8-431b-4234-aedd-1ab53bc2c143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842066761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.842066761
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.4182322995
Short name T581
Test name
Test status
Simulation time 727174075 ps
CPU time 14.92 seconds
Started Jul 21 07:02:55 PM PDT 24
Finished Jul 21 07:03:11 PM PDT 24
Peak memory 217816 kb
Host smart-705da08c-8771-419c-ae0a-79385da78029
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182322995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.4182322995
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2070293647
Short name T398
Test name
Test status
Simulation time 237079120 ps
CPU time 6.28 seconds
Started Jul 21 07:02:54 PM PDT 24
Finished Jul 21 07:03:01 PM PDT 24
Peak memory 224796 kb
Host smart-6a33f8b3-1705-4ce7-b792-ed43f3354b5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070293647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2070293647
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1711140164
Short name T455
Test name
Test status
Simulation time 268041103 ps
CPU time 11.12 seconds
Started Jul 21 07:03:00 PM PDT 24
Finished Jul 21 07:03:13 PM PDT 24
Peak memory 217864 kb
Host smart-88fc7984-27ef-45bc-98da-0fa9c4aff0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711140164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1711140164
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3248471110
Short name T81
Test name
Test status
Simulation time 268784223 ps
CPU time 3.01 seconds
Started Jul 21 07:02:58 PM PDT 24
Finished Jul 21 07:03:03 PM PDT 24
Peak memory 214228 kb
Host smart-0eb874f5-30b1-4b3c-85ac-d6a947378f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248471110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3248471110
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1269751444
Short name T742
Test name
Test status
Simulation time 206438562 ps
CPU time 20.37 seconds
Started Jul 21 07:02:58 PM PDT 24
Finished Jul 21 07:03:21 PM PDT 24
Peak memory 250540 kb
Host smart-3a56be96-b144-4458-8680-436909363244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269751444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1269751444
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2365040658
Short name T298
Test name
Test status
Simulation time 54978075 ps
CPU time 7.4 seconds
Started Jul 21 07:02:59 PM PDT 24
Finished Jul 21 07:03:09 PM PDT 24
Peak memory 250444 kb
Host smart-ce4ba2b1-3749-4e11-abdd-735162b3b56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365040658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2365040658
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1799663284
Short name T99
Test name
Test status
Simulation time 5622536166 ps
CPU time 108.01 seconds
Started Jul 21 07:03:00 PM PDT 24
Finished Jul 21 07:04:50 PM PDT 24
Peak memory 297176 kb
Host smart-79b8238b-0d26-45a2-b3db-f45dcb8049c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799663284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1799663284
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1197454322
Short name T241
Test name
Test status
Simulation time 10059677 ps
CPU time 0.78 seconds
Started Jul 21 07:03:02 PM PDT 24
Finished Jul 21 07:03:04 PM PDT 24
Peak memory 207680 kb
Host smart-21548c36-5398-4405-96d7-64df4a60e53f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197454322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1197454322
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3961342126
Short name T249
Test name
Test status
Simulation time 56872431 ps
CPU time 1.34 seconds
Started Jul 21 07:02:55 PM PDT 24
Finished Jul 21 07:02:57 PM PDT 24
Peak memory 208628 kb
Host smart-c0b98a6c-5ac8-4c93-acca-7d262fff526c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961342126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3961342126
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2185425924
Short name T625
Test name
Test status
Simulation time 880990113 ps
CPU time 13.87 seconds
Started Jul 21 07:03:01 PM PDT 24
Finished Jul 21 07:03:17 PM PDT 24
Peak memory 217836 kb
Host smart-06e4da10-9353-48b1-8486-3b9e455cb975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185425924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2185425924
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3455519284
Short name T428
Test name
Test status
Simulation time 797295780 ps
CPU time 6.1 seconds
Started Jul 21 07:03:01 PM PDT 24
Finished Jul 21 07:03:09 PM PDT 24
Peak memory 216852 kb
Host smart-1486f419-86f0-4d4d-9e08-bb213f6e1155
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455519284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3455519284
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2176797874
Short name T237
Test name
Test status
Simulation time 307297329 ps
CPU time 3.04 seconds
Started Jul 21 07:02:58 PM PDT 24
Finished Jul 21 07:03:03 PM PDT 24
Peak memory 217808 kb
Host smart-b84e02dc-0e3d-4e3d-86b8-b5d6afa8a1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176797874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2176797874
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.609039575
Short name T754
Test name
Test status
Simulation time 295825159 ps
CPU time 10.81 seconds
Started Jul 21 07:02:52 PM PDT 24
Finished Jul 21 07:03:03 PM PDT 24
Peak memory 218512 kb
Host smart-345e758a-af15-4675-be6e-e7b31b27ef4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609039575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.609039575
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3028445822
Short name T657
Test name
Test status
Simulation time 1042154115 ps
CPU time 11.34 seconds
Started Jul 21 07:02:53 PM PDT 24
Finished Jul 21 07:03:05 PM PDT 24
Peak memory 217840 kb
Host smart-0870f8ce-6dd4-4656-a868-bb61563adcbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028445822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3028445822
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.4171621079
Short name T414
Test name
Test status
Simulation time 4077073126 ps
CPU time 14.17 seconds
Started Jul 21 07:02:59 PM PDT 24
Finished Jul 21 07:03:15 PM PDT 24
Peak memory 225620 kb
Host smart-312eaa17-e59c-401d-872b-37751d24ba40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171621079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
4171621079
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.384064683
Short name T532
Test name
Test status
Simulation time 469436904 ps
CPU time 8.51 seconds
Started Jul 21 07:03:04 PM PDT 24
Finished Jul 21 07:03:14 PM PDT 24
Peak memory 217880 kb
Host smart-44d57fa5-6e4d-4ad0-8fa4-0f3770a8851b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384064683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.384064683
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.505135517
Short name T399
Test name
Test status
Simulation time 86782633 ps
CPU time 3.22 seconds
Started Jul 21 07:02:57 PM PDT 24
Finished Jul 21 07:03:02 PM PDT 24
Peak memory 217236 kb
Host smart-112b0507-87cf-41a6-a1e5-6a9ac3f2a7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505135517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.505135517
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.139404143
Short name T223
Test name
Test status
Simulation time 416667695 ps
CPU time 24.54 seconds
Started Jul 21 07:03:03 PM PDT 24
Finished Jul 21 07:03:29 PM PDT 24
Peak memory 250548 kb
Host smart-c2f34efc-3f33-4e71-97a9-c43496d682d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139404143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.139404143
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.747858293
Short name T378
Test name
Test status
Simulation time 151009741 ps
CPU time 7.13 seconds
Started Jul 21 07:02:56 PM PDT 24
Finished Jul 21 07:03:04 PM PDT 24
Peak memory 246556 kb
Host smart-6ed2bd45-12f2-4acb-8b7a-9476c6597391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747858293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.747858293
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.896549472
Short name T638
Test name
Test status
Simulation time 11663666888 ps
CPU time 105.94 seconds
Started Jul 21 07:02:53 PM PDT 24
Finished Jul 21 07:04:40 PM PDT 24
Peak memory 251536 kb
Host smart-a3488a2f-aed5-4152-b738-299c5b8fdbe4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896549472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.896549472
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.894399404
Short name T845
Test name
Test status
Simulation time 14032099 ps
CPU time 0.96 seconds
Started Jul 21 07:02:56 PM PDT 24
Finished Jul 21 07:02:58 PM PDT 24
Peak memory 208476 kb
Host smart-f6103ba2-7227-4bce-a3bf-3bdbf76cfd1d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894399404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.894399404
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3201867648
Short name T413
Test name
Test status
Simulation time 112158198 ps
CPU time 1 seconds
Started Jul 21 07:03:05 PM PDT 24
Finished Jul 21 07:03:06 PM PDT 24
Peak memory 208584 kb
Host smart-08d7ef11-05b8-4e2e-8b49-a827aa2e37ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201867648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3201867648
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2420595212
Short name T501
Test name
Test status
Simulation time 1388753215 ps
CPU time 12.46 seconds
Started Jul 21 07:02:59 PM PDT 24
Finished Jul 21 07:03:14 PM PDT 24
Peak memory 217740 kb
Host smart-6d954c5a-b681-4b75-87d5-bb349d0971b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420595212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2420595212
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.780517369
Short name T433
Test name
Test status
Simulation time 363192074 ps
CPU time 5.16 seconds
Started Jul 21 07:03:04 PM PDT 24
Finished Jul 21 07:03:10 PM PDT 24
Peak memory 217148 kb
Host smart-484011fc-846b-4085-bc2d-d125c4aed090
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780517369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.780517369
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1141305784
Short name T325
Test name
Test status
Simulation time 204711378 ps
CPU time 4.49 seconds
Started Jul 21 07:02:57 PM PDT 24
Finished Jul 21 07:03:03 PM PDT 24
Peak memory 217836 kb
Host smart-82f44bde-0f2f-4539-bf52-592bf3c01b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141305784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1141305784
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3027108874
Short name T437
Test name
Test status
Simulation time 1987488753 ps
CPU time 16.19 seconds
Started Jul 21 07:03:00 PM PDT 24
Finished Jul 21 07:03:19 PM PDT 24
Peak memory 217828 kb
Host smart-54d78ff4-5098-430c-aa7f-9ddbf25c44b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027108874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3027108874
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2594609812
Short name T326
Test name
Test status
Simulation time 273320223 ps
CPU time 7.39 seconds
Started Jul 21 07:02:58 PM PDT 24
Finished Jul 21 07:03:07 PM PDT 24
Peak memory 225192 kb
Host smart-7020663d-31bc-4a99-8522-f1ec96d49f07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594609812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2594609812
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2892394478
Short name T168
Test name
Test status
Simulation time 371522862 ps
CPU time 9.8 seconds
Started Jul 21 07:03:00 PM PDT 24
Finished Jul 21 07:03:12 PM PDT 24
Peak memory 225192 kb
Host smart-61285c8a-3d36-4f4c-b550-b50195dbce4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892394478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2892394478
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2294714710
Short name T536
Test name
Test status
Simulation time 21307622 ps
CPU time 1.75 seconds
Started Jul 21 07:03:00 PM PDT 24
Finished Jul 21 07:03:04 PM PDT 24
Peak memory 213680 kb
Host smart-11e9753a-0b3c-473d-9505-5110a3df1951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294714710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2294714710
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3259266042
Short name T789
Test name
Test status
Simulation time 884955515 ps
CPU time 18.75 seconds
Started Jul 21 07:02:56 PM PDT 24
Finished Jul 21 07:03:15 PM PDT 24
Peak memory 250580 kb
Host smart-c8070a60-a9a5-4c68-bf44-fc7191ad85af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259266042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3259266042
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1983545990
Short name T644
Test name
Test status
Simulation time 211251271 ps
CPU time 3.5 seconds
Started Jul 21 07:03:11 PM PDT 24
Finished Jul 21 07:03:15 PM PDT 24
Peak memory 222216 kb
Host smart-24d30b3d-14ab-4c50-b280-f91484e596ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983545990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1983545990
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3624899387
Short name T483
Test name
Test status
Simulation time 19986784904 ps
CPU time 288.97 seconds
Started Jul 21 07:02:54 PM PDT 24
Finished Jul 21 07:07:44 PM PDT 24
Peak memory 250888 kb
Host smart-2a7dec45-5d73-4c70-a9a9-66a263f45493
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624899387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3624899387
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3219673060
Short name T490
Test name
Test status
Simulation time 15711547 ps
CPU time 1 seconds
Started Jul 21 07:02:57 PM PDT 24
Finished Jul 21 07:03:00 PM PDT 24
Peak memory 208480 kb
Host smart-e0507e03-05c5-4e5b-8341-b189678df757
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219673060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3219673060
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2373562490
Short name T77
Test name
Test status
Simulation time 58304963 ps
CPU time 0.88 seconds
Started Jul 21 07:02:59 PM PDT 24
Finished Jul 21 07:03:01 PM PDT 24
Peak memory 208364 kb
Host smart-c0912e31-6f9a-4a92-b551-1d9ed3249502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373562490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2373562490
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1615131134
Short name T730
Test name
Test status
Simulation time 5935920475 ps
CPU time 15.89 seconds
Started Jul 21 07:03:14 PM PDT 24
Finished Jul 21 07:03:30 PM PDT 24
Peak memory 218496 kb
Host smart-b9b711df-371e-4cae-8560-6a6963e648fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615131134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1615131134
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.777058224
Short name T421
Test name
Test status
Simulation time 61396028 ps
CPU time 1.78 seconds
Started Jul 21 07:03:06 PM PDT 24
Finished Jul 21 07:03:08 PM PDT 24
Peak memory 216824 kb
Host smart-ddce052e-c21e-469b-af3f-98746025097d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777058224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.777058224
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2129629222
Short name T412
Test name
Test status
Simulation time 84245412 ps
CPU time 2.72 seconds
Started Jul 21 07:03:04 PM PDT 24
Finished Jul 21 07:03:08 PM PDT 24
Peak memory 217964 kb
Host smart-052abe0f-2a0f-4f24-9181-3d55db729cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129629222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2129629222
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3379217181
Short name T628
Test name
Test status
Simulation time 1990293043 ps
CPU time 14.53 seconds
Started Jul 21 07:03:04 PM PDT 24
Finished Jul 21 07:03:20 PM PDT 24
Peak memory 217996 kb
Host smart-b3f125d0-73de-4a74-9e14-ed35663ee181
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379217181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3379217181
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.4034098450
Short name T822
Test name
Test status
Simulation time 4804931240 ps
CPU time 16.75 seconds
Started Jul 21 07:02:59 PM PDT 24
Finished Jul 21 07:03:18 PM PDT 24
Peak memory 225716 kb
Host smart-e12bf4cb-ac21-476b-9b00-2383d91916ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034098450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
4034098450
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1420147405
Short name T751
Test name
Test status
Simulation time 367837022 ps
CPU time 8.67 seconds
Started Jul 21 07:02:59 PM PDT 24
Finished Jul 21 07:03:10 PM PDT 24
Peak memory 217868 kb
Host smart-1edb5921-b517-4880-b962-5765fe5a3e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420147405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1420147405
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2037023097
Short name T334
Test name
Test status
Simulation time 123195236 ps
CPU time 2.81 seconds
Started Jul 21 07:02:58 PM PDT 24
Finished Jul 21 07:03:02 PM PDT 24
Peak memory 223472 kb
Host smart-a3290130-f858-493e-b200-460b21564f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037023097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2037023097
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1861807490
Short name T788
Test name
Test status
Simulation time 747826125 ps
CPU time 18.34 seconds
Started Jul 21 07:03:10 PM PDT 24
Finished Jul 21 07:03:29 PM PDT 24
Peak memory 250588 kb
Host smart-2708b590-f0e4-4297-b132-0f3bc78b0230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861807490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1861807490
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3637434293
Short name T821
Test name
Test status
Simulation time 446717299 ps
CPU time 6.7 seconds
Started Jul 21 07:02:55 PM PDT 24
Finished Jul 21 07:03:03 PM PDT 24
Peak memory 249900 kb
Host smart-8599af61-5214-45e8-a220-75c445b57450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637434293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3637434293
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2503708031
Short name T277
Test name
Test status
Simulation time 4884732523 ps
CPU time 89.65 seconds
Started Jul 21 07:02:57 PM PDT 24
Finished Jul 21 07:04:28 PM PDT 24
Peak memory 267020 kb
Host smart-e38ed3cb-9ee8-48e0-9ee1-e7f11e397c84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503708031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2503708031
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1852390414
Short name T470
Test name
Test status
Simulation time 13414188 ps
CPU time 0.96 seconds
Started Jul 21 07:02:57 PM PDT 24
Finished Jul 21 07:03:00 PM PDT 24
Peak memory 208484 kb
Host smart-5daaf8af-05f2-4d3b-8bf6-3c16a4a9818b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852390414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1852390414
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.429319886
Short name T342
Test name
Test status
Simulation time 32733259 ps
CPU time 1.37 seconds
Started Jul 21 07:03:07 PM PDT 24
Finished Jul 21 07:03:09 PM PDT 24
Peak memory 208736 kb
Host smart-de0224ae-2fb2-48e8-970b-93515506a381
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429319886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.429319886
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1737665051
Short name T494
Test name
Test status
Simulation time 1237508468 ps
CPU time 13.44 seconds
Started Jul 21 07:03:14 PM PDT 24
Finished Jul 21 07:03:28 PM PDT 24
Peak memory 217884 kb
Host smart-84d454fc-05c1-46f5-9d21-b599fe947c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737665051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1737665051
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1394889446
Short name T756
Test name
Test status
Simulation time 2261610049 ps
CPU time 4.24 seconds
Started Jul 21 07:03:09 PM PDT 24
Finished Jul 21 07:03:13 PM PDT 24
Peak memory 217328 kb
Host smart-6fd21a32-9e15-40b2-b37a-31e04521d648
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394889446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1394889446
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2498743086
Short name T485
Test name
Test status
Simulation time 34896948 ps
CPU time 1.93 seconds
Started Jul 21 07:02:56 PM PDT 24
Finished Jul 21 07:03:00 PM PDT 24
Peak memory 221860 kb
Host smart-742b798d-c888-47a4-8c12-7092429a5ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498743086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2498743086
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2475012021
Short name T384
Test name
Test status
Simulation time 5506857495 ps
CPU time 17.31 seconds
Started Jul 21 07:03:09 PM PDT 24
Finished Jul 21 07:03:32 PM PDT 24
Peak memory 225740 kb
Host smart-39638ef8-99e4-497f-a9f7-2a423a41cbab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475012021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2475012021
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2867773188
Short name T225
Test name
Test status
Simulation time 1116795829 ps
CPU time 12.91 seconds
Started Jul 21 07:03:11 PM PDT 24
Finished Jul 21 07:03:24 PM PDT 24
Peak memory 217804 kb
Host smart-8dc82916-4c2a-49ad-a969-e3e157a42a90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867773188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2867773188
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3600483618
Short name T164
Test name
Test status
Simulation time 2209020364 ps
CPU time 7.47 seconds
Started Jul 21 07:03:06 PM PDT 24
Finished Jul 21 07:03:14 PM PDT 24
Peak memory 224744 kb
Host smart-e8d80eb0-f417-4df3-a513-e107fcc1821e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600483618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3600483618
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1130311752
Short name T493
Test name
Test status
Simulation time 529810188 ps
CPU time 10.13 seconds
Started Jul 21 07:03:00 PM PDT 24
Finished Jul 21 07:03:12 PM PDT 24
Peak memory 217924 kb
Host smart-36a7a048-292b-463e-85c6-2952ca5748c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130311752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1130311752
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1107959979
Short name T666
Test name
Test status
Simulation time 36277522 ps
CPU time 0.94 seconds
Started Jul 21 07:03:03 PM PDT 24
Finished Jul 21 07:03:09 PM PDT 24
Peak memory 208496 kb
Host smart-969c71be-abca-41c8-b7eb-17a809333106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107959979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1107959979
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1448035832
Short name T458
Test name
Test status
Simulation time 3279372513 ps
CPU time 28.21 seconds
Started Jul 21 07:03:00 PM PDT 24
Finished Jul 21 07:03:30 PM PDT 24
Peak memory 250616 kb
Host smart-a7ebe545-d4d2-49aa-a834-1d8d5089945d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448035832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1448035832
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2709184290
Short name T732
Test name
Test status
Simulation time 107643443 ps
CPU time 3.1 seconds
Started Jul 21 07:03:09 PM PDT 24
Finished Jul 21 07:03:13 PM PDT 24
Peak memory 222100 kb
Host smart-b2e14a0b-4f30-445a-bec5-664ca4baa8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709184290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2709184290
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1170338031
Short name T767
Test name
Test status
Simulation time 14337036315 ps
CPU time 92.77 seconds
Started Jul 21 07:03:00 PM PDT 24
Finished Jul 21 07:04:35 PM PDT 24
Peak memory 283288 kb
Host smart-4bb7a425-f253-4df9-9baf-c47092266c87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170338031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1170338031
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3789804292
Short name T563
Test name
Test status
Simulation time 72558411 ps
CPU time 0.93 seconds
Started Jul 21 07:03:07 PM PDT 24
Finished Jul 21 07:03:09 PM PDT 24
Peak memory 211440 kb
Host smart-44a088df-4b18-4853-9be6-67a700ae7018
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789804292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3789804292
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3644064648
Short name T218
Test name
Test status
Simulation time 13553599 ps
CPU time 1.01 seconds
Started Jul 21 07:03:01 PM PDT 24
Finished Jul 21 07:03:04 PM PDT 24
Peak memory 208420 kb
Host smart-8b8849e9-57db-4dc9-b5ca-e17366c19002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644064648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3644064648
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.114798970
Short name T244
Test name
Test status
Simulation time 924260300 ps
CPU time 10.87 seconds
Started Jul 21 07:02:58 PM PDT 24
Finished Jul 21 07:03:10 PM PDT 24
Peak memory 217852 kb
Host smart-0fcf0bfb-fb9b-42fa-a45f-f5ed7a5bf14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114798970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.114798970
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2935715014
Short name T586
Test name
Test status
Simulation time 615103885 ps
CPU time 6.03 seconds
Started Jul 21 07:03:14 PM PDT 24
Finished Jul 21 07:03:21 PM PDT 24
Peak memory 216760 kb
Host smart-61e6bb0e-dd0f-47f7-a58f-4eddf67744e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935715014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2935715014
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1789569167
Short name T166
Test name
Test status
Simulation time 21054946 ps
CPU time 1.72 seconds
Started Jul 21 07:03:03 PM PDT 24
Finished Jul 21 07:03:06 PM PDT 24
Peak memory 217780 kb
Host smart-b5fcdaca-3f54-4132-9a22-1e7381be3e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789569167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1789569167
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.1198624349
Short name T741
Test name
Test status
Simulation time 810655555 ps
CPU time 17.16 seconds
Started Jul 21 07:03:01 PM PDT 24
Finished Jul 21 07:03:20 PM PDT 24
Peak memory 218464 kb
Host smart-43692b07-bdb2-4d3b-b8d1-20a8c5c36b4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198624349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1198624349
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.79701829
Short name T183
Test name
Test status
Simulation time 351093932 ps
CPU time 13.29 seconds
Started Jul 21 07:03:02 PM PDT 24
Finished Jul 21 07:03:17 PM PDT 24
Peak memory 225572 kb
Host smart-7f9bf8aa-2217-4914-bcc8-9ee46895569a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79701829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_dig
est.79701829
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.131333576
Short name T242
Test name
Test status
Simulation time 4341999958 ps
CPU time 10.95 seconds
Started Jul 21 07:03:11 PM PDT 24
Finished Jul 21 07:03:23 PM PDT 24
Peak memory 225552 kb
Host smart-d34e4690-8d2d-4ed8-b1d1-fe3f512d7b86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131333576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.131333576
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.4078958197
Short name T450
Test name
Test status
Simulation time 279500113 ps
CPU time 10.02 seconds
Started Jul 21 07:03:04 PM PDT 24
Finished Jul 21 07:03:15 PM PDT 24
Peak memory 225716 kb
Host smart-e4b48b3b-8cb0-4ed0-8702-c165a4fe118b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078958197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.4078958197
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3505538530
Short name T605
Test name
Test status
Simulation time 135651158 ps
CPU time 2.74 seconds
Started Jul 21 07:03:01 PM PDT 24
Finished Jul 21 07:03:06 PM PDT 24
Peak memory 217204 kb
Host smart-875322d9-049c-4b07-bd84-f814f0fcfec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505538530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3505538530
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.817386022
Short name T404
Test name
Test status
Simulation time 604592072 ps
CPU time 26.59 seconds
Started Jul 21 07:03:07 PM PDT 24
Finished Jul 21 07:03:35 PM PDT 24
Peak memory 250692 kb
Host smart-c5c8e27b-29dc-49e9-84b5-867094b8bd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817386022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.817386022
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.4180154272
Short name T796
Test name
Test status
Simulation time 67521025 ps
CPU time 4.04 seconds
Started Jul 21 07:03:00 PM PDT 24
Finished Jul 21 07:03:06 PM PDT 24
Peak memory 222472 kb
Host smart-d084e5c3-28cd-4f51-86e9-7000f879715e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180154272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.4180154272
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1485264357
Short name T190
Test name
Test status
Simulation time 22963485647 ps
CPU time 184.27 seconds
Started Jul 21 07:03:14 PM PDT 24
Finished Jul 21 07:06:18 PM PDT 24
Peak memory 267988 kb
Host smart-0b265458-c7b5-4a5d-b338-f60d933642be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485264357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1485264357
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.596688927
Short name T113
Test name
Test status
Simulation time 12380097981 ps
CPU time 522.9 seconds
Started Jul 21 07:03:03 PM PDT 24
Finished Jul 21 07:11:47 PM PDT 24
Peak memory 421772 kb
Host smart-74282f25-dd34-4560-a17c-3d2e5b316496
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=596688927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.596688927
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3530262330
Short name T744
Test name
Test status
Simulation time 15056070 ps
CPU time 0.9 seconds
Started Jul 21 07:03:17 PM PDT 24
Finished Jul 21 07:03:19 PM PDT 24
Peak memory 208480 kb
Host smart-13b374ea-2f72-44ad-ab46-da8e543b5b89
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530262330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3530262330
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1829700766
Short name T247
Test name
Test status
Simulation time 23010597 ps
CPU time 0.97 seconds
Started Jul 21 07:03:11 PM PDT 24
Finished Jul 21 07:03:12 PM PDT 24
Peak memory 208424 kb
Host smart-67cb5b20-c4af-481b-ae77-c66d3661850e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829700766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1829700766
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1867462327
Short name T276
Test name
Test status
Simulation time 338168368 ps
CPU time 15.14 seconds
Started Jul 21 07:03:01 PM PDT 24
Finished Jul 21 07:03:18 PM PDT 24
Peak memory 217888 kb
Host smart-b728f27a-c4b2-4f63-b193-a0a13c7fc849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867462327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1867462327
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3616858174
Short name T453
Test name
Test status
Simulation time 4404982079 ps
CPU time 8.72 seconds
Started Jul 21 07:03:21 PM PDT 24
Finished Jul 21 07:03:30 PM PDT 24
Peak memory 217240 kb
Host smart-3397b807-8040-4949-8140-a0cbb497ff50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616858174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.3616858174
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2504208650
Short name T552
Test name
Test status
Simulation time 59948207 ps
CPU time 2.82 seconds
Started Jul 21 07:03:06 PM PDT 24
Finished Jul 21 07:03:09 PM PDT 24
Peak memory 217812 kb
Host smart-faa2ef8d-fdb1-4296-8b42-31ede08d19bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504208650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2504208650
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1859592320
Short name T340
Test name
Test status
Simulation time 496780942 ps
CPU time 13.63 seconds
Started Jul 21 07:03:18 PM PDT 24
Finished Jul 21 07:03:32 PM PDT 24
Peak memory 218448 kb
Host smart-61f26f6f-06c5-4cf8-b59f-b7e570198d1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859592320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1859592320
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3836260413
Short name T791
Test name
Test status
Simulation time 421056658 ps
CPU time 15.1 seconds
Started Jul 21 07:03:03 PM PDT 24
Finished Jul 21 07:03:20 PM PDT 24
Peak memory 217768 kb
Host smart-629e6380-33d2-4642-a0c6-e078e6277544
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836260413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3836260413
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2579457868
Short name T318
Test name
Test status
Simulation time 669872204 ps
CPU time 12.27 seconds
Started Jul 21 07:02:59 PM PDT 24
Finished Jul 21 07:03:14 PM PDT 24
Peak memory 225492 kb
Host smart-e144e3da-6b34-4ab9-8681-65e5c2129f9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579457868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2579457868
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.318593098
Short name T463
Test name
Test status
Simulation time 1445300946 ps
CPU time 8.65 seconds
Started Jul 21 07:03:01 PM PDT 24
Finished Jul 21 07:03:12 PM PDT 24
Peak memory 217896 kb
Host smart-d8204c8f-0734-4152-9414-82b4cf7ed0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318593098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.318593098
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1080689340
Short name T65
Test name
Test status
Simulation time 64572181 ps
CPU time 2.83 seconds
Started Jul 21 07:03:18 PM PDT 24
Finished Jul 21 07:03:21 PM PDT 24
Peak memory 213884 kb
Host smart-585cebd9-87b5-43af-9f1b-225ad363210e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080689340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1080689340
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1197811997
Short name T718
Test name
Test status
Simulation time 244290673 ps
CPU time 24.71 seconds
Started Jul 21 07:03:01 PM PDT 24
Finished Jul 21 07:03:28 PM PDT 24
Peak memory 250556 kb
Host smart-992754f8-7bb8-485f-90dc-d4242c8f12b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197811997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1197811997
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1882811314
Short name T591
Test name
Test status
Simulation time 66703624 ps
CPU time 7.23 seconds
Started Jul 21 07:03:01 PM PDT 24
Finished Jul 21 07:03:11 PM PDT 24
Peak memory 246780 kb
Host smart-7be4a16f-e96e-46af-bae2-b60eb41e2ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882811314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1882811314
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1800318431
Short name T594
Test name
Test status
Simulation time 6106174933 ps
CPU time 217.24 seconds
Started Jul 21 07:03:17 PM PDT 24
Finished Jul 21 07:06:54 PM PDT 24
Peak memory 283392 kb
Host smart-c014e7de-def6-4bf1-a431-7f17d4d133a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800318431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1800318431
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.2830752400
Short name T539
Test name
Test status
Simulation time 95721598217 ps
CPU time 390.27 seconds
Started Jul 21 07:03:10 PM PDT 24
Finished Jul 21 07:09:40 PM PDT 24
Peak memory 283548 kb
Host smart-7ea79575-87cd-4d3b-8bdf-2df765647835
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2830752400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.2830752400
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3404045839
Short name T457
Test name
Test status
Simulation time 19485761 ps
CPU time 0.81 seconds
Started Jul 21 07:03:02 PM PDT 24
Finished Jul 21 07:03:04 PM PDT 24
Peak memory 208272 kb
Host smart-ab035960-a15a-4106-8476-226deedecf8c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404045839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3404045839
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3539581586
Short name T850
Test name
Test status
Simulation time 16741113 ps
CPU time 1.12 seconds
Started Jul 21 07:03:24 PM PDT 24
Finished Jul 21 07:03:25 PM PDT 24
Peak memory 208428 kb
Host smart-bd725d1a-dd44-4ef6-9619-f8760bfbc330
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539581586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3539581586
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3892847367
Short name T615
Test name
Test status
Simulation time 224821774 ps
CPU time 9.32 seconds
Started Jul 21 07:03:32 PM PDT 24
Finished Jul 21 07:03:42 PM PDT 24
Peak memory 217740 kb
Host smart-95d4f704-cc98-4a05-a316-7a3dbf5537b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892847367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3892847367
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2583009489
Short name T329
Test name
Test status
Simulation time 32410260 ps
CPU time 1.59 seconds
Started Jul 21 07:03:15 PM PDT 24
Finished Jul 21 07:03:17 PM PDT 24
Peak memory 216612 kb
Host smart-e876117c-c9ee-46c0-be1e-8efe6a19aead
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583009489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2583009489
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3372317285
Short name T658
Test name
Test status
Simulation time 17285571 ps
CPU time 1.44 seconds
Started Jul 21 07:03:03 PM PDT 24
Finished Jul 21 07:03:06 PM PDT 24
Peak memory 217732 kb
Host smart-5938ed77-8040-4dbb-b4aa-b240a645f024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372317285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3372317285
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1866764025
Short name T306
Test name
Test status
Simulation time 1317887227 ps
CPU time 11.18 seconds
Started Jul 21 07:03:12 PM PDT 24
Finished Jul 21 07:03:24 PM PDT 24
Peak memory 217760 kb
Host smart-87eb153c-0093-4b06-9a4c-8cc84430a1b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866764025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1866764025
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1975423872
Short name T642
Test name
Test status
Simulation time 255090088 ps
CPU time 9.1 seconds
Started Jul 21 07:03:27 PM PDT 24
Finished Jul 21 07:03:36 PM PDT 24
Peak memory 224520 kb
Host smart-b12ea41c-b7bd-46b7-859c-761b1f48da1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975423872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1975423872
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3960051683
Short name T720
Test name
Test status
Simulation time 457332408 ps
CPU time 10.08 seconds
Started Jul 21 07:03:06 PM PDT 24
Finished Jul 21 07:03:17 PM PDT 24
Peak memory 217880 kb
Host smart-0bd69a68-ea69-4de8-8475-7fab4fd67371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960051683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3960051683
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1497453906
Short name T636
Test name
Test status
Simulation time 72960175 ps
CPU time 2.86 seconds
Started Jul 21 07:03:12 PM PDT 24
Finished Jul 21 07:03:15 PM PDT 24
Peak memory 217216 kb
Host smart-7d5792e8-d191-4baa-bea3-d93c72a05f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497453906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1497453906
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1258309911
Short name T472
Test name
Test status
Simulation time 1118581618 ps
CPU time 29.27 seconds
Started Jul 21 07:03:04 PM PDT 24
Finished Jul 21 07:03:34 PM PDT 24
Peak memory 250680 kb
Host smart-660f3dc2-fef1-418a-8d74-8fb811783dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258309911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1258309911
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1608145532
Short name T369
Test name
Test status
Simulation time 66437501 ps
CPU time 7.1 seconds
Started Jul 21 07:03:26 PM PDT 24
Finished Jul 21 07:03:33 PM PDT 24
Peak memory 250128 kb
Host smart-885ccdfd-e381-4650-a932-0e363ec9536c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608145532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1608145532
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3420183432
Short name T542
Test name
Test status
Simulation time 34719381450 ps
CPU time 147.11 seconds
Started Jul 21 07:03:13 PM PDT 24
Finished Jul 21 07:05:40 PM PDT 24
Peak memory 276592 kb
Host smart-a5f4c451-df96-44e4-bf83-cede68a1aeb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420183432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3420183432
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.3533066793
Short name T151
Test name
Test status
Simulation time 17721615408 ps
CPU time 359.16 seconds
Started Jul 21 07:03:16 PM PDT 24
Finished Jul 21 07:09:15 PM PDT 24
Peak memory 275120 kb
Host smart-05bc3e0a-beed-412b-9612-bd2dab3d6b9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3533066793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.3533066793
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3198952495
Short name T337
Test name
Test status
Simulation time 11633064 ps
CPU time 0.83 seconds
Started Jul 21 07:03:10 PM PDT 24
Finished Jul 21 07:03:11 PM PDT 24
Peak memory 208624 kb
Host smart-9da2063a-f9a2-4fb1-906f-6e440178fb8f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198952495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3198952495
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3941003355
Short name T240
Test name
Test status
Simulation time 96512769 ps
CPU time 1.13 seconds
Started Jul 21 07:01:48 PM PDT 24
Finished Jul 21 07:01:50 PM PDT 24
Peak memory 208416 kb
Host smart-4bea493c-1217-4368-855e-0c3bd0d0a9d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941003355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3941003355
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.4063354064
Short name T207
Test name
Test status
Simulation time 13387893 ps
CPU time 1 seconds
Started Jul 21 07:01:26 PM PDT 24
Finished Jul 21 07:01:27 PM PDT 24
Peak memory 208068 kb
Host smart-2f59864c-47c5-4240-a81e-7013bb07bdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063354064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.4063354064
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1930818020
Short name T349
Test name
Test status
Simulation time 818249000 ps
CPU time 14.87 seconds
Started Jul 21 07:01:49 PM PDT 24
Finished Jul 21 07:02:06 PM PDT 24
Peak memory 217752 kb
Host smart-29f3aeb5-2509-460c-bd99-c485819ab7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930818020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1930818020
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.4001156726
Short name T23
Test name
Test status
Simulation time 1554768494 ps
CPU time 11.09 seconds
Started Jul 21 07:01:25 PM PDT 24
Finished Jul 21 07:01:37 PM PDT 24
Peak memory 216748 kb
Host smart-d6b1b563-b3d6-41e4-87f9-5132245d8f65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001156726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.4001156726
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1217800289
Short name T396
Test name
Test status
Simulation time 2031268131 ps
CPU time 31.45 seconds
Started Jul 21 07:01:26 PM PDT 24
Finished Jul 21 07:01:57 PM PDT 24
Peak memory 217760 kb
Host smart-37612f32-890b-4356-b842-aa0272dd5eb2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217800289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1217800289
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3491366393
Short name T475
Test name
Test status
Simulation time 168799083 ps
CPU time 2.41 seconds
Started Jul 21 07:01:49 PM PDT 24
Finished Jul 21 07:01:53 PM PDT 24
Peak memory 217296 kb
Host smart-d4cb8afa-a7f3-460e-8771-4ed2a54d2e43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491366393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
491366393
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1156659541
Short name T436
Test name
Test status
Simulation time 268697022 ps
CPU time 4.92 seconds
Started Jul 21 07:01:44 PM PDT 24
Finished Jul 21 07:01:49 PM PDT 24
Peak memory 222440 kb
Host smart-fd0f7980-03c0-4968-9948-a4566f51b826
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156659541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1156659541
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3881387281
Short name T90
Test name
Test status
Simulation time 1422536431 ps
CPU time 17.36 seconds
Started Jul 21 07:01:28 PM PDT 24
Finished Jul 21 07:01:45 PM PDT 24
Peak memory 217152 kb
Host smart-6e4157bc-9efe-41c7-a4e5-30e24afbfecd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881387281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3881387281
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3490817825
Short name T733
Test name
Test status
Simulation time 282023507 ps
CPU time 3.89 seconds
Started Jul 21 07:01:28 PM PDT 24
Finished Jul 21 07:01:33 PM PDT 24
Peak memory 217160 kb
Host smart-a6e90475-2e82-4991-af3b-2ddaa27a25d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490817825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3490817825
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.64052313
Short name T840
Test name
Test status
Simulation time 7659004933 ps
CPU time 93.39 seconds
Started Jul 21 07:01:53 PM PDT 24
Finished Jul 21 07:03:28 PM PDT 24
Peak memory 283224 kb
Host smart-5bcaa4b1-cec0-489e-a439-e89c6c3c3d8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64052313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
state_failure.64052313
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3525319761
Short name T368
Test name
Test status
Simulation time 596481956 ps
CPU time 12.9 seconds
Started Jul 21 07:01:50 PM PDT 24
Finished Jul 21 07:02:04 PM PDT 24
Peak memory 245828 kb
Host smart-e8167ab7-2809-45d6-8842-a37e0cb48a1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525319761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3525319761
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1328402864
Short name T836
Test name
Test status
Simulation time 46514423 ps
CPU time 2.25 seconds
Started Jul 21 07:01:48 PM PDT 24
Finished Jul 21 07:01:52 PM PDT 24
Peak memory 217744 kb
Host smart-aa63959d-5121-4c9a-abd4-8a4644108c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328402864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1328402864
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2070208689
Short name T67
Test name
Test status
Simulation time 943411529 ps
CPU time 9.86 seconds
Started Jul 21 07:01:48 PM PDT 24
Finished Jul 21 07:01:59 PM PDT 24
Peak memory 217204 kb
Host smart-bf3ae836-85c4-4d3b-be01-62a0e4805cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070208689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2070208689
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1790854946
Short name T588
Test name
Test status
Simulation time 298997468 ps
CPU time 11.68 seconds
Started Jul 21 07:01:27 PM PDT 24
Finished Jul 21 07:01:39 PM PDT 24
Peak memory 218572 kb
Host smart-937bb583-3068-458a-a62e-7e989990b442
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790854946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1790854946
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3014594543
Short name T735
Test name
Test status
Simulation time 339019902 ps
CPU time 14.49 seconds
Started Jul 21 07:01:27 PM PDT 24
Finished Jul 21 07:01:42 PM PDT 24
Peak memory 225544 kb
Host smart-6d7d3a12-8665-407f-bc76-67ecf73bf34a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014594543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3014594543
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2576116731
Short name T288
Test name
Test status
Simulation time 1945713402 ps
CPU time 10.91 seconds
Started Jul 21 07:01:26 PM PDT 24
Finished Jul 21 07:01:37 PM PDT 24
Peak memory 225480 kb
Host smart-af4e3522-999c-4db8-b998-de413c3e32ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576116731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
576116731
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3660327672
Short name T469
Test name
Test status
Simulation time 1564898532 ps
CPU time 10.1 seconds
Started Jul 21 07:01:30 PM PDT 24
Finished Jul 21 07:01:41 PM PDT 24
Peak memory 217888 kb
Host smart-65a28bd6-cc1f-4fed-9b62-b979d7a60e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660327672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3660327672
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2706120032
Short name T285
Test name
Test status
Simulation time 183774459 ps
CPU time 2.28 seconds
Started Jul 21 07:01:39 PM PDT 24
Finished Jul 21 07:01:42 PM PDT 24
Peak memory 213608 kb
Host smart-ddb7cf90-17c5-4206-a8a5-c2454f010514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706120032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2706120032
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.4063597223
Short name T695
Test name
Test status
Simulation time 1012212861 ps
CPU time 22.41 seconds
Started Jul 21 07:01:36 PM PDT 24
Finished Jul 21 07:01:59 PM PDT 24
Peak memory 250616 kb
Host smart-50311d27-cef8-416f-9710-fa20aca5de0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063597223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.4063597223
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1439403417
Short name T375
Test name
Test status
Simulation time 45595387 ps
CPU time 7.71 seconds
Started Jul 21 07:01:38 PM PDT 24
Finished Jul 21 07:01:47 PM PDT 24
Peak memory 250580 kb
Host smart-6c8ecf26-6264-4137-8d89-b2752c9dc579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439403417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1439403417
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2349017873
Short name T693
Test name
Test status
Simulation time 15488363963 ps
CPU time 76.43 seconds
Started Jul 21 07:01:29 PM PDT 24
Finished Jul 21 07:02:45 PM PDT 24
Peak memory 225684 kb
Host smart-b5c4ad10-b4d2-45ba-972c-fe9977e7f889
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349017873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2349017873
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.527214715
Short name T170
Test name
Test status
Simulation time 23921370832 ps
CPU time 494.23 seconds
Started Jul 21 07:01:31 PM PDT 24
Finished Jul 21 07:09:46 PM PDT 24
Peak memory 332808 kb
Host smart-82957cae-d135-4b1a-b43a-3fb7ca4963c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=527214715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.527214715
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.247736814
Short name T432
Test name
Test status
Simulation time 17215441 ps
CPU time 0.96 seconds
Started Jul 21 07:01:42 PM PDT 24
Finished Jul 21 07:01:43 PM PDT 24
Peak memory 211436 kb
Host smart-c4b268d2-4e96-4718-b752-c6ce50cd8c2c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247736814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.247736814
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2380154815
Short name T233
Test name
Test status
Simulation time 29741387 ps
CPU time 1.02 seconds
Started Jul 21 07:01:47 PM PDT 24
Finished Jul 21 07:01:49 PM PDT 24
Peak memory 208448 kb
Host smart-4f9b21df-4b84-4842-b26d-69a5c39ed837
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380154815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2380154815
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1519646999
Short name T224
Test name
Test status
Simulation time 339771616 ps
CPU time 11.73 seconds
Started Jul 21 07:01:40 PM PDT 24
Finished Jul 21 07:01:53 PM PDT 24
Peak memory 217756 kb
Host smart-ee6aade5-527d-4ea8-9043-751305f7b6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519646999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1519646999
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.3142018889
Short name T24
Test name
Test status
Simulation time 631802084 ps
CPU time 9.88 seconds
Started Jul 21 07:01:42 PM PDT 24
Finished Jul 21 07:01:53 PM PDT 24
Peak memory 216948 kb
Host smart-d028dfd2-375a-4463-af01-db9dbb0c1c86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142018889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3142018889
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.4205815119
Short name T498
Test name
Test status
Simulation time 17253939389 ps
CPU time 58.59 seconds
Started Jul 21 07:01:28 PM PDT 24
Finished Jul 21 07:02:27 PM PDT 24
Peak memory 219376 kb
Host smart-bb010619-79a1-44a5-adb9-3f419c819e8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205815119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.4205815119
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.618874073
Short name T770
Test name
Test status
Simulation time 415340716 ps
CPU time 3.35 seconds
Started Jul 21 07:01:32 PM PDT 24
Finished Jul 21 07:01:35 PM PDT 24
Peak memory 217300 kb
Host smart-36fd7f35-cbc5-4c30-ae08-708bfbf96bc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618874073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.618874073
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2909608066
Short name T220
Test name
Test status
Simulation time 2705397113 ps
CPU time 11.56 seconds
Started Jul 21 07:01:45 PM PDT 24
Finished Jul 21 07:01:57 PM PDT 24
Peak memory 223380 kb
Host smart-f407c68a-b204-48e6-b1ea-026ec2c84741
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909608066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2909608066
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.225110729
Short name T489
Test name
Test status
Simulation time 16246689081 ps
CPU time 16.6 seconds
Started Jul 21 07:01:45 PM PDT 24
Finished Jul 21 07:02:02 PM PDT 24
Peak memory 217116 kb
Host smart-ddba75f1-26a6-49c0-a6f0-32a4250aed60
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225110729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_regwen_during_op.225110729
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.869182025
Short name T162
Test name
Test status
Simulation time 100100370 ps
CPU time 2.22 seconds
Started Jul 21 07:01:37 PM PDT 24
Finished Jul 21 07:01:40 PM PDT 24
Peak memory 217144 kb
Host smart-ae252546-d0b9-48ba-8657-f0e360d3e1c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869182025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.869182025
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1582940583
Short name T367
Test name
Test status
Simulation time 16530961661 ps
CPU time 35.3 seconds
Started Jul 21 07:01:43 PM PDT 24
Finished Jul 21 07:02:19 PM PDT 24
Peak memory 251096 kb
Host smart-3291226a-e816-42cf-a9f5-e8fe6487e282
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582940583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1582940583
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1331463683
Short name T443
Test name
Test status
Simulation time 581003341 ps
CPU time 13.54 seconds
Started Jul 21 07:01:51 PM PDT 24
Finished Jul 21 07:02:07 PM PDT 24
Peak memory 250100 kb
Host smart-ee1af069-6b26-4bf2-a717-ad259ac27ef5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331463683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1331463683
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1526012815
Short name T684
Test name
Test status
Simulation time 50150485 ps
CPU time 2.95 seconds
Started Jul 21 07:01:48 PM PDT 24
Finished Jul 21 07:01:53 PM PDT 24
Peak memory 217752 kb
Host smart-8d46ffcd-940f-4077-b3e3-b165c0859484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526012815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1526012815
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3415121337
Short name T802
Test name
Test status
Simulation time 544405632 ps
CPU time 18.36 seconds
Started Jul 21 07:01:51 PM PDT 24
Finished Jul 21 07:02:12 PM PDT 24
Peak memory 214412 kb
Host smart-f3e5ad71-ac54-4fa4-a01f-1542ae63cecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415121337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3415121337
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1027303896
Short name T617
Test name
Test status
Simulation time 405669004 ps
CPU time 12.26 seconds
Started Jul 21 07:01:41 PM PDT 24
Finished Jul 21 07:01:54 PM PDT 24
Peak memory 218504 kb
Host smart-b7476d94-4133-47de-b538-14d158c5fe7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027303896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1027303896
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.192258858
Short name T274
Test name
Test status
Simulation time 800928501 ps
CPU time 11.09 seconds
Started Jul 21 07:01:41 PM PDT 24
Finished Jul 21 07:01:53 PM PDT 24
Peak memory 217780 kb
Host smart-b62060c5-ba46-4be8-8a27-b72be73b11b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192258858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.192258858
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3979809186
Short name T568
Test name
Test status
Simulation time 273248018 ps
CPU time 11.61 seconds
Started Jul 21 07:01:34 PM PDT 24
Finished Jul 21 07:01:47 PM PDT 24
Peak memory 225556 kb
Host smart-c9e29e7a-f3c3-4b9a-b869-8bcb4971fdf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979809186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
979809186
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.441647908
Short name T702
Test name
Test status
Simulation time 546549677 ps
CPU time 11.5 seconds
Started Jul 21 07:01:51 PM PDT 24
Finished Jul 21 07:02:05 PM PDT 24
Peak memory 217900 kb
Host smart-d880ca96-79f5-45d2-81b3-eb5e3218a9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441647908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.441647908
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.239309077
Short name T89
Test name
Test status
Simulation time 208544075 ps
CPU time 3.13 seconds
Started Jul 21 07:01:26 PM PDT 24
Finished Jul 21 07:01:30 PM PDT 24
Peak memory 214440 kb
Host smart-3d369cb8-3750-4934-a04b-269ae73ec2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239309077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.239309077
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.4070926532
Short name T238
Test name
Test status
Simulation time 365761513 ps
CPU time 27.47 seconds
Started Jul 21 07:01:37 PM PDT 24
Finished Jul 21 07:02:05 PM PDT 24
Peak memory 247364 kb
Host smart-911e8979-bffc-495e-8f56-9a5e3064c2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070926532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.4070926532
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.832898775
Short name T527
Test name
Test status
Simulation time 319214840 ps
CPU time 5.88 seconds
Started Jul 21 07:01:36 PM PDT 24
Finished Jul 21 07:01:42 PM PDT 24
Peak memory 246556 kb
Host smart-6ed57e90-ba9f-432f-86a9-22480beb80eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832898775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.832898775
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.388040873
Short name T646
Test name
Test status
Simulation time 32891902896 ps
CPU time 277.33 seconds
Started Jul 21 07:01:27 PM PDT 24
Finished Jul 21 07:06:05 PM PDT 24
Peak memory 274508 kb
Host smart-02110eca-26f0-4677-bf7d-b6c7da935d4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388040873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.388040873
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.4114743402
Short name T35
Test name
Test status
Simulation time 36059587 ps
CPU time 0.89 seconds
Started Jul 21 07:01:30 PM PDT 24
Finished Jul 21 07:01:31 PM PDT 24
Peak memory 208648 kb
Host smart-82027f5b-c5fb-4263-b1d6-44fc91ec7bd8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114743402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.4114743402
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.658701227
Short name T620
Test name
Test status
Simulation time 31454526 ps
CPU time 1.06 seconds
Started Jul 21 07:01:50 PM PDT 24
Finished Jul 21 07:01:53 PM PDT 24
Peak memory 208488 kb
Host smart-1b3b749f-f44b-4892-bff8-9ff96d1019fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658701227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.658701227
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.929158182
Short name T571
Test name
Test status
Simulation time 925831294 ps
CPU time 12.3 seconds
Started Jul 21 07:01:34 PM PDT 24
Finished Jul 21 07:01:46 PM PDT 24
Peak memory 217904 kb
Host smart-68fd7e65-62a2-4e0d-96f5-8fb561b5e76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929158182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.929158182
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2005693672
Short name T8
Test name
Test status
Simulation time 2645915824 ps
CPU time 13.84 seconds
Started Jul 21 07:01:35 PM PDT 24
Finished Jul 21 07:01:49 PM PDT 24
Peak memory 217176 kb
Host smart-34332647-223b-4e46-bf61-4a35ddbbd083
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005693672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2005693672
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.4222596906
Short name T42
Test name
Test status
Simulation time 6281059055 ps
CPU time 22.44 seconds
Started Jul 21 07:01:51 PM PDT 24
Finished Jul 21 07:02:16 PM PDT 24
Peak memory 217876 kb
Host smart-c40072d2-0c2c-4c9c-9957-170dab3c9130
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222596906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.4222596906
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2478875473
Short name T714
Test name
Test status
Simulation time 1253849337 ps
CPU time 32.09 seconds
Started Jul 21 07:01:40 PM PDT 24
Finished Jul 21 07:02:13 PM PDT 24
Peak memory 217308 kb
Host smart-5b6579b2-2fab-44de-adbc-d0d2d8258b98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478875473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
478875473
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2436925867
Short name T784
Test name
Test status
Simulation time 1289460044 ps
CPU time 10.13 seconds
Started Jul 21 07:01:51 PM PDT 24
Finished Jul 21 07:02:03 PM PDT 24
Peak memory 222980 kb
Host smart-9504a54d-b480-44df-a201-d972f0be76e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436925867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2436925867
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.870792062
Short name T757
Test name
Test status
Simulation time 2138342496 ps
CPU time 15.32 seconds
Started Jul 21 07:01:36 PM PDT 24
Finished Jul 21 07:01:52 PM PDT 24
Peak memory 217184 kb
Host smart-88536862-510f-47da-b4b6-7e9b77b8e8ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870792062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.870792062
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1091745948
Short name T816
Test name
Test status
Simulation time 872988903 ps
CPU time 4.17 seconds
Started Jul 21 07:01:45 PM PDT 24
Finished Jul 21 07:01:49 PM PDT 24
Peak memory 217128 kb
Host smart-6f2954de-c625-4977-be18-5746f91ca25d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091745948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1091745948
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2907250470
Short name T611
Test name
Test status
Simulation time 1798996515 ps
CPU time 57 seconds
Started Jul 21 07:01:42 PM PDT 24
Finished Jul 21 07:02:40 PM PDT 24
Peak memory 275020 kb
Host smart-f8ca3555-9bfd-48e2-acad-e52b567749bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907250470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2907250470
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2713576544
Short name T222
Test name
Test status
Simulation time 355809322 ps
CPU time 10.15 seconds
Started Jul 21 07:01:30 PM PDT 24
Finished Jul 21 07:01:40 PM PDT 24
Peak memory 246044 kb
Host smart-0a211138-01d5-45cf-b5c1-1a8f549cd123
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713576544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2713576544
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.357368807
Short name T479
Test name
Test status
Simulation time 49081736 ps
CPU time 2.43 seconds
Started Jul 21 07:01:40 PM PDT 24
Finished Jul 21 07:01:43 PM PDT 24
Peak memory 217788 kb
Host smart-202022a2-4e18-4e6e-9692-bc866040d857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357368807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.357368807
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2759843294
Short name T698
Test name
Test status
Simulation time 227032750 ps
CPU time 14.72 seconds
Started Jul 21 07:01:50 PM PDT 24
Finished Jul 21 07:02:06 PM PDT 24
Peak memory 214208 kb
Host smart-48fc5022-fdbc-42c4-8a30-55dc6663580d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759843294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2759843294
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3202794492
Short name T219
Test name
Test status
Simulation time 1497440718 ps
CPU time 8.21 seconds
Started Jul 21 07:01:48 PM PDT 24
Finished Jul 21 07:01:57 PM PDT 24
Peak memory 217832 kb
Host smart-61fd8354-e72c-4f1c-b80f-6a6d0c0945b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202794492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3202794492
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2246755168
Short name T359
Test name
Test status
Simulation time 291651353 ps
CPU time 8.86 seconds
Started Jul 21 07:01:42 PM PDT 24
Finished Jul 21 07:01:51 PM PDT 24
Peak memory 225536 kb
Host smart-6e0089b7-9801-4535-85ae-7ecce8f22e33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246755168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
246755168
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2361015843
Short name T577
Test name
Test status
Simulation time 1810752564 ps
CPU time 11.15 seconds
Started Jul 21 07:01:41 PM PDT 24
Finished Jul 21 07:01:52 PM PDT 24
Peak memory 225604 kb
Host smart-219edba6-9f08-4e67-8113-3253d2a5e0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361015843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2361015843
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.3365516152
Short name T448
Test name
Test status
Simulation time 44050845 ps
CPU time 1.65 seconds
Started Jul 21 07:01:27 PM PDT 24
Finished Jul 21 07:01:29 PM PDT 24
Peak memory 213380 kb
Host smart-c4638ff1-9020-4b1d-a171-49cdc0a0d9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365516152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3365516152
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.997400198
Short name T385
Test name
Test status
Simulation time 2435405892 ps
CPU time 30.14 seconds
Started Jul 21 07:01:29 PM PDT 24
Finished Jul 21 07:01:59 PM PDT 24
Peak memory 250592 kb
Host smart-e620bad8-fb57-414f-b8db-7f9d0251a8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997400198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.997400198
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1044481241
Short name T392
Test name
Test status
Simulation time 84824241 ps
CPU time 3.77 seconds
Started Jul 21 07:01:41 PM PDT 24
Finished Jul 21 07:01:45 PM PDT 24
Peak memory 222460 kb
Host smart-29ead64f-1f17-4fa1-ba7a-83d7db05f3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044481241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1044481241
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.804809191
Short name T797
Test name
Test status
Simulation time 15325528 ps
CPU time 0.85 seconds
Started Jul 21 07:01:32 PM PDT 24
Finished Jul 21 07:01:33 PM PDT 24
Peak memory 208452 kb
Host smart-cb796f39-6118-4f31-bef1-3cd5a6457d6e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804809191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.804809191
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2408877877
Short name T507
Test name
Test status
Simulation time 29893601 ps
CPU time 0.88 seconds
Started Jul 21 07:01:52 PM PDT 24
Finished Jul 21 07:01:55 PM PDT 24
Peak memory 208364 kb
Host smart-697b2753-1ae1-4719-927e-bc4f2a734d33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408877877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2408877877
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3593110317
Short name T303
Test name
Test status
Simulation time 12376562 ps
CPU time 1.05 seconds
Started Jul 21 07:01:50 PM PDT 24
Finished Jul 21 07:01:52 PM PDT 24
Peak memory 208352 kb
Host smart-05410489-88b8-4b11-8ebf-9b5f7696face
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593110317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3593110317
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1743738353
Short name T618
Test name
Test status
Simulation time 402608339 ps
CPU time 16.52 seconds
Started Jul 21 07:01:41 PM PDT 24
Finished Jul 21 07:01:58 PM PDT 24
Peak memory 217796 kb
Host smart-bbc24a6e-73dc-414e-8106-d57a214092a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743738353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1743738353
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.4050634479
Short name T438
Test name
Test status
Simulation time 6877885624 ps
CPU time 12.35 seconds
Started Jul 21 07:01:52 PM PDT 24
Finished Jul 21 07:02:07 PM PDT 24
Peak memory 217248 kb
Host smart-9b1cd4bc-cb47-476d-826f-19396f72daec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050634479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.4050634479
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.3862675740
Short name T637
Test name
Test status
Simulation time 7614148940 ps
CPU time 56.06 seconds
Started Jul 21 07:01:53 PM PDT 24
Finished Jul 21 07:02:51 PM PDT 24
Peak memory 219312 kb
Host smart-83d61aeb-1819-41a8-8b38-82bed28b3a6a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862675740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.3862675740
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1398575006
Short name T221
Test name
Test status
Simulation time 289772820 ps
CPU time 2.63 seconds
Started Jul 21 07:01:58 PM PDT 24
Finished Jul 21 07:02:03 PM PDT 24
Peak memory 217208 kb
Host smart-9f8b001d-a0c9-443a-9795-d9051c0e084f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398575006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
398575006
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2764749481
Short name T664
Test name
Test status
Simulation time 1713508611 ps
CPU time 22.3 seconds
Started Jul 21 07:01:49 PM PDT 24
Finished Jul 21 07:02:12 PM PDT 24
Peak memory 217804 kb
Host smart-2d5cef8d-e6ff-4bf1-aa18-68e44523d58e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764749481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2764749481
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1981868068
Short name T557
Test name
Test status
Simulation time 1978079252 ps
CPU time 28.1 seconds
Started Jul 21 07:01:52 PM PDT 24
Finished Jul 21 07:02:22 PM PDT 24
Peak memory 217180 kb
Host smart-577e229e-9b9e-4694-bde9-10b3eb39f1e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981868068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1981868068
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2220720579
Short name T595
Test name
Test status
Simulation time 187469156 ps
CPU time 3.96 seconds
Started Jul 21 07:01:56 PM PDT 24
Finished Jul 21 07:02:02 PM PDT 24
Peak memory 217136 kb
Host smart-7f445ef0-481d-4064-8a8b-b6daace9284b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220720579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2220720579
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3350803484
Short name T688
Test name
Test status
Simulation time 6350659449 ps
CPU time 47.04 seconds
Started Jul 21 07:01:51 PM PDT 24
Finished Jul 21 07:02:41 PM PDT 24
Peak memory 275468 kb
Host smart-12aef67d-6705-4fd3-a8d7-ff768dbf262b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350803484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3350803484
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2982478267
Short name T268
Test name
Test status
Simulation time 521659420 ps
CPU time 13.34 seconds
Started Jul 21 07:01:35 PM PDT 24
Finished Jul 21 07:01:49 PM PDT 24
Peak memory 245628 kb
Host smart-d988b29f-8a9a-4299-b8fa-e39453fd4923
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982478267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2982478267
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2996875510
Short name T690
Test name
Test status
Simulation time 175672703 ps
CPU time 2.83 seconds
Started Jul 21 07:01:47 PM PDT 24
Finished Jul 21 07:01:51 PM PDT 24
Peak memory 221888 kb
Host smart-268bfe9b-cebe-47a7-b894-1b2b32f31661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996875510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2996875510
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2940381036
Short name T502
Test name
Test status
Simulation time 384590183 ps
CPU time 15.53 seconds
Started Jul 21 07:01:52 PM PDT 24
Finished Jul 21 07:02:10 PM PDT 24
Peak memory 217196 kb
Host smart-3d0d8001-bf2b-4088-800a-4380137d4b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940381036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2940381036
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.1492184486
Short name T512
Test name
Test status
Simulation time 681212959 ps
CPU time 9.83 seconds
Started Jul 21 07:02:01 PM PDT 24
Finished Jul 21 07:02:14 PM PDT 24
Peak memory 217948 kb
Host smart-2925c02c-ba58-4157-b0d1-9a4b5a2301ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492184486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1492184486
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3366726948
Short name T264
Test name
Test status
Simulation time 1448551789 ps
CPU time 12.64 seconds
Started Jul 21 07:01:45 PM PDT 24
Finished Jul 21 07:01:58 PM PDT 24
Peak memory 217856 kb
Host smart-b62d7b7f-1c05-4d85-9d17-ad774765699a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366726948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3366726948
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3966036715
Short name T176
Test name
Test status
Simulation time 908294936 ps
CPU time 7 seconds
Started Jul 21 07:01:49 PM PDT 24
Finished Jul 21 07:01:58 PM PDT 24
Peak memory 225420 kb
Host smart-a86a7b4c-ecf7-4f3a-88e3-17154cda67f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966036715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
966036715
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.4018407279
Short name T38
Test name
Test status
Simulation time 311844696 ps
CPU time 8.89 seconds
Started Jul 21 07:01:49 PM PDT 24
Finished Jul 21 07:01:59 PM PDT 24
Peak memory 217924 kb
Host smart-1d24f9a8-15f2-485c-a800-af3360577118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018407279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.4018407279
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2479429615
Short name T445
Test name
Test status
Simulation time 45112704 ps
CPU time 2.11 seconds
Started Jul 21 07:01:48 PM PDT 24
Finished Jul 21 07:01:52 PM PDT 24
Peak memory 213792 kb
Host smart-087bd308-33b3-4e14-966e-7e0967224e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479429615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2479429615
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3653638571
Short name T103
Test name
Test status
Simulation time 133542650 ps
CPU time 16.13 seconds
Started Jul 21 07:01:30 PM PDT 24
Finished Jul 21 07:01:47 PM PDT 24
Peak memory 250512 kb
Host smart-30541aea-3b2b-43dd-85c5-5e059f67f41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653638571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3653638571
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.195860271
Short name T712
Test name
Test status
Simulation time 69419836 ps
CPU time 3.9 seconds
Started Jul 21 07:01:33 PM PDT 24
Finished Jul 21 07:01:37 PM PDT 24
Peak memory 222252 kb
Host smart-bdf5b882-aa8c-406c-9ed0-da3f2c35fda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195860271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.195860271
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.43483315
Short name T719
Test name
Test status
Simulation time 9358620538 ps
CPU time 313.89 seconds
Started Jul 21 07:01:43 PM PDT 24
Finished Jul 21 07:06:58 PM PDT 24
Peak memory 388740 kb
Host smart-2c9d7636-dec5-4328-8aef-8840dfedfb74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43483315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.lc_ctrl_stress_all.43483315
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2737511870
Short name T545
Test name
Test status
Simulation time 37774313 ps
CPU time 1 seconds
Started Jul 21 07:01:33 PM PDT 24
Finished Jul 21 07:01:35 PM PDT 24
Peak memory 211384 kb
Host smart-7f8cbb07-ad9a-4191-9bb7-b37482730774
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737511870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2737511870
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.527291931
Short name T245
Test name
Test status
Simulation time 35187978 ps
CPU time 0.88 seconds
Started Jul 21 07:01:49 PM PDT 24
Finished Jul 21 07:01:51 PM PDT 24
Peak memory 208200 kb
Host smart-d709c30d-2a66-4840-b670-773bf97344a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527291931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.527291931
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.45427305
Short name T271
Test name
Test status
Simulation time 30565608 ps
CPU time 0.79 seconds
Started Jul 21 07:02:00 PM PDT 24
Finished Jul 21 07:02:03 PM PDT 24
Peak memory 208524 kb
Host smart-3752617b-777e-4dda-a366-b290d7cd5763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45427305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.45427305
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3868635299
Short name T549
Test name
Test status
Simulation time 287510193 ps
CPU time 12.13 seconds
Started Jul 21 07:01:47 PM PDT 24
Finished Jul 21 07:02:00 PM PDT 24
Peak memory 225584 kb
Host smart-a4a6c8c5-8834-4c67-aebc-475384ab6c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868635299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3868635299
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3400122635
Short name T389
Test name
Test status
Simulation time 1724778003 ps
CPU time 20.26 seconds
Started Jul 21 07:01:49 PM PDT 24
Finished Jul 21 07:02:11 PM PDT 24
Peak memory 216856 kb
Host smart-c48fc30a-e123-458b-9274-a3532a0f6adf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400122635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3400122635
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.34185562
Short name T466
Test name
Test status
Simulation time 9200114916 ps
CPU time 32.07 seconds
Started Jul 21 07:01:52 PM PDT 24
Finished Jul 21 07:02:27 PM PDT 24
Peak memory 218172 kb
Host smart-0b5419dc-7962-49bc-93f0-37a815cb65bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34185562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_erro
rs.34185562
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1514100608
Short name T420
Test name
Test status
Simulation time 4256657820 ps
CPU time 11.65 seconds
Started Jul 21 07:01:55 PM PDT 24
Finished Jul 21 07:02:09 PM PDT 24
Peak memory 217328 kb
Host smart-aa27b384-f8aa-487e-baf6-edfffe46c454
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514100608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
514100608
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.375832590
Short name T546
Test name
Test status
Simulation time 444484411 ps
CPU time 4.49 seconds
Started Jul 21 07:01:49 PM PDT 24
Finished Jul 21 07:01:55 PM PDT 24
Peak memory 217948 kb
Host smart-c1a4c850-c923-486b-9e6b-b25fdf4d8ee6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375832590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.375832590
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2639974997
Short name T774
Test name
Test status
Simulation time 774616609 ps
CPU time 22.84 seconds
Started Jul 21 07:01:58 PM PDT 24
Finished Jul 21 07:02:23 PM PDT 24
Peak memory 217104 kb
Host smart-64d9a7f7-88d7-4c9e-950e-9b75db941732
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639974997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2639974997
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1714472133
Short name T526
Test name
Test status
Simulation time 241395940 ps
CPU time 4.46 seconds
Started Jul 21 07:01:47 PM PDT 24
Finished Jul 21 07:01:52 PM PDT 24
Peak memory 217164 kb
Host smart-6e2d625b-8673-4586-9dcf-65a4ce8736bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714472133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1714472133
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.556436116
Short name T296
Test name
Test status
Simulation time 6025309950 ps
CPU time 55.61 seconds
Started Jul 21 07:01:49 PM PDT 24
Finished Jul 21 07:02:46 PM PDT 24
Peak memory 283396 kb
Host smart-f76a8a5d-e77e-480a-8fae-b5adb3c657f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556436116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.556436116
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.664080648
Short name T258
Test name
Test status
Simulation time 1718870041 ps
CPU time 19.05 seconds
Started Jul 21 07:01:53 PM PDT 24
Finished Jul 21 07:02:15 PM PDT 24
Peak memory 250560 kb
Host smart-84fc2945-9fdd-4357-94e7-d40ba5c7d2b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664080648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.664080648
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1318903625
Short name T775
Test name
Test status
Simulation time 86562370 ps
CPU time 4.07 seconds
Started Jul 21 07:01:59 PM PDT 24
Finished Jul 21 07:02:05 PM PDT 24
Peak memory 217836 kb
Host smart-40d72af1-9135-4a48-8dd9-183597e79d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318903625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1318903625
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2832677126
Short name T639
Test name
Test status
Simulation time 1516090898 ps
CPU time 13.87 seconds
Started Jul 21 07:01:59 PM PDT 24
Finished Jul 21 07:02:16 PM PDT 24
Peak memory 217224 kb
Host smart-2e2fcf26-99af-40f7-aeef-34de7a44fc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832677126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2832677126
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.457540458
Short name T175
Test name
Test status
Simulation time 726212805 ps
CPU time 11.58 seconds
Started Jul 21 07:01:54 PM PDT 24
Finished Jul 21 07:02:08 PM PDT 24
Peak memory 225588 kb
Host smart-88738da7-7885-4c9f-9f5d-5d426227fe1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457540458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.457540458
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.246686686
Short name T348
Test name
Test status
Simulation time 20235389308 ps
CPU time 24.39 seconds
Started Jul 21 07:01:50 PM PDT 24
Finished Jul 21 07:02:17 PM PDT 24
Peak memory 217868 kb
Host smart-729fc8d4-ca92-4c1b-b84f-988e7d4d5f54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246686686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.246686686
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3064801885
Short name T857
Test name
Test status
Simulation time 983438501 ps
CPU time 8.06 seconds
Started Jul 21 07:01:48 PM PDT 24
Finished Jul 21 07:01:58 PM PDT 24
Peak memory 225516 kb
Host smart-6b87a4d6-bae0-4216-b60e-1878f2359155
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064801885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
064801885
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.4276258037
Short name T320
Test name
Test status
Simulation time 1355779690 ps
CPU time 12.01 seconds
Started Jul 21 07:01:55 PM PDT 24
Finished Jul 21 07:02:09 PM PDT 24
Peak memory 217864 kb
Host smart-1aa4f46e-bb93-4068-ba92-7c0815c48aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276258037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.4276258037
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1905664821
Short name T672
Test name
Test status
Simulation time 70972593 ps
CPU time 1.58 seconds
Started Jul 21 07:01:45 PM PDT 24
Finished Jul 21 07:01:47 PM PDT 24
Peak memory 213476 kb
Host smart-a392a339-c633-4d94-bf2c-1de5022de540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905664821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1905664821
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1465560738
Short name T570
Test name
Test status
Simulation time 390423603 ps
CPU time 34.82 seconds
Started Jul 21 07:01:53 PM PDT 24
Finished Jul 21 07:02:30 PM PDT 24
Peak memory 250460 kb
Host smart-e7ae1500-6b31-41e3-9a1a-1c000dcc3111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465560738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1465560738
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3992264924
Short name T849
Test name
Test status
Simulation time 70947535 ps
CPU time 10.16 seconds
Started Jul 21 07:01:43 PM PDT 24
Finished Jul 21 07:01:54 PM PDT 24
Peak memory 250476 kb
Host smart-ba6c38de-eb8d-4d64-880a-a76af4f6d451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992264924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3992264924
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1871803095
Short name T558
Test name
Test status
Simulation time 6640154287 ps
CPU time 189.23 seconds
Started Jul 21 07:01:51 PM PDT 24
Finished Jul 21 07:05:03 PM PDT 24
Peak memory 272312 kb
Host smart-38384d14-1559-4966-95b8-ac4e00270a93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871803095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1871803095
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.3135141810
Short name T150
Test name
Test status
Simulation time 111794167223 ps
CPU time 575.75 seconds
Started Jul 21 07:01:51 PM PDT 24
Finished Jul 21 07:11:29 PM PDT 24
Peak memory 496512 kb
Host smart-35e44e9d-895a-4692-b2f3-9372a4d7b356
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3135141810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.3135141810
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.295872271
Short name T262
Test name
Test status
Simulation time 13163302 ps
CPU time 0.85 seconds
Started Jul 21 07:01:54 PM PDT 24
Finished Jul 21 07:01:57 PM PDT 24
Peak memory 207812 kb
Host smart-eef4222d-fcfe-48ee-97f5-df3008dc9927
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295872271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.295872271
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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