Summary for Variable clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
48980 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
1824 | 
1 | 
 | 
 | 
T4 | 
8 | 
 | 
T17 | 
2 | 
 | 
T19 | 
11 | 
Summary for Variable clk_byp_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
50256 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
87 | 
 | 
T3 | 
76 | 
| auto[1] | 
548 | 
1 | 
 | 
 | 
T2 | 
11 | 
 | 
T47 | 
15 | 
 | 
T48 | 
19 | 
Summary for Variable count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
49056 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
1748 | 
1 | 
 | 
 | 
T4 | 
8 | 
 | 
T15 | 
6 | 
 | 
T18 | 
24 | 
Summary for Variable count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
49065 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
1739 | 
1 | 
 | 
 | 
T4 | 
15 | 
 | 
T13 | 
1 | 
 | 
T15 | 
4 | 
Summary for Variable count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
49095 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
1709 | 
1 | 
 | 
 | 
T4 | 
11 | 
 | 
T15 | 
8 | 
 | 
T18 | 
24 | 
Summary for Variable err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
2 | 
0 | 
2 | 
100.00 | 
User Defined Bins for err_inj_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| err_inj | 
46212 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| no_err_inj | 
4592 | 
1 | 
 | 
 | 
T4 | 
46 | 
 | 
T5 | 
7 | 
 | 
T13 | 
7 | 
Summary for Variable flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
49031 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
1773 | 
1 | 
 | 
 | 
T4 | 
13 | 
 | 
T17 | 
5 | 
 | 
T19 | 
5 | 
Summary for Variable flash_rma_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
50246 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
76 | 
 | 
T3 | 
76 | 
| auto[1] | 
558 | 
1 | 
 | 
 | 
T2 | 
22 | 
 | 
T47 | 
18 | 
 | 
T48 | 
18 | 
Summary for Variable jtag_csr_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for jtag_csr_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
35941 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
14863 | 
1 | 
 | 
 | 
T4 | 
138 | 
 | 
T5 | 
7 | 
 | 
T16 | 
17 | 
Summary for Variable kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
49019 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
1785 | 
1 | 
 | 
 | 
T4 | 
5 | 
 | 
T13 | 
1 | 
 | 
T15 | 
8 | 
Summary for Variable lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
49026 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
1778 | 
1 | 
 | 
 | 
T4 | 
9 | 
 | 
T13 | 
1 | 
 | 
T15 | 
4 | 
Summary for Variable otp_lc_data_i_valid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
49032 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
1772 | 
1 | 
 | 
 | 
T4 | 
8 | 
 | 
T13 | 
1 | 
 | 
T15 | 
3 | 
Summary for Variable otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_partition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
48946 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
1858 | 
1 | 
 | 
 | 
T4 | 
10 | 
 | 
T17 | 
4 | 
 | 
T19 | 
13 | 
Summary for Variable otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_prog_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
48758 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
2046 | 
1 | 
 | 
 | 
T4 | 
28 | 
 | 
T67 | 
5 | 
 | 
T18 | 
19 | 
Summary for Variable otp_rma_token_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
50261 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
77 | 
 | 
T3 | 
76 | 
| auto[1] | 
543 | 
1 | 
 | 
 | 
T2 | 
21 | 
 | 
T47 | 
20 | 
 | 
T48 | 
12 | 
Summary for Variable otp_secrets_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
50216 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
74 | 
 | 
T3 | 
76 | 
| auto[1] | 
588 | 
1 | 
 | 
 | 
T2 | 
24 | 
 | 
T47 | 
15 | 
 | 
T48 | 
31 | 
Summary for Variable otp_test_tokens_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
50276 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
78 | 
 | 
T3 | 
76 | 
| auto[1] | 
528 | 
1 | 
 | 
 | 
T2 | 
20 | 
 | 
T47 | 
23 | 
 | 
T48 | 
16 | 
Summary for Variable post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for post_trans_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
47985 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
2819 | 
1 | 
 | 
 | 
T4 | 
25 | 
 | 
T13 | 
13 | 
 | 
T20 | 
36 | 
Summary for Variable security_escalation_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for security_escalation_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
47173 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T4 | 
255 | 
| auto[1] | 
3631 | 
1 | 
 | 
 | 
T3 | 
76 | 
 | 
T55 | 
65 | 
 | 
T35 | 
57 | 
Summary for Variable state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
49098 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
1706 | 
1 | 
 | 
 | 
T4 | 
16 | 
 | 
T13 | 
1 | 
 | 
T15 | 
3 | 
Summary for Variable state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
49073 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
1731 | 
1 | 
 | 
 | 
T4 | 
9 | 
 | 
T13 | 
1 | 
 | 
T15 | 
8 | 
Summary for Variable state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
49004 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
1800 | 
1 | 
 | 
 | 
T4 | 
13 | 
 | 
T15 | 
8 | 
 | 
T18 | 
23 | 
Summary for Variable token_invalid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_invalid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
49005 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
1799 | 
1 | 
 | 
 | 
T4 | 
8 | 
 | 
T17 | 
10 | 
 | 
T19 | 
13 | 
Summary for Variable token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mismatch_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
45259 | 
1 | 
 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
 | 
T4 | 
246 | 
| auto[1] | 
5545 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T4 | 
9 | 
 | 
T12 | 
62 | 
Summary for Variable token_mux_ctrl_redun_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
47149 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
3655 | 
1 | 
 | 
 | 
T54 | 
79 | 
 | 
T43 | 
64 | 
 | 
T34 | 
96 | 
Summary for Variable token_mux_digest_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
1 | 
1 | 
50.00  | 
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS | 
| [auto[1]] | 
0 | 
1 | 
1 | 
 | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
50804 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
Summary for Variable token_response_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_response_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
48980 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
1824 | 
1 | 
 | 
 | 
T4 | 
12 | 
 | 
T17 | 
4 | 
 | 
T19 | 
12 | 
Summary for Variable transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
48986 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
1818 | 
1 | 
 | 
 | 
T4 | 
12 | 
 | 
T17 | 
7 | 
 | 
T19 | 
15 | 
Summary for Variable transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
48898 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[1] | 
1906 | 
1 | 
 | 
 | 
T4 | 
15 | 
 | 
T17 | 
8 | 
 | 
T19 | 
11 | 
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
| post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
err_inj | 
44823 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
no_err_inj | 
3162 | 
1 | 
 | 
 | 
T4 | 
33 | 
 | 
T5 | 
7 | 
 | 
T16 | 
17 | 
| auto[1] | 
err_inj | 
1389 | 
1 | 
 | 
 | 
T4 | 
12 | 
 | 
T13 | 
6 | 
 | 
T20 | 
15 | 
| auto[1] | 
no_err_inj | 
1430 | 
1 | 
 | 
 | 
T4 | 
13 | 
 | 
T13 | 
7 | 
 | 
T20 | 
21 | 
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
| post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
46421 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
auto[1] | 
1564 | 
1 | 
 | 
 | 
T4 | 
8 | 
 | 
T15 | 
8 | 
 | 
T18 | 
19 | 
| auto[1] | 
auto[0] | 
2652 | 
1 | 
 | 
 | 
T4 | 
24 | 
 | 
T13 | 
12 | 
 | 
T20 | 
32 | 
| auto[1] | 
auto[1] | 
167 | 
1 | 
 | 
 | 
T4 | 
1 | 
 | 
T13 | 
1 | 
 | 
T20 | 
4 | 
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
| post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
46356 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
auto[1] | 
1629 | 
1 | 
 | 
 | 
T4 | 
7 | 
 | 
T15 | 
4 | 
 | 
T18 | 
21 | 
| auto[1] | 
auto[0] | 
2670 | 
1 | 
 | 
 | 
T4 | 
23 | 
 | 
T13 | 
12 | 
 | 
T20 | 
35 | 
| auto[1] | 
auto[1] | 
149 | 
1 | 
 | 
 | 
T4 | 
2 | 
 | 
T13 | 
1 | 
 | 
T20 | 
1 | 
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
| post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
46331 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
auto[1] | 
1654 | 
1 | 
 | 
 | 
T4 | 
12 | 
 | 
T15 | 
8 | 
 | 
T18 | 
23 | 
| auto[1] | 
auto[0] | 
2673 | 
1 | 
 | 
 | 
T4 | 
24 | 
 | 
T13 | 
13 | 
 | 
T20 | 
34 | 
| auto[1] | 
auto[1] | 
146 | 
1 | 
 | 
 | 
T4 | 
1 | 
 | 
T20 | 
2 | 
 | 
T83 | 
1 | 
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
| post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
46405 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
auto[1] | 
1580 | 
1 | 
 | 
 | 
T4 | 
15 | 
 | 
T15 | 
4 | 
 | 
T18 | 
21 | 
| auto[1] | 
auto[0] | 
2660 | 
1 | 
 | 
 | 
T4 | 
25 | 
 | 
T13 | 
12 | 
 | 
T20 | 
32 | 
| auto[1] | 
auto[1] | 
159 | 
1 | 
 | 
 | 
T13 | 
1 | 
 | 
T20 | 
4 | 
 | 
T38 | 
1 | 
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
| post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
46421 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
auto[1] | 
1564 | 
1 | 
 | 
 | 
T4 | 
9 | 
 | 
T15 | 
8 | 
 | 
T18 | 
24 | 
| auto[1] | 
auto[0] | 
2674 | 
1 | 
 | 
 | 
T4 | 
23 | 
 | 
T13 | 
13 | 
 | 
T20 | 
35 | 
| auto[1] | 
auto[1] | 
145 | 
1 | 
 | 
 | 
T4 | 
2 | 
 | 
T20 | 
1 | 
 | 
T83 | 
1 | 
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
| post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
46391 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
auto[1] | 
1594 | 
1 | 
 | 
 | 
T4 | 
7 | 
 | 
T15 | 
6 | 
 | 
T18 | 
24 | 
| auto[1] | 
auto[0] | 
2665 | 
1 | 
 | 
 | 
T4 | 
24 | 
 | 
T13 | 
13 | 
 | 
T20 | 
36 | 
| auto[1] | 
auto[1] | 
154 | 
1 | 
 | 
 | 
T4 | 
1 | 
 | 
T83 | 
1 | 
 | 
T49 | 
2 | 
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
| jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
34807 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
auto[1] | 
1134 | 
1 | 
 | 
 | 
T17 | 
2 | 
 | 
T20 | 
9 | 
 | 
T145 | 
9 | 
| auto[1] | 
auto[0] | 
14173 | 
1 | 
 | 
 | 
T4 | 
130 | 
 | 
T5 | 
7 | 
 | 
T16 | 
17 | 
| auto[1] | 
auto[1] | 
690 | 
1 | 
 | 
 | 
T4 | 
8 | 
 | 
T19 | 
11 | 
 | 
T21 | 
11 | 
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
| jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
34848 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
auto[1] | 
1093 | 
1 | 
 | 
 | 
T17 | 
5 | 
 | 
T20 | 
10 | 
 | 
T145 | 
13 | 
| auto[1] | 
auto[0] | 
14183 | 
1 | 
 | 
 | 
T4 | 
125 | 
 | 
T5 | 
7 | 
 | 
T16 | 
17 | 
| auto[1] | 
auto[1] | 
680 | 
1 | 
 | 
 | 
T4 | 
13 | 
 | 
T19 | 
5 | 
 | 
T21 | 
9 | 
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
| jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
34728 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
auto[1] | 
1213 | 
1 | 
 | 
 | 
T4 | 
12 | 
 | 
T67 | 
5 | 
 | 
T18 | 
19 | 
| auto[1] | 
auto[0] | 
14030 | 
1 | 
 | 
 | 
T4 | 
122 | 
 | 
T5 | 
7 | 
 | 
T16 | 
17 | 
| auto[1] | 
auto[1] | 
833 | 
1 | 
 | 
 | 
T4 | 
16 | 
 | 
T20 | 
26 | 
 | 
T224 | 
8 | 
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
| jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
34806 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
auto[1] | 
1135 | 
1 | 
 | 
 | 
T17 | 
4 | 
 | 
T20 | 
9 | 
 | 
T145 | 
14 | 
| auto[1] | 
auto[0] | 
14140 | 
1 | 
 | 
 | 
T4 | 
128 | 
 | 
T5 | 
7 | 
 | 
T16 | 
17 | 
| auto[1] | 
auto[1] | 
723 | 
1 | 
 | 
 | 
T4 | 
10 | 
 | 
T19 | 
13 | 
 | 
T21 | 
9 | 
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
| jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
31126 | 
1 | 
 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
 | 
T4 | 
117 | 
| auto[0] | 
auto[1] | 
4815 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T12 | 
62 | 
 | 
T17 | 
10 | 
| auto[1] | 
auto[0] | 
14133 | 
1 | 
 | 
 | 
T4 | 
129 | 
 | 
T5 | 
7 | 
 | 
T16 | 
17 | 
| auto[1] | 
auto[1] | 
730 | 
1 | 
 | 
 | 
T4 | 
9 | 
 | 
T19 | 
9 | 
 | 
T21 | 
11 | 
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
| jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
34890 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
auto[1] | 
1051 | 
1 | 
 | 
 | 
T4 | 
8 | 
 | 
T13 | 
1 | 
 | 
T15 | 
8 | 
| auto[1] | 
auto[0] | 
14183 | 
1 | 
 | 
 | 
T4 | 
137 | 
 | 
T5 | 
7 | 
 | 
T16 | 
17 | 
| auto[1] | 
auto[1] | 
680 | 
1 | 
 | 
 | 
T4 | 
1 | 
 | 
T18 | 
6 | 
 | 
T20 | 
4 | 
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
| jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
34936 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
auto[1] | 
1005 | 
1 | 
 | 
 | 
T4 | 
14 | 
 | 
T13 | 
1 | 
 | 
T15 | 
3 | 
| auto[1] | 
auto[0] | 
14162 | 
1 | 
 | 
 | 
T4 | 
136 | 
 | 
T5 | 
7 | 
 | 
T16 | 
17 | 
| auto[1] | 
auto[1] | 
701 | 
1 | 
 | 
 | 
T4 | 
2 | 
 | 
T18 | 
4 | 
 | 
T20 | 
6 | 
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
34917 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
auto[1] | 
1024 | 
1 | 
 | 
 | 
T4 | 
7 | 
 | 
T13 | 
1 | 
 | 
T15 | 
4 | 
| auto[1] | 
auto[0] | 
14109 | 
1 | 
 | 
 | 
T4 | 
136 | 
 | 
T5 | 
7 | 
 | 
T16 | 
17 | 
| auto[1] | 
auto[1] | 
754 | 
1 | 
 | 
 | 
T4 | 
2 | 
 | 
T18 | 
8 | 
 | 
T20 | 
12 | 
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
34880 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
auto[1] | 
1061 | 
1 | 
 | 
 | 
T4 | 
4 | 
 | 
T13 | 
1 | 
 | 
T15 | 
8 | 
| auto[1] | 
auto[0] | 
14139 | 
1 | 
 | 
 | 
T4 | 
137 | 
 | 
T5 | 
7 | 
 | 
T16 | 
17 | 
| auto[1] | 
auto[1] | 
724 | 
1 | 
 | 
 | 
T4 | 
1 | 
 | 
T18 | 
5 | 
 | 
T20 | 
8 | 
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
| jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
34942 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
auto[1] | 
999 | 
1 | 
 | 
 | 
T4 | 
15 | 
 | 
T13 | 
1 | 
 | 
T15 | 
4 | 
| auto[1] | 
auto[0] | 
14123 | 
1 | 
 | 
 | 
T4 | 
138 | 
 | 
T5 | 
7 | 
 | 
T16 | 
17 | 
| auto[1] | 
auto[1] | 
740 | 
1 | 
 | 
 | 
T18 | 
8 | 
 | 
T20 | 
4 | 
 | 
T38 | 
1 | 
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
| jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
34888 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
auto[1] | 
1053 | 
1 | 
 | 
 | 
T4 | 
7 | 
 | 
T15 | 
6 | 
 | 
T18 | 
18 | 
| auto[1] | 
auto[0] | 
14168 | 
1 | 
 | 
 | 
T4 | 
137 | 
 | 
T5 | 
7 | 
 | 
T16 | 
17 | 
| auto[1] | 
auto[1] | 
695 | 
1 | 
 | 
 | 
T4 | 
1 | 
 | 
T18 | 
6 | 
 | 
T20 | 
6 | 
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
| jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
34772 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
auto[1] | 
1169 | 
1 | 
 | 
 | 
T17 | 
8 | 
 | 
T20 | 
19 | 
 | 
T145 | 
12 | 
| auto[1] | 
auto[0] | 
14126 | 
1 | 
 | 
 | 
T4 | 
123 | 
 | 
T5 | 
7 | 
 | 
T16 | 
17 | 
| auto[1] | 
auto[1] | 
737 | 
1 | 
 | 
 | 
T4 | 
15 | 
 | 
T19 | 
11 | 
 | 
T21 | 
10 | 
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
| jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
34835 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
auto[1] | 
1106 | 
1 | 
 | 
 | 
T17 | 
7 | 
 | 
T20 | 
12 | 
 | 
T145 | 
12 | 
| auto[1] | 
auto[0] | 
14151 | 
1 | 
 | 
 | 
T4 | 
126 | 
 | 
T5 | 
7 | 
 | 
T16 | 
17 | 
| auto[1] | 
auto[1] | 
712 | 
1 | 
 | 
 | 
T4 | 
12 | 
 | 
T19 | 
15 | 
 | 
T21 | 
9 | 
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
| jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
34408 | 
1 | 
 | 
 | 
T1 | 
71 | 
 | 
T2 | 
98 | 
 | 
T3 | 
76 | 
| auto[0] | 
auto[1] | 
1533 | 
1 | 
 | 
 | 
T13 | 
13 | 
 | 
T20 | 
25 | 
 | 
T83 | 
15 | 
| auto[1] | 
auto[0] | 
13577 | 
1 | 
 | 
 | 
T4 | 
113 | 
 | 
T5 | 
7 | 
 | 
T16 | 
17 | 
| auto[1] | 
auto[1] | 
1286 | 
1 | 
 | 
 | 
T4 | 
25 | 
 | 
T20 | 
11 | 
 | 
T22 | 
14 |