Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97441407

1

T1

57015

T2

41564

T3

14775

auto[1]

1276278

1

T2

1782

T3

7645

T4

5138

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97411960

1

T1

57015

T2

41663

T3

14110

auto[1]

1305725

1

T2

1683

T3

8310

T4

5628

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6874881	1			T1	6271		T2	8836		T3	6860
auto[IdleSt]	20367297	1			T1	2453		T2	8878		T3	2241
auto[ClkMuxSt]	34117	1			T1	71		T2	74		T3	69
auto[CntIncrSt]	33860	1			T1	71		T2	74		T3	69
auto[CntProgSt]	1495148	1			T1	142		T2	280		T3	803
auto[TransCheckSt]	26459	1			T1	71		T2	63		T3	34
auto[TokenHashSt]	39607804	1			T1	37247		T2	1931		T3	272
auto[FlashRmaSt]	33451	1			T2	148		T3	23		T4	137
auto[TokenCheck0St]	11945	1			T2	59		T3	19		T4	69
auto[TokenCheck1St]	8928	1			T2	38		T3	18		T4	58
auto[TransProgSt]	391082	1			T2	153		T3	58		T4	112
auto[PostTransSt]	12639946	1			T1	10689		T2	12785		T3	3
auto[ScrapSt]	144790	1			T3	9		T5	618		T42	71
auto[EscalateSt]	6328683	1			T2	5189		T3	11942		T4	30963
auto[InvalidSt]	10717434	1			T2	4838		T4	19992		T13	1126

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1860	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10717434	1			T2	4838		T4	19992		T13	1126
EscalateSt	6328683	1			T2	5189		T3	11942		T4	30963
ScrapSt	144790	1			T3	9		T5	618		T42	71
PostTransSt	12639946	1			T1	10689		T2	12785		T3	3
TransProgSt	391082	1			T2	153		T3	58		T4	112
TokenCheck1St	8928	1			T2	38		T3	18		T4	58
TokenCheck0St	11945	1			T2	59		T3	19		T4	69
FlashRmaSt	33451	1			T2	148		T3	23		T4	137
TokenHashSt	39607804	1			T1	37247		T2	1931		T3	272
TransCheckSt	26459	1			T1	71		T2	63		T3	34
CntProgSt	1495148	1			T1	142		T2	280		T3	803
CntIncrSt	33860	1			T1	71		T2	74		T3	69
ClkMuxSt	34117	1			T1	71		T2	74		T3	69
IdleSt	20367297	1			T1	2453		T2	8878		T3	2241
ResetSt	6874881	1			T1	6271		T2	8836		T3	6860
arcs[ResetSt=>IdleSt]	51200	1			T1	72		T2	99		T3	73
arcs[IdleSt=>ScrapSt]	263	1			T3	3		T5	1		T42	2
arcs[IdleSt=>ClkMuxSt]	33924	1			T1	71		T2	74		T3	69
arcs[ClkMuxSt=>CntIncrSt]	33860	1			T1	71		T2	74		T3	69
arcs[CntIncrSt=>PostTransSt]	1819	1			T4	12		T17	7		T19	15
arcs[CntIncrSt=>CntProgSt]	31980	1			T1	71		T2	74		T3	68
arcs[CntProgSt=>PostTransSt]	4393	1			T2	11		T4	34		T17	2
arcs[CntProgSt=>TransCheckSt]	26459	1			T1	71		T2	63		T3	34
arcs[TransCheckSt=>PostTransSt]	3737	1			T4	15		T17	8		T19	11
arcs[TransCheckSt=>TokenHashSt]	22615	1			T1	71		T2	63		T3	33
arcs[TokenHashSt=>PostTransSt]	9934	1			T1	71		T2	4		T4	29
arcs[TokenHashSt=>FlashRmaSt]	12024	1			T2	59		T3	21		T4	69
arcs[FlashRmaSt=>TokenCheck0St]	11945	1			T2	59		T3	19		T4	69
arcs[TokenCheck0St=>PostTransSt]	2986	1			T2	21		T4	11		T17	4
arcs[TokenCheck0St=>TokenCheck1St]	8928	1			T2	38		T3	18		T4	58
arcs[TokenCheck1St=>PostTransSt]	619	1			T4	2		T17	1		T19	1
arcs[TransProgSt=>PostTransSt]	7450	1			T2	38		T3	1		T4	56
arcs[IdleSt=>EscalateSt]	164	1			T55	6		T57	9		T58	7
arcs[ClkMuxSt=>EscalateSt]	64	1			T55	2		T37	2		T56	3
arcs[CntIncrSt=>EscalateSt]	61	1			T3	1		T55	3		T37	1
arcs[CntProgSt=>EscalateSt]	1128	1			T3	34		T55	25		T35	29
arcs[TransCheckSt=>EscalateSt]	107	1			T3	1		T35	1		T37	4
arcs[TokenHashSt=>EscalateSt]	657	1			T3	12		T4	2		T55	2
arcs[FlashRmaSt=>EscalateSt]	79	1			T3	2		T35	1		T37	4
arcs[TokenCheck0St=>EscalateSt]	31	1			T3	1		T62	1		T63	1
arcs[TokenCheck1St=>EscalateSt]	131	1			T3	3		T55	2		T35	3
arcs[TransProgSt=>EscalateSt]	728	1			T3	14		T55	20		T35	12
arcs[PostTransSt=>EscalateSt]	4630	1			T2	11		T3	1		T4	34
arcs[InvalidSt=>EscalateSt]	12793	1			T2	24		T4	73		T13	5

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6874735	1			T1	6271		T2	8836		T3	6857
auto[0]	auto[IdleSt]	20367197	1			T1	2453		T2	8878		T3	2241
auto[0]	auto[ClkMuxSt]	34076	1			T1	71		T2	74		T3	69
auto[0]	auto[CntIncrSt]	33823	1			T1	71		T2	74		T3	69
auto[0]	auto[CntProgSt]	1494401	1			T1	142		T2	280		T3	780
auto[0]	auto[TransCheckSt]	26392	1			T1	71		T2	63		T3	34
auto[0]	auto[TokenHashSt]	39607351	1			T1	37247		T2	1931		T3	266
auto[0]	auto[FlashRmaSt]	33400	1			T2	148		T3	21		T4	137
auto[0]	auto[TokenCheck0St]	11927	1			T2	59		T3	19		T4	69
auto[0]	auto[TokenCheck1St]	8843	1			T2	38		T3	16		T4	58
auto[0]	auto[TransProgSt]	390596	1			T2	153		T3	48		T4	112
auto[0]	auto[PostTransSt]	12637636	1			T1	10689		T2	12778		T3	2
auto[0]	auto[ScrapSt]	144760	1			T3	6		T5	618		T42	71
auto[0]	auto[EscalateSt]	5063286	1			T2	3425		T3	4347		T4	25877
auto[0]	auto[InvalidSt]	10711124	1			T2	4827		T4	19956		T13	1121
auto[1]	auto[ResetSt]	146	1			T3	3		T35	5		T37	1
auto[1]	auto[IdleSt]	100	1			T55	5		T57	5		T58	6
auto[1]	auto[ClkMuxSt]	41	1			T55	1		T37	1		T56	2
auto[1]	auto[CntIncrSt]	37	1			T55	2		T37	1		T57	1
auto[1]	auto[CntProgSt]	747	1			T3	23		T55	17		T35	18
auto[1]	auto[TransCheckSt]	67	1			T37	3		T56	4		T57	4
auto[1]	auto[TokenHashSt]	453	1			T3	6		T4	1		T55	2
auto[1]	auto[FlashRmaSt]	51	1			T3	2		T35	1		T37	2
auto[1]	auto[TokenCheck0St]	18	1			T63	1		T162	1		T165	1
auto[1]	auto[TokenCheck1St]	85	1			T3	2		T55	1		T35	3
auto[1]	auto[TransProgSt]	486	1			T3	10		T55	14		T35	5
auto[1]	auto[PostTransSt]	2310	1			T2	7		T3	1		T4	15
auto[1]	auto[ScrapSt]	30	1			T3	3		T55	1		T35	1
auto[1]	auto[EscalateSt]	1265397	1			T2	1764		T3	7595		T4	5086
auto[1]	auto[InvalidSt]	6310	1			T2	11		T4	36		T13	5

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6874727	1			T1	6271		T2	8836		T3	6859
auto[0]	auto[IdleSt]	20367186	1			T1	2453		T2	8878		T3	2241
auto[0]	auto[ClkMuxSt]	34075	1			T1	71		T2	74		T3	69
auto[0]	auto[CntIncrSt]	33822	1			T1	71		T2	74		T3	68
auto[0]	auto[CntProgSt]	1494379	1			T1	142		T2	280		T3	779
auto[0]	auto[TransCheckSt]	26389	1			T1	71		T2	63		T3	33
auto[0]	auto[TokenHashSt]	39607381	1			T1	37247		T2	1931		T3	264
auto[0]	auto[FlashRmaSt]	33397	1			T2	148		T3	23		T4	137
auto[0]	auto[TokenCheck0St]	11923	1			T2	59		T3	18		T4	69
auto[0]	auto[TokenCheck1St]	8839	1			T2	38		T3	16		T4	58
auto[0]	auto[TransProgSt]	390599	1			T2	153		T3	46		T4	112
auto[0]	auto[PostTransSt]	12637545	1			T1	10689		T2	12781		T3	2
auto[0]	auto[ScrapSt]	144757	1			T3	8		T5	618		T42	71
auto[0]	auto[EscalateSt]	5034130	1			T2	3523		T3	3684		T4	25392
auto[0]	auto[InvalidSt]	10710951	1			T2	4825		T4	19955		T13	1126
auto[1]	auto[ResetSt]	154	1			T3	1		T55	1		T35	4
auto[1]	auto[IdleSt]	111	1			T55	5		T57	4		T58	2
auto[1]	auto[ClkMuxSt]	42	1			T55	1		T37	2		T56	3
auto[1]	auto[CntIncrSt]	38	1			T3	1		T55	3		T56	1
auto[1]	auto[CntProgSt]	769	1			T3	24		T55	18		T35	22
auto[1]	auto[TransCheckSt]	70	1			T3	1		T35	1		T37	2
auto[1]	auto[TokenHashSt]	423	1			T3	8		T4	1		T35	2
auto[1]	auto[FlashRmaSt]	54	1			T35	1		T37	4		T56	1
auto[1]	auto[TokenCheck0St]	22	1			T3	1		T62	1		T63	1
auto[1]	auto[TokenCheck1St]	89	1			T3	2		T55	1		T35	2
auto[1]	auto[TransProgSt]	483	1			T3	12		T55	16		T35	8
auto[1]	auto[PostTransSt]	2401	1			T2	4		T3	1		T4	19
auto[1]	auto[ScrapSt]	33	1			T3	1		T55	1		T35	1
auto[1]	auto[EscalateSt]	1294553	1			T2	1666		T3	8258		T4	5571
auto[1]	auto[InvalidSt]	6483	1			T2	13		T4	37		T15	24