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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.14 97.99 95.41 93.40 100.00 98.55 98.51 96.11


Total test records in report: 987
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T812 /workspace/coverage/default/28.lc_ctrl_state_failure.159053566 Jul 22 04:45:56 PM PDT 24 Jul 22 04:46:26 PM PDT 24 2620663430 ps
T813 /workspace/coverage/default/31.lc_ctrl_state_post_trans.707271011 Jul 22 04:46:16 PM PDT 24 Jul 22 04:46:28 PM PDT 24 370886920 ps
T814 /workspace/coverage/default/12.lc_ctrl_prog_failure.1115670542 Jul 22 04:44:46 PM PDT 24 Jul 22 04:44:51 PM PDT 24 101530899 ps
T815 /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1152384132 Jul 22 04:47:12 PM PDT 24 Jul 22 04:47:14 PM PDT 24 129022268 ps
T816 /workspace/coverage/default/31.lc_ctrl_errors.3590448237 Jul 22 04:46:16 PM PDT 24 Jul 22 04:46:30 PM PDT 24 331818110 ps
T817 /workspace/coverage/default/22.lc_ctrl_prog_failure.3854925282 Jul 22 04:48:00 PM PDT 24 Jul 22 04:48:03 PM PDT 24 257256434 ps
T818 /workspace/coverage/default/0.lc_ctrl_stress_all.3368330815 Jul 22 04:43:17 PM PDT 24 Jul 22 04:46:36 PM PDT 24 14613091999 ps
T819 /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.971681316 Jul 22 04:43:53 PM PDT 24 Jul 22 04:43:55 PM PDT 24 42322846 ps
T820 /workspace/coverage/default/20.lc_ctrl_sec_token_mux.902151633 Jul 22 04:45:29 PM PDT 24 Jul 22 04:45:38 PM PDT 24 171350362 ps
T821 /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.645241291 Jul 22 04:43:35 PM PDT 24 Jul 22 04:43:36 PM PDT 24 22748292 ps
T822 /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1186291851 Jul 22 04:44:00 PM PDT 24 Jul 22 04:44:13 PM PDT 24 417061050 ps
T823 /workspace/coverage/default/18.lc_ctrl_jtag_smoke.906214341 Jul 22 04:45:12 PM PDT 24 Jul 22 04:45:16 PM PDT 24 786806952 ps
T824 /workspace/coverage/default/18.lc_ctrl_state_failure.2557250068 Jul 22 04:45:12 PM PDT 24 Jul 22 04:45:41 PM PDT 24 1158221705 ps
T825 /workspace/coverage/default/40.lc_ctrl_smoke.3430200158 Jul 22 04:46:55 PM PDT 24 Jul 22 04:46:59 PM PDT 24 1081425949 ps
T826 /workspace/coverage/default/17.lc_ctrl_errors.1095401669 Jul 22 04:45:10 PM PDT 24 Jul 22 04:45:24 PM PDT 24 556512075 ps
T827 /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3264463921 Jul 22 04:45:13 PM PDT 24 Jul 22 04:45:24 PM PDT 24 490053841 ps
T828 /workspace/coverage/default/33.lc_ctrl_state_failure.3874322885 Jul 22 04:46:17 PM PDT 24 Jul 22 04:46:43 PM PDT 24 500131867 ps
T829 /workspace/coverage/default/23.lc_ctrl_jtag_access.4142659629 Jul 22 04:48:00 PM PDT 24 Jul 22 04:48:07 PM PDT 24 3977650476 ps
T830 /workspace/coverage/default/23.lc_ctrl_errors.1475501194 Jul 22 04:45:28 PM PDT 24 Jul 22 04:45:43 PM PDT 24 413471921 ps
T831 /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2635356845 Jul 22 04:44:40 PM PDT 24 Jul 22 04:44:56 PM PDT 24 683374703 ps
T832 /workspace/coverage/default/36.lc_ctrl_security_escalation.3053459174 Jul 22 04:48:29 PM PDT 24 Jul 22 04:48:41 PM PDT 24 574491755 ps
T833 /workspace/coverage/default/47.lc_ctrl_state_failure.1330889486 Jul 22 04:47:30 PM PDT 24 Jul 22 04:48:03 PM PDT 24 306155522 ps
T834 /workspace/coverage/default/7.lc_ctrl_alert_test.3378219502 Jul 22 04:44:00 PM PDT 24 Jul 22 04:44:02 PM PDT 24 59834348 ps
T835 /workspace/coverage/default/37.lc_ctrl_alert_test.749549450 Jul 22 04:46:45 PM PDT 24 Jul 22 04:46:47 PM PDT 24 102853031 ps
T836 /workspace/coverage/default/25.lc_ctrl_alert_test.3874434490 Jul 22 04:45:46 PM PDT 24 Jul 22 04:45:48 PM PDT 24 119889181 ps
T837 /workspace/coverage/default/28.lc_ctrl_alert_test.895093843 Jul 22 04:46:06 PM PDT 24 Jul 22 04:46:07 PM PDT 24 29749688 ps
T838 /workspace/coverage/default/13.lc_ctrl_prog_failure.3002630546 Jul 22 04:44:39 PM PDT 24 Jul 22 04:44:44 PM PDT 24 810315664 ps
T839 /workspace/coverage/default/27.lc_ctrl_state_post_trans.520010518 Jul 22 04:47:05 PM PDT 24 Jul 22 04:47:12 PM PDT 24 178114632 ps
T840 /workspace/coverage/default/31.lc_ctrl_state_failure.1571512100 Jul 22 04:46:19 PM PDT 24 Jul 22 04:46:49 PM PDT 24 601356208 ps
T841 /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.539341072 Jul 22 04:43:23 PM PDT 24 Jul 22 04:43:25 PM PDT 24 66753536 ps
T842 /workspace/coverage/default/17.lc_ctrl_stress_all.695625495 Jul 22 04:45:12 PM PDT 24 Jul 22 04:46:20 PM PDT 24 4162995316 ps
T843 /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3004287452 Jul 22 04:44:22 PM PDT 24 Jul 22 04:44:24 PM PDT 24 10353633 ps
T844 /workspace/coverage/default/15.lc_ctrl_smoke.1124785875 Jul 22 04:44:49 PM PDT 24 Jul 22 04:44:52 PM PDT 24 76379898 ps
T845 /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.342503339 Jul 22 04:43:18 PM PDT 24 Jul 22 04:43:46 PM PDT 24 2029108152 ps
T846 /workspace/coverage/default/29.lc_ctrl_stress_all.759620017 Jul 22 04:46:06 PM PDT 24 Jul 22 04:49:30 PM PDT 24 55537443030 ps
T847 /workspace/coverage/default/2.lc_ctrl_smoke.2689667725 Jul 22 04:43:18 PM PDT 24 Jul 22 04:43:21 PM PDT 24 102566522 ps
T848 /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3859619313 Jul 22 04:47:39 PM PDT 24 Jul 22 04:47:50 PM PDT 24 843472875 ps
T849 /workspace/coverage/default/34.lc_ctrl_state_failure.3015779164 Jul 22 04:47:40 PM PDT 24 Jul 22 04:48:02 PM PDT 24 610849469 ps
T850 /workspace/coverage/default/21.lc_ctrl_state_failure.2869012252 Jul 22 04:45:24 PM PDT 24 Jul 22 04:46:00 PM PDT 24 329744068 ps
T851 /workspace/coverage/default/21.lc_ctrl_prog_failure.1989113771 Jul 22 04:45:26 PM PDT 24 Jul 22 04:45:29 PM PDT 24 82475944 ps
T852 /workspace/coverage/default/0.lc_ctrl_prog_failure.2775946413 Jul 22 04:43:55 PM PDT 24 Jul 22 04:44:00 PM PDT 24 66635099 ps
T853 /workspace/coverage/default/44.lc_ctrl_prog_failure.173861386 Jul 22 04:47:15 PM PDT 24 Jul 22 04:47:20 PM PDT 24 548089496 ps
T854 /workspace/coverage/default/20.lc_ctrl_alert_test.3287419188 Jul 22 04:45:23 PM PDT 24 Jul 22 04:45:24 PM PDT 24 113688745 ps
T855 /workspace/coverage/default/3.lc_ctrl_smoke.2322634109 Jul 22 04:43:29 PM PDT 24 Jul 22 04:43:31 PM PDT 24 24452257 ps
T856 /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1832026184 Jul 22 04:44:47 PM PDT 24 Jul 22 04:44:57 PM PDT 24 1030541759 ps
T857 /workspace/coverage/default/12.lc_ctrl_errors.260290117 Jul 22 04:44:45 PM PDT 24 Jul 22 04:44:59 PM PDT 24 810187633 ps
T858 /workspace/coverage/default/9.lc_ctrl_smoke.3010578004 Jul 22 04:44:11 PM PDT 24 Jul 22 04:44:13 PM PDT 24 18193449 ps
T859 /workspace/coverage/default/41.lc_ctrl_stress_all.2754502197 Jul 22 04:47:01 PM PDT 24 Jul 22 04:49:42 PM PDT 24 7723030061 ps
T860 /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2164922737 Jul 22 04:44:12 PM PDT 24 Jul 22 04:44:24 PM PDT 24 2347432480 ps
T861 /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.511937686 Jul 22 04:43:40 PM PDT 24 Jul 22 04:43:56 PM PDT 24 1349465845 ps
T82 /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2062218553 Jul 22 04:43:26 PM PDT 24 Jul 22 04:43:46 PM PDT 24 1127598026 ps
T862 /workspace/coverage/default/9.lc_ctrl_state_failure.2769794632 Jul 22 04:44:13 PM PDT 24 Jul 22 04:44:30 PM PDT 24 1044606760 ps
T116 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.761006225 Jul 22 06:20:01 PM PDT 24 Jul 22 06:20:03 PM PDT 24 55552002 ps
T137 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3725188976 Jul 22 06:19:20 PM PDT 24 Jul 22 06:19:24 PM PDT 24 53662868 ps
T109 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3936250077 Jul 22 06:19:17 PM PDT 24 Jul 22 06:19:20 PM PDT 24 211583400 ps
T101 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2166884697 Jul 22 06:19:23 PM PDT 24 Jul 22 06:19:27 PM PDT 24 174812718 ps
T133 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3490175871 Jul 22 06:19:33 PM PDT 24 Jul 22 06:19:35 PM PDT 24 74620758 ps
T102 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3842801514 Jul 22 06:19:21 PM PDT 24 Jul 22 06:19:26 PM PDT 24 65594876 ps
T110 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1604080607 Jul 22 06:19:41 PM PDT 24 Jul 22 06:19:43 PM PDT 24 27667134 ps
T103 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1849617875 Jul 22 06:20:03 PM PDT 24 Jul 22 06:20:06 PM PDT 24 56934174 ps
T149 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.85974969 Jul 22 06:19:40 PM PDT 24 Jul 22 06:19:42 PM PDT 24 42105269 ps
T105 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.752464198 Jul 22 06:19:54 PM PDT 24 Jul 22 06:19:57 PM PDT 24 46510325 ps
T108 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3806276950 Jul 22 06:19:53 PM PDT 24 Jul 22 06:19:56 PM PDT 24 87832221 ps
T122 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2480137707 Jul 22 06:19:33 PM PDT 24 Jul 22 06:19:36 PM PDT 24 90198098 ps
T106 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2020552225 Jul 22 06:19:46 PM PDT 24 Jul 22 06:19:49 PM PDT 24 78019171 ps
T863 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2456472700 Jul 22 06:19:28 PM PDT 24 Jul 22 06:19:30 PM PDT 24 51512067 ps
T210 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1492477103 Jul 22 06:20:08 PM PDT 24 Jul 22 06:20:11 PM PDT 24 16818902 ps
T107 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.533408886 Jul 22 06:19:42 PM PDT 24 Jul 22 06:19:45 PM PDT 24 222996901 ps
T864 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3435255883 Jul 22 06:19:32 PM PDT 24 Jul 22 06:19:35 PM PDT 24 66798366 ps
T865 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3499373839 Jul 22 06:20:07 PM PDT 24 Jul 22 06:20:10 PM PDT 24 28602689 ps
T211 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.939241494 Jul 22 06:19:44 PM PDT 24 Jul 22 06:19:46 PM PDT 24 72739454 ps
T866 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.719652874 Jul 22 06:20:07 PM PDT 24 Jul 22 06:20:10 PM PDT 24 331508872 ps
T212 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.4099532252 Jul 22 06:19:43 PM PDT 24 Jul 22 06:19:45 PM PDT 24 36959853 ps
T117 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1067222738 Jul 22 06:19:31 PM PDT 24 Jul 22 06:19:34 PM PDT 24 107773424 ps
T213 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2489176354 Jul 22 06:20:03 PM PDT 24 Jul 22 06:20:05 PM PDT 24 42145729 ps
T123 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1230842921 Jul 22 06:19:40 PM PDT 24 Jul 22 06:19:45 PM PDT 24 144152374 ps
T867 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1267133411 Jul 22 06:19:43 PM PDT 24 Jul 22 06:19:45 PM PDT 24 50445637 ps
T219 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4025119591 Jul 22 06:19:23 PM PDT 24 Jul 22 06:19:32 PM PDT 24 1201993671 ps
T134 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.410626215 Jul 22 06:20:02 PM PDT 24 Jul 22 06:20:04 PM PDT 24 151097685 ps
T111 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2594107820 Jul 22 06:19:41 PM PDT 24 Jul 22 06:19:45 PM PDT 24 40544127 ps
T121 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.219055769 Jul 22 06:19:40 PM PDT 24 Jul 22 06:19:44 PM PDT 24 261229334 ps
T868 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2783360155 Jul 22 06:19:17 PM PDT 24 Jul 22 06:19:20 PM PDT 24 97399002 ps
T150 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4133797168 Jul 22 06:19:31 PM PDT 24 Jul 22 06:19:33 PM PDT 24 19058399 ps
T214 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3668967683 Jul 22 06:19:21 PM PDT 24 Jul 22 06:19:24 PM PDT 24 112076604 ps
T198 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2866828948 Jul 22 06:19:30 PM PDT 24 Jul 22 06:19:32 PM PDT 24 24425081 ps
T135 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.508146429 Jul 22 06:19:13 PM PDT 24 Jul 22 06:19:32 PM PDT 24 7789938457 ps
T112 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1338627925 Jul 22 06:19:17 PM PDT 24 Jul 22 06:19:23 PM PDT 24 563378993 ps
T113 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3489842441 Jul 22 06:19:40 PM PDT 24 Jul 22 06:19:43 PM PDT 24 98970168 ps
T869 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1314407300 Jul 22 06:20:07 PM PDT 24 Jul 22 06:20:12 PM PDT 24 832627341 ps
T151 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2802035030 Jul 22 06:19:27 PM PDT 24 Jul 22 06:19:28 PM PDT 24 39816792 ps
T870 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.476333550 Jul 22 06:19:47 PM PDT 24 Jul 22 06:19:49 PM PDT 24 35100044 ps
T125 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3536864319 Jul 22 06:19:41 PM PDT 24 Jul 22 06:19:46 PM PDT 24 813829589 ps
T871 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.43752994 Jul 22 06:19:32 PM PDT 24 Jul 22 06:19:35 PM PDT 24 95266074 ps
T119 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1719013730 Jul 22 06:20:06 PM PDT 24 Jul 22 06:20:11 PM PDT 24 346381516 ps
T215 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2423065975 Jul 22 06:19:20 PM PDT 24 Jul 22 06:19:24 PM PDT 24 92867409 ps
T216 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2706089699 Jul 22 06:19:20 PM PDT 24 Jul 22 06:19:24 PM PDT 24 99265790 ps
T872 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2358377334 Jul 22 06:20:09 PM PDT 24 Jul 22 06:20:15 PM PDT 24 430812093 ps
T873 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.4094489989 Jul 22 06:19:12 PM PDT 24 Jul 22 06:19:14 PM PDT 24 44289886 ps
T874 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1523196422 Jul 22 06:19:22 PM PDT 24 Jul 22 06:19:27 PM PDT 24 380896495 ps
T875 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1639716756 Jul 22 06:19:40 PM PDT 24 Jul 22 06:19:41 PM PDT 24 129572424 ps
T876 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3878766494 Jul 22 06:19:31 PM PDT 24 Jul 22 06:19:38 PM PDT 24 281870711 ps
T217 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1943092303 Jul 22 06:19:33 PM PDT 24 Jul 22 06:19:35 PM PDT 24 27905493 ps
T877 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2203038398 Jul 22 06:19:20 PM PDT 24 Jul 22 06:19:22 PM PDT 24 131875446 ps
T199 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2158092195 Jul 22 06:19:38 PM PDT 24 Jul 22 06:19:39 PM PDT 24 37026160 ps
T878 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1894112575 Jul 22 06:19:16 PM PDT 24 Jul 22 06:19:18 PM PDT 24 82944825 ps
T879 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.316061585 Jul 22 06:19:39 PM PDT 24 Jul 22 06:19:43 PM PDT 24 234184884 ps
T880 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2944420885 Jul 22 06:19:16 PM PDT 24 Jul 22 06:19:19 PM PDT 24 25245693 ps
T881 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.90875272 Jul 22 06:20:02 PM PDT 24 Jul 22 06:20:04 PM PDT 24 90771825 ps
T200 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.197350233 Jul 22 06:19:16 PM PDT 24 Jul 22 06:19:18 PM PDT 24 38715877 ps
T882 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1324430942 Jul 22 06:19:32 PM PDT 24 Jul 22 06:19:40 PM PDT 24 1111713864 ps
T126 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1611016097 Jul 22 06:19:21 PM PDT 24 Jul 22 06:19:25 PM PDT 24 132523359 ps
T130 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2545357280 Jul 22 06:19:39 PM PDT 24 Jul 22 06:19:41 PM PDT 24 64041999 ps
T218 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.662986519 Jul 22 06:19:21 PM PDT 24 Jul 22 06:19:24 PM PDT 24 115978433 ps
T883 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.209009274 Jul 22 06:19:21 PM PDT 24 Jul 22 06:19:25 PM PDT 24 146997862 ps
T884 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1018215703 Jul 22 06:19:28 PM PDT 24 Jul 22 06:19:30 PM PDT 24 469282749 ps
T885 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.709334797 Jul 22 06:20:09 PM PDT 24 Jul 22 06:20:13 PM PDT 24 512949615 ps
T886 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1022753854 Jul 22 06:19:17 PM PDT 24 Jul 22 06:19:23 PM PDT 24 1928753947 ps
T887 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.625212343 Jul 22 06:19:23 PM PDT 24 Jul 22 06:19:28 PM PDT 24 98437513 ps
T888 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1283168454 Jul 22 06:19:29 PM PDT 24 Jul 22 06:19:31 PM PDT 24 46081924 ps
T889 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1706793327 Jul 22 06:19:31 PM PDT 24 Jul 22 06:19:33 PM PDT 24 20626590 ps
T890 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3670404370 Jul 22 06:19:17 PM PDT 24 Jul 22 06:19:21 PM PDT 24 97030362 ps
T891 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1830264038 Jul 22 06:19:13 PM PDT 24 Jul 22 06:19:16 PM PDT 24 526119033 ps
T892 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3888776123 Jul 22 06:19:16 PM PDT 24 Jul 22 06:19:19 PM PDT 24 216798829 ps
T893 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.998359679 Jul 22 06:19:20 PM PDT 24 Jul 22 06:19:23 PM PDT 24 14566921 ps
T201 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2323024835 Jul 22 06:19:13 PM PDT 24 Jul 22 06:19:16 PM PDT 24 39826394 ps
T894 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3622889297 Jul 22 06:19:23 PM PDT 24 Jul 22 06:19:29 PM PDT 24 182370588 ps
T895 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1509079223 Jul 22 06:19:11 PM PDT 24 Jul 22 06:19:13 PM PDT 24 99633177 ps
T896 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.792472841 Jul 22 06:20:18 PM PDT 24 Jul 22 06:20:21 PM PDT 24 15629664 ps
T897 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3507123004 Jul 22 06:19:16 PM PDT 24 Jul 22 06:19:20 PM PDT 24 1101122516 ps
T898 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.585142470 Jul 22 06:19:56 PM PDT 24 Jul 22 06:20:00 PM PDT 24 107388167 ps
T899 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.423438238 Jul 22 06:20:07 PM PDT 24 Jul 22 06:20:13 PM PDT 24 424745904 ps
T900 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2839394290 Jul 22 06:19:32 PM PDT 24 Jul 22 06:19:34 PM PDT 24 14971584 ps
T901 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1688733488 Jul 22 06:19:33 PM PDT 24 Jul 22 06:19:37 PM PDT 24 271506194 ps
T902 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1991021774 Jul 22 06:19:46 PM PDT 24 Jul 22 06:19:48 PM PDT 24 77445798 ps
T903 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3926404680 Jul 22 06:19:16 PM PDT 24 Jul 22 06:19:24 PM PDT 24 7415247597 ps
T904 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3084253391 Jul 22 06:19:29 PM PDT 24 Jul 22 06:19:31 PM PDT 24 110220816 ps
T905 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.884946263 Jul 22 06:19:17 PM PDT 24 Jul 22 06:19:37 PM PDT 24 9664937024 ps
T906 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.235727697 Jul 22 06:19:42 PM PDT 24 Jul 22 06:19:44 PM PDT 24 77911693 ps
T907 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1743458730 Jul 22 06:19:14 PM PDT 24 Jul 22 06:19:22 PM PDT 24 701138403 ps
T908 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3670456722 Jul 22 06:20:06 PM PDT 24 Jul 22 06:20:09 PM PDT 24 46371264 ps
T909 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1203568485 Jul 22 06:19:13 PM PDT 24 Jul 22 06:19:24 PM PDT 24 1798537469 ps
T910 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.925492898 Jul 22 06:19:43 PM PDT 24 Jul 22 06:19:45 PM PDT 24 48117079 ps
T202 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3361575019 Jul 22 06:19:58 PM PDT 24 Jul 22 06:20:00 PM PDT 24 34265115 ps
T911 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1772829353 Jul 22 06:19:17 PM PDT 24 Jul 22 06:19:22 PM PDT 24 430334967 ps
T912 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1417437769 Jul 22 06:20:02 PM PDT 24 Jul 22 06:20:12 PM PDT 24 3565890349 ps
T913 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3041343086 Jul 22 06:19:40 PM PDT 24 Jul 22 06:19:43 PM PDT 24 76414648 ps
T114 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.69228135 Jul 22 06:19:41 PM PDT 24 Jul 22 06:19:44 PM PDT 24 174851442 ps
T914 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1495326649 Jul 22 06:19:23 PM PDT 24 Jul 22 06:19:26 PM PDT 24 88311169 ps
T915 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.333502779 Jul 22 06:19:23 PM PDT 24 Jul 22 06:19:29 PM PDT 24 551505731 ps
T916 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1190207672 Jul 22 06:19:27 PM PDT 24 Jul 22 06:19:29 PM PDT 24 48815968 ps
T917 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1718879785 Jul 22 06:19:33 PM PDT 24 Jul 22 06:19:35 PM PDT 24 48661593 ps
T918 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.4098325363 Jul 22 06:19:22 PM PDT 24 Jul 22 06:19:26 PM PDT 24 163923686 ps
T919 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1171999101 Jul 22 06:19:32 PM PDT 24 Jul 22 06:19:45 PM PDT 24 1669664769 ps
T920 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3098010632 Jul 22 06:19:42 PM PDT 24 Jul 22 06:19:46 PM PDT 24 111920263 ps
T921 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3707778932 Jul 22 06:19:23 PM PDT 24 Jul 22 06:19:27 PM PDT 24 14114029 ps
T922 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2594657809 Jul 22 06:19:16 PM PDT 24 Jul 22 06:19:18 PM PDT 24 28415565 ps
T923 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.373591930 Jul 22 06:19:21 PM PDT 24 Jul 22 06:19:26 PM PDT 24 2337915382 ps
T924 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1440253564 Jul 22 06:19:16 PM PDT 24 Jul 22 06:19:19 PM PDT 24 146294490 ps
T925 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.944198668 Jul 22 06:19:20 PM PDT 24 Jul 22 06:19:25 PM PDT 24 138753871 ps
T926 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4250401637 Jul 22 06:19:22 PM PDT 24 Jul 22 06:19:29 PM PDT 24 258611805 ps
T927 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1706673769 Jul 22 06:19:13 PM PDT 24 Jul 22 06:19:16 PM PDT 24 199788831 ps
T928 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.221808341 Jul 22 06:19:23 PM PDT 24 Jul 22 06:19:26 PM PDT 24 51710430 ps
T929 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3474198396 Jul 22 06:19:20 PM PDT 24 Jul 22 06:19:27 PM PDT 24 159859103 ps
T115 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1294574730 Jul 22 06:19:58 PM PDT 24 Jul 22 06:20:04 PM PDT 24 229924856 ps
T930 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.537241642 Jul 22 06:19:17 PM PDT 24 Jul 22 06:19:20 PM PDT 24 112378055 ps
T203 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.938959881 Jul 22 06:20:31 PM PDT 24 Jul 22 06:20:33 PM PDT 24 41029099 ps
T931 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1500640255 Jul 22 06:19:18 PM PDT 24 Jul 22 06:19:27 PM PDT 24 3055618478 ps
T932 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.448047289 Jul 22 06:19:33 PM PDT 24 Jul 22 06:19:38 PM PDT 24 666866382 ps
T933 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.175282930 Jul 22 06:20:07 PM PDT 24 Jul 22 06:20:10 PM PDT 24 333399353 ps
T934 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.401235757 Jul 22 06:19:20 PM PDT 24 Jul 22 06:19:24 PM PDT 24 247528076 ps
T935 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4106397174 Jul 22 06:19:33 PM PDT 24 Jul 22 06:19:37 PM PDT 24 375738757 ps
T936 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1152835959 Jul 22 06:20:02 PM PDT 24 Jul 22 06:20:04 PM PDT 24 40467131 ps
T937 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2779507253 Jul 22 06:19:34 PM PDT 24 Jul 22 06:19:38 PM PDT 24 625664995 ps
T938 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1028100376 Jul 22 06:19:23 PM PDT 24 Jul 22 06:19:27 PM PDT 24 97024477 ps
T939 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.707267127 Jul 22 06:20:18 PM PDT 24 Jul 22 06:20:21 PM PDT 24 44202557 ps
T940 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1559857554 Jul 22 06:19:43 PM PDT 24 Jul 22 06:19:47 PM PDT 24 58139482 ps
T941 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.772332281 Jul 22 06:20:07 PM PDT 24 Jul 22 06:20:10 PM PDT 24 22942903 ps
T124 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2770285477 Jul 22 06:19:27 PM PDT 24 Jul 22 06:19:31 PM PDT 24 362773450 ps
T128 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.165113961 Jul 22 06:19:47 PM PDT 24 Jul 22 06:19:49 PM PDT 24 157038279 ps
T942 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3634673977 Jul 22 06:19:43 PM PDT 24 Jul 22 06:19:45 PM PDT 24 16413907 ps
T943 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1747863383 Jul 22 06:19:21 PM PDT 24 Jul 22 06:19:26 PM PDT 24 45609995 ps
T129 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1413869291 Jul 22 06:19:31 PM PDT 24 Jul 22 06:19:34 PM PDT 24 245468356 ps
T944 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1835684041 Jul 22 06:20:02 PM PDT 24 Jul 22 06:20:12 PM PDT 24 374014403 ps
T945 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1276766596 Jul 22 06:19:47 PM PDT 24 Jul 22 06:19:49 PM PDT 24 39828340 ps
T946 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.366130674 Jul 22 06:19:21 PM PDT 24 Jul 22 06:19:45 PM PDT 24 3193421447 ps
T947 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3852547484 Jul 22 06:19:32 PM PDT 24 Jul 22 06:19:40 PM PDT 24 4686928155 ps
T948 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1785040345 Jul 22 06:19:30 PM PDT 24 Jul 22 06:19:32 PM PDT 24 24677807 ps
T949 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2995733793 Jul 22 06:19:39 PM PDT 24 Jul 22 06:19:40 PM PDT 24 134718404 ps
T950 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1341662430 Jul 22 06:19:11 PM PDT 24 Jul 22 06:19:14 PM PDT 24 289464093 ps
T951 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2212837593 Jul 22 06:19:39 PM PDT 24 Jul 22 06:19:41 PM PDT 24 141976950 ps
T952 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2518873245 Jul 22 06:19:50 PM PDT 24 Jul 22 06:19:52 PM PDT 24 657378151 ps
T953 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.25072500 Jul 22 06:19:34 PM PDT 24 Jul 22 06:19:36 PM PDT 24 66428547 ps
T120 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3960343166 Jul 22 06:19:17 PM PDT 24 Jul 22 06:19:20 PM PDT 24 48000104 ps
T954 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1322199082 Jul 22 06:19:22 PM PDT 24 Jul 22 06:19:26 PM PDT 24 113339813 ps
T955 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.831622131 Jul 22 06:19:37 PM PDT 24 Jul 22 06:19:38 PM PDT 24 25460834 ps
T956 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2830553298 Jul 22 06:19:17 PM PDT 24 Jul 22 06:19:21 PM PDT 24 92088233 ps
T957 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3629230277 Jul 22 06:19:24 PM PDT 24 Jul 22 06:19:27 PM PDT 24 55425304 ps
T958 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2503022758 Jul 22 06:20:06 PM PDT 24 Jul 22 06:20:09 PM PDT 24 53789893 ps
T204 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.632789762 Jul 22 06:19:50 PM PDT 24 Jul 22 06:19:51 PM PDT 24 37409327 ps
T205 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1310112116 Jul 22 06:19:55 PM PDT 24 Jul 22 06:19:56 PM PDT 24 80714160 ps
T959 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3326649079 Jul 22 06:19:23 PM PDT 24 Jul 22 06:19:27 PM PDT 24 214588962 ps
T960 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.635601874 Jul 22 06:19:30 PM PDT 24 Jul 22 06:19:32 PM PDT 24 169971294 ps
T961 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1744839725 Jul 22 06:19:23 PM PDT 24 Jul 22 06:19:27 PM PDT 24 23969423 ps
T962 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.423228918 Jul 22 06:19:15 PM PDT 24 Jul 22 06:19:17 PM PDT 24 65086994 ps
T963 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1750023845 Jul 22 06:19:40 PM PDT 24 Jul 22 06:19:42 PM PDT 24 73318118 ps
T964 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2383427229 Jul 22 06:19:50 PM PDT 24 Jul 22 06:19:52 PM PDT 24 116465245 ps
T118 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.321799991 Jul 22 06:20:35 PM PDT 24 Jul 22 06:20:38 PM PDT 24 356046753 ps
T965 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3746220554 Jul 22 06:19:23 PM PDT 24 Jul 22 06:19:27 PM PDT 24 241225496 ps
T966 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1725144069 Jul 22 06:20:02 PM PDT 24 Jul 22 06:20:34 PM PDT 24 4668590982 ps
T967 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1292685323 Jul 22 06:19:23 PM PDT 24 Jul 22 06:19:28 PM PDT 24 229312580 ps
T968 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.109354619 Jul 22 06:19:39 PM PDT 24 Jul 22 06:19:41 PM PDT 24 174690038 ps
T969 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2020704190 Jul 22 06:19:29 PM PDT 24 Jul 22 06:19:52 PM PDT 24 2214362140 ps
T970 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.131308268 Jul 22 06:19:41 PM PDT 24 Jul 22 06:19:43 PM PDT 24 94431095 ps
T971 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3546849455 Jul 22 06:19:16 PM PDT 24 Jul 22 06:19:20 PM PDT 24 316353952 ps
T972 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2335775689 Jul 22 06:19:11 PM PDT 24 Jul 22 06:19:13 PM PDT 24 58637952 ps
T973 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1177199245 Jul 22 06:20:06 PM PDT 24 Jul 22 06:20:08 PM PDT 24 18515034 ps
T974 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.589301158 Jul 22 06:19:23 PM PDT 24 Jul 22 06:19:27 PM PDT 24 67323284 ps
T975 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.819510613 Jul 22 06:19:47 PM PDT 24 Jul 22 06:19:48 PM PDT 24 19688007 ps
T206 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4276655826 Jul 22 06:19:29 PM PDT 24 Jul 22 06:19:31 PM PDT 24 50553212 ps
T976 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1457064706 Jul 22 06:19:22 PM PDT 24 Jul 22 06:19:26 PM PDT 24 46798121 ps
T977 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1415533603 Jul 22 06:19:39 PM PDT 24 Jul 22 06:19:41 PM PDT 24 40297817 ps
T978 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2330221999 Jul 22 06:19:20 PM PDT 24 Jul 22 06:19:34 PM PDT 24 875683305 ps
T209 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3633824807 Jul 22 06:19:29 PM PDT 24 Jul 22 06:19:31 PM PDT 24 16416422 ps
T207 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1272604332 Jul 22 06:19:40 PM PDT 24 Jul 22 06:19:42 PM PDT 24 16808687 ps
T979 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2143076949 Jul 22 06:19:40 PM PDT 24 Jul 22 06:19:42 PM PDT 24 147065630 ps
T980 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.196456237 Jul 22 06:19:39 PM PDT 24 Jul 22 06:19:41 PM PDT 24 70468278 ps
T981 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.4239649679 Jul 22 06:20:16 PM PDT 24 Jul 22 06:20:19 PM PDT 24 299507284 ps
T982 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4055708185 Jul 22 06:19:18 PM PDT 24 Jul 22 06:19:21 PM PDT 24 291830778 ps
T983 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.138829335 Jul 22 06:19:39 PM PDT 24 Jul 22 06:19:40 PM PDT 24 24616434 ps
T984 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1683569287 Jul 22 06:19:33 PM PDT 24 Jul 22 06:19:36 PM PDT 24 38086487 ps
T985 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.568571623 Jul 22 06:20:07 PM PDT 24 Jul 22 06:20:10 PM PDT 24 217933185 ps
T986 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1877990734 Jul 22 06:19:21 PM PDT 24 Jul 22 06:19:24 PM PDT 24 195748825 ps
T987 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1751225355 Jul 22 06:19:22 PM PDT 24 Jul 22 06:19:26 PM PDT 24 72034317 ps
T131 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.175957223 Jul 22 06:19:21 PM PDT 24 Jul 22 06:19:27 PM PDT 24 200602724 ps
T208 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.143846642 Jul 22 06:19:22 PM PDT 24 Jul 22 06:19:25 PM PDT 24 56659822 ps
T127 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3732328440 Jul 22 06:19:56 PM PDT 24 Jul 22 06:19:59 PM PDT 24 118485600 ps
T132 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2714503271 Jul 22 06:19:43 PM PDT 24 Jul 22 06:19:46 PM PDT 24 889666766 ps

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2723285613
Short name T4
Test name
Test status
Simulation time 14967924943 ps
CPU time 286.36 seconds
Started Jul 22 04:47:42 PM PDT 24
Finished Jul 22 04:52:29 PM PDT 24
Peak memory 259028 kb
Host smart-5e66fd6b-643b-4671-8330-a9e33edd69df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723285613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2723285613
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.115484892
Short name T3
Test name
Test status
Simulation time 934292175 ps
CPU time 9.66 seconds
Started Jul 22 04:45:12 PM PDT 24
Finished Jul 22 04:45:23 PM PDT 24
Peak memory 218064 kb
Host smart-ed17d752-5fd5-4174-b4d4-f89be0c1cad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115484892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.115484892
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.2442812223
Short name T20
Test name
Test status
Simulation time 10168127918 ps
CPU time 237.79 seconds
Started Jul 22 04:47:27 PM PDT 24
Finished Jul 22 04:51:25 PM PDT 24
Peak memory 253548 kb
Host smart-b4d0e468-ac75-49a4-a27e-628a7ae0be11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2442812223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.2442812223
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.899891864
Short name T2
Test name
Test status
Simulation time 433484766 ps
CPU time 16.03 seconds
Started Jul 22 04:45:38 PM PDT 24
Finished Jul 22 04:45:55 PM PDT 24
Peak memory 218560 kb
Host smart-0708be4f-8350-4cad-8069-3ab079e9011b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899891864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.899891864
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2166884697
Short name T101
Test name
Test status
Simulation time 174812718 ps
CPU time 1.55 seconds
Started Jul 22 06:19:23 PM PDT 24
Finished Jul 22 06:19:27 PM PDT 24
Peak memory 223688 kb
Host smart-53d716c6-8297-4f99-adad-15b0d0987044
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166884697 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2166884697
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2639123219
Short name T55
Test name
Test status
Simulation time 294852534 ps
CPU time 11 seconds
Started Jul 22 04:46:52 PM PDT 24
Finished Jul 22 04:47:03 PM PDT 24
Peak memory 218068 kb
Host smart-80525c35-c619-4bfa-8bcb-63cdea337a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639123219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2639123219
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2881434155
Short name T39
Test name
Test status
Simulation time 36122719 ps
CPU time 0.78 seconds
Started Jul 22 04:47:05 PM PDT 24
Finished Jul 22 04:47:06 PM PDT 24
Peak memory 208528 kb
Host smart-312b78a9-1987-4feb-b62d-f12557e9f563
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881434155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2881434155
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3277898301
Short name T59
Test name
Test status
Simulation time 907568387 ps
CPU time 37.46 seconds
Started Jul 22 04:43:57 PM PDT 24
Finished Jul 22 04:44:34 PM PDT 24
Peak memory 284204 kb
Host smart-ee0fe5fa-31bb-4070-a128-ae20d9c7cd32
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277898301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3277898301
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1293789909
Short name T18
Test name
Test status
Simulation time 3809132506 ps
CPU time 142.13 seconds
Started Jul 22 04:44:46 PM PDT 24
Finished Jul 22 04:47:09 PM PDT 24
Peak memory 283428 kb
Host smart-a00e59ed-9f25-466f-8fae-409b8d61c675
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293789909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1293789909
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.925422785
Short name T140
Test name
Test status
Simulation time 222656974595 ps
CPU time 340.76 seconds
Started Jul 22 04:47:41 PM PDT 24
Finished Jul 22 04:53:22 PM PDT 24
Peak memory 280952 kb
Host smart-e6e8edae-d684-4be9-a19f-e0be82aadcdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=925422785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.925422785
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.224165932
Short name T25
Test name
Test status
Simulation time 488492617 ps
CPU time 6.97 seconds
Started Jul 22 04:44:36 PM PDT 24
Finished Jul 22 04:44:43 PM PDT 24
Peak memory 216988 kb
Host smart-eae43d9a-92cc-4754-9b2c-ac7d5a76dee7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224165932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.224165932
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1067222738
Short name T117
Test name
Test status
Simulation time 107773424 ps
CPU time 2.95 seconds
Started Jul 22 06:19:31 PM PDT 24
Finished Jul 22 06:19:34 PM PDT 24
Peak memory 223312 kb
Host smart-b43e66e0-c6f4-473f-a63a-5a2424b7e6d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067222738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1067222738
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1743082617
Short name T158
Test name
Test status
Simulation time 648287628 ps
CPU time 10.53 seconds
Started Jul 22 04:46:44 PM PDT 24
Finished Jul 22 04:46:55 PM PDT 24
Peak memory 218108 kb
Host smart-caca6514-c957-4501-ad62-b0c575ad6e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743082617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1743082617
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2990171098
Short name T54
Test name
Test status
Simulation time 630519280 ps
CPU time 9.03 seconds
Started Jul 22 04:45:02 PM PDT 24
Finished Jul 22 04:45:12 PM PDT 24
Peak memory 225724 kb
Host smart-cd89a100-2c74-431c-9ad1-37f4c8b189ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990171098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2990171098
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.197350233
Short name T200
Test name
Test status
Simulation time 38715877 ps
CPU time 1.73 seconds
Started Jul 22 06:19:16 PM PDT 24
Finished Jul 22 06:19:18 PM PDT 24
Peak memory 210060 kb
Host smart-afeaac33-d09f-4ded-93b6-b5ec4d7c1c74
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197350233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.197350233
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3936250077
Short name T109
Test name
Test status
Simulation time 211583400 ps
CPU time 1.87 seconds
Started Jul 22 06:19:17 PM PDT 24
Finished Jul 22 06:19:20 PM PDT 24
Peak memory 211636 kb
Host smart-4c6d9c34-8e43-4717-90a4-3bb10a4ec2e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936250077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3936250077
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.407329441
Short name T187
Test name
Test status
Simulation time 15544355 ps
CPU time 0.88 seconds
Started Jul 22 04:45:22 PM PDT 24
Finished Jul 22 04:45:24 PM PDT 24
Peak memory 208548 kb
Host smart-b5dd2038-5220-48cd-9576-4993daec7710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407329441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.407329441
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3287835018
Short name T88
Test name
Test status
Simulation time 148163887716 ps
CPU time 2276.66 seconds
Started Jul 22 04:44:02 PM PDT 24
Finished Jul 22 05:22:00 PM PDT 24
Peak memory 1548228 kb
Host smart-d5d3c09f-b7f7-4b07-9cd0-b17969331a8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3287835018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.3287835018
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2594107820
Short name T111
Test name
Test status
Simulation time 40544127 ps
CPU time 2.96 seconds
Started Jul 22 06:19:41 PM PDT 24
Finished Jul 22 06:19:45 PM PDT 24
Peak memory 219212 kb
Host smart-5d48b69c-41bc-4ace-a3a0-beaba7fd7d0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594107820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2594107820
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1992522157
Short name T191
Test name
Test status
Simulation time 10925356122 ps
CPU time 140.13 seconds
Started Jul 22 04:46:14 PM PDT 24
Finished Jul 22 04:48:35 PM PDT 24
Peak memory 250732 kb
Host smart-69dd4864-2c22-40cd-8140-5baba53bebab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992522157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1992522157
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2316523124
Short name T46
Test name
Test status
Simulation time 8946297467 ps
CPU time 37.23 seconds
Started Jul 22 04:44:33 PM PDT 24
Finished Jul 22 04:45:11 PM PDT 24
Peak memory 225744 kb
Host smart-af077b9b-a227-4dd4-a56a-2f571407a895
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316523124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2316523124
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2770285477
Short name T124
Test name
Test status
Simulation time 362773450 ps
CPU time 2.66 seconds
Started Jul 22 06:19:27 PM PDT 24
Finished Jul 22 06:19:31 PM PDT 24
Peak memory 223016 kb
Host smart-6a536f33-3d2c-4489-9e9f-c1b97280443d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770285477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2770285477
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2708707048
Short name T57
Test name
Test status
Simulation time 1703175482 ps
CPU time 10.8 seconds
Started Jul 22 04:44:39 PM PDT 24
Finished Jul 22 04:44:50 PM PDT 24
Peak memory 225752 kb
Host smart-e23dff27-5c80-49cd-9a76-c51b3c4700c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708707048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2708707048
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.533408886
Short name T107
Test name
Test status
Simulation time 222996901 ps
CPU time 2.42 seconds
Started Jul 22 06:19:42 PM PDT 24
Finished Jul 22 06:19:45 PM PDT 24
Peak memory 218184 kb
Host smart-18e26851-e0ed-4170-b828-9bea7b641c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533408886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.533408886
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.165113961
Short name T128
Test name
Test status
Simulation time 157038279 ps
CPU time 1.76 seconds
Started Jul 22 06:19:47 PM PDT 24
Finished Jul 22 06:19:49 PM PDT 24
Peak memory 222516 kb
Host smart-15bc0be6-82f7-457b-ab26-34928b26534b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165113961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.165113961
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3842801514
Short name T102
Test name
Test status
Simulation time 65594876 ps
CPU time 2.76 seconds
Started Jul 22 06:19:21 PM PDT 24
Finished Jul 22 06:19:26 PM PDT 24
Peak memory 218264 kb
Host smart-69f505af-19c9-4113-93ae-961fa123ef3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842801514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3842801514
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2489176354
Short name T213
Test name
Test status
Simulation time 42145729 ps
CPU time 0.81 seconds
Started Jul 22 06:20:03 PM PDT 24
Finished Jul 22 06:20:05 PM PDT 24
Peak memory 209692 kb
Host smart-ecafcc43-1a0a-45c5-ae5e-9ab7a7d45975
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489176354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2489176354
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.220319284
Short name T47
Test name
Test status
Simulation time 939022465 ps
CPU time 13.91 seconds
Started Jul 22 04:45:35 PM PDT 24
Finished Jul 22 04:45:49 PM PDT 24
Peak memory 218640 kb
Host smart-df0f91f1-ae9b-4c02-8116-5831d10f1c2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220319284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.220319284
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1294574730
Short name T115
Test name
Test status
Simulation time 229924856 ps
CPU time 4.09 seconds
Started Jul 22 06:19:58 PM PDT 24
Finished Jul 22 06:20:04 PM PDT 24
Peak memory 218248 kb
Host smart-2e1abfef-2339-4bf6-9a02-f4318b1f5655
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294574730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1294574730
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.363873152
Short name T220
Test name
Test status
Simulation time 21413867 ps
CPU time 0.87 seconds
Started Jul 22 04:43:24 PM PDT 24
Finished Jul 22 04:43:26 PM PDT 24
Peak memory 208444 kb
Host smart-3c7065b4-f81b-41e3-b47e-c50e53f222c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363873152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.363873152
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1197501349
Short name T450
Test name
Test status
Simulation time 290043649 ps
CPU time 8.23 seconds
Started Jul 22 04:45:47 PM PDT 24
Finished Jul 22 04:45:56 PM PDT 24
Peak memory 217944 kb
Host smart-f74ebbb5-0ca3-468f-a596-df980f08f7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197501349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1197501349
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1739177409
Short name T222
Test name
Test status
Simulation time 11127101 ps
CPU time 0.83 seconds
Started Jul 22 04:44:10 PM PDT 24
Finished Jul 22 04:44:12 PM PDT 24
Peak memory 208452 kb
Host smart-ba4a235a-65ae-404f-a5b0-2a800677c715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739177409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1739177409
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3433016225
Short name T223
Test name
Test status
Simulation time 29637442 ps
CPU time 0.86 seconds
Started Jul 22 04:44:20 PM PDT 24
Finished Jul 22 04:44:22 PM PDT 24
Peak memory 208540 kb
Host smart-7e1b08ad-bb95-4a75-ad2e-313b934ef434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433016225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3433016225
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1509079223
Short name T895
Test name
Test status
Simulation time 99633177 ps
CPU time 1.31 seconds
Started Jul 22 06:19:11 PM PDT 24
Finished Jul 22 06:19:13 PM PDT 24
Peak memory 218376 kb
Host smart-29ff9cd6-a727-4bdc-be60-86c25c6f2d2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150907
9223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1509079223
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.321799991
Short name T118
Test name
Test status
Simulation time 356046753 ps
CPU time 1.94 seconds
Started Jul 22 06:20:35 PM PDT 24
Finished Jul 22 06:20:38 PM PDT 24
Peak memory 222824 kb
Host smart-f02b9eb7-30df-4366-b101-85f733c16b58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321799991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.321799991
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.69228135
Short name T114
Test name
Test status
Simulation time 174851442 ps
CPU time 2.75 seconds
Started Jul 22 06:19:41 PM PDT 24
Finished Jul 22 06:19:44 PM PDT 24
Peak memory 223216 kb
Host smart-efc5b67b-0748-421b-bd7a-c55c97c5e918
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69228135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_e
rr.69228135
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2714503271
Short name T132
Test name
Test status
Simulation time 889666766 ps
CPU time 2.68 seconds
Started Jul 22 06:19:43 PM PDT 24
Finished Jul 22 06:19:46 PM PDT 24
Peak memory 218060 kb
Host smart-edaf9b6e-f629-48b0-bd50-0e8896c58037
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714503271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2714503271
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.797529269
Short name T52
Test name
Test status
Simulation time 1142523783 ps
CPU time 30.55 seconds
Started Jul 22 04:43:35 PM PDT 24
Finished Jul 22 04:44:06 PM PDT 24
Peak memory 250456 kb
Host smart-a393bcfb-3b36-4c81-aa12-a8480f707172
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797529269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.797529269
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.499963818
Short name T256
Test name
Test status
Simulation time 1636203054 ps
CPU time 32.2 seconds
Started Jul 22 04:44:50 PM PDT 24
Finished Jul 22 04:45:22 PM PDT 24
Peak memory 251076 kb
Host smart-8d285f42-ca80-4869-8981-2cec3a7a9de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499963818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.499963818
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1270861152
Short name T17
Test name
Test status
Simulation time 873447891 ps
CPU time 8.01 seconds
Started Jul 22 04:45:36 PM PDT 24
Finished Jul 22 04:45:45 PM PDT 24
Peak memory 217940 kb
Host smart-f3e93ef1-07e4-4f97-a0c8-b88bb09885b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270861152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1270861152
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2323024835
Short name T201
Test name
Test status
Simulation time 39826394 ps
CPU time 1.25 seconds
Started Jul 22 06:19:13 PM PDT 24
Finished Jul 22 06:19:16 PM PDT 24
Peak memory 210024 kb
Host smart-8ed85317-216f-4038-812c-f646adf7021d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323024835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2323024835
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3499373839
Short name T865
Test name
Test status
Simulation time 28602689 ps
CPU time 1.19 seconds
Started Jul 22 06:20:07 PM PDT 24
Finished Jul 22 06:20:10 PM PDT 24
Peak memory 210068 kb
Host smart-b87c820a-0178-4e52-bd14-dbb893ed159d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499373839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3499373839
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1177199245
Short name T973
Test name
Test status
Simulation time 18515034 ps
CPU time 0.92 seconds
Started Jul 22 06:20:06 PM PDT 24
Finished Jul 22 06:20:08 PM PDT 24
Peak memory 210508 kb
Host smart-966d8961-5acd-40b8-9d22-8c343d0aa99a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177199245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1177199245
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1706673769
Short name T927
Test name
Test status
Simulation time 199788831 ps
CPU time 1.02 seconds
Started Jul 22 06:19:13 PM PDT 24
Finished Jul 22 06:19:16 PM PDT 24
Peak memory 220024 kb
Host smart-9f5554eb-296a-40c0-bd96-819e9964a636
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706673769 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1706673769
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.4094489989
Short name T873
Test name
Test status
Simulation time 44289886 ps
CPU time 0.96 seconds
Started Jul 22 06:19:12 PM PDT 24
Finished Jul 22 06:19:14 PM PDT 24
Peak memory 209896 kb
Host smart-0266c641-fd01-4948-b173-e74828505673
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094489989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.4094489989
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3888776123
Short name T892
Test name
Test status
Simulation time 216798829 ps
CPU time 1.82 seconds
Started Jul 22 06:19:16 PM PDT 24
Finished Jul 22 06:19:19 PM PDT 24
Peak memory 209764 kb
Host smart-597dc079-66d5-4eda-bb9c-233229b98a47
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888776123 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3888776123
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1835684041
Short name T944
Test name
Test status
Simulation time 374014403 ps
CPU time 9.62 seconds
Started Jul 22 06:20:02 PM PDT 24
Finished Jul 22 06:20:12 PM PDT 24
Peak memory 208768 kb
Host smart-52fca359-b3a3-46c4-ac76-726e903d5c1e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835684041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1835684041
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1203568485
Short name T909
Test name
Test status
Simulation time 1798537469 ps
CPU time 9.51 seconds
Started Jul 22 06:19:13 PM PDT 24
Finished Jul 22 06:19:24 PM PDT 24
Peak memory 209996 kb
Host smart-078f2b44-4717-4dd5-8469-30a6a98fc1ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203568485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1203568485
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3507123004
Short name T897
Test name
Test status
Simulation time 1101122516 ps
CPU time 2.02 seconds
Started Jul 22 06:19:16 PM PDT 24
Finished Jul 22 06:19:20 PM PDT 24
Peak memory 219380 kb
Host smart-f5763200-cb29-4748-9ef7-f06e9eb5dbfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350712
3004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3507123004
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1440253564
Short name T924
Test name
Test status
Simulation time 146294490 ps
CPU time 1.53 seconds
Started Jul 22 06:19:16 PM PDT 24
Finished Jul 22 06:19:19 PM PDT 24
Peak memory 210172 kb
Host smart-3346d0d7-234c-4fd0-9dcc-2a854c6abbe5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440253564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1440253564
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3670404370
Short name T890
Test name
Test status
Simulation time 97030362 ps
CPU time 1.99 seconds
Started Jul 22 06:19:17 PM PDT 24
Finished Jul 22 06:19:21 PM PDT 24
Peak memory 210072 kb
Host smart-314f0cf9-3b3c-4a03-9965-a8a29c27232e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670404370 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3670404370
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1830264038
Short name T891
Test name
Test status
Simulation time 526119033 ps
CPU time 1.79 seconds
Started Jul 22 06:19:13 PM PDT 24
Finished Jul 22 06:19:16 PM PDT 24
Peak memory 210092 kb
Host smart-1b21bba1-124c-4311-845c-8dd75567c637
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830264038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1830264038
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.944198668
Short name T925
Test name
Test status
Simulation time 138753871 ps
CPU time 1.97 seconds
Started Jul 22 06:19:20 PM PDT 24
Finished Jul 22 06:19:25 PM PDT 24
Peak memory 218880 kb
Host smart-75bb6e65-7d33-41ff-9711-d545c6c2dab6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944198668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.944198668
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1341662430
Short name T950
Test name
Test status
Simulation time 289464093 ps
CPU time 1.96 seconds
Started Jul 22 06:19:11 PM PDT 24
Finished Jul 22 06:19:14 PM PDT 24
Peak memory 222596 kb
Host smart-55b8955c-68c5-4cc6-8e37-117eb549c82d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341662430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1341662430
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2594657809
Short name T922
Test name
Test status
Simulation time 28415565 ps
CPU time 1.53 seconds
Started Jul 22 06:19:16 PM PDT 24
Finished Jul 22 06:19:18 PM PDT 24
Peak memory 210088 kb
Host smart-d3465d59-1742-43be-904c-242261d627bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594657809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2594657809
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.761006225
Short name T116
Test name
Test status
Simulation time 55552002 ps
CPU time 0.89 seconds
Started Jul 22 06:20:01 PM PDT 24
Finished Jul 22 06:20:03 PM PDT 24
Peak memory 210536 kb
Host smart-bac08f84-03b1-43c9-887d-e13d26f8832d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761006225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.761006225
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.90875272
Short name T881
Test name
Test status
Simulation time 90771825 ps
CPU time 1.23 seconds
Started Jul 22 06:20:02 PM PDT 24
Finished Jul 22 06:20:04 PM PDT 24
Peak memory 218268 kb
Host smart-af6626e5-1fbe-4e05-848b-51f4729935c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90875272 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.90875272
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2944420885
Short name T880
Test name
Test status
Simulation time 25245693 ps
CPU time 0.79 seconds
Started Jul 22 06:19:16 PM PDT 24
Finished Jul 22 06:19:19 PM PDT 24
Peak memory 209808 kb
Host smart-a8b62afb-7e21-4a91-8d66-42e75948d746
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944420885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2944420885
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3546849455
Short name T971
Test name
Test status
Simulation time 316353952 ps
CPU time 2.42 seconds
Started Jul 22 06:19:16 PM PDT 24
Finished Jul 22 06:19:20 PM PDT 24
Peak memory 208708 kb
Host smart-ebbc5a29-e57a-42a1-968b-5ffb2ad75c7c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546849455 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.3546849455
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3926404680
Short name T903
Test name
Test status
Simulation time 7415247597 ps
CPU time 6.88 seconds
Started Jul 22 06:19:16 PM PDT 24
Finished Jul 22 06:19:24 PM PDT 24
Peak memory 210084 kb
Host smart-8a8ef218-512f-4650-90d5-345d2e21f80b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926404680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3926404680
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1743458730
Short name T907
Test name
Test status
Simulation time 701138403 ps
CPU time 6.92 seconds
Started Jul 22 06:19:14 PM PDT 24
Finished Jul 22 06:19:22 PM PDT 24
Peak memory 209336 kb
Host smart-d0d127c9-3bc5-4f07-88bd-d6080c23350b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743458730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1743458730
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2335775689
Short name T972
Test name
Test status
Simulation time 58637952 ps
CPU time 1.42 seconds
Started Jul 22 06:19:11 PM PDT 24
Finished Jul 22 06:19:13 PM PDT 24
Peak memory 211452 kb
Host smart-104e1c4a-51c0-42cf-aba4-99be8d0ba32a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335775689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2335775689
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.410626215
Short name T134
Test name
Test status
Simulation time 151097685 ps
CPU time 1.12 seconds
Started Jul 22 06:20:02 PM PDT 24
Finished Jul 22 06:20:04 PM PDT 24
Peak memory 209956 kb
Host smart-e654274c-1fe1-4257-8314-7f9c3b906071
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410626215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.410626215
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3326649079
Short name T959
Test name
Test status
Simulation time 214588962 ps
CPU time 1.69 seconds
Started Jul 22 06:19:23 PM PDT 24
Finished Jul 22 06:19:27 PM PDT 24
Peak memory 210044 kb
Host smart-82bcf6bb-6af1-40b0-b8e7-83049f9b3c67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326649079 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3326649079
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.537241642
Short name T930
Test name
Test status
Simulation time 112378055 ps
CPU time 1.54 seconds
Started Jul 22 06:19:17 PM PDT 24
Finished Jul 22 06:19:20 PM PDT 24
Peak memory 211908 kb
Host smart-c6275e4f-6fbf-4a6a-a860-d80caa71faee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537241642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.537241642
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1772829353
Short name T911
Test name
Test status
Simulation time 430334967 ps
CPU time 3.13 seconds
Started Jul 22 06:19:17 PM PDT 24
Finished Jul 22 06:19:22 PM PDT 24
Peak memory 218200 kb
Host smart-2e64d019-b3e2-4c72-a377-e26de7aef55f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772829353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1772829353
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3960343166
Short name T120
Test name
Test status
Simulation time 48000104 ps
CPU time 2.03 seconds
Started Jul 22 06:19:17 PM PDT 24
Finished Jul 22 06:19:20 PM PDT 24
Peak memory 222612 kb
Host smart-6f209126-a1e2-4cf3-ab64-b6a1a1d1ee3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960343166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3960343166
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1639716756
Short name T875
Test name
Test status
Simulation time 129572424 ps
CPU time 1.32 seconds
Started Jul 22 06:19:40 PM PDT 24
Finished Jul 22 06:19:41 PM PDT 24
Peak memory 222852 kb
Host smart-6e74fc82-26b5-44d3-b66d-b23b0d4d3ea8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639716756 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1639716756
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.235727697
Short name T906
Test name
Test status
Simulation time 77911693 ps
CPU time 1.61 seconds
Started Jul 22 06:19:42 PM PDT 24
Finished Jul 22 06:19:44 PM PDT 24
Peak memory 212068 kb
Host smart-73edd18a-945b-4826-99ff-85d2a5f97eb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235727697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.235727697
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1230842921
Short name T123
Test name
Test status
Simulation time 144152374 ps
CPU time 4.28 seconds
Started Jul 22 06:19:40 PM PDT 24
Finished Jul 22 06:19:45 PM PDT 24
Peak memory 218252 kb
Host smart-865bdb8b-16e7-41ec-bf0a-8f8418278a00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230842921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1230842921
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.196456237
Short name T980
Test name
Test status
Simulation time 70468278 ps
CPU time 1.06 seconds
Started Jul 22 06:19:39 PM PDT 24
Finished Jul 22 06:19:41 PM PDT 24
Peak memory 219380 kb
Host smart-3fd3c9b5-ef4d-457d-b890-15f3ae7af839
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196456237 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.196456237
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2158092195
Short name T199
Test name
Test status
Simulation time 37026160 ps
CPU time 0.8 seconds
Started Jul 22 06:19:38 PM PDT 24
Finished Jul 22 06:19:39 PM PDT 24
Peak memory 209860 kb
Host smart-5b45a7ff-f55e-4abe-8d4a-0fe3b0e07e33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158092195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2158092195
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.4239649679
Short name T981
Test name
Test status
Simulation time 299507284 ps
CPU time 1.34 seconds
Started Jul 22 06:20:16 PM PDT 24
Finished Jul 22 06:20:19 PM PDT 24
Peak memory 210052 kb
Host smart-cfe79698-f667-4096-96b0-acc9b7c39722
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239649679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.4239649679
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3536864319
Short name T125
Test name
Test status
Simulation time 813829589 ps
CPU time 4.36 seconds
Started Jul 22 06:19:41 PM PDT 24
Finished Jul 22 06:19:46 PM PDT 24
Peak memory 218196 kb
Host smart-f9d66b4b-0946-4340-8fd5-58e3d3d47d72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536864319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3536864319
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1604080607
Short name T110
Test name
Test status
Simulation time 27667134 ps
CPU time 1.2 seconds
Started Jul 22 06:19:41 PM PDT 24
Finished Jul 22 06:19:43 PM PDT 24
Peak memory 218408 kb
Host smart-a959bbe3-1387-40f3-a72c-35b216c7b026
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604080607 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1604080607
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3634673977
Short name T942
Test name
Test status
Simulation time 16413907 ps
CPU time 0.89 seconds
Started Jul 22 06:19:43 PM PDT 24
Finished Jul 22 06:19:45 PM PDT 24
Peak memory 209592 kb
Host smart-f99b0bb6-5c7c-435a-9b63-b8dc7abbba25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634673977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3634673977
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.138829335
Short name T983
Test name
Test status
Simulation time 24616434 ps
CPU time 1 seconds
Started Jul 22 06:19:39 PM PDT 24
Finished Jul 22 06:19:40 PM PDT 24
Peak memory 209992 kb
Host smart-cfc77f1c-a77d-4a0e-a59a-4ac3def8c9c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138829335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.138829335
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.316061585
Short name T879
Test name
Test status
Simulation time 234184884 ps
CPU time 3.95 seconds
Started Jul 22 06:19:39 PM PDT 24
Finished Jul 22 06:19:43 PM PDT 24
Peak memory 218196 kb
Host smart-f0eeed3c-23a4-4405-aba2-7b97646571ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316061585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.316061585
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1267133411
Short name T867
Test name
Test status
Simulation time 50445637 ps
CPU time 1.38 seconds
Started Jul 22 06:19:43 PM PDT 24
Finished Jul 22 06:19:45 PM PDT 24
Peak memory 218424 kb
Host smart-c2242ea8-f37d-4e6e-9085-65a62e19a8e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267133411 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1267133411
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3361575019
Short name T202
Test name
Test status
Simulation time 34265115 ps
CPU time 0.94 seconds
Started Jul 22 06:19:58 PM PDT 24
Finished Jul 22 06:20:00 PM PDT 24
Peak memory 210020 kb
Host smart-5cd8951d-f959-4875-9c23-6ed3fdb72221
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361575019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3361575019
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.925492898
Short name T910
Test name
Test status
Simulation time 48117079 ps
CPU time 1.1 seconds
Started Jul 22 06:19:43 PM PDT 24
Finished Jul 22 06:19:45 PM PDT 24
Peak memory 209896 kb
Host smart-970b9c55-9d8e-457f-b5c6-a7e2fd811970
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925492898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.925492898
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3098010632
Short name T920
Test name
Test status
Simulation time 111920263 ps
CPU time 3.38 seconds
Started Jul 22 06:19:42 PM PDT 24
Finished Jul 22 06:19:46 PM PDT 24
Peak memory 218212 kb
Host smart-7a8b1a48-a1c0-406b-bfc3-f43e1a86650b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098010632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3098010632
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.476333550
Short name T870
Test name
Test status
Simulation time 35100044 ps
CPU time 1.82 seconds
Started Jul 22 06:19:47 PM PDT 24
Finished Jul 22 06:19:49 PM PDT 24
Peak memory 223504 kb
Host smart-e996ffb5-ac6b-4a09-8af7-7fd069070939
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476333550 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.476333550
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.707267127
Short name T939
Test name
Test status
Simulation time 44202557 ps
CPU time 0.97 seconds
Started Jul 22 06:20:18 PM PDT 24
Finished Jul 22 06:20:21 PM PDT 24
Peak memory 218224 kb
Host smart-72d48221-30b2-4b4d-a510-c40042c58731
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707267127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.707267127
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2143076949
Short name T979
Test name
Test status
Simulation time 147065630 ps
CPU time 1.17 seconds
Started Jul 22 06:19:40 PM PDT 24
Finished Jul 22 06:19:42 PM PDT 24
Peak memory 210008 kb
Host smart-809fd07b-f8be-4b27-a333-34954f5daa4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143076949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2143076949
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.752464198
Short name T105
Test name
Test status
Simulation time 46510325 ps
CPU time 1.66 seconds
Started Jul 22 06:19:54 PM PDT 24
Finished Jul 22 06:19:57 PM PDT 24
Peak memory 218300 kb
Host smart-433fffd1-fc8c-4a7f-903d-3a43bbb37184
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752464198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.752464198
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.85974969
Short name T149
Test name
Test status
Simulation time 42105269 ps
CPU time 1.2 seconds
Started Jul 22 06:19:40 PM PDT 24
Finished Jul 22 06:19:42 PM PDT 24
Peak memory 218248 kb
Host smart-bed6cafc-b90e-4a13-a45c-2f21e056211e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85974969 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.85974969
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1272604332
Short name T207
Test name
Test status
Simulation time 16808687 ps
CPU time 1.11 seconds
Started Jul 22 06:19:40 PM PDT 24
Finished Jul 22 06:19:42 PM PDT 24
Peak memory 210024 kb
Host smart-b575fcbb-98f2-4a54-860c-02be36551614
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272604332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.1272604332
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2212837593
Short name T951
Test name
Test status
Simulation time 141976950 ps
CPU time 1.37 seconds
Started Jul 22 06:19:39 PM PDT 24
Finished Jul 22 06:19:41 PM PDT 24
Peak memory 212036 kb
Host smart-6d45e950-dd8e-4f07-9001-96e0a57651dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212837593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2212837593
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.219055769
Short name T121
Test name
Test status
Simulation time 261229334 ps
CPU time 3.12 seconds
Started Jul 22 06:19:40 PM PDT 24
Finished Jul 22 06:19:44 PM PDT 24
Peak memory 218352 kb
Host smart-3844b91e-181c-4725-a753-025d579721d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219055769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.219055769
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1559857554
Short name T940
Test name
Test status
Simulation time 58139482 ps
CPU time 2.74 seconds
Started Jul 22 06:19:43 PM PDT 24
Finished Jul 22 06:19:47 PM PDT 24
Peak memory 218168 kb
Host smart-ad31bf98-7907-4d6f-9ea2-4059bd9b21ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559857554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1559857554
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1750023845
Short name T963
Test name
Test status
Simulation time 73318118 ps
CPU time 1.36 seconds
Started Jul 22 06:19:40 PM PDT 24
Finished Jul 22 06:19:42 PM PDT 24
Peak memory 218288 kb
Host smart-e4aee57c-9a13-48cb-a300-735783d1c8cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750023845 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1750023845
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.792472841
Short name T896
Test name
Test status
Simulation time 15629664 ps
CPU time 0.83 seconds
Started Jul 22 06:20:18 PM PDT 24
Finished Jul 22 06:20:21 PM PDT 24
Peak memory 210020 kb
Host smart-4c31df59-81ba-4d6d-9b98-bc681e7b03f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792472841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.792472841
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.4099532252
Short name T212
Test name
Test status
Simulation time 36959853 ps
CPU time 1.82 seconds
Started Jul 22 06:19:43 PM PDT 24
Finished Jul 22 06:19:45 PM PDT 24
Peak memory 210032 kb
Host smart-7fd9ad9d-e264-4ed4-9e30-53a3b30df878
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099532252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.4099532252
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1415533603
Short name T977
Test name
Test status
Simulation time 40297817 ps
CPU time 2.3 seconds
Started Jul 22 06:19:39 PM PDT 24
Finished Jul 22 06:19:41 PM PDT 24
Peak memory 218164 kb
Host smart-9856e18a-1a49-43bf-8c62-7f28cd9f0cba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415533603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1415533603
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.131308268
Short name T970
Test name
Test status
Simulation time 94431095 ps
CPU time 1.47 seconds
Started Jul 22 06:19:41 PM PDT 24
Finished Jul 22 06:19:43 PM PDT 24
Peak memory 218480 kb
Host smart-b52dfc17-ff4c-4f5a-a962-06b85e210711
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131308268 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.131308268
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1310112116
Short name T205
Test name
Test status
Simulation time 80714160 ps
CPU time 0.91 seconds
Started Jul 22 06:19:55 PM PDT 24
Finished Jul 22 06:19:56 PM PDT 24
Peak memory 210036 kb
Host smart-11caa3ed-c167-4016-84b7-c4c3b5a35a9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310112116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1310112116
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.831622131
Short name T955
Test name
Test status
Simulation time 25460834 ps
CPU time 1.3 seconds
Started Jul 22 06:19:37 PM PDT 24
Finished Jul 22 06:19:38 PM PDT 24
Peak memory 209684 kb
Host smart-3c56c04f-b810-48a1-8c94-05a3ddf0320d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831622131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.831622131
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.109354619
Short name T968
Test name
Test status
Simulation time 174690038 ps
CPU time 1.96 seconds
Started Jul 22 06:19:39 PM PDT 24
Finished Jul 22 06:19:41 PM PDT 24
Peak memory 218236 kb
Host smart-5d255b1a-2cb7-4e74-98b8-6221fc1138b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109354619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.109354619
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2545357280
Short name T130
Test name
Test status
Simulation time 64041999 ps
CPU time 1.99 seconds
Started Jul 22 06:19:39 PM PDT 24
Finished Jul 22 06:19:41 PM PDT 24
Peak memory 218212 kb
Host smart-55efc5f0-aa8f-4b00-8f24-501753c31b16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545357280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2545357280
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.819510613
Short name T975
Test name
Test status
Simulation time 19688007 ps
CPU time 1.05 seconds
Started Jul 22 06:19:47 PM PDT 24
Finished Jul 22 06:19:48 PM PDT 24
Peak memory 218540 kb
Host smart-b3b11db8-ab11-4b25-9703-8376091db957
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819510613 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.819510613
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.938959881
Short name T203
Test name
Test status
Simulation time 41029099 ps
CPU time 0.83 seconds
Started Jul 22 06:20:31 PM PDT 24
Finished Jul 22 06:20:33 PM PDT 24
Peak memory 209992 kb
Host smart-b20da245-738e-41be-a6c7-53f2cdba2a40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938959881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.938959881
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1991021774
Short name T902
Test name
Test status
Simulation time 77445798 ps
CPU time 1.03 seconds
Started Jul 22 06:19:46 PM PDT 24
Finished Jul 22 06:19:48 PM PDT 24
Peak memory 209956 kb
Host smart-744b3f1d-1afc-4226-aaa5-ae753c07d9bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991021774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1991021774
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.772332281
Short name T941
Test name
Test status
Simulation time 22942903 ps
CPU time 1.48 seconds
Started Jul 22 06:20:07 PM PDT 24
Finished Jul 22 06:20:10 PM PDT 24
Peak memory 218212 kb
Host smart-61b650b3-652f-48be-a252-e8c6e343cdda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772332281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.772332281
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2020552225
Short name T106
Test name
Test status
Simulation time 78019171 ps
CPU time 2.48 seconds
Started Jul 22 06:19:46 PM PDT 24
Finished Jul 22 06:19:49 PM PDT 24
Peak memory 222624 kb
Host smart-f2bd8f06-cd4a-4bf5-a1dc-d4ae861a71d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020552225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2020552225
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2383427229
Short name T964
Test name
Test status
Simulation time 116465245 ps
CPU time 1.46 seconds
Started Jul 22 06:19:50 PM PDT 24
Finished Jul 22 06:19:52 PM PDT 24
Peak memory 218496 kb
Host smart-e3bbc665-8f16-4a24-9d56-e48100d5390e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383427229 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2383427229
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.632789762
Short name T204
Test name
Test status
Simulation time 37409327 ps
CPU time 0.89 seconds
Started Jul 22 06:19:50 PM PDT 24
Finished Jul 22 06:19:51 PM PDT 24
Peak memory 209872 kb
Host smart-0622d682-ab3a-42bc-8e78-f5d93a3118b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632789762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.632789762
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2518873245
Short name T952
Test name
Test status
Simulation time 657378151 ps
CPU time 1.37 seconds
Started Jul 22 06:19:50 PM PDT 24
Finished Jul 22 06:19:52 PM PDT 24
Peak memory 210104 kb
Host smart-3fd00a84-b3ba-4941-bd1e-5878da5d6b62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518873245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2518873245
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2358377334
Short name T872
Test name
Test status
Simulation time 430812093 ps
CPU time 2.62 seconds
Started Jul 22 06:20:09 PM PDT 24
Finished Jul 22 06:20:15 PM PDT 24
Peak memory 218272 kb
Host smart-92821eea-7541-4207-b362-7bad504c11dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358377334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2358377334
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3806276950
Short name T108
Test name
Test status
Simulation time 87832221 ps
CPU time 2.16 seconds
Started Jul 22 06:19:53 PM PDT 24
Finished Jul 22 06:19:56 PM PDT 24
Peak memory 218336 kb
Host smart-f509fb27-8318-439c-9f7c-ed43b2091d67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806276950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3806276950
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2802035030
Short name T151
Test name
Test status
Simulation time 39816792 ps
CPU time 1.01 seconds
Started Jul 22 06:19:27 PM PDT 24
Finished Jul 22 06:19:28 PM PDT 24
Peak memory 209972 kb
Host smart-f231c671-73b9-407d-be07-c56a267565b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802035030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2802035030
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2830553298
Short name T956
Test name
Test status
Simulation time 92088233 ps
CPU time 2.96 seconds
Started Jul 22 06:19:17 PM PDT 24
Finished Jul 22 06:19:21 PM PDT 24
Peak memory 209952 kb
Host smart-c3313e66-6b6f-4abb-b305-b533c15c3ffa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830553298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2830553298
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1190207672
Short name T916
Test name
Test status
Simulation time 48815968 ps
CPU time 1.17 seconds
Started Jul 22 06:19:27 PM PDT 24
Finished Jul 22 06:19:29 PM PDT 24
Peak memory 212088 kb
Host smart-3fbea1c1-8ecd-4030-aef4-f58ba57cafe7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190207672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1190207672
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1894112575
Short name T878
Test name
Test status
Simulation time 82944825 ps
CPU time 1.16 seconds
Started Jul 22 06:19:16 PM PDT 24
Finished Jul 22 06:19:18 PM PDT 24
Peak memory 222888 kb
Host smart-afd9fd6a-882d-4686-8f6b-79563b011247
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894112575 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1894112575
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.998359679
Short name T893
Test name
Test status
Simulation time 14566921 ps
CPU time 1.01 seconds
Started Jul 22 06:19:20 PM PDT 24
Finished Jul 22 06:19:23 PM PDT 24
Peak memory 209760 kb
Host smart-3a356562-e9b2-4a5b-aba5-b1709830dd19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998359679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.998359679
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1022753854
Short name T886
Test name
Test status
Simulation time 1928753947 ps
CPU time 4.45 seconds
Started Jul 22 06:19:17 PM PDT 24
Finished Jul 22 06:19:23 PM PDT 24
Peak memory 209892 kb
Host smart-32aefcaf-ad4e-435b-a726-9a5388cf08ea
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022753854 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1022753854
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.508146429
Short name T135
Test name
Test status
Simulation time 7789938457 ps
CPU time 18.73 seconds
Started Jul 22 06:19:13 PM PDT 24
Finished Jul 22 06:19:32 PM PDT 24
Peak memory 210252 kb
Host smart-714cbda0-acf4-48d5-a3c0-2f1117b6e0e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508146429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.508146429
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.884946263
Short name T905
Test name
Test status
Simulation time 9664937024 ps
CPU time 19.02 seconds
Started Jul 22 06:19:17 PM PDT 24
Finished Jul 22 06:19:37 PM PDT 24
Peak memory 209968 kb
Host smart-cd5e66e9-803f-4111-9b8e-32d5d3bc8e55
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884946263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.884946263
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2503022758
Short name T958
Test name
Test status
Simulation time 53789893 ps
CPU time 1.29 seconds
Started Jul 22 06:20:06 PM PDT 24
Finished Jul 22 06:20:09 PM PDT 24
Peak memory 211464 kb
Host smart-b87ac772-ea67-4267-a366-5a9f9a2c34fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503022758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2503022758
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.401235757
Short name T934
Test name
Test status
Simulation time 247528076 ps
CPU time 1.46 seconds
Started Jul 22 06:19:20 PM PDT 24
Finished Jul 22 06:19:24 PM PDT 24
Peak memory 218216 kb
Host smart-7038025c-9b67-4c25-85b2-748248864bc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401235
757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.401235757
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2783360155
Short name T868
Test name
Test status
Simulation time 97399002 ps
CPU time 1.41 seconds
Started Jul 22 06:19:17 PM PDT 24
Finished Jul 22 06:19:20 PM PDT 24
Peak memory 208872 kb
Host smart-c92d143f-219e-4a37-8efc-9ebc1ead2d59
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783360155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2783360155
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3670456722
Short name T908
Test name
Test status
Simulation time 46371264 ps
CPU time 1.38 seconds
Started Jul 22 06:20:06 PM PDT 24
Finished Jul 22 06:20:09 PM PDT 24
Peak memory 210040 kb
Host smart-6b7b7c56-ff41-4d11-878c-3b6b2584a166
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670456722 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3670456722
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2423065975
Short name T215
Test name
Test status
Simulation time 92867409 ps
CPU time 1.28 seconds
Started Jul 22 06:19:20 PM PDT 24
Finished Jul 22 06:19:24 PM PDT 24
Peak memory 210024 kb
Host smart-c1733338-1f55-4159-99d2-5f92e09d56d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423065975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2423065975
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1338627925
Short name T112
Test name
Test status
Simulation time 563378993 ps
CPU time 3.79 seconds
Started Jul 22 06:19:17 PM PDT 24
Finished Jul 22 06:19:23 PM PDT 24
Peak memory 218228 kb
Host smart-5d4bfdb1-ba33-406e-be2f-b218875ad5be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338627925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1338627925
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.143846642
Short name T208
Test name
Test status
Simulation time 56659822 ps
CPU time 1.14 seconds
Started Jul 22 06:19:22 PM PDT 24
Finished Jul 22 06:19:25 PM PDT 24
Peak memory 210012 kb
Host smart-100debf7-0ceb-421c-aa35-0d1359b8782c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143846642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.143846642
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1283168454
Short name T888
Test name
Test status
Simulation time 46081924 ps
CPU time 1.46 seconds
Started Jul 22 06:19:29 PM PDT 24
Finished Jul 22 06:19:31 PM PDT 24
Peak memory 209956 kb
Host smart-6318ee57-deb3-4721-96b5-77d510730a78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283168454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1283168454
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1495326649
Short name T914
Test name
Test status
Simulation time 88311169 ps
CPU time 0.91 seconds
Started Jul 22 06:19:23 PM PDT 24
Finished Jul 22 06:19:26 PM PDT 24
Peak memory 210296 kb
Host smart-0e858c87-ffbd-4af9-a0b7-9c546bec429e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495326649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1495326649
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1751225355
Short name T987
Test name
Test status
Simulation time 72034317 ps
CPU time 1.32 seconds
Started Jul 22 06:19:22 PM PDT 24
Finished Jul 22 06:19:26 PM PDT 24
Peak memory 221380 kb
Host smart-bf7c77a3-56a6-4e6a-a934-5cb41feacca3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751225355 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1751225355
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2456472700
Short name T863
Test name
Test status
Simulation time 51512067 ps
CPU time 0.99 seconds
Started Jul 22 06:19:28 PM PDT 24
Finished Jul 22 06:19:30 PM PDT 24
Peak memory 209944 kb
Host smart-4574868c-4768-469a-bc1c-10da910366ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456472700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2456472700
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3725188976
Short name T137
Test name
Test status
Simulation time 53662868 ps
CPU time 1.78 seconds
Started Jul 22 06:19:20 PM PDT 24
Finished Jul 22 06:19:24 PM PDT 24
Peak memory 209960 kb
Host smart-7b1c93e6-2945-4ed3-8208-98f9a342b1f9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725188976 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3725188976
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1523196422
Short name T874
Test name
Test status
Simulation time 380896495 ps
CPU time 2.93 seconds
Started Jul 22 06:19:22 PM PDT 24
Finished Jul 22 06:19:27 PM PDT 24
Peak memory 209836 kb
Host smart-842994db-5a26-4d24-9639-3a0a1d8d506c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523196422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1523196422
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1500640255
Short name T931
Test name
Test status
Simulation time 3055618478 ps
CPU time 8.37 seconds
Started Jul 22 06:19:18 PM PDT 24
Finished Jul 22 06:19:27 PM PDT 24
Peak memory 209172 kb
Host smart-38d4376b-d917-489f-b72c-706b83c22796
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500640255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1500640255
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.423228918
Short name T962
Test name
Test status
Simulation time 65086994 ps
CPU time 1.36 seconds
Started Jul 22 06:19:15 PM PDT 24
Finished Jul 22 06:19:17 PM PDT 24
Peak memory 211520 kb
Host smart-cc89cb7c-4dfb-4cbd-9a40-ed6bd25c2888
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423228918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.423228918
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3622889297
Short name T894
Test name
Test status
Simulation time 182370588 ps
CPU time 3.56 seconds
Started Jul 22 06:19:23 PM PDT 24
Finished Jul 22 06:19:29 PM PDT 24
Peak memory 220036 kb
Host smart-1c1fa664-41f4-4c68-a723-cfb21efb3844
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362288
9297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3622889297
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4055708185
Short name T982
Test name
Test status
Simulation time 291830778 ps
CPU time 1.65 seconds
Started Jul 22 06:19:18 PM PDT 24
Finished Jul 22 06:19:21 PM PDT 24
Peak memory 210032 kb
Host smart-922d50ab-9f6d-4833-93c5-8b6ea86d7fc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055708185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.4055708185
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3668967683
Short name T214
Test name
Test status
Simulation time 112076604 ps
CPU time 1.4 seconds
Started Jul 22 06:19:21 PM PDT 24
Finished Jul 22 06:19:24 PM PDT 24
Peak memory 210116 kb
Host smart-f46bfbe9-2055-45d0-b684-45031c9f695a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668967683 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3668967683
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.662986519
Short name T218
Test name
Test status
Simulation time 115978433 ps
CPU time 1.42 seconds
Started Jul 22 06:19:21 PM PDT 24
Finished Jul 22 06:19:24 PM PDT 24
Peak memory 210036 kb
Host smart-ba48c5f2-1218-45d3-af11-d7ae05e788e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662986519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.662986519
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.625212343
Short name T887
Test name
Test status
Simulation time 98437513 ps
CPU time 2.26 seconds
Started Jul 22 06:19:23 PM PDT 24
Finished Jul 22 06:19:28 PM PDT 24
Peak memory 219676 kb
Host smart-42bdedc7-22a2-43fe-ab4a-8fa9aa05eae2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625212343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.625212343
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3732328440
Short name T127
Test name
Test status
Simulation time 118485600 ps
CPU time 2.75 seconds
Started Jul 22 06:19:56 PM PDT 24
Finished Jul 22 06:19:59 PM PDT 24
Peak memory 218228 kb
Host smart-371e3425-c880-433b-826b-7f1f72bed97c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732328440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3732328440
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4276655826
Short name T206
Test name
Test status
Simulation time 50553212 ps
CPU time 0.95 seconds
Started Jul 22 06:19:29 PM PDT 24
Finished Jul 22 06:19:31 PM PDT 24
Peak memory 209952 kb
Host smart-79c38b7c-bf6a-4059-a0a0-eb6905fb7b85
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276655826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.4276655826
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3490175871
Short name T133
Test name
Test status
Simulation time 74620758 ps
CPU time 1.25 seconds
Started Jul 22 06:19:33 PM PDT 24
Finished Jul 22 06:19:35 PM PDT 24
Peak memory 209804 kb
Host smart-8199d41c-392d-4215-ab04-9ebf9d4c7fcc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490175871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3490175871
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1152835959
Short name T936
Test name
Test status
Simulation time 40467131 ps
CPU time 0.89 seconds
Started Jul 22 06:20:02 PM PDT 24
Finished Jul 22 06:20:04 PM PDT 24
Peak memory 210324 kb
Host smart-25638c32-e25f-4f06-a8d7-7c139c58d104
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152835959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1152835959
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1744839725
Short name T961
Test name
Test status
Simulation time 23969423 ps
CPU time 1.44 seconds
Started Jul 22 06:19:23 PM PDT 24
Finished Jul 22 06:19:27 PM PDT 24
Peak memory 218288 kb
Host smart-0f643047-3c29-4503-933d-b3eee64c5e7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744839725 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1744839725
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3629230277
Short name T957
Test name
Test status
Simulation time 55425304 ps
CPU time 0.88 seconds
Started Jul 22 06:19:24 PM PDT 24
Finished Jul 22 06:19:27 PM PDT 24
Peak memory 210024 kb
Host smart-287d857a-a181-42b2-b0b8-152dd9ad8464
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629230277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3629230277
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1028100376
Short name T938
Test name
Test status
Simulation time 97024477 ps
CPU time 1.33 seconds
Started Jul 22 06:19:23 PM PDT 24
Finished Jul 22 06:19:27 PM PDT 24
Peak memory 209940 kb
Host smart-44b692dc-7da8-40c9-bd7e-b129e380b7b8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028100376 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1028100376
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1292685323
Short name T967
Test name
Test status
Simulation time 229312580 ps
CPU time 2.8 seconds
Started Jul 22 06:19:23 PM PDT 24
Finished Jul 22 06:19:28 PM PDT 24
Peak memory 209764 kb
Host smart-843d816d-17a9-4d65-bcd5-cd34204970bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292685323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1292685323
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.366130674
Short name T946
Test name
Test status
Simulation time 3193421447 ps
CPU time 21.41 seconds
Started Jul 22 06:19:21 PM PDT 24
Finished Jul 22 06:19:45 PM PDT 24
Peak memory 209236 kb
Host smart-de4de177-f381-46dc-a56e-7357e1e0213e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366130674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.366130674
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1322199082
Short name T954
Test name
Test status
Simulation time 113339813 ps
CPU time 1.54 seconds
Started Jul 22 06:19:22 PM PDT 24
Finished Jul 22 06:19:26 PM PDT 24
Peak memory 211168 kb
Host smart-c9fd62c0-d5bf-4389-9c04-7b08032bd58d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322199082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1322199082
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.373591930
Short name T923
Test name
Test status
Simulation time 2337915382 ps
CPU time 3.24 seconds
Started Jul 22 06:19:21 PM PDT 24
Finished Jul 22 06:19:26 PM PDT 24
Peak memory 218360 kb
Host smart-f27819dc-0f48-4d12-9518-419af2ac6585
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373591
930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.373591930
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.4098325363
Short name T918
Test name
Test status
Simulation time 163923686 ps
CPU time 1.43 seconds
Started Jul 22 06:19:22 PM PDT 24
Finished Jul 22 06:19:26 PM PDT 24
Peak memory 209968 kb
Host smart-c147c843-122d-4a57-b69c-db0ed8949385
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098325363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.4098325363
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.209009274
Short name T883
Test name
Test status
Simulation time 146997862 ps
CPU time 1.33 seconds
Started Jul 22 06:19:21 PM PDT 24
Finished Jul 22 06:19:25 PM PDT 24
Peak memory 211936 kb
Host smart-e5ad73de-1cd6-4930-9f1c-aa7d7dddcbe9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209009274 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.209009274
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3746220554
Short name T965
Test name
Test status
Simulation time 241225496 ps
CPU time 1.7 seconds
Started Jul 22 06:19:23 PM PDT 24
Finished Jul 22 06:19:27 PM PDT 24
Peak memory 210000 kb
Host smart-0e050070-d95b-4be1-8071-c2d699448e48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746220554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3746220554
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.585142470
Short name T898
Test name
Test status
Simulation time 107388167 ps
CPU time 3.04 seconds
Started Jul 22 06:19:56 PM PDT 24
Finished Jul 22 06:20:00 PM PDT 24
Peak memory 218284 kb
Host smart-190357b4-bab1-4c1f-b639-67b24cdfbcb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585142470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.585142470
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1611016097
Short name T126
Test name
Test status
Simulation time 132523359 ps
CPU time 2.61 seconds
Started Jul 22 06:19:21 PM PDT 24
Finished Jul 22 06:19:25 PM PDT 24
Peak memory 222860 kb
Host smart-d6f6a10a-4805-41ce-ab15-13104aaa21d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611016097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1611016097
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1877990734
Short name T986
Test name
Test status
Simulation time 195748825 ps
CPU time 0.85 seconds
Started Jul 22 06:19:21 PM PDT 24
Finished Jul 22 06:19:24 PM PDT 24
Peak memory 209660 kb
Host smart-61af224e-d142-42d3-a23a-72e249cfb2de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877990734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1877990734
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.589301158
Short name T974
Test name
Test status
Simulation time 67323284 ps
CPU time 1.34 seconds
Started Jul 22 06:19:23 PM PDT 24
Finished Jul 22 06:19:27 PM PDT 24
Peak memory 208592 kb
Host smart-8d1a6a3d-3342-4a4a-a0e4-91edbd385e62
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589301158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.lc_ctrl_jtag_alert_test.589301158
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1314407300
Short name T869
Test name
Test status
Simulation time 832627341 ps
CPU time 3.75 seconds
Started Jul 22 06:20:07 PM PDT 24
Finished Jul 22 06:20:12 PM PDT 24
Peak memory 209844 kb
Host smart-3e7e5d9b-d186-44be-b539-77fb662c4c78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314407300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1314407300
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.423438238
Short name T899
Test name
Test status
Simulation time 424745904 ps
CPU time 5.23 seconds
Started Jul 22 06:20:07 PM PDT 24
Finished Jul 22 06:20:13 PM PDT 24
Peak memory 209832 kb
Host smart-d45abaa9-6cc4-4335-83b6-bc4201414a75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423438238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.423438238
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1018215703
Short name T884
Test name
Test status
Simulation time 469282749 ps
CPU time 1.26 seconds
Started Jul 22 06:19:28 PM PDT 24
Finished Jul 22 06:19:30 PM PDT 24
Peak memory 211152 kb
Host smart-ebbbc3da-465f-4f55-9f9d-667693520663
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018215703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1018215703
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4250401637
Short name T926
Test name
Test status
Simulation time 258611805 ps
CPU time 4.59 seconds
Started Jul 22 06:19:22 PM PDT 24
Finished Jul 22 06:19:29 PM PDT 24
Peak memory 223964 kb
Host smart-0a9217fe-157a-4bf1-8e72-6636c6da6430
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425040
1637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4250401637
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.175282930
Short name T933
Test name
Test status
Simulation time 333399353 ps
CPU time 1.69 seconds
Started Jul 22 06:20:07 PM PDT 24
Finished Jul 22 06:20:10 PM PDT 24
Peak memory 209988 kb
Host smart-23281173-0982-448b-b9d0-02b7317d0d93
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175282930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.175282930
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1457064706
Short name T976
Test name
Test status
Simulation time 46798121 ps
CPU time 1.49 seconds
Started Jul 22 06:19:22 PM PDT 24
Finished Jul 22 06:19:26 PM PDT 24
Peak memory 210168 kb
Host smart-cd5deef7-1d69-4acd-8691-d00c3ce120db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457064706 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1457064706
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3084253391
Short name T904
Test name
Test status
Simulation time 110220816 ps
CPU time 1.39 seconds
Started Jul 22 06:19:29 PM PDT 24
Finished Jul 22 06:19:31 PM PDT 24
Peak memory 209948 kb
Host smart-3e94e765-3cbf-418f-9155-6c1319ef86b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084253391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3084253391
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3474198396
Short name T929
Test name
Test status
Simulation time 159859103 ps
CPU time 5.33 seconds
Started Jul 22 06:19:20 PM PDT 24
Finished Jul 22 06:19:27 PM PDT 24
Peak memory 218244 kb
Host smart-af12aae1-6dd1-4c61-90d1-561943a8fb23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474198396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3474198396
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.175957223
Short name T131
Test name
Test status
Simulation time 200602724 ps
CPU time 3.01 seconds
Started Jul 22 06:19:21 PM PDT 24
Finished Jul 22 06:19:27 PM PDT 24
Peak memory 214168 kb
Host smart-a45ae4a3-10b0-43f1-9dd0-46640c6b01f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175957223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.175957223
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1747863383
Short name T943
Test name
Test status
Simulation time 45609995 ps
CPU time 2.13 seconds
Started Jul 22 06:19:21 PM PDT 24
Finished Jul 22 06:19:26 PM PDT 24
Peak memory 218364 kb
Host smart-a326555c-f830-477f-a36a-91acbe7bc6a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747863383 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1747863383
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3707778932
Short name T921
Test name
Test status
Simulation time 14114029 ps
CPU time 1.03 seconds
Started Jul 22 06:19:23 PM PDT 24
Finished Jul 22 06:19:27 PM PDT 24
Peak memory 210008 kb
Host smart-eb043521-3251-40d5-a71d-64302ff0205b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707778932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3707778932
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2203038398
Short name T877
Test name
Test status
Simulation time 131875446 ps
CPU time 1.2 seconds
Started Jul 22 06:19:20 PM PDT 24
Finished Jul 22 06:19:22 PM PDT 24
Peak memory 208644 kb
Host smart-176536d1-c123-4caf-aad7-fddab10f6287
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203038398 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2203038398
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2330221999
Short name T978
Test name
Test status
Simulation time 875683305 ps
CPU time 11.2 seconds
Started Jul 22 06:19:20 PM PDT 24
Finished Jul 22 06:19:34 PM PDT 24
Peak memory 209780 kb
Host smart-5a3d4fe0-b535-41f8-a99f-16bd053a9a30
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330221999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2330221999
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2020704190
Short name T969
Test name
Test status
Simulation time 2214362140 ps
CPU time 22.12 seconds
Started Jul 22 06:19:29 PM PDT 24
Finished Jul 22 06:19:52 PM PDT 24
Peak memory 209840 kb
Host smart-61169aa9-e6dd-4f0d-aa38-ae53fe53d2ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020704190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2020704190
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4025119591
Short name T219
Test name
Test status
Simulation time 1201993671 ps
CPU time 6.65 seconds
Started Jul 22 06:19:23 PM PDT 24
Finished Jul 22 06:19:32 PM PDT 24
Peak memory 211764 kb
Host smart-cead7de2-1443-4b6c-b147-2c4897d77f61
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025119591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.4025119591
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.333502779
Short name T915
Test name
Test status
Simulation time 551505731 ps
CPU time 4.11 seconds
Started Jul 22 06:19:23 PM PDT 24
Finished Jul 22 06:19:29 PM PDT 24
Peak memory 219564 kb
Host smart-a34e5bd7-4ce7-4976-9f04-a264b0b5c624
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333502
779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.333502779
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.719652874
Short name T866
Test name
Test status
Simulation time 331508872 ps
CPU time 1.65 seconds
Started Jul 22 06:20:07 PM PDT 24
Finished Jul 22 06:20:10 PM PDT 24
Peak memory 210020 kb
Host smart-47088164-e68c-4f07-9b10-160d1d451209
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719652874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.719652874
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2706089699
Short name T216
Test name
Test status
Simulation time 99265790 ps
CPU time 1.89 seconds
Started Jul 22 06:19:20 PM PDT 24
Finished Jul 22 06:19:24 PM PDT 24
Peak memory 210096 kb
Host smart-4a172664-2fcc-40d2-a90e-86c928792e4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706089699 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2706089699
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1492477103
Short name T210
Test name
Test status
Simulation time 16818902 ps
CPU time 1.16 seconds
Started Jul 22 06:20:08 PM PDT 24
Finished Jul 22 06:20:11 PM PDT 24
Peak memory 210072 kb
Host smart-14da4317-e6b7-461e-b197-4e75cb566dfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492477103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1492477103
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1719013730
Short name T119
Test name
Test status
Simulation time 346381516 ps
CPU time 4.03 seconds
Started Jul 22 06:20:06 PM PDT 24
Finished Jul 22 06:20:11 PM PDT 24
Peak memory 218360 kb
Host smart-a538275e-d323-4cc4-9ea3-abc5d7255f1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719013730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1719013730
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1683569287
Short name T984
Test name
Test status
Simulation time 38086487 ps
CPU time 1.98 seconds
Started Jul 22 06:19:33 PM PDT 24
Finished Jul 22 06:19:36 PM PDT 24
Peak memory 220164 kb
Host smart-5945aa25-fa0d-4af0-82e2-95e869582d5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683569287 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1683569287
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4133797168
Short name T150
Test name
Test status
Simulation time 19058399 ps
CPU time 0.99 seconds
Started Jul 22 06:19:31 PM PDT 24
Finished Jul 22 06:19:33 PM PDT 24
Peak memory 209940 kb
Host smart-4260f8e9-3ed9-4f91-acfc-5370de46083d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133797168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.4133797168
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.25072500
Short name T953
Test name
Test status
Simulation time 66428547 ps
CPU time 1.54 seconds
Started Jul 22 06:19:34 PM PDT 24
Finished Jul 22 06:19:36 PM PDT 24
Peak memory 209936 kb
Host smart-5ad8eddd-7f69-4124-b0d8-1ff539d7996f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25072500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_alert_test.25072500
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1324430942
Short name T882
Test name
Test status
Simulation time 1111713864 ps
CPU time 6.85 seconds
Started Jul 22 06:19:32 PM PDT 24
Finished Jul 22 06:19:40 PM PDT 24
Peak memory 210036 kb
Host smart-48c8dae7-df02-46db-8d2a-c07dee3bde3d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324430942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1324430942
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1725144069
Short name T966
Test name
Test status
Simulation time 4668590982 ps
CPU time 25.89 seconds
Started Jul 22 06:20:02 PM PDT 24
Finished Jul 22 06:20:34 PM PDT 24
Peak memory 210020 kb
Host smart-aaad473a-4aa1-49f2-a420-fb536714e0b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725144069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1725144069
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.221808341
Short name T928
Test name
Test status
Simulation time 51710430 ps
CPU time 1.3 seconds
Started Jul 22 06:19:23 PM PDT 24
Finished Jul 22 06:19:26 PM PDT 24
Peak memory 211408 kb
Host smart-3a9b37d3-0c3e-43e7-9b5a-c9f1394fc5e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221808341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.221808341
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3435255883
Short name T864
Test name
Test status
Simulation time 66798366 ps
CPU time 1.85 seconds
Started Jul 22 06:19:32 PM PDT 24
Finished Jul 22 06:19:35 PM PDT 24
Peak memory 219416 kb
Host smart-7034b1cc-f864-479c-ac25-88fb76ed2c43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343525
5883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3435255883
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.568571623
Short name T985
Test name
Test status
Simulation time 217933185 ps
CPU time 1.34 seconds
Started Jul 22 06:20:07 PM PDT 24
Finished Jul 22 06:20:10 PM PDT 24
Peak memory 210020 kb
Host smart-25ca47f1-26b1-489e-a286-a4c2e54802d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568571623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.568571623
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1943092303
Short name T217
Test name
Test status
Simulation time 27905493 ps
CPU time 1.46 seconds
Started Jul 22 06:19:33 PM PDT 24
Finished Jul 22 06:19:35 PM PDT 24
Peak memory 209904 kb
Host smart-c001776e-dd8c-4c68-ac29-2887fd681d4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943092303 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1943092303
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1706793327
Short name T889
Test name
Test status
Simulation time 20626590 ps
CPU time 1.3 seconds
Started Jul 22 06:19:31 PM PDT 24
Finished Jul 22 06:19:33 PM PDT 24
Peak memory 212376 kb
Host smart-fdf954f3-e5f1-4220-ab54-d6df891fc1c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706793327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1706793327
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3041343086
Short name T913
Test name
Test status
Simulation time 76414648 ps
CPU time 1.59 seconds
Started Jul 22 06:19:40 PM PDT 24
Finished Jul 22 06:19:43 PM PDT 24
Peak memory 218268 kb
Host smart-6a8ed5c8-7061-4ec2-aa16-2d75d0d19f1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041343086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3041343086
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1413869291
Short name T129
Test name
Test status
Simulation time 245468356 ps
CPU time 2.01 seconds
Started Jul 22 06:19:31 PM PDT 24
Finished Jul 22 06:19:34 PM PDT 24
Peak memory 222692 kb
Host smart-9923d96e-3aec-46df-8337-032257cdaf8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413869291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1413869291
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1785040345
Short name T948
Test name
Test status
Simulation time 24677807 ps
CPU time 1.16 seconds
Started Jul 22 06:19:30 PM PDT 24
Finished Jul 22 06:19:32 PM PDT 24
Peak memory 220348 kb
Host smart-4f9070e0-f45e-4374-8696-6ca509bd41a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785040345 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1785040345
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2866828948
Short name T198
Test name
Test status
Simulation time 24425081 ps
CPU time 0.97 seconds
Started Jul 22 06:19:30 PM PDT 24
Finished Jul 22 06:19:32 PM PDT 24
Peak memory 210020 kb
Host smart-f3251e97-a3e3-4d62-a13c-148f4a5bf782
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866828948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2866828948
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4106397174
Short name T935
Test name
Test status
Simulation time 375738757 ps
CPU time 2.92 seconds
Started Jul 22 06:19:33 PM PDT 24
Finished Jul 22 06:19:37 PM PDT 24
Peak memory 209772 kb
Host smart-bb035fba-4065-4beb-b4c1-822c0825ec75
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106397174 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.4106397174
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1417437769
Short name T912
Test name
Test status
Simulation time 3565890349 ps
CPU time 8.56 seconds
Started Jul 22 06:20:02 PM PDT 24
Finished Jul 22 06:20:12 PM PDT 24
Peak memory 210060 kb
Host smart-d3c72226-035f-4ece-a935-0b7fc08abc9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417437769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1417437769
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3852547484
Short name T947
Test name
Test status
Simulation time 4686928155 ps
CPU time 7.84 seconds
Started Jul 22 06:19:32 PM PDT 24
Finished Jul 22 06:19:40 PM PDT 24
Peak memory 209140 kb
Host smart-39d7d70e-108a-4992-b1d8-561dfafccca1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852547484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3852547484
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3878766494
Short name T876
Test name
Test status
Simulation time 281870711 ps
CPU time 6.27 seconds
Started Jul 22 06:19:31 PM PDT 24
Finished Jul 22 06:19:38 PM PDT 24
Peak memory 211652 kb
Host smart-179f474b-4561-4fe2-baf8-55914a9c2965
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878766494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3878766494
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2480137707
Short name T122
Test name
Test status
Simulation time 90198098 ps
CPU time 2.33 seconds
Started Jul 22 06:19:33 PM PDT 24
Finished Jul 22 06:19:36 PM PDT 24
Peak memory 218344 kb
Host smart-7024fd31-b712-4e08-9f74-53d07e2f9475
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248013
7707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2480137707
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.448047289
Short name T932
Test name
Test status
Simulation time 666866382 ps
CPU time 4.22 seconds
Started Jul 22 06:19:33 PM PDT 24
Finished Jul 22 06:19:38 PM PDT 24
Peak memory 210068 kb
Host smart-f3746c0f-be3b-4dc7-9458-a84b61032316
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448047289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.448047289
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2995733793
Short name T949
Test name
Test status
Simulation time 134718404 ps
CPU time 1.11 seconds
Started Jul 22 06:19:39 PM PDT 24
Finished Jul 22 06:19:40 PM PDT 24
Peak memory 210044 kb
Host smart-15d67ec6-5023-48d4-ba54-8f42c86e93f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995733793 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2995733793
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1718879785
Short name T917
Test name
Test status
Simulation time 48661593 ps
CPU time 1.52 seconds
Started Jul 22 06:19:33 PM PDT 24
Finished Jul 22 06:19:35 PM PDT 24
Peak memory 210084 kb
Host smart-cd5b2920-3601-4391-bd16-ecacd5389873
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718879785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1718879785
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1688733488
Short name T901
Test name
Test status
Simulation time 271506194 ps
CPU time 2.99 seconds
Started Jul 22 06:19:33 PM PDT 24
Finished Jul 22 06:19:37 PM PDT 24
Peak memory 218224 kb
Host smart-e9d75d87-b0ae-4155-aaf1-40d84404cc6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688733488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1688733488
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3489842441
Short name T113
Test name
Test status
Simulation time 98970168 ps
CPU time 1.8 seconds
Started Jul 22 06:19:40 PM PDT 24
Finished Jul 22 06:19:43 PM PDT 24
Peak memory 218284 kb
Host smart-9ce70bd5-26fe-412a-bab7-afcbb138b7fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489842441 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3489842441
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3633824807
Short name T209
Test name
Test status
Simulation time 16416422 ps
CPU time 1.12 seconds
Started Jul 22 06:19:29 PM PDT 24
Finished Jul 22 06:19:31 PM PDT 24
Peak memory 210024 kb
Host smart-e34f8345-674c-43ce-9057-c6c6eb52f60a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633824807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3633824807
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1276766596
Short name T945
Test name
Test status
Simulation time 39828340 ps
CPU time 1.46 seconds
Started Jul 22 06:19:47 PM PDT 24
Finished Jul 22 06:19:49 PM PDT 24
Peak memory 208684 kb
Host smart-239a540b-7aac-49e4-acdf-d48f4969e2a8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276766596 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1276766596
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2779507253
Short name T937
Test name
Test status
Simulation time 625664995 ps
CPU time 3.45 seconds
Started Jul 22 06:19:34 PM PDT 24
Finished Jul 22 06:19:38 PM PDT 24
Peak memory 209724 kb
Host smart-a77ccd84-9802-4028-a990-76b7b1ab5f9f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779507253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2779507253
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1171999101
Short name T919
Test name
Test status
Simulation time 1669664769 ps
CPU time 11.69 seconds
Started Jul 22 06:19:32 PM PDT 24
Finished Jul 22 06:19:45 PM PDT 24
Peak memory 209868 kb
Host smart-c159546d-70bc-4970-970c-1cc058e5902a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171999101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1171999101
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.709334797
Short name T885
Test name
Test status
Simulation time 512949615 ps
CPU time 1.91 seconds
Started Jul 22 06:20:09 PM PDT 24
Finished Jul 22 06:20:13 PM PDT 24
Peak memory 211440 kb
Host smart-1e8f64d8-3893-401c-a023-788e02b2f5ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709334797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.709334797
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1849617875
Short name T103
Test name
Test status
Simulation time 56934174 ps
CPU time 1.53 seconds
Started Jul 22 06:20:03 PM PDT 24
Finished Jul 22 06:20:06 PM PDT 24
Peak memory 218308 kb
Host smart-aa81fc01-5d59-42bb-928a-063e38026707
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184961
7875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1849617875
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.635601874
Short name T960
Test name
Test status
Simulation time 169971294 ps
CPU time 1.11 seconds
Started Jul 22 06:19:30 PM PDT 24
Finished Jul 22 06:19:32 PM PDT 24
Peak memory 209928 kb
Host smart-43c23a02-81fa-47f9-b837-32add92442a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635601874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.635601874
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2839394290
Short name T900
Test name
Test status
Simulation time 14971584 ps
CPU time 1.15 seconds
Started Jul 22 06:19:32 PM PDT 24
Finished Jul 22 06:19:34 PM PDT 24
Peak memory 209996 kb
Host smart-b080e947-d7cd-4fb1-9e3d-60f816706e44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839394290 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2839394290
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.939241494
Short name T211
Test name
Test status
Simulation time 72739454 ps
CPU time 1.53 seconds
Started Jul 22 06:19:44 PM PDT 24
Finished Jul 22 06:19:46 PM PDT 24
Peak memory 210016 kb
Host smart-07f3ef19-a78c-4f17-afd6-e9eab86cc1ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939241494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.939241494
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.43752994
Short name T871
Test name
Test status
Simulation time 95266074 ps
CPU time 1.8 seconds
Started Jul 22 06:19:32 PM PDT 24
Finished Jul 22 06:19:35 PM PDT 24
Peak memory 219528 kb
Host smart-5144457f-e303-45e6-87e2-cca665df3320
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43752994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.43752994
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.978292459
Short name T559
Test name
Test status
Simulation time 92890672 ps
CPU time 1 seconds
Started Jul 22 04:43:18 PM PDT 24
Finished Jul 22 04:43:20 PM PDT 24
Peak memory 208748 kb
Host smart-3660c593-4223-4fc3-82cb-d520a1558926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978292459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.978292459
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.21971651
Short name T449
Test name
Test status
Simulation time 22298019 ps
CPU time 0.88 seconds
Started Jul 22 04:43:12 PM PDT 24
Finished Jul 22 04:43:14 PM PDT 24
Peak memory 208368 kb
Host smart-184fac30-9fb6-4f94-9523-3c6a5ed79a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21971651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.21971651
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1906640943
Short name T229
Test name
Test status
Simulation time 269415483 ps
CPU time 13.29 seconds
Started Jul 22 04:44:19 PM PDT 24
Finished Jul 22 04:44:33 PM PDT 24
Peak memory 217976 kb
Host smart-3b347068-97c0-4a28-a765-f839619e303a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906640943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1906640943
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.789253797
Short name T689
Test name
Test status
Simulation time 3211088654 ps
CPU time 15.35 seconds
Started Jul 22 04:43:09 PM PDT 24
Finished Jul 22 04:43:24 PM PDT 24
Peak memory 217436 kb
Host smart-77771f1c-7e0c-4cf6-af86-35300336914b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789253797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.789253797
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1178592150
Short name T275
Test name
Test status
Simulation time 1045588161 ps
CPU time 19.92 seconds
Started Jul 22 04:43:12 PM PDT 24
Finished Jul 22 04:43:33 PM PDT 24
Peak memory 225164 kb
Host smart-d246378f-b5d0-4f8e-abf0-4ebca56c0244
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178592150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1178592150
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.201030064
Short name T92
Test name
Test status
Simulation time 1644447705 ps
CPU time 5.91 seconds
Started Jul 22 04:43:12 PM PDT 24
Finished Jul 22 04:43:19 PM PDT 24
Peak memory 217428 kb
Host smart-4b926c65-c5a8-4903-80f7-c289b10edb9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201030064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.201030064
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2315497291
Short name T696
Test name
Test status
Simulation time 3433037011 ps
CPU time 5.85 seconds
Started Jul 22 04:43:09 PM PDT 24
Finished Jul 22 04:43:15 PM PDT 24
Peak memory 224396 kb
Host smart-3fe4c11c-5dee-423c-8a10-f23167ae786f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315497291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2315497291
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1253737981
Short name T627
Test name
Test status
Simulation time 7957744122 ps
CPU time 16.69 seconds
Started Jul 22 04:43:10 PM PDT 24
Finished Jul 22 04:43:27 PM PDT 24
Peak memory 217268 kb
Host smart-708d61eb-84fa-4347-8a8d-356ebcdb454f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253737981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.1253737981
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3471817609
Short name T238
Test name
Test status
Simulation time 2287072216 ps
CPU time 6.29 seconds
Started Jul 22 04:43:13 PM PDT 24
Finished Jul 22 04:43:19 PM PDT 24
Peak memory 217368 kb
Host smart-4704d6d6-d8df-4733-bc3a-b253e1587cb8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471817609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3471817609
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3888688584
Short name T290
Test name
Test status
Simulation time 920549860 ps
CPU time 33.9 seconds
Started Jul 22 04:43:11 PM PDT 24
Finished Jul 22 04:43:46 PM PDT 24
Peak memory 250688 kb
Host smart-d13dad9d-a694-4006-b1ac-cc6fbeda303f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888688584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3888688584
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.4018201724
Short name T510
Test name
Test status
Simulation time 853341527 ps
CPU time 16.48 seconds
Started Jul 22 04:43:11 PM PDT 24
Finished Jul 22 04:43:28 PM PDT 24
Peak memory 250580 kb
Host smart-3eb9dff8-7d8a-47f5-ad4c-1675a436d17b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018201724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.4018201724
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2775946413
Short name T852
Test name
Test status
Simulation time 66635099 ps
CPU time 3.41 seconds
Started Jul 22 04:43:55 PM PDT 24
Finished Jul 22 04:44:00 PM PDT 24
Peak memory 222248 kb
Host smart-d541f3b9-69f5-4097-a3a0-6d20ba1dea86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775946413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2775946413
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2273251692
Short name T798
Test name
Test status
Simulation time 596790617 ps
CPU time 12.95 seconds
Started Jul 22 04:43:10 PM PDT 24
Finished Jul 22 04:43:24 PM PDT 24
Peak memory 214344 kb
Host smart-1f05b3cf-497a-4b75-ae12-6511bc09a2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273251692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2273251692
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3903650686
Short name T60
Test name
Test status
Simulation time 404441714 ps
CPU time 36.32 seconds
Started Jul 22 04:43:17 PM PDT 24
Finished Jul 22 04:43:54 PM PDT 24
Peak memory 280780 kb
Host smart-c41f5504-296b-401c-96b8-a424ac6278a6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903650686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3903650686
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.42146007
Short name T391
Test name
Test status
Simulation time 378602540 ps
CPU time 13.68 seconds
Started Jul 22 04:43:14 PM PDT 24
Finished Jul 22 04:43:28 PM PDT 24
Peak memory 218620 kb
Host smart-81214c0a-ffaa-42d5-a51f-472baec4011b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42146007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.42146007
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1716894963
Short name T754
Test name
Test status
Simulation time 206977989 ps
CPU time 9.02 seconds
Started Jul 22 04:43:11 PM PDT 24
Finished Jul 22 04:43:21 PM PDT 24
Peak memory 218312 kb
Host smart-ecbac621-bc7e-4c57-b6a7-c33f9a3d0a69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716894963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1716894963
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3126720693
Short name T566
Test name
Test status
Simulation time 252412753 ps
CPU time 6.93 seconds
Started Jul 22 04:43:11 PM PDT 24
Finished Jul 22 04:43:19 PM PDT 24
Peak memory 225532 kb
Host smart-d9793d07-15eb-4ceb-87a4-eabcdee89e75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126720693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
126720693
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.4172143815
Short name T751
Test name
Test status
Simulation time 216960589 ps
CPU time 8.85 seconds
Started Jul 22 04:43:10 PM PDT 24
Finished Jul 22 04:43:20 PM PDT 24
Peak memory 218060 kb
Host smart-37c20ef2-c957-4ede-9768-4d9ea33b1a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172143815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.4172143815
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.4109597215
Short name T328
Test name
Test status
Simulation time 276446657 ps
CPU time 1.74 seconds
Started Jul 22 04:43:09 PM PDT 24
Finished Jul 22 04:43:12 PM PDT 24
Peak memory 213584 kb
Host smart-f80b5176-deb3-4098-b1b0-6b171d5b9fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109597215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.4109597215
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2188117021
Short name T548
Test name
Test status
Simulation time 211145276 ps
CPU time 20.05 seconds
Started Jul 22 04:43:10 PM PDT 24
Finished Jul 22 04:43:31 PM PDT 24
Peak memory 250648 kb
Host smart-93a67723-91e3-4dca-a6b9-9bed5eeca9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188117021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2188117021
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.463904592
Short name T312
Test name
Test status
Simulation time 917647036 ps
CPU time 9.42 seconds
Started Jul 22 04:43:46 PM PDT 24
Finished Jul 22 04:43:56 PM PDT 24
Peak memory 250484 kb
Host smart-a797d5f9-891d-4fff-9040-bbe923df0ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463904592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.463904592
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3368330815
Short name T818
Test name
Test status
Simulation time 14613091999 ps
CPU time 198.26 seconds
Started Jul 22 04:43:17 PM PDT 24
Finished Jul 22 04:46:36 PM PDT 24
Peak memory 250556 kb
Host smart-d478c3be-7869-4cef-867a-e122221c6558
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368330815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3368330815
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.2131255835
Short name T95
Test name
Test status
Simulation time 22525976734 ps
CPU time 641 seconds
Started Jul 22 04:43:20 PM PDT 24
Finished Jul 22 04:54:01 PM PDT 24
Peak memory 268596 kb
Host smart-17728217-2b4c-40c7-9eb8-5de7bbd35ee2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2131255835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.2131255835
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1528041906
Short name T582
Test name
Test status
Simulation time 40573282 ps
CPU time 1.24 seconds
Started Jul 22 04:43:16 PM PDT 24
Finished Jul 22 04:43:18 PM PDT 24
Peak memory 208684 kb
Host smart-54067ca6-c6ee-4a64-993c-90478e8c0943
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528041906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1528041906
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1877389922
Short name T662
Test name
Test status
Simulation time 673906250 ps
CPU time 18.81 seconds
Started Jul 22 04:43:17 PM PDT 24
Finished Jul 22 04:43:36 PM PDT 24
Peak memory 218020 kb
Host smart-e71a0a2f-b37e-40c0-b7d9-74fa3fe45fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877389922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1877389922
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1033462744
Short name T710
Test name
Test status
Simulation time 749128334 ps
CPU time 5.23 seconds
Started Jul 22 04:43:34 PM PDT 24
Finished Jul 22 04:43:40 PM PDT 24
Peak memory 217096 kb
Host smart-8397dae5-3910-4b90-8bd3-ded20d1bc8ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033462744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1033462744
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3951615533
Short name T260
Test name
Test status
Simulation time 4258558265 ps
CPU time 55.97 seconds
Started Jul 22 04:43:23 PM PDT 24
Finished Jul 22 04:44:20 PM PDT 24
Peak memory 217984 kb
Host smart-7ccd95ed-4929-4d26-bcb2-020dfa76eb01
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951615533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3951615533
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.1682141766
Short name T153
Test name
Test status
Simulation time 1207615061 ps
CPU time 26.68 seconds
Started Jul 22 04:43:24 PM PDT 24
Finished Jul 22 04:43:51 PM PDT 24
Peak memory 217396 kb
Host smart-51b9625c-f3f1-4782-9880-5b658b5e5294
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682141766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.1
682141766
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.109055305
Short name T385
Test name
Test status
Simulation time 1593230580 ps
CPU time 12.67 seconds
Started Jul 22 04:43:17 PM PDT 24
Finished Jul 22 04:43:30 PM PDT 24
Peak memory 217900 kb
Host smart-98385946-3388-4604-a6fc-7c2f043e2448
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109055305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.109055305
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.342503339
Short name T845
Test name
Test status
Simulation time 2029108152 ps
CPU time 27.56 seconds
Started Jul 22 04:43:18 PM PDT 24
Finished Jul 22 04:43:46 PM PDT 24
Peak memory 217328 kb
Host smart-48e2024a-1a5a-41c2-8714-a352d59acee3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342503339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_regwen_during_op.342503339
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2779641693
Short name T679
Test name
Test status
Simulation time 1338821078 ps
CPU time 5.29 seconds
Started Jul 22 04:43:17 PM PDT 24
Finished Jul 22 04:43:23 PM PDT 24
Peak memory 217324 kb
Host smart-13b00fc2-80f1-4cff-a00f-5af8b5c72205
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779641693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2779641693
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3445876843
Short name T89
Test name
Test status
Simulation time 6157268183 ps
CPU time 56.86 seconds
Started Jul 22 04:43:17 PM PDT 24
Finished Jul 22 04:44:15 PM PDT 24
Peak memory 275348 kb
Host smart-4f3c6c9a-08d0-4933-8095-2f004182cf97
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445876843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3445876843
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2294448715
Short name T309
Test name
Test status
Simulation time 487452278 ps
CPU time 12.7 seconds
Started Jul 22 04:43:17 PM PDT 24
Finished Jul 22 04:43:31 PM PDT 24
Peak memory 222636 kb
Host smart-d12d9d8a-b9ca-4642-98d9-e5ceaab26411
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294448715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2294448715
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.394585209
Short name T386
Test name
Test status
Simulation time 47532104 ps
CPU time 2.34 seconds
Started Jul 22 04:43:17 PM PDT 24
Finished Jul 22 04:43:20 PM PDT 24
Peak memory 221856 kb
Host smart-6eebf4c5-8b97-42c8-a04d-87d087948d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394585209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.394585209
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.382023773
Short name T706
Test name
Test status
Simulation time 424569253 ps
CPU time 6.09 seconds
Started Jul 22 04:43:17 PM PDT 24
Finished Jul 22 04:43:23 PM PDT 24
Peak memory 217448 kb
Host smart-eb0a95e6-3bc1-421b-bb1b-d316191978aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382023773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.382023773
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3235390874
Short name T90
Test name
Test status
Simulation time 640356768 ps
CPU time 26.1 seconds
Started Jul 22 04:43:18 PM PDT 24
Finished Jul 22 04:43:45 PM PDT 24
Peak memory 268960 kb
Host smart-49678e28-ef17-4919-86d3-4c7b3b015528
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235390874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3235390874
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2954220320
Short name T343
Test name
Test status
Simulation time 843731056 ps
CPU time 19.58 seconds
Started Jul 22 04:43:17 PM PDT 24
Finished Jul 22 04:43:37 PM PDT 24
Peak memory 218044 kb
Host smart-c419ab9f-1f59-4a2b-922c-fab35eaced68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954220320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2954220320
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3853378976
Short name T43
Test name
Test status
Simulation time 229001309 ps
CPU time 8.91 seconds
Started Jul 22 04:43:24 PM PDT 24
Finished Jul 22 04:43:33 PM PDT 24
Peak memory 225724 kb
Host smart-19905f2d-6483-411b-a42d-e11f27dbe08e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853378976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
853378976
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3993036316
Short name T608
Test name
Test status
Simulation time 1199756596 ps
CPU time 8.77 seconds
Started Jul 22 04:43:20 PM PDT 24
Finished Jul 22 04:43:29 PM PDT 24
Peak memory 218044 kb
Host smart-edd8a1b6-81ff-41ef-8d9f-9f51b2e00b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993036316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3993036316
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3813291308
Short name T452
Test name
Test status
Simulation time 45049419 ps
CPU time 2.28 seconds
Started Jul 22 04:43:24 PM PDT 24
Finished Jul 22 04:43:27 PM PDT 24
Peak memory 214264 kb
Host smart-c33f52ff-cf4b-464b-a047-2e56fcd0d556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813291308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3813291308
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3723545096
Short name T526
Test name
Test status
Simulation time 1204397248 ps
CPU time 30.79 seconds
Started Jul 22 04:43:17 PM PDT 24
Finished Jul 22 04:43:48 PM PDT 24
Peak memory 250672 kb
Host smart-ff674c15-e562-4316-a03d-5c6ab5f1f412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723545096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3723545096
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2965376980
Short name T617
Test name
Test status
Simulation time 218933614 ps
CPU time 9.12 seconds
Started Jul 22 04:43:18 PM PDT 24
Finished Jul 22 04:43:28 PM PDT 24
Peak memory 250668 kb
Host smart-26bb2388-92ae-4885-858f-6c193eceac0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965376980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2965376980
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.4181441837
Short name T749
Test name
Test status
Simulation time 10283027645 ps
CPU time 74.01 seconds
Started Jul 22 04:43:24 PM PDT 24
Finished Jul 22 04:44:38 PM PDT 24
Peak memory 245692 kb
Host smart-dfbca64f-2c38-424c-a6fe-2ee6109af83a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181441837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.4181441837
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.335344921
Short name T40
Test name
Test status
Simulation time 15836717 ps
CPU time 1.03 seconds
Started Jul 22 04:43:19 PM PDT 24
Finished Jul 22 04:43:21 PM PDT 24
Peak memory 208748 kb
Host smart-4528f385-ad21-4bdf-925f-b2d67dca0ac5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335344921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr
l_volatile_unlock_smoke.335344921
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1938485345
Short name T359
Test name
Test status
Simulation time 38263724 ps
CPU time 1.15 seconds
Started Jul 22 04:44:32 PM PDT 24
Finished Jul 22 04:44:34 PM PDT 24
Peak memory 208672 kb
Host smart-e5dee5fe-d89d-47fe-ab63-028bf0b446b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938485345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1938485345
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.691487899
Short name T461
Test name
Test status
Simulation time 538566575 ps
CPU time 14.89 seconds
Started Jul 22 04:44:25 PM PDT 24
Finished Jul 22 04:44:40 PM PDT 24
Peak memory 218080 kb
Host smart-2a2c74ab-06ed-48db-8cb6-9a0ebbc25bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691487899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.691487899
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3734378697
Short name T344
Test name
Test status
Simulation time 3156929962 ps
CPU time 8.44 seconds
Started Jul 22 04:44:31 PM PDT 24
Finished Jul 22 04:44:40 PM PDT 24
Peak memory 217432 kb
Host smart-9dab07f6-d2d2-45c2-a09a-0d7eadf105d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734378697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3734378697
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.3047791276
Short name T595
Test name
Test status
Simulation time 2385927982 ps
CPU time 63.63 seconds
Started Jul 22 04:44:22 PM PDT 24
Finished Jul 22 04:45:26 PM PDT 24
Peak memory 218128 kb
Host smart-7b6fd60f-750b-49e8-9a5b-4ef95d0dbbf0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047791276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.3047791276
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2522876057
Short name T499
Test name
Test status
Simulation time 56123528 ps
CPU time 2.69 seconds
Started Jul 22 04:44:22 PM PDT 24
Finished Jul 22 04:44:25 PM PDT 24
Peak memory 221420 kb
Host smart-5b5e9b3e-7644-4d35-9fd6-b67ae95d132e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522876057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2522876057
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1462351444
Short name T572
Test name
Test status
Simulation time 174748440 ps
CPU time 2.4 seconds
Started Jul 22 04:44:22 PM PDT 24
Finished Jul 22 04:44:25 PM PDT 24
Peak memory 217324 kb
Host smart-6c845ed3-78c0-417e-9963-2719925fee44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462351444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1462351444
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3407494916
Short name T569
Test name
Test status
Simulation time 2806000429 ps
CPU time 47.24 seconds
Started Jul 22 04:44:21 PM PDT 24
Finished Jul 22 04:45:08 PM PDT 24
Peak memory 250716 kb
Host smart-8e660764-3bf5-4b56-bd83-01590cc3900f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407494916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3407494916
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.4245129239
Short name T758
Test name
Test status
Simulation time 3067427560 ps
CPU time 16.21 seconds
Started Jul 22 04:44:23 PM PDT 24
Finished Jul 22 04:44:40 PM PDT 24
Peak memory 250768 kb
Host smart-a1198f60-2926-40f5-86ac-6dce106d389f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245129239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.4245129239
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.4003799422
Short name T775
Test name
Test status
Simulation time 80785366 ps
CPU time 2.54 seconds
Started Jul 22 04:44:30 PM PDT 24
Finished Jul 22 04:44:33 PM PDT 24
Peak memory 218068 kb
Host smart-16fe5d21-0966-445d-828f-881a32575553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003799422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.4003799422
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.4070790353
Short name T494
Test name
Test status
Simulation time 810387892 ps
CPU time 16.37 seconds
Started Jul 22 04:44:36 PM PDT 24
Finished Jul 22 04:44:53 PM PDT 24
Peak memory 217992 kb
Host smart-7ca45b91-2ed8-435e-9dee-00acd561e9d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070790353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.4070790353
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1200393473
Short name T469
Test name
Test status
Simulation time 438265421 ps
CPU time 8.04 seconds
Started Jul 22 04:44:31 PM PDT 24
Finished Jul 22 04:44:39 PM PDT 24
Peak memory 225812 kb
Host smart-1b16def3-8250-49f1-a390-4a86c01bf8a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200393473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1200393473
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1651124623
Short name T240
Test name
Test status
Simulation time 278146905 ps
CPU time 11.76 seconds
Started Jul 22 04:44:23 PM PDT 24
Finished Jul 22 04:44:35 PM PDT 24
Peak memory 225104 kb
Host smart-ce2a9c7c-0622-4695-ab9c-4913ce7822b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651124623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1651124623
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.920569288
Short name T74
Test name
Test status
Simulation time 217410781 ps
CPU time 3.18 seconds
Started Jul 22 04:44:21 PM PDT 24
Finished Jul 22 04:44:25 PM PDT 24
Peak memory 217376 kb
Host smart-a1c4f88a-b130-4675-a822-57c50af69d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920569288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.920569288
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2441696619
Short name T660
Test name
Test status
Simulation time 464631400 ps
CPU time 25.56 seconds
Started Jul 22 04:44:21 PM PDT 24
Finished Jul 22 04:44:47 PM PDT 24
Peak memory 250724 kb
Host smart-51d6afdf-db5b-43d8-8cc6-ce95bd271f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441696619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2441696619
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.765321361
Short name T560
Test name
Test status
Simulation time 47647237 ps
CPU time 3.62 seconds
Started Jul 22 04:44:23 PM PDT 24
Finished Jul 22 04:44:28 PM PDT 24
Peak memory 222252 kb
Host smart-92bb0bf3-44d8-4050-84a8-31ebe6d37fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765321361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.765321361
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.944727414
Short name T588
Test name
Test status
Simulation time 30011458372 ps
CPU time 216.23 seconds
Started Jul 22 04:44:30 PM PDT 24
Finished Jul 22 04:48:07 PM PDT 24
Peak memory 221520 kb
Host smart-b8c281ad-ad6e-4498-b4bb-e3e2e7ad23f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944727414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.944727414
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3004287452
Short name T843
Test name
Test status
Simulation time 10353633 ps
CPU time 0.76 seconds
Started Jul 22 04:44:22 PM PDT 24
Finished Jul 22 04:44:24 PM PDT 24
Peak memory 207252 kb
Host smart-7f32e9a7-9c41-488b-90e5-3339714ecb46
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004287452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3004287452
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1396692147
Short name T444
Test name
Test status
Simulation time 14847364 ps
CPU time 0.88 seconds
Started Jul 22 04:44:44 PM PDT 24
Finished Jul 22 04:44:46 PM PDT 24
Peak memory 208440 kb
Host smart-3d14687c-5e30-4f62-aa37-f605777b9953
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396692147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1396692147
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2183681278
Short name T781
Test name
Test status
Simulation time 993867294 ps
CPU time 14.36 seconds
Started Jul 22 04:44:31 PM PDT 24
Finished Jul 22 04:44:46 PM PDT 24
Peak memory 218076 kb
Host smart-415e982a-bbf0-4701-aaa2-b1087f7e596c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183681278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2183681278
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3083972800
Short name T545
Test name
Test status
Simulation time 771064935 ps
CPU time 5.1 seconds
Started Jul 22 04:44:32 PM PDT 24
Finished Jul 22 04:44:38 PM PDT 24
Peak memory 222896 kb
Host smart-54b77e02-cc19-4273-a765-a0aa973a33e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083972800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.3083972800
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3331425544
Short name T718
Test name
Test status
Simulation time 133915697 ps
CPU time 3.42 seconds
Started Jul 22 04:44:34 PM PDT 24
Finished Jul 22 04:44:38 PM PDT 24
Peak memory 217420 kb
Host smart-65b8dff7-7b77-44c2-81f8-02072fa1ba49
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331425544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3331425544
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1087601523
Short name T705
Test name
Test status
Simulation time 8752643888 ps
CPU time 61.11 seconds
Started Jul 22 04:44:32 PM PDT 24
Finished Jul 22 04:45:33 PM PDT 24
Peak memory 268104 kb
Host smart-d83fe747-8564-4d8b-8696-9c970b1e3283
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087601523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.1087601523
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.132928108
Short name T341
Test name
Test status
Simulation time 1671240936 ps
CPU time 18.52 seconds
Started Jul 22 04:44:34 PM PDT 24
Finished Jul 22 04:44:53 PM PDT 24
Peak memory 250692 kb
Host smart-91cc9c89-144d-4cfa-9948-a57ab9f7451e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132928108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
jtag_state_post_trans.132928108
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.944634247
Short name T419
Test name
Test status
Simulation time 334278286 ps
CPU time 3.19 seconds
Started Jul 22 04:44:33 PM PDT 24
Finished Jul 22 04:44:37 PM PDT 24
Peak memory 222168 kb
Host smart-d3ee2860-9b3d-4476-a852-b02fd38fa99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944634247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.944634247
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2868905205
Short name T155
Test name
Test status
Simulation time 3026229309 ps
CPU time 14.92 seconds
Started Jul 22 04:44:33 PM PDT 24
Finished Jul 22 04:44:49 PM PDT 24
Peak memory 219272 kb
Host smart-352cb75f-877a-411e-be5a-7768b6c8bf1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868905205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2868905205
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3436028611
Short name T305
Test name
Test status
Simulation time 346315574 ps
CPU time 11.85 seconds
Started Jul 22 04:44:31 PM PDT 24
Finished Jul 22 04:44:44 PM PDT 24
Peak memory 217916 kb
Host smart-9bee59c9-1a57-44c7-a7da-26b7118aea89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436028611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3436028611
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3010326735
Short name T430
Test name
Test status
Simulation time 638207962 ps
CPU time 7.43 seconds
Started Jul 22 04:44:33 PM PDT 24
Finished Jul 22 04:44:41 PM PDT 24
Peak memory 225188 kb
Host smart-baa0b804-afa0-4a44-b587-9624982c53eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010326735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3010326735
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2548589566
Short name T763
Test name
Test status
Simulation time 894550645 ps
CPU time 9.1 seconds
Started Jul 22 04:44:32 PM PDT 24
Finished Jul 22 04:44:42 PM PDT 24
Peak memory 224432 kb
Host smart-874093f4-b7a8-4bd8-a956-31719e664584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548589566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2548589566
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3068276131
Short name T502
Test name
Test status
Simulation time 240888317 ps
CPU time 2.03 seconds
Started Jul 22 04:44:35 PM PDT 24
Finished Jul 22 04:44:38 PM PDT 24
Peak memory 213896 kb
Host smart-a1ea1a22-f0c1-4cf3-9943-a29bf0c1ce7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068276131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3068276131
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.549217831
Short name T283
Test name
Test status
Simulation time 720969175 ps
CPU time 40.41 seconds
Started Jul 22 04:44:33 PM PDT 24
Finished Jul 22 04:45:14 PM PDT 24
Peak memory 250656 kb
Host smart-78140254-027a-491b-a5bd-e2a4956320af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549217831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.549217831
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1138297357
Short name T247
Test name
Test status
Simulation time 275619110 ps
CPU time 5.96 seconds
Started Jul 22 04:44:31 PM PDT 24
Finished Jul 22 04:44:37 PM PDT 24
Peak memory 250148 kb
Host smart-cf97d4d2-a335-4170-b6fa-895ae4c56699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138297357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1138297357
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2785388327
Short name T692
Test name
Test status
Simulation time 2494056061 ps
CPU time 24.89 seconds
Started Jul 22 04:44:33 PM PDT 24
Finished Jul 22 04:44:58 PM PDT 24
Peak memory 236172 kb
Host smart-1c55bb26-8d99-40c0-96f3-ce246bc45e30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785388327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2785388327
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.1126601642
Short name T148
Test name
Test status
Simulation time 27688217800 ps
CPU time 531.95 seconds
Started Jul 22 04:44:31 PM PDT 24
Finished Jul 22 04:53:24 PM PDT 24
Peak memory 447556 kb
Host smart-d38c94a6-f91e-4202-9064-1664a00945ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1126601642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.1126601642
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.816317203
Short name T695
Test name
Test status
Simulation time 51972860 ps
CPU time 0.89 seconds
Started Jul 22 04:44:31 PM PDT 24
Finished Jul 22 04:44:32 PM PDT 24
Peak memory 211668 kb
Host smart-dd8d5eb5-02cd-4732-9946-8d86b390c66c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816317203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_volatile_unlock_smoke.816317203
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.4232209633
Short name T594
Test name
Test status
Simulation time 16628643 ps
CPU time 1.11 seconds
Started Jul 22 04:44:39 PM PDT 24
Finished Jul 22 04:44:41 PM PDT 24
Peak memory 208672 kb
Host smart-9dd59f17-d4ae-4ffa-a49f-87f845d55ff6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232209633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.4232209633
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.260290117
Short name T857
Test name
Test status
Simulation time 810187633 ps
CPU time 13.48 seconds
Started Jul 22 04:44:45 PM PDT 24
Finished Jul 22 04:44:59 PM PDT 24
Peak memory 218080 kb
Host smart-aaa58d22-78be-4d8c-b66b-5b001b6f4947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260290117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.260290117
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1136332860
Short name T552
Test name
Test status
Simulation time 89007016 ps
CPU time 2.69 seconds
Started Jul 22 04:44:39 PM PDT 24
Finished Jul 22 04:44:42 PM PDT 24
Peak memory 216960 kb
Host smart-54214a7f-8cfb-4b70-95b8-0a31c153ca1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136332860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1136332860
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.606843333
Short name T19
Test name
Test status
Simulation time 5376283156 ps
CPU time 37.7 seconds
Started Jul 22 04:44:40 PM PDT 24
Finished Jul 22 04:45:18 PM PDT 24
Peak memory 218728 kb
Host smart-19a0b996-a181-48d5-a92e-4ca0f0d6f085
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606843333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er
rors.606843333
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.939697746
Short name T616
Test name
Test status
Simulation time 119946046 ps
CPU time 3.09 seconds
Started Jul 22 04:44:40 PM PDT 24
Finished Jul 22 04:44:44 PM PDT 24
Peak memory 221640 kb
Host smart-a9b22eb0-8378-4e48-a95b-4377cb402419
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939697746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.939697746
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1338611568
Short name T5
Test name
Test status
Simulation time 595565485 ps
CPU time 4.13 seconds
Started Jul 22 04:44:31 PM PDT 24
Finished Jul 22 04:44:36 PM PDT 24
Peak memory 217300 kb
Host smart-667c0d84-f1a1-4978-896d-37825190a7ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338611568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1338611568
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3082851144
Short name T314
Test name
Test status
Simulation time 3888790229 ps
CPU time 36.71 seconds
Started Jul 22 04:44:41 PM PDT 24
Finished Jul 22 04:45:19 PM PDT 24
Peak memory 250828 kb
Host smart-8773969f-25e1-48cf-9bb0-ffb382ff92f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082851144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3082851144
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.902127838
Short name T602
Test name
Test status
Simulation time 2553101853 ps
CPU time 16.07 seconds
Started Jul 22 04:44:45 PM PDT 24
Finished Jul 22 04:45:01 PM PDT 24
Peak memory 250224 kb
Host smart-d8b46721-df68-43ec-be33-20c4ea2d22e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902127838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.902127838
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1115670542
Short name T814
Test name
Test status
Simulation time 101530899 ps
CPU time 4.22 seconds
Started Jul 22 04:44:46 PM PDT 24
Finished Jul 22 04:44:51 PM PDT 24
Peak memory 218080 kb
Host smart-cfd7b654-1bb0-4bca-8d8f-67b195ff2be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115670542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1115670542
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2255365857
Short name T626
Test name
Test status
Simulation time 1041375039 ps
CPU time 12.78 seconds
Started Jul 22 04:44:44 PM PDT 24
Finished Jul 22 04:44:57 PM PDT 24
Peak memory 218728 kb
Host smart-e41b5b41-96f9-410d-aaf0-366f97549a80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255365857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2255365857
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.4259090269
Short name T585
Test name
Test status
Simulation time 698762793 ps
CPU time 10.27 seconds
Started Jul 22 04:44:45 PM PDT 24
Finished Jul 22 04:44:56 PM PDT 24
Peak memory 217984 kb
Host smart-bb6a3a79-a4e5-497a-82b2-0f4da028e9ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259090269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.4259090269
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.319854238
Short name T680
Test name
Test status
Simulation time 231982614 ps
CPU time 8.83 seconds
Started Jul 22 04:44:39 PM PDT 24
Finished Jul 22 04:44:49 PM PDT 24
Peak memory 217924 kb
Host smart-74a9387e-2dd3-4c30-80f1-46154b05aba7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319854238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.319854238
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.760471856
Short name T426
Test name
Test status
Simulation time 1165071657 ps
CPU time 8.56 seconds
Started Jul 22 04:44:34 PM PDT 24
Finished Jul 22 04:44:43 PM PDT 24
Peak memory 218044 kb
Host smart-9304d1a2-605e-4b1b-beb3-1477ad95bb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760471856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.760471856
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.843317952
Short name T800
Test name
Test status
Simulation time 73008599 ps
CPU time 2.29 seconds
Started Jul 22 04:44:33 PM PDT 24
Finished Jul 22 04:44:36 PM PDT 24
Peak memory 213848 kb
Host smart-c6b02a8e-be1f-47a5-97af-bd9b2f278f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843317952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.843317952
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.510078058
Short name T505
Test name
Test status
Simulation time 1089457150 ps
CPU time 28.76 seconds
Started Jul 22 04:44:35 PM PDT 24
Finished Jul 22 04:45:05 PM PDT 24
Peak memory 250756 kb
Host smart-274d2992-683e-4cc0-aad0-0f25c154669e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510078058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.510078058
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2041489966
Short name T442
Test name
Test status
Simulation time 127888080 ps
CPU time 6.95 seconds
Started Jul 22 04:44:48 PM PDT 24
Finished Jul 22 04:44:56 PM PDT 24
Peak memory 246632 kb
Host smart-a223dfb0-0ad9-41be-a51e-8b553b017b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041489966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2041489966
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.284217601
Short name T581
Test name
Test status
Simulation time 26232048584 ps
CPU time 243.05 seconds
Started Jul 22 04:44:38 PM PDT 24
Finished Jul 22 04:48:42 PM PDT 24
Peak memory 270092 kb
Host smart-31721521-6054-43b5-8ef7-1e9f04b4e24e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284217601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.284217601
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.1195289485
Short name T417
Test name
Test status
Simulation time 114301807058 ps
CPU time 414.05 seconds
Started Jul 22 04:44:42 PM PDT 24
Finished Jul 22 04:51:37 PM PDT 24
Peak memory 277632 kb
Host smart-98a9d09d-7c49-4ec5-8118-93a965d2800c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1195289485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.1195289485
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1508798925
Short name T683
Test name
Test status
Simulation time 41324147 ps
CPU time 0.86 seconds
Started Jul 22 04:44:32 PM PDT 24
Finished Jul 22 04:44:33 PM PDT 24
Peak memory 208864 kb
Host smart-c01a9717-b384-4a7e-a29c-75c2e7346718
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508798925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1508798925
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.484159574
Short name T401
Test name
Test status
Simulation time 17791174 ps
CPU time 1.03 seconds
Started Jul 22 04:44:47 PM PDT 24
Finished Jul 22 04:44:48 PM PDT 24
Peak memory 208464 kb
Host smart-d3df0048-9a9e-417e-a619-5f2bcc279cb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484159574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.484159574
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.843971797
Short name T690
Test name
Test status
Simulation time 605851498 ps
CPU time 9.25 seconds
Started Jul 22 04:44:53 PM PDT 24
Finished Jul 22 04:45:02 PM PDT 24
Peak memory 218048 kb
Host smart-7b0dcdf9-285f-48e6-90c4-2f87d698cfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843971797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.843971797
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.486287738
Short name T791
Test name
Test status
Simulation time 1704370855 ps
CPU time 2.01 seconds
Started Jul 22 04:44:38 PM PDT 24
Finished Jul 22 04:44:40 PM PDT 24
Peak memory 216876 kb
Host smart-f9a5d4cd-15ab-420a-a044-5ddc0e852cd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486287738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.486287738
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3328042143
Short name T44
Test name
Test status
Simulation time 1323945506 ps
CPU time 43 seconds
Started Jul 22 04:44:41 PM PDT 24
Finished Jul 22 04:45:25 PM PDT 24
Peak memory 218576 kb
Host smart-7a409000-b327-414a-92db-1a76c16a0c62
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328042143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3328042143
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2809052366
Short name T239
Test name
Test status
Simulation time 2185129975 ps
CPU time 12.29 seconds
Started Jul 22 04:44:38 PM PDT 24
Finished Jul 22 04:44:51 PM PDT 24
Peak memory 223056 kb
Host smart-ded2eed5-e900-4c81-b8c0-d101d1336d3a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809052366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2809052366
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2733955149
Short name T415
Test name
Test status
Simulation time 2270329256 ps
CPU time 13.77 seconds
Started Jul 22 04:44:40 PM PDT 24
Finished Jul 22 04:44:54 PM PDT 24
Peak memory 217348 kb
Host smart-0e7a0864-98de-4879-81af-7786a56dfa05
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733955149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2733955149
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2564434938
Short name T279
Test name
Test status
Simulation time 2070921739 ps
CPU time 70.31 seconds
Started Jul 22 04:44:45 PM PDT 24
Finished Jul 22 04:45:56 PM PDT 24
Peak memory 275196 kb
Host smart-bb3d5570-1a1f-4be2-9695-2d4b2d4b17fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564434938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2564434938
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2270702295
Short name T418
Test name
Test status
Simulation time 448458270 ps
CPU time 12.45 seconds
Started Jul 22 04:44:37 PM PDT 24
Finished Jul 22 04:44:50 PM PDT 24
Peak memory 250628 kb
Host smart-306e5462-7bec-4473-929e-3329c1fc3f66
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270702295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2270702295
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3002630546
Short name T838
Test name
Test status
Simulation time 810315664 ps
CPU time 3.96 seconds
Started Jul 22 04:44:39 PM PDT 24
Finished Jul 22 04:44:44 PM PDT 24
Peak memory 217984 kb
Host smart-77e39e85-8173-4af5-aa8f-ac2821607082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002630546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3002630546
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2868867244
Short name T228
Test name
Test status
Simulation time 466392246 ps
CPU time 12.55 seconds
Started Jul 22 04:44:41 PM PDT 24
Finished Jul 22 04:44:54 PM PDT 24
Peak memory 218052 kb
Host smart-3b176b99-65cd-4637-84f7-75b6b02f260a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868867244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2868867244
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2635356845
Short name T831
Test name
Test status
Simulation time 683374703 ps
CPU time 15.59 seconds
Started Jul 22 04:44:40 PM PDT 24
Finished Jul 22 04:44:56 PM PDT 24
Peak memory 225196 kb
Host smart-adcf0686-6af7-459b-b5af-0a344f07916d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635356845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2635356845
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2246896898
Short name T504
Test name
Test status
Simulation time 83521413 ps
CPU time 1.63 seconds
Started Jul 22 04:44:39 PM PDT 24
Finished Jul 22 04:44:41 PM PDT 24
Peak memory 217472 kb
Host smart-f251160f-8d0c-4074-b249-9efacff7bff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246896898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2246896898
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1603205933
Short name T15
Test name
Test status
Simulation time 434513925 ps
CPU time 17.47 seconds
Started Jul 22 04:44:44 PM PDT 24
Finished Jul 22 04:45:02 PM PDT 24
Peak memory 250676 kb
Host smart-c19059a8-2f66-44fa-88d9-e28eee5130c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603205933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1603205933
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1532554934
Short name T413
Test name
Test status
Simulation time 444095269 ps
CPU time 5.22 seconds
Started Jul 22 04:45:02 PM PDT 24
Finished Jul 22 04:45:08 PM PDT 24
Peak memory 222596 kb
Host smart-36bf52d0-6fe5-4e2c-828c-fbb7157f5d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532554934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1532554934
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.594773877
Short name T38
Test name
Test status
Simulation time 8322429443 ps
CPU time 72.85 seconds
Started Jul 22 04:44:46 PM PDT 24
Finished Jul 22 04:45:59 PM PDT 24
Peak memory 250776 kb
Host smart-7532d9f6-d658-4e10-a0de-fe328378e6a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594773877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.594773877
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3235459329
Short name T637
Test name
Test status
Simulation time 13264049 ps
CPU time 1.1 seconds
Started Jul 22 04:44:41 PM PDT 24
Finished Jul 22 04:44:43 PM PDT 24
Peak memory 211636 kb
Host smart-57282b12-28a7-450f-a55b-0119ce8858f4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235459329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3235459329
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2526199658
Short name T298
Test name
Test status
Simulation time 30193676 ps
CPU time 0.95 seconds
Started Jul 22 04:44:50 PM PDT 24
Finished Jul 22 04:44:52 PM PDT 24
Peak memory 208568 kb
Host smart-71c66f17-4e68-4244-a387-16fe978e92d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526199658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2526199658
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3750516860
Short name T618
Test name
Test status
Simulation time 326535825 ps
CPU time 16.17 seconds
Started Jul 22 04:44:48 PM PDT 24
Finished Jul 22 04:45:05 PM PDT 24
Peak memory 218072 kb
Host smart-05824ef1-8139-4749-b37f-74b18a26ece2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750516860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3750516860
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2340868011
Short name T531
Test name
Test status
Simulation time 523301472 ps
CPU time 2.79 seconds
Started Jul 22 04:44:48 PM PDT 24
Finished Jul 22 04:44:52 PM PDT 24
Peak memory 216840 kb
Host smart-a2e44f53-7554-40df-89e1-abfb7a1ed2e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340868011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2340868011
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.635650885
Short name T518
Test name
Test status
Simulation time 1789382073 ps
CPU time 19.37 seconds
Started Jul 22 04:44:48 PM PDT 24
Finished Jul 22 04:45:08 PM PDT 24
Peak memory 217996 kb
Host smart-7c7dfa42-a886-4572-9b63-4e5029ea4018
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635650885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.635650885
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.445476505
Short name T516
Test name
Test status
Simulation time 350858421 ps
CPU time 11.91 seconds
Started Jul 22 04:44:50 PM PDT 24
Finished Jul 22 04:45:02 PM PDT 24
Peak memory 223412 kb
Host smart-166db407-f5a4-437d-b170-def37fc61dea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445476505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.445476505
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.39746635
Short name T361
Test name
Test status
Simulation time 137796061 ps
CPU time 3.93 seconds
Started Jul 22 04:44:48 PM PDT 24
Finished Jul 22 04:44:52 PM PDT 24
Peak memory 217476 kb
Host smart-8673fd93-1f12-4337-a197-1e233b77cdbf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39746635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.39746635
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1404508650
Short name T495
Test name
Test status
Simulation time 6712943390 ps
CPU time 39.81 seconds
Started Jul 22 04:44:49 PM PDT 24
Finished Jul 22 04:45:29 PM PDT 24
Peak memory 251724 kb
Host smart-998f5f68-2142-46d4-a033-94b5a4d9752d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404508650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1404508650
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2831895793
Short name T600
Test name
Test status
Simulation time 794922983 ps
CPU time 17.73 seconds
Started Jul 22 04:45:10 PM PDT 24
Finished Jul 22 04:45:29 PM PDT 24
Peak memory 250708 kb
Host smart-b915bc0d-04b6-4ee2-b2e5-9c7f97ae9c32
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831895793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2831895793
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2999423295
Short name T313
Test name
Test status
Simulation time 188732316 ps
CPU time 3.73 seconds
Started Jul 22 04:44:57 PM PDT 24
Finished Jul 22 04:45:02 PM PDT 24
Peak memory 222156 kb
Host smart-048747ab-c6a0-473e-a796-b38780ab5429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999423295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2999423295
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.3450510287
Short name T91
Test name
Test status
Simulation time 352040530 ps
CPU time 12.96 seconds
Started Jul 22 04:45:05 PM PDT 24
Finished Jul 22 04:45:19 PM PDT 24
Peak memory 218624 kb
Host smart-7286cec7-9ef5-4933-b5dc-cf0504876aa2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450510287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3450510287
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.4161688569
Short name T565
Test name
Test status
Simulation time 230913162 ps
CPU time 10.11 seconds
Started Jul 22 04:44:51 PM PDT 24
Finished Jul 22 04:45:02 PM PDT 24
Peak memory 225720 kb
Host smart-e73f8245-18a5-41dd-9e6e-98deeb7c585f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161688569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.4161688569
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2176085540
Short name T466
Test name
Test status
Simulation time 276996228 ps
CPU time 9.03 seconds
Started Jul 22 04:44:53 PM PDT 24
Finished Jul 22 04:45:02 PM PDT 24
Peak memory 225816 kb
Host smart-14a7ea62-6412-4e93-8317-2cc8bcb96945
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176085540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2176085540
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1631658463
Short name T64
Test name
Test status
Simulation time 3455052705 ps
CPU time 7.15 seconds
Started Jul 22 04:44:47 PM PDT 24
Finished Jul 22 04:44:55 PM PDT 24
Peak memory 225936 kb
Host smart-b62bc686-ec32-4057-8bb3-90768b223dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631658463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1631658463
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2391077942
Short name T185
Test name
Test status
Simulation time 21381708 ps
CPU time 1.56 seconds
Started Jul 22 04:44:41 PM PDT 24
Finished Jul 22 04:44:43 PM PDT 24
Peak memory 213696 kb
Host smart-8753bdf2-f15d-4f3b-8d8d-60ac8df20722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391077942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2391077942
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.372405598
Short name T330
Test name
Test status
Simulation time 859211594 ps
CPU time 22.08 seconds
Started Jul 22 04:44:46 PM PDT 24
Finished Jul 22 04:45:09 PM PDT 24
Peak memory 250660 kb
Host smart-bb9ad49c-ed58-4661-a35d-f3654de91074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372405598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.372405598
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.4101659831
Short name T534
Test name
Test status
Simulation time 383368337 ps
CPU time 8.21 seconds
Started Jul 22 04:44:48 PM PDT 24
Finished Jul 22 04:44:57 PM PDT 24
Peak memory 250756 kb
Host smart-754c27e6-cb77-4b82-93ce-6ac3edde5e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101659831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.4101659831
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1227545784
Short name T163
Test name
Test status
Simulation time 39668141 ps
CPU time 0.82 seconds
Started Jul 22 04:44:40 PM PDT 24
Finished Jul 22 04:44:41 PM PDT 24
Peak memory 208564 kb
Host smart-37976f63-f1c4-47fd-9f87-78d23cba4716
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227545784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1227545784
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.4057517865
Short name T528
Test name
Test status
Simulation time 24412251 ps
CPU time 0.84 seconds
Started Jul 22 04:44:59 PM PDT 24
Finished Jul 22 04:45:00 PM PDT 24
Peak memory 208460 kb
Host smart-618eea3e-1a0f-410c-9a6f-ee6ee876c6b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057517865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.4057517865
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1884083578
Short name T281
Test name
Test status
Simulation time 734202413 ps
CPU time 12.74 seconds
Started Jul 22 04:44:53 PM PDT 24
Finished Jul 22 04:45:06 PM PDT 24
Peak memory 218088 kb
Host smart-b42d9b49-7a62-4b19-898b-46dfa868c061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884083578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1884083578
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2403120118
Short name T650
Test name
Test status
Simulation time 364577568 ps
CPU time 4.99 seconds
Started Jul 22 04:45:14 PM PDT 24
Finished Jul 22 04:45:19 PM PDT 24
Peak memory 216956 kb
Host smart-b08eb462-786f-4fca-98c2-839317825ee8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403120118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2403120118
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1571607114
Short name T21
Test name
Test status
Simulation time 1457442268 ps
CPU time 25.57 seconds
Started Jul 22 04:45:02 PM PDT 24
Finished Jul 22 04:45:28 PM PDT 24
Peak memory 218076 kb
Host smart-74200d35-9498-482c-8b82-d4828309dc00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571607114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1571607114
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2596114473
Short name T362
Test name
Test status
Simulation time 355757009 ps
CPU time 6.44 seconds
Started Jul 22 04:44:57 PM PDT 24
Finished Jul 22 04:45:04 PM PDT 24
Peak memory 221764 kb
Host smart-35a3f0a6-6f40-474e-8900-074f9a8f3011
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596114473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2596114473
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1130647744
Short name T16
Test name
Test status
Simulation time 947853011 ps
CPU time 8.78 seconds
Started Jul 22 04:44:49 PM PDT 24
Finished Jul 22 04:44:58 PM PDT 24
Peak memory 217328 kb
Host smart-f257ab6d-6199-4423-8b66-48fa8ded4a36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130647744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1130647744
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1868736654
Short name T420
Test name
Test status
Simulation time 1148079106 ps
CPU time 31.24 seconds
Started Jul 22 04:44:50 PM PDT 24
Finished Jul 22 04:45:22 PM PDT 24
Peak memory 275160 kb
Host smart-c5e59c54-3ce8-4027-a8f7-6bf2c1855333
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868736654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1868736654
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.4289403870
Short name T606
Test name
Test status
Simulation time 373222071 ps
CPU time 11.61 seconds
Started Jul 22 04:44:52 PM PDT 24
Finished Jul 22 04:45:04 PM PDT 24
Peak memory 250716 kb
Host smart-e1921a75-de95-47aa-b57e-72dba20d3ade
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289403870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.4289403870
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.634076396
Short name T258
Test name
Test status
Simulation time 46795525 ps
CPU time 2.62 seconds
Started Jul 22 04:47:35 PM PDT 24
Finished Jul 22 04:47:38 PM PDT 24
Peak memory 222148 kb
Host smart-4f92fe41-43fc-4df4-8123-47ea297f544b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634076396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.634076396
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.3795434346
Short name T438
Test name
Test status
Simulation time 1737706340 ps
CPU time 12.04 seconds
Started Jul 22 04:44:59 PM PDT 24
Finished Jul 22 04:45:12 PM PDT 24
Peak memory 218084 kb
Host smart-c5c34a75-d53f-4551-a204-0cc13a516dc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795434346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3795434346
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2601794358
Short name T764
Test name
Test status
Simulation time 3063853063 ps
CPU time 12 seconds
Started Jul 22 04:44:58 PM PDT 24
Finished Jul 22 04:45:10 PM PDT 24
Peak memory 218000 kb
Host smart-98998671-7d82-462a-b99d-5c063d147c67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601794358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2601794358
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1707367810
Short name T498
Test name
Test status
Simulation time 2483900999 ps
CPU time 16.05 seconds
Started Jul 22 04:44:58 PM PDT 24
Finished Jul 22 04:45:14 PM PDT 24
Peak memory 225716 kb
Host smart-fca3f22e-ac0c-42e0-ae07-93ee292e924e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707367810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1707367810
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2461577080
Short name T636
Test name
Test status
Simulation time 780080003 ps
CPU time 9.22 seconds
Started Jul 22 04:47:35 PM PDT 24
Finished Jul 22 04:47:44 PM PDT 24
Peak memory 225760 kb
Host smart-d3db8889-4f85-40dd-a17a-b4cf526487ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461577080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2461577080
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1124785875
Short name T844
Test name
Test status
Simulation time 76379898 ps
CPU time 2.89 seconds
Started Jul 22 04:44:49 PM PDT 24
Finished Jul 22 04:44:52 PM PDT 24
Peak memory 214196 kb
Host smart-1ee7e7fa-bc5b-4c4e-a235-68adc4ffefec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124785875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1124785875
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1489694139
Short name T96
Test name
Test status
Simulation time 91326469 ps
CPU time 4.52 seconds
Started Jul 22 04:44:49 PM PDT 24
Finished Jul 22 04:44:54 PM PDT 24
Peak memory 226056 kb
Host smart-6267f836-1dcc-4557-84c1-310869fe71e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489694139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1489694139
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3522530089
Short name T746
Test name
Test status
Simulation time 5938308955 ps
CPU time 168.96 seconds
Started Jul 22 04:45:02 PM PDT 24
Finished Jul 22 04:47:52 PM PDT 24
Peak memory 266772 kb
Host smart-be8718e2-d1c5-4672-8104-f251e0e8d258
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522530089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3522530089
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3676485007
Short name T405
Test name
Test status
Simulation time 14318344 ps
CPU time 0.99 seconds
Started Jul 22 04:44:51 PM PDT 24
Finished Jul 22 04:44:52 PM PDT 24
Peak memory 208952 kb
Host smart-3323f203-fc93-40f7-830b-5d09b2698515
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676485007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3676485007
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2263944243
Short name T71
Test name
Test status
Simulation time 22403913 ps
CPU time 1.27 seconds
Started Jul 22 04:45:09 PM PDT 24
Finished Jul 22 04:45:11 PM PDT 24
Peak memory 208620 kb
Host smart-318a111f-6462-4ec0-a3b1-7f3909ab135d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263944243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2263944243
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3312222910
Short name T777
Test name
Test status
Simulation time 2117328112 ps
CPU time 12.14 seconds
Started Jul 22 04:44:57 PM PDT 24
Finished Jul 22 04:45:10 PM PDT 24
Peak memory 218116 kb
Host smart-92198a95-543f-4a8d-9201-ac307e5f22fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312222910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3312222910
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.451742199
Short name T646
Test name
Test status
Simulation time 961516288 ps
CPU time 9.55 seconds
Started Jul 22 04:45:09 PM PDT 24
Finished Jul 22 04:45:19 PM PDT 24
Peak memory 216916 kb
Host smart-047ad81a-efe9-4219-a198-2b2cbf39b76f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451742199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.451742199
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2561670819
Short name T614
Test name
Test status
Simulation time 17513951702 ps
CPU time 35.12 seconds
Started Jul 22 04:44:59 PM PDT 24
Finished Jul 22 04:45:35 PM PDT 24
Peak memory 218720 kb
Host smart-d7de44d5-fe26-4b9f-b016-1394c1bd9f33
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561670819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2561670819
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1987781777
Short name T641
Test name
Test status
Simulation time 73839720 ps
CPU time 2.17 seconds
Started Jul 22 04:45:03 PM PDT 24
Finished Jul 22 04:45:05 PM PDT 24
Peak memory 221200 kb
Host smart-471deff5-7d80-4eb5-9a7b-a899c39d337d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987781777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1987781777
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2801272889
Short name T779
Test name
Test status
Simulation time 300396159 ps
CPU time 5.64 seconds
Started Jul 22 04:45:03 PM PDT 24
Finished Jul 22 04:45:09 PM PDT 24
Peak memory 217420 kb
Host smart-330d2766-0879-40ff-a745-5f270f864c62
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801272889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2801272889
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.445091409
Short name T734
Test name
Test status
Simulation time 6765112718 ps
CPU time 44.33 seconds
Started Jul 22 04:45:01 PM PDT 24
Finished Jul 22 04:45:46 PM PDT 24
Peak memory 269540 kb
Host smart-d511b2ce-1a8f-4b25-b784-7fd9a4632784
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445091409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.445091409
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3578517046
Short name T745
Test name
Test status
Simulation time 386200494 ps
CPU time 15.39 seconds
Started Jul 22 04:45:00 PM PDT 24
Finished Jul 22 04:45:16 PM PDT 24
Peak memory 246992 kb
Host smart-b650e844-e3b6-4bd8-8bca-1ad4acf61737
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578517046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3578517046
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3724659754
Short name T675
Test name
Test status
Simulation time 364720176 ps
CPU time 2.14 seconds
Started Jul 22 04:44:59 PM PDT 24
Finished Jul 22 04:45:02 PM PDT 24
Peak memory 222132 kb
Host smart-32574010-ad9e-4618-92c2-512fe5c4fb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724659754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3724659754
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1955951461
Short name T720
Test name
Test status
Simulation time 438668101 ps
CPU time 17.26 seconds
Started Jul 22 04:44:59 PM PDT 24
Finished Jul 22 04:45:16 PM PDT 24
Peak memory 218116 kb
Host smart-c89e6ed2-b161-46d2-b8a4-e96e709d24bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955951461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1955951461
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2919878768
Short name T584
Test name
Test status
Simulation time 213691803 ps
CPU time 9.32 seconds
Started Jul 22 04:44:57 PM PDT 24
Finished Jul 22 04:45:07 PM PDT 24
Peak memory 218064 kb
Host smart-73387006-9c94-4fdf-b91f-5fd3d3c82644
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919878768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2919878768
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2249261352
Short name T371
Test name
Test status
Simulation time 1325608901 ps
CPU time 12.56 seconds
Started Jul 22 04:45:00 PM PDT 24
Finished Jul 22 04:45:13 PM PDT 24
Peak memory 218100 kb
Host smart-06441d78-a124-4793-90cc-a4f98d8066ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249261352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2249261352
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2633075727
Short name T76
Test name
Test status
Simulation time 279364269 ps
CPU time 4.13 seconds
Started Jul 22 04:44:59 PM PDT 24
Finished Jul 22 04:45:04 PM PDT 24
Peak memory 217616 kb
Host smart-495a2124-e2ff-477d-9ab4-0ea592ed19ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633075727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2633075727
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.4209961641
Short name T456
Test name
Test status
Simulation time 1341263991 ps
CPU time 33.45 seconds
Started Jul 22 04:45:02 PM PDT 24
Finished Jul 22 04:45:36 PM PDT 24
Peak memory 250644 kb
Host smart-8533a332-04b4-4e64-b38c-c8a756206dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209961641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.4209961641
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.4004799980
Short name T748
Test name
Test status
Simulation time 184843246 ps
CPU time 8.26 seconds
Started Jul 22 04:45:00 PM PDT 24
Finished Jul 22 04:45:09 PM PDT 24
Peak memory 250680 kb
Host smart-e066e05e-6408-4f2f-abbe-ddf8b309d070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004799980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.4004799980
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.961170302
Short name T480
Test name
Test status
Simulation time 7603906361 ps
CPU time 60.68 seconds
Started Jul 22 04:45:09 PM PDT 24
Finished Jul 22 04:46:10 PM PDT 24
Peak memory 250736 kb
Host smart-ca85d957-00ee-421e-96a5-293366b6bdc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961170302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.961170302
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.2897486933
Short name T136
Test name
Test status
Simulation time 27170012897 ps
CPU time 561.47 seconds
Started Jul 22 04:45:13 PM PDT 24
Finished Jul 22 04:54:35 PM PDT 24
Peak memory 261764 kb
Host smart-4c82f05b-7e08-4990-ad09-0e567d12e7de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2897486933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.2897486933
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.51223043
Short name T244
Test name
Test status
Simulation time 18574020 ps
CPU time 0.9 seconds
Started Jul 22 04:44:59 PM PDT 24
Finished Jul 22 04:45:00 PM PDT 24
Peak memory 208632 kb
Host smart-7d967503-de7a-4105-89ef-122a35c8caf1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51223043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_volatile_unlock_smoke.51223043
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1275475979
Short name T396
Test name
Test status
Simulation time 57664276 ps
CPU time 0.97 seconds
Started Jul 22 04:45:11 PM PDT 24
Finished Jul 22 04:45:12 PM PDT 24
Peak memory 208584 kb
Host smart-3153ba4c-20a0-41d2-96c3-88bddc3afc10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275475979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1275475979
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1095401669
Short name T826
Test name
Test status
Simulation time 556512075 ps
CPU time 13.49 seconds
Started Jul 22 04:45:10 PM PDT 24
Finished Jul 22 04:45:24 PM PDT 24
Peak memory 225792 kb
Host smart-8f033598-d9b8-4058-9c3f-163678e9ecd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095401669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1095401669
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3024407169
Short name T269
Test name
Test status
Simulation time 1223355480 ps
CPU time 3.22 seconds
Started Jul 22 04:45:27 PM PDT 24
Finished Jul 22 04:45:31 PM PDT 24
Peak memory 216804 kb
Host smart-e0a5033e-7b4e-48f2-a8b5-e2f260a02218
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024407169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3024407169
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1211106967
Short name T318
Test name
Test status
Simulation time 3442753914 ps
CPU time 32.26 seconds
Started Jul 22 04:45:12 PM PDT 24
Finished Jul 22 04:45:45 PM PDT 24
Peak memory 218616 kb
Host smart-4abb1764-0d82-4881-b81c-f3c9b2815d34
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211106967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1211106967
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3786332539
Short name T224
Test name
Test status
Simulation time 557825099 ps
CPU time 8.94 seconds
Started Jul 22 04:45:10 PM PDT 24
Finished Jul 22 04:45:19 PM PDT 24
Peak memory 222876 kb
Host smart-5ef6a281-7a83-4291-ad01-7d39c81aa46c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786332539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3786332539
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1360403840
Short name T289
Test name
Test status
Simulation time 521893789 ps
CPU time 8.22 seconds
Started Jul 22 04:45:24 PM PDT 24
Finished Jul 22 04:45:32 PM PDT 24
Peak memory 217540 kb
Host smart-10dbd71f-1e89-4fc2-a2ab-727e94ea577a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360403840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1360403840
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.138875099
Short name T550
Test name
Test status
Simulation time 2357647024 ps
CPU time 47.92 seconds
Started Jul 22 04:45:10 PM PDT 24
Finished Jul 22 04:45:58 PM PDT 24
Peak memory 277016 kb
Host smart-524bef7c-1ce5-48e1-a0ae-2159dc2ba2cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138875099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.138875099
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.321688317
Short name T264
Test name
Test status
Simulation time 11371324302 ps
CPU time 30.36 seconds
Started Jul 22 04:45:11 PM PDT 24
Finished Jul 22 04:45:42 PM PDT 24
Peak memory 246728 kb
Host smart-3dec7d26-054e-42fd-9abe-8deb59dcafe6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321688317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.321688317
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2244625069
Short name T31
Test name
Test status
Simulation time 330756118 ps
CPU time 3.56 seconds
Started Jul 22 04:45:33 PM PDT 24
Finished Jul 22 04:45:38 PM PDT 24
Peak memory 222048 kb
Host smart-81aeb99e-910e-46cb-b153-93c64ceb0193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244625069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2244625069
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3622959680
Short name T500
Test name
Test status
Simulation time 944287865 ps
CPU time 13.42 seconds
Started Jul 22 04:45:14 PM PDT 24
Finished Jul 22 04:45:27 PM PDT 24
Peak memory 218068 kb
Host smart-fc948c1a-0f0d-4351-80f5-144941157763
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622959680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3622959680
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3264463921
Short name T827
Test name
Test status
Simulation time 490053841 ps
CPU time 10.27 seconds
Started Jul 22 04:45:13 PM PDT 24
Finished Jul 22 04:45:24 PM PDT 24
Peak memory 225812 kb
Host smart-455a3a73-4b58-4fe5-bd98-1daec9faae26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264463921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3264463921
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1184812168
Short name T611
Test name
Test status
Simulation time 2862565139 ps
CPU time 7 seconds
Started Jul 22 04:45:09 PM PDT 24
Finished Jul 22 04:45:17 PM PDT 24
Peak memory 218124 kb
Host smart-c7468a9c-6083-4508-99c9-ae725f68590d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184812168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1184812168
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1760368590
Short name T317
Test name
Test status
Simulation time 501968769 ps
CPU time 5.3 seconds
Started Jul 22 04:45:11 PM PDT 24
Finished Jul 22 04:45:16 PM PDT 24
Peak memory 217508 kb
Host smart-3fe6f3b0-a8aa-4fbe-8e34-5d761ec5d402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760368590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1760368590
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2099651495
Short name T251
Test name
Test status
Simulation time 911306260 ps
CPU time 22.94 seconds
Started Jul 22 04:45:11 PM PDT 24
Finished Jul 22 04:45:35 PM PDT 24
Peak memory 250664 kb
Host smart-2e413db2-c8ce-45ae-879a-9b62ba61e63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099651495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2099651495
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.1209486762
Short name T792
Test name
Test status
Simulation time 877096079 ps
CPU time 7.93 seconds
Started Jul 22 04:45:11 PM PDT 24
Finished Jul 22 04:45:20 PM PDT 24
Peak memory 246884 kb
Host smart-5a711f71-7a33-4b8e-b69f-79e8c3e1ee79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209486762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1209486762
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.695625495
Short name T842
Test name
Test status
Simulation time 4162995316 ps
CPU time 67.34 seconds
Started Jul 22 04:45:12 PM PDT 24
Finished Jul 22 04:46:20 PM PDT 24
Peak memory 272516 kb
Host smart-edeca14e-7ee0-4be2-972c-0c7e3ce78bc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695625495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.695625495
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.4150340646
Short name T755
Test name
Test status
Simulation time 8588134924 ps
CPU time 272.16 seconds
Started Jul 22 04:45:11 PM PDT 24
Finished Jul 22 04:49:44 PM PDT 24
Peak memory 309600 kb
Host smart-ae178b8d-955c-4aee-9a49-89d7a0c7f947
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4150340646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.4150340646
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2638169924
Short name T266
Test name
Test status
Simulation time 99906417 ps
CPU time 0.87 seconds
Started Jul 22 04:45:34 PM PDT 24
Finished Jul 22 04:45:35 PM PDT 24
Peak memory 208708 kb
Host smart-7a30a091-e551-4b31-b4a3-9255e9760627
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638169924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2638169924
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.512224866
Short name T486
Test name
Test status
Simulation time 219515222 ps
CPU time 8.89 seconds
Started Jul 22 04:45:13 PM PDT 24
Finished Jul 22 04:45:22 PM PDT 24
Peak memory 218048 kb
Host smart-e43dfd92-89c8-49b6-b123-e4ffaf3e873f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512224866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.512224866
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1434355401
Short name T347
Test name
Test status
Simulation time 298457651 ps
CPU time 8.21 seconds
Started Jul 22 04:45:21 PM PDT 24
Finished Jul 22 04:45:30 PM PDT 24
Peak memory 217164 kb
Host smart-3e10ac20-0a0b-4015-8c25-9145ded6177a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434355401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1434355401
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1495867486
Short name T429
Test name
Test status
Simulation time 3895794189 ps
CPU time 90.17 seconds
Started Jul 22 04:45:20 PM PDT 24
Finished Jul 22 04:46:51 PM PDT 24
Peak memory 218568 kb
Host smart-2a38c5fb-3cfd-48d5-bf9f-4fa54539e8ff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495867486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1495867486
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3179536437
Short name T519
Test name
Test status
Simulation time 552895298 ps
CPU time 9.35 seconds
Started Jul 22 04:45:21 PM PDT 24
Finished Jul 22 04:45:30 PM PDT 24
Peak memory 224156 kb
Host smart-ac43333a-54dd-45b7-a5c2-4cebd9456be2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179536437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3179536437
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.906214341
Short name T823
Test name
Test status
Simulation time 786806952 ps
CPU time 3.5 seconds
Started Jul 22 04:45:12 PM PDT 24
Finished Jul 22 04:45:16 PM PDT 24
Peak memory 217324 kb
Host smart-d02bb7d2-61b8-4cf0-9226-c79816bd78f6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906214341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
906214341
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.500439537
Short name T546
Test name
Test status
Simulation time 2907784202 ps
CPU time 59.4 seconds
Started Jul 22 04:45:23 PM PDT 24
Finished Jul 22 04:46:23 PM PDT 24
Peak memory 250796 kb
Host smart-c0abcbc6-57ee-4b0e-a661-5b346721e7cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500439537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.500439537
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2054525564
Short name T517
Test name
Test status
Simulation time 3360509044 ps
CPU time 27.28 seconds
Started Jul 22 04:45:25 PM PDT 24
Finished Jul 22 04:45:53 PM PDT 24
Peak memory 250768 kb
Host smart-590e5aa2-7dfd-4653-8be1-a3b8a963f444
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054525564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2054525564
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.421284471
Short name T354
Test name
Test status
Simulation time 38971271 ps
CPU time 2.13 seconds
Started Jul 22 04:45:23 PM PDT 24
Finished Jul 22 04:45:26 PM PDT 24
Peak memory 218072 kb
Host smart-e2d66d55-d859-4485-8679-65240fa40c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421284471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.421284471
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.312202757
Short name T327
Test name
Test status
Simulation time 2287720300 ps
CPU time 18.18 seconds
Started Jul 22 04:45:22 PM PDT 24
Finished Jul 22 04:45:41 PM PDT 24
Peak memory 218404 kb
Host smart-ded5dc29-3eb3-4ac9-aac1-82218869cb51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312202757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.312202757
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.147810532
Short name T236
Test name
Test status
Simulation time 1676388536 ps
CPU time 10.88 seconds
Started Jul 22 04:45:20 PM PDT 24
Finished Jul 22 04:45:31 PM PDT 24
Peak memory 218008 kb
Host smart-f21ef967-74f3-4f2f-bd4a-69c55b7b0dbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147810532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.147810532
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.103926867
Short name T796
Test name
Test status
Simulation time 1970345546 ps
CPU time 9.87 seconds
Started Jul 22 04:48:43 PM PDT 24
Finished Jul 22 04:48:54 PM PDT 24
Peak memory 225716 kb
Host smart-c2e547c3-d5e8-4e1e-a57f-7c9cc7ae3a9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103926867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.103926867
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.698455367
Short name T323
Test name
Test status
Simulation time 113275120 ps
CPU time 2.08 seconds
Started Jul 22 04:45:09 PM PDT 24
Finished Jul 22 04:45:12 PM PDT 24
Peak memory 213852 kb
Host smart-1292de3b-33c6-480b-ab1f-568729306f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698455367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.698455367
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2557250068
Short name T824
Test name
Test status
Simulation time 1158221705 ps
CPU time 28.59 seconds
Started Jul 22 04:45:12 PM PDT 24
Finished Jul 22 04:45:41 PM PDT 24
Peak memory 250692 kb
Host smart-0ff560ef-9d5d-4231-9716-38bbd8933bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557250068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2557250068
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1024042011
Short name T378
Test name
Test status
Simulation time 309196272 ps
CPU time 7.32 seconds
Started Jul 22 04:45:25 PM PDT 24
Finished Jul 22 04:45:33 PM PDT 24
Peak memory 250756 kb
Host smart-1290619a-5e83-4b34-8362-50566c1c6cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024042011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1024042011
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.4105923282
Short name T742
Test name
Test status
Simulation time 46697980782 ps
CPU time 269.76 seconds
Started Jul 22 04:45:21 PM PDT 24
Finished Jul 22 04:49:52 PM PDT 24
Peak memory 250800 kb
Host smart-d01fdc21-cc88-47eb-9413-6856fd93c23f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105923282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.4105923282
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.732266587
Short name T474
Test name
Test status
Simulation time 16138005 ps
CPU time 1 seconds
Started Jul 22 04:45:34 PM PDT 24
Finished Jul 22 04:45:35 PM PDT 24
Peak memory 211540 kb
Host smart-8032f2cb-5c9d-47d7-832d-39e6a263abf5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732266587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.732266587
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.853427651
Short name T478
Test name
Test status
Simulation time 44375186 ps
CPU time 1.06 seconds
Started Jul 22 04:45:20 PM PDT 24
Finished Jul 22 04:45:22 PM PDT 24
Peak memory 208568 kb
Host smart-1eeccced-f06e-488c-96c8-cc663f9015e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853427651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.853427651
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2209259462
Short name T50
Test name
Test status
Simulation time 7726616814 ps
CPU time 13.7 seconds
Started Jul 22 04:45:24 PM PDT 24
Finished Jul 22 04:45:39 PM PDT 24
Peak memory 218328 kb
Host smart-9d747c06-9729-484c-b90a-25b0333a8e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209259462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2209259462
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1460205960
Short name T181
Test name
Test status
Simulation time 855776488 ps
CPU time 5.25 seconds
Started Jul 22 04:45:19 PM PDT 24
Finished Jul 22 04:45:25 PM PDT 24
Peak memory 216852 kb
Host smart-3df8d075-3039-400d-935d-ad95e785e809
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460205960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1460205960
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.4012599474
Short name T703
Test name
Test status
Simulation time 23006187930 ps
CPU time 72.13 seconds
Started Jul 22 04:45:22 PM PDT 24
Finished Jul 22 04:46:34 PM PDT 24
Peak memory 217984 kb
Host smart-3cd50de5-3947-41e4-bd76-456ffae0cb73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012599474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.4012599474
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.332882702
Short name T575
Test name
Test status
Simulation time 1247510565 ps
CPU time 8.53 seconds
Started Jul 22 04:45:21 PM PDT 24
Finished Jul 22 04:45:30 PM PDT 24
Peak memory 221632 kb
Host smart-d99e29d9-26c2-4041-8742-df762ad8a90b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332882702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.332882702
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.552801768
Short name T234
Test name
Test status
Simulation time 5164687554 ps
CPU time 16.38 seconds
Started Jul 22 04:48:43 PM PDT 24
Finished Jul 22 04:49:00 PM PDT 24
Peak memory 217392 kb
Host smart-50a008ab-847c-43cf-af86-e3b00a192cb2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552801768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke.
552801768
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2141738201
Short name T152
Test name
Test status
Simulation time 2732109537 ps
CPU time 47.07 seconds
Started Jul 22 04:45:27 PM PDT 24
Finished Jul 22 04:46:15 PM PDT 24
Peak memory 252932 kb
Host smart-c0ea1505-a0e0-4273-8e10-d7d7c6fee459
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141738201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2141738201
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2799602393
Short name T284
Test name
Test status
Simulation time 4659834868 ps
CPU time 20.06 seconds
Started Jul 22 04:45:23 PM PDT 24
Finished Jul 22 04:45:44 PM PDT 24
Peak memory 250752 kb
Host smart-5c805918-19f4-4215-bf60-fc7b339b7795
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799602393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2799602393
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3274448099
Short name T726
Test name
Test status
Simulation time 486378775 ps
CPU time 3.67 seconds
Started Jul 22 04:45:30 PM PDT 24
Finished Jul 22 04:45:34 PM PDT 24
Peak memory 217948 kb
Host smart-1fa27c16-3833-44d7-84dc-d067a51ab377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274448099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3274448099
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3397893317
Short name T242
Test name
Test status
Simulation time 317665227 ps
CPU time 10.64 seconds
Started Jul 22 04:45:20 PM PDT 24
Finished Jul 22 04:45:31 PM PDT 24
Peak memory 225880 kb
Host smart-429ebabf-2fb8-4b29-92d2-506c4811767a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397893317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3397893317
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2254123670
Short name T390
Test name
Test status
Simulation time 7047405738 ps
CPU time 15.33 seconds
Started Jul 22 04:47:52 PM PDT 24
Finished Jul 22 04:48:08 PM PDT 24
Peak memory 217996 kb
Host smart-5b54efd8-5a6e-4d7b-8ce2-ad3a96d5cdcd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254123670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2254123670
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3438203153
Short name T303
Test name
Test status
Simulation time 1776962068 ps
CPU time 11.44 seconds
Started Jul 22 04:45:36 PM PDT 24
Finished Jul 22 04:45:48 PM PDT 24
Peak memory 225728 kb
Host smart-f1ee7f5a-d17d-468d-97a2-074b27331f1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438203153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
3438203153
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3834483382
Short name T454
Test name
Test status
Simulation time 1454237347 ps
CPU time 9.66 seconds
Started Jul 22 04:45:24 PM PDT 24
Finished Jul 22 04:45:34 PM PDT 24
Peak memory 218052 kb
Host smart-a5560827-d263-403d-87af-1500bbd4710a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834483382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3834483382
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1232476254
Short name T311
Test name
Test status
Simulation time 32917138 ps
CPU time 1.36 seconds
Started Jul 22 04:48:43 PM PDT 24
Finished Jul 22 04:48:45 PM PDT 24
Peak memory 213524 kb
Host smart-22526bdc-a58f-433b-95b0-8c69e812d591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232476254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1232476254
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.642851855
Short name T189
Test name
Test status
Simulation time 558605170 ps
CPU time 20.75 seconds
Started Jul 22 04:45:22 PM PDT 24
Finished Jul 22 04:45:44 PM PDT 24
Peak memory 250708 kb
Host smart-b536bdbe-d974-4510-bc16-146e43a0af2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642851855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.642851855
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1500397892
Short name T557
Test name
Test status
Simulation time 933447322 ps
CPU time 6.09 seconds
Started Jul 22 04:45:25 PM PDT 24
Finished Jul 22 04:45:31 PM PDT 24
Peak memory 246652 kb
Host smart-ff472885-1c74-4cd0-b092-2df8a1dea7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500397892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1500397892
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.4214342407
Short name T533
Test name
Test status
Simulation time 40516548699 ps
CPU time 178.32 seconds
Started Jul 22 04:48:43 PM PDT 24
Finished Jul 22 04:51:43 PM PDT 24
Peak memory 251176 kb
Host smart-7a7912a8-7f49-4ca8-a895-6204fd0c58cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214342407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.4214342407
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.1884848696
Short name T104
Test name
Test status
Simulation time 411001364154 ps
CPU time 1214.02 seconds
Started Jul 22 04:48:43 PM PDT 24
Finished Jul 22 05:09:00 PM PDT 24
Peak memory 275660 kb
Host smart-aa796731-e667-429f-aecb-ad84f09c8ffd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1884848696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.1884848696
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.144543843
Short name T394
Test name
Test status
Simulation time 54770596 ps
CPU time 1.13 seconds
Started Jul 22 04:45:21 PM PDT 24
Finished Jul 22 04:45:22 PM PDT 24
Peak memory 217568 kb
Host smart-52bda90d-70e4-4c79-8ad0-41cc8b9b4439
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144543843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.144543843
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.4047649626
Short name T587
Test name
Test status
Simulation time 81341438 ps
CPU time 1.25 seconds
Started Jul 22 04:43:30 PM PDT 24
Finished Jul 22 04:43:31 PM PDT 24
Peak memory 208684 kb
Host smart-eba6d92a-4831-4da0-91a3-2ce2c0e10134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047649626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.4047649626
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3080144089
Short name T221
Test name
Test status
Simulation time 13467268 ps
CPU time 0.98 seconds
Started Jul 22 04:43:17 PM PDT 24
Finished Jul 22 04:43:19 PM PDT 24
Peak memory 208496 kb
Host smart-ec11f87f-f440-4d89-9499-7576422756a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080144089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3080144089
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.286360229
Short name T771
Test name
Test status
Simulation time 521215761 ps
CPU time 19.33 seconds
Started Jul 22 04:43:24 PM PDT 24
Finished Jul 22 04:43:44 PM PDT 24
Peak memory 217952 kb
Host smart-625a7e5d-fb10-4c63-b6ae-199a58a2158b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286360229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.286360229
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2791739131
Short name T7
Test name
Test status
Simulation time 251970379 ps
CPU time 1.46 seconds
Started Jul 22 04:43:26 PM PDT 24
Finished Jul 22 04:43:28 PM PDT 24
Peak memory 216988 kb
Host smart-576259b9-7775-4c16-bbba-74d4c74193c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791739131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2791739131
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.895520659
Short name T277
Test name
Test status
Simulation time 12802451769 ps
CPU time 91.99 seconds
Started Jul 22 04:43:25 PM PDT 24
Finished Jul 22 04:44:58 PM PDT 24
Peak memory 218544 kb
Host smart-ed76e143-11da-44b2-a69c-7a0584515db5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895520659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.895520659
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3258471090
Short name T192
Test name
Test status
Simulation time 3693003128 ps
CPU time 10.15 seconds
Started Jul 22 04:43:39 PM PDT 24
Finished Jul 22 04:43:49 PM PDT 24
Peak memory 217452 kb
Host smart-b51aedc9-3b27-4007-bfeb-c142866ad2ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258471090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3
258471090
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1904115054
Short name T667
Test name
Test status
Simulation time 890914084 ps
CPU time 13.42 seconds
Started Jul 22 04:43:25 PM PDT 24
Finished Jul 22 04:43:39 PM PDT 24
Peak memory 225080 kb
Host smart-afae9663-b6d8-496d-a858-b0b33bacbfbe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904115054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.1904115054
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2062218553
Short name T82
Test name
Test status
Simulation time 1127598026 ps
CPU time 19.45 seconds
Started Jul 22 04:43:26 PM PDT 24
Finished Jul 22 04:43:46 PM PDT 24
Peak memory 217288 kb
Host smart-c2a00b11-7144-4bd7-8cb9-9b930320e78b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062218553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2062218553
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3738825880
Short name T340
Test name
Test status
Simulation time 2510526827 ps
CPU time 7.26 seconds
Started Jul 22 04:43:19 PM PDT 24
Finished Jul 22 04:43:27 PM PDT 24
Peak memory 217388 kb
Host smart-259319b1-0418-4fc0-88e8-3934f6a7877f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738825880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3738825880
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2118440053
Short name T615
Test name
Test status
Simulation time 5626682189 ps
CPU time 40.96 seconds
Started Jul 22 04:44:19 PM PDT 24
Finished Jul 22 04:45:01 PM PDT 24
Peak memory 267392 kb
Host smart-ee84289c-f80f-401b-a6a8-1cf7f2c82f21
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118440053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2118440053
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1642685435
Short name T154
Test name
Test status
Simulation time 1460675832 ps
CPU time 15.25 seconds
Started Jul 22 04:43:29 PM PDT 24
Finished Jul 22 04:43:45 PM PDT 24
Peak memory 249172 kb
Host smart-422e339c-bf4f-46e6-9cba-9711667e82d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642685435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1642685435
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2556903855
Short name T540
Test name
Test status
Simulation time 24221399 ps
CPU time 1.83 seconds
Started Jul 22 04:43:18 PM PDT 24
Finished Jul 22 04:43:21 PM PDT 24
Peak memory 221908 kb
Host smart-4a3ea096-7f57-4ec1-8be3-86054e29b877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556903855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2556903855
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1983098360
Short name T193
Test name
Test status
Simulation time 1254451776 ps
CPU time 11.19 seconds
Started Jul 22 04:43:20 PM PDT 24
Finished Jul 22 04:43:32 PM PDT 24
Peak memory 217312 kb
Host smart-2e0f115c-b8a3-4ef0-b32f-2ad92fd997c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983098360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1983098360
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2049938868
Short name T778
Test name
Test status
Simulation time 2345047906 ps
CPU time 15.91 seconds
Started Jul 22 04:43:25 PM PDT 24
Finished Jul 22 04:43:41 PM PDT 24
Peak memory 218984 kb
Host smart-56704dd7-9b51-409c-a1c7-90897db9b708
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049938868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2049938868
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2858773223
Short name T629
Test name
Test status
Simulation time 2829277635 ps
CPU time 7.44 seconds
Started Jul 22 04:43:40 PM PDT 24
Finished Jul 22 04:43:48 PM PDT 24
Peak memory 217968 kb
Host smart-c6e2b920-5132-4dff-8954-8587cadfe4d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858773223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2858773223
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.4106949518
Short name T642
Test name
Test status
Simulation time 515418283 ps
CPU time 8.61 seconds
Started Jul 22 04:43:28 PM PDT 24
Finished Jul 22 04:43:37 PM PDT 24
Peak memory 217920 kb
Host smart-2c0446c6-ca31-406a-9a3b-d1bcdf5a0a0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106949518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.4
106949518
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.470488980
Short name T372
Test name
Test status
Simulation time 379987387 ps
CPU time 8.69 seconds
Started Jul 22 04:43:17 PM PDT 24
Finished Jul 22 04:43:27 PM PDT 24
Peak memory 225756 kb
Host smart-3e30d666-4632-43b4-bc1a-1cf6c4276085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470488980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.470488980
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2689667725
Short name T847
Test name
Test status
Simulation time 102566522 ps
CPU time 1.52 seconds
Started Jul 22 04:43:18 PM PDT 24
Finished Jul 22 04:43:21 PM PDT 24
Peak memory 221652 kb
Host smart-3ccd9522-93c5-46c8-af3f-0764375f3e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689667725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2689667725
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3520319402
Short name T507
Test name
Test status
Simulation time 339868694 ps
CPU time 31.03 seconds
Started Jul 22 04:43:20 PM PDT 24
Finished Jul 22 04:43:51 PM PDT 24
Peak memory 250756 kb
Host smart-167682a6-afae-4d0d-9bac-4de1f3c7f08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520319402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3520319402
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.46081139
Short name T285
Test name
Test status
Simulation time 340647191 ps
CPU time 8.9 seconds
Started Jul 22 04:43:20 PM PDT 24
Finished Jul 22 04:43:29 PM PDT 24
Peak memory 250656 kb
Host smart-cf961649-375c-442d-9c78-1599eaf9010b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46081139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.46081139
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2586590902
Short name T182
Test name
Test status
Simulation time 74328501069 ps
CPU time 184.98 seconds
Started Jul 22 04:44:19 PM PDT 24
Finished Jul 22 04:47:25 PM PDT 24
Peak memory 280572 kb
Host smart-4706701d-bef9-4262-a463-9bb13b4569ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586590902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2586590902
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3201266754
Short name T51
Test name
Test status
Simulation time 20375297207 ps
CPU time 342.2 seconds
Started Jul 22 04:43:26 PM PDT 24
Finished Jul 22 04:49:09 PM PDT 24
Peak memory 310440 kb
Host smart-6141bbf3-fb53-4ec0-869f-2518dcbb7da3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3201266754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.3201266754
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.539341072
Short name T841
Test name
Test status
Simulation time 66753536 ps
CPU time 0.92 seconds
Started Jul 22 04:43:23 PM PDT 24
Finished Jul 22 04:43:25 PM PDT 24
Peak memory 208624 kb
Host smart-ef6b164e-e442-4e42-be7c-fef13db87f40
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539341072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.539341072
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3287419188
Short name T854
Test name
Test status
Simulation time 113688745 ps
CPU time 0.91 seconds
Started Jul 22 04:45:23 PM PDT 24
Finished Jul 22 04:45:24 PM PDT 24
Peak memory 208548 kb
Host smart-18e9754a-261d-4896-a71e-17d1ea78de91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287419188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3287419188
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.987650494
Short name T733
Test name
Test status
Simulation time 1005308259 ps
CPU time 9.59 seconds
Started Jul 22 04:45:23 PM PDT 24
Finished Jul 22 04:45:33 PM PDT 24
Peak memory 217376 kb
Host smart-6907df9b-1218-4671-8a5e-2f25a4f6493c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987650494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.987650494
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.64750752
Short name T583
Test name
Test status
Simulation time 154344252 ps
CPU time 3.91 seconds
Started Jul 22 04:48:43 PM PDT 24
Finished Jul 22 04:48:48 PM PDT 24
Peak memory 222588 kb
Host smart-8f0bee0c-017d-4778-a1d9-b11f90176a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64750752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.64750752
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3379409534
Short name T12
Test name
Test status
Simulation time 1175422272 ps
CPU time 11.25 seconds
Started Jul 22 04:45:26 PM PDT 24
Finished Jul 22 04:45:37 PM PDT 24
Peak memory 217948 kb
Host smart-50cef69a-d776-42ee-a91d-8a3a2f884e01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379409534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3379409534
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.902151633
Short name T820
Test name
Test status
Simulation time 171350362 ps
CPU time 7.61 seconds
Started Jul 22 04:45:29 PM PDT 24
Finished Jul 22 04:45:38 PM PDT 24
Peak memory 225792 kb
Host smart-a989a12a-d5f8-4a2e-b5e2-2c19ebed261a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902151633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.902151633
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1166977726
Short name T35
Test name
Test status
Simulation time 191091855 ps
CPU time 8.07 seconds
Started Jul 22 04:45:22 PM PDT 24
Finished Jul 22 04:45:31 PM PDT 24
Peak memory 224752 kb
Host smart-b9a9b424-2e9e-4b34-99f5-6248ce48d8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166977726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1166977726
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.627909475
Short name T512
Test name
Test status
Simulation time 15173402 ps
CPU time 1.2 seconds
Started Jul 22 04:45:21 PM PDT 24
Finished Jul 22 04:45:23 PM PDT 24
Peak memory 213492 kb
Host smart-388228c1-9b40-424d-b971-3c129f562d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627909475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.627909475
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.66888922
Short name T93
Test name
Test status
Simulation time 1077051383 ps
CPU time 24.13 seconds
Started Jul 22 04:45:21 PM PDT 24
Finished Jul 22 04:45:45 PM PDT 24
Peak memory 250644 kb
Host smart-c4346214-dcb3-4a29-a24e-3fbd798e5c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66888922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.66888922
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1467794721
Short name T13
Test name
Test status
Simulation time 104107194 ps
CPU time 6.48 seconds
Started Jul 22 04:47:52 PM PDT 24
Finished Jul 22 04:48:00 PM PDT 24
Peak memory 245856 kb
Host smart-e62a6f31-6cfc-4b5a-8d43-fe1a812b8fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467794721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1467794721
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3878334374
Short name T425
Test name
Test status
Simulation time 880030689 ps
CPU time 32.92 seconds
Started Jul 22 04:45:31 PM PDT 24
Finished Jul 22 04:46:05 PM PDT 24
Peak memory 250680 kb
Host smart-1590682f-8e54-4d5f-88e5-bc7db26cc1ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878334374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3878334374
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3505861246
Short name T735
Test name
Test status
Simulation time 15634458 ps
CPU time 0.79 seconds
Started Jul 22 04:48:43 PM PDT 24
Finished Jul 22 04:48:45 PM PDT 24
Peak memory 208556 kb
Host smart-add9c5ca-c25f-47d7-9efc-dc13b867fa0e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505861246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.3505861246
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.998558164
Short name T98
Test name
Test status
Simulation time 33105690 ps
CPU time 1.15 seconds
Started Jul 22 04:45:28 PM PDT 24
Finished Jul 22 04:45:30 PM PDT 24
Peak memory 208592 kb
Host smart-de4e1b35-356a-458e-bcda-29518181f11d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998558164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.998558164
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.4098287090
Short name T387
Test name
Test status
Simulation time 451395993 ps
CPU time 17.93 seconds
Started Jul 22 04:45:24 PM PDT 24
Finished Jul 22 04:45:42 PM PDT 24
Peak memory 218052 kb
Host smart-fcaffcdf-7af4-48e0-89f0-c690ce3f7c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098287090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.4098287090
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3332281551
Short name T590
Test name
Test status
Simulation time 2122737345 ps
CPU time 6.41 seconds
Started Jul 22 04:45:30 PM PDT 24
Finished Jul 22 04:45:37 PM PDT 24
Peak memory 216944 kb
Host smart-d17271eb-6a3a-43fc-994a-1641a603c978
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332281551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3332281551
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1989113771
Short name T851
Test name
Test status
Simulation time 82475944 ps
CPU time 3.19 seconds
Started Jul 22 04:45:26 PM PDT 24
Finished Jul 22 04:45:29 PM PDT 24
Peak memory 217960 kb
Host smart-3424ea29-d528-45b5-8fc4-549dff2f85a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989113771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1989113771
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1823988111
Short name T276
Test name
Test status
Simulation time 338512031 ps
CPU time 11.59 seconds
Started Jul 22 04:45:28 PM PDT 24
Finished Jul 22 04:45:40 PM PDT 24
Peak memory 218728 kb
Host smart-0c5031b2-0a64-44f9-a498-59f1600ba0ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823988111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1823988111
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2895894934
Short name T539
Test name
Test status
Simulation time 1769188554 ps
CPU time 13.07 seconds
Started Jul 22 04:45:34 PM PDT 24
Finished Jul 22 04:45:47 PM PDT 24
Peak memory 218056 kb
Host smart-0ef7e760-8c82-44e4-b414-725bd50c7870
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895894934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2895894934
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2016410788
Short name T342
Test name
Test status
Simulation time 445672181 ps
CPU time 10.86 seconds
Started Jul 22 04:45:27 PM PDT 24
Finished Jul 22 04:45:38 PM PDT 24
Peak memory 225688 kb
Host smart-1c0b94b3-591f-4f42-af44-c232b2e7202b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016410788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2016410788
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3190508810
Short name T170
Test name
Test status
Simulation time 239503953 ps
CPU time 10.68 seconds
Started Jul 22 04:45:22 PM PDT 24
Finished Jul 22 04:45:34 PM PDT 24
Peak memory 218076 kb
Host smart-0b37ab87-cd53-4ed7-b518-9d45214847f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190508810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3190508810
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3918698973
Short name T287
Test name
Test status
Simulation time 35362088 ps
CPU time 2.65 seconds
Started Jul 22 04:45:21 PM PDT 24
Finished Jul 22 04:45:24 PM PDT 24
Peak memory 214492 kb
Host smart-0eac6046-b84b-43bd-a867-ab52506d4944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918698973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3918698973
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2869012252
Short name T850
Test name
Test status
Simulation time 329744068 ps
CPU time 35.48 seconds
Started Jul 22 04:45:24 PM PDT 24
Finished Jul 22 04:46:00 PM PDT 24
Peak memory 250652 kb
Host smart-69bedff8-72a9-4230-9fbc-6c3acca52340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869012252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2869012252
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.697611236
Short name T652
Test name
Test status
Simulation time 205257117 ps
CPU time 7.75 seconds
Started Jul 22 04:48:43 PM PDT 24
Finished Jul 22 04:48:52 PM PDT 24
Peak memory 250480 kb
Host smart-85008381-342d-4e25-a66a-6af1e2a223bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697611236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.697611236
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3415974259
Short name T501
Test name
Test status
Simulation time 4343936663 ps
CPU time 63.9 seconds
Started Jul 22 04:45:29 PM PDT 24
Finished Jul 22 04:46:34 PM PDT 24
Peak memory 269688 kb
Host smart-e37726b9-4416-44fd-81bb-5e6680e8e67c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415974259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3415974259
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.605817371
Short name T491
Test name
Test status
Simulation time 45003150 ps
CPU time 1.02 seconds
Started Jul 22 04:45:23 PM PDT 24
Finished Jul 22 04:45:25 PM PDT 24
Peak memory 211624 kb
Host smart-44b9ca69-2e12-411b-9707-4eb3086911d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605817371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.605817371
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2101884029
Short name T551
Test name
Test status
Simulation time 36882230 ps
CPU time 0.91 seconds
Started Jul 22 04:45:27 PM PDT 24
Finished Jul 22 04:45:29 PM PDT 24
Peak memory 208544 kb
Host smart-c1995663-2026-44d1-9d63-eed491a4c500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101884029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2101884029
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2567739811
Short name T488
Test name
Test status
Simulation time 4352546773 ps
CPU time 14.54 seconds
Started Jul 22 04:45:33 PM PDT 24
Finished Jul 22 04:45:48 PM PDT 24
Peak memory 218220 kb
Host smart-0110a9d0-cf19-4930-a2d6-7530738b6d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567739811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2567739811
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.931981821
Short name T356
Test name
Test status
Simulation time 734680600 ps
CPU time 10.19 seconds
Started Jul 22 04:45:30 PM PDT 24
Finished Jul 22 04:45:41 PM PDT 24
Peak memory 217212 kb
Host smart-401a88ae-05ba-4888-bde5-fa6691161281
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931981821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.931981821
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3854925282
Short name T817
Test name
Test status
Simulation time 257256434 ps
CPU time 2.34 seconds
Started Jul 22 04:48:00 PM PDT 24
Finished Jul 22 04:48:03 PM PDT 24
Peak memory 217980 kb
Host smart-c247a016-2d28-4b44-9b60-f6744b8c2164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854925282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3854925282
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.4208184087
Short name T708
Test name
Test status
Simulation time 1585018546 ps
CPU time 13.64 seconds
Started Jul 22 04:45:29 PM PDT 24
Finished Jul 22 04:45:44 PM PDT 24
Peak memory 218516 kb
Host smart-098c4bcb-dd2f-448d-89a5-b58c4d073118
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208184087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.4208184087
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3914858286
Short name T320
Test name
Test status
Simulation time 573520175 ps
CPU time 19.22 seconds
Started Jul 22 04:45:46 PM PDT 24
Finished Jul 22 04:46:06 PM PDT 24
Peak memory 225696 kb
Host smart-2e0e1799-3d2c-49a3-8773-581d95ed37f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914858286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3914858286
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3048811960
Short name T576
Test name
Test status
Simulation time 1496247861 ps
CPU time 13.54 seconds
Started Jul 22 04:45:46 PM PDT 24
Finished Jul 22 04:46:01 PM PDT 24
Peak memory 225676 kb
Host smart-63c38310-0d93-4ddc-b022-e9f2adc16bf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048811960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3048811960
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.2071714411
Short name T58
Test name
Test status
Simulation time 291799255 ps
CPU time 7.66 seconds
Started Jul 22 04:45:28 PM PDT 24
Finished Jul 22 04:45:36 PM PDT 24
Peak memory 218072 kb
Host smart-4eec971f-0b3e-4ae8-980d-8f3a7fe3921e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071714411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2071714411
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.237110844
Short name T392
Test name
Test status
Simulation time 144433546 ps
CPU time 4.32 seconds
Started Jul 22 04:46:16 PM PDT 24
Finished Jul 22 04:46:21 PM PDT 24
Peak memory 217416 kb
Host smart-a3e0126b-2db3-4176-9343-15c36a812032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237110844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.237110844
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.665884560
Short name T265
Test name
Test status
Simulation time 899880543 ps
CPU time 19.28 seconds
Started Jul 22 04:48:00 PM PDT 24
Finished Jul 22 04:48:20 PM PDT 24
Peak memory 250652 kb
Host smart-0625103b-633d-4e50-961b-0daa14d2d139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665884560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.665884560
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3869319055
Short name T624
Test name
Test status
Simulation time 76499615 ps
CPU time 6.31 seconds
Started Jul 22 04:45:36 PM PDT 24
Finished Jul 22 04:45:43 PM PDT 24
Peak memory 246792 kb
Host smart-b16f99da-3947-4f85-8fa8-89053178f517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869319055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3869319055
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3794282068
Short name T589
Test name
Test status
Simulation time 9871745608 ps
CPU time 400.69 seconds
Started Jul 22 04:45:35 PM PDT 24
Finished Jul 22 04:52:17 PM PDT 24
Peak memory 267092 kb
Host smart-d10f4d93-ac38-4e2f-a250-0f3ccd7be619
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794282068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3794282068
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3653133094
Short name T756
Test name
Test status
Simulation time 22134532 ps
CPU time 1.08 seconds
Started Jul 22 04:45:28 PM PDT 24
Finished Jul 22 04:45:30 PM PDT 24
Peak memory 211592 kb
Host smart-e513ecda-6488-4109-87c5-746bd83e7116
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653133094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3653133094
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1001308768
Short name T230
Test name
Test status
Simulation time 22261263 ps
CPU time 1.22 seconds
Started Jul 22 04:45:37 PM PDT 24
Finished Jul 22 04:45:39 PM PDT 24
Peak memory 208676 kb
Host smart-64c21f06-7ecd-4762-8bc1-de1296101c89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001308768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1001308768
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1475501194
Short name T830
Test name
Test status
Simulation time 413471921 ps
CPU time 14.22 seconds
Started Jul 22 04:45:28 PM PDT 24
Finished Jul 22 04:45:43 PM PDT 24
Peak memory 218004 kb
Host smart-8f630c40-97b7-4c52-ae13-eaf6a31d6031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475501194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1475501194
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.4142659629
Short name T829
Test name
Test status
Simulation time 3977650476 ps
CPU time 6.12 seconds
Started Jul 22 04:48:00 PM PDT 24
Finished Jul 22 04:48:07 PM PDT 24
Peak memory 217512 kb
Host smart-15348ea9-f0c3-4c63-a191-369a71c1fc2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142659629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.4142659629
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1751605566
Short name T67
Test name
Test status
Simulation time 64771350 ps
CPU time 2.36 seconds
Started Jul 22 04:46:16 PM PDT 24
Finished Jul 22 04:46:19 PM PDT 24
Peak memory 218004 kb
Host smart-3f1ad4d7-a6b5-46a6-aa0b-cd7d1d308cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751605566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1751605566
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.166731031
Short name T157
Test name
Test status
Simulation time 1124570361 ps
CPU time 14.61 seconds
Started Jul 22 04:45:38 PM PDT 24
Finished Jul 22 04:45:53 PM PDT 24
Peak memory 225732 kb
Host smart-3f2af469-7827-41a4-a6d4-7f9c4871c427
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166731031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.166731031
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3693958029
Short name T666
Test name
Test status
Simulation time 367734254 ps
CPU time 6.64 seconds
Started Jul 22 04:45:36 PM PDT 24
Finished Jul 22 04:45:43 PM PDT 24
Peak memory 225684 kb
Host smart-f7da2e6b-9fa3-4db8-9da4-fb4fda8128a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693958029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3693958029
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3483974925
Short name T422
Test name
Test status
Simulation time 5226550079 ps
CPU time 15.33 seconds
Started Jul 22 04:45:39 PM PDT 24
Finished Jul 22 04:45:55 PM PDT 24
Peak memory 218108 kb
Host smart-c8674864-a81c-4652-a2f4-4ffc70cfb78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483974925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3483974925
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.3831569442
Short name T527
Test name
Test status
Simulation time 44352741 ps
CPU time 2.69 seconds
Started Jul 22 04:48:00 PM PDT 24
Finished Jul 22 04:48:04 PM PDT 24
Peak memory 217388 kb
Host smart-43bbb83d-86da-4ba2-84d9-ef4e6ca20279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831569442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3831569442
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.2389599187
Short name T241
Test name
Test status
Simulation time 148162506 ps
CPU time 16.76 seconds
Started Jul 22 04:45:29 PM PDT 24
Finished Jul 22 04:45:46 PM PDT 24
Peak memory 250756 kb
Host smart-b645a70e-93d5-464d-be64-d289a65359b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389599187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2389599187
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2005358438
Short name T713
Test name
Test status
Simulation time 182019039 ps
CPU time 2.87 seconds
Started Jul 22 04:48:00 PM PDT 24
Finished Jul 22 04:48:04 PM PDT 24
Peak memory 217972 kb
Host smart-ca680702-34f3-4bae-9000-a229269f1916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005358438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2005358438
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3693593176
Short name T100
Test name
Test status
Simulation time 12318171485 ps
CPU time 330.62 seconds
Started Jul 22 04:45:36 PM PDT 24
Finished Jul 22 04:51:07 PM PDT 24
Peak memory 283580 kb
Host smart-7ffd496f-6c23-4300-876b-9a8d82020899
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693593176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3693593176
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.3809533812
Short name T99
Test name
Test status
Simulation time 72527336238 ps
CPU time 337.33 seconds
Started Jul 22 04:45:37 PM PDT 24
Finished Jul 22 04:51:15 PM PDT 24
Peak memory 276264 kb
Host smart-a2ff2218-287c-4311-92d6-8c389080cdeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3809533812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.3809533812
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1347499886
Short name T302
Test name
Test status
Simulation time 31259944 ps
CPU time 1.11 seconds
Started Jul 22 04:45:29 PM PDT 24
Finished Jul 22 04:45:30 PM PDT 24
Peak memory 217592 kb
Host smart-b521ae8f-172c-4977-a13d-04f929cf8217
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347499886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1347499886
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.4273973399
Short name T87
Test name
Test status
Simulation time 48079522 ps
CPU time 0.83 seconds
Started Jul 22 04:45:36 PM PDT 24
Finished Jul 22 04:45:37 PM PDT 24
Peak memory 208968 kb
Host smart-322ccb04-dc71-4aa7-b293-a43488078358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273973399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.4273973399
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1293347615
Short name T428
Test name
Test status
Simulation time 1551045209 ps
CPU time 17.08 seconds
Started Jul 22 04:46:51 PM PDT 24
Finished Jul 22 04:47:09 PM PDT 24
Peak memory 218004 kb
Host smart-53104986-1e50-4534-8eac-4d02871f24d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293347615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1293347615
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2770919698
Short name T591
Test name
Test status
Simulation time 396849291 ps
CPU time 11.16 seconds
Started Jul 22 04:45:37 PM PDT 24
Finished Jul 22 04:45:49 PM PDT 24
Peak memory 217176 kb
Host smart-83a7a84a-b06a-466a-80dc-12b80aa1803b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770919698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2770919698
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.4256349417
Short name T411
Test name
Test status
Simulation time 111225896 ps
CPU time 3.05 seconds
Started Jul 22 04:45:37 PM PDT 24
Finished Jul 22 04:45:41 PM PDT 24
Peak memory 218084 kb
Host smart-b73ab648-058b-42ac-ab94-a9d24ce2f992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256349417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.4256349417
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.236982197
Short name T797
Test name
Test status
Simulation time 1344361530 ps
CPU time 14.46 seconds
Started Jul 22 04:45:57 PM PDT 24
Finished Jul 22 04:46:12 PM PDT 24
Peak memory 225712 kb
Host smart-b00d8538-16fc-480c-9474-4b7f304b9def
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236982197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.236982197
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1698329954
Short name T164
Test name
Test status
Simulation time 460357231 ps
CPU time 9.02 seconds
Started Jul 22 04:45:35 PM PDT 24
Finished Jul 22 04:45:45 PM PDT 24
Peak memory 225724 kb
Host smart-8ff50201-1734-43e7-ba6f-a82fbfabe417
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698329954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1698329954
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.832091359
Short name T625
Test name
Test status
Simulation time 88600308 ps
CPU time 3.54 seconds
Started Jul 22 04:45:39 PM PDT 24
Finished Jul 22 04:45:43 PM PDT 24
Peak memory 217496 kb
Host smart-2f0ec54a-c3ab-4f05-9cc1-f86ac0e9c50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832091359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.832091359
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2609832686
Short name T612
Test name
Test status
Simulation time 546525895 ps
CPU time 28.45 seconds
Started Jul 22 04:45:46 PM PDT 24
Finished Jul 22 04:46:15 PM PDT 24
Peak memory 250680 kb
Host smart-a59a38df-6f39-400e-a98b-5dbd3e2b7d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609832686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2609832686
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2809387259
Short name T562
Test name
Test status
Simulation time 275307131 ps
CPU time 6.88 seconds
Started Jul 22 04:45:38 PM PDT 24
Finished Jul 22 04:45:46 PM PDT 24
Peak memory 247100 kb
Host smart-d4e0c52c-9ff6-402c-884b-14da279a4932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809387259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2809387259
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2364604363
Short name T259
Test name
Test status
Simulation time 11214532132 ps
CPU time 195.97 seconds
Started Jul 22 04:45:38 PM PDT 24
Finished Jul 22 04:48:55 PM PDT 24
Peak memory 250736 kb
Host smart-22ada3e5-a52d-4f1e-b626-5359c4ffb24c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364604363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2364604363
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3603581964
Short name T370
Test name
Test status
Simulation time 47169177 ps
CPU time 1.11 seconds
Started Jul 22 04:45:34 PM PDT 24
Finished Jul 22 04:45:36 PM PDT 24
Peak memory 217488 kb
Host smart-80616c7a-97a6-45ef-ad13-a39878149766
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603581964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3603581964
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3874434490
Short name T836
Test name
Test status
Simulation time 119889181 ps
CPU time 0.81 seconds
Started Jul 22 04:45:46 PM PDT 24
Finished Jul 22 04:45:48 PM PDT 24
Peak memory 208380 kb
Host smart-29574da6-d1f7-45a6-ad94-b1eec1f607a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874434490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3874434490
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1529952821
Short name T674
Test name
Test status
Simulation time 2336823938 ps
CPU time 21.81 seconds
Started Jul 22 04:45:45 PM PDT 24
Finished Jul 22 04:46:07 PM PDT 24
Peak memory 218804 kb
Host smart-483507c2-9106-49e6-ad0a-fde9b40d5155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529952821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1529952821
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1247856499
Short name T197
Test name
Test status
Simulation time 1353696547 ps
CPU time 7.04 seconds
Started Jul 22 04:45:49 PM PDT 24
Finished Jul 22 04:45:56 PM PDT 24
Peak memory 217164 kb
Host smart-7a7eaa65-cbe9-4e4f-851e-deee7d785c6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247856499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1247856499
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1738273327
Short name T520
Test name
Test status
Simulation time 30739437 ps
CPU time 1.59 seconds
Started Jul 22 04:45:38 PM PDT 24
Finished Jul 22 04:45:41 PM PDT 24
Peak memory 221688 kb
Host smart-d0fc4754-39ff-41d1-a2bd-cbe1c4111e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738273327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1738273327
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.32733868
Short name T421
Test name
Test status
Simulation time 297198075 ps
CPU time 13.31 seconds
Started Jul 22 04:45:45 PM PDT 24
Finished Jul 22 04:45:59 PM PDT 24
Peak memory 225908 kb
Host smart-8561506a-644d-41b7-a91f-443a8a0565ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32733868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.32733868
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2271127815
Short name T490
Test name
Test status
Simulation time 415797490 ps
CPU time 15.5 seconds
Started Jul 22 04:45:43 PM PDT 24
Finished Jul 22 04:45:59 PM PDT 24
Peak memory 225720 kb
Host smart-f25c0077-901f-425f-a84f-bb8dee4571f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271127815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2271127815
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2635456377
Short name T482
Test name
Test status
Simulation time 990481993 ps
CPU time 8.72 seconds
Started Jul 22 04:46:58 PM PDT 24
Finished Jul 22 04:47:07 PM PDT 24
Peak memory 225812 kb
Host smart-e32ce42a-0056-4181-9e33-a01640c91e36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635456377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2635456377
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2305528195
Short name T63
Test name
Test status
Simulation time 680576097 ps
CPU time 7.45 seconds
Started Jul 22 04:47:04 PM PDT 24
Finished Jul 22 04:47:13 PM PDT 24
Peak memory 218072 kb
Host smart-73e3aef6-6a54-4ad9-a1eb-118dd508bfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305528195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2305528195
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3743884656
Short name T593
Test name
Test status
Simulation time 26232861 ps
CPU time 1.37 seconds
Started Jul 22 04:45:46 PM PDT 24
Finished Jul 22 04:45:48 PM PDT 24
Peak memory 213464 kb
Host smart-0812924b-9883-49f4-863f-d33051e058e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743884656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3743884656
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3279213111
Short name T727
Test name
Test status
Simulation time 974205960 ps
CPU time 26.38 seconds
Started Jul 22 04:46:51 PM PDT 24
Finished Jul 22 04:47:18 PM PDT 24
Peak memory 250676 kb
Host smart-08b7239f-63c2-4ae8-8085-acd039402f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279213111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3279213111
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1736245045
Short name T793
Test name
Test status
Simulation time 83186340 ps
CPU time 7.58 seconds
Started Jul 22 04:45:38 PM PDT 24
Finished Jul 22 04:45:46 PM PDT 24
Peak memory 250076 kb
Host smart-e7725867-8231-4861-9d5e-ab1f0ebed213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736245045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1736245045
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.383286980
Short name T476
Test name
Test status
Simulation time 2559866429 ps
CPU time 99.55 seconds
Started Jul 22 04:45:46 PM PDT 24
Finished Jul 22 04:47:26 PM PDT 24
Peak memory 250628 kb
Host smart-0a30677a-9b18-4d94-81cf-bc88b21b35fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383286980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.383286980
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3482776187
Short name T253
Test name
Test status
Simulation time 92605815 ps
CPU time 0.9 seconds
Started Jul 22 04:45:36 PM PDT 24
Finished Jul 22 04:45:37 PM PDT 24
Peak memory 217472 kb
Host smart-8b0d93d6-d74c-4b35-9db2-f12be00940b4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482776187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3482776187
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.400508122
Short name T377
Test name
Test status
Simulation time 45682205 ps
CPU time 0.86 seconds
Started Jul 22 04:46:01 PM PDT 24
Finished Jul 22 04:46:02 PM PDT 24
Peak memory 208580 kb
Host smart-12501ab3-f973-4e07-a6da-e28fce383969
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400508122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.400508122
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.94126281
Short name T145
Test name
Test status
Simulation time 404125081 ps
CPU time 17.7 seconds
Started Jul 22 04:45:50 PM PDT 24
Finished Jul 22 04:46:08 PM PDT 24
Peak memory 218088 kb
Host smart-99c3857f-dd67-4ffa-b28e-7fc39634648c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94126281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.94126281
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.2902253339
Short name T194
Test name
Test status
Simulation time 636654311 ps
CPU time 7.77 seconds
Started Jul 22 04:45:44 PM PDT 24
Finished Jul 22 04:45:52 PM PDT 24
Peak memory 217412 kb
Host smart-c39fa780-9990-444f-a8ea-f16f7a0da65c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902253339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.2902253339
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1708365553
Short name T677
Test name
Test status
Simulation time 243262568 ps
CPU time 2.39 seconds
Started Jul 22 04:45:49 PM PDT 24
Finished Jul 22 04:45:52 PM PDT 24
Peak memory 218132 kb
Host smart-015e8d68-bae1-4998-ac7b-4e14c9c7db98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708365553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1708365553
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.1738624398
Short name T94
Test name
Test status
Simulation time 723230538 ps
CPU time 12.83 seconds
Started Jul 22 04:45:45 PM PDT 24
Finished Jul 22 04:45:59 PM PDT 24
Peak memory 219684 kb
Host smart-ed60a9ce-bd9c-4c03-b9fa-83c9db6cb612
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738624398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1738624398
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1093596010
Short name T804
Test name
Test status
Simulation time 2476702169 ps
CPU time 14.02 seconds
Started Jul 22 04:45:47 PM PDT 24
Finished Jul 22 04:46:01 PM PDT 24
Peak memory 218120 kb
Host smart-ab8b69ec-2e2e-4f89-985a-6be67795fc80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093596010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1093596010
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2092488828
Short name T321
Test name
Test status
Simulation time 540746859 ps
CPU time 7.23 seconds
Started Jul 22 04:45:45 PM PDT 24
Finished Jul 22 04:45:52 PM PDT 24
Peak memory 225696 kb
Host smart-db69fba2-87cb-4012-b4cd-1f61b1c5ed82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092488828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2092488828
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1754992126
Short name T62
Test name
Test status
Simulation time 307647927 ps
CPU time 7.29 seconds
Started Jul 22 04:45:49 PM PDT 24
Finished Jul 22 04:45:56 PM PDT 24
Peak memory 218156 kb
Host smart-93e62102-1b90-438c-adcc-6ccae8bcf8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754992126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1754992126
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.20812421
Short name T352
Test name
Test status
Simulation time 68676443 ps
CPU time 1.49 seconds
Started Jul 22 04:45:47 PM PDT 24
Finished Jul 22 04:45:49 PM PDT 24
Peak memory 213512 kb
Host smart-513f2aee-4f81-4dc4-9c14-f837e8d73fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20812421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.20812421
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.573104915
Short name T782
Test name
Test status
Simulation time 997869935 ps
CPU time 23.61 seconds
Started Jul 22 04:45:58 PM PDT 24
Finished Jul 22 04:46:23 PM PDT 24
Peak memory 250648 kb
Host smart-e034af40-926c-40d9-9e20-e5915c7e9caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573104915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.573104915
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3162436665
Short name T424
Test name
Test status
Simulation time 79114318 ps
CPU time 7.6 seconds
Started Jul 22 04:45:45 PM PDT 24
Finished Jul 22 04:45:53 PM PDT 24
Peak memory 250640 kb
Host smart-3beadfb6-0424-43ff-98d4-613f0eb34ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162436665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3162436665
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1431734897
Short name T180
Test name
Test status
Simulation time 11665826527 ps
CPU time 77.89 seconds
Started Jul 22 04:45:46 PM PDT 24
Finished Jul 22 04:47:04 PM PDT 24
Peak memory 278152 kb
Host smart-7265f5e1-fc4a-4c32-bac2-0912aaa18325
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431734897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1431734897
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.3034612818
Short name T375
Test name
Test status
Simulation time 47309964560 ps
CPU time 832.76 seconds
Started Jul 22 04:45:48 PM PDT 24
Finished Jul 22 04:59:41 PM PDT 24
Peak memory 267628 kb
Host smart-b8d27d31-81db-46bf-9d9b-1e05f631c230
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3034612818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.3034612818
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.4268183670
Short name T41
Test name
Test status
Simulation time 12474439 ps
CPU time 0.8 seconds
Started Jul 22 04:45:46 PM PDT 24
Finished Jul 22 04:45:47 PM PDT 24
Peak memory 208568 kb
Host smart-949f40fd-7b91-4abf-93cb-f49f6b46912b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268183670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.4268183670
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2905400672
Short name T463
Test name
Test status
Simulation time 79598849 ps
CPU time 1.01 seconds
Started Jul 22 04:45:55 PM PDT 24
Finished Jul 22 04:45:57 PM PDT 24
Peak memory 208620 kb
Host smart-9c9a82ba-6686-4cb1-9257-e876616928e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905400672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2905400672
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1640688404
Short name T770
Test name
Test status
Simulation time 321587043 ps
CPU time 13.29 seconds
Started Jul 22 04:46:14 PM PDT 24
Finished Jul 22 04:46:28 PM PDT 24
Peak memory 218048 kb
Host smart-7bc9054f-4a0b-4508-89cb-96600ba85694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640688404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1640688404
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.795425250
Short name T282
Test name
Test status
Simulation time 87988366 ps
CPU time 1.63 seconds
Started Jul 22 04:45:55 PM PDT 24
Finished Jul 22 04:45:57 PM PDT 24
Peak memory 216832 kb
Host smart-56c02931-2351-4c3d-97b4-139fdb76939d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795425250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.795425250
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1991479153
Short name T643
Test name
Test status
Simulation time 203855658 ps
CPU time 2.63 seconds
Started Jul 22 04:45:57 PM PDT 24
Finished Jul 22 04:46:00 PM PDT 24
Peak memory 222140 kb
Host smart-9b584981-7687-4e72-bbca-c8d97938cd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991479153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1991479153
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.236772473
Short name T693
Test name
Test status
Simulation time 3723430474 ps
CPU time 17 seconds
Started Jul 22 04:45:56 PM PDT 24
Finished Jul 22 04:46:13 PM PDT 24
Peak memory 225808 kb
Host smart-5abd51e7-178e-4869-89d1-3e4ad59381ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236772473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.236772473
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3951333648
Short name T780
Test name
Test status
Simulation time 915583717 ps
CPU time 22.69 seconds
Started Jul 22 04:45:57 PM PDT 24
Finished Jul 22 04:46:20 PM PDT 24
Peak memory 217952 kb
Host smart-f3ea907e-ea9f-44a9-87c4-78e9b9bc3a36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951333648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3951333648
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.80958068
Short name T433
Test name
Test status
Simulation time 300100314 ps
CPU time 8.1 seconds
Started Jul 22 04:45:57 PM PDT 24
Finished Jul 22 04:46:06 PM PDT 24
Peak memory 225716 kb
Host smart-a6f28c48-39d5-413d-a1c5-b83caa264b8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80958068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.80958068
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2003933416
Short name T765
Test name
Test status
Simulation time 4039808106 ps
CPU time 7.46 seconds
Started Jul 22 04:45:55 PM PDT 24
Finished Jul 22 04:46:03 PM PDT 24
Peak memory 218108 kb
Host smart-6600287f-8151-4923-ad1c-38449d0e479d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003933416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2003933416
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1335754969
Short name T68
Test name
Test status
Simulation time 58039259 ps
CPU time 2.47 seconds
Started Jul 22 04:45:59 PM PDT 24
Finished Jul 22 04:46:02 PM PDT 24
Peak memory 217416 kb
Host smart-385f7ece-b6cd-467f-9331-e1a44f3d12f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335754969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1335754969
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3892307079
Short name T32
Test name
Test status
Simulation time 449474010 ps
CPU time 21.46 seconds
Started Jul 22 04:45:49 PM PDT 24
Finished Jul 22 04:46:11 PM PDT 24
Peak memory 250760 kb
Host smart-f40c2b2c-5457-4290-95f3-9b6d1899fc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892307079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3892307079
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.520010518
Short name T839
Test name
Test status
Simulation time 178114632 ps
CPU time 7.01 seconds
Started Jul 22 04:47:05 PM PDT 24
Finished Jul 22 04:47:12 PM PDT 24
Peak memory 250244 kb
Host smart-a70fd083-5deb-40c9-8738-b6138a784e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520010518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.520010518
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1678009724
Short name T739
Test name
Test status
Simulation time 3520786389 ps
CPU time 140.25 seconds
Started Jul 22 04:45:55 PM PDT 24
Finished Jul 22 04:48:15 PM PDT 24
Peak memory 267112 kb
Host smart-db9cd0c4-af10-453c-b5ed-798b8671d39c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678009724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1678009724
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.895093843
Short name T837
Test name
Test status
Simulation time 29749688 ps
CPU time 0.99 seconds
Started Jul 22 04:46:06 PM PDT 24
Finished Jul 22 04:46:07 PM PDT 24
Peak memory 208548 kb
Host smart-064c697c-393e-42c1-8d1f-e67502d66273
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895093843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.895093843
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3757825185
Short name T541
Test name
Test status
Simulation time 424998572 ps
CPU time 13.8 seconds
Started Jul 22 04:45:57 PM PDT 24
Finished Jul 22 04:46:11 PM PDT 24
Peak memory 218008 kb
Host smart-d589c1b5-1041-4f1a-ad9f-c60f8dba7139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757825185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3757825185
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2565046853
Short name T28
Test name
Test status
Simulation time 830687357 ps
CPU time 8.42 seconds
Started Jul 22 04:45:56 PM PDT 24
Finished Jul 22 04:46:05 PM PDT 24
Peak memory 217416 kb
Host smart-80fceb4b-1951-4d35-8e2b-76b1c7e995e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565046853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2565046853
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.388701463
Short name T639
Test name
Test status
Simulation time 52380252 ps
CPU time 2.01 seconds
Started Jul 22 04:45:55 PM PDT 24
Finished Jul 22 04:45:58 PM PDT 24
Peak memory 217916 kb
Host smart-8c2e9323-3bc8-42de-9f37-a536fb7d896e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388701463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.388701463
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1306039541
Short name T638
Test name
Test status
Simulation time 196160277 ps
CPU time 7.95 seconds
Started Jul 22 04:45:57 PM PDT 24
Finished Jul 22 04:46:06 PM PDT 24
Peak memory 225792 kb
Host smart-450d5fa6-26c7-44ff-a215-73b6ffa38e1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306039541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1306039541
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3239767793
Short name T622
Test name
Test status
Simulation time 500838981 ps
CPU time 11.89 seconds
Started Jul 22 04:46:08 PM PDT 24
Finished Jul 22 04:46:20 PM PDT 24
Peak memory 225808 kb
Host smart-9dfab993-28dd-48fb-8197-5ebad37ca742
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239767793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3239767793
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3929748281
Short name T252
Test name
Test status
Simulation time 406323436 ps
CPU time 6.92 seconds
Started Jul 22 04:45:56 PM PDT 24
Finished Jul 22 04:46:03 PM PDT 24
Peak memory 225712 kb
Host smart-83d4af4c-366f-449a-93ee-5ac4ec1b981a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929748281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3929748281
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3719950096
Short name T165
Test name
Test status
Simulation time 365744007 ps
CPU time 9.36 seconds
Started Jul 22 04:46:08 PM PDT 24
Finished Jul 22 04:46:18 PM PDT 24
Peak memory 225772 kb
Host smart-68d16d4e-79cd-4daa-9bcc-4f5ad2a06284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719950096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3719950096
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.927563417
Short name T65
Test name
Test status
Simulation time 49581071 ps
CPU time 3.95 seconds
Started Jul 22 04:45:56 PM PDT 24
Finished Jul 22 04:46:00 PM PDT 24
Peak memory 217480 kb
Host smart-75093b11-08cf-4f5a-ba13-a2ab7a4c8163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927563417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.927563417
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.159053566
Short name T812
Test name
Test status
Simulation time 2620663430 ps
CPU time 29.7 seconds
Started Jul 22 04:45:56 PM PDT 24
Finished Jul 22 04:46:26 PM PDT 24
Peak memory 250716 kb
Host smart-85f760d6-2ffb-41d6-aeac-41a4779f1dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159053566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.159053566
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.386928182
Short name T304
Test name
Test status
Simulation time 284201549 ps
CPU time 8.87 seconds
Started Jul 22 04:45:57 PM PDT 24
Finished Jul 22 04:46:06 PM PDT 24
Peak memory 250676 kb
Host smart-df073fbf-9976-448d-b3da-f29ed08e1fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386928182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.386928182
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.167973593
Short name T195
Test name
Test status
Simulation time 4755628757 ps
CPU time 120.04 seconds
Started Jul 22 04:46:04 PM PDT 24
Finished Jul 22 04:48:05 PM PDT 24
Peak memory 283520 kb
Host smart-87a30912-6ca5-4c30-b076-c97438f26517
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167973593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.167973593
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1319071917
Short name T538
Test name
Test status
Simulation time 15039081 ps
CPU time 0.82 seconds
Started Jul 22 04:46:12 PM PDT 24
Finished Jul 22 04:46:13 PM PDT 24
Peak memory 208740 kb
Host smart-92ba0f63-7a9e-40fa-b34f-fd33053ce5fb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319071917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1319071917
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2108111424
Short name T431
Test name
Test status
Simulation time 64704859 ps
CPU time 0.9 seconds
Started Jul 22 04:46:57 PM PDT 24
Finished Jul 22 04:46:58 PM PDT 24
Peak memory 208496 kb
Host smart-3797f3f3-2d87-40db-9061-cb4801069b99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108111424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2108111424
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2710129009
Short name T647
Test name
Test status
Simulation time 223193413 ps
CPU time 11.7 seconds
Started Jul 22 04:46:06 PM PDT 24
Finished Jul 22 04:46:19 PM PDT 24
Peak memory 217916 kb
Host smart-198ec60a-d3eb-42d2-bc76-7134b7f6374b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710129009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2710129009
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2809829799
Short name T729
Test name
Test status
Simulation time 987387427 ps
CPU time 13.48 seconds
Started Jul 22 04:46:07 PM PDT 24
Finished Jul 22 04:46:21 PM PDT 24
Peak memory 217480 kb
Host smart-baa5cf25-b653-4653-aa41-8942bb552bc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809829799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2809829799
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.550402913
Short name T699
Test name
Test status
Simulation time 428338617 ps
CPU time 4.51 seconds
Started Jul 22 04:46:07 PM PDT 24
Finished Jul 22 04:46:12 PM PDT 24
Peak memory 217984 kb
Host smart-75f1a236-cb2c-4d1e-b4e4-8f862b685038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550402913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.550402913
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.985937330
Short name T784
Test name
Test status
Simulation time 5334807969 ps
CPU time 10.41 seconds
Started Jul 22 04:46:06 PM PDT 24
Finished Jul 22 04:46:17 PM PDT 24
Peak memory 225804 kb
Host smart-447c9c27-b4f2-4e5e-a8bc-d2fa7ab3a7eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985937330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.985937330
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.792719507
Short name T339
Test name
Test status
Simulation time 365339212 ps
CPU time 8.67 seconds
Started Jul 22 04:46:06 PM PDT 24
Finished Jul 22 04:46:15 PM PDT 24
Peak memory 225812 kb
Host smart-c00610dc-e9e8-4d1d-9074-eabd69d80381
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792719507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.792719507
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1252801096
Short name T801
Test name
Test status
Simulation time 186756149 ps
CPU time 7.36 seconds
Started Jul 22 04:46:07 PM PDT 24
Finished Jul 22 04:46:15 PM PDT 24
Peak memory 218100 kb
Host smart-81c75c66-d5a7-4e15-844b-c0b12a6f21e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252801096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1252801096
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.316516790
Short name T573
Test name
Test status
Simulation time 61988672 ps
CPU time 3.35 seconds
Started Jul 22 04:46:07 PM PDT 24
Finished Jul 22 04:46:11 PM PDT 24
Peak memory 214372 kb
Host smart-ab3bfd1f-2a99-48c4-bd60-bda45d4d6b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316516790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.316516790
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3132935335
Short name T345
Test name
Test status
Simulation time 1148892251 ps
CPU time 26.04 seconds
Started Jul 22 04:46:06 PM PDT 24
Finished Jul 22 04:46:32 PM PDT 24
Peak memory 250672 kb
Host smart-89264c53-ce8d-41f3-b2bc-0c17e5f26859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132935335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3132935335
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2182177655
Short name T291
Test name
Test status
Simulation time 219347719 ps
CPU time 9.66 seconds
Started Jul 22 04:46:07 PM PDT 24
Finished Jul 22 04:46:17 PM PDT 24
Peak memory 250708 kb
Host smart-0145c91c-17e7-4353-a5f5-a7966b8948ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182177655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2182177655
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.759620017
Short name T846
Test name
Test status
Simulation time 55537443030 ps
CPU time 202.92 seconds
Started Jul 22 04:46:06 PM PDT 24
Finished Jul 22 04:49:30 PM PDT 24
Peak memory 330268 kb
Host smart-cd873a5b-8313-4648-a5c4-6ce56cc255ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759620017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.759620017
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.349123653
Short name T160
Test name
Test status
Simulation time 40948320247 ps
CPU time 163.04 seconds
Started Jul 22 04:47:50 PM PDT 24
Finished Jul 22 04:50:34 PM PDT 24
Peak memory 226164 kb
Host smart-c9184144-7ede-4916-9e71-db6749041093
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=349123653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.349123653
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.132983856
Short name T445
Test name
Test status
Simulation time 41072934 ps
CPU time 0.93 seconds
Started Jul 22 04:46:06 PM PDT 24
Finished Jul 22 04:46:07 PM PDT 24
Peak memory 211676 kb
Host smart-82a8abc3-4779-4437-9b43-19408fc64fad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132983856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.132983856
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3386180310
Short name T508
Test name
Test status
Simulation time 44840936 ps
CPU time 1.61 seconds
Started Jul 22 04:43:37 PM PDT 24
Finished Jul 22 04:43:39 PM PDT 24
Peak memory 208708 kb
Host smart-8cc7d947-e1cf-4eac-92e9-5b0fde73b453
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386180310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3386180310
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.304135342
Short name T171
Test name
Test status
Simulation time 13011806 ps
CPU time 0.94 seconds
Started Jul 22 04:43:26 PM PDT 24
Finished Jul 22 04:43:28 PM PDT 24
Peak memory 208476 kb
Host smart-27cab997-b07f-4eb3-9141-19505b2110fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304135342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.304135342
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2724575122
Short name T368
Test name
Test status
Simulation time 327155504 ps
CPU time 10.05 seconds
Started Jul 22 04:43:25 PM PDT 24
Finished Jul 22 04:43:36 PM PDT 24
Peak memory 217952 kb
Host smart-1b6489aa-088c-4d92-acb4-e03ce459071e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724575122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2724575122
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1026837712
Short name T280
Test name
Test status
Simulation time 92879099 ps
CPU time 1.9 seconds
Started Jul 22 04:43:35 PM PDT 24
Finished Jul 22 04:43:38 PM PDT 24
Peak memory 216768 kb
Host smart-e91d2bf6-80ac-4099-9349-dad6c5410bfe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026837712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1026837712
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.65798418
Short name T365
Test name
Test status
Simulation time 4629254839 ps
CPU time 62.35 seconds
Started Jul 22 04:43:34 PM PDT 24
Finished Jul 22 04:44:37 PM PDT 24
Peak memory 218596 kb
Host smart-3725230d-ec6b-48ec-a53d-2ab33f434b5c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65798418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_erro
rs.65798418
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3306078523
Short name T6
Test name
Test status
Simulation time 2036452709 ps
CPU time 13.78 seconds
Started Jul 22 04:43:43 PM PDT 24
Finished Jul 22 04:43:57 PM PDT 24
Peak memory 217384 kb
Host smart-98412bf1-577b-4ab1-b0a0-2b9b55afaec4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306078523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
306078523
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.4234844929
Short name T613
Test name
Test status
Simulation time 841521180 ps
CPU time 24.13 seconds
Started Jul 22 04:43:35 PM PDT 24
Finished Jul 22 04:44:00 PM PDT 24
Peak memory 225340 kb
Host smart-aa7d6f0a-8e3d-4f58-960c-925bf8d6ba3b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234844929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.4234844929
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3122933025
Short name T574
Test name
Test status
Simulation time 4665153692 ps
CPU time 19.41 seconds
Started Jul 22 04:43:36 PM PDT 24
Finished Jul 22 04:43:56 PM PDT 24
Peak memory 217480 kb
Host smart-7d6debb1-7971-4632-959c-ce5733dcc9c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122933025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3122933025
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1963797699
Short name T634
Test name
Test status
Simulation time 600341679 ps
CPU time 8.82 seconds
Started Jul 22 04:43:43 PM PDT 24
Finished Jul 22 04:43:52 PM PDT 24
Peak memory 217340 kb
Host smart-03131367-8afe-4367-b8a0-e9b26f6c373d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963797699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1963797699
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3958147741
Short name T267
Test name
Test status
Simulation time 5063628932 ps
CPU time 34.97 seconds
Started Jul 22 04:43:36 PM PDT 24
Finished Jul 22 04:44:12 PM PDT 24
Peak memory 250600 kb
Host smart-7c99b96d-5d48-4d2c-98db-b408f7565bb0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958147741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3958147741
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.511937686
Short name T861
Test name
Test status
Simulation time 1349465845 ps
CPU time 15.67 seconds
Started Jul 22 04:43:40 PM PDT 24
Finished Jul 22 04:43:56 PM PDT 24
Peak memory 250464 kb
Host smart-d4c87fc4-c134-4d1c-a85b-4e3793352f69
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511937686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.511937686
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.998668855
Short name T744
Test name
Test status
Simulation time 112641078 ps
CPU time 2.55 seconds
Started Jul 22 04:43:28 PM PDT 24
Finished Jul 22 04:43:31 PM PDT 24
Peak memory 218000 kb
Host smart-d9ce9710-2674-463d-9427-3a84d7cdb994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998668855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.998668855
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2805719634
Short name T684
Test name
Test status
Simulation time 233433718 ps
CPU time 12.66 seconds
Started Jul 22 04:43:30 PM PDT 24
Finished Jul 22 04:43:43 PM PDT 24
Peak memory 217404 kb
Host smart-fe242b7e-c4b3-4c99-a2bd-dc4d91a7e607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805719634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2805719634
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2533725296
Short name T84
Test name
Test status
Simulation time 295058772 ps
CPU time 22.2 seconds
Started Jul 22 04:43:36 PM PDT 24
Finished Jul 22 04:43:59 PM PDT 24
Peak memory 281512 kb
Host smart-1b7a788b-9ceb-485b-84e8-b7608ab63f08
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533725296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2533725296
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.869721800
Short name T658
Test name
Test status
Simulation time 1216830881 ps
CPU time 14.08 seconds
Started Jul 22 04:43:36 PM PDT 24
Finished Jul 22 04:43:51 PM PDT 24
Peak memory 218588 kb
Host smart-e36ae96b-22ac-406d-afb8-4cfc16769076
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869721800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.869721800
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.4281699697
Short name T143
Test name
Test status
Simulation time 376605314 ps
CPU time 12.59 seconds
Started Jul 22 04:43:43 PM PDT 24
Finished Jul 22 04:43:56 PM PDT 24
Peak memory 225540 kb
Host smart-849c093e-a291-4e98-bcb9-18649e136b8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281699697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.4281699697
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1554005716
Short name T657
Test name
Test status
Simulation time 184034675 ps
CPU time 6.45 seconds
Started Jul 22 04:43:36 PM PDT 24
Finished Jul 22 04:43:44 PM PDT 24
Peak memory 225812 kb
Host smart-42c46e66-0a58-4d05-a993-c23730b4b917
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554005716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
554005716
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.4020442457
Short name T732
Test name
Test status
Simulation time 4709017975 ps
CPU time 6.97 seconds
Started Jul 22 04:43:26 PM PDT 24
Finished Jul 22 04:43:33 PM PDT 24
Peak memory 218216 kb
Host smart-4e4d4332-6678-4516-ad70-074cf997c727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020442457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.4020442457
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2322634109
Short name T855
Test name
Test status
Simulation time 24452257 ps
CPU time 1.55 seconds
Started Jul 22 04:43:29 PM PDT 24
Finished Jul 22 04:43:31 PM PDT 24
Peak memory 213656 kb
Host smart-3b956a78-4587-4479-ad82-03fb99dfded0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322634109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2322634109
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.479665846
Short name T803
Test name
Test status
Simulation time 822039352 ps
CPU time 23.09 seconds
Started Jul 22 04:43:27 PM PDT 24
Finished Jul 22 04:43:50 PM PDT 24
Peak memory 250672 kb
Host smart-2ae6930b-6e2b-408a-a8f9-e772be4c4eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479665846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.479665846
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1698583889
Short name T83
Test name
Test status
Simulation time 86831952 ps
CPU time 8.17 seconds
Started Jul 22 04:43:29 PM PDT 24
Finished Jul 22 04:43:38 PM PDT 24
Peak memory 250800 kb
Host smart-48bd9c43-303b-447b-a172-99464ae39013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698583889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1698583889
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1846898669
Short name T271
Test name
Test status
Simulation time 130283168 ps
CPU time 1.08 seconds
Started Jul 22 04:43:24 PM PDT 24
Finished Jul 22 04:43:26 PM PDT 24
Peak memory 212648 kb
Host smart-fe4a3edf-3567-41f4-b61d-4589d6a17640
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846898669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1846898669
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.642742088
Short name T86
Test name
Test status
Simulation time 27448232 ps
CPU time 1.05 seconds
Started Jul 22 04:46:08 PM PDT 24
Finished Jul 22 04:46:09 PM PDT 24
Peak memory 208708 kb
Host smart-960f29ab-ad37-428c-8e9c-bd618a137f38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642742088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.642742088
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3943636039
Short name T226
Test name
Test status
Simulation time 443868935 ps
CPU time 15.54 seconds
Started Jul 22 04:46:06 PM PDT 24
Finished Jul 22 04:46:22 PM PDT 24
Peak memory 218028 kb
Host smart-393e8c5f-514a-47c7-b559-e88f627e257d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943636039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3943636039
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.4018233168
Short name T27
Test name
Test status
Simulation time 3778061774 ps
CPU time 5.38 seconds
Started Jul 22 04:47:52 PM PDT 24
Finished Jul 22 04:47:58 PM PDT 24
Peak memory 217376 kb
Host smart-118b0738-3f5e-412f-87a5-d2b30a542f96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018233168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.4018233168
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2838281441
Short name T485
Test name
Test status
Simulation time 67907364 ps
CPU time 2.35 seconds
Started Jul 22 04:46:06 PM PDT 24
Finished Jul 22 04:46:09 PM PDT 24
Peak memory 218068 kb
Host smart-ced773a0-ae48-407b-ad67-680152e456c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838281441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2838281441
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3054595578
Short name T294
Test name
Test status
Simulation time 501459529 ps
CPU time 15.9 seconds
Started Jul 22 04:46:07 PM PDT 24
Finished Jul 22 04:46:23 PM PDT 24
Peak memory 225792 kb
Host smart-48d81c4d-267e-47cf-8c93-aef7368a5178
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054595578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3054595578
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3016667451
Short name T563
Test name
Test status
Simulation time 952627605 ps
CPU time 11.26 seconds
Started Jul 22 04:46:07 PM PDT 24
Finished Jul 22 04:46:19 PM PDT 24
Peak memory 218036 kb
Host smart-9a7342b3-b276-44c3-9d4d-bb9242794c57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016667451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3016667451
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.432854483
Short name T455
Test name
Test status
Simulation time 1018864286 ps
CPU time 9.3 seconds
Started Jul 22 04:46:10 PM PDT 24
Finished Jul 22 04:46:20 PM PDT 24
Peak memory 225796 kb
Host smart-9a9a4906-8a7b-4f37-a10b-f2d85ac7a235
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432854483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.432854483
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.4282847884
Short name T477
Test name
Test status
Simulation time 205380281 ps
CPU time 6.82 seconds
Started Jul 22 04:47:52 PM PDT 24
Finished Jul 22 04:48:00 PM PDT 24
Peak memory 217996 kb
Host smart-7ca04acd-b421-47cd-a1e3-d3c27fe27692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282847884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.4282847884
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3400499528
Short name T306
Test name
Test status
Simulation time 47881358 ps
CPU time 2.47 seconds
Started Jul 22 04:46:18 PM PDT 24
Finished Jul 22 04:46:21 PM PDT 24
Peak memory 213956 kb
Host smart-1a4428ef-9197-4195-a31c-171d6f6dd5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400499528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3400499528
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3167195905
Short name T332
Test name
Test status
Simulation time 820948032 ps
CPU time 31.11 seconds
Started Jul 22 04:46:07 PM PDT 24
Finished Jul 22 04:46:39 PM PDT 24
Peak memory 250664 kb
Host smart-81fa39d2-fb68-4fff-9820-e76eccb36dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167195905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3167195905
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1637077927
Short name T604
Test name
Test status
Simulation time 238274425 ps
CPU time 7.51 seconds
Started Jul 22 04:46:06 PM PDT 24
Finished Jul 22 04:46:14 PM PDT 24
Peak memory 250592 kb
Host smart-8b97d8cf-ac54-46e9-8763-5a68962dedf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637077927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1637077927
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1029226729
Short name T525
Test name
Test status
Simulation time 94118619633 ps
CPU time 248.99 seconds
Started Jul 22 04:46:05 PM PDT 24
Finished Jul 22 04:50:15 PM PDT 24
Peak memory 283356 kb
Host smart-0aab6863-f3e9-4a16-9426-177faeb940c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029226729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1029226729
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.3331093808
Short name T142
Test name
Test status
Simulation time 183171578142 ps
CPU time 1560.74 seconds
Started Jul 22 04:46:17 PM PDT 24
Finished Jul 22 05:12:19 PM PDT 24
Peak memory 480252 kb
Host smart-fb318a5e-3a17-44c3-a187-1fc06ae9c619
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3331093808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.3331093808
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3767891373
Short name T633
Test name
Test status
Simulation time 23904120 ps
CPU time 0.81 seconds
Started Jul 22 04:46:07 PM PDT 24
Finished Jul 22 04:46:09 PM PDT 24
Peak memory 208584 kb
Host smart-ad029602-90d9-48b3-9761-5b743730c99e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767891373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3767891373
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3081976220
Short name T619
Test name
Test status
Simulation time 94900425 ps
CPU time 1.32 seconds
Started Jul 22 04:46:18 PM PDT 24
Finished Jul 22 04:46:20 PM PDT 24
Peak memory 208752 kb
Host smart-1653b55d-3397-421f-8d67-64f90828f49c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081976220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3081976220
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3590448237
Short name T816
Test name
Test status
Simulation time 331818110 ps
CPU time 13.48 seconds
Started Jul 22 04:46:16 PM PDT 24
Finished Jul 22 04:46:30 PM PDT 24
Peak memory 218092 kb
Host smart-c83e7687-48f8-49fc-87ef-37aa78c370e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590448237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3590448237
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3976330493
Short name T535
Test name
Test status
Simulation time 947015064 ps
CPU time 17.73 seconds
Started Jul 22 04:46:16 PM PDT 24
Finished Jul 22 04:46:34 PM PDT 24
Peak memory 217416 kb
Host smart-5b8c64ad-915c-4e83-9859-3709cc7f7660
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976330493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3976330493
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.780402809
Short name T774
Test name
Test status
Simulation time 57351965 ps
CPU time 3.34 seconds
Started Jul 22 04:46:21 PM PDT 24
Finished Jul 22 04:46:25 PM PDT 24
Peak memory 222340 kb
Host smart-13bb14e4-d8b1-4c6a-93f1-cec5561f1337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780402809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.780402809
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2290854640
Short name T166
Test name
Test status
Simulation time 684545364 ps
CPU time 12.67 seconds
Started Jul 22 04:46:15 PM PDT 24
Finished Jul 22 04:46:29 PM PDT 24
Peak memory 218056 kb
Host smart-b7e55361-cfaf-4c4e-8bc5-85c653cde628
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290854640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2290854640
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2474274479
Short name T709
Test name
Test status
Simulation time 675389310 ps
CPU time 8.26 seconds
Started Jul 22 04:46:16 PM PDT 24
Finished Jul 22 04:46:25 PM PDT 24
Peak memory 225812 kb
Host smart-8520c28b-b13f-4c97-af87-41aeb1494c05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474274479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2474274479
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3330339939
Short name T747
Test name
Test status
Simulation time 1214278704 ps
CPU time 8.15 seconds
Started Jul 22 04:46:17 PM PDT 24
Finished Jul 22 04:46:25 PM PDT 24
Peak memory 218148 kb
Host smart-7a2d175c-7440-4ad9-9f12-6f8a5f801b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330339939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3330339939
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.4199305747
Short name T567
Test name
Test status
Simulation time 36287973 ps
CPU time 2.85 seconds
Started Jul 22 04:46:16 PM PDT 24
Finished Jul 22 04:46:20 PM PDT 24
Peak memory 222784 kb
Host smart-29ef8e15-1d0b-4ca8-bd9d-d1876dafb7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199305747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.4199305747
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1571512100
Short name T840
Test name
Test status
Simulation time 601356208 ps
CPU time 29.64 seconds
Started Jul 22 04:46:19 PM PDT 24
Finished Jul 22 04:46:49 PM PDT 24
Peak memory 250644 kb
Host smart-1f5f5b5e-4a07-417c-ac17-da333e8a5e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571512100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1571512100
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.707271011
Short name T813
Test name
Test status
Simulation time 370886920 ps
CPU time 11.07 seconds
Started Jul 22 04:46:16 PM PDT 24
Finished Jul 22 04:46:28 PM PDT 24
Peak memory 250736 kb
Host smart-dfb2e11f-5da4-417d-aaa4-ae98be1b6780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707271011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.707271011
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2245881344
Short name T381
Test name
Test status
Simulation time 36044754 ps
CPU time 0.95 seconds
Started Jul 22 04:46:14 PM PDT 24
Finished Jul 22 04:46:16 PM PDT 24
Peak memory 211732 kb
Host smart-e10cc4ed-340c-4a48-9767-afc68db072fa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245881344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2245881344
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.4225115757
Short name T740
Test name
Test status
Simulation time 19509530 ps
CPU time 0.99 seconds
Started Jul 22 04:47:01 PM PDT 24
Finished Jul 22 04:47:03 PM PDT 24
Peak memory 208656 kb
Host smart-91aa2adc-4db4-4d4f-9897-caa3c2a844c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225115757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.4225115757
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.4088757171
Short name T245
Test name
Test status
Simulation time 200412829 ps
CPU time 8.35 seconds
Started Jul 22 04:46:15 PM PDT 24
Finished Jul 22 04:46:24 PM PDT 24
Peak memory 218160 kb
Host smart-b94318e6-8e79-4de9-9d38-a7b010a35a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088757171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.4088757171
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3994273440
Short name T799
Test name
Test status
Simulation time 842578937 ps
CPU time 6.01 seconds
Started Jul 22 04:46:17 PM PDT 24
Finished Jul 22 04:46:23 PM PDT 24
Peak memory 216876 kb
Host smart-7e757a23-457d-445a-9f5c-0b79e94c8244
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994273440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3994273440
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.2555997974
Short name T184
Test name
Test status
Simulation time 45805217 ps
CPU time 2.65 seconds
Started Jul 22 04:47:52 PM PDT 24
Finished Jul 22 04:47:56 PM PDT 24
Peak memory 217928 kb
Host smart-2052ef11-0f24-4bdb-a41e-b41b6c1e98a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555997974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2555997974
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.4030469360
Short name T363
Test name
Test status
Simulation time 1163577222 ps
CPU time 13.33 seconds
Started Jul 22 04:46:15 PM PDT 24
Finished Jul 22 04:46:29 PM PDT 24
Peak memory 218232 kb
Host smart-f2e7e35d-6d18-4c9a-b13a-bac036989aad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030469360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.4030469360
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3313916456
Short name T701
Test name
Test status
Simulation time 721389466 ps
CPU time 13.84 seconds
Started Jul 22 04:46:16 PM PDT 24
Finished Jul 22 04:46:30 PM PDT 24
Peak memory 218036 kb
Host smart-f68e95fe-3c27-4053-96b9-719e39757a6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313916456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3313916456
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2424902787
Short name T623
Test name
Test status
Simulation time 1301174721 ps
CPU time 9.38 seconds
Started Jul 22 04:46:52 PM PDT 24
Finished Jul 22 04:47:02 PM PDT 24
Peak memory 225804 kb
Host smart-0bdca90b-7c30-477f-a93a-3a5475efed54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424902787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2424902787
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.150125727
Short name T503
Test name
Test status
Simulation time 678745730 ps
CPU time 13.24 seconds
Started Jul 22 04:46:17 PM PDT 24
Finished Jul 22 04:46:31 PM PDT 24
Peak memory 218040 kb
Host smart-c42e9504-c7ee-4fd8-b14b-e3a17ed49ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150125727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.150125727
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.1909261812
Short name T233
Test name
Test status
Simulation time 15914179 ps
CPU time 1.53 seconds
Started Jul 22 04:46:17 PM PDT 24
Finished Jul 22 04:46:19 PM PDT 24
Peak memory 213484 kb
Host smart-7eeea242-7eaf-4ea4-b74e-3878d12a4e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909261812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1909261812
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.4003845277
Short name T384
Test name
Test status
Simulation time 259392920 ps
CPU time 36.44 seconds
Started Jul 22 04:47:37 PM PDT 24
Finished Jul 22 04:48:14 PM PDT 24
Peak memory 250812 kb
Host smart-41578f6b-7c1b-4cba-9d3a-3bc349ba26a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003845277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.4003845277
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3884696679
Short name T338
Test name
Test status
Simulation time 86052676 ps
CPU time 3.16 seconds
Started Jul 22 04:46:17 PM PDT 24
Finished Jul 22 04:46:21 PM PDT 24
Peak memory 222196 kb
Host smart-ca03cae3-f9c3-491f-8ef9-08d06728f784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884696679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3884696679
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.4021915383
Short name T350
Test name
Test status
Simulation time 6441664436 ps
CPU time 62 seconds
Started Jul 22 04:46:16 PM PDT 24
Finished Jul 22 04:47:18 PM PDT 24
Peak memory 250648 kb
Host smart-638a5e6b-3915-4172-8457-9f76ddc2e3a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021915383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.4021915383
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.1447386795
Short name T141
Test name
Test status
Simulation time 125228069599 ps
CPU time 1656.63 seconds
Started Jul 22 04:46:14 PM PDT 24
Finished Jul 22 05:13:51 PM PDT 24
Peak memory 957596 kb
Host smart-40cdf4ca-310e-4545-b3f8-e3e8dc262c03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1447386795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.1447386795
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2912184742
Short name T322
Test name
Test status
Simulation time 14146840 ps
CPU time 0.97 seconds
Started Jul 22 04:46:15 PM PDT 24
Finished Jul 22 04:46:17 PM PDT 24
Peak memory 211612 kb
Host smart-c8eb1ce0-5737-4171-8318-d53de5d6d7e5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912184742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2912184742
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1093993096
Short name T481
Test name
Test status
Simulation time 18217563 ps
CPU time 0.92 seconds
Started Jul 22 04:46:26 PM PDT 24
Finished Jul 22 04:46:27 PM PDT 24
Peak memory 208640 kb
Host smart-a8b05c34-8a4e-42c8-b439-a77438f87fb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093993096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1093993096
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3951848563
Short name T524
Test name
Test status
Simulation time 401982207 ps
CPU time 11.43 seconds
Started Jul 22 04:46:15 PM PDT 24
Finished Jul 22 04:46:27 PM PDT 24
Peak memory 218056 kb
Host smart-b92241a2-aff8-4023-b3af-5ccbd0c6ef1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951848563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3951848563
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.47648456
Short name T487
Test name
Test status
Simulation time 57669354 ps
CPU time 1.48 seconds
Started Jul 22 04:46:27 PM PDT 24
Finished Jul 22 04:46:29 PM PDT 24
Peak memory 215772 kb
Host smart-8215d812-c14f-4ff4-80e7-1d22f17050b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47648456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.47648456
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3403710134
Short name T596
Test name
Test status
Simulation time 119195132 ps
CPU time 3.46 seconds
Started Jul 22 04:46:17 PM PDT 24
Finished Jul 22 04:46:21 PM PDT 24
Peak memory 222404 kb
Host smart-f5e69671-5987-451f-8f77-0e6b21e3e7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403710134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3403710134
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2794830311
Short name T286
Test name
Test status
Simulation time 829408609 ps
CPU time 11.18 seconds
Started Jul 22 04:46:24 PM PDT 24
Finished Jul 22 04:46:36 PM PDT 24
Peak memory 218148 kb
Host smart-04082f1a-32ff-4c5b-994a-31b0497647c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794830311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2794830311
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2911751736
Short name T274
Test name
Test status
Simulation time 262143428 ps
CPU time 8.18 seconds
Started Jul 22 04:46:21 PM PDT 24
Finished Jul 22 04:46:30 PM PDT 24
Peak memory 217948 kb
Host smart-0c411af1-766d-4153-ad79-e6d1f7e98ff7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911751736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2911751736
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.520357282
Short name T288
Test name
Test status
Simulation time 5061337327 ps
CPU time 8.87 seconds
Started Jul 22 04:46:25 PM PDT 24
Finished Jul 22 04:46:35 PM PDT 24
Peak memory 225792 kb
Host smart-9632e751-91a7-486c-ba2f-3beec198384f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520357282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.520357282
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3449940206
Short name T235
Test name
Test status
Simulation time 490416944 ps
CPU time 14.32 seconds
Started Jul 22 04:46:17 PM PDT 24
Finished Jul 22 04:46:32 PM PDT 24
Peak memory 218156 kb
Host smart-aad4592d-4a49-4d5c-9145-c84384ea432f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449940206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3449940206
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3733812735
Short name T78
Test name
Test status
Simulation time 247370761 ps
CPU time 3.7 seconds
Started Jul 22 04:46:15 PM PDT 24
Finished Jul 22 04:46:20 PM PDT 24
Peak memory 217420 kb
Host smart-06ed420f-5ff1-439b-a2ca-1d6305897678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733812735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3733812735
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3874322885
Short name T828
Test name
Test status
Simulation time 500131867 ps
CPU time 24.85 seconds
Started Jul 22 04:46:17 PM PDT 24
Finished Jul 22 04:46:43 PM PDT 24
Peak memory 250644 kb
Host smart-ad6a2f89-1bb7-4691-92f2-fd33b50121ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874322885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3874322885
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2737355856
Short name T270
Test name
Test status
Simulation time 90177604 ps
CPU time 6.56 seconds
Started Jul 22 04:47:30 PM PDT 24
Finished Jul 22 04:47:37 PM PDT 24
Peak memory 250240 kb
Host smart-a0e1ac4c-b88a-44ac-9925-7f8778ae2a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737355856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2737355856
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.144687879
Short name T66
Test name
Test status
Simulation time 4259300112 ps
CPU time 112.32 seconds
Started Jul 22 04:46:27 PM PDT 24
Finished Jul 22 04:48:20 PM PDT 24
Peak memory 250860 kb
Host smart-b74bb7a1-b5da-44ca-9602-87a8d853eedc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144687879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.144687879
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.1018472291
Short name T53
Test name
Test status
Simulation time 116915847156 ps
CPU time 789.79 seconds
Started Jul 22 04:46:25 PM PDT 24
Finished Jul 22 04:59:36 PM PDT 24
Peak memory 397528 kb
Host smart-b05da829-cf27-4aa2-a2ec-45e4fd8f97ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1018472291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.1018472291
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.222750187
Short name T69
Test name
Test status
Simulation time 19042097 ps
CPU time 1.01 seconds
Started Jul 22 04:46:18 PM PDT 24
Finished Jul 22 04:46:19 PM PDT 24
Peak memory 212540 kb
Host smart-ff24db1e-9b99-48c6-9bfc-ef782b2c1ebb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222750187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.222750187
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3006734820
Short name T156
Test name
Test status
Simulation time 38595374 ps
CPU time 0.85 seconds
Started Jul 22 04:46:25 PM PDT 24
Finished Jul 22 04:46:27 PM PDT 24
Peak memory 208444 kb
Host smart-27de63e0-2d41-403a-a99d-eac6f0b041ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006734820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3006734820
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2501820678
Short name T45
Test name
Test status
Simulation time 537288290 ps
CPU time 15.64 seconds
Started Jul 22 04:47:33 PM PDT 24
Finished Jul 22 04:47:49 PM PDT 24
Peak memory 218028 kb
Host smart-a4ed5cf3-0af1-48d7-a141-c12a93c11d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501820678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2501820678
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3712543049
Short name T10
Test name
Test status
Simulation time 399822527 ps
CPU time 4.72 seconds
Started Jul 22 04:46:24 PM PDT 24
Finished Jul 22 04:46:29 PM PDT 24
Peak memory 217492 kb
Host smart-b25f5d7b-fc0b-4c14-9d67-01f8cfb3c3b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712543049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3712543049
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3369811363
Short name T225
Test name
Test status
Simulation time 34355239 ps
CPU time 1.53 seconds
Started Jul 22 04:46:25 PM PDT 24
Finished Jul 22 04:46:27 PM PDT 24
Peak memory 217928 kb
Host smart-05c8bfad-c121-4a35-ae38-1a5fcd536a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369811363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3369811363
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.713920231
Short name T570
Test name
Test status
Simulation time 966855262 ps
CPU time 10.85 seconds
Started Jul 22 04:46:27 PM PDT 24
Finished Jul 22 04:46:39 PM PDT 24
Peak memory 218140 kb
Host smart-f64d5b8d-0b8f-4098-b4c3-bbb182fb5184
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713920231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.713920231
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2060625473
Short name T249
Test name
Test status
Simulation time 1837329234 ps
CPU time 12.28 seconds
Started Jul 22 04:48:29 PM PDT 24
Finished Jul 22 04:48:42 PM PDT 24
Peak memory 217968 kb
Host smart-59885296-88a3-48fe-8172-1162f61b0be3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060625473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2060625473
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2671911488
Short name T395
Test name
Test status
Simulation time 540386632 ps
CPU time 11.6 seconds
Started Jul 22 04:46:25 PM PDT 24
Finished Jul 22 04:46:37 PM PDT 24
Peak memory 225728 kb
Host smart-1d94d96b-0a4b-466c-96cb-1a2bd41f8baa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671911488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2671911488
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.747706542
Short name T586
Test name
Test status
Simulation time 1004152395 ps
CPU time 9.34 seconds
Started Jul 22 04:46:25 PM PDT 24
Finished Jul 22 04:46:35 PM PDT 24
Peak memory 218112 kb
Host smart-48c4f417-e4eb-467d-a115-a4e1d21a6631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747706542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.747706542
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3340902865
Short name T406
Test name
Test status
Simulation time 43416122 ps
CPU time 2.18 seconds
Started Jul 22 04:46:25 PM PDT 24
Finished Jul 22 04:46:28 PM PDT 24
Peak memory 217416 kb
Host smart-795be3bd-410a-48ee-8fcd-27363dd3c4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340902865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3340902865
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.3015779164
Short name T849
Test name
Test status
Simulation time 610849469 ps
CPU time 21.95 seconds
Started Jul 22 04:47:40 PM PDT 24
Finished Jul 22 04:48:02 PM PDT 24
Peak memory 250676 kb
Host smart-fd93785f-0a88-4f65-86ca-3a1e8f414707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015779164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3015779164
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2998372157
Short name T295
Test name
Test status
Simulation time 57634085 ps
CPU time 2.71 seconds
Started Jul 22 04:46:26 PM PDT 24
Finished Jul 22 04:46:29 PM PDT 24
Peak memory 222240 kb
Host smart-561591af-1501-4d86-a744-bdac65122c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998372157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2998372157
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3464843709
Short name T299
Test name
Test status
Simulation time 7102327480 ps
CPU time 52.16 seconds
Started Jul 22 04:46:27 PM PDT 24
Finished Jul 22 04:47:20 PM PDT 24
Peak memory 225932 kb
Host smart-0993a6ce-3608-4a83-abfe-6e9c1c0d1843
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464843709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3464843709
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.4278951368
Short name T772
Test name
Test status
Simulation time 13660318 ps
CPU time 0.99 seconds
Started Jul 22 04:46:27 PM PDT 24
Finished Jul 22 04:46:28 PM PDT 24
Peak memory 207680 kb
Host smart-f9a55d32-3758-4b74-bf26-f2f0e526bcb5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278951368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.4278951368
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1635501569
Short name T640
Test name
Test status
Simulation time 69641658 ps
CPU time 0.95 seconds
Started Jul 22 04:46:56 PM PDT 24
Finished Jul 22 04:46:58 PM PDT 24
Peak memory 208616 kb
Host smart-4e4147ad-c4cc-4456-a4a9-605c5cdf1f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635501569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1635501569
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.383607632
Short name T529
Test name
Test status
Simulation time 4415428589 ps
CPU time 16.07 seconds
Started Jul 22 04:47:38 PM PDT 24
Finished Jul 22 04:47:54 PM PDT 24
Peak memory 218796 kb
Host smart-af438d5d-b45c-4cd4-8dc5-36ea14f41c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383607632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.383607632
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2770418991
Short name T24
Test name
Test status
Simulation time 427869489 ps
CPU time 3.04 seconds
Started Jul 22 04:46:31 PM PDT 24
Finished Jul 22 04:46:35 PM PDT 24
Peak memory 216880 kb
Host smart-c0789ffe-6faa-4736-a055-ea2033a65b26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770418991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2770418991
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3564543740
Short name T521
Test name
Test status
Simulation time 73172519 ps
CPU time 2.77 seconds
Started Jul 22 04:46:27 PM PDT 24
Finished Jul 22 04:46:31 PM PDT 24
Peak memory 218004 kb
Host smart-38a48aaa-fcb3-4eaf-94b2-5f715d0864c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564543740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3564543740
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.604112908
Short name T671
Test name
Test status
Simulation time 266699501 ps
CPU time 8.83 seconds
Started Jul 22 04:46:34 PM PDT 24
Finished Jul 22 04:46:44 PM PDT 24
Peak memory 218056 kb
Host smart-9ac9781a-f96f-40b8-a7c4-ade61a4e957b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604112908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.604112908
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3559132570
Short name T161
Test name
Test status
Simulation time 2259084455 ps
CPU time 11.25 seconds
Started Jul 22 04:46:42 PM PDT 24
Finished Jul 22 04:46:53 PM PDT 24
Peak memory 225868 kb
Host smart-6b24ad7d-eced-4015-8169-090282c8483f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559132570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
3559132570
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.775534308
Short name T296
Test name
Test status
Simulation time 700194819 ps
CPU time 7.87 seconds
Started Jul 22 04:46:27 PM PDT 24
Finished Jul 22 04:46:36 PM PDT 24
Peak memory 218136 kb
Host smart-777a405f-e793-455d-a50e-69dcdec56f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775534308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.775534308
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.4086873681
Short name T75
Test name
Test status
Simulation time 90791198 ps
CPU time 2.26 seconds
Started Jul 22 04:46:25 PM PDT 24
Finished Jul 22 04:46:28 PM PDT 24
Peak memory 214072 kb
Host smart-f4f639bf-e870-44a3-81a8-f98ef18bc69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086873681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.4086873681
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.989510901
Short name T795
Test name
Test status
Simulation time 795014376 ps
CPU time 26.26 seconds
Started Jul 22 04:47:33 PM PDT 24
Finished Jul 22 04:47:59 PM PDT 24
Peak memory 250632 kb
Host smart-84dd21be-4e9a-4fe6-8f27-0f2f7fa80a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989510901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.989510901
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.2557014479
Short name T752
Test name
Test status
Simulation time 46823216 ps
CPU time 2.72 seconds
Started Jul 22 04:46:27 PM PDT 24
Finished Jul 22 04:46:30 PM PDT 24
Peak memory 221912 kb
Host smart-47f012d5-b675-4dd5-95c4-940354d88981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557014479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2557014479
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.720055218
Short name T410
Test name
Test status
Simulation time 16384966478 ps
CPU time 506.13 seconds
Started Jul 22 04:46:39 PM PDT 24
Finished Jul 22 04:55:05 PM PDT 24
Peak memory 250744 kb
Host smart-2bb3ec36-0407-4b23-9431-e06949d39bd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720055218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.720055218
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1724689863
Short name T731
Test name
Test status
Simulation time 43385297 ps
CPU time 0.91 seconds
Started Jul 22 04:46:25 PM PDT 24
Finished Jul 22 04:46:27 PM PDT 24
Peak memory 212596 kb
Host smart-bf81800e-9cf8-4768-9a28-9f91519ce4da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724689863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1724689863
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3377301208
Short name T712
Test name
Test status
Simulation time 126863497 ps
CPU time 0.97 seconds
Started Jul 22 04:46:36 PM PDT 24
Finished Jul 22 04:46:37 PM PDT 24
Peak memory 208608 kb
Host smart-09f03fa7-8c04-47bd-9c27-f969a26d7eb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377301208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3377301208
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3674586797
Short name T759
Test name
Test status
Simulation time 858056414 ps
CPU time 18.37 seconds
Started Jul 22 04:46:38 PM PDT 24
Finished Jul 22 04:46:57 PM PDT 24
Peak memory 218076 kb
Host smart-06d307a6-b59f-45a3-a9a6-af7767312a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674586797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3674586797
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.4063356307
Short name T728
Test name
Test status
Simulation time 370446976 ps
CPU time 1.82 seconds
Started Jul 22 04:46:35 PM PDT 24
Finished Jul 22 04:46:37 PM PDT 24
Peak memory 216788 kb
Host smart-5816d246-8ea3-46de-afd5-89b7ae5af8a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063356307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.4063356307
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1334170713
Short name T468
Test name
Test status
Simulation time 811406437 ps
CPU time 2.96 seconds
Started Jul 22 04:46:35 PM PDT 24
Finished Jul 22 04:46:38 PM PDT 24
Peak memory 217988 kb
Host smart-f69bed32-1d96-4923-9eac-5a5e3bd09883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334170713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1334170713
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1966851006
Short name T599
Test name
Test status
Simulation time 1202473173 ps
CPU time 14.76 seconds
Started Jul 22 04:47:40 PM PDT 24
Finished Jul 22 04:47:55 PM PDT 24
Peak memory 218120 kb
Host smart-4cbeb096-a14c-4137-93be-26c893e636e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966851006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1966851006
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.71292262
Short name T700
Test name
Test status
Simulation time 726783416 ps
CPU time 9.75 seconds
Started Jul 22 04:48:28 PM PDT 24
Finished Jul 22 04:48:39 PM PDT 24
Peak memory 217968 kb
Host smart-d3adc3b3-73e1-4702-a13f-3403f0d0ffdf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71292262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_dig
est.71292262
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1215606312
Short name T183
Test name
Test status
Simulation time 429281168 ps
CPU time 9.11 seconds
Started Jul 22 04:46:37 PM PDT 24
Finished Jul 22 04:46:46 PM PDT 24
Peak memory 218056 kb
Host smart-bfa9d3ed-d514-40d1-94d8-0ed46a4d2686
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215606312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1215606312
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3053459174
Short name T832
Test name
Test status
Simulation time 574491755 ps
CPU time 11.65 seconds
Started Jul 22 04:48:29 PM PDT 24
Finished Jul 22 04:48:41 PM PDT 24
Peak memory 218048 kb
Host smart-bb233040-4ec5-4eca-8976-a1cf13b6ead2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053459174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3053459174
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2839761365
Short name T479
Test name
Test status
Simulation time 140135289 ps
CPU time 3.01 seconds
Started Jul 22 04:48:23 PM PDT 24
Finished Jul 22 04:48:27 PM PDT 24
Peak memory 214616 kb
Host smart-5baa268b-7759-4033-9e65-b556811cb490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839761365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2839761365
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3875612403
Short name T292
Test name
Test status
Simulation time 624926200 ps
CPU time 31.45 seconds
Started Jul 22 04:46:34 PM PDT 24
Finished Jul 22 04:47:06 PM PDT 24
Peak memory 250724 kb
Host smart-ef585ebd-aa28-4931-ac5a-32e67c3f9fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875612403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3875612403
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2064239573
Short name T188
Test name
Test status
Simulation time 283656545 ps
CPU time 6.54 seconds
Started Jul 22 04:46:36 PM PDT 24
Finished Jul 22 04:46:43 PM PDT 24
Peak memory 250040 kb
Host smart-780e4bb8-9de3-49a6-8d96-eb6c4a7c96e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064239573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2064239573
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2719465282
Short name T736
Test name
Test status
Simulation time 2468492104 ps
CPU time 79.83 seconds
Started Jul 22 04:46:34 PM PDT 24
Finished Jul 22 04:47:55 PM PDT 24
Peak memory 225820 kb
Host smart-1330ed94-c397-48af-a4e9-7a089ee11465
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719465282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2719465282
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1083644920
Short name T472
Test name
Test status
Simulation time 70385470 ps
CPU time 0.79 seconds
Started Jul 22 04:46:35 PM PDT 24
Finished Jul 22 04:46:36 PM PDT 24
Peak memory 208580 kb
Host smart-64aea262-0eb4-481c-985c-357dced47b18
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083644920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1083644920
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.749549450
Short name T835
Test name
Test status
Simulation time 102853031 ps
CPU time 0.87 seconds
Started Jul 22 04:46:45 PM PDT 24
Finished Jul 22 04:46:47 PM PDT 24
Peak memory 208580 kb
Host smart-d7f793ae-c64c-4bbc-8135-a64bac04aa37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749549450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.749549450
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2437867167
Short name T261
Test name
Test status
Simulation time 1025902672 ps
CPU time 10.67 seconds
Started Jul 22 04:46:35 PM PDT 24
Finished Jul 22 04:46:46 PM PDT 24
Peak memory 218040 kb
Host smart-a4a03a60-61cb-4f0e-b37b-0a01e3e8a8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437867167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2437867167
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2320410174
Short name T441
Test name
Test status
Simulation time 103076540 ps
CPU time 2.01 seconds
Started Jul 22 04:47:52 PM PDT 24
Finished Jul 22 04:47:55 PM PDT 24
Peak memory 216804 kb
Host smart-be764b2c-38d8-4ead-aa53-dee721201211
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320410174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2320410174
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3943345159
Short name T231
Test name
Test status
Simulation time 40224738 ps
CPU time 1.56 seconds
Started Jul 22 04:48:23 PM PDT 24
Finished Jul 22 04:48:25 PM PDT 24
Peak memory 218000 kb
Host smart-6cec5b9a-d91e-4804-a480-8e4e07d746bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943345159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3943345159
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.3171514863
Short name T173
Test name
Test status
Simulation time 298804919 ps
CPU time 13.79 seconds
Started Jul 22 04:46:42 PM PDT 24
Finished Jul 22 04:46:57 PM PDT 24
Peak memory 218572 kb
Host smart-798d7242-861f-4819-8204-80aa0deef765
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171514863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3171514863
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1984791617
Short name T750
Test name
Test status
Simulation time 290176423 ps
CPU time 8.22 seconds
Started Jul 22 04:46:43 PM PDT 24
Finished Jul 22 04:46:52 PM PDT 24
Peak memory 218020 kb
Host smart-eec7ac6b-1756-4899-945e-fe7d29e44689
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984791617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1984791617
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.71784436
Short name T592
Test name
Test status
Simulation time 1424608129 ps
CPU time 11.97 seconds
Started Jul 22 04:46:44 PM PDT 24
Finished Jul 22 04:46:57 PM PDT 24
Peak memory 225720 kb
Host smart-43b07363-fdc3-4b42-9ff5-966ca62574cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71784436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.71784436
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.3212338940
Short name T30
Test name
Test status
Simulation time 75947212 ps
CPU time 2.95 seconds
Started Jul 22 04:46:36 PM PDT 24
Finished Jul 22 04:46:39 PM PDT 24
Peak memory 217392 kb
Host smart-f0424ae3-c1b1-43b3-975a-94e631da0a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212338940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3212338940
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3952726070
Short name T665
Test name
Test status
Simulation time 1056294111 ps
CPU time 24.6 seconds
Started Jul 22 04:46:36 PM PDT 24
Finished Jul 22 04:47:01 PM PDT 24
Peak memory 250644 kb
Host smart-84d34016-531d-4814-9a89-9b3ae8288fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952726070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3952726070
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.956503498
Short name T506
Test name
Test status
Simulation time 55602308 ps
CPU time 6.65 seconds
Started Jul 22 04:46:35 PM PDT 24
Finished Jul 22 04:46:42 PM PDT 24
Peak memory 250240 kb
Host smart-45bda263-d1c9-48df-a40a-f2884942993b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956503498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.956503498
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.573727983
Short name T262
Test name
Test status
Simulation time 709127445 ps
CPU time 33.44 seconds
Started Jul 22 04:46:46 PM PDT 24
Finished Jul 22 04:47:20 PM PDT 24
Peak memory 225784 kb
Host smart-c96e9523-42cf-493e-ae27-74089fbd5a09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573727983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.573727983
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.2721903829
Short name T146
Test name
Test status
Simulation time 18587753247 ps
CPU time 87.93 seconds
Started Jul 22 04:46:44 PM PDT 24
Finished Jul 22 04:48:12 PM PDT 24
Peak memory 250856 kb
Host smart-66875eec-8d99-4d1f-a623-2da949645793
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2721903829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.2721903829
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.100362018
Short name T688
Test name
Test status
Simulation time 17698893 ps
CPU time 1.01 seconds
Started Jul 22 04:46:37 PM PDT 24
Finished Jul 22 04:46:39 PM PDT 24
Peak memory 217408 kb
Host smart-0efb1690-9f1e-4ced-8097-f72114b7b131
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100362018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.100362018
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1247379741
Short name T682
Test name
Test status
Simulation time 34416232 ps
CPU time 0.91 seconds
Started Jul 22 04:46:46 PM PDT 24
Finished Jul 22 04:46:47 PM PDT 24
Peak memory 208576 kb
Host smart-c76722c5-f26c-483a-8c27-3c9bc62d2217
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247379741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1247379741
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2122959459
Short name T399
Test name
Test status
Simulation time 757010587 ps
CPU time 16.98 seconds
Started Jul 22 04:46:45 PM PDT 24
Finished Jul 22 04:47:02 PM PDT 24
Peak memory 218076 kb
Host smart-319e75d4-d1f9-472b-9390-3ea3ad868198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122959459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2122959459
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.569081520
Short name T542
Test name
Test status
Simulation time 7794583910 ps
CPU time 5.78 seconds
Started Jul 22 04:47:19 PM PDT 24
Finished Jul 22 04:47:25 PM PDT 24
Peak memory 217408 kb
Host smart-18820f81-56da-4362-acb1-35dbdc0baba4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569081520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.569081520
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1255205689
Short name T802
Test name
Test status
Simulation time 156254029 ps
CPU time 3.11 seconds
Started Jul 22 04:46:44 PM PDT 24
Finished Jul 22 04:46:48 PM PDT 24
Peak memory 218156 kb
Host smart-fde9096f-caf4-40c0-a40a-7eae2d370083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255205689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1255205689
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.583196702
Short name T553
Test name
Test status
Simulation time 1098894043 ps
CPU time 13.71 seconds
Started Jul 22 04:46:43 PM PDT 24
Finished Jul 22 04:46:58 PM PDT 24
Peak memory 225748 kb
Host smart-e1598b72-6134-4c51-877c-395528dbb34a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583196702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.583196702
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3859619313
Short name T848
Test name
Test status
Simulation time 843472875 ps
CPU time 9.88 seconds
Started Jul 22 04:47:39 PM PDT 24
Finished Jul 22 04:47:50 PM PDT 24
Peak memory 218068 kb
Host smart-1ed26cf9-f902-48c2-823c-b01390c67750
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859619313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3859619313
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1312415100
Short name T346
Test name
Test status
Simulation time 255805226 ps
CPU time 6.74 seconds
Started Jul 22 04:47:36 PM PDT 24
Finished Jul 22 04:47:43 PM PDT 24
Peak memory 225828 kb
Host smart-bdb12ca8-89a6-4180-a85a-0bc00e8bcec7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312415100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1312415100
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.4043587674
Short name T605
Test name
Test status
Simulation time 423812441 ps
CPU time 5.83 seconds
Started Jul 22 04:46:43 PM PDT 24
Finished Jul 22 04:46:50 PM PDT 24
Peak memory 218052 kb
Host smart-243752da-6d2a-4c3b-8f8b-c87377010eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043587674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.4043587674
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.1125331960
Short name T374
Test name
Test status
Simulation time 339699731 ps
CPU time 3.04 seconds
Started Jul 22 04:47:38 PM PDT 24
Finished Jul 22 04:47:42 PM PDT 24
Peak memory 217488 kb
Host smart-b9f624df-2cc0-498c-b933-a7d2174aa16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125331960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1125331960
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1828363449
Short name T237
Test name
Test status
Simulation time 1165632586 ps
CPU time 27.4 seconds
Started Jul 22 04:46:43 PM PDT 24
Finished Jul 22 04:47:12 PM PDT 24
Peak memory 250648 kb
Host smart-93696424-2a05-48ab-a604-34a3810124e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828363449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1828363449
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2726037703
Short name T460
Test name
Test status
Simulation time 62616098 ps
CPU time 3.21 seconds
Started Jul 22 04:46:47 PM PDT 24
Finished Jul 22 04:46:51 PM PDT 24
Peak memory 222392 kb
Host smart-07d1b2c2-8ad1-4620-88f6-7fbfb75f40fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726037703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2726037703
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.705509253
Short name T741
Test name
Test status
Simulation time 1243281629 ps
CPU time 18.73 seconds
Started Jul 22 04:47:37 PM PDT 24
Finished Jul 22 04:47:56 PM PDT 24
Peak memory 250352 kb
Host smart-9d5e53b5-dc46-4552-8183-f7acd989783d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705509253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.705509253
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3991644965
Short name T523
Test name
Test status
Simulation time 39384583 ps
CPU time 0.87 seconds
Started Jul 22 04:46:47 PM PDT 24
Finished Jul 22 04:46:48 PM PDT 24
Peak memory 208616 kb
Host smart-54742e71-ff87-4453-a032-7fc4ec5742d3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991644965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3991644965
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.67187181
Short name T805
Test name
Test status
Simulation time 53646770 ps
CPU time 0.91 seconds
Started Jul 22 04:46:54 PM PDT 24
Finished Jul 22 04:46:56 PM PDT 24
Peak memory 208612 kb
Host smart-a3bbce0b-fc82-4a2f-9490-272be52b2428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67187181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.67187181
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1593162477
Short name T773
Test name
Test status
Simulation time 1255017300 ps
CPU time 14.8 seconds
Started Jul 22 04:46:53 PM PDT 24
Finished Jul 22 04:47:08 PM PDT 24
Peak memory 218000 kb
Host smart-893e3c86-c4cc-4e02-9504-8b9818dc4a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593162477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1593162477
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1241779938
Short name T785
Test name
Test status
Simulation time 539894290 ps
CPU time 8.52 seconds
Started Jul 22 04:46:51 PM PDT 24
Finished Jul 22 04:47:00 PM PDT 24
Peak memory 217080 kb
Host smart-b8749bce-ff00-41b4-9ae0-6597e1af1bf3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241779938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1241779938
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1941134968
Short name T663
Test name
Test status
Simulation time 270711349 ps
CPU time 3.18 seconds
Started Jul 22 04:46:51 PM PDT 24
Finished Jul 22 04:46:54 PM PDT 24
Peak memory 222216 kb
Host smart-82bff048-0a02-464e-9326-d8d19d630d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941134968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1941134968
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3222317380
Short name T186
Test name
Test status
Simulation time 880344858 ps
CPU time 11.05 seconds
Started Jul 22 04:46:53 PM PDT 24
Finished Jul 22 04:47:05 PM PDT 24
Peak memory 218120 kb
Host smart-eee40100-e69c-484d-b965-558a94e86624
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222317380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3222317380
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3005705151
Short name T168
Test name
Test status
Simulation time 300076138 ps
CPU time 8.24 seconds
Started Jul 22 04:46:52 PM PDT 24
Finished Jul 22 04:47:01 PM PDT 24
Peak memory 218024 kb
Host smart-24695a04-450f-459b-bd4d-1679a6bbd8c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005705151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3005705151
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2697828654
Short name T355
Test name
Test status
Simulation time 233610717 ps
CPU time 9.69 seconds
Started Jul 22 04:46:54 PM PDT 24
Finished Jul 22 04:47:05 PM PDT 24
Peak memory 225724 kb
Host smart-386b21a4-d351-498e-b8e3-8fdb072501c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697828654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2697828654
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1222381961
Short name T628
Test name
Test status
Simulation time 117848703 ps
CPU time 2.02 seconds
Started Jul 22 04:48:23 PM PDT 24
Finished Jul 22 04:48:26 PM PDT 24
Peak memory 222140 kb
Host smart-85e281cd-d0a2-49ed-b116-f036fd058ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222381961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1222381961
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1968928504
Short name T543
Test name
Test status
Simulation time 206542956 ps
CPU time 19.39 seconds
Started Jul 22 04:46:44 PM PDT 24
Finished Jul 22 04:47:04 PM PDT 24
Peak memory 250756 kb
Host smart-8b34d97b-f4a6-4562-b505-03a5b52a8a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968928504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1968928504
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3753185657
Short name T470
Test name
Test status
Simulation time 294909355 ps
CPU time 3.14 seconds
Started Jul 22 04:46:43 PM PDT 24
Finished Jul 22 04:46:47 PM PDT 24
Peak memory 217904 kb
Host smart-098d21cd-9756-4b2f-b742-2875694788bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753185657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3753185657
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3929327011
Short name T757
Test name
Test status
Simulation time 2763907958 ps
CPU time 93.32 seconds
Started Jul 22 04:46:54 PM PDT 24
Finished Jul 22 04:48:28 PM PDT 24
Peak memory 279080 kb
Host smart-14d73f3b-b353-4405-9a83-e68ad0ed8cb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929327011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3929327011
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.998675562
Short name T719
Test name
Test status
Simulation time 10339063481 ps
CPU time 286.97 seconds
Started Jul 22 04:46:52 PM PDT 24
Finished Jul 22 04:51:40 PM PDT 24
Peak memory 421988 kb
Host smart-1f0790b9-b4f5-4991-aedf-737fd1734688
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=998675562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.998675562
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1995427224
Short name T447
Test name
Test status
Simulation time 38848739 ps
CPU time 0.92 seconds
Started Jul 22 04:47:38 PM PDT 24
Finished Jul 22 04:47:39 PM PDT 24
Peak memory 208912 kb
Host smart-386e46ec-7713-4f4d-b761-bda32d4dd2d7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995427224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1995427224
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.555253925
Short name T412
Test name
Test status
Simulation time 47515196 ps
CPU time 0.83 seconds
Started Jul 22 04:43:45 PM PDT 24
Finished Jul 22 04:43:47 PM PDT 24
Peak memory 208468 kb
Host smart-26705e66-1afd-42d3-8cc7-6beaa8313f68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555253925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.555253925
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2579762764
Short name T14
Test name
Test status
Simulation time 15753918 ps
CPU time 0.91 seconds
Started Jul 22 04:43:35 PM PDT 24
Finished Jul 22 04:43:36 PM PDT 24
Peak memory 208544 kb
Host smart-8fefec86-86c0-4341-93a5-0bcd804197f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579762764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2579762764
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.268006224
Short name T579
Test name
Test status
Simulation time 902372074 ps
CPU time 11.44 seconds
Started Jul 22 04:43:37 PM PDT 24
Finished Jul 22 04:43:49 PM PDT 24
Peak memory 218144 kb
Host smart-412843ae-59ec-4716-adae-5ed3216deb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268006224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.268006224
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.2128469550
Short name T811
Test name
Test status
Simulation time 32128088 ps
CPU time 1.26 seconds
Started Jul 22 04:43:45 PM PDT 24
Finished Jul 22 04:43:47 PM PDT 24
Peak memory 216696 kb
Host smart-34074ec9-174f-4d61-9dec-9c9d70518269
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128469550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.2128469550
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1218821916
Short name T678
Test name
Test status
Simulation time 7152312939 ps
CPU time 56.6 seconds
Started Jul 22 04:43:49 PM PDT 24
Finished Jul 22 04:44:46 PM PDT 24
Peak memory 225904 kb
Host smart-62c1fd72-2be2-43bf-8d49-1198e93d5812
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218821916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1218821916
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3884815508
Short name T388
Test name
Test status
Simulation time 493671072 ps
CPU time 2.32 seconds
Started Jul 22 04:43:43 PM PDT 24
Finished Jul 22 04:43:46 PM PDT 24
Peak memory 217448 kb
Host smart-255b4e50-ad4b-4cfa-bfcf-c92496d7314b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884815508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.3
884815508
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1326549861
Short name T509
Test name
Test status
Simulation time 963707176 ps
CPU time 3.98 seconds
Started Jul 22 04:43:35 PM PDT 24
Finished Jul 22 04:43:39 PM PDT 24
Peak memory 222648 kb
Host smart-9e3b752a-2b48-4961-9ec3-ae2207de6ebf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326549861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1326549861
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3334077378
Short name T644
Test name
Test status
Simulation time 2046828217 ps
CPU time 35.39 seconds
Started Jul 22 04:43:45 PM PDT 24
Finished Jul 22 04:44:21 PM PDT 24
Peak memory 217332 kb
Host smart-d0c1ab06-48eb-4f69-a361-43bbc817fa25
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334077378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3334077378
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3031092454
Short name T621
Test name
Test status
Simulation time 586187057 ps
CPU time 4.91 seconds
Started Jul 22 04:44:24 PM PDT 24
Finished Jul 22 04:44:30 PM PDT 24
Peak memory 217256 kb
Host smart-6330852d-b754-48ff-98b3-9135adf44083
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031092454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3031092454
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.599919050
Short name T310
Test name
Test status
Simulation time 5700850257 ps
CPU time 92.96 seconds
Started Jul 22 04:44:24 PM PDT 24
Finished Jul 22 04:45:58 PM PDT 24
Peak memory 282312 kb
Host smart-e1aaf07d-09b8-4200-8bc5-17620d0fe47f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599919050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_state_failure.599919050
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1254598335
Short name T649
Test name
Test status
Simulation time 2269629730 ps
CPU time 21.18 seconds
Started Jul 22 04:43:43 PM PDT 24
Finished Jul 22 04:44:05 PM PDT 24
Peak memory 250648 kb
Host smart-73bf8377-5175-4769-9587-7786b08b04aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254598335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1254598335
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3303854154
Short name T787
Test name
Test status
Simulation time 87695308 ps
CPU time 4.21 seconds
Started Jul 22 04:43:34 PM PDT 24
Finished Jul 22 04:43:39 PM PDT 24
Peak memory 222568 kb
Host smart-29174ce7-2ef7-4590-9058-7c734767a188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303854154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3303854154
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2018997294
Short name T547
Test name
Test status
Simulation time 1703494852 ps
CPU time 11.28 seconds
Started Jul 22 04:44:24 PM PDT 24
Finished Jul 22 04:44:36 PM PDT 24
Peak memory 217384 kb
Host smart-0b58de03-cbd8-4a8f-b69f-8bbe05a13250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018997294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2018997294
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1022441220
Short name T61
Test name
Test status
Simulation time 833367161 ps
CPU time 35.99 seconds
Started Jul 22 04:43:44 PM PDT 24
Finished Jul 22 04:44:21 PM PDT 24
Peak memory 281600 kb
Host smart-0f895106-28b7-48d1-b056-2fe5466a2b6e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022441220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1022441220
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2697545651
Short name T403
Test name
Test status
Simulation time 718021265 ps
CPU time 24.2 seconds
Started Jul 22 04:43:44 PM PDT 24
Finished Jul 22 04:44:08 PM PDT 24
Peak memory 225716 kb
Host smart-a1d9c3b2-29ef-4b0e-93b9-16971f63731e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697545651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2697545651
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3875024380
Short name T783
Test name
Test status
Simulation time 422480808 ps
CPU time 13.2 seconds
Started Jul 22 04:43:43 PM PDT 24
Finished Jul 22 04:43:57 PM PDT 24
Peak memory 225680 kb
Host smart-6997a70a-e94b-4264-b36e-2d8f5b8f999c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875024380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
875024380
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.473078145
Short name T578
Test name
Test status
Simulation time 1388174705 ps
CPU time 14.23 seconds
Started Jul 22 04:43:36 PM PDT 24
Finished Jul 22 04:43:51 PM PDT 24
Peak memory 225780 kb
Host smart-82aaeb07-5b40-4f93-9782-1bfbe850aad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473078145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.473078145
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.330212245
Short name T457
Test name
Test status
Simulation time 131176652 ps
CPU time 2.8 seconds
Started Jul 22 04:43:36 PM PDT 24
Finished Jul 22 04:43:39 PM PDT 24
Peak memory 222680 kb
Host smart-d753060c-0442-4e3d-ba0d-fc212a4d1cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330212245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.330212245
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1145061111
Short name T737
Test name
Test status
Simulation time 728830456 ps
CPU time 24.73 seconds
Started Jul 22 04:43:36 PM PDT 24
Finished Jul 22 04:44:02 PM PDT 24
Peak memory 250804 kb
Host smart-95c2c0f2-4c20-416a-897a-a01d4daea09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145061111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1145061111
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2712173108
Short name T446
Test name
Test status
Simulation time 71241065 ps
CPU time 10.61 seconds
Started Jul 22 04:43:35 PM PDT 24
Finished Jul 22 04:43:46 PM PDT 24
Peak memory 250684 kb
Host smart-061e1394-4d51-471b-9a5d-a74c596de49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712173108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2712173108
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.4143005614
Short name T308
Test name
Test status
Simulation time 19984920225 ps
CPU time 326.28 seconds
Started Jul 22 04:43:45 PM PDT 24
Finished Jul 22 04:49:12 PM PDT 24
Peak memory 250736 kb
Host smart-2a4f54f7-b1b8-4753-8a0c-6cc27d02002e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143005614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.4143005614
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.645241291
Short name T821
Test name
Test status
Simulation time 22748292 ps
CPU time 0.89 seconds
Started Jul 22 04:43:35 PM PDT 24
Finished Jul 22 04:43:36 PM PDT 24
Peak memory 211532 kb
Host smart-9f9914e7-2278-4cd7-81fa-6e45469dc27f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645241291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.645241291
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.4140397032
Short name T246
Test name
Test status
Simulation time 18543388 ps
CPU time 1.13 seconds
Started Jul 22 04:47:03 PM PDT 24
Finished Jul 22 04:47:04 PM PDT 24
Peak memory 208644 kb
Host smart-b51f5db6-3fde-40f4-90ad-ef68c4db42db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140397032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.4140397032
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.480679881
Short name T97
Test name
Test status
Simulation time 975693689 ps
CPU time 8.63 seconds
Started Jul 22 04:46:54 PM PDT 24
Finished Jul 22 04:47:03 PM PDT 24
Peak memory 218004 kb
Host smart-a5eec678-9de0-4676-aa11-cd0273c3f0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480679881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.480679881
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2093061151
Short name T379
Test name
Test status
Simulation time 474783433 ps
CPU time 7.04 seconds
Started Jul 22 04:46:53 PM PDT 24
Finished Jul 22 04:47:01 PM PDT 24
Peak memory 216864 kb
Host smart-dffabdd3-633d-4dbc-addf-fa69b62991e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093061151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2093061151
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1201309740
Short name T369
Test name
Test status
Simulation time 249026863 ps
CPU time 2.42 seconds
Started Jul 22 04:46:51 PM PDT 24
Finished Jul 22 04:46:54 PM PDT 24
Peak memory 221920 kb
Host smart-f9fb8f4c-e822-4f19-bee1-531801b091d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201309740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1201309740
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1861369441
Short name T248
Test name
Test status
Simulation time 1528760418 ps
CPU time 12.91 seconds
Started Jul 22 04:46:53 PM PDT 24
Finished Jul 22 04:47:06 PM PDT 24
Peak memory 219748 kb
Host smart-30fa8613-16aa-4210-85a8-e5985a877c43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861369441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1861369441
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.664450389
Short name T1
Test name
Test status
Simulation time 2375739877 ps
CPU time 15.61 seconds
Started Jul 22 04:46:50 PM PDT 24
Finished Jul 22 04:47:06 PM PDT 24
Peak memory 218188 kb
Host smart-c97cde20-f6c9-4a4c-9d7b-40d415aa1024
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664450389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_di
gest.664450389
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1819136186
Short name T255
Test name
Test status
Simulation time 6014764164 ps
CPU time 11.36 seconds
Started Jul 22 04:46:52 PM PDT 24
Finished Jul 22 04:47:04 PM PDT 24
Peak memory 225872 kb
Host smart-889564a4-eb98-4ee7-8657-39ae03e9eee8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819136186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1819136186
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2632631689
Short name T37
Test name
Test status
Simulation time 751269380 ps
CPU time 8.87 seconds
Started Jul 22 04:46:55 PM PDT 24
Finished Jul 22 04:47:05 PM PDT 24
Peak memory 225784 kb
Host smart-889bc277-f9c1-4d44-9504-718ef4f78900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632631689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2632631689
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3430200158
Short name T825
Test name
Test status
Simulation time 1081425949 ps
CPU time 3.52 seconds
Started Jul 22 04:46:55 PM PDT 24
Finished Jul 22 04:46:59 PM PDT 24
Peak memory 217396 kb
Host smart-d8df9fa3-7a2a-4566-b732-02d1d1493bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430200158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3430200158
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3756089383
Short name T715
Test name
Test status
Simulation time 838280836 ps
CPU time 24.11 seconds
Started Jul 22 04:46:53 PM PDT 24
Finished Jul 22 04:47:18 PM PDT 24
Peak memory 250688 kb
Host smart-08c30a2e-8b3b-4e78-94e7-c603a3f85ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756089383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3756089383
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2113730840
Short name T448
Test name
Test status
Simulation time 89259296 ps
CPU time 7.01 seconds
Started Jul 22 04:46:53 PM PDT 24
Finished Jul 22 04:47:01 PM PDT 24
Peak memory 250056 kb
Host smart-a005a942-ac4c-4474-93f3-96a7ae53908e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113730840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2113730840
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3125477583
Short name T714
Test name
Test status
Simulation time 39241763572 ps
CPU time 183.51 seconds
Started Jul 22 04:46:54 PM PDT 24
Finished Jul 22 04:49:59 PM PDT 24
Peak memory 250748 kb
Host smart-419c5182-8d71-4637-90af-b660045a83a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125477583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3125477583
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.283431651
Short name T440
Test name
Test status
Simulation time 48039310 ps
CPU time 0.85 seconds
Started Jul 22 04:46:52 PM PDT 24
Finished Jul 22 04:46:53 PM PDT 24
Peak memory 208556 kb
Host smart-f5dba4c5-4ff2-4280-bab6-28d9f33dcc69
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283431651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.283431651
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2017054899
Short name T250
Test name
Test status
Simulation time 17804838 ps
CPU time 1.11 seconds
Started Jul 22 04:47:04 PM PDT 24
Finished Jul 22 04:47:06 PM PDT 24
Peak memory 208636 kb
Host smart-ffcbedb3-048d-4116-a07d-07d5c307e3e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017054899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2017054899
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3180292265
Short name T232
Test name
Test status
Simulation time 540837435 ps
CPU time 9.27 seconds
Started Jul 22 04:47:03 PM PDT 24
Finished Jul 22 04:47:13 PM PDT 24
Peak memory 218044 kb
Host smart-8f193143-d94e-47a6-854a-d78487d3b863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180292265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3180292265
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3914820107
Short name T23
Test name
Test status
Simulation time 1002086303 ps
CPU time 6.68 seconds
Started Jul 22 04:47:00 PM PDT 24
Finished Jul 22 04:47:07 PM PDT 24
Peak memory 217228 kb
Host smart-a55ec8cb-f936-4843-9aaa-9e4403445de0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914820107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3914820107
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1260719342
Short name T144
Test name
Test status
Simulation time 37650878 ps
CPU time 2.02 seconds
Started Jul 22 04:47:03 PM PDT 24
Finished Jul 22 04:47:06 PM PDT 24
Peak memory 221988 kb
Host smart-38d6efdc-66fe-4053-9996-91fbf27151cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260719342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1260719342
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.821913051
Short name T544
Test name
Test status
Simulation time 1656362591 ps
CPU time 15.83 seconds
Started Jul 22 04:47:03 PM PDT 24
Finished Jul 22 04:47:20 PM PDT 24
Peak memory 218056 kb
Host smart-81994e46-2224-4ddf-820f-330d97d1268d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821913051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.821913051
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1059660636
Short name T34
Test name
Test status
Simulation time 585511447 ps
CPU time 10.32 seconds
Started Jul 22 04:47:02 PM PDT 24
Finished Jul 22 04:47:13 PM PDT 24
Peak memory 225664 kb
Host smart-b75a8789-af43-4436-8d9a-6abee2128dee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059660636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1059660636
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.1194537904
Short name T601
Test name
Test status
Simulation time 217104288 ps
CPU time 6.43 seconds
Started Jul 22 04:47:03 PM PDT 24
Finished Jul 22 04:47:10 PM PDT 24
Peak memory 224736 kb
Host smart-c0871de8-b616-4d12-9f17-362a43976291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194537904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1194537904
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.4077721032
Short name T42
Test name
Test status
Simulation time 59057717 ps
CPU time 3.26 seconds
Started Jul 22 04:47:01 PM PDT 24
Finished Jul 22 04:47:05 PM PDT 24
Peak memory 217416 kb
Host smart-cf47a3dc-5d8c-49aa-8ff5-46fb1ea2577b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077721032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.4077721032
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1842065329
Short name T635
Test name
Test status
Simulation time 216174078 ps
CPU time 27.25 seconds
Started Jul 22 04:47:01 PM PDT 24
Finished Jul 22 04:47:29 PM PDT 24
Peak memory 250748 kb
Host smart-ffcb12f0-9004-40a1-8c7e-5f43fb7926fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842065329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1842065329
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.375799044
Short name T393
Test name
Test status
Simulation time 326040905 ps
CPU time 3.53 seconds
Started Jul 22 04:47:00 PM PDT 24
Finished Jul 22 04:47:04 PM PDT 24
Peak memory 222312 kb
Host smart-c146370f-b265-49c1-84c3-f3312c2b829d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375799044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.375799044
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2754502197
Short name T859
Test name
Test status
Simulation time 7723030061 ps
CPU time 159.17 seconds
Started Jul 22 04:47:01 PM PDT 24
Finished Jul 22 04:49:42 PM PDT 24
Peak memory 274048 kb
Host smart-928b01ef-e15b-4102-9d81-42e47faa5751
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754502197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2754502197
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.485939040
Short name T138
Test name
Test status
Simulation time 26785956472 ps
CPU time 1068.37 seconds
Started Jul 22 04:47:04 PM PDT 24
Finished Jul 22 05:04:53 PM PDT 24
Peak memory 496672 kb
Host smart-77bac46c-be1b-43d1-94c6-940924db6eb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=485939040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.485939040
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.4125395928
Short name T80
Test name
Test status
Simulation time 19078103 ps
CPU time 1.32 seconds
Started Jul 22 04:47:02 PM PDT 24
Finished Jul 22 04:47:04 PM PDT 24
Peak memory 217580 kb
Host smart-50252224-e466-4b13-acd8-47429a9948f2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125395928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.4125395928
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2888191528
Short name T85
Test name
Test status
Simulation time 46942495 ps
CPU time 0.98 seconds
Started Jul 22 04:47:02 PM PDT 24
Finished Jul 22 04:47:03 PM PDT 24
Peak memory 208568 kb
Host smart-b6ed8f35-1a5a-4721-95e6-0d8d424e5fa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888191528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2888191528
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2979998465
Short name T36
Test name
Test status
Simulation time 273225312 ps
CPU time 11.93 seconds
Started Jul 22 04:47:18 PM PDT 24
Finished Jul 22 04:47:30 PM PDT 24
Peak memory 218020 kb
Host smart-b6ec8ce6-eb30-4a41-b90a-74b16eddd371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979998465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2979998465
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3838328091
Short name T661
Test name
Test status
Simulation time 6043592333 ps
CPU time 5.95 seconds
Started Jul 22 04:47:01 PM PDT 24
Finished Jul 22 04:47:08 PM PDT 24
Peak memory 217412 kb
Host smart-e22fe94b-8724-4ffc-9aa0-aaa645502a65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838328091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3838328091
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1342884303
Short name T423
Test name
Test status
Simulation time 66883987 ps
CPU time 3.91 seconds
Started Jul 22 04:47:01 PM PDT 24
Finished Jul 22 04:47:06 PM PDT 24
Peak memory 218320 kb
Host smart-900c2321-afea-422a-a89c-11a96d68613f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342884303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1342884303
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.2819152750
Short name T178
Test name
Test status
Simulation time 592725739 ps
CPU time 15.85 seconds
Started Jul 22 04:47:41 PM PDT 24
Finished Jul 22 04:47:58 PM PDT 24
Peak memory 225664 kb
Host smart-1ea777b9-9a6f-49cf-abcb-cfd983e10179
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819152750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2819152750
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2040151573
Short name T334
Test name
Test status
Simulation time 298731337 ps
CPU time 13.37 seconds
Started Jul 22 04:47:01 PM PDT 24
Finished Jul 22 04:47:15 PM PDT 24
Peak memory 218000 kb
Host smart-cc4c0dac-8361-4032-be32-7ba497830a0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040151573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2040151573
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.330153919
Short name T564
Test name
Test status
Simulation time 568221912 ps
CPU time 12.08 seconds
Started Jul 22 04:47:03 PM PDT 24
Finished Jul 22 04:47:16 PM PDT 24
Peak memory 225716 kb
Host smart-4998bfdf-8ac3-49a7-90a9-840904913820
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330153919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.330153919
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1512954562
Short name T400
Test name
Test status
Simulation time 1213331551 ps
CPU time 7.71 seconds
Started Jul 22 04:47:00 PM PDT 24
Finished Jul 22 04:47:08 PM PDT 24
Peak memory 218044 kb
Host smart-089d7259-7a8e-4b30-b641-759ca4d0bcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512954562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1512954562
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.140162747
Short name T380
Test name
Test status
Simulation time 51968658 ps
CPU time 1.15 seconds
Started Jul 22 04:47:01 PM PDT 24
Finished Jul 22 04:47:03 PM PDT 24
Peak memory 213516 kb
Host smart-b2c18dcd-9f46-4410-9f04-25564cb0f7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140162747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.140162747
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3560845572
Short name T473
Test name
Test status
Simulation time 383633178 ps
CPU time 17.71 seconds
Started Jul 22 04:47:03 PM PDT 24
Finished Jul 22 04:47:21 PM PDT 24
Peak memory 250688 kb
Host smart-a9da071b-d74d-42f5-9554-6cb90e50cb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560845572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3560845572
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.263430975
Short name T691
Test name
Test status
Simulation time 396404474 ps
CPU time 4.79 seconds
Started Jul 22 04:47:03 PM PDT 24
Finished Jul 22 04:47:08 PM PDT 24
Peak memory 222540 kb
Host smart-9f9bd835-42ca-4e90-bd10-20e2d1192f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263430975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.263430975
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.4222962273
Short name T439
Test name
Test status
Simulation time 8309211097 ps
CPU time 179.48 seconds
Started Jul 22 04:47:02 PM PDT 24
Finished Jul 22 04:50:02 PM PDT 24
Peak memory 280452 kb
Host smart-18ff66ed-2b4e-4453-bdf1-ea583528a3aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222962273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.4222962273
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3745539856
Short name T11
Test name
Test status
Simulation time 14334546 ps
CPU time 0.91 seconds
Started Jul 22 04:47:03 PM PDT 24
Finished Jul 22 04:47:04 PM PDT 24
Peak memory 211576 kb
Host smart-a865dc83-bb7e-4e1b-94fd-a84f14fee27e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745539856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.3745539856
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3180361716
Short name T73
Test name
Test status
Simulation time 26870654 ps
CPU time 1.04 seconds
Started Jul 22 04:47:13 PM PDT 24
Finished Jul 22 04:47:15 PM PDT 24
Peak memory 208668 kb
Host smart-68788f08-9310-4181-93fc-f71c269076f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180361716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3180361716
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3171971210
Short name T630
Test name
Test status
Simulation time 1182626169 ps
CPU time 10.21 seconds
Started Jul 22 04:47:13 PM PDT 24
Finished Jul 22 04:47:24 PM PDT 24
Peak memory 217932 kb
Host smart-6c1544a0-22b2-4191-9b38-639a76fc4d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171971210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3171971210
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.4261008948
Short name T9
Test name
Test status
Simulation time 133310146 ps
CPU time 2.48 seconds
Started Jul 22 04:47:52 PM PDT 24
Finished Jul 22 04:47:56 PM PDT 24
Peak memory 216776 kb
Host smart-477d3730-ece5-46f9-ae65-c25159d54414
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261008948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.4261008948
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.387268469
Short name T326
Test name
Test status
Simulation time 127635858 ps
CPU time 2.85 seconds
Started Jul 22 04:47:12 PM PDT 24
Finished Jul 22 04:47:16 PM PDT 24
Peak memory 222316 kb
Host smart-e78d4d9c-809a-458d-a74c-beb10072fd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387268469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.387268469
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.1623916966
Short name T316
Test name
Test status
Simulation time 835073520 ps
CPU time 19.39 seconds
Started Jul 22 04:47:12 PM PDT 24
Finished Jul 22 04:47:32 PM PDT 24
Peak memory 225792 kb
Host smart-5b52429a-524a-4327-85b1-044cbdb64dc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623916966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1623916966
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1478020846
Short name T668
Test name
Test status
Simulation time 206466221 ps
CPU time 8.48 seconds
Started Jul 22 04:47:14 PM PDT 24
Finished Jul 22 04:47:23 PM PDT 24
Peak memory 218036 kb
Host smart-5319fbcc-d544-46f4-b597-2571a974ced8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478020846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1478020846
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.274033563
Short name T273
Test name
Test status
Simulation time 1432605849 ps
CPU time 13.29 seconds
Started Jul 22 04:47:12 PM PDT 24
Finished Jul 22 04:47:27 PM PDT 24
Peak memory 225652 kb
Host smart-8558ac44-fbb3-4b52-bad6-fb586b1fba2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274033563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.274033563
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2029295085
Short name T704
Test name
Test status
Simulation time 744767528 ps
CPU time 6.21 seconds
Started Jul 22 04:47:13 PM PDT 24
Finished Jul 22 04:47:21 PM PDT 24
Peak memory 218060 kb
Host smart-92ebcd2f-e21a-44e8-8014-9d7482f56232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029295085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2029295085
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.928777357
Short name T79
Test name
Test status
Simulation time 30098620 ps
CPU time 2.05 seconds
Started Jul 22 04:47:12 PM PDT 24
Finished Jul 22 04:47:14 PM PDT 24
Peak memory 223308 kb
Host smart-75b73b0e-499c-49b8-87ce-1ad6a9490f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928777357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.928777357
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.522936520
Short name T257
Test name
Test status
Simulation time 896919108 ps
CPU time 23.21 seconds
Started Jul 22 04:47:52 PM PDT 24
Finished Jul 22 04:48:16 PM PDT 24
Peak memory 250636 kb
Host smart-8044deec-688b-435d-941d-39e4c36c9dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522936520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.522936520
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.4280831149
Short name T555
Test name
Test status
Simulation time 462614436 ps
CPU time 8.39 seconds
Started Jul 22 04:47:15 PM PDT 24
Finished Jul 22 04:47:24 PM PDT 24
Peak memory 250676 kb
Host smart-f455968f-d499-47fa-9401-72a6dd45bc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280831149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.4280831149
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1266141907
Short name T174
Test name
Test status
Simulation time 1961036698 ps
CPU time 32.47 seconds
Started Jul 22 04:47:13 PM PDT 24
Finished Jul 22 04:47:47 PM PDT 24
Peak memory 250724 kb
Host smart-e64102a8-1f3f-4faa-bfd0-6b45970a9d42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266141907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1266141907
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2427368053
Short name T467
Test name
Test status
Simulation time 20489266 ps
CPU time 1.29 seconds
Started Jul 22 04:47:14 PM PDT 24
Finished Jul 22 04:47:16 PM PDT 24
Peak memory 217400 kb
Host smart-163b821c-0eb2-45dd-b42b-2855c98add3e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427368053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2427368053
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3688759812
Short name T558
Test name
Test status
Simulation time 65724885 ps
CPU time 1.12 seconds
Started Jul 22 04:47:13 PM PDT 24
Finished Jul 22 04:47:15 PM PDT 24
Peak memory 208732 kb
Host smart-62725693-6395-4522-905b-26e4448e4b62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688759812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3688759812
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.3050132590
Short name T722
Test name
Test status
Simulation time 290415817 ps
CPU time 9.19 seconds
Started Jul 22 04:47:14 PM PDT 24
Finished Jul 22 04:47:24 PM PDT 24
Peak memory 217948 kb
Host smart-89a4104b-a664-41ef-ac8b-b46309312e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050132590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3050132590
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3614909711
Short name T333
Test name
Test status
Simulation time 233917565 ps
CPU time 1.45 seconds
Started Jul 22 04:47:12 PM PDT 24
Finished Jul 22 04:47:14 PM PDT 24
Peak memory 217232 kb
Host smart-655408f9-9d8e-43a3-ac97-74ea55e0def7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614909711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3614909711
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.173861386
Short name T853
Test name
Test status
Simulation time 548089496 ps
CPU time 4.26 seconds
Started Jul 22 04:47:15 PM PDT 24
Finished Jul 22 04:47:20 PM PDT 24
Peak memory 218008 kb
Host smart-05e48ee7-4a5f-429e-a00c-9d8bdfc620a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173861386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.173861386
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1184459228
Short name T48
Test name
Test status
Simulation time 2560968070 ps
CPU time 17.8 seconds
Started Jul 22 04:47:12 PM PDT 24
Finished Jul 22 04:47:30 PM PDT 24
Peak memory 219400 kb
Host smart-d5763ace-711b-4a62-81f0-741428cde177
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184459228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1184459228
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3369968512
Short name T776
Test name
Test status
Simulation time 1077901115 ps
CPU time 13.25 seconds
Started Jul 22 04:47:15 PM PDT 24
Finished Jul 22 04:47:29 PM PDT 24
Peak memory 218056 kb
Host smart-ec5b7da7-bd72-40fb-b505-4cfab2007391
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369968512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3369968512
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.4114936083
Short name T654
Test name
Test status
Simulation time 1061060282 ps
CPU time 10.9 seconds
Started Jul 22 04:47:11 PM PDT 24
Finished Jul 22 04:47:23 PM PDT 24
Peak memory 225676 kb
Host smart-79552a3b-2faa-4ffb-98dc-7e53a41f4f0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114936083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
4114936083
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.3528848474
Short name T483
Test name
Test status
Simulation time 1166657049 ps
CPU time 12.13 seconds
Started Jul 22 04:47:41 PM PDT 24
Finished Jul 22 04:47:54 PM PDT 24
Peak memory 218220 kb
Host smart-bd947fd2-cbb9-4036-a926-7db4fe6c27e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528848474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3528848474
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2816978493
Short name T33
Test name
Test status
Simulation time 21250758 ps
CPU time 1.33 seconds
Started Jul 22 04:47:14 PM PDT 24
Finished Jul 22 04:47:16 PM PDT 24
Peak memory 213448 kb
Host smart-cd1d1fb2-39ec-48c6-8c1d-65c8f9cd74a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816978493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2816978493
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2242013055
Short name T367
Test name
Test status
Simulation time 857727305 ps
CPU time 16.62 seconds
Started Jul 22 04:47:13 PM PDT 24
Finished Jul 22 04:47:30 PM PDT 24
Peak memory 250700 kb
Host smart-2cc34b8e-92b2-4c7a-92d4-ba17feebca33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242013055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2242013055
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2933568128
Short name T607
Test name
Test status
Simulation time 100534519 ps
CPU time 7.15 seconds
Started Jul 22 04:47:13 PM PDT 24
Finished Jul 22 04:47:21 PM PDT 24
Peak memory 250128 kb
Host smart-b8a343a3-c3b7-48cf-a0b2-e610b04b9d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933568128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2933568128
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3985382089
Short name T655
Test name
Test status
Simulation time 7841270110 ps
CPU time 227.53 seconds
Started Jul 22 04:47:13 PM PDT 24
Finished Jul 22 04:51:01 PM PDT 24
Peak memory 250908 kb
Host smart-21500c23-61ad-438d-86bc-3ca127744773
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985382089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3985382089
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.2522736406
Short name T147
Test name
Test status
Simulation time 11072651443 ps
CPU time 171.71 seconds
Started Jul 22 04:47:12 PM PDT 24
Finished Jul 22 04:50:04 PM PDT 24
Peak memory 277840 kb
Host smart-5fdc2b51-d4e9-4781-8c3e-450773fd527f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2522736406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.2522736406
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1152384132
Short name T815
Test name
Test status
Simulation time 129022268 ps
CPU time 0.77 seconds
Started Jul 22 04:47:12 PM PDT 24
Finished Jul 22 04:47:14 PM PDT 24
Peak memory 208680 kb
Host smart-ebdae980-8ca0-442e-8bd3-e991cc9b0bf1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152384132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.1152384132
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1100620546
Short name T315
Test name
Test status
Simulation time 70324668 ps
CPU time 0.93 seconds
Started Jul 22 04:48:12 PM PDT 24
Finished Jul 22 04:48:13 PM PDT 24
Peak memory 208592 kb
Host smart-25c6f83c-3104-4b6f-907e-b1f07f4c5e24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100620546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1100620546
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.393500518
Short name T382
Test name
Test status
Simulation time 505825859 ps
CPU time 20.11 seconds
Started Jul 22 04:47:24 PM PDT 24
Finished Jul 22 04:47:45 PM PDT 24
Peak memory 217968 kb
Host smart-6e7c743b-05d7-4398-a5cc-0a828c4b71b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393500518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.393500518
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1697766425
Short name T26
Test name
Test status
Simulation time 1383216681 ps
CPU time 4.75 seconds
Started Jul 22 04:47:52 PM PDT 24
Finished Jul 22 04:47:58 PM PDT 24
Peak memory 217228 kb
Host smart-309cd16c-5032-44ef-b126-031fa6d7d24b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697766425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1697766425
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1113630384
Short name T324
Test name
Test status
Simulation time 253043538 ps
CPU time 1.58 seconds
Started Jul 22 04:48:23 PM PDT 24
Finished Jul 22 04:48:25 PM PDT 24
Peak memory 218000 kb
Host smart-5b4d48dc-3c7b-45ea-ab6a-01717cd6afc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113630384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1113630384
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3169261870
Short name T436
Test name
Test status
Simulation time 283094493 ps
CPU time 9.75 seconds
Started Jul 22 04:47:24 PM PDT 24
Finished Jul 22 04:47:34 PM PDT 24
Peak memory 217980 kb
Host smart-442d0805-f41d-4282-8c97-d8ef07db5e7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169261870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3169261870
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2422796025
Short name T408
Test name
Test status
Simulation time 417848491 ps
CPU time 9.15 seconds
Started Jul 22 04:47:23 PM PDT 24
Finished Jul 22 04:47:33 PM PDT 24
Peak memory 225716 kb
Host smart-e0ed38b0-4ff6-4470-9356-b70b7f42f2f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422796025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2422796025
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.629824365
Short name T162
Test name
Test status
Simulation time 827705261 ps
CPU time 6.07 seconds
Started Jul 22 04:47:52 PM PDT 24
Finished Jul 22 04:47:59 PM PDT 24
Peak memory 218040 kb
Host smart-e0c77610-37f2-40b2-8944-d5735a88119a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629824365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.629824365
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1987622190
Short name T806
Test name
Test status
Simulation time 77201328 ps
CPU time 2.13 seconds
Started Jul 22 04:47:13 PM PDT 24
Finished Jul 22 04:47:16 PM PDT 24
Peak memory 213972 kb
Host smart-1db838ea-97ff-4375-b7f2-72bbdbc17945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987622190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1987622190
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2506461370
Short name T398
Test name
Test status
Simulation time 869055310 ps
CPU time 25.74 seconds
Started Jul 22 04:47:23 PM PDT 24
Finished Jul 22 04:47:50 PM PDT 24
Peak memory 250788 kb
Host smart-53db7479-1cad-47a0-b180-79dbf24bab03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506461370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2506461370
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.1104565327
Short name T407
Test name
Test status
Simulation time 248832879 ps
CPU time 3.44 seconds
Started Jul 22 04:47:23 PM PDT 24
Finished Jul 22 04:47:27 PM PDT 24
Peak memory 221944 kb
Host smart-e5a676ad-560f-44e0-9db3-d9adbfa55f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104565327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.1104565327
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.4209871882
Short name T603
Test name
Test status
Simulation time 14167724124 ps
CPU time 341.09 seconds
Started Jul 22 04:47:22 PM PDT 24
Finished Jul 22 04:53:04 PM PDT 24
Peak memory 283464 kb
Host smart-9a7b407f-65bb-462c-a385-4d38aabd3550
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209871882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.4209871882
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2450805967
Short name T664
Test name
Test status
Simulation time 24933267 ps
CPU time 0.93 seconds
Started Jul 22 04:47:24 PM PDT 24
Finished Jul 22 04:47:26 PM PDT 24
Peak memory 208728 kb
Host smart-8931324f-90ba-47da-8327-e8550b190419
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450805967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.2450805967
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2101280208
Short name T794
Test name
Test status
Simulation time 44715095 ps
CPU time 0.99 seconds
Started Jul 22 04:47:34 PM PDT 24
Finished Jul 22 04:47:35 PM PDT 24
Peak memory 208564 kb
Host smart-d6fa7305-03c1-4b77-afa4-004bdc4e6308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101280208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2101280208
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2347141672
Short name T337
Test name
Test status
Simulation time 1563552485 ps
CPU time 15.08 seconds
Started Jul 22 04:47:26 PM PDT 24
Finished Jul 22 04:47:42 PM PDT 24
Peak memory 218076 kb
Host smart-9fb79072-e843-44e6-ae41-13875e8bd17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347141672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2347141672
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.428057358
Short name T717
Test name
Test status
Simulation time 129865118 ps
CPU time 4.04 seconds
Started Jul 22 04:47:25 PM PDT 24
Finished Jul 22 04:47:30 PM PDT 24
Peak memory 216792 kb
Host smart-b793b118-24e3-42dd-b761-cfe3bb864c47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428057358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.428057358
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1056175587
Short name T462
Test name
Test status
Simulation time 60915160 ps
CPU time 3.4 seconds
Started Jul 22 04:47:27 PM PDT 24
Finished Jul 22 04:47:31 PM PDT 24
Peak memory 217940 kb
Host smart-6694e9e3-8c96-482b-84eb-ff82f30a999c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056175587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1056175587
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1904236890
Short name T243
Test name
Test status
Simulation time 3711421734 ps
CPU time 13.69 seconds
Started Jul 22 04:47:24 PM PDT 24
Finished Jul 22 04:47:38 PM PDT 24
Peak memory 225880 kb
Host smart-92599f66-9250-4bc7-ae8f-3996937b707c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904236890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1904236890
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2583301077
Short name T373
Test name
Test status
Simulation time 1128756426 ps
CPU time 12.21 seconds
Started Jul 22 04:47:23 PM PDT 24
Finished Jul 22 04:47:36 PM PDT 24
Peak memory 225728 kb
Host smart-83a8ad75-22bf-4a9e-a895-a5dc30ba365d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583301077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2583301077
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3072367707
Short name T687
Test name
Test status
Simulation time 798886463 ps
CPU time 10.29 seconds
Started Jul 22 04:48:00 PM PDT 24
Finished Jul 22 04:48:11 PM PDT 24
Peak memory 218048 kb
Host smart-1e981e18-7401-43fc-9a07-e46282f35e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072367707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3072367707
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1226888877
Short name T549
Test name
Test status
Simulation time 19132830 ps
CPU time 1.51 seconds
Started Jul 22 04:47:24 PM PDT 24
Finished Jul 22 04:47:26 PM PDT 24
Peak memory 213644 kb
Host smart-7743d6f0-e6e9-40ae-b7db-5dd1400fd844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226888877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1226888877
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1128887043
Short name T409
Test name
Test status
Simulation time 516534081 ps
CPU time 26.92 seconds
Started Jul 22 04:47:23 PM PDT 24
Finished Jul 22 04:47:50 PM PDT 24
Peak memory 250792 kb
Host smart-13eb8050-f7c2-453f-851c-ae0994918d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128887043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1128887043
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.104570397
Short name T537
Test name
Test status
Simulation time 47736534 ps
CPU time 2.52 seconds
Started Jul 22 04:48:11 PM PDT 24
Finished Jul 22 04:48:14 PM PDT 24
Peak memory 217996 kb
Host smart-e67032dd-acd3-427b-bf35-20a940b5f471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104570397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.104570397
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.337456453
Short name T471
Test name
Test status
Simulation time 6600289412 ps
CPU time 86.01 seconds
Started Jul 22 04:47:33 PM PDT 24
Finished Jul 22 04:49:00 PM PDT 24
Peak memory 250560 kb
Host smart-cee7fbf5-68ac-4651-a963-7bcbd52b050c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337456453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.337456453
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2629504141
Short name T336
Test name
Test status
Simulation time 46335672 ps
CPU time 0.93 seconds
Started Jul 22 04:47:25 PM PDT 24
Finished Jul 22 04:47:26 PM PDT 24
Peak memory 208872 kb
Host smart-5e45c201-a561-45d1-a7f3-7dab7026c4e6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629504141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2629504141
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2365908726
Short name T577
Test name
Test status
Simulation time 14797815 ps
CPU time 1.02 seconds
Started Jul 22 04:47:32 PM PDT 24
Finished Jul 22 04:47:33 PM PDT 24
Peak memory 208572 kb
Host smart-002b4872-fb0f-4b93-8510-578e67a804ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365908726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2365908726
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3279150287
Short name T335
Test name
Test status
Simulation time 682518290 ps
CPU time 27.33 seconds
Started Jul 22 04:47:35 PM PDT 24
Finished Jul 22 04:48:03 PM PDT 24
Peak memory 218012 kb
Host smart-b4d2695b-c37e-4d83-9b68-b4d60552e469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279150287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3279150287
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1098515476
Short name T554
Test name
Test status
Simulation time 323181310 ps
CPU time 8.45 seconds
Started Jul 22 04:48:12 PM PDT 24
Finished Jul 22 04:48:21 PM PDT 24
Peak memory 217168 kb
Host smart-59122e8b-630e-4c68-85a2-11594b4b654a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098515476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.1098515476
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1758458318
Short name T769
Test name
Test status
Simulation time 71891109 ps
CPU time 2.3 seconds
Started Jul 22 04:47:32 PM PDT 24
Finished Jul 22 04:47:35 PM PDT 24
Peak memory 218000 kb
Host smart-b5a797bb-1166-421d-af00-c00e341aa6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758458318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1758458318
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3244665107
Short name T697
Test name
Test status
Simulation time 461054196 ps
CPU time 18.36 seconds
Started Jul 22 04:47:32 PM PDT 24
Finished Jul 22 04:47:51 PM PDT 24
Peak memory 218628 kb
Host smart-b1271e41-519b-4923-be09-8d43cf63dd8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244665107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3244665107
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1688403087
Short name T532
Test name
Test status
Simulation time 282962088 ps
CPU time 12.01 seconds
Started Jul 22 04:47:32 PM PDT 24
Finished Jul 22 04:47:45 PM PDT 24
Peak memory 217988 kb
Host smart-2cc1d826-f493-448f-a165-3e21248ce080
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688403087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1688403087
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3086216957
Short name T465
Test name
Test status
Simulation time 201292307 ps
CPU time 6.23 seconds
Started Jul 22 04:47:34 PM PDT 24
Finished Jul 22 04:47:40 PM PDT 24
Peak memory 224880 kb
Host smart-61dfe8f4-08ae-4ee7-9a99-aeb05c2cbb5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086216957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3086216957
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.2897051438
Short name T515
Test name
Test status
Simulation time 1390339959 ps
CPU time 13.37 seconds
Started Jul 22 04:47:33 PM PDT 24
Finished Jul 22 04:47:47 PM PDT 24
Peak memory 218112 kb
Host smart-02a039bd-6509-4d93-a425-ebc298d95e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897051438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.2897051438
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1351646898
Short name T464
Test name
Test status
Simulation time 46435262 ps
CPU time 2.35 seconds
Started Jul 22 04:48:11 PM PDT 24
Finished Jul 22 04:48:14 PM PDT 24
Peak memory 214056 kb
Host smart-35cc1224-042e-4b6e-a319-bf29a586e1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351646898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1351646898
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1330889486
Short name T833
Test name
Test status
Simulation time 306155522 ps
CPU time 31.94 seconds
Started Jul 22 04:47:30 PM PDT 24
Finished Jul 22 04:48:03 PM PDT 24
Peak memory 250672 kb
Host smart-6971d102-14bb-4604-83e3-9b276f76b8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330889486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1330889486
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.182558264
Short name T349
Test name
Test status
Simulation time 333114410 ps
CPU time 9.42 seconds
Started Jul 22 04:47:32 PM PDT 24
Finished Jul 22 04:47:41 PM PDT 24
Peak memory 250768 kb
Host smart-d29c67a7-a892-41de-80ee-22f11853f9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182558264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.182558264
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2592722227
Short name T493
Test name
Test status
Simulation time 27209047079 ps
CPU time 160.03 seconds
Started Jul 22 04:47:35 PM PDT 24
Finished Jul 22 04:50:15 PM PDT 24
Peak memory 280832 kb
Host smart-8bd9a186-6283-4710-a2a8-671246a25bc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592722227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2592722227
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3260421667
Short name T475
Test name
Test status
Simulation time 14340670 ps
CPU time 1.01 seconds
Started Jul 22 04:47:34 PM PDT 24
Finished Jul 22 04:47:36 PM PDT 24
Peak memory 208980 kb
Host smart-0baf6642-db5e-4c0e-98e4-d5d9ebb1475d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260421667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3260421667
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2514116690
Short name T434
Test name
Test status
Simulation time 75285701 ps
CPU time 1.17 seconds
Started Jul 22 04:47:40 PM PDT 24
Finished Jul 22 04:47:42 PM PDT 24
Peak memory 208672 kb
Host smart-7228d98b-f0fa-49b7-8a7e-4bf5c0ff87f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514116690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2514116690
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2367885881
Short name T648
Test name
Test status
Simulation time 238638936 ps
CPU time 10.05 seconds
Started Jul 22 04:47:40 PM PDT 24
Finished Jul 22 04:47:51 PM PDT 24
Peak memory 218088 kb
Host smart-d65c16ba-064d-4fd7-a774-9da43a982667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367885881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2367885881
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3786281144
Short name T681
Test name
Test status
Simulation time 383957357 ps
CPU time 1.84 seconds
Started Jul 22 04:47:42 PM PDT 24
Finished Jul 22 04:47:45 PM PDT 24
Peak memory 216828 kb
Host smart-a03884a3-4344-4049-8f70-814b0cdb4a60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786281144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.3786281144
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2284083657
Short name T702
Test name
Test status
Simulation time 38057005 ps
CPU time 2.01 seconds
Started Jul 22 04:48:00 PM PDT 24
Finished Jul 22 04:48:04 PM PDT 24
Peak memory 218000 kb
Host smart-751d9d95-8d80-45e9-a8af-6e8c3d336958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284083657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2284083657
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2206392693
Short name T808
Test name
Test status
Simulation time 267299178 ps
CPU time 11.9 seconds
Started Jul 22 04:48:15 PM PDT 24
Finished Jul 22 04:48:28 PM PDT 24
Peak memory 218576 kb
Host smart-efa40fd2-c1d9-4c31-9524-99862638a956
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206392693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2206392693
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.552288243
Short name T707
Test name
Test status
Simulation time 3065099190 ps
CPU time 15.7 seconds
Started Jul 22 04:47:40 PM PDT 24
Finished Jul 22 04:47:56 PM PDT 24
Peak memory 218592 kb
Host smart-1effcef8-70e7-4fba-a8b1-9c5af7a19755
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552288243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.552288243
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3399854694
Short name T190
Test name
Test status
Simulation time 1315997482 ps
CPU time 8.6 seconds
Started Jul 22 04:47:41 PM PDT 24
Finished Jul 22 04:47:50 PM PDT 24
Peak memory 225700 kb
Host smart-201f4c15-6dd2-4445-b160-51bb8fcc4637
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399854694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3399854694
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1995422152
Short name T56
Test name
Test status
Simulation time 234232148 ps
CPU time 7.31 seconds
Started Jul 22 04:47:43 PM PDT 24
Finished Jul 22 04:47:51 PM PDT 24
Peak memory 224856 kb
Host smart-2c4c7beb-a473-4237-88ff-5b3a6a620970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995422152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1995422152
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2453950238
Short name T522
Test name
Test status
Simulation time 64921508 ps
CPU time 3.26 seconds
Started Jul 22 04:47:34 PM PDT 24
Finished Jul 22 04:47:38 PM PDT 24
Peak memory 217416 kb
Host smart-42719138-6122-48a4-9283-84d28c83c27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453950238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2453950238
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2510418918
Short name T686
Test name
Test status
Simulation time 1006560376 ps
CPU time 23.95 seconds
Started Jul 22 04:47:43 PM PDT 24
Finished Jul 22 04:48:07 PM PDT 24
Peak memory 250660 kb
Host smart-a1fb9bf5-293f-4c7e-b27e-33b797d0f367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510418918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2510418918
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.891819581
Short name T437
Test name
Test status
Simulation time 362674390 ps
CPU time 8.29 seconds
Started Jul 22 04:47:40 PM PDT 24
Finished Jul 22 04:47:48 PM PDT 24
Peak memory 242576 kb
Host smart-6756c008-7bf9-4a5f-bc0a-bd2a1a73f951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891819581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.891819581
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.4294738489
Short name T159
Test name
Test status
Simulation time 78655604050 ps
CPU time 656 seconds
Started Jul 22 04:47:44 PM PDT 24
Finished Jul 22 04:58:40 PM PDT 24
Peak memory 276068 kb
Host smart-fd19a8db-030b-4cd2-a85d-4c6bf6174454
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294738489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.4294738489
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2789169262
Short name T580
Test name
Test status
Simulation time 34530729 ps
CPU time 0.84 seconds
Started Jul 22 04:47:42 PM PDT 24
Finished Jul 22 04:47:44 PM PDT 24
Peak memory 208720 kb
Host smart-ecbb815c-0fa1-48b0-bf2b-63d1fb615696
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789169262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2789169262
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.4063997595
Short name T453
Test name
Test status
Simulation time 44141413 ps
CPU time 0.9 seconds
Started Jul 22 04:47:44 PM PDT 24
Finished Jul 22 04:47:45 PM PDT 24
Peak memory 208472 kb
Host smart-963fbe28-b619-4af8-8ea2-498bd155b863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063997595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.4063997595
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2055167482
Short name T278
Test name
Test status
Simulation time 1027847607 ps
CPU time 11.18 seconds
Started Jul 22 04:47:43 PM PDT 24
Finished Jul 22 04:47:55 PM PDT 24
Peak memory 218060 kb
Host smart-e35a7699-699c-4e96-aea9-85cb89b98ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055167482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2055167482
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.3973255537
Short name T177
Test name
Test status
Simulation time 809995185 ps
CPU time 5.75 seconds
Started Jul 22 04:47:43 PM PDT 24
Finished Jul 22 04:47:49 PM PDT 24
Peak memory 216924 kb
Host smart-51d76792-4158-4de7-81ba-7b6a57e5db52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973255537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3973255537
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3359427534
Short name T496
Test name
Test status
Simulation time 96534401 ps
CPU time 1.61 seconds
Started Jul 22 04:47:44 PM PDT 24
Finished Jul 22 04:47:46 PM PDT 24
Peak memory 217996 kb
Host smart-b56c2cbe-304d-4b91-83b1-85af97d1e474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359427534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3359427534
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2361103921
Short name T458
Test name
Test status
Simulation time 286841740 ps
CPU time 10.99 seconds
Started Jul 22 04:48:04 PM PDT 24
Finished Jul 22 04:48:15 PM PDT 24
Peak memory 218792 kb
Host smart-18dd365e-f762-48a4-89e6-a4031bb706ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361103921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2361103921
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1113982921
Short name T511
Test name
Test status
Simulation time 874706113 ps
CPU time 26.47 seconds
Started Jul 22 04:47:43 PM PDT 24
Finished Jul 22 04:48:10 PM PDT 24
Peak memory 225728 kb
Host smart-389fbbd0-35f1-4ac6-9892-2e0e39280411
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113982921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1113982921
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1044381201
Short name T172
Test name
Test status
Simulation time 3436905872 ps
CPU time 16.22 seconds
Started Jul 22 04:47:42 PM PDT 24
Finished Jul 22 04:47:58 PM PDT 24
Peak memory 218676 kb
Host smart-d53b9e41-0c24-4ebd-9d14-a7d49b6e2e0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044381201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1044381201
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.85505114
Short name T514
Test name
Test status
Simulation time 606415859 ps
CPU time 11.59 seconds
Started Jul 22 04:47:40 PM PDT 24
Finished Jul 22 04:47:52 PM PDT 24
Peak memory 225736 kb
Host smart-96e85db3-7408-4df1-9827-334559c276f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85505114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.85505114
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3006131895
Short name T353
Test name
Test status
Simulation time 98366420 ps
CPU time 1.83 seconds
Started Jul 22 04:47:43 PM PDT 24
Finished Jul 22 04:47:45 PM PDT 24
Peak memory 213844 kb
Host smart-67c550b3-76c0-45cd-b6a9-9b2f9aa1990e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006131895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3006131895
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.985410748
Short name T360
Test name
Test status
Simulation time 661536280 ps
CPU time 26.12 seconds
Started Jul 22 04:47:42 PM PDT 24
Finished Jul 22 04:48:09 PM PDT 24
Peak memory 250684 kb
Host smart-7db72565-884d-4941-be80-07df5b507d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985410748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.985410748
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1800613960
Short name T669
Test name
Test status
Simulation time 100901906 ps
CPU time 3.48 seconds
Started Jul 22 04:47:44 PM PDT 24
Finished Jul 22 04:47:48 PM PDT 24
Peak memory 222072 kb
Host smart-1495fc3d-c8ca-459e-9166-e63e84d2bd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800613960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1800613960
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1664769905
Short name T492
Test name
Test status
Simulation time 13668253 ps
CPU time 0.89 seconds
Started Jul 22 04:47:42 PM PDT 24
Finished Jul 22 04:47:43 PM PDT 24
Peak memory 208376 kb
Host smart-5756fedb-17e1-43e8-95b9-1acee9b3dd62
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664769905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1664769905
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.209350955
Short name T451
Test name
Test status
Simulation time 21939904 ps
CPU time 1.26 seconds
Started Jul 22 04:43:51 PM PDT 24
Finished Jul 22 04:43:53 PM PDT 24
Peak memory 208768 kb
Host smart-d67bb7cc-8712-4c3f-911c-a62c5c5a03bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209350955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.209350955
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3604807084
Short name T790
Test name
Test status
Simulation time 27122358 ps
CPU time 0.96 seconds
Started Jul 22 04:43:53 PM PDT 24
Finished Jul 22 04:43:55 PM PDT 24
Peak memory 208496 kb
Host smart-0559fb65-028d-45f3-933d-13458fa8c301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604807084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3604807084
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2976522417
Short name T254
Test name
Test status
Simulation time 213834759 ps
CPU time 11.34 seconds
Started Jul 22 04:43:43 PM PDT 24
Finished Jul 22 04:43:55 PM PDT 24
Peak memory 218020 kb
Host smart-52cc8fce-1524-4b8e-bf5e-f2af23ce03bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976522417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2976522417
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1344685381
Short name T738
Test name
Test status
Simulation time 1053068968 ps
CPU time 9.52 seconds
Started Jul 22 04:43:53 PM PDT 24
Finished Jul 22 04:44:04 PM PDT 24
Peak memory 217080 kb
Host smart-b0620101-48c1-415c-9589-1ef674c733ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344685381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1344685381
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2421899700
Short name T348
Test name
Test status
Simulation time 1601874484 ps
CPU time 32.08 seconds
Started Jul 22 04:43:54 PM PDT 24
Finished Jul 22 04:44:27 PM PDT 24
Peak memory 218544 kb
Host smart-0f7c14fe-50a8-49f1-ba4c-a4bbf5cdbbf6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421899700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2421899700
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2937635931
Short name T536
Test name
Test status
Simulation time 226909819 ps
CPU time 5.28 seconds
Started Jul 22 04:43:54 PM PDT 24
Finished Jul 22 04:44:00 PM PDT 24
Peak memory 217512 kb
Host smart-2c4e08f5-d1dd-4e8e-b6c5-24ed77cd9be8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937635931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
937635931
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3764030201
Short name T698
Test name
Test status
Simulation time 352205456 ps
CPU time 3.71 seconds
Started Jul 22 04:43:52 PM PDT 24
Finished Jul 22 04:43:56 PM PDT 24
Peak memory 221436 kb
Host smart-3b5fb283-8851-412b-9d81-ed35b7abe605
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764030201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3764030201
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.530970430
Short name T694
Test name
Test status
Simulation time 3600806170 ps
CPU time 26.48 seconds
Started Jul 22 04:43:51 PM PDT 24
Finished Jul 22 04:44:18 PM PDT 24
Peak memory 217320 kb
Host smart-ae9f966e-79a1-4adf-8b8f-e393f9b804b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530970430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.530970430
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.2414520985
Short name T571
Test name
Test status
Simulation time 206641281 ps
CPU time 5.48 seconds
Started Jul 22 04:43:52 PM PDT 24
Finished Jul 22 04:43:59 PM PDT 24
Peak memory 217284 kb
Host smart-a85ccca4-2682-4029-b50e-a381f387bb69
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414520985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
2414520985
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2086812556
Short name T358
Test name
Test status
Simulation time 1077378747 ps
CPU time 38.94 seconds
Started Jul 22 04:43:56 PM PDT 24
Finished Jul 22 04:44:35 PM PDT 24
Peak memory 250620 kb
Host smart-94a7a283-99b8-4845-8459-371a9e5b1ed4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086812556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2086812556
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2222786866
Short name T724
Test name
Test status
Simulation time 302525163 ps
CPU time 16.26 seconds
Started Jul 22 04:43:52 PM PDT 24
Finished Jul 22 04:44:08 PM PDT 24
Peak memory 250572 kb
Host smart-02cc5847-432a-4964-95aa-b48cffcd476e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222786866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2222786866
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3886061824
Short name T676
Test name
Test status
Simulation time 169389241 ps
CPU time 3.86 seconds
Started Jul 22 04:43:44 PM PDT 24
Finished Jul 22 04:43:48 PM PDT 24
Peak memory 222292 kb
Host smart-39dbefec-5931-4b26-8ca2-5f0c4892c770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886061824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3886061824
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.4197009011
Short name T357
Test name
Test status
Simulation time 874714163 ps
CPU time 7.96 seconds
Started Jul 22 04:43:44 PM PDT 24
Finished Jul 22 04:43:52 PM PDT 24
Peak memory 217460 kb
Host smart-1323d38b-da13-4c61-a9f1-0a0137ba093e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197009011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.4197009011
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1065838975
Short name T402
Test name
Test status
Simulation time 1237397077 ps
CPU time 9.41 seconds
Started Jul 22 04:43:53 PM PDT 24
Finished Jul 22 04:44:04 PM PDT 24
Peak memory 218640 kb
Host smart-8cec707b-1617-4bd6-96d5-f9fcb2dba1e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065838975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1065838975
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2606584422
Short name T484
Test name
Test status
Simulation time 557934673 ps
CPU time 13.61 seconds
Started Jul 22 04:43:53 PM PDT 24
Finished Jul 22 04:44:08 PM PDT 24
Peak memory 218312 kb
Host smart-1692abb2-a624-49a2-8d11-50688a598d4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606584422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2606584422
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2284233553
Short name T760
Test name
Test status
Simulation time 1685362038 ps
CPU time 6.73 seconds
Started Jul 22 04:44:14 PM PDT 24
Finished Jul 22 04:44:21 PM PDT 24
Peak memory 217868 kb
Host smart-2e43fbd9-0b74-4bee-bf0e-e71c0529a683
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284233553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
284233553
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.903666483
Short name T301
Test name
Test status
Simulation time 1542839702 ps
CPU time 14.05 seconds
Started Jul 22 04:43:46 PM PDT 24
Finished Jul 22 04:44:01 PM PDT 24
Peak memory 218152 kb
Host smart-39f8f40a-eb2c-46c4-9e20-50eec91c29fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903666483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.903666483
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3516104028
Short name T721
Test name
Test status
Simulation time 146002201 ps
CPU time 7.21 seconds
Started Jul 22 04:43:45 PM PDT 24
Finished Jul 22 04:43:52 PM PDT 24
Peak memory 217404 kb
Host smart-c780b366-9f0d-45d2-89d8-6aeee1bd55be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516104028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3516104028
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1652240462
Short name T489
Test name
Test status
Simulation time 1943123127 ps
CPU time 24.48 seconds
Started Jul 22 04:43:46 PM PDT 24
Finished Jul 22 04:44:11 PM PDT 24
Peak memory 250880 kb
Host smart-53fc1b72-e868-4531-9f49-bd960ab6bf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652240462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1652240462
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.53324415
Short name T786
Test name
Test status
Simulation time 61221249 ps
CPU time 3.23 seconds
Started Jul 22 04:43:45 PM PDT 24
Finished Jul 22 04:43:49 PM PDT 24
Peak memory 221900 kb
Host smart-1a6726f2-f5b2-413c-84c7-11f3fd0ea9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53324415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.53324415
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.805590959
Short name T196
Test name
Test status
Simulation time 5034671692 ps
CPU time 57.06 seconds
Started Jul 22 04:43:52 PM PDT 24
Finished Jul 22 04:44:50 PM PDT 24
Peak memory 250816 kb
Host smart-54cbf866-223b-42fe-8d4f-d465fe50dedf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805590959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.805590959
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2557659616
Short name T435
Test name
Test status
Simulation time 22182983 ps
CPU time 0.8 seconds
Started Jul 22 04:43:45 PM PDT 24
Finished Jul 22 04:43:46 PM PDT 24
Peak memory 208756 kb
Host smart-31e46b4e-9b39-4cc0-93ff-37211812507d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557659616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2557659616
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2636637102
Short name T72
Test name
Test status
Simulation time 27211451 ps
CPU time 0.85 seconds
Started Jul 22 04:44:00 PM PDT 24
Finished Jul 22 04:44:01 PM PDT 24
Peak memory 208608 kb
Host smart-a9599869-3494-447e-ace2-e2823e0f375a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636637102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2636637102
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1412945172
Short name T70
Test name
Test status
Simulation time 36238630 ps
CPU time 0.89 seconds
Started Jul 22 04:43:52 PM PDT 24
Finished Jul 22 04:43:53 PM PDT 24
Peak memory 208520 kb
Host smart-a6a7c065-0905-4af7-955b-06f63a4123de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412945172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1412945172
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2790882952
Short name T331
Test name
Test status
Simulation time 1319893564 ps
CPU time 12.36 seconds
Started Jul 22 04:43:53 PM PDT 24
Finished Jul 22 04:44:07 PM PDT 24
Peak memory 218020 kb
Host smart-f0f4085d-2552-4cc0-82b1-d6089612c256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790882952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2790882952
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.3287317552
Short name T762
Test name
Test status
Simulation time 431540580 ps
CPU time 5.69 seconds
Started Jul 22 04:44:00 PM PDT 24
Finished Jul 22 04:44:06 PM PDT 24
Peak memory 217336 kb
Host smart-d4ca7b7a-a8e5-4d9a-87f1-b9e785b27dc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287317552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3287317552
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1388765983
Short name T325
Test name
Test status
Simulation time 13379167183 ps
CPU time 37.41 seconds
Started Jul 22 04:44:09 PM PDT 24
Finished Jul 22 04:44:47 PM PDT 24
Peak memory 225752 kb
Host smart-0e6b8984-4036-4829-81a7-b26db9988ebf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388765983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1388765983
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.3162308023
Short name T263
Test name
Test status
Simulation time 68335597 ps
CPU time 1.58 seconds
Started Jul 22 04:44:05 PM PDT 24
Finished Jul 22 04:44:07 PM PDT 24
Peak memory 217556 kb
Host smart-75c2c0d9-8aa6-49c7-8a5a-e7b3c1299cda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162308023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.3
162308023
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1862001546
Short name T810
Test name
Test status
Simulation time 150343020 ps
CPU time 4.63 seconds
Started Jul 22 04:43:53 PM PDT 24
Finished Jul 22 04:43:59 PM PDT 24
Peak memory 221644 kb
Host smart-9a58d7ef-47f7-418e-a940-415403394c8b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862001546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1862001546
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.173199458
Short name T297
Test name
Test status
Simulation time 1741630595 ps
CPU time 11.97 seconds
Started Jul 22 04:44:03 PM PDT 24
Finished Jul 22 04:44:15 PM PDT 24
Peak memory 217356 kb
Host smart-facdb878-4f87-49c7-beed-1753d7853445
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173199458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_regwen_during_op.173199458
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.363229250
Short name T272
Test name
Test status
Simulation time 117206715 ps
CPU time 2.13 seconds
Started Jul 22 04:43:53 PM PDT 24
Finished Jul 22 04:43:56 PM PDT 24
Peak memory 217336 kb
Host smart-cc885053-735d-4f08-8c2b-09b88d016e24
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363229250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.363229250
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1784556621
Short name T293
Test name
Test status
Simulation time 2348793250 ps
CPU time 89.68 seconds
Started Jul 22 04:43:54 PM PDT 24
Finished Jul 22 04:45:25 PM PDT 24
Peak memory 267696 kb
Host smart-61f2e222-fad0-4d9b-adcc-adc1886582f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784556621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1784556621
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1132519885
Short name T22
Test name
Test status
Simulation time 1757836908 ps
CPU time 11.22 seconds
Started Jul 22 04:44:13 PM PDT 24
Finished Jul 22 04:44:25 PM PDT 24
Peak memory 217976 kb
Host smart-90e95b5f-acc0-4749-b5d5-3b569ef37e00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132519885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1132519885
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.224777269
Short name T416
Test name
Test status
Simulation time 556775042 ps
CPU time 3.16 seconds
Started Jul 22 04:43:51 PM PDT 24
Finished Jul 22 04:43:55 PM PDT 24
Peak memory 222080 kb
Host smart-835d6b37-ec5d-4d0e-b560-d47b7c701bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224777269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.224777269
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3084454614
Short name T179
Test name
Test status
Simulation time 2718526183 ps
CPU time 10.26 seconds
Started Jul 22 04:43:52 PM PDT 24
Finished Jul 22 04:44:04 PM PDT 24
Peak memory 217472 kb
Host smart-b0288c98-8948-459c-b403-28f822040abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084454614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3084454614
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.4216037427
Short name T300
Test name
Test status
Simulation time 627202231 ps
CPU time 13.22 seconds
Started Jul 22 04:44:23 PM PDT 24
Finished Jul 22 04:44:37 PM PDT 24
Peak memory 217900 kb
Host smart-93d07df5-9ed2-414d-92a0-b4ab5da6d009
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216037427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.4216037427
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2401804609
Short name T620
Test name
Test status
Simulation time 876841063 ps
CPU time 9.25 seconds
Started Jul 22 04:44:01 PM PDT 24
Finished Jul 22 04:44:11 PM PDT 24
Peak memory 225696 kb
Host smart-d95038ed-4757-410e-a616-3c54c132d9a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401804609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
401804609
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.682037661
Short name T651
Test name
Test status
Simulation time 321501599 ps
CPU time 8.15 seconds
Started Jul 22 04:43:53 PM PDT 24
Finished Jul 22 04:44:02 PM PDT 24
Peak memory 218052 kb
Host smart-488ef2c3-61c0-4dfe-9bb7-562223eaaf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682037661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.682037661
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.618420359
Short name T77
Test name
Test status
Simulation time 129579518 ps
CPU time 4.1 seconds
Started Jul 22 04:43:52 PM PDT 24
Finished Jul 22 04:43:57 PM PDT 24
Peak memory 217448 kb
Host smart-4044da7d-ce61-4ebe-ba92-53f54d278c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618420359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.618420359
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.2791852565
Short name T711
Test name
Test status
Simulation time 295599562 ps
CPU time 24.37 seconds
Started Jul 22 04:43:53 PM PDT 24
Finished Jul 22 04:44:19 PM PDT 24
Peak memory 250720 kb
Host smart-3cdabffc-4875-402f-a7bf-d9db97ca6541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791852565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2791852565
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.492750628
Short name T716
Test name
Test status
Simulation time 461417008 ps
CPU time 8.05 seconds
Started Jul 22 04:44:36 PM PDT 24
Finished Jul 22 04:44:45 PM PDT 24
Peak memory 250568 kb
Host smart-b8a5ef09-a37e-4db0-90ea-ec9fc4f6808c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492750628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.492750628
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2536404228
Short name T49
Test name
Test status
Simulation time 23269612526 ps
CPU time 391.48 seconds
Started Jul 22 04:44:00 PM PDT 24
Finished Jul 22 04:50:32 PM PDT 24
Peak memory 250696 kb
Host smart-746e647d-7144-4025-b1ec-4d614a97efb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536404228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2536404228
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.971681316
Short name T819
Test name
Test status
Simulation time 42322846 ps
CPU time 0.78 seconds
Started Jul 22 04:43:53 PM PDT 24
Finished Jul 22 04:43:55 PM PDT 24
Peak memory 208592 kb
Host smart-6a1e9916-0bbf-47ed-9e1f-ebfc4493fdee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971681316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr
l_volatile_unlock_smoke.971681316
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3378219502
Short name T834
Test name
Test status
Simulation time 59834348 ps
CPU time 1.09 seconds
Started Jul 22 04:44:00 PM PDT 24
Finished Jul 22 04:44:02 PM PDT 24
Peak memory 208716 kb
Host smart-58ce2f01-d20a-45fa-bff8-fb29f503002f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378219502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3378219502
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1588292743
Short name T659
Test name
Test status
Simulation time 38211136 ps
CPU time 0.8 seconds
Started Jul 22 04:44:02 PM PDT 24
Finished Jul 22 04:44:04 PM PDT 24
Peak memory 208732 kb
Host smart-77c7948e-1629-4c85-866e-3a0e42e63a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588292743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1588292743
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2069634063
Short name T397
Test name
Test status
Simulation time 470543896 ps
CPU time 13.82 seconds
Started Jul 22 04:44:02 PM PDT 24
Finished Jul 22 04:44:16 PM PDT 24
Peak memory 218020 kb
Host smart-cd298d3d-e93d-4b7f-9557-5c47cd2804e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069634063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2069634063
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3586242775
Short name T8
Test name
Test status
Simulation time 1359795498 ps
CPU time 3.85 seconds
Started Jul 22 04:44:04 PM PDT 24
Finished Jul 22 04:44:09 PM PDT 24
Peak memory 216900 kb
Host smart-80f7318a-bdce-4a08-a34e-8a7c4897d16e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586242775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3586242775
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3922709640
Short name T670
Test name
Test status
Simulation time 1635694268 ps
CPU time 26.6 seconds
Started Jul 22 04:44:05 PM PDT 24
Finished Jul 22 04:44:32 PM PDT 24
Peak memory 218060 kb
Host smart-8dcb3c37-2499-4c96-bbcd-bf7af0562e30
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922709640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3922709640
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3710144434
Short name T807
Test name
Test status
Simulation time 428828206 ps
CPU time 2.07 seconds
Started Jul 22 04:44:01 PM PDT 24
Finished Jul 22 04:44:03 PM PDT 24
Peak memory 217564 kb
Host smart-c10eabd9-4567-4b7e-b66d-4b7a52c7d473
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710144434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
710144434
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2660821619
Short name T597
Test name
Test status
Simulation time 493957209 ps
CPU time 7.81 seconds
Started Jul 22 04:44:02 PM PDT 24
Finished Jul 22 04:44:11 PM PDT 24
Peak memory 221764 kb
Host smart-c2b7798f-1df2-436e-a01e-3b958c3325a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660821619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2660821619
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2043627709
Short name T383
Test name
Test status
Simulation time 1276877386 ps
CPU time 33.89 seconds
Started Jul 22 04:44:02 PM PDT 24
Finished Jul 22 04:44:36 PM PDT 24
Peak memory 217428 kb
Host smart-ae0ac13b-8fcb-48cd-958e-98fabfc5f0db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043627709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2043627709
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.486969287
Short name T766
Test name
Test status
Simulation time 215760753 ps
CPU time 1.42 seconds
Started Jul 22 04:43:59 PM PDT 24
Finished Jul 22 04:44:01 PM PDT 24
Peak memory 217328 kb
Host smart-a0bd2e70-f58a-405f-9bc6-635ccf2fcbc6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486969287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.486969287
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2813929862
Short name T730
Test name
Test status
Simulation time 31031820385 ps
CPU time 115.08 seconds
Started Jul 22 04:44:02 PM PDT 24
Finished Jul 22 04:45:58 PM PDT 24
Peak memory 283448 kb
Host smart-0b05ecb0-9c17-4469-9b15-7ec2ce9958a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813929862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2813929862
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1186291851
Short name T822
Test name
Test status
Simulation time 417061050 ps
CPU time 12.45 seconds
Started Jul 22 04:44:00 PM PDT 24
Finished Jul 22 04:44:13 PM PDT 24
Peak memory 246168 kb
Host smart-cbd76c93-28ce-46a4-b8f1-85b23b46287e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186291851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.1186291851
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1297798615
Short name T645
Test name
Test status
Simulation time 48861983 ps
CPU time 2.29 seconds
Started Jul 22 04:44:26 PM PDT 24
Finished Jul 22 04:44:29 PM PDT 24
Peak memory 217936 kb
Host smart-8338700d-ee87-4d90-bad9-844162c57c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297798615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1297798615
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3980161052
Short name T459
Test name
Test status
Simulation time 203767250 ps
CPU time 5.67 seconds
Started Jul 22 04:44:01 PM PDT 24
Finished Jul 22 04:44:07 PM PDT 24
Peak memory 217408 kb
Host smart-c6e9f3a8-5fec-4659-944b-3815e64067ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980161052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3980161052
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3707859124
Short name T432
Test name
Test status
Simulation time 751448254 ps
CPU time 10.5 seconds
Started Jul 22 04:44:02 PM PDT 24
Finished Jul 22 04:44:13 PM PDT 24
Peak memory 218640 kb
Host smart-2fee01e3-e98c-4ae9-a249-788de5b4b3e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707859124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3707859124
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.976871954
Short name T725
Test name
Test status
Simulation time 1492777848 ps
CPU time 8.26 seconds
Started Jul 22 04:44:02 PM PDT 24
Finished Jul 22 04:44:11 PM PDT 24
Peak memory 217972 kb
Host smart-1e97f2ad-cad2-48bb-bed1-b7a733daedf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976871954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.976871954
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.336545538
Short name T176
Test name
Test status
Simulation time 199752298 ps
CPU time 8.53 seconds
Started Jul 22 04:44:00 PM PDT 24
Finished Jul 22 04:44:09 PM PDT 24
Peak memory 225720 kb
Host smart-9eb9fe8e-4bb7-4b47-8dbb-b30c5b7e9a21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336545538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.336545538
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.875296439
Short name T414
Test name
Test status
Simulation time 1141784870 ps
CPU time 9.59 seconds
Started Jul 22 04:44:03 PM PDT 24
Finished Jul 22 04:44:13 PM PDT 24
Peak memory 218064 kb
Host smart-8c9128a5-07d4-453a-ba73-7b2aa0e636fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875296439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.875296439
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.533297533
Short name T427
Test name
Test status
Simulation time 168742702 ps
CPU time 3.04 seconds
Started Jul 22 04:44:03 PM PDT 24
Finished Jul 22 04:44:06 PM PDT 24
Peak memory 217412 kb
Host smart-e1d86742-3e3d-4479-a1ac-531abc49a069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533297533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.533297533
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1816212405
Short name T307
Test name
Test status
Simulation time 352253050 ps
CPU time 32.62 seconds
Started Jul 22 04:44:02 PM PDT 24
Finished Jul 22 04:44:36 PM PDT 24
Peak memory 250748 kb
Host smart-da75a424-da27-46dc-ad86-149717d89f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816212405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1816212405
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2318849518
Short name T743
Test name
Test status
Simulation time 75229704 ps
CPU time 5.94 seconds
Started Jul 22 04:44:02 PM PDT 24
Finished Jul 22 04:44:08 PM PDT 24
Peak memory 246864 kb
Host smart-6171622e-f904-4bb1-aa5a-9d3641219c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318849518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2318849518
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2223330117
Short name T568
Test name
Test status
Simulation time 11612409058 ps
CPU time 246.45 seconds
Started Jul 22 04:44:03 PM PDT 24
Finished Jul 22 04:48:10 PM PDT 24
Peak memory 279688 kb
Host smart-e2f462d2-cf3b-4d4f-aaad-2e88eaaf28f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223330117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2223330117
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.573716997
Short name T139
Test name
Test status
Simulation time 11406075314 ps
CPU time 221.45 seconds
Started Jul 22 04:44:02 PM PDT 24
Finished Jul 22 04:47:45 PM PDT 24
Peak memory 277212 kb
Host smart-927e462a-b2da-4bd9-aac2-8ef32a24dccf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=573716997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.573716997
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1766127739
Short name T497
Test name
Test status
Simulation time 15061159 ps
CPU time 1 seconds
Started Jul 22 04:44:00 PM PDT 24
Finished Jul 22 04:44:01 PM PDT 24
Peak memory 208952 kb
Host smart-670944ee-d2c3-49f0-854c-22807e1a6b09
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766127739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1766127739
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2159869489
Short name T632
Test name
Test status
Simulation time 26702905 ps
CPU time 1.42 seconds
Started Jul 22 04:44:27 PM PDT 24
Finished Jul 22 04:44:29 PM PDT 24
Peak memory 208828 kb
Host smart-c1fda9b4-4761-4af9-8a9b-7a7a770d445e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159869489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2159869489
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.687106050
Short name T761
Test name
Test status
Simulation time 1328090307 ps
CPU time 12.64 seconds
Started Jul 22 04:44:27 PM PDT 24
Finished Jul 22 04:44:41 PM PDT 24
Peak memory 218000 kb
Host smart-58daad33-49aa-4449-bc53-91e0bf05ac35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687106050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.687106050
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1790675496
Short name T376
Test name
Test status
Simulation time 664330243 ps
CPU time 3.93 seconds
Started Jul 22 04:44:12 PM PDT 24
Finished Jul 22 04:44:16 PM PDT 24
Peak memory 216820 kb
Host smart-83a2828e-c620-4ed2-b96b-0d5f1b0271f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790675496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1790675496
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.3438609299
Short name T768
Test name
Test status
Simulation time 1166125547 ps
CPU time 23.71 seconds
Started Jul 22 04:44:10 PM PDT 24
Finished Jul 22 04:44:35 PM PDT 24
Peak memory 218580 kb
Host smart-e31b6481-a942-4bf7-8d23-3f6999c4ae21
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438609299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.3438609299
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2699082631
Short name T366
Test name
Test status
Simulation time 1641357182 ps
CPU time 5.16 seconds
Started Jul 22 04:44:10 PM PDT 24
Finished Jul 22 04:44:16 PM PDT 24
Peak memory 217540 kb
Host smart-4752bb90-90fe-425d-b288-c318d3938b27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699082631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
699082631
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2164922737
Short name T860
Test name
Test status
Simulation time 2347432480 ps
CPU time 11.59 seconds
Started Jul 22 04:44:12 PM PDT 24
Finished Jul 22 04:44:24 PM PDT 24
Peak memory 218064 kb
Host smart-3d89f33f-5924-4628-9c81-1c05650edb05
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164922737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2164922737
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2418507919
Short name T443
Test name
Test status
Simulation time 8807793338 ps
CPU time 36.24 seconds
Started Jul 22 04:44:32 PM PDT 24
Finished Jul 22 04:45:09 PM PDT 24
Peak memory 217352 kb
Host smart-a861d2bc-68bf-4394-ba81-9e51a0a59811
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418507919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2418507919
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1708746353
Short name T81
Test name
Test status
Simulation time 380858112 ps
CPU time 3.76 seconds
Started Jul 22 04:44:22 PM PDT 24
Finished Jul 22 04:44:26 PM PDT 24
Peak memory 217428 kb
Host smart-18534c19-6081-49f9-a08e-14ccd8dca45c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708746353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1708746353
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.6733682
Short name T672
Test name
Test status
Simulation time 8262721415 ps
CPU time 74.84 seconds
Started Jul 22 04:44:12 PM PDT 24
Finished Jul 22 04:45:27 PM PDT 24
Peak memory 283392 kb
Host smart-166273ce-0bd8-4dbf-a1f6-3c990dc70e4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6733682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_st
ate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_s
tate_failure.6733682
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.987240663
Short name T788
Test name
Test status
Simulation time 1431192743 ps
CPU time 16.19 seconds
Started Jul 22 04:44:13 PM PDT 24
Finished Jul 22 04:44:29 PM PDT 24
Peak memory 250576 kb
Host smart-7a32376c-0df7-491c-8c2a-17ae6df22943
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987240663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.987240663
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1611107183
Short name T268
Test name
Test status
Simulation time 62776642 ps
CPU time 2.92 seconds
Started Jul 22 04:44:12 PM PDT 24
Finished Jul 22 04:44:15 PM PDT 24
Peak memory 218048 kb
Host smart-8941cd8e-b32b-4d66-afbb-95744d9a181c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611107183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1611107183
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.853238896
Short name T530
Test name
Test status
Simulation time 341954661 ps
CPU time 8.85 seconds
Started Jul 22 04:44:47 PM PDT 24
Finished Jul 22 04:44:56 PM PDT 24
Peak memory 217524 kb
Host smart-017f3f64-45c5-41c5-bbc7-4950c055b7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853238896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.853238896
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.468420687
Short name T169
Test name
Test status
Simulation time 571183882 ps
CPU time 21.78 seconds
Started Jul 22 04:44:10 PM PDT 24
Finished Jul 22 04:44:33 PM PDT 24
Peak memory 218692 kb
Host smart-d66e71f4-ded3-45d6-b95f-35b43df4e8a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468420687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.468420687
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1832026184
Short name T856
Test name
Test status
Simulation time 1030541759 ps
CPU time 9.83 seconds
Started Jul 22 04:44:47 PM PDT 24
Finished Jul 22 04:44:57 PM PDT 24
Peak memory 225712 kb
Host smart-374562a1-44ce-4ee0-bb55-a345a24748ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832026184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1832026184
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.164926031
Short name T175
Test name
Test status
Simulation time 278445139 ps
CPU time 7.45 seconds
Started Jul 22 04:44:10 PM PDT 24
Finished Jul 22 04:44:18 PM PDT 24
Peak memory 225800 kb
Host smart-c14211ce-2763-4d83-94e9-b7a1705150f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164926031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.164926031
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3440888524
Short name T561
Test name
Test status
Simulation time 393311098 ps
CPU time 10.41 seconds
Started Jul 22 04:44:38 PM PDT 24
Finished Jul 22 04:44:49 PM PDT 24
Peak memory 225800 kb
Host smart-5e60734f-56bc-45d6-893d-59be40537d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440888524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3440888524
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3138720998
Short name T329
Test name
Test status
Simulation time 41420023 ps
CPU time 3.15 seconds
Started Jul 22 04:44:01 PM PDT 24
Finished Jul 22 04:44:04 PM PDT 24
Peak memory 214820 kb
Host smart-18a3e5b0-041c-4f62-93bc-2b2c2914e7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138720998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3138720998
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2678834298
Short name T609
Test name
Test status
Simulation time 465629672 ps
CPU time 26.71 seconds
Started Jul 22 04:44:09 PM PDT 24
Finished Jul 22 04:44:37 PM PDT 24
Peak memory 250692 kb
Host smart-85b24352-621f-4ef4-8214-90339b778c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678834298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2678834298
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3755342915
Short name T351
Test name
Test status
Simulation time 508714680 ps
CPU time 9.66 seconds
Started Jul 22 04:44:10 PM PDT 24
Finished Jul 22 04:44:21 PM PDT 24
Peak memory 250672 kb
Host smart-dd0c59cd-21c6-4c5a-89bd-4734603e6939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755342915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3755342915
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.729381035
Short name T319
Test name
Test status
Simulation time 4585431428 ps
CPU time 36.29 seconds
Started Jul 22 04:44:11 PM PDT 24
Finished Jul 22 04:44:48 PM PDT 24
Peak memory 225928 kb
Host smart-8983ad41-6046-4a36-a7c9-fed2e8477ddb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729381035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.729381035
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2235903932
Short name T610
Test name
Test status
Simulation time 12777129 ps
CPU time 0.97 seconds
Started Jul 22 04:44:10 PM PDT 24
Finished Jul 22 04:44:12 PM PDT 24
Peak memory 211592 kb
Host smart-584c930d-1952-4582-a054-3de573fb8d80
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235903932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2235903932
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.343212072
Short name T227
Test name
Test status
Simulation time 36152106 ps
CPU time 1.17 seconds
Started Jul 22 04:44:52 PM PDT 24
Finished Jul 22 04:44:54 PM PDT 24
Peak memory 208636 kb
Host smart-8ed221f0-18fa-4a6b-bc4f-c3fcd0985d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343212072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.343212072
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.600245255
Short name T556
Test name
Test status
Simulation time 912368919 ps
CPU time 15.46 seconds
Started Jul 22 04:44:09 PM PDT 24
Finished Jul 22 04:44:25 PM PDT 24
Peak memory 218012 kb
Host smart-d2bf713c-9625-4852-8cc4-acc98f2b3e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600245255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.600245255
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3893060278
Short name T29
Test name
Test status
Simulation time 127818309 ps
CPU time 2.21 seconds
Started Jul 22 04:44:21 PM PDT 24
Finished Jul 22 04:44:24 PM PDT 24
Peak memory 216784 kb
Host smart-0631a2a1-be8d-4e56-a8cd-bc59db447635
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893060278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3893060278
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1952737577
Short name T653
Test name
Test status
Simulation time 2414134275 ps
CPU time 37.32 seconds
Started Jul 22 04:44:34 PM PDT 24
Finished Jul 22 04:45:12 PM PDT 24
Peak memory 218612 kb
Host smart-9749c831-5724-4105-837b-df1d0c78fa90
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952737577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1952737577
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3391073742
Short name T631
Test name
Test status
Simulation time 1431439198 ps
CPU time 10.02 seconds
Started Jul 22 04:44:21 PM PDT 24
Finished Jul 22 04:44:32 PM PDT 24
Peak memory 217452 kb
Host smart-0f483960-7d4a-4809-8e45-2a90d5914484
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391073742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
391073742
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3914021200
Short name T364
Test name
Test status
Simulation time 152685836 ps
CPU time 3.43 seconds
Started Jul 22 04:44:38 PM PDT 24
Finished Jul 22 04:44:42 PM PDT 24
Peak memory 221624 kb
Host smart-294c4826-272a-4bab-b148-7a5e6251a222
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914021200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.3914021200
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.28677545
Short name T598
Test name
Test status
Simulation time 18080889174 ps
CPU time 17.53 seconds
Started Jul 22 04:44:21 PM PDT 24
Finished Jul 22 04:44:39 PM PDT 24
Peak memory 217376 kb
Host smart-b640e446-ec0c-4af9-a496-0d05ecb3fde7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28677545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jt
ag_regwen_during_op.28677545
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3923380913
Short name T167
Test name
Test status
Simulation time 98946092 ps
CPU time 3.41 seconds
Started Jul 22 04:44:21 PM PDT 24
Finished Jul 22 04:44:25 PM PDT 24
Peak memory 217312 kb
Host smart-416c459a-b383-493e-92ae-88e13c6a20ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923380913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3923380913
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2218884412
Short name T656
Test name
Test status
Simulation time 4864313545 ps
CPU time 83.03 seconds
Started Jul 22 04:44:22 PM PDT 24
Finished Jul 22 04:45:45 PM PDT 24
Peak memory 283388 kb
Host smart-037250da-a0ce-4f65-b258-3347fed47021
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218884412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2218884412
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2993464750
Short name T673
Test name
Test status
Simulation time 4629234885 ps
CPU time 13.03 seconds
Started Jul 22 04:44:52 PM PDT 24
Finished Jul 22 04:45:06 PM PDT 24
Peak memory 223184 kb
Host smart-6c5cbfb3-a85e-4897-a365-684d134adf84
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993464750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2993464750
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1165681803
Short name T789
Test name
Test status
Simulation time 445144981 ps
CPU time 1.72 seconds
Started Jul 22 04:44:09 PM PDT 24
Finished Jul 22 04:44:11 PM PDT 24
Peak memory 221852 kb
Host smart-5f2e3d76-dbfa-4d5d-a031-c083890d16b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165681803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1165681803
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3002811883
Short name T767
Test name
Test status
Simulation time 1753254400 ps
CPU time 17.63 seconds
Started Jul 22 04:44:22 PM PDT 24
Finished Jul 22 04:44:41 PM PDT 24
Peak memory 217420 kb
Host smart-249b3b2f-aab4-414e-9afb-7e9c2f39f3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002811883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3002811883
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.3860958199
Short name T389
Test name
Test status
Simulation time 289737977 ps
CPU time 8.88 seconds
Started Jul 22 04:44:38 PM PDT 24
Finished Jul 22 04:44:48 PM PDT 24
Peak memory 218604 kb
Host smart-fbe2e1a3-d744-4a81-8025-011264e3c4d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860958199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3860958199
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1722007803
Short name T723
Test name
Test status
Simulation time 713040224 ps
CPU time 13.74 seconds
Started Jul 22 04:44:21 PM PDT 24
Finished Jul 22 04:44:36 PM PDT 24
Peak memory 217948 kb
Host smart-c6229771-e516-4cfa-ab1d-c40b5b6be362
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722007803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1722007803
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3497469762
Short name T685
Test name
Test status
Simulation time 3794823883 ps
CPU time 11.47 seconds
Started Jul 22 04:44:23 PM PDT 24
Finished Jul 22 04:44:35 PM PDT 24
Peak memory 225880 kb
Host smart-7bfb067b-de19-440c-b283-f1b61b559363
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497469762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
497469762
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3919181537
Short name T404
Test name
Test status
Simulation time 300275540 ps
CPU time 12.57 seconds
Started Jul 22 04:44:48 PM PDT 24
Finished Jul 22 04:45:01 PM PDT 24
Peak memory 218164 kb
Host smart-fc2f7c83-5d8c-40cd-b32e-5ed78a1f8c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919181537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3919181537
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3010578004
Short name T858
Test name
Test status
Simulation time 18193449 ps
CPU time 1.46 seconds
Started Jul 22 04:44:11 PM PDT 24
Finished Jul 22 04:44:13 PM PDT 24
Peak memory 222656 kb
Host smart-2173cdf3-99c5-4141-8b39-ea984813865a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010578004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3010578004
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2769794632
Short name T862
Test name
Test status
Simulation time 1044606760 ps
CPU time 17.08 seconds
Started Jul 22 04:44:13 PM PDT 24
Finished Jul 22 04:44:30 PM PDT 24
Peak memory 250680 kb
Host smart-53a94a19-cdf8-4b70-8831-80de6c2f7518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769794632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2769794632
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2796024612
Short name T753
Test name
Test status
Simulation time 73175048 ps
CPU time 2.8 seconds
Started Jul 22 04:44:12 PM PDT 24
Finished Jul 22 04:44:15 PM PDT 24
Peak memory 217968 kb
Host smart-c33d57a3-8f48-4ece-9f3f-928b67d7fcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796024612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2796024612
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3282278444
Short name T809
Test name
Test status
Simulation time 1106207908 ps
CPU time 30.72 seconds
Started Jul 22 04:44:32 PM PDT 24
Finished Jul 22 04:45:04 PM PDT 24
Peak memory 250364 kb
Host smart-35aa5e5f-cc69-4440-b6d9-ec3f7adc2cf7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282278444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3282278444
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.485481405
Short name T513
Test name
Test status
Simulation time 14106141 ps
CPU time 1.17 seconds
Started Jul 22 04:44:12 PM PDT 24
Finished Jul 22 04:44:14 PM PDT 24
Peak memory 211684 kb
Host smart-cdc8d4b0-a233-45d2-9e08-4709d9a910ef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485481405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.485481405
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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