Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110753290

1

T1

181285

T2

28775

T3

29485

auto[1]

1461395

1

T1

4312

T2

495

T10

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110739646

1

T1

182265

T2

28478

T3

29485

auto[1]

1475039

1

T1

3332

T2

792

T10

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8089947	1			T1	25511		T2	10548		T3	9142
auto[IdleSt]	20679857	1			T1	9634		T2	2185		T3	2837
auto[ClkMuxSt]	36375	1			T2	76		T3	99		T8	68
auto[CntIncrSt]	36049	1			T2	76		T3	99		T8	68
auto[CntProgSt]	1962492	1			T2	2053		T3	462		T8	2052
auto[TransCheckSt]	28174	1			T2	57		T3	99		T8	68
auto[TokenHashSt]	47085269	1			T2	1473		T3	973		T8	752
auto[FlashRmaSt]	36791	1			T2	58		T3	229		T10	32
auto[TokenCheck0St]	13400	1			T2	24		T3	38		T10	6
auto[TokenCheck1St]	9911	1			T2	12		T3	14		T10	6
auto[TransProgSt]	484148	1			T2	537		T10	38		T11	49
auto[PostTransSt]	12346372	1			T2	10521		T3	15493		T8	9966
auto[ScrapSt]	207585	1			T13	8		T5	553		T27	57
auto[EscalateSt]	7350468	1			T1	35471		T2	1650		T10	1307
auto[InvalidSt]	13845769	1			T1	114973		T10	1158		T38	2596

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2078	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	13845769	1			T1	114973		T10	1158		T38	2596
EscalateSt	7350468	1			T1	35471		T2	1650		T10	1307
ScrapSt	207585	1			T13	8		T5	553		T27	57
PostTransSt	12346372	1			T2	10521		T3	15493		T8	9966
TransProgSt	484148	1			T2	537		T10	38		T11	49
TokenCheck1St	9911	1			T2	12		T3	14		T10	6
TokenCheck0St	13400	1			T2	24		T3	38		T10	6
FlashRmaSt	36791	1			T2	58		T3	229		T10	32
TokenHashSt	47085269	1			T2	1473		T3	973		T8	752
TransCheckSt	28174	1			T2	57		T3	99		T8	68
CntProgSt	1962492	1			T2	2053		T3	462		T8	2052
CntIncrSt	36049	1			T2	76		T3	99		T8	68
ClkMuxSt	36375	1			T2	76		T3	99		T8	68
IdleSt	20679857	1			T1	9634		T2	2185		T3	2837
ResetSt	8089947	1			T1	25511		T2	10548		T3	9142
arcs[ResetSt=>IdleSt]	55899	1			T1	88		T2	77		T3	100
arcs[IdleSt=>ScrapSt]	328	1			T13	2		T5	1		T27	1
arcs[IdleSt=>ClkMuxSt]	36088	1			T2	76		T3	99		T8	68
arcs[ClkMuxSt=>CntIncrSt]	36049	1			T2	76		T3	99		T8	68
arcs[CntIncrSt=>PostTransSt]	1863	1			T2	6		T15	11		T34	1
arcs[CntIncrSt=>CntProgSt]	34110	1			T2	70		T3	99		T8	68
arcs[CntProgSt=>PostTransSt]	4908	1			T2	13		T38	24		T15	34
arcs[CntProgSt=>TransCheckSt]	28174	1			T2	57		T3	99		T8	68
arcs[TransCheckSt=>PostTransSt]	3749	1			T2	6		T3	52		T15	8
arcs[TransCheckSt=>TokenHashSt]	24318	1			T2	51		T3	47		T8	68
arcs[TokenHashSt=>PostTransSt]	9974	1			T2	27		T3	9		T8	68
arcs[TokenHashSt=>FlashRmaSt]	13436	1			T2	24		T3	38		T10	6
arcs[FlashRmaSt=>TokenCheck0St]	13400	1			T2	24		T3	38		T10	6
arcs[TokenCheck0St=>PostTransSt]	3430	1			T2	12		T3	24		T38	20
arcs[TokenCheck0St=>TokenCheck1St]	9911	1			T2	12		T3	14		T10	6
arcs[TokenCheck1St=>PostTransSt]	667	1			T3	14		T15	2		T57	11
arcs[TransProgSt=>PostTransSt]	8426	1			T2	12		T10	6		T11	18
arcs[IdleSt=>EscalateSt]	163	1			T11	7		T13	4		T49	5
arcs[ClkMuxSt=>EscalateSt]	39	1			T11	3		T13	1		T49	1
arcs[CntIncrSt=>EscalateSt]	76	1			T11	1		T49	1		T50	1
arcs[CntProgSt=>EscalateSt]	1028	1			T11	6		T13	28		T49	18
arcs[TransCheckSt=>EscalateSt]	107	1			T11	9		T53	4		T51	5
arcs[TokenHashSt=>EscalateSt]	908	1			T11	34		T13	4		T49	7
arcs[FlashRmaSt=>EscalateSt]	36	1			T49	2		T51	1		T52	1
arcs[TokenCheck0St=>EscalateSt]	59	1			T11	1		T13	2		T49	1
arcs[TokenCheck1St=>EscalateSt]	24	1			T11	4		T53	1		T52	1
arcs[TransProgSt=>EscalateSt]	794	1			T11	8		T13	14		T49	22
arcs[PostTransSt=>EscalateSt]	5330	1			T2	13		T11	18		T38	24
arcs[InvalidSt=>EscalateSt]	15049	1			T1	78		T10	5		T38	14

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8089783	1			T1	25511		T2	10548		T3	9142
auto[0]	auto[IdleSt]	20679749	1			T1	9634		T2	2185		T3	2837
auto[0]	auto[ClkMuxSt]	36346	1			T2	76		T3	99		T8	68
auto[0]	auto[CntIncrSt]	35997	1			T2	76		T3	99		T8	68
auto[0]	auto[CntProgSt]	1961808	1			T2	2053		T3	462		T8	2052
auto[0]	auto[TransCheckSt]	28094	1			T2	57		T3	99		T8	68
auto[0]	auto[TokenHashSt]	47084673	1			T2	1473		T3	973		T8	752
auto[0]	auto[FlashRmaSt]	36764	1			T2	58		T3	229		T10	32
auto[0]	auto[TokenCheck0St]	13361	1			T2	24		T3	38		T10	6
auto[0]	auto[TokenCheck1St]	9895	1			T2	12		T3	14		T10	6
auto[0]	auto[TransProgSt]	483634	1			T2	537		T10	38		T11	41
auto[0]	auto[PostTransSt]	12343665	1			T2	10516		T3	15493		T8	9966
auto[0]	auto[ScrapSt]	207547	1			T13	7		T5	553		T27	57
auto[0]	auto[EscalateSt]	5901616	1			T1	31203		T2	1160		T10	1111
auto[0]	auto[InvalidSt]	13838280	1			T1	114929		T10	1156		T38	2588
auto[1]	auto[ResetSt]	164	1			T11	5		T13	1		T49	3
auto[1]	auto[IdleSt]	108	1			T11	6		T13	3		T49	5
auto[1]	auto[ClkMuxSt]	29	1			T11	2		T13	1		T49	1
auto[1]	auto[CntIncrSt]	52	1			T11	1		T49	1		T50	1
auto[1]	auto[CntProgSt]	684	1			T11	6		T13	19		T49	8
auto[1]	auto[TransCheckSt]	80	1			T11	5		T53	1		T51	3
auto[1]	auto[TokenHashSt]	596	1			T11	20		T13	4		T49	5
auto[1]	auto[FlashRmaSt]	27	1			T49	2		T51	1		T52	1
auto[1]	auto[TokenCheck0St]	39	1			T11	1		T13	1		T50	2
auto[1]	auto[TokenCheck1St]	16	1			T11	2		T53	1		T52	1
auto[1]	auto[TransProgSt]	514	1			T11	8		T13	7		T49	15
auto[1]	auto[PostTransSt]	2707	1			T2	5		T11	12		T38	13
auto[1]	auto[ScrapSt]	38	1			T13	1		T50	1		T53	1
auto[1]	auto[EscalateSt]	1448852	1			T1	4268		T2	490		T10	196
auto[1]	auto[InvalidSt]	7489	1			T1	44		T10	2		T38	8

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8089774	1			T1	25511		T2	10548		T3	9142
auto[0]	auto[IdleSt]	20679740	1			T1	9634		T2	2185		T3	2837
auto[0]	auto[ClkMuxSt]	36352	1			T2	76		T3	99		T8	68
auto[0]	auto[CntIncrSt]	35999	1			T2	76		T3	99		T8	68
auto[0]	auto[CntProgSt]	1961801	1			T2	2053		T3	462		T8	2052
auto[0]	auto[TransCheckSt]	28107	1			T2	57		T3	99		T8	68
auto[0]	auto[TokenHashSt]	47084679	1			T2	1473		T3	973		T8	752
auto[0]	auto[FlashRmaSt]	36770	1			T2	58		T3	229		T10	32
auto[0]	auto[TokenCheck0St]	13363	1			T2	24		T3	38		T10	6
auto[0]	auto[TokenCheck1St]	9894	1			T2	12		T3	14		T10	6
auto[0]	auto[TransProgSt]	483607	1			T2	537		T10	38		T11	43
auto[0]	auto[PostTransSt]	12343624	1			T2	10513		T3	15493		T8	9966
auto[0]	auto[ScrapSt]	207547	1			T13	7		T5	553		T27	57
auto[0]	auto[EscalateSt]	5888102	1			T1	32173		T2	866		T10	1013
auto[0]	auto[InvalidSt]	13838209	1			T1	114939		T10	1155		T38	2590
auto[1]	auto[ResetSt]	173	1			T11	4		T13	2		T49	2
auto[1]	auto[IdleSt]	117	1			T11	3		T13	2		T49	5
auto[1]	auto[ClkMuxSt]	23	1			T11	3		T50	2		T53	1
auto[1]	auto[CntIncrSt]	50	1			T49	1		T50	1		T53	2
auto[1]	auto[CntProgSt]	691	1			T11	4		T13	17		T49	15
auto[1]	auto[TransCheckSt]	67	1			T11	7		T53	4		T51	3
auto[1]	auto[TokenHashSt]	590	1			T11	18		T13	3		T49	5
auto[1]	auto[FlashRmaSt]	21	1			T51	1		T229	2		T230	1
auto[1]	auto[TokenCheck0St]	37	1			T13	1		T49	1		T50	1
auto[1]	auto[TokenCheck1St]	17	1			T11	2		T53	1		T52	1
auto[1]	auto[TransProgSt]	541	1			T11	6		T13	10		T49	15
auto[1]	auto[PostTransSt]	2748	1			T2	8		T11	13		T38	11
auto[1]	auto[ScrapSt]	38	1			T13	1		T50	1		T169	4
auto[1]	auto[EscalateSt]	1462366	1			T1	3298		T2	784		T10	294
auto[1]	auto[InvalidSt]	7560	1			T1	34		T10	3		T38	6