Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104423553

1

T1

1264

T2

28995

T3

21872

auto[1]

1437157

1

T2

3267

T3

1485

T4

8048

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104438958

1

T1

1264

T2

29094

T3

22268

auto[1]

1421752

1

T2

3168

T3

1089

T4

9407

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7624127	1			T1	96		T2	9834		T3	5631
auto[IdleSt]	21937308	1			T1	204		T2	1330		T3	2214
auto[ClkMuxSt]	36014	1			T1	1		T3	48		T4	45
auto[CntIncrSt]	35728	1			T1	1		T3	48		T4	45
auto[CntProgSt]	1862141	1			T1	16		T3	3565		T4	5576
auto[TransCheckSt]	27911	1			T1	1		T3	32		T4	26
auto[TokenHashSt]	42184278	1			T1	39		T3	340		T4	600
auto[FlashRmaSt]	37857	1			T1	1		T3	134		T4	33
auto[TokenCheck0St]	13288	1			T1	1		T3	28		T4	17
auto[TokenCheck1St]	9949	1			T1	1		T3	21		T4	15
auto[TransProgSt]	498790	1			T1	14		T3	1301		T4	159
auto[PostTransSt]	12998371	1			T1	889		T3	6020		T4	4
auto[ScrapSt]	262334	1			T4	8		T12	9		T35	4
auto[EscalateSt]	6814720	1			T2	9249		T3	3137		T4	12364
auto[InvalidSt]	11515832	1			T2	11839		T3	838		T7	5425

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2062	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11515832	1			T2	11839		T3	838		T7	5425
EscalateSt	6814720	1			T2	9249		T3	3137		T4	12364
ScrapSt	262334	1			T4	8		T12	9		T35	4
PostTransSt	12998371	1			T1	889		T3	6020		T4	4
TransProgSt	498790	1			T1	14		T3	1301		T4	159
TokenCheck1St	9949	1			T1	1		T3	21		T4	15
TokenCheck0St	13288	1			T1	1		T3	28		T4	17
FlashRmaSt	37857	1			T1	1		T3	134		T4	33
TokenHashSt	42184278	1			T1	39		T3	340		T4	600
TransCheckSt	27911	1			T1	1		T3	32		T4	26
CntProgSt	1862141	1			T1	16		T3	3565		T4	5576
CntIncrSt	35728	1			T1	1		T3	48		T4	45
ClkMuxSt	36014	1			T1	1		T3	48		T4	45
IdleSt	21937308	1			T1	204		T2	1330		T3	2214
ResetSt	7624127	1			T1	96		T2	9834		T3	5631
arcs[ResetSt=>IdleSt]	55442	1			T1	1		T2	78		T3	59
arcs[IdleSt=>ScrapSt]	313	1			T4	2		T12	1		T35	1
arcs[IdleSt=>ClkMuxSt]	35766	1			T1	1		T3	48		T4	45
arcs[ClkMuxSt=>CntIncrSt]	35728	1			T1	1		T3	48		T4	45
arcs[CntIncrSt=>PostTransSt]	1864	1			T17	9		T18	11		T19	13
arcs[CntIncrSt=>CntProgSt]	33798	1			T1	1		T3	48		T4	44
arcs[CntProgSt=>PostTransSt]	4917	1			T3	16		T13	13		T6	15
arcs[CntProgSt=>TransCheckSt]	27911	1			T1	1		T3	32		T4	26
arcs[TransCheckSt=>PostTransSt]	3540	1			T48	37		T17	6		T18	14
arcs[TransCheckSt=>TokenHashSt]	24243	1			T1	1		T3	32		T4	26
arcs[TokenHashSt=>PostTransSt]	10147	1			T3	4		T10	83		T14	53
arcs[TokenHashSt=>FlashRmaSt]	13316	1			T1	1		T3	28		T4	17
arcs[FlashRmaSt=>TokenCheck0St]	13288	1			T1	1		T3	28		T4	17
arcs[TokenCheck0St=>PostTransSt]	3270	1			T3	7		T48	16		T17	8
arcs[TokenCheck0St=>TokenCheck1St]	9949	1			T1	1		T3	21		T4	15
arcs[TokenCheck1St=>PostTransSt]	632	1			T3	2		T48	4		T17	1
arcs[TransProgSt=>PostTransSt]	8507	1			T1	1		T3	19		T4	1
arcs[IdleSt=>EscalateSt]	163	1			T4	2		T35	5		T49	9
arcs[ClkMuxSt=>EscalateSt]	38	1			T35	2		T49	1		T50	1
arcs[CntIncrSt=>EscalateSt]	66	1			T4	1		T35	1		T36	2
arcs[CntProgSt=>EscalateSt]	970	1			T4	18		T35	23		T36	5
arcs[TransCheckSt=>EscalateSt]	128	1			T36	4		T55	3		T56	2
arcs[TokenHashSt=>EscalateSt]	780	1			T4	9		T35	5		T36	40
arcs[FlashRmaSt=>EscalateSt]	28	1			T35	1		T51	2		T50	1
arcs[TokenCheck0St=>EscalateSt]	69	1			T4	2		T35	1		T36	1
arcs[TokenCheck1St=>EscalateSt]	42	1			T4	1		T55	3		T56	1
arcs[TransProgSt=>EscalateSt]	768	1			T4	13		T35	26		T36	5
arcs[PostTransSt=>EscalateSt]	5287	1			T3	16		T4	1		T13	13
arcs[InvalidSt=>EscalateSt]	14786	1			T2	65		T3	10		T7	2

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7623970	1			T1	96		T2	9834		T3	5631
auto[0]	auto[IdleSt]	21937191	1			T1	204		T2	1330		T3	2214
auto[0]	auto[ClkMuxSt]	35988	1			T1	1		T3	48		T4	45
auto[0]	auto[CntIncrSt]	35680	1			T1	1		T3	48		T4	45
auto[0]	auto[CntProgSt]	1861483	1			T1	16		T3	3565		T4	5565
auto[0]	auto[TransCheckSt]	27835	1			T1	1		T3	32		T4	26
auto[0]	auto[TokenHashSt]	42183736	1			T1	39		T3	340		T4	593
auto[0]	auto[FlashRmaSt]	37841	1			T1	1		T3	134		T4	33
auto[0]	auto[TokenCheck0St]	13241	1			T1	1		T3	28		T4	17
auto[0]	auto[TokenCheck1St]	9921	1			T1	1		T3	21		T4	14
auto[0]	auto[TransProgSt]	498286	1			T1	14		T3	1301		T4	149
auto[0]	auto[PostTransSt]	12995659	1			T1	889		T3	6010		T4	4
auto[0]	auto[ScrapSt]	262299	1			T4	6		T12	9		T35	4
auto[0]	auto[EscalateSt]	5389920	1			T2	6015		T3	1667		T4	4353
auto[0]	auto[InvalidSt]	11508441	1			T2	11806		T3	833		T7	5424
auto[1]	auto[ResetSt]	157	1			T4	5		T35	2		T36	4
auto[1]	auto[IdleSt]	117	1			T4	1		T35	4		T49	7
auto[1]	auto[ClkMuxSt]	26	1			T35	1		T49	1		T231	1
auto[1]	auto[CntIncrSt]	48	1			T35	1		T36	2		T55	1
auto[1]	auto[CntProgSt]	658	1			T4	11		T35	18		T36	4
auto[1]	auto[TransCheckSt]	76	1			T36	3		T55	2		T232	5
auto[1]	auto[TokenHashSt]	542	1			T4	7		T35	3		T36	24
auto[1]	auto[FlashRmaSt]	16	1			T51	2		T50	1		T233	1
auto[1]	auto[TokenCheck0St]	47	1			T35	1		T36	1		T55	1
auto[1]	auto[TokenCheck1St]	28	1			T4	1		T55	1		T56	1
auto[1]	auto[TransProgSt]	504	1			T4	10		T35	13		T36	4
auto[1]	auto[PostTransSt]	2712	1			T3	10		T13	6		T6	6
auto[1]	auto[ScrapSt]	35	1			T4	2		T36	1		T55	1
auto[1]	auto[EscalateSt]	1424800	1			T2	3234		T3	1470		T4	8011
auto[1]	auto[InvalidSt]	7391	1			T2	33		T3	5		T7	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7623982	1			T1	96		T2	9834		T3	5631
auto[0]	auto[IdleSt]	21937207	1			T1	204		T2	1330		T3	2214
auto[0]	auto[ClkMuxSt]	35987	1			T1	1		T3	48		T4	45
auto[0]	auto[CntIncrSt]	35685	1			T1	1		T3	48		T4	44
auto[0]	auto[CntProgSt]	1861507	1			T1	16		T3	3565		T4	5560
auto[0]	auto[TransCheckSt]	27822	1			T1	1		T3	32		T4	26
auto[0]	auto[TokenHashSt]	42183771	1			T1	39		T3	340		T4	593
auto[0]	auto[FlashRmaSt]	37838	1			T1	1		T3	134		T4	33
auto[0]	auto[TokenCheck0St]	13242	1			T1	1		T3	28		T4	15
auto[0]	auto[TokenCheck1St]	9923	1			T1	1		T3	21		T4	15
auto[0]	auto[TransProgSt]	498278	1			T1	14		T3	1301		T4	151
auto[0]	auto[PostTransSt]	12995685	1			T1	889		T3	6014		T4	3
auto[0]	auto[ScrapSt]	262297	1			T4	8		T12	9		T35	3
auto[0]	auto[EscalateSt]	5405235	1			T2	6113		T3	2059		T4	2998
auto[0]	auto[InvalidSt]	11508437	1			T2	11807		T3	833		T7	5424
auto[1]	auto[ResetSt]	145	1			T4	4		T35	1		T36	1
auto[1]	auto[IdleSt]	101	1			T4	2		T35	3		T49	5
auto[1]	auto[ClkMuxSt]	27	1			T35	1		T49	1		T50	1
auto[1]	auto[CntIncrSt]	43	1			T4	1		T35	1		T36	1
auto[1]	auto[CntProgSt]	634	1			T4	16		T35	14		T36	3
auto[1]	auto[TransCheckSt]	89	1			T36	2		T55	3		T56	2
auto[1]	auto[TokenHashSt]	507	1			T4	7		T35	4		T36	32
auto[1]	auto[FlashRmaSt]	19	1			T35	1		T51	2		T50	1
auto[1]	auto[TokenCheck0St]	46	1			T4	2		T49	1		T56	2
auto[1]	auto[TokenCheck1St]	26	1			T55	3		T56	1		T51	1
auto[1]	auto[TransProgSt]	512	1			T4	8		T35	19		T36	5
auto[1]	auto[PostTransSt]	2686	1			T3	6		T4	1		T13	7
auto[1]	auto[ScrapSt]	37	1			T35	1		T55	1		T49	1
auto[1]	auto[EscalateSt]	1409485	1			T2	3136		T3	1078		T4	9366
auto[1]	auto[InvalidSt]	7395	1			T2	32		T3	5		T7	1