Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109008644

1

T1

29359

T2

3525

T3

18656

auto[1]

1440354

1

T1

3960

T2

198

T3

9247

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109005371

1

T1

30250

T2

3525

T3

18543

auto[1]

1443627

1

T1

3069

T2

198

T3

9360

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7474178	1			T1	8854		T2	1006		T3	7574
auto[IdleSt]	21203896	1			T1	1313		T2	730		T3	5184
auto[ClkMuxSt]	36570	1			T2	5		T3	60		T11	89
auto[CntIncrSt]	36413	1			T2	5		T3	58		T11	89
auto[CntProgSt]	1434922	1			T2	10		T3	853		T11	1749
auto[TransCheckSt]	28354	1			T2	5		T3	35		T11	71
auto[TokenHashSt]	47972071	1			T2	56		T3	314		T11	1270
auto[FlashRmaSt]	36081	1			T2	5		T3	96		T11	24
auto[TokenCheck0St]	13231	1			T2	5		T3	24		T11	23
auto[TokenCheck1St]	9857	1			T2	5		T3	23		T11	15
auto[TransProgSt]	340764	1			T2	10		T3	85		T11	485
auto[PostTransSt]	12959566	1			T2	853		T3	10		T11	16150
auto[ScrapSt]	177592	1			T3	8		T15	4		T50	4
auto[EscalateSt]	6952948	1			T1	10120		T2	733		T3	13579
auto[InvalidSt]	11770482	1			T1	13022		T2	294		T16	310

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2073	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11770482	1			T1	13022		T2	294		T16	310
EscalateSt	6952948	1			T1	10120		T2	733		T3	13579
ScrapSt	177592	1			T3	8		T15	4		T50	4
PostTransSt	12959566	1			T2	853		T3	10		T11	16150
TransProgSt	340764	1			T2	10		T3	85		T11	485
TokenCheck1St	9857	1			T2	5		T3	23		T11	15
TokenCheck0St	13231	1			T2	5		T3	24		T11	23
FlashRmaSt	36081	1			T2	5		T3	96		T11	24
TokenHashSt	47972071	1			T2	56		T3	314		T11	1270
TransCheckSt	28354	1			T2	5		T3	35		T11	71
CntProgSt	1434922	1			T2	10		T3	853		T11	1749
CntIncrSt	36413	1			T2	5		T3	58		T11	89
ClkMuxSt	36570	1			T2	5		T3	60		T11	89
IdleSt	21203896	1			T1	1313		T2	730		T3	5184
ResetSt	7474178	1			T1	8854		T2	1006		T3	7574
arcs[ResetSt=>IdleSt]	55967	1			T1	78		T2	10		T3	69
arcs[IdleSt=>ScrapSt]	300	1			T3	2		T15	1		T50	1
arcs[IdleSt=>ClkMuxSt]	36452	1			T2	5		T3	60		T11	89
arcs[ClkMuxSt=>CntIncrSt]	36413	1			T2	5		T3	58		T11	89
arcs[CntIncrSt=>PostTransSt]	1844	1			T11	8		T34	15		T43	10
arcs[CntIncrSt=>CntProgSt]	34506	1			T2	5		T3	57		T11	81
arcs[CntProgSt=>PostTransSt]	5110	1			T11	10		T12	9		T5	5
arcs[CntProgSt=>TransCheckSt]	28354	1			T2	5		T3	35		T11	71
arcs[TransCheckSt=>PostTransSt]	3836	1			T11	14		T14	37		T33	33
arcs[TransCheckSt=>TokenHashSt]	24410	1			T2	5		T3	34		T11	57
arcs[TokenHashSt=>PostTransSt]	10390	1			T11	34		T14	11		T21	11
arcs[TokenHashSt=>FlashRmaSt]	13277	1			T2	5		T3	25		T11	23
arcs[FlashRmaSt=>TokenCheck0St]	13231	1			T2	5		T3	24		T11	23
arcs[TokenCheck0St=>PostTransSt]	3304	1			T11	8		T14	21		T21	16
arcs[TokenCheck0St=>TokenCheck1St]	9857	1			T2	5		T3	23		T11	15
arcs[TokenCheck1St=>PostTransSt]	636	1			T14	11		T33	7		T34	2
arcs[TransProgSt=>PostTransSt]	8365	1			T2	5		T3	3		T11	15
arcs[IdleSt=>EscalateSt]	172	1			T3	6		T15	9		T50	4
arcs[ClkMuxSt=>EscalateSt]	39	1			T3	2		T15	1		T50	1
arcs[CntIncrSt=>EscalateSt]	63	1			T3	1		T15	1		T50	3
arcs[CntProgSt=>EscalateSt]	1042	1			T3	22		T15	25		T50	21
arcs[TransCheckSt=>EscalateSt]	108	1			T3	1		T15	3		T50	1
arcs[TokenHashSt=>EscalateSt]	743	1			T3	9		T15	8		T50	11
arcs[FlashRmaSt=>EscalateSt]	46	1			T3	1		T15	2		T50	1
arcs[TokenCheck0St=>EscalateSt]	70	1			T3	1		T15	3		T50	1
arcs[TokenCheck1St=>EscalateSt]	31	1			T50	2		T63	1		T64	1
arcs[TransProgSt=>EscalateSt]	825	1			T3	20		T15	18		T50	18
arcs[PostTransSt=>EscalateSt]	5423	1			T3	3		T11	10		T12	9
arcs[InvalidSt=>EscalateSt]	14777	1			T1	71		T2	4		T16	4

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7474001	1			T1	8854		T2	1006		T3	7572
auto[0]	auto[IdleSt]	21203783	1			T1	1313		T2	730		T3	5180
auto[0]	auto[ClkMuxSt]	36544	1			T2	5		T3	59		T11	89
auto[0]	auto[CntIncrSt]	36369	1			T2	5		T3	57		T11	89
auto[0]	auto[CntProgSt]	1434227	1			T2	10		T3	838		T11	1749
auto[0]	auto[TransCheckSt]	28281	1			T2	5		T3	34		T11	71
auto[0]	auto[TokenHashSt]	47971582	1			T2	56		T3	307		T11	1270
auto[0]	auto[FlashRmaSt]	36053	1			T2	5		T3	95		T11	24
auto[0]	auto[TokenCheck0St]	13182	1			T2	5		T3	23		T11	23
auto[0]	auto[TokenCheck1St]	9840	1			T2	5		T3	23		T11	15
auto[0]	auto[TransProgSt]	340209	1			T2	10		T3	72		T11	485
auto[0]	auto[PostTransSt]	12956817	1			T2	853		T3	8		T11	16146
auto[0]	auto[ScrapSt]	177550	1			T3	7		T15	3		T50	3
auto[0]	auto[EscalateSt]	5525004	1			T1	6200		T2	537		T3	4381
auto[0]	auto[InvalidSt]	11763129	1			T1	12982		T2	292		T16	307
auto[1]	auto[ResetSt]	177	1			T3	2		T15	2		T50	6
auto[1]	auto[IdleSt]	113	1			T3	4		T15	5		T50	3
auto[1]	auto[ClkMuxSt]	26	1			T3	1		T15	1		T50	1
auto[1]	auto[CntIncrSt]	44	1			T3	1		T50	2		T94	1
auto[1]	auto[CntProgSt]	695	1			T3	15		T15	16		T50	11
auto[1]	auto[TransCheckSt]	73	1			T3	1		T15	1		T50	1
auto[1]	auto[TokenHashSt]	489	1			T3	7		T15	6		T50	8
auto[1]	auto[FlashRmaSt]	28	1			T3	1		T15	1		T63	2
auto[1]	auto[TokenCheck0St]	49	1			T3	1		T15	3		T63	1
auto[1]	auto[TokenCheck1St]	17	1			T50	2		T64	1		T234	1
auto[1]	auto[TransProgSt]	555	1			T3	13		T15	13		T50	11
auto[1]	auto[PostTransSt]	2749	1			T3	2		T11	4		T12	5
auto[1]	auto[ScrapSt]	42	1			T3	1		T15	1		T50	1
auto[1]	auto[EscalateSt]	1427944	1			T1	3920		T2	196		T3	9198
auto[1]	auto[InvalidSt]	7353	1			T1	40		T2	2		T16	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7474022	1			T1	8854		T2	1006		T3	7572
auto[0]	auto[IdleSt]	21203779	1			T1	1313		T2	730		T3	5180
auto[0]	auto[ClkMuxSt]	36541	1			T2	5		T3	58		T11	89
auto[0]	auto[CntIncrSt]	36372	1			T2	5		T3	57		T11	89
auto[0]	auto[CntProgSt]	1434223	1			T2	10		T3	838		T11	1749
auto[0]	auto[TransCheckSt]	28289	1			T2	5		T3	34		T11	71
auto[0]	auto[TokenHashSt]	47971583	1			T2	56		T3	308		T11	1270
auto[0]	auto[FlashRmaSt]	36050	1			T2	5		T3	96		T11	24
auto[0]	auto[TokenCheck0St]	13192	1			T2	5		T3	24		T11	23
auto[0]	auto[TokenCheck1St]	9833	1			T2	5		T3	23		T11	15
auto[0]	auto[TransProgSt]	340212	1			T2	10		T3	70		T11	485
auto[0]	auto[PostTransSt]	12956777	1			T2	853		T3	8		T11	16144
auto[0]	auto[ScrapSt]	177547	1			T3	7		T15	4		T50	3
auto[0]	auto[EscalateSt]	5521820	1			T1	7082		T2	537		T3	4268
auto[0]	auto[InvalidSt]	11763058	1			T1	12991		T2	292		T16	309
auto[1]	auto[ResetSt]	156	1			T3	2		T15	1		T50	4
auto[1]	auto[IdleSt]	117	1			T3	4		T15	6		T50	2
auto[1]	auto[ClkMuxSt]	29	1			T3	2		T15	1		T50	1
auto[1]	auto[CntIncrSt]	41	1			T3	1		T15	1		T50	1
auto[1]	auto[CntProgSt]	699	1			T3	15		T15	21		T50	14
auto[1]	auto[TransCheckSt]	65	1			T3	1		T15	3		T50	1
auto[1]	auto[TokenHashSt]	488	1			T3	6		T15	3		T50	8
auto[1]	auto[FlashRmaSt]	31	1			T15	1		T50	1		T63	1
auto[1]	auto[TokenCheck0St]	39	1			T15	1		T50	1		T63	1
auto[1]	auto[TokenCheck1St]	24	1			T50	1		T63	1		T64	1
auto[1]	auto[TransProgSt]	552	1			T3	15		T15	12		T50	10
auto[1]	auto[PostTransSt]	2789	1			T3	2		T11	6		T12	4
auto[1]	auto[ScrapSt]	45	1			T3	1		T50	1		T94	1
auto[1]	auto[EscalateSt]	1431128	1			T1	3038		T2	196		T3	9311
auto[1]	auto[InvalidSt]	7424	1			T1	31		T2	2		T16	1