Summary for Variable clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57252 | 
1 | 
 | 
 | 
T1 | 
70 | 
 | 
T2 | 
13 | 
 | 
T4 | 
249 | 
| auto[1] | 
2189 | 
1 | 
 | 
 | 
T1 | 
9 | 
 | 
T4 | 
6 | 
 | 
T12 | 
14 | 
Summary for Variable clk_byp_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
58686 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T2 | 
13 | 
 | 
T4 | 
255 | 
| auto[1] | 
755 | 
1 | 
 | 
 | 
T37 | 
11 | 
 | 
T50 | 
16 | 
 | 
T69 | 
11 | 
Summary for Variable count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57323 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T2 | 
12 | 
 | 
T4 | 
242 | 
| auto[1] | 
2118 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T4 | 
13 | 
 | 
T9 | 
5 | 
Summary for Variable count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57298 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T2 | 
12 | 
 | 
T4 | 
227 | 
| auto[1] | 
2143 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T4 | 
28 | 
 | 
T9 | 
11 | 
Summary for Variable count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57330 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T2 | 
11 | 
 | 
T4 | 
235 | 
| auto[1] | 
2111 | 
1 | 
 | 
 | 
T2 | 
2 | 
 | 
T4 | 
20 | 
 | 
T9 | 
4 | 
Summary for Variable err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
2 | 
0 | 
2 | 
100.00 | 
User Defined Bins for err_inj_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| err_inj | 
53870 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T2 | 
8 | 
 | 
T4 | 
227 | 
| no_err_inj | 
5571 | 
1 | 
 | 
 | 
T2 | 
5 | 
 | 
T4 | 
28 | 
 | 
T11 | 
9 | 
Summary for Variable flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57299 | 
1 | 
 | 
 | 
T1 | 
65 | 
 | 
T2 | 
13 | 
 | 
T4 | 
254 | 
| auto[1] | 
2142 | 
1 | 
 | 
 | 
T1 | 
14 | 
 | 
T4 | 
1 | 
 | 
T12 | 
12 | 
Summary for Variable flash_rma_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
58701 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T2 | 
13 | 
 | 
T4 | 
255 | 
| auto[1] | 
740 | 
1 | 
 | 
 | 
T37 | 
10 | 
 | 
T50 | 
22 | 
 | 
T69 | 
8 | 
Summary for Variable jtag_csr_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for jtag_csr_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
40304 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T4 | 
173 | 
 | 
T9 | 
64 | 
| auto[1] | 
19137 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T4 | 
82 | 
 | 
T5 | 
61 | 
Summary for Variable kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57340 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T2 | 
13 | 
 | 
T4 | 
237 | 
| auto[1] | 
2101 | 
1 | 
 | 
 | 
T4 | 
18 | 
 | 
T9 | 
6 | 
 | 
T5 | 
5 | 
Summary for Variable lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57268 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T2 | 
11 | 
 | 
T4 | 
233 | 
| auto[1] | 
2173 | 
1 | 
 | 
 | 
T2 | 
2 | 
 | 
T4 | 
22 | 
 | 
T9 | 
10 | 
Summary for Variable otp_lc_data_i_valid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57400 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T2 | 
12 | 
 | 
T4 | 
236 | 
| auto[1] | 
2041 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T4 | 
19 | 
 | 
T9 | 
7 | 
Summary for Variable otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_partition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57337 | 
1 | 
 | 
 | 
T1 | 
65 | 
 | 
T2 | 
13 | 
 | 
T4 | 
246 | 
| auto[1] | 
2104 | 
1 | 
 | 
 | 
T1 | 
14 | 
 | 
T4 | 
9 | 
 | 
T12 | 
15 | 
Summary for Variable otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_prog_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56820 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T2 | 
13 | 
 | 
T4 | 
255 | 
| auto[1] | 
2621 | 
1 | 
 | 
 | 
T10 | 
13 | 
 | 
T13 | 
3 | 
 | 
T18 | 
17 | 
Summary for Variable otp_rma_token_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
58688 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T2 | 
13 | 
 | 
T4 | 
255 | 
| auto[1] | 
753 | 
1 | 
 | 
 | 
T37 | 
10 | 
 | 
T50 | 
14 | 
 | 
T69 | 
22 | 
Summary for Variable otp_secrets_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
58729 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T2 | 
13 | 
 | 
T4 | 
255 | 
| auto[1] | 
712 | 
1 | 
 | 
 | 
T37 | 
10 | 
 | 
T50 | 
20 | 
 | 
T69 | 
14 | 
Summary for Variable otp_test_tokens_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
58716 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T2 | 
13 | 
 | 
T4 | 
255 | 
| auto[1] | 
725 | 
1 | 
 | 
 | 
T37 | 
11 | 
 | 
T50 | 
11 | 
 | 
T69 | 
11 | 
Summary for Variable post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for post_trans_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56387 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T4 | 
255 | 
 | 
T9 | 
64 | 
| auto[1] | 
3054 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T34 | 
10 | 
 | 
T18 | 
10 | 
Summary for Variable security_escalation_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for security_escalation_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
55649 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T2 | 
13 | 
 | 
T4 | 
255 | 
| auto[1] | 
3792 | 
1 | 
 | 
 | 
T45 | 
89 | 
 | 
T33 | 
94 | 
 | 
T57 | 
68 | 
Summary for Variable state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57347 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T2 | 
12 | 
 | 
T4 | 
239 | 
| auto[1] | 
2094 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T4 | 
16 | 
 | 
T9 | 
6 | 
Summary for Variable state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57261 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T2 | 
13 | 
 | 
T4 | 
241 | 
| auto[1] | 
2180 | 
1 | 
 | 
 | 
T4 | 
14 | 
 | 
T9 | 
10 | 
 | 
T5 | 
4 | 
Summary for Variable state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57246 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T2 | 
13 | 
 | 
T4 | 
232 | 
| auto[1] | 
2195 | 
1 | 
 | 
 | 
T4 | 
23 | 
 | 
T9 | 
5 | 
 | 
T5 | 
6 | 
Summary for Variable token_invalid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_invalid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57299 | 
1 | 
 | 
 | 
T1 | 
72 | 
 | 
T2 | 
13 | 
 | 
T4 | 
246 | 
| auto[1] | 
2142 | 
1 | 
 | 
 | 
T1 | 
7 | 
 | 
T4 | 
9 | 
 | 
T12 | 
7 | 
Summary for Variable token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mismatch_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53488 | 
1 | 
 | 
 | 
T1 | 
72 | 
 | 
T2 | 
13 | 
 | 
T4 | 
248 | 
| auto[1] | 
5953 | 
1 | 
 | 
 | 
T1 | 
7 | 
 | 
T4 | 
7 | 
 | 
T12 | 
13 | 
Summary for Variable token_mux_ctrl_redun_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
55609 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T2 | 
13 | 
 | 
T4 | 
255 | 
| auto[1] | 
3832 | 
1 | 
 | 
 | 
T44 | 
68 | 
 | 
T40 | 
69 | 
 | 
T68 | 
88 | 
Summary for Variable token_mux_digest_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
1 | 
1 | 
50.00  | 
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS | 
| [auto[1]] | 
0 | 
1 | 
1 | 
 | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
59441 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T2 | 
13 | 
 | 
T4 | 
255 | 
Summary for Variable token_response_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_response_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57361 | 
1 | 
 | 
 | 
T1 | 
69 | 
 | 
T2 | 
13 | 
 | 
T4 | 
249 | 
| auto[1] | 
2080 | 
1 | 
 | 
 | 
T1 | 
10 | 
 | 
T4 | 
6 | 
 | 
T12 | 
20 | 
Summary for Variable transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57366 | 
1 | 
 | 
 | 
T1 | 
70 | 
 | 
T2 | 
13 | 
 | 
T4 | 
246 | 
| auto[1] | 
2075 | 
1 | 
 | 
 | 
T1 | 
9 | 
 | 
T4 | 
9 | 
 | 
T12 | 
11 | 
Summary for Variable transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57342 | 
1 | 
 | 
 | 
T1 | 
70 | 
 | 
T2 | 
13 | 
 | 
T4 | 
248 | 
| auto[1] | 
2099 | 
1 | 
 | 
 | 
T1 | 
9 | 
 | 
T4 | 
7 | 
 | 
T12 | 
7 | 
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
| post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
err_inj | 
52353 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T4 | 
227 | 
 | 
T9 | 
64 | 
| auto[0] | 
no_err_inj | 
4034 | 
1 | 
 | 
 | 
T4 | 
28 | 
 | 
T11 | 
9 | 
 | 
T46 | 
15 | 
| auto[1] | 
err_inj | 
1517 | 
1 | 
 | 
 | 
T2 | 
8 | 
 | 
T34 | 
9 | 
 | 
T18 | 
6 | 
| auto[1] | 
no_err_inj | 
1537 | 
1 | 
 | 
 | 
T2 | 
5 | 
 | 
T34 | 
1 | 
 | 
T18 | 
4 | 
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
| post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
54390 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T4 | 
241 | 
 | 
T9 | 
54 | 
| auto[0] | 
auto[1] | 
1997 | 
1 | 
 | 
 | 
T4 | 
14 | 
 | 
T9 | 
10 | 
 | 
T5 | 
4 | 
| auto[1] | 
auto[0] | 
2871 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T34 | 
8 | 
 | 
T18 | 
9 | 
| auto[1] | 
auto[1] | 
183 | 
1 | 
 | 
 | 
T34 | 
2 | 
 | 
T18 | 
1 | 
 | 
T202 | 
3 | 
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
| post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
54393 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T4 | 
233 | 
 | 
T9 | 
54 | 
| auto[0] | 
auto[1] | 
1994 | 
1 | 
 | 
 | 
T4 | 
22 | 
 | 
T9 | 
10 | 
 | 
T5 | 
7 | 
| auto[1] | 
auto[0] | 
2875 | 
1 | 
 | 
 | 
T2 | 
11 | 
 | 
T34 | 
9 | 
 | 
T18 | 
10 | 
| auto[1] | 
auto[1] | 
179 | 
1 | 
 | 
 | 
T2 | 
2 | 
 | 
T34 | 
1 | 
 | 
T21 | 
1 | 
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
| post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
54360 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T4 | 
232 | 
 | 
T9 | 
59 | 
| auto[0] | 
auto[1] | 
2027 | 
1 | 
 | 
 | 
T4 | 
23 | 
 | 
T9 | 
5 | 
 | 
T5 | 
6 | 
| auto[1] | 
auto[0] | 
2886 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T34 | 
8 | 
 | 
T18 | 
9 | 
| auto[1] | 
auto[1] | 
168 | 
1 | 
 | 
 | 
T34 | 
2 | 
 | 
T18 | 
1 | 
 | 
T21 | 
1 | 
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
| post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
54424 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T4 | 
227 | 
 | 
T9 | 
53 | 
| auto[0] | 
auto[1] | 
1963 | 
1 | 
 | 
 | 
T4 | 
28 | 
 | 
T9 | 
11 | 
 | 
T5 | 
8 | 
| auto[1] | 
auto[0] | 
2874 | 
1 | 
 | 
 | 
T2 | 
12 | 
 | 
T34 | 
9 | 
 | 
T18 | 
9 | 
| auto[1] | 
auto[1] | 
180 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T34 | 
1 | 
 | 
T18 | 
1 | 
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
| post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
54440 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T4 | 
235 | 
 | 
T9 | 
60 | 
| auto[0] | 
auto[1] | 
1947 | 
1 | 
 | 
 | 
T4 | 
20 | 
 | 
T9 | 
4 | 
 | 
T5 | 
7 | 
| auto[1] | 
auto[0] | 
2890 | 
1 | 
 | 
 | 
T2 | 
11 | 
 | 
T34 | 
9 | 
 | 
T18 | 
10 | 
| auto[1] | 
auto[1] | 
164 | 
1 | 
 | 
 | 
T2 | 
2 | 
 | 
T34 | 
1 | 
 | 
T202 | 
1 | 
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
| post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
54428 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T4 | 
242 | 
 | 
T9 | 
59 | 
| auto[0] | 
auto[1] | 
1959 | 
1 | 
 | 
 | 
T4 | 
13 | 
 | 
T9 | 
5 | 
 | 
T5 | 
9 | 
| auto[1] | 
auto[0] | 
2895 | 
1 | 
 | 
 | 
T2 | 
12 | 
 | 
T34 | 
9 | 
 | 
T18 | 
8 | 
| auto[1] | 
auto[1] | 
159 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T34 | 
1 | 
 | 
T18 | 
2 | 
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
| jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
39076 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T4 | 
173 | 
 | 
T9 | 
64 | 
| auto[0] | 
auto[1] | 
1228 | 
1 | 
 | 
 | 
T12 | 
14 | 
 | 
T61 | 
8 | 
 | 
T43 | 
16 | 
| auto[1] | 
auto[0] | 
18176 | 
1 | 
 | 
 | 
T1 | 
70 | 
 | 
T4 | 
76 | 
 | 
T5 | 
61 | 
| auto[1] | 
auto[1] | 
961 | 
1 | 
 | 
 | 
T1 | 
9 | 
 | 
T4 | 
6 | 
 | 
T20 | 
10 | 
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
| jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
39069 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T4 | 
173 | 
 | 
T9 | 
64 | 
| auto[0] | 
auto[1] | 
1235 | 
1 | 
 | 
 | 
T12 | 
12 | 
 | 
T61 | 
8 | 
 | 
T43 | 
19 | 
| auto[1] | 
auto[0] | 
18230 | 
1 | 
 | 
 | 
T1 | 
65 | 
 | 
T4 | 
81 | 
 | 
T5 | 
61 | 
| auto[1] | 
auto[1] | 
907 | 
1 | 
 | 
 | 
T1 | 
14 | 
 | 
T4 | 
1 | 
 | 
T20 | 
6 | 
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
| jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38777 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T4 | 
173 | 
 | 
T9 | 
64 | 
| auto[0] | 
auto[1] | 
1527 | 
1 | 
 | 
 | 
T10 | 
13 | 
 | 
T13 | 
3 | 
 | 
T18 | 
6 | 
| auto[1] | 
auto[0] | 
18043 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T4 | 
82 | 
 | 
T5 | 
61 | 
| auto[1] | 
auto[1] | 
1094 | 
1 | 
 | 
 | 
T18 | 
11 | 
 | 
T43 | 
7 | 
 | 
T41 | 
23 | 
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
| jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
39154 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T4 | 
173 | 
 | 
T9 | 
64 | 
| auto[0] | 
auto[1] | 
1150 | 
1 | 
 | 
 | 
T12 | 
15 | 
 | 
T61 | 
14 | 
 | 
T43 | 
10 | 
| auto[1] | 
auto[0] | 
18183 | 
1 | 
 | 
 | 
T1 | 
65 | 
 | 
T4 | 
73 | 
 | 
T5 | 
61 | 
| auto[1] | 
auto[1] | 
954 | 
1 | 
 | 
 | 
T1 | 
14 | 
 | 
T4 | 
9 | 
 | 
T20 | 
12 | 
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
| jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
35258 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T4 | 
173 | 
 | 
T9 | 
64 | 
| auto[0] | 
auto[1] | 
5046 | 
1 | 
 | 
 | 
T12 | 
13 | 
 | 
T15 | 
66 | 
 | 
T61 | 
10 | 
| auto[1] | 
auto[0] | 
18230 | 
1 | 
 | 
 | 
T1 | 
72 | 
 | 
T4 | 
75 | 
 | 
T5 | 
61 | 
| auto[1] | 
auto[1] | 
907 | 
1 | 
 | 
 | 
T1 | 
7 | 
 | 
T4 | 
7 | 
 | 
T20 | 
9 | 
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
| jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
39027 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T4 | 
159 | 
 | 
T9 | 
54 | 
| auto[0] | 
auto[1] | 
1277 | 
1 | 
 | 
 | 
T4 | 
14 | 
 | 
T9 | 
10 | 
 | 
T29 | 
8 | 
| auto[1] | 
auto[0] | 
18234 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T4 | 
82 | 
 | 
T5 | 
57 | 
| auto[1] | 
auto[1] | 
903 | 
1 | 
 | 
 | 
T5 | 
4 | 
 | 
T16 | 
9 | 
 | 
T43 | 
31 | 
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
| jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
39093 | 
1 | 
 | 
 | 
T2 | 
12 | 
 | 
T4 | 
157 | 
 | 
T9 | 
58 | 
| auto[0] | 
auto[1] | 
1211 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T4 | 
16 | 
 | 
T9 | 
6 | 
| auto[1] | 
auto[0] | 
18254 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T4 | 
82 | 
 | 
T5 | 
54 | 
| auto[1] | 
auto[1] | 
883 | 
1 | 
 | 
 | 
T5 | 
7 | 
 | 
T16 | 
7 | 
 | 
T43 | 
30 | 
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
39065 | 
1 | 
 | 
 | 
T2 | 
11 | 
 | 
T4 | 
151 | 
 | 
T9 | 
54 | 
| auto[0] | 
auto[1] | 
1239 | 
1 | 
 | 
 | 
T2 | 
2 | 
 | 
T4 | 
22 | 
 | 
T9 | 
10 | 
| auto[1] | 
auto[0] | 
18203 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T4 | 
82 | 
 | 
T5 | 
54 | 
| auto[1] | 
auto[1] | 
934 | 
1 | 
 | 
 | 
T5 | 
7 | 
 | 
T16 | 
14 | 
 | 
T43 | 
37 | 
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
39083 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T4 | 
155 | 
 | 
T9 | 
58 | 
| auto[0] | 
auto[1] | 
1221 | 
1 | 
 | 
 | 
T4 | 
18 | 
 | 
T9 | 
6 | 
 | 
T29 | 
14 | 
| auto[1] | 
auto[0] | 
18257 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T4 | 
82 | 
 | 
T5 | 
56 | 
| auto[1] | 
auto[1] | 
880 | 
1 | 
 | 
 | 
T5 | 
5 | 
 | 
T16 | 
15 | 
 | 
T43 | 
24 | 
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
| jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
39082 | 
1 | 
 | 
 | 
T2 | 
12 | 
 | 
T4 | 
145 | 
 | 
T9 | 
53 | 
| auto[0] | 
auto[1] | 
1222 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T4 | 
28 | 
 | 
T9 | 
11 | 
| auto[1] | 
auto[0] | 
18216 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T4 | 
82 | 
 | 
T5 | 
53 | 
| auto[1] | 
auto[1] | 
921 | 
1 | 
 | 
 | 
T5 | 
8 | 
 | 
T16 | 
12 | 
 | 
T43 | 
25 | 
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
| jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
39089 | 
1 | 
 | 
 | 
T2 | 
12 | 
 | 
T4 | 
160 | 
 | 
T9 | 
59 | 
| auto[0] | 
auto[1] | 
1215 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T4 | 
13 | 
 | 
T9 | 
5 | 
| auto[1] | 
auto[0] | 
18234 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T4 | 
82 | 
 | 
T5 | 
52 | 
| auto[1] | 
auto[1] | 
903 | 
1 | 
 | 
 | 
T5 | 
9 | 
 | 
T16 | 
9 | 
 | 
T43 | 
23 | 
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
| jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
39179 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T4 | 
173 | 
 | 
T9 | 
64 | 
| auto[0] | 
auto[1] | 
1125 | 
1 | 
 | 
 | 
T12 | 
7 | 
 | 
T61 | 
7 | 
 | 
T43 | 
11 | 
| auto[1] | 
auto[0] | 
18163 | 
1 | 
 | 
 | 
T1 | 
70 | 
 | 
T4 | 
75 | 
 | 
T5 | 
61 | 
| auto[1] | 
auto[1] | 
974 | 
1 | 
 | 
 | 
T1 | 
9 | 
 | 
T4 | 
7 | 
 | 
T20 | 
10 | 
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
| jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
39157 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T4 | 
173 | 
 | 
T9 | 
64 | 
| auto[0] | 
auto[1] | 
1147 | 
1 | 
 | 
 | 
T12 | 
11 | 
 | 
T61 | 
17 | 
 | 
T43 | 
19 | 
| auto[1] | 
auto[0] | 
18209 | 
1 | 
 | 
 | 
T1 | 
70 | 
 | 
T4 | 
73 | 
 | 
T5 | 
61 | 
| auto[1] | 
auto[1] | 
928 | 
1 | 
 | 
 | 
T1 | 
9 | 
 | 
T4 | 
9 | 
 | 
T20 | 
7 | 
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
| jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38547 | 
1 | 
 | 
 | 
T4 | 
173 | 
 | 
T9 | 
64 | 
 | 
T10 | 
13 | 
| auto[0] | 
auto[1] | 
1757 | 
1 | 
 | 
 | 
T2 | 
13 | 
 | 
T34 | 
10 | 
 | 
T18 | 
10 | 
| auto[1] | 
auto[0] | 
17840 | 
1 | 
 | 
 | 
T1 | 
79 | 
 | 
T4 | 
82 | 
 | 
T5 | 
61 | 
| auto[1] | 
auto[1] | 
1297 | 
1 | 
 | 
 | 
T43 | 
31 | 
 | 
T154 | 
10 | 
 | 
T93 | 
25 |