Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110980018

1

T1

286970

T2

7882

T3

641

auto[1]

1509495

1

T1

594

T2

396

T4

6831

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110958412

1

T1

287267

T2

7981

T3

641

auto[1]

1531101

1

T1

297

T2

297

T4

6732

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7589548	1			T1	7347		T2	1667		T3	79
auto[IdleSt]	24117099	1			T1	146016		T2	1225		T3	562
auto[ClkMuxSt]	39228	1			T1	79		T2	5		T4	81
auto[CntIncrSt]	38976	1			T1	79		T2	5		T4	81
auto[CntProgSt]	1509165	1			T1	2827		T2	78		T4	138
auto[TransCheckSt]	30325	1			T1	61		T2	5		T4	66
auto[TokenHashSt]	44344096	1			T1	4651		T2	54		T4	645686
auto[FlashRmaSt]	39150	1			T1	42		T2	20		T4	125
auto[TokenCheck0St]	14126	1			T1	28		T2	5		T4	37
auto[TokenCheck1St]	10462	1			T1	14		T2	5		T4	36
auto[TransProgSt]	383899	1			T1	693		T2	146		T4	72
auto[PostTransSt]	15058978	1			T1	119471		T2	1595		T4	47759
auto[ScrapSt]	251445	1			T4	282		T11	38		T45	8
auto[EscalateSt]	7309408	1			T1	6256		T2	2024		T4	20678
auto[InvalidSt]	11751353	1			T2	1442		T4	24359		T9	3960

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2255	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11751353	1			T2	1442		T4	24359		T9	3960
EscalateSt	7309408	1			T1	6256		T2	2024		T4	20678
ScrapSt	251445	1			T4	282		T11	38		T45	8
PostTransSt	15058978	1			T1	119471		T2	1595		T4	47759
TransProgSt	383899	1			T1	693		T2	146		T4	72
TokenCheck1St	10462	1			T1	14		T2	5		T4	36
TokenCheck0St	14126	1			T1	28		T2	5		T4	37
FlashRmaSt	39150	1			T1	42		T2	20		T4	125
TokenHashSt	44344096	1			T1	4651		T2	54		T4	645686
TransCheckSt	30325	1			T1	61		T2	5		T4	66
CntProgSt	1509165	1			T1	2827		T2	78		T4	138
CntIncrSt	38976	1			T1	79		T2	5		T4	81
ClkMuxSt	39228	1			T1	79		T2	5		T4	81
IdleSt	24117099	1			T1	146016		T2	1225		T3	562
ResetSt	7589548	1			T1	7347		T2	1667		T3	79
arcs[ResetSt=>IdleSt]	59727	1			T1	80		T2	13		T3	1
arcs[IdleSt=>ScrapSt]	329	1			T4	1		T11	1		T45	2
arcs[IdleSt=>ClkMuxSt]	39008	1			T1	79		T2	5		T4	81
arcs[ClkMuxSt=>CntIncrSt]	38976	1			T1	79		T2	5		T4	81
arcs[CntIncrSt=>PostTransSt]	2077	1			T1	9		T4	9		T12	11
arcs[CntIncrSt=>CntProgSt]	36828	1			T1	70		T2	5		T4	72
arcs[CntProgSt=>PostTransSt]	5513	1			T1	9		T4	6		T10	13
arcs[CntProgSt=>TransCheckSt]	30325	1			T1	61		T2	5		T4	66
arcs[TransCheckSt=>PostTransSt]	3988	1			T1	9		T4	7		T12	7
arcs[TransCheckSt=>TokenHashSt]	26216	1			T1	52		T2	5		T4	59
arcs[TokenHashSt=>PostTransSt]	11160	1			T1	24		T4	22		T12	40
arcs[TokenHashSt=>FlashRmaSt]	14181	1			T1	28		T2	5		T4	37
arcs[FlashRmaSt=>TokenCheck0St]	14126	1			T1	28		T2	5		T4	37
arcs[TokenCheck0St=>PostTransSt]	3611	1			T1	14		T4	1		T12	12
arcs[TokenCheck0St=>TokenCheck1St]	10462	1			T1	14		T2	5		T4	36
arcs[TokenCheck1St=>PostTransSt]	713	1			T44	6		T40	8		T61	1
arcs[TransProgSt=>PostTransSt]	8935	1			T1	14		T2	5		T4	36
arcs[IdleSt=>EscalateSt]	144	1			T45	8		T33	5		T56	9
arcs[ClkMuxSt=>EscalateSt]	32	1			T45	1		T33	1		T56	4
arcs[CntIncrSt=>EscalateSt]	71	1			T33	2		T57	2		T56	1
arcs[CntProgSt=>EscalateSt]	990	1			T45	30		T33	5		T57	27
arcs[TransCheckSt=>EscalateSt]	121	1			T33	9		T57	1		T62	1
arcs[TokenHashSt=>EscalateSt]	875	1			T45	12		T33	33		T57	13
arcs[FlashRmaSt=>EscalateSt]	55	1			T45	1		T33	1		T56	1
arcs[TokenCheck0St=>EscalateSt]	53	1			T45	1		T57	4		T56	2
arcs[TokenCheck1St=>EscalateSt]	35	1			T33	3		T57	1		T56	1
arcs[TransProgSt=>EscalateSt]	779	1			T45	22		T33	8		T57	14
arcs[PostTransSt=>EscalateSt]	5892	1			T1	9		T4	6		T10	13
arcs[InvalidSt=>EscalateSt]	15644	1			T2	7		T4	131		T9	52

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7589385	1			T1	7347		T2	1667		T3	79
auto[0]	auto[IdleSt]	24117007	1			T1	146016		T2	1225		T3	562
auto[0]	auto[ClkMuxSt]	39207	1			T1	79		T2	5		T4	81
auto[0]	auto[CntIncrSt]	38927	1			T1	79		T2	5		T4	81
auto[0]	auto[CntProgSt]	1508500	1			T1	2827		T2	78		T4	138
auto[0]	auto[TransCheckSt]	30240	1			T1	61		T2	5		T4	66
auto[0]	auto[TokenHashSt]	44343535	1			T1	4651		T2	54		T4	645686
auto[0]	auto[FlashRmaSt]	39114	1			T1	42		T2	20		T4	125
auto[0]	auto[TokenCheck0St]	14089	1			T1	28		T2	5		T4	37
auto[0]	auto[TokenCheck1St]	10438	1			T1	14		T2	5		T4	36
auto[0]	auto[TransProgSt]	383381	1			T1	693		T2	146		T4	72
auto[0]	auto[PostTransSt]	15056025	1			T1	119465		T2	1595		T4	47756
auto[0]	auto[ScrapSt]	251404	1			T4	282		T11	38		T45	8
auto[0]	auto[EscalateSt]	5812999	1			T1	5668		T2	1632		T4	13916
auto[0]	auto[InvalidSt]	11743512	1			T2	1438		T4	24293		T9	3938
auto[1]	auto[ResetSt]	163	1			T45	6		T33	4		T57	1
auto[1]	auto[IdleSt]	92	1			T45	7		T33	4		T56	3
auto[1]	auto[ClkMuxSt]	21	1			T45	1		T56	3		T58	3
auto[1]	auto[CntIncrSt]	49	1			T33	2		T57	2		T56	1
auto[1]	auto[CntProgSt]	665	1			T45	19		T33	2		T57	19
auto[1]	auto[TransCheckSt]	85	1			T33	7		T57	1		T62	1
auto[1]	auto[TokenHashSt]	561	1			T45	5		T33	17		T57	10
auto[1]	auto[FlashRmaSt]	36	1			T45	1		T33	1		T56	1
auto[1]	auto[TokenCheck0St]	37	1			T45	1		T57	3		T56	1
auto[1]	auto[TokenCheck1St]	24	1			T33	3		T57	1		T236	1
auto[1]	auto[TransProgSt]	518	1			T45	16		T33	4		T57	11
auto[1]	auto[PostTransSt]	2953	1			T1	6		T4	3		T10	3
auto[1]	auto[ScrapSt]	41	1			T56	2		T58	1		T236	1
auto[1]	auto[EscalateSt]	1496409	1			T1	588		T2	392		T4	6762
auto[1]	auto[InvalidSt]	7841	1			T2	4		T4	66		T9	22

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7589379	1			T1	7347		T2	1667		T3	79
auto[0]	auto[IdleSt]	24117005	1			T1	146016		T2	1225		T3	562
auto[0]	auto[ClkMuxSt]	39204	1			T1	79		T2	5		T4	81
auto[0]	auto[CntIncrSt]	38935	1			T1	79		T2	5		T4	81
auto[0]	auto[CntProgSt]	1508488	1			T1	2827		T2	78		T4	138
auto[0]	auto[TransCheckSt]	30242	1			T1	61		T2	5		T4	66
auto[0]	auto[TokenHashSt]	44343509	1			T1	4651		T2	54		T4	645686
auto[0]	auto[FlashRmaSt]	39113	1			T1	42		T2	20		T4	125
auto[0]	auto[TokenCheck0St]	14089	1			T1	28		T2	5		T4	37
auto[0]	auto[TokenCheck1St]	10437	1			T1	14		T2	5		T4	36
auto[0]	auto[TransProgSt]	383367	1			T1	693		T2	146		T4	72
auto[0]	auto[PostTransSt]	15055920	1			T1	119468		T2	1595		T4	47756
auto[0]	auto[ScrapSt]	251402	1			T4	282		T11	38		T45	6
auto[0]	auto[EscalateSt]	5791517	1			T1	5962		T2	1730		T4	14014
auto[0]	auto[InvalidSt]	11743550	1			T2	1439		T4	24294		T9	3930
auto[1]	auto[ResetSt]	169	1			T45	8		T33	3		T57	5
auto[1]	auto[IdleSt]	94	1			T45	3		T33	3		T56	8
auto[1]	auto[ClkMuxSt]	24	1			T45	1		T33	1		T56	3
auto[1]	auto[CntIncrSt]	41	1			T33	1		T58	1		T62	2
auto[1]	auto[CntProgSt]	677	1			T45	21		T33	4		T57	20
auto[1]	auto[TransCheckSt]	83	1			T33	7		T62	1		T237	2
auto[1]	auto[TokenHashSt]	587	1			T45	9		T33	25		T57	7
auto[1]	auto[FlashRmaSt]	37	1			T33	1		T238	1		T236	2
auto[1]	auto[TokenCheck0St]	37	1			T45	1		T57	4		T56	2
auto[1]	auto[TokenCheck1St]	25	1			T33	1		T56	1		T237	1
auto[1]	auto[TransProgSt]	532	1			T45	14		T33	6		T57	9
auto[1]	auto[PostTransSt]	3058	1			T1	3		T4	3		T10	10
auto[1]	auto[ScrapSt]	43	1			T45	2		T56	1		T58	1
auto[1]	auto[EscalateSt]	1517891	1			T1	294		T2	294		T4	6664
auto[1]	auto[InvalidSt]	7803	1			T2	3		T4	65		T9	30