Summary for Variable clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57483 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
1943 | 
1 | 
 | 
 | 
T10 | 
10 | 
 | 
T15 | 
8 | 
 | 
T31 | 
5 | 
Summary for Variable clk_byp_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
58712 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
714 | 
1 | 
 | 
 | 
T14 | 
10 | 
 | 
T68 | 
21 | 
 | 
T69 | 
12 | 
Summary for Variable count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57148 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
2278 | 
1 | 
 | 
 | 
T13 | 
10 | 
 | 
T38 | 
11 | 
 | 
T96 | 
9 | 
Summary for Variable count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57095 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
2331 | 
1 | 
 | 
 | 
T13 | 
10 | 
 | 
T38 | 
7 | 
 | 
T9 | 
1 | 
Summary for Variable count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57029 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
2397 | 
1 | 
 | 
 | 
T13 | 
11 | 
 | 
T38 | 
6 | 
 | 
T96 | 
7 | 
Summary for Variable err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
2 | 
0 | 
2 | 
100.00 | 
User Defined Bins for err_inj_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| err_inj | 
53759 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| no_err_inj | 
5667 | 
1 | 
 | 
 | 
T5 | 
2 | 
 | 
T11 | 
7 | 
 | 
T9 | 
10 | 
Summary for Variable flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57554 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
1872 | 
1 | 
 | 
 | 
T10 | 
6 | 
 | 
T15 | 
9 | 
 | 
T31 | 
4 | 
Summary for Variable flash_rma_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
58702 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
724 | 
1 | 
 | 
 | 
T14 | 
18 | 
 | 
T68 | 
17 | 
 | 
T69 | 
13 | 
Summary for Variable jtag_csr_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for jtag_csr_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39391 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
20035 | 
1 | 
 | 
 | 
T5 | 
2 | 
 | 
T6 | 
4 | 
 | 
T9 | 
15 | 
Summary for Variable kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57167 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
2259 | 
1 | 
 | 
 | 
T13 | 
10 | 
 | 
T38 | 
9 | 
 | 
T9 | 
1 | 
Summary for Variable lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57149 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
2277 | 
1 | 
 | 
 | 
T13 | 
3 | 
 | 
T38 | 
4 | 
 | 
T9 | 
1 | 
Summary for Variable otp_lc_data_i_valid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57221 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
2205 | 
1 | 
 | 
 | 
T13 | 
5 | 
 | 
T38 | 
8 | 
 | 
T9 | 
1 | 
Summary for Variable otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_partition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57455 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
1971 | 
1 | 
 | 
 | 
T10 | 
14 | 
 | 
T15 | 
5 | 
 | 
T31 | 
8 | 
Summary for Variable otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_prog_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56814 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T10 | 
73 | 
 | 
T5 | 
2 | 
| auto[1] | 
2612 | 
1 | 
 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
 | 
T6 | 
4 | 
Summary for Variable otp_rma_token_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
58650 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
776 | 
1 | 
 | 
 | 
T14 | 
12 | 
 | 
T68 | 
14 | 
 | 
T69 | 
11 | 
Summary for Variable otp_secrets_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
58694 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
732 | 
1 | 
 | 
 | 
T14 | 
7 | 
 | 
T68 | 
21 | 
 | 
T69 | 
15 | 
Summary for Variable otp_test_tokens_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
58635 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
791 | 
1 | 
 | 
 | 
T14 | 
12 | 
 | 
T68 | 
14 | 
 | 
T69 | 
19 | 
Summary for Variable post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for post_trans_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56145 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
3281 | 
1 | 
 | 
 | 
T9 | 
15 | 
 | 
T18 | 
25 | 
 | 
T19 | 
13 | 
Summary for Variable security_escalation_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for security_escalation_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
55618 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
3808 | 
1 | 
 | 
 | 
T53 | 
74 | 
 | 
T33 | 
72 | 
 | 
T55 | 
84 | 
Summary for Variable state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57114 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
2312 | 
1 | 
 | 
 | 
T13 | 
8 | 
 | 
T38 | 
16 | 
 | 
T96 | 
6 | 
Summary for Variable state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57139 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
2287 | 
1 | 
 | 
 | 
T13 | 
7 | 
 | 
T38 | 
7 | 
 | 
T9 | 
1 | 
Summary for Variable state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57069 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
2357 | 
1 | 
 | 
 | 
T13 | 
9 | 
 | 
T38 | 
11 | 
 | 
T96 | 
6 | 
Summary for Variable token_invalid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_invalid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57422 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
2004 | 
1 | 
 | 
 | 
T10 | 
9 | 
 | 
T15 | 
9 | 
 | 
T31 | 
12 | 
Summary for Variable token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mismatch_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53815 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
5611 | 
1 | 
 | 
 | 
T10 | 
10 | 
 | 
T15 | 
5 | 
 | 
T20 | 
56 | 
Summary for Variable token_mux_ctrl_redun_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
55805 | 
1 | 
 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
 | 
T10 | 
73 | 
| auto[1] | 
3621 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T12 | 
81 | 
 | 
T67 | 
71 | 
Summary for Variable token_mux_digest_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
1 | 
1 | 
50.00  | 
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS | 
| [auto[1]] | 
0 | 
1 | 
1 | 
 | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
59426 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
Summary for Variable token_response_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_response_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57520 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
1906 | 
1 | 
 | 
 | 
T10 | 
6 | 
 | 
T15 | 
8 | 
 | 
T31 | 
9 | 
Summary for Variable transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57479 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
1947 | 
1 | 
 | 
 | 
T10 | 
10 | 
 | 
T15 | 
7 | 
 | 
T31 | 
6 | 
Summary for Variable transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57402 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[1] | 
2024 | 
1 | 
 | 
 | 
T10 | 
8 | 
 | 
T15 | 
5 | 
 | 
T31 | 
7 | 
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
| post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
err_inj | 
52118 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
no_err_inj | 
4027 | 
1 | 
 | 
 | 
T5 | 
2 | 
 | 
T11 | 
7 | 
 | 
T16 | 
5 | 
| auto[1] | 
err_inj | 
1641 | 
1 | 
 | 
 | 
T9 | 
5 | 
 | 
T18 | 
15 | 
 | 
T19 | 
6 | 
| auto[1] | 
no_err_inj | 
1640 | 
1 | 
 | 
 | 
T9 | 
10 | 
 | 
T18 | 
10 | 
 | 
T19 | 
7 | 
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
| post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
54044 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
auto[1] | 
2101 | 
1 | 
 | 
 | 
T13 | 
7 | 
 | 
T38 | 
7 | 
 | 
T96 | 
5 | 
| auto[1] | 
auto[0] | 
3095 | 
1 | 
 | 
 | 
T9 | 
14 | 
 | 
T18 | 
20 | 
 | 
T19 | 
13 | 
| auto[1] | 
auto[1] | 
186 | 
1 | 
 | 
 | 
T9 | 
1 | 
 | 
T18 | 
5 | 
 | 
T213 | 
2 | 
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
| post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
54040 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
auto[1] | 
2105 | 
1 | 
 | 
 | 
T13 | 
3 | 
 | 
T38 | 
4 | 
 | 
T96 | 
4 | 
| auto[1] | 
auto[0] | 
3109 | 
1 | 
 | 
 | 
T9 | 
14 | 
 | 
T18 | 
21 | 
 | 
T19 | 
12 | 
| auto[1] | 
auto[1] | 
172 | 
1 | 
 | 
 | 
T9 | 
1 | 
 | 
T18 | 
4 | 
 | 
T19 | 
1 | 
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
| post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
53965 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
auto[1] | 
2180 | 
1 | 
 | 
 | 
T13 | 
9 | 
 | 
T38 | 
11 | 
 | 
T96 | 
6 | 
| auto[1] | 
auto[0] | 
3104 | 
1 | 
 | 
 | 
T9 | 
15 | 
 | 
T18 | 
24 | 
 | 
T19 | 
13 | 
| auto[1] | 
auto[1] | 
177 | 
1 | 
 | 
 | 
T18 | 
1 | 
 | 
T214 | 
2 | 
 | 
T215 | 
1 | 
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
| post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
54023 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
auto[1] | 
2122 | 
1 | 
 | 
 | 
T13 | 
10 | 
 | 
T38 | 
7 | 
 | 
T96 | 
6 | 
| auto[1] | 
auto[0] | 
3072 | 
1 | 
 | 
 | 
T9 | 
14 | 
 | 
T18 | 
25 | 
 | 
T19 | 
12 | 
| auto[1] | 
auto[1] | 
209 | 
1 | 
 | 
 | 
T9 | 
1 | 
 | 
T19 | 
1 | 
 | 
T216 | 
1 | 
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
| post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
53924 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
auto[1] | 
2221 | 
1 | 
 | 
 | 
T13 | 
11 | 
 | 
T38 | 
6 | 
 | 
T96 | 
7 | 
| auto[1] | 
auto[0] | 
3105 | 
1 | 
 | 
 | 
T9 | 
15 | 
 | 
T18 | 
24 | 
 | 
T19 | 
12 | 
| auto[1] | 
auto[1] | 
176 | 
1 | 
 | 
 | 
T18 | 
1 | 
 | 
T19 | 
1 | 
 | 
T216 | 
1 | 
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
| post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
54041 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
auto[1] | 
2104 | 
1 | 
 | 
 | 
T13 | 
10 | 
 | 
T38 | 
11 | 
 | 
T96 | 
9 | 
| auto[1] | 
auto[0] | 
3107 | 
1 | 
 | 
 | 
T9 | 
15 | 
 | 
T18 | 
24 | 
 | 
T19 | 
12 | 
| auto[1] | 
auto[1] | 
174 | 
1 | 
 | 
 | 
T18 | 
1 | 
 | 
T19 | 
1 | 
 | 
T216 | 
1 | 
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
| jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38306 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
auto[1] | 
1085 | 
1 | 
 | 
 | 
T10 | 
10 | 
 | 
T15 | 
8 | 
 | 
T31 | 
5 | 
| auto[1] | 
auto[0] | 
19177 | 
1 | 
 | 
 | 
T5 | 
2 | 
 | 
T6 | 
4 | 
 | 
T9 | 
15 | 
| auto[1] | 
auto[1] | 
858 | 
1 | 
 | 
 | 
T98 | 
7 | 
 | 
T99 | 
13 | 
 | 
T34 | 
9 | 
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
| jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38334 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
auto[1] | 
1057 | 
1 | 
 | 
 | 
T10 | 
6 | 
 | 
T15 | 
9 | 
 | 
T31 | 
4 | 
| auto[1] | 
auto[0] | 
19220 | 
1 | 
 | 
 | 
T5 | 
2 | 
 | 
T6 | 
4 | 
 | 
T9 | 
15 | 
| auto[1] | 
auto[1] | 
815 | 
1 | 
 | 
 | 
T98 | 
5 | 
 | 
T99 | 
6 | 
 | 
T34 | 
15 | 
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
| jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37983 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T10 | 
73 | 
 | 
T11 | 
7 | 
| auto[0] | 
auto[1] | 
1408 | 
1 | 
 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
 | 
T72 | 
15 | 
| auto[1] | 
auto[0] | 
18831 | 
1 | 
 | 
 | 
T5 | 
2 | 
 | 
T9 | 
15 | 
 | 
T16 | 
5 | 
| auto[1] | 
auto[1] | 
1204 | 
1 | 
 | 
 | 
T6 | 
4 | 
 | 
T18 | 
17 | 
 | 
T98 | 
20 | 
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
| jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38300 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
auto[1] | 
1091 | 
1 | 
 | 
 | 
T10 | 
14 | 
 | 
T15 | 
5 | 
 | 
T31 | 
8 | 
| auto[1] | 
auto[0] | 
19155 | 
1 | 
 | 
 | 
T5 | 
2 | 
 | 
T6 | 
4 | 
 | 
T9 | 
15 | 
| auto[1] | 
auto[1] | 
880 | 
1 | 
 | 
 | 
T98 | 
16 | 
 | 
T99 | 
8 | 
 | 
T34 | 
8 | 
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
| jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
34663 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
auto[1] | 
4728 | 
1 | 
 | 
 | 
T10 | 
10 | 
 | 
T15 | 
5 | 
 | 
T20 | 
56 | 
| auto[1] | 
auto[0] | 
19152 | 
1 | 
 | 
 | 
T5 | 
2 | 
 | 
T6 | 
4 | 
 | 
T9 | 
15 | 
| auto[1] | 
auto[1] | 
883 | 
1 | 
 | 
 | 
T98 | 
3 | 
 | 
T99 | 
6 | 
 | 
T34 | 
15 | 
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
| jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38160 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
auto[1] | 
1231 | 
1 | 
 | 
 | 
T13 | 
7 | 
 | 
T38 | 
7 | 
 | 
T96 | 
5 | 
| auto[1] | 
auto[0] | 
18979 | 
1 | 
 | 
 | 
T5 | 
2 | 
 | 
T6 | 
4 | 
 | 
T9 | 
14 | 
| auto[1] | 
auto[1] | 
1056 | 
1 | 
 | 
 | 
T9 | 
1 | 
 | 
T112 | 
9 | 
 | 
T98 | 
8 | 
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
| jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38140 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
auto[1] | 
1251 | 
1 | 
 | 
 | 
T13 | 
8 | 
 | 
T38 | 
16 | 
 | 
T96 | 
6 | 
| auto[1] | 
auto[0] | 
18974 | 
1 | 
 | 
 | 
T5 | 
2 | 
 | 
T6 | 
4 | 
 | 
T9 | 
15 | 
| auto[1] | 
auto[1] | 
1061 | 
1 | 
 | 
 | 
T112 | 
11 | 
 | 
T98 | 
9 | 
 | 
T34 | 
1 | 
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38163 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
auto[1] | 
1228 | 
1 | 
 | 
 | 
T13 | 
3 | 
 | 
T38 | 
4 | 
 | 
T96 | 
4 | 
| auto[1] | 
auto[0] | 
18986 | 
1 | 
 | 
 | 
T5 | 
2 | 
 | 
T6 | 
4 | 
 | 
T9 | 
14 | 
| auto[1] | 
auto[1] | 
1049 | 
1 | 
 | 
 | 
T9 | 
1 | 
 | 
T19 | 
1 | 
 | 
T112 | 
12 | 
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38151 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
auto[1] | 
1240 | 
1 | 
 | 
 | 
T13 | 
10 | 
 | 
T38 | 
9 | 
 | 
T96 | 
6 | 
| auto[1] | 
auto[0] | 
19016 | 
1 | 
 | 
 | 
T5 | 
2 | 
 | 
T6 | 
4 | 
 | 
T9 | 
14 | 
| auto[1] | 
auto[1] | 
1019 | 
1 | 
 | 
 | 
T9 | 
1 | 
 | 
T19 | 
1 | 
 | 
T112 | 
6 | 
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
| jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38103 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
auto[1] | 
1288 | 
1 | 
 | 
 | 
T13 | 
10 | 
 | 
T38 | 
7 | 
 | 
T96 | 
6 | 
| auto[1] | 
auto[0] | 
18992 | 
1 | 
 | 
 | 
T5 | 
2 | 
 | 
T6 | 
4 | 
 | 
T9 | 
14 | 
| auto[1] | 
auto[1] | 
1043 | 
1 | 
 | 
 | 
T9 | 
1 | 
 | 
T19 | 
1 | 
 | 
T112 | 
9 | 
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
| jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38129 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
auto[1] | 
1262 | 
1 | 
 | 
 | 
T13 | 
10 | 
 | 
T38 | 
11 | 
 | 
T96 | 
9 | 
| auto[1] | 
auto[0] | 
19019 | 
1 | 
 | 
 | 
T5 | 
2 | 
 | 
T6 | 
4 | 
 | 
T9 | 
15 | 
| auto[1] | 
auto[1] | 
1016 | 
1 | 
 | 
 | 
T19 | 
1 | 
 | 
T112 | 
6 | 
 | 
T98 | 
6 | 
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
| jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38276 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
auto[1] | 
1115 | 
1 | 
 | 
 | 
T10 | 
8 | 
 | 
T15 | 
5 | 
 | 
T31 | 
7 | 
| auto[1] | 
auto[0] | 
19126 | 
1 | 
 | 
 | 
T5 | 
2 | 
 | 
T6 | 
4 | 
 | 
T9 | 
15 | 
| auto[1] | 
auto[1] | 
909 | 
1 | 
 | 
 | 
T98 | 
10 | 
 | 
T99 | 
8 | 
 | 
T34 | 
9 | 
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
| jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38322 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
auto[1] | 
1069 | 
1 | 
 | 
 | 
T10 | 
10 | 
 | 
T15 | 
7 | 
 | 
T31 | 
6 | 
| auto[1] | 
auto[0] | 
19157 | 
1 | 
 | 
 | 
T5 | 
2 | 
 | 
T6 | 
4 | 
 | 
T9 | 
15 | 
| auto[1] | 
auto[1] | 
878 | 
1 | 
 | 
 | 
T98 | 
8 | 
 | 
T99 | 
9 | 
 | 
T34 | 
7 | 
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
| jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37541 | 
1 | 
 | 
 | 
T1 | 
60 | 
 | 
T2 | 
10 | 
 | 
T4 | 
13 | 
| auto[0] | 
auto[1] | 
1850 | 
1 | 
 | 
 | 
T18 | 
25 | 
 | 
T216 | 
10 | 
 | 
T214 | 
12 | 
| auto[1] | 
auto[0] | 
18604 | 
1 | 
 | 
 | 
T5 | 
2 | 
 | 
T6 | 
4 | 
 | 
T16 | 
5 | 
| auto[1] | 
auto[1] | 
1431 | 
1 | 
 | 
 | 
T9 | 
15 | 
 | 
T19 | 
13 | 
 | 
T34 | 
11 |