Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118645612

1

T1

28394

T2

5416

T3

38637

auto[1]

1581651

1

T2

396

T4

594

T10

495

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118677713

1

T1

28394

T2

5218

T3

38637

auto[1]

1549550

1

T2

594

T4

693

T10

495

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8451054	1			T1	6463		T2	1036		T3	69
auto[IdleSt]	24673347	1			T1	7574		T2	2375		T3	38568
auto[ClkMuxSt]	37609	1			T1	60		T2	10		T4	13
auto[CntIncrSt]	37345	1			T1	60		T2	10		T4	13
auto[CntProgSt]	1555702	1			T1	2508		T2	73		T4	222
auto[TransCheckSt]	29012	1			T1	60		T10	53		T5	2
auto[TokenHashSt]	46163866	1			T1	2127		T10	1451		T5	24
auto[FlashRmaSt]	38717	1			T1	111		T10	77		T5	2
auto[TokenCheck0St]	13826	1			T1	25		T10	20		T5	2
auto[TokenCheck1St]	10494	1			T1	9		T10	15		T5	2
auto[TransProgSt]	446008	1			T10	381		T5	27		T11	2724
auto[PostTransSt]	14720382	1			T1	9397		T2	807		T4	1005
auto[ScrapSt]	149033	1			T39	189		T18	301		T40	1142
auto[EscalateSt]	8323828	1			T2	1501		T4	1831		T10	1390
auto[InvalidSt]	15574690	1			T13	8314		T14	580		T38	11166

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2350	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	15574690	1			T13	8314		T14	580		T38	11166
EscalateSt	8323828	1			T2	1501		T4	1831		T10	1390
ScrapSt	149033	1			T39	189		T18	301		T40	1142
PostTransSt	14720382	1			T1	9397		T2	807		T4	1005
TransProgSt	446008	1			T10	381		T5	27		T11	2724
TokenCheck1St	10494	1			T1	9		T10	15		T5	2
TokenCheck0St	13826	1			T1	25		T10	20		T5	2
FlashRmaSt	38717	1			T1	111		T10	77		T5	2
TokenHashSt	46163866	1			T1	2127		T10	1451		T5	24
TransCheckSt	29012	1			T1	60		T10	53		T5	2
CntProgSt	1555702	1			T1	2508		T2	73		T4	222
CntIncrSt	37345	1			T1	60		T2	10		T4	13
ClkMuxSt	37609	1			T1	60		T2	10		T4	13
IdleSt	24673347	1			T1	7574		T2	2375		T3	38568
ResetSt	8451054	1			T1	6463		T2	1036		T3	69
arcs[ResetSt=>IdleSt]	59434	1			T1	61		T2	11		T3	1
arcs[IdleSt=>ScrapSt]	318	1			T39	1		T18	2		T40	1
arcs[IdleSt=>ClkMuxSt]	37379	1			T1	60		T2	10		T4	13
arcs[ClkMuxSt=>CntIncrSt]	37345	1			T1	60		T2	10		T4	13
arcs[CntIncrSt=>PostTransSt]	1947	1			T10	10		T15	7		T31	6
arcs[CntIncrSt=>CntProgSt]	35334	1			T1	60		T2	10		T4	13
arcs[CntProgSt=>PostTransSt]	5234	1			T2	10		T4	13		T10	10
arcs[CntProgSt=>TransCheckSt]	29012	1			T1	60		T10	53		T5	2
arcs[TransCheckSt=>PostTransSt]	3811	1			T1	29		T10	8		T12	38
arcs[TransCheckSt=>TokenHashSt]	25102	1			T1	31		T10	45		T5	2
arcs[TokenHashSt=>PostTransSt]	10425	1			T1	6		T10	25		T12	13
arcs[TokenHashSt=>FlashRmaSt]	13862	1			T1	25		T10	20		T5	2
arcs[FlashRmaSt=>TokenCheck0St]	13826	1			T1	25		T10	20		T5	2
arcs[TokenCheck0St=>PostTransSt]	3270	1			T1	16		T10	5		T12	24
arcs[TokenCheck0St=>TokenCheck1St]	10494	1			T1	9		T10	15		T5	2
arcs[TokenCheck1St=>PostTransSt]	680	1			T1	9		T10	1		T12	6
arcs[TransProgSt=>PostTransSt]	8965	1			T10	14		T5	2		T11	7
arcs[IdleSt=>EscalateSt]	129	1			T53	1		T33	5		T57	8
arcs[ClkMuxSt=>EscalateSt]	34	1			T53	2		T33	2		T54	3
arcs[CntIncrSt=>EscalateSt]	64	1			T53	6		T33	1		T55	1
arcs[CntProgSt=>EscalateSt]	1088	1			T53	26		T33	30		T55	40
arcs[TransCheckSt=>EscalateSt]	99	1			T56	5		T62	1		T57	5
arcs[TokenHashSt=>EscalateSt]	815	1			T53	6		T33	3		T61	1
arcs[FlashRmaSt=>EscalateSt]	36	1			T33	1		T56	1		T57	3
arcs[TokenCheck0St=>EscalateSt]	62	1			T53	3		T33	2		T55	1
arcs[TokenCheck1St=>EscalateSt]	22	1			T33	2		T57	1		T60	2
arcs[TransProgSt=>EscalateSt]	827	1			T53	18		T33	23		T55	22
arcs[PostTransSt=>EscalateSt]	5539	1			T2	10		T4	13		T10	10
arcs[InvalidSt=>EscalateSt]	16886	1			T13	59		T14	7		T38	60

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8450852	1			T1	6463		T2	1036		T3	69
auto[0]	auto[IdleSt]	24673258	1			T1	7574		T2	2375		T3	38568
auto[0]	auto[ClkMuxSt]	37587	1			T1	60		T2	10		T4	13
auto[0]	auto[CntIncrSt]	37310	1			T1	60		T2	10		T4	13
auto[0]	auto[CntProgSt]	1554960	1			T1	2508		T2	73		T4	222
auto[0]	auto[TransCheckSt]	28943	1			T1	60		T10	53		T5	2
auto[0]	auto[TokenHashSt]	46163291	1			T1	2127		T10	1451		T5	24
auto[0]	auto[FlashRmaSt]	38689	1			T1	111		T10	77		T5	2
auto[0]	auto[TokenCheck0St]	13784	1			T1	25		T10	20		T5	2
auto[0]	auto[TokenCheck1St]	10479	1			T1	9		T10	15		T5	2
auto[0]	auto[TransProgSt]	445446	1			T10	381		T5	27		T11	2724
auto[0]	auto[PostTransSt]	14717520	1			T1	9397		T2	803		T4	999
auto[0]	auto[ScrapSt]	148984	1			T39	189		T18	301		T40	1142
auto[0]	auto[EscalateSt]	6755914	1			T2	1109		T4	1243		T10	900
auto[0]	auto[InvalidSt]	15566245	1			T13	8280		T14	577		T38	11139
auto[1]	auto[ResetSt]	202	1			T53	7		T33	1		T55	2
auto[1]	auto[IdleSt]	89	1			T53	1		T33	4		T57	7
auto[1]	auto[ClkMuxSt]	22	1			T53	1		T33	1		T54	2
auto[1]	auto[CntIncrSt]	35	1			T53	3		T57	2		T60	1
auto[1]	auto[CntProgSt]	742	1			T53	18		T33	22		T55	30
auto[1]	auto[TransCheckSt]	69	1			T56	3		T57	4		T60	2
auto[1]	auto[TokenHashSt]	575	1			T53	2		T33	3		T61	1
auto[1]	auto[FlashRmaSt]	28	1			T33	1		T56	1		T57	1
auto[1]	auto[TokenCheck0St]	42	1			T53	2		T33	2		T55	1
auto[1]	auto[TokenCheck1St]	15	1			T33	2		T57	1		T60	2
auto[1]	auto[TransProgSt]	562	1			T53	14		T33	11		T55	17
auto[1]	auto[PostTransSt]	2862	1			T2	4		T4	6		T10	5
auto[1]	auto[ScrapSt]	49	1			T57	1		T212	1		T54	1
auto[1]	auto[EscalateSt]	1567914	1			T2	392		T4	588		T10	490
auto[1]	auto[InvalidSt]	8445	1			T13	34		T14	3		T38	27

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8450861	1			T1	6463		T2	1036		T3	69
auto[0]	auto[IdleSt]	24673256	1			T1	7574		T2	2375		T3	38568
auto[0]	auto[ClkMuxSt]	37585	1			T1	60		T2	10		T4	13
auto[0]	auto[CntIncrSt]	37302	1			T1	60		T2	10		T4	13
auto[0]	auto[CntProgSt]	1554997	1			T1	2508		T2	73		T4	222
auto[0]	auto[TransCheckSt]	28955	1			T1	60		T10	53		T5	2
auto[0]	auto[TokenHashSt]	46163340	1			T1	2127		T10	1451		T5	24
auto[0]	auto[FlashRmaSt]	38691	1			T1	111		T10	77		T5	2
auto[0]	auto[TokenCheck0St]	13792	1			T1	25		T10	20		T5	2
auto[0]	auto[TokenCheck1St]	10481	1			T1	9		T10	15		T5	2
auto[0]	auto[TransProgSt]	445463	1			T10	381		T5	27		T11	2724
auto[0]	auto[PostTransSt]	14717615	1			T1	9397		T2	801		T4	998
auto[0]	auto[ScrapSt]	148985	1			T39	189		T18	301		T40	1142
auto[0]	auto[EscalateSt]	6787791	1			T2	913		T4	1145		T10	900
auto[0]	auto[InvalidSt]	15566249	1			T13	8289		T14	576		T38	11133
auto[1]	auto[ResetSt]	193	1			T53	5		T33	2		T55	3
auto[1]	auto[IdleSt]	91	1			T33	4		T57	5		T54	6
auto[1]	auto[ClkMuxSt]	24	1			T53	2		T33	2		T54	3
auto[1]	auto[CntIncrSt]	43	1			T53	3		T33	1		T55	1
auto[1]	auto[CntProgSt]	705	1			T53	21		T33	18		T55	21
auto[1]	auto[TransCheckSt]	57	1			T56	3		T62	1		T57	3
auto[1]	auto[TokenHashSt]	526	1			T53	4		T33	3		T55	9
auto[1]	auto[FlashRmaSt]	26	1			T33	1		T56	1		T57	3
auto[1]	auto[TokenCheck0St]	34	1			T53	2		T60	1		T54	1
auto[1]	auto[TokenCheck1St]	13	1			T33	1		T60	1		T212	2
auto[1]	auto[TransProgSt]	545	1			T53	10		T33	18		T55	14
auto[1]	auto[PostTransSt]	2767	1			T2	6		T4	7		T10	5
auto[1]	auto[ScrapSt]	48	1			T55	1		T56	1		T57	1
auto[1]	auto[EscalateSt]	1536037	1			T2	588		T4	686		T10	490
auto[1]	auto[InvalidSt]	8441	1			T13	25		T14	4		T38	33