Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120752334

1

T1

668452

T2

1084

T3

27243

auto[1]

1491067

1

T1

5989

T3

12493

T12

5126

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120732770

1

T1

668348

T2

1084

T3

28568

auto[1]

1510631

1

T1

6093

T3

11168

T12

6940

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7825112	1			T1	84679		T2	162		T3	8390
auto[IdleSt]	24980535	1			T1	39971		T2	136		T3	8682
auto[ClkMuxSt]	38117	1			T1	101		T3	74		T4	57
auto[CntIncrSt]	37828	1			T1	101		T3	73		T4	57
auto[CntProgSt]	1964462	1			T1	39727		T3	1825		T4	2050
auto[TransCheckSt]	28986	1			T1	72		T3	37		T4	57
auto[TokenHashSt]	51581004	1			T1	31681		T3	1629		T4	3117
auto[FlashRmaSt]	37637	1			T1	82		T3	59		T4	145
auto[TokenCheck0St]	13476	1			T1	38		T3	32		T4	24
auto[TokenCheck1St]	9934	1			T1	31		T3	31		T4	13
auto[TransProgSt]	530853	1			T1	14364		T3	97		T12	192
auto[PostTransSt]	15019687	1			T1	18629		T2	786		T3	1
auto[ScrapSt]	295822	1			T3	4		T11	1535		T40	8
auto[EscalateSt]	7305650	1			T1	94217		T3	18802		T12	9336
auto[InvalidSt]	12572083	1			T1	350733		T13	4169		T20	12505

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2215	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12572083	1			T1	350733		T13	4169		T20	12505
EscalateSt	7305650	1			T1	94217		T3	18802		T12	9336
ScrapSt	295822	1			T3	4		T11	1535		T40	8
PostTransSt	15019687	1			T1	18629		T2	786		T3	1
TransProgSt	530853	1			T1	14364		T3	97		T12	192
TokenCheck1St	9934	1			T1	31		T3	31		T4	13
TokenCheck0St	13476	1			T1	38		T3	32		T4	24
FlashRmaSt	37637	1			T1	82		T3	59		T4	145
TokenHashSt	51581004	1			T1	31681		T3	1629		T4	3117
TransCheckSt	28986	1			T1	72		T3	37		T4	57
CntProgSt	1964462	1			T1	39727		T3	1825		T4	2050
CntIncrSt	37828	1			T1	101		T3	73		T4	57
ClkMuxSt	38117	1			T1	101		T3	74		T4	57
IdleSt	24980535	1			T1	39971		T2	136		T3	8682
ResetSt	7825112	1			T1	84679		T2	162		T3	8390
arcs[ResetSt=>IdleSt]	58424	1			T1	233		T2	1		T3	81
arcs[IdleSt=>ScrapSt]	281	1			T3	1		T11	1		T40	2
arcs[IdleSt=>ClkMuxSt]	37862	1			T1	101		T3	74		T4	57
arcs[ClkMuxSt=>CntIncrSt]	37828	1			T1	101		T3	73		T4	57
arcs[CntIncrSt=>PostTransSt]	2234	1			T1	12		T6	13		T21	56
arcs[CntIncrSt=>CntProgSt]	35536	1			T1	89		T3	71		T4	57
arcs[CntProgSt=>PostTransSt]	5464	1			T1	17		T14	1		T6	4
arcs[CntProgSt=>TransCheckSt]	28986	1			T1	72		T3	37		T4	57
arcs[TransCheckSt=>PostTransSt]	3835	1			T1	8		T4	21		T17	51
arcs[TransCheckSt=>TokenHashSt]	25059	1			T1	64		T3	37		T4	36
arcs[TokenHashSt=>PostTransSt]	10825	1			T1	26		T4	12		T17	14
arcs[TokenHashSt=>FlashRmaSt]	13516	1			T1	38		T3	32		T4	24
arcs[FlashRmaSt=>TokenCheck0St]	13476	1			T1	38		T3	32		T4	24
arcs[TokenCheck0St=>PostTransSt]	3479	1			T1	7		T4	11		T17	21
arcs[TokenCheck0St=>TokenCheck1St]	9934	1			T1	31		T3	31		T4	13
arcs[TokenCheck1St=>PostTransSt]	659	1			T4	13		T17	10		T6	1
arcs[TransProgSt=>PostTransSt]	8482	1			T1	31		T3	1		T12	2
arcs[IdleSt=>EscalateSt]	153	1			T3	5		T12	4		T51	3
arcs[ClkMuxSt=>EscalateSt]	34	1			T3	1		T51	3		T52	1
arcs[CntIncrSt=>EscalateSt]	58	1			T3	2		T40	2		T51	2
arcs[CntProgSt=>EscalateSt]	1086	1			T3	34		T12	13		T40	21
arcs[TransCheckSt=>EscalateSt]	92	1			T51	2		T52	1		T55	1
arcs[TokenHashSt=>EscalateSt]	718	1			T3	5		T12	6		T40	10
arcs[FlashRmaSt=>EscalateSt]	40	1			T12	2		T51	1		T52	1
arcs[TokenCheck0St=>EscalateSt]	63	1			T3	1		T12	1		T40	2
arcs[TokenCheck1St=>EscalateSt]	23	1			T12	2		T39	1		T54	1
arcs[TransProgSt=>EscalateSt]	770	1			T3	30		T12	19		T40	12
arcs[PostTransSt=>EscalateSt]	5773	1			T1	17		T3	1		T12	2
arcs[InvalidSt=>EscalateSt]	15755	1			T1	106		T13	57		T20	164

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7824936	1			T1	84679		T2	162		T3	8386
auto[0]	auto[IdleSt]	24980444	1			T1	39971		T2	136		T3	8680
auto[0]	auto[ClkMuxSt]	38094	1			T1	101		T3	73		T4	57
auto[0]	auto[CntIncrSt]	37793	1			T1	101		T3	72		T4	57
auto[0]	auto[CntProgSt]	1963736	1			T1	39727		T3	1802		T4	2050
auto[0]	auto[TransCheckSt]	28926	1			T1	72		T3	37		T4	57
auto[0]	auto[TokenHashSt]	51580547	1			T1	31681		T3	1626		T4	3117
auto[0]	auto[FlashRmaSt]	37611	1			T1	82		T3	59		T4	145
auto[0]	auto[TokenCheck0St]	13431	1			T1	38		T3	31		T4	24
auto[0]	auto[TokenCheck1St]	9920	1			T1	31		T3	31		T4	13
auto[0]	auto[TransProgSt]	530337	1			T1	14364		T3	74		T12	182
auto[0]	auto[PostTransSt]	15016744	1			T1	18623		T2	786		T3	1
auto[0]	auto[ScrapSt]	295781	1			T3	3		T11	1535		T40	7
auto[0]	auto[EscalateSt]	5827536	1			T1	88289		T3	6368		T12	4237
auto[0]	auto[InvalidSt]	12564283	1			T1	350678		T13	4146		T20	12430
auto[1]	auto[ResetSt]	176	1			T3	4		T12	2		T40	4
auto[1]	auto[IdleSt]	91	1			T3	2		T12	2		T51	2
auto[1]	auto[ClkMuxSt]	23	1			T3	1		T51	2		T52	1
auto[1]	auto[CntIncrSt]	35	1			T3	1		T40	2		T51	1
auto[1]	auto[CntProgSt]	726	1			T3	23		T12	7		T40	13
auto[1]	auto[TransCheckSt]	60	1			T51	1		T52	1		T208	4
auto[1]	auto[TokenHashSt]	457	1			T3	3		T12	1		T40	8
auto[1]	auto[FlashRmaSt]	26	1			T12	1		T51	1		T52	1
auto[1]	auto[TokenCheck0St]	45	1			T3	1		T40	2		T51	1
auto[1]	auto[TokenCheck1St]	14	1			T12	2		T39	1		T209	1
auto[1]	auto[TransProgSt]	516	1			T3	23		T12	10		T40	8
auto[1]	auto[PostTransSt]	2943	1			T1	6		T12	2		T40	2
auto[1]	auto[ScrapSt]	41	1			T3	1		T40	1		T51	1
auto[1]	auto[EscalateSt]	1478114	1			T1	5928		T3	12434		T12	5099
auto[1]	auto[InvalidSt]	7800	1			T1	55		T13	23		T20	75

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7824945	1			T1	84679		T2	162		T3	8387
auto[0]	auto[IdleSt]	24980421	1			T1	39971		T2	136		T3	8678
auto[0]	auto[ClkMuxSt]	38097	1			T1	101		T3	74		T4	57
auto[0]	auto[CntIncrSt]	37792	1			T1	101		T3	71		T4	57
auto[0]	auto[CntProgSt]	1963735	1			T1	39727		T3	1804		T4	2050
auto[0]	auto[TransCheckSt]	28926	1			T1	72		T3	37		T4	57
auto[0]	auto[TokenHashSt]	51580523	1			T1	31681		T3	1626		T4	3117
auto[0]	auto[FlashRmaSt]	37607	1			T1	82		T3	59		T4	145
auto[0]	auto[TokenCheck0St]	13437	1			T1	38		T3	31		T4	24
auto[0]	auto[TokenCheck1St]	9916	1			T1	31		T3	31		T4	13
auto[0]	auto[TransProgSt]	530353	1			T1	14364		T3	81		T12	178
auto[0]	auto[PostTransSt]	15016756	1			T1	18618		T2	786		T4	9092
auto[0]	auto[ScrapSt]	295775	1			T3	3		T11	1535		T40	6
auto[0]	auto[EscalateSt]	5808144	1			T1	88186		T3	7686		T12	2434
auto[0]	auto[InvalidSt]	12564128	1			T1	350682		T13	4135		T20	12416
auto[1]	auto[ResetSt]	167	1			T3	3		T12	1		T40	3
auto[1]	auto[IdleSt]	114	1			T3	4		T12	4		T51	1
auto[1]	auto[ClkMuxSt]	20	1			T51	1		T209	1		T210	2
auto[1]	auto[CntIncrSt]	36	1			T3	2		T51	2		T52	1
auto[1]	auto[CntProgSt]	727	1			T3	21		T12	9		T40	15
auto[1]	auto[TransCheckSt]	60	1			T51	2		T52	1		T55	1
auto[1]	auto[TokenHashSt]	481	1			T3	3		T12	6		T40	5
auto[1]	auto[FlashRmaSt]	30	1			T12	2		T211	1		T39	1
auto[1]	auto[TokenCheck0St]	39	1			T3	1		T12	1		T40	2
auto[1]	auto[TokenCheck1St]	18	1			T12	1		T39	1		T54	1
auto[1]	auto[TransProgSt]	500	1			T3	16		T12	14		T40	8
auto[1]	auto[PostTransSt]	2931	1			T1	11		T3	1		T14	1
auto[1]	auto[ScrapSt]	47	1			T3	1		T40	2		T51	2
auto[1]	auto[EscalateSt]	1497506	1			T1	6031		T3	11116		T12	6902
auto[1]	auto[InvalidSt]	7955	1			T1	51		T13	34		T20	89