Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57373 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
2046 |
1 |
|
|
T11 |
5 |
|
T4 |
26 |
|
T15 |
11 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58691 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
728 |
1 |
|
|
T13 |
24 |
|
T37 |
8 |
|
T68 |
20 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57235 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
2184 |
1 |
|
|
T4 |
31 |
|
T16 |
5 |
|
T18 |
4 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57129 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
2290 |
1 |
|
|
T4 |
38 |
|
T16 |
6 |
|
T18 |
4 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57162 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
2257 |
1 |
|
|
T4 |
35 |
|
T16 |
5 |
|
T18 |
6 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
53933 |
1 |
|
|
T2 |
20 |
|
T3 |
72 |
|
T11 |
86 |
no_err_inj |
5486 |
1 |
|
|
T1 |
10 |
|
T10 |
6 |
|
T4 |
51 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57423 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
1996 |
1 |
|
|
T11 |
14 |
|
T4 |
26 |
|
T15 |
13 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58666 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
753 |
1 |
|
|
T13 |
19 |
|
T37 |
18 |
|
T68 |
14 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39794 |
1 |
|
|
T1 |
10 |
|
T3 |
72 |
|
T10 |
6 |
auto[1] |
19625 |
1 |
|
|
T2 |
20 |
|
T4 |
369 |
|
T5 |
11 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57181 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
2238 |
1 |
|
|
T4 |
45 |
|
T16 |
5 |
|
T18 |
7 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57194 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
2225 |
1 |
|
|
T4 |
32 |
|
T16 |
7 |
|
T18 |
8 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57163 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
2256 |
1 |
|
|
T4 |
49 |
|
T16 |
9 |
|
T18 |
5 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57382 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
2037 |
1 |
|
|
T11 |
7 |
|
T4 |
29 |
|
T15 |
12 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56807 |
1 |
|
|
T1 |
10 |
|
T3 |
72 |
|
T10 |
6 |
auto[1] |
2612 |
1 |
|
|
T2 |
20 |
|
T4 |
52 |
|
T21 |
13 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58659 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
760 |
1 |
|
|
T13 |
17 |
|
T37 |
15 |
|
T68 |
10 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58698 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
721 |
1 |
|
|
T13 |
12 |
|
T37 |
16 |
|
T68 |
16 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58699 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
720 |
1 |
|
|
T13 |
14 |
|
T37 |
22 |
|
T68 |
15 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56214 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
3205 |
1 |
|
|
T4 |
45 |
|
T5 |
11 |
|
T79 |
15 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55567 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
3852 |
1 |
|
|
T59 |
83 |
|
T55 |
98 |
|
T60 |
52 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57144 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
2275 |
1 |
|
|
T4 |
37 |
|
T16 |
7 |
|
T18 |
10 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57170 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
2249 |
1 |
|
|
T4 |
30 |
|
T16 |
5 |
|
T5 |
2 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57156 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
2263 |
1 |
|
|
T4 |
53 |
|
T16 |
2 |
|
T18 |
5 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57406 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
2013 |
1 |
|
|
T11 |
19 |
|
T4 |
29 |
|
T15 |
10 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53750 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
5669 |
1 |
|
|
T11 |
8 |
|
T4 |
32 |
|
T15 |
13 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55635 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T10 |
6 |
auto[1] |
3784 |
1 |
|
|
T3 |
72 |
|
T73 |
63 |
|
T74 |
57 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59419 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57392 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
2027 |
1 |
|
|
T11 |
9 |
|
T4 |
19 |
|
T15 |
9 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57435 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
1984 |
1 |
|
|
T11 |
11 |
|
T4 |
23 |
|
T15 |
13 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57425 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[1] |
1994 |
1 |
|
|
T11 |
13 |
|
T4 |
27 |
|
T15 |
18 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
52291 |
1 |
|
|
T2 |
20 |
|
T3 |
72 |
|
T11 |
86 |
auto[0] |
no_err_inj |
3923 |
1 |
|
|
T1 |
10 |
|
T10 |
6 |
|
T4 |
32 |
auto[1] |
err_inj |
1642 |
1 |
|
|
T4 |
26 |
|
T5 |
2 |
|
T79 |
6 |
auto[1] |
no_err_inj |
1563 |
1 |
|
|
T4 |
19 |
|
T5 |
9 |
|
T79 |
9 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54140 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[0] |
auto[1] |
2074 |
1 |
|
|
T4 |
27 |
|
T16 |
5 |
|
T18 |
7 |
auto[1] |
auto[0] |
3030 |
1 |
|
|
T4 |
42 |
|
T5 |
9 |
|
T79 |
15 |
auto[1] |
auto[1] |
175 |
1 |
|
|
T4 |
3 |
|
T5 |
2 |
|
T41 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54163 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[0] |
auto[1] |
2051 |
1 |
|
|
T4 |
27 |
|
T16 |
7 |
|
T18 |
8 |
auto[1] |
auto[0] |
3031 |
1 |
|
|
T4 |
40 |
|
T5 |
11 |
|
T79 |
14 |
auto[1] |
auto[1] |
174 |
1 |
|
|
T4 |
5 |
|
T79 |
1 |
|
T31 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54129 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[0] |
auto[1] |
2085 |
1 |
|
|
T4 |
50 |
|
T16 |
2 |
|
T18 |
5 |
auto[1] |
auto[0] |
3027 |
1 |
|
|
T4 |
42 |
|
T5 |
11 |
|
T79 |
14 |
auto[1] |
auto[1] |
178 |
1 |
|
|
T4 |
3 |
|
T79 |
1 |
|
T31 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54102 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[0] |
auto[1] |
2112 |
1 |
|
|
T4 |
35 |
|
T16 |
6 |
|
T18 |
4 |
auto[1] |
auto[0] |
3027 |
1 |
|
|
T4 |
42 |
|
T5 |
11 |
|
T79 |
14 |
auto[1] |
auto[1] |
178 |
1 |
|
|
T4 |
3 |
|
T79 |
1 |
|
T31 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54146 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[0] |
auto[1] |
2068 |
1 |
|
|
T4 |
35 |
|
T16 |
5 |
|
T18 |
6 |
auto[1] |
auto[0] |
3016 |
1 |
|
|
T4 |
45 |
|
T5 |
11 |
|
T79 |
15 |
auto[1] |
auto[1] |
189 |
1 |
|
|
T32 |
3 |
|
T41 |
4 |
|
T81 |
4 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54229 |
1 |
|
|
T1 |
10 |
|
T2 |
20 |
|
T3 |
72 |
auto[0] |
auto[1] |
1985 |
1 |
|
|
T4 |
28 |
|
T16 |
5 |
|
T18 |
4 |
auto[1] |
auto[0] |
3006 |
1 |
|
|
T4 |
42 |
|
T5 |
11 |
|
T79 |
15 |
auto[1] |
auto[1] |
199 |
1 |
|
|
T4 |
3 |
|
T32 |
4 |
|
T41 |
4 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38595 |
1 |
|
|
T1 |
10 |
|
T3 |
72 |
|
T10 |
6 |
auto[0] |
auto[1] |
1199 |
1 |
|
|
T11 |
5 |
|
T15 |
11 |
|
T43 |
8 |
auto[1] |
auto[0] |
18778 |
1 |
|
|
T2 |
20 |
|
T4 |
343 |
|
T5 |
11 |
auto[1] |
auto[1] |
847 |
1 |
|
|
T4 |
26 |
|
T41 |
13 |
|
T52 |
22 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38706 |
1 |
|
|
T1 |
10 |
|
T3 |
72 |
|
T10 |
6 |
auto[0] |
auto[1] |
1088 |
1 |
|
|
T11 |
14 |
|
T15 |
13 |
|
T43 |
10 |
auto[1] |
auto[0] |
18717 |
1 |
|
|
T2 |
20 |
|
T4 |
343 |
|
T5 |
11 |
auto[1] |
auto[1] |
908 |
1 |
|
|
T4 |
26 |
|
T41 |
20 |
|
T52 |
27 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38514 |
1 |
|
|
T1 |
10 |
|
T3 |
72 |
|
T10 |
6 |
auto[0] |
auto[1] |
1280 |
1 |
|
|
T4 |
49 |
|
T32 |
1 |
|
T35 |
3 |
auto[1] |
auto[0] |
18293 |
1 |
|
|
T4 |
366 |
|
T5 |
11 |
|
T17 |
5 |
auto[1] |
auto[1] |
1332 |
1 |
|
|
T2 |
20 |
|
T4 |
3 |
|
T21 |
13 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38676 |
1 |
|
|
T1 |
10 |
|
T3 |
72 |
|
T10 |
6 |
auto[0] |
auto[1] |
1118 |
1 |
|
|
T11 |
7 |
|
T15 |
12 |
|
T43 |
7 |
auto[1] |
auto[0] |
18706 |
1 |
|
|
T2 |
20 |
|
T4 |
340 |
|
T5 |
11 |
auto[1] |
auto[1] |
919 |
1 |
|
|
T4 |
29 |
|
T41 |
28 |
|
T52 |
25 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35009 |
1 |
|
|
T1 |
10 |
|
T3 |
72 |
|
T10 |
6 |
auto[0] |
auto[1] |
4785 |
1 |
|
|
T11 |
8 |
|
T15 |
13 |
|
T43 |
6 |
auto[1] |
auto[0] |
18741 |
1 |
|
|
T2 |
20 |
|
T4 |
337 |
|
T5 |
11 |
auto[1] |
auto[1] |
884 |
1 |
|
|
T4 |
32 |
|
T41 |
17 |
|
T52 |
17 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38541 |
1 |
|
|
T1 |
10 |
|
T3 |
72 |
|
T10 |
6 |
auto[0] |
auto[1] |
1253 |
1 |
|
|
T4 |
15 |
|
T16 |
5 |
|
T98 |
9 |
auto[1] |
auto[0] |
18629 |
1 |
|
|
T2 |
20 |
|
T4 |
354 |
|
T5 |
9 |
auto[1] |
auto[1] |
996 |
1 |
|
|
T4 |
15 |
|
T5 |
2 |
|
T18 |
7 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38490 |
1 |
|
|
T1 |
10 |
|
T3 |
72 |
|
T10 |
6 |
auto[0] |
auto[1] |
1304 |
1 |
|
|
T4 |
19 |
|
T16 |
7 |
|
T79 |
2 |
auto[1] |
auto[0] |
18654 |
1 |
|
|
T2 |
20 |
|
T4 |
351 |
|
T5 |
11 |
auto[1] |
auto[1] |
971 |
1 |
|
|
T4 |
18 |
|
T18 |
10 |
|
T32 |
2 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38516 |
1 |
|
|
T1 |
10 |
|
T3 |
72 |
|
T10 |
6 |
auto[0] |
auto[1] |
1278 |
1 |
|
|
T4 |
24 |
|
T16 |
7 |
|
T79 |
1 |
auto[1] |
auto[0] |
18678 |
1 |
|
|
T2 |
20 |
|
T4 |
361 |
|
T5 |
11 |
auto[1] |
auto[1] |
947 |
1 |
|
|
T4 |
8 |
|
T18 |
8 |
|
T31 |
1 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38521 |
1 |
|
|
T1 |
10 |
|
T3 |
72 |
|
T10 |
6 |
auto[0] |
auto[1] |
1273 |
1 |
|
|
T4 |
29 |
|
T16 |
5 |
|
T98 |
7 |
auto[1] |
auto[0] |
18660 |
1 |
|
|
T2 |
20 |
|
T4 |
353 |
|
T5 |
11 |
auto[1] |
auto[1] |
965 |
1 |
|
|
T4 |
16 |
|
T18 |
7 |
|
T31 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38475 |
1 |
|
|
T1 |
10 |
|
T3 |
72 |
|
T10 |
6 |
auto[0] |
auto[1] |
1319 |
1 |
|
|
T4 |
23 |
|
T16 |
6 |
|
T79 |
1 |
auto[1] |
auto[0] |
18654 |
1 |
|
|
T2 |
20 |
|
T4 |
354 |
|
T5 |
11 |
auto[1] |
auto[1] |
971 |
1 |
|
|
T4 |
15 |
|
T18 |
4 |
|
T31 |
1 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38541 |
1 |
|
|
T1 |
10 |
|
T3 |
72 |
|
T10 |
6 |
auto[0] |
auto[1] |
1253 |
1 |
|
|
T4 |
18 |
|
T16 |
5 |
|
T98 |
7 |
auto[1] |
auto[0] |
18694 |
1 |
|
|
T2 |
20 |
|
T4 |
356 |
|
T5 |
11 |
auto[1] |
auto[1] |
931 |
1 |
|
|
T4 |
13 |
|
T18 |
4 |
|
T32 |
4 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38715 |
1 |
|
|
T1 |
10 |
|
T3 |
72 |
|
T10 |
6 |
auto[0] |
auto[1] |
1079 |
1 |
|
|
T11 |
13 |
|
T15 |
18 |
|
T43 |
7 |
auto[1] |
auto[0] |
18710 |
1 |
|
|
T2 |
20 |
|
T4 |
342 |
|
T5 |
11 |
auto[1] |
auto[1] |
915 |
1 |
|
|
T4 |
27 |
|
T41 |
14 |
|
T52 |
22 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38710 |
1 |
|
|
T1 |
10 |
|
T3 |
72 |
|
T10 |
6 |
auto[0] |
auto[1] |
1084 |
1 |
|
|
T11 |
11 |
|
T15 |
13 |
|
T43 |
7 |
auto[1] |
auto[0] |
18725 |
1 |
|
|
T2 |
20 |
|
T4 |
346 |
|
T5 |
11 |
auto[1] |
auto[1] |
900 |
1 |
|
|
T4 |
23 |
|
T41 |
20 |
|
T52 |
27 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38092 |
1 |
|
|
T1 |
10 |
|
T3 |
72 |
|
T10 |
6 |
auto[0] |
auto[1] |
1702 |
1 |
|
|
T4 |
45 |
|
T79 |
15 |
|
T41 |
12 |
auto[1] |
auto[0] |
18122 |
1 |
|
|
T2 |
20 |
|
T4 |
369 |
|
T17 |
5 |
auto[1] |
auto[1] |
1503 |
1 |
|
|
T5 |
11 |
|
T31 |
12 |
|
T32 |
39 |