Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111957350

1

T1

3493

T2

64162

T3

34095

auto[1]

1554934

1

T2

980

T11

297

T4

17445

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111982964

1

T1

3493

T2

64162

T3

34095

auto[1]

1529320

1

T2

980

T11

198

T4

14803

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8217010	1			T1	950		T2	2014		T3	6589
auto[IdleSt]	23872298	1			T1	1034		T2	35181		T3	2471
auto[ClkMuxSt]	38075	1			T1	10		T2	20		T3	72
auto[CntIncrSt]	37841	1			T1	10		T2	20		T3	72
auto[CntProgSt]	1418468	1			T1	275		T2	40		T3	2483
auto[TransCheckSt]	29090	1			T1	10		T3	72		T10	6
auto[TokenHashSt]	42192854	1			T1	108		T3	11028		T10	18779
auto[FlashRmaSt]	38051	1			T1	48		T3	77		T10	6
auto[TokenCheck0St]	13829	1			T1	10		T3	28		T10	6
auto[TokenCheck1St]	10299	1			T1	10		T3	8		T10	6
auto[TransProgSt]	346998	1			T1	215		T10	285		T11	14
auto[PostTransSt]	14542192	1			T1	813		T2	16064		T3	11195
auto[ScrapSt]	143830	1			T14	106		T19	982		T20	390
auto[EscalateSt]	8065140	1			T2	11803		T11	654		T4	103080
auto[InvalidSt]	14544002	1			T4	230984		T13	1750		T14	2353

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2307	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	14544002	1			T4	230984		T13	1750		T14	2353
EscalateSt	8065140	1			T2	11803		T11	654		T4	103080
ScrapSt	143830	1			T14	106		T19	982		T20	390
PostTransSt	14542192	1			T1	813		T2	16064		T3	11195
TransProgSt	346998	1			T1	215		T10	285		T11	14
TokenCheck1St	10299	1			T1	10		T3	8		T10	6
TokenCheck0St	13829	1			T1	10		T3	28		T10	6
FlashRmaSt	38051	1			T1	48		T3	77		T10	6
TokenHashSt	42192854	1			T1	108		T3	11028		T10	18779
TransCheckSt	29090	1			T1	10		T3	72		T10	6
CntProgSt	1418468	1			T1	275		T2	40		T3	2483
CntIncrSt	37841	1			T1	10		T2	20		T3	72
ClkMuxSt	38075	1			T1	10		T2	20		T3	72
IdleSt	23872298	1			T1	1034		T2	35181		T3	2471
ResetSt	8217010	1			T1	950		T2	2014		T3	6589
arcs[ResetSt=>IdleSt]	59523	1			T1	10		T2	21		T3	73
arcs[IdleSt=>ScrapSt]	311	1			T14	4		T19	3		T20	1
arcs[IdleSt=>ClkMuxSt]	37878	1			T1	10		T2	20		T3	72
arcs[ClkMuxSt=>CntIncrSt]	37841	1			T1	10		T2	20		T3	72
arcs[CntIncrSt=>PostTransSt]	1985	1			T11	11		T4	23		T15	13
arcs[CntIncrSt=>CntProgSt]	35800	1			T1	10		T2	20		T3	72
arcs[CntProgSt=>PostTransSt]	5363	1			T2	20		T11	5		T4	78
arcs[CntProgSt=>TransCheckSt]	29090	1			T1	10		T3	72		T10	6
arcs[TransCheckSt=>PostTransSt]	3860	1			T3	33		T11	13		T4	27
arcs[TransCheckSt=>TokenHashSt]	25152	1			T1	10		T3	39		T10	6
arcs[TokenHashSt=>PostTransSt]	10642	1			T3	11		T11	36		T4	82
arcs[TokenHashSt=>FlashRmaSt]	13859	1			T1	10		T3	28		T10	6
arcs[FlashRmaSt=>TokenCheck0St]	13829	1			T1	10		T3	28		T10	6
arcs[TokenCheck0St=>PostTransSt]	3469	1			T3	20		T11	13		T4	26
arcs[TokenCheck0St=>TokenCheck1St]	10299	1			T1	10		T3	8		T10	6
arcs[TokenCheck1St=>PostTransSt]	670	1			T3	8		T11	1		T13	1
arcs[TransProgSt=>PostTransSt]	8702	1			T1	10		T10	6		T11	7
arcs[IdleSt=>EscalateSt]	149	1			T55	7		T60	5		T56	2
arcs[ClkMuxSt=>EscalateSt]	37	1			T55	3		T56	2		T57	3
arcs[CntIncrSt=>EscalateSt]	56	1			T56	3		T58	1		T57	1
arcs[CntProgSt=>EscalateSt]	1347	1			T59	29		T55	32		T60	5
arcs[TransCheckSt=>EscalateSt]	78	1			T60	4		T58	10		T67	3
arcs[TokenHashSt=>EscalateSt]	651	1			T59	13		T66	1		T55	9
arcs[FlashRmaSt=>EscalateSt]	30	1			T59	1		T57	2		T61	1
arcs[TokenCheck0St=>EscalateSt]	61	1			T59	2		T55	2		T60	1
arcs[TokenCheck1St=>EscalateSt]	21	1			T59	1		T64	1		T65	1
arcs[TransProgSt=>EscalateSt]	906	1			T59	27		T55	37		T60	5
arcs[PostTransSt=>EscalateSt]	5583	1			T2	20		T11	5		T4	78
arcs[InvalidSt=>EscalateSt]	16455	1			T4	249		T13	12		T16	40

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8216832	1			T1	950		T2	2014		T3	6589
auto[0]	auto[IdleSt]	23872199	1			T1	1034		T2	35181		T3	2471
auto[0]	auto[ClkMuxSt]	38044	1			T1	10		T2	20		T3	72
auto[0]	auto[CntIncrSt]	37808	1			T1	10		T2	20		T3	72
auto[0]	auto[CntProgSt]	1417556	1			T1	275		T2	40		T3	2483
auto[0]	auto[TransCheckSt]	29035	1			T1	10		T3	72		T10	6
auto[0]	auto[TokenHashSt]	42192418	1			T1	108		T3	11028		T10	18779
auto[0]	auto[FlashRmaSt]	38031	1			T1	48		T3	77		T10	6
auto[0]	auto[TokenCheck0St]	13789	1			T1	10		T3	28		T10	6
auto[0]	auto[TokenCheck1St]	10286	1			T1	10		T3	8		T10	6
auto[0]	auto[TransProgSt]	346406	1			T1	215		T10	285		T11	14
auto[0]	auto[PostTransSt]	14539364	1			T1	813		T2	16054		T3	11195
auto[0]	auto[ScrapSt]	143787	1			T14	106		T19	982		T20	390
auto[0]	auto[EscalateSt]	6523800	1			T2	10833		T11	360		T4	85812
auto[0]	auto[InvalidSt]	14535688	1			T4	230851		T13	1742		T14	2353
auto[1]	auto[ResetSt]	178	1			T59	3		T55	3		T60	3
auto[1]	auto[IdleSt]	99	1			T55	6		T60	3		T56	2
auto[1]	auto[ClkMuxSt]	31	1			T55	3		T56	1		T57	3
auto[1]	auto[CntIncrSt]	33	1			T56	1		T57	1		T67	2
auto[1]	auto[CntProgSt]	912	1			T59	21		T55	21		T60	3
auto[1]	auto[TransCheckSt]	55	1			T60	2		T58	6		T67	2
auto[1]	auto[TokenHashSt]	436	1			T59	8		T55	5		T46	2
auto[1]	auto[FlashRmaSt]	20	1			T59	1		T57	1		T67	1
auto[1]	auto[TokenCheck0St]	40	1			T59	1		T55	1		T56	2
auto[1]	auto[TokenCheck1St]	13	1			T59	1		T65	1		T213	1
auto[1]	auto[TransProgSt]	592	1			T59	17		T55	24		T60	2
auto[1]	auto[PostTransSt]	2828	1			T2	10		T11	3		T4	44
auto[1]	auto[ScrapSt]	43	1			T58	2		T64	1		T214	3
auto[1]	auto[EscalateSt]	1541340	1			T2	970		T11	294		T4	17268
auto[1]	auto[InvalidSt]	8314	1			T4	133		T13	8		T16	23

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8216848	1			T1	950		T2	2014		T3	6589
auto[0]	auto[IdleSt]	23872199	1			T1	1034		T2	35181		T3	2471
auto[0]	auto[ClkMuxSt]	38047	1			T1	10		T2	20		T3	72
auto[0]	auto[CntIncrSt]	37804	1			T1	10		T2	20		T3	72
auto[0]	auto[CntProgSt]	1417597	1			T1	275		T2	40		T3	2483
auto[0]	auto[TransCheckSt]	29041	1			T1	10		T3	72		T10	6
auto[0]	auto[TokenHashSt]	42192423	1			T1	108		T3	11028		T10	18779
auto[0]	auto[FlashRmaSt]	38028	1			T1	48		T3	77		T10	6
auto[0]	auto[TokenCheck0St]	13787	1			T1	10		T3	28		T10	6
auto[0]	auto[TokenCheck1St]	10284	1			T1	10		T3	8		T10	6
auto[0]	auto[TransProgSt]	346387	1			T1	215		T10	285		T11	14
auto[0]	auto[PostTransSt]	14539364	1			T1	813		T2	16054		T3	11195
auto[0]	auto[ScrapSt]	143778	1			T14	106		T19	982		T20	390
auto[0]	auto[EscalateSt]	6549209	1			T2	10833		T11	458		T4	88427
auto[0]	auto[InvalidSt]	14535861	1			T4	230868		T13	1746		T14	2353
auto[1]	auto[ResetSt]	162	1			T59	5		T55	3		T56	1
auto[1]	auto[IdleSt]	99	1			T55	4		T60	3		T56	1
auto[1]	auto[ClkMuxSt]	28	1			T56	2		T57	1		T61	2
auto[1]	auto[CntIncrSt]	37	1			T56	2		T58	1		T57	1
auto[1]	auto[CntProgSt]	871	1			T59	19		T55	18		T60	3
auto[1]	auto[TransCheckSt]	49	1			T60	3		T58	7		T67	2
auto[1]	auto[TokenHashSt]	431	1			T59	12		T66	1		T55	7
auto[1]	auto[FlashRmaSt]	23	1			T59	1		T57	1		T61	1
auto[1]	auto[TokenCheck0St]	42	1			T59	1		T55	2		T60	1
auto[1]	auto[TokenCheck1St]	15	1			T64	1		T65	1		T215	1
auto[1]	auto[TransProgSt]	611	1			T59	18		T55	27		T60	4
auto[1]	auto[PostTransSt]	2828	1			T2	10		T11	2		T4	34
auto[1]	auto[ScrapSt]	52	1			T59	1		T55	1		T58	1
auto[1]	auto[EscalateSt]	1515931	1			T2	970		T11	196		T4	14653
auto[1]	auto[InvalidSt]	8141	1			T4	116		T13	4		T16	17