Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116199818

1

T1

38527

T2

28981

T3

27370

auto[1]

1511233

1

T4

4653

T5

20233

T6

196

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116219631

1

T1

38527

T2

28981

T3

27370

auto[1]

1491420

1

T4

2376

T5

16870

T6

196

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7908793	1			T1	8665		T2	94		T3	6654
auto[IdleSt]	25683666	1			T1	8416		T2	28887		T3	6190
auto[ClkMuxSt]	39753	1			T1	98		T3	71		T10	1
auto[CntIncrSt]	39528	1			T1	98		T3	71		T10	1
auto[CntProgSt]	1671052	1			T1	4762		T3	2496		T10	425
auto[TransCheckSt]	30452	1			T1	98		T3	71		T10	1
auto[TokenHashSt]	46104881	1			T1	1011		T3	733		T10	10
auto[FlashRmaSt]	40360	1			T1	172		T3	71		T10	1
auto[TokenCheck0St]	14088	1			T1	39		T3	29		T10	1
auto[TokenCheck1St]	10488	1			T1	14		T3	11		T10	1
auto[TransProgSt]	433140	1			T10	643		T5	4614		T12	8
auto[PostTransSt]	15881835	1			T1	15154		T3	10973		T10	993
auto[ScrapSt]	295400	1			T5	1208		T14	6834		T38	15
auto[EscalateSt]	7458738	1			T4	8809		T5	118006		T6	13435
auto[InvalidSt]	12096742	1			T4	5424		T5	134983		T6	20510

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2135	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12096742	1			T4	5424		T5	134983		T6	20510
EscalateSt	7458738	1			T4	8809		T5	118006		T6	13435
ScrapSt	295400	1			T5	1208		T14	6834		T38	15
PostTransSt	15881835	1			T1	15154		T3	10973		T10	993
TransProgSt	433140	1			T10	643		T5	4614		T12	8
TokenCheck1St	10488	1			T1	14		T3	11		T10	1
TokenCheck0St	14088	1			T1	39		T3	29		T10	1
FlashRmaSt	40360	1			T1	172		T3	71		T10	1
TokenHashSt	46104881	1			T1	1011		T3	733		T10	10
TransCheckSt	30452	1			T1	98		T3	71		T10	1
CntProgSt	1671052	1			T1	4762		T3	2496		T10	425
CntIncrSt	39528	1			T1	98		T3	71		T10	1
ClkMuxSt	39753	1			T1	98		T3	71		T10	1
IdleSt	25683666	1			T1	8416		T2	28887		T3	6190
ResetSt	7908793	1			T1	8665		T2	94		T3	6654
arcs[ResetSt=>IdleSt]	59719	1			T1	99		T2	1		T3	72
arcs[IdleSt=>ScrapSt]	311	1			T5	3		T14	4		T38	1
arcs[IdleSt=>ClkMuxSt]	39574	1			T1	98		T3	71		T10	1
arcs[ClkMuxSt=>CntIncrSt]	39528	1			T1	98		T3	71		T10	1
arcs[CntIncrSt=>PostTransSt]	2292	1			T5	37		T13	11		T14	32
arcs[CntIncrSt=>CntProgSt]	37166	1			T1	98		T3	71		T10	1
arcs[CntProgSt=>PostTransSt]	5701	1			T5	123		T13	11		T14	90
arcs[CntProgSt=>TransCheckSt]	30452	1			T1	98		T3	71		T10	1
arcs[TransCheckSt=>PostTransSt]	4098	1			T1	52		T3	37		T5	42
arcs[TransCheckSt=>TokenHashSt]	26247	1			T1	46		T3	34		T10	1
arcs[TokenHashSt=>PostTransSt]	11341	1			T1	7		T3	5		T5	140
arcs[TokenHashSt=>FlashRmaSt]	14127	1			T1	39		T3	29		T10	1
arcs[FlashRmaSt=>TokenCheck0St]	14088	1			T1	39		T3	29		T10	1
arcs[TokenCheck0St=>PostTransSt]	3536	1			T1	25		T3	18		T5	33
arcs[TokenCheck0St=>TokenCheck1St]	10488	1			T1	14		T3	11		T10	1
arcs[TokenCheck1St=>PostTransSt]	642	1			T1	14		T3	11		T5	3
arcs[TransProgSt=>PostTransSt]	9024	1			T10	1		T5	100		T12	1
arcs[IdleSt=>EscalateSt]	144	1			T45	3		T46	6		T47	8
arcs[ClkMuxSt=>EscalateSt]	46	1			T45	1		T46	1		T47	1
arcs[CntIncrSt=>EscalateSt]	70	1			T48	1		T29	2		T45	1
arcs[CntProgSt=>EscalateSt]	1013	1			T48	4		T29	24		T45	24
arcs[TransCheckSt=>EscalateSt]	107	1			T48	8		T29	1		T50	1
arcs[TokenHashSt=>EscalateSt]	779	1			T48	41		T29	10		T20	1
arcs[FlashRmaSt=>EscalateSt]	39	1			T47	2		T49	2		T50	2
arcs[TokenCheck0St=>EscalateSt]	64	1			T48	2		T29	2		T45	1
arcs[TokenCheck1St=>EscalateSt]	29	1			T45	1		T49	1		T51	3
arcs[TransProgSt=>EscalateSt]	793	1			T48	11		T29	26		T45	21
arcs[PostTransSt=>EscalateSt]	6043	1			T5	123		T13	11		T14	89
arcs[InvalidSt=>EscalateSt]	15238	1			T4	71		T5	253		T6	4

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7908614	1			T1	8665		T2	94		T3	6654
auto[0]	auto[IdleSt]	25683569	1			T1	8416		T2	28887		T3	6190
auto[0]	auto[ClkMuxSt]	39724	1			T1	98		T3	71		T10	1
auto[0]	auto[CntIncrSt]	39474	1			T1	98		T3	71		T10	1
auto[0]	auto[CntProgSt]	1670369	1			T1	4762		T3	2496		T10	425
auto[0]	auto[TransCheckSt]	30379	1			T1	98		T3	71		T10	1
auto[0]	auto[TokenHashSt]	46104352	1			T1	1011		T3	733		T10	10
auto[0]	auto[FlashRmaSt]	40332	1			T1	172		T3	71		T10	1
auto[0]	auto[TokenCheck0St]	14041	1			T1	39		T3	29		T10	1
auto[0]	auto[TokenCheck1St]	10467	1			T1	14		T3	11		T10	1
auto[0]	auto[TransProgSt]	432620	1			T10	643		T5	4614		T12	8
auto[0]	auto[PostTransSt]	15878696	1			T1	15154		T3	10973		T10	993
auto[0]	auto[ScrapSt]	295352	1			T5	1208		T14	6834		T38	15
auto[0]	auto[EscalateSt]	5960590	1			T4	4203		T5	97978		T6	13241
auto[0]	auto[InvalidSt]	12089104	1			T4	5377		T5	134843		T6	20508
auto[1]	auto[ResetSt]	179	1			T48	2		T29	6		T45	3
auto[1]	auto[IdleSt]	97	1			T45	1		T46	5		T47	7
auto[1]	auto[ClkMuxSt]	29	1			T45	1		T46	1		T51	2
auto[1]	auto[CntIncrSt]	54	1			T29	2		T45	1		T47	2
auto[1]	auto[CntProgSt]	683	1			T48	3		T29	15		T45	17
auto[1]	auto[TransCheckSt]	73	1			T48	4		T29	1		T50	1
auto[1]	auto[TokenHashSt]	529	1			T48	30		T29	7		T45	7
auto[1]	auto[FlashRmaSt]	28	1			T47	1		T49	2		T50	2
auto[1]	auto[TokenCheck0St]	47	1			T48	2		T29	2		T45	1
auto[1]	auto[TokenCheck1St]	21	1			T45	1		T51	3		T197	1
auto[1]	auto[TransProgSt]	520	1			T48	7		T29	13		T45	13
auto[1]	auto[PostTransSt]	3139	1			T5	65		T13	4		T14	46
auto[1]	auto[ScrapSt]	48	1			T48	3		T45	2		T46	2
auto[1]	auto[EscalateSt]	1498148	1			T4	4606		T5	20028		T6	194
auto[1]	auto[InvalidSt]	7638	1			T4	47		T5	140		T6	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7908621	1			T1	8665		T2	94		T3	6654
auto[0]	auto[IdleSt]	25683567	1			T1	8416		T2	28887		T3	6190
auto[0]	auto[ClkMuxSt]	39717	1			T1	98		T3	71		T10	1
auto[0]	auto[CntIncrSt]	39479	1			T1	98		T3	71		T10	1
auto[0]	auto[CntProgSt]	1670381	1			T1	4762		T3	2496		T10	425
auto[0]	auto[TransCheckSt]	30383	1			T1	98		T3	71		T10	1
auto[0]	auto[TokenHashSt]	46104353	1			T1	1011		T3	733		T10	10
auto[0]	auto[FlashRmaSt]	40335	1			T1	172		T3	71		T10	1
auto[0]	auto[TokenCheck0St]	14051	1			T1	39		T3	29		T10	1
auto[0]	auto[TokenCheck1St]	10469	1			T1	14		T3	11		T10	1
auto[0]	auto[TransProgSt]	432599	1			T10	643		T5	4614		T12	8
auto[0]	auto[PostTransSt]	15878823	1			T1	15154		T3	10973		T10	993
auto[0]	auto[ScrapSt]	295355	1			T5	1208		T14	6834		T38	15
auto[0]	auto[EscalateSt]	5980221	1			T4	6457		T5	101307		T6	13241
auto[0]	auto[InvalidSt]	12089142	1			T4	5400		T5	134870		T6	20508
auto[1]	auto[ResetSt]	172	1			T29	4		T45	2		T46	4
auto[1]	auto[IdleSt]	99	1			T45	3		T46	3		T47	5
auto[1]	auto[ClkMuxSt]	36	1			T45	1		T47	1		T51	1
auto[1]	auto[CntIncrSt]	49	1			T48	1		T47	1		T49	1
auto[1]	auto[CntProgSt]	671	1			T48	3		T29	17		T45	16
auto[1]	auto[TransCheckSt]	69	1			T48	5		T50	1		T51	1
auto[1]	auto[TokenHashSt]	528	1			T48	25		T29	8		T20	1
auto[1]	auto[FlashRmaSt]	25	1			T47	2		T49	1		T50	1
auto[1]	auto[TokenCheck0St]	37	1			T48	1		T29	1		T46	1
auto[1]	auto[TokenCheck1St]	19	1			T45	1		T49	1		T51	1
auto[1]	auto[TransProgSt]	541	1			T48	9		T29	19		T45	12
auto[1]	auto[PostTransSt]	3012	1			T5	58		T13	7		T14	43
auto[1]	auto[ScrapSt]	45	1			T48	4		T45	1		T46	1
auto[1]	auto[EscalateSt]	1478517	1			T4	2352		T5	16699		T6	194
auto[1]	auto[InvalidSt]	7600	1			T4	24		T5	113		T6	2