Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56354 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
2094 |
1 |
|
|
T34 |
9 |
|
T17 |
16 |
|
T35 |
13 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57686 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
762 |
1 |
|
|
T37 |
13 |
|
T64 |
15 |
|
T65 |
20 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56431 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
2017 |
1 |
|
|
T11 |
1 |
|
T16 |
9 |
|
T18 |
9 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56396 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
2052 |
1 |
|
|
T9 |
1 |
|
T15 |
2 |
|
T16 |
18 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56311 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
2137 |
1 |
|
|
T9 |
1 |
|
T11 |
1 |
|
T16 |
8 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
52838 |
1 |
|
|
T3 |
2 |
|
T4 |
3 |
|
T9 |
6 |
no_err_inj |
5610 |
1 |
|
|
T2 |
10 |
|
T8 |
20 |
|
T9 |
8 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56316 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
2132 |
1 |
|
|
T34 |
10 |
|
T17 |
13 |
|
T35 |
18 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57692 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
756 |
1 |
|
|
T37 |
17 |
|
T64 |
6 |
|
T65 |
28 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40334 |
1 |
|
|
T2 |
10 |
|
T4 |
3 |
|
T8 |
20 |
auto[1] |
18114 |
1 |
|
|
T3 |
2 |
|
T15 |
14 |
|
T16 |
13 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56326 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
2122 |
1 |
|
|
T9 |
1 |
|
T16 |
3 |
|
T18 |
9 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56385 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
2063 |
1 |
|
|
T11 |
2 |
|
T16 |
13 |
|
T18 |
10 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56335 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
2113 |
1 |
|
|
T15 |
2 |
|
T16 |
14 |
|
T18 |
2 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56382 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
2066 |
1 |
|
|
T34 |
11 |
|
T17 |
13 |
|
T35 |
12 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55680 |
1 |
|
|
T2 |
10 |
|
T8 |
20 |
|
T9 |
14 |
auto[1] |
2768 |
1 |
|
|
T3 |
2 |
|
T4 |
3 |
|
T16 |
13 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57651 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
797 |
1 |
|
|
T37 |
18 |
|
T64 |
10 |
|
T65 |
19 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57701 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
747 |
1 |
|
|
T37 |
9 |
|
T64 |
9 |
|
T65 |
14 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57676 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
772 |
1 |
|
|
T37 |
17 |
|
T64 |
11 |
|
T65 |
19 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55021 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
3427 |
1 |
|
|
T9 |
14 |
|
T11 |
11 |
|
T15 |
14 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54789 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
3659 |
1 |
|
|
T14 |
84 |
|
T40 |
92 |
|
T55 |
69 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56405 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
2043 |
1 |
|
|
T9 |
1 |
|
T11 |
2 |
|
T16 |
10 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56260 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
2188 |
1 |
|
|
T9 |
1 |
|
T11 |
1 |
|
T16 |
13 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56352 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
2096 |
1 |
|
|
T9 |
1 |
|
T16 |
6 |
|
T18 |
3 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56384 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
2064 |
1 |
|
|
T34 |
11 |
|
T17 |
13 |
|
T35 |
9 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52829 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
5619 |
1 |
|
|
T10 |
92 |
|
T34 |
6 |
|
T17 |
5 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54785 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
3663 |
1 |
|
|
T13 |
66 |
|
T52 |
72 |
|
T63 |
100 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58448 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56423 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
2025 |
1 |
|
|
T34 |
8 |
|
T17 |
11 |
|
T35 |
12 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56408 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
2040 |
1 |
|
|
T34 |
10 |
|
T17 |
7 |
|
T35 |
10 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56405 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[1] |
2043 |
1 |
|
|
T34 |
12 |
|
T17 |
11 |
|
T35 |
7 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
51108 |
1 |
|
|
T3 |
2 |
|
T4 |
3 |
|
T10 |
92 |
auto[0] |
no_err_inj |
3913 |
1 |
|
|
T2 |
10 |
|
T8 |
20 |
|
T12 |
19 |
auto[1] |
err_inj |
1730 |
1 |
|
|
T9 |
6 |
|
T11 |
7 |
|
T15 |
4 |
auto[1] |
no_err_inj |
1697 |
1 |
|
|
T9 |
8 |
|
T11 |
4 |
|
T15 |
10 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53042 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[0] |
auto[1] |
1979 |
1 |
|
|
T16 |
11 |
|
T18 |
8 |
|
T19 |
8 |
auto[1] |
auto[0] |
3218 |
1 |
|
|
T9 |
13 |
|
T11 |
10 |
|
T15 |
14 |
auto[1] |
auto[1] |
209 |
1 |
|
|
T9 |
1 |
|
T11 |
1 |
|
T16 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53151 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[0] |
auto[1] |
1870 |
1 |
|
|
T16 |
13 |
|
T18 |
10 |
|
T19 |
11 |
auto[1] |
auto[0] |
3234 |
1 |
|
|
T9 |
14 |
|
T11 |
9 |
|
T15 |
14 |
auto[1] |
auto[1] |
193 |
1 |
|
|
T11 |
2 |
|
T92 |
1 |
|
T146 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53098 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[0] |
auto[1] |
1923 |
1 |
|
|
T16 |
5 |
|
T18 |
3 |
|
T19 |
9 |
auto[1] |
auto[0] |
3254 |
1 |
|
|
T9 |
13 |
|
T11 |
11 |
|
T15 |
14 |
auto[1] |
auto[1] |
173 |
1 |
|
|
T9 |
1 |
|
T16 |
1 |
|
T86 |
5 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53137 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[0] |
auto[1] |
1884 |
1 |
|
|
T16 |
17 |
|
T18 |
9 |
|
T19 |
10 |
auto[1] |
auto[0] |
3259 |
1 |
|
|
T9 |
13 |
|
T11 |
11 |
|
T15 |
12 |
auto[1] |
auto[1] |
168 |
1 |
|
|
T9 |
1 |
|
T15 |
2 |
|
T16 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53077 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[0] |
auto[1] |
1944 |
1 |
|
|
T16 |
7 |
|
T18 |
6 |
|
T19 |
14 |
auto[1] |
auto[0] |
3234 |
1 |
|
|
T9 |
13 |
|
T11 |
10 |
|
T15 |
14 |
auto[1] |
auto[1] |
193 |
1 |
|
|
T9 |
1 |
|
T11 |
1 |
|
T16 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53198 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T4 |
3 |
auto[0] |
auto[1] |
1823 |
1 |
|
|
T16 |
9 |
|
T18 |
9 |
|
T19 |
5 |
auto[1] |
auto[0] |
3233 |
1 |
|
|
T9 |
14 |
|
T11 |
10 |
|
T15 |
14 |
auto[1] |
auto[1] |
194 |
1 |
|
|
T11 |
1 |
|
T91 |
1 |
|
T146 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39025 |
1 |
|
|
T2 |
10 |
|
T4 |
3 |
|
T8 |
20 |
auto[0] |
auto[1] |
1309 |
1 |
|
|
T34 |
9 |
|
T35 |
13 |
|
T60 |
4 |
auto[1] |
auto[0] |
17329 |
1 |
|
|
T3 |
2 |
|
T15 |
14 |
|
T16 |
13 |
auto[1] |
auto[1] |
785 |
1 |
|
|
T17 |
16 |
|
T18 |
8 |
|
T20 |
7 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38959 |
1 |
|
|
T2 |
10 |
|
T4 |
3 |
|
T8 |
20 |
auto[0] |
auto[1] |
1375 |
1 |
|
|
T34 |
10 |
|
T35 |
18 |
|
T60 |
7 |
auto[1] |
auto[0] |
17357 |
1 |
|
|
T3 |
2 |
|
T15 |
14 |
|
T16 |
13 |
auto[1] |
auto[1] |
757 |
1 |
|
|
T17 |
13 |
|
T18 |
12 |
|
T20 |
8 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38741 |
1 |
|
|
T2 |
10 |
|
T8 |
20 |
|
T9 |
14 |
auto[0] |
auto[1] |
1593 |
1 |
|
|
T4 |
3 |
|
T222 |
19 |
|
T18 |
16 |
auto[1] |
auto[0] |
16939 |
1 |
|
|
T15 |
14 |
|
T17 |
89 |
|
T18 |
64 |
auto[1] |
auto[1] |
1175 |
1 |
|
|
T3 |
2 |
|
T16 |
13 |
|
T223 |
9 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39035 |
1 |
|
|
T2 |
10 |
|
T4 |
3 |
|
T8 |
20 |
auto[0] |
auto[1] |
1299 |
1 |
|
|
T34 |
11 |
|
T35 |
12 |
|
T60 |
7 |
auto[1] |
auto[0] |
17347 |
1 |
|
|
T3 |
2 |
|
T15 |
14 |
|
T16 |
13 |
auto[1] |
auto[1] |
767 |
1 |
|
|
T17 |
13 |
|
T18 |
5 |
|
T20 |
6 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35486 |
1 |
|
|
T2 |
10 |
|
T4 |
3 |
|
T8 |
20 |
auto[0] |
auto[1] |
4848 |
1 |
|
|
T10 |
92 |
|
T34 |
6 |
|
T35 |
7 |
auto[1] |
auto[0] |
17343 |
1 |
|
|
T3 |
2 |
|
T15 |
14 |
|
T16 |
13 |
auto[1] |
auto[1] |
771 |
1 |
|
|
T17 |
5 |
|
T18 |
12 |
|
T20 |
12 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39068 |
1 |
|
|
T2 |
10 |
|
T4 |
3 |
|
T8 |
20 |
auto[0] |
auto[1] |
1266 |
1 |
|
|
T9 |
1 |
|
T11 |
1 |
|
T16 |
13 |
auto[1] |
auto[0] |
17192 |
1 |
|
|
T3 |
2 |
|
T15 |
14 |
|
T16 |
13 |
auto[1] |
auto[1] |
922 |
1 |
|
|
T19 |
8 |
|
T86 |
19 |
|
T94 |
13 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39179 |
1 |
|
|
T2 |
10 |
|
T4 |
3 |
|
T8 |
20 |
auto[0] |
auto[1] |
1155 |
1 |
|
|
T9 |
1 |
|
T11 |
2 |
|
T16 |
10 |
auto[1] |
auto[0] |
17226 |
1 |
|
|
T3 |
2 |
|
T15 |
14 |
|
T16 |
13 |
auto[1] |
auto[1] |
888 |
1 |
|
|
T19 |
8 |
|
T86 |
24 |
|
T94 |
13 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39131 |
1 |
|
|
T2 |
10 |
|
T4 |
3 |
|
T8 |
20 |
auto[0] |
auto[1] |
1203 |
1 |
|
|
T11 |
2 |
|
T16 |
13 |
|
T18 |
10 |
auto[1] |
auto[0] |
17254 |
1 |
|
|
T3 |
2 |
|
T15 |
14 |
|
T16 |
13 |
auto[1] |
auto[1] |
860 |
1 |
|
|
T19 |
11 |
|
T86 |
15 |
|
T94 |
6 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39111 |
1 |
|
|
T2 |
10 |
|
T4 |
3 |
|
T8 |
20 |
auto[0] |
auto[1] |
1223 |
1 |
|
|
T9 |
1 |
|
T16 |
3 |
|
T18 |
9 |
auto[1] |
auto[0] |
17215 |
1 |
|
|
T3 |
2 |
|
T15 |
14 |
|
T16 |
13 |
auto[1] |
auto[1] |
899 |
1 |
|
|
T19 |
11 |
|
T146 |
1 |
|
T86 |
17 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39184 |
1 |
|
|
T2 |
10 |
|
T4 |
3 |
|
T8 |
20 |
auto[0] |
auto[1] |
1150 |
1 |
|
|
T9 |
1 |
|
T16 |
18 |
|
T18 |
9 |
auto[1] |
auto[0] |
17212 |
1 |
|
|
T3 |
2 |
|
T15 |
12 |
|
T16 |
13 |
auto[1] |
auto[1] |
902 |
1 |
|
|
T15 |
2 |
|
T19 |
10 |
|
T86 |
18 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39215 |
1 |
|
|
T2 |
10 |
|
T4 |
3 |
|
T8 |
20 |
auto[0] |
auto[1] |
1119 |
1 |
|
|
T11 |
1 |
|
T16 |
9 |
|
T18 |
9 |
auto[1] |
auto[0] |
17216 |
1 |
|
|
T3 |
2 |
|
T15 |
14 |
|
T16 |
13 |
auto[1] |
auto[1] |
898 |
1 |
|
|
T19 |
5 |
|
T86 |
12 |
|
T94 |
12 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39051 |
1 |
|
|
T2 |
10 |
|
T4 |
3 |
|
T8 |
20 |
auto[0] |
auto[1] |
1283 |
1 |
|
|
T34 |
12 |
|
T35 |
7 |
|
T60 |
9 |
auto[1] |
auto[0] |
17354 |
1 |
|
|
T3 |
2 |
|
T15 |
14 |
|
T16 |
13 |
auto[1] |
auto[1] |
760 |
1 |
|
|
T17 |
11 |
|
T18 |
3 |
|
T20 |
10 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39121 |
1 |
|
|
T2 |
10 |
|
T4 |
3 |
|
T8 |
20 |
auto[0] |
auto[1] |
1213 |
1 |
|
|
T34 |
10 |
|
T35 |
10 |
|
T60 |
7 |
auto[1] |
auto[0] |
17287 |
1 |
|
|
T3 |
2 |
|
T15 |
14 |
|
T16 |
13 |
auto[1] |
auto[1] |
827 |
1 |
|
|
T17 |
7 |
|
T18 |
10 |
|
T20 |
5 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38321 |
1 |
|
|
T2 |
10 |
|
T4 |
3 |
|
T8 |
20 |
auto[0] |
auto[1] |
2013 |
1 |
|
|
T9 |
14 |
|
T11 |
11 |
|
T16 |
12 |
auto[1] |
auto[0] |
16700 |
1 |
|
|
T3 |
2 |
|
T16 |
13 |
|
T17 |
89 |
auto[1] |
auto[1] |
1414 |
1 |
|
|
T15 |
14 |
|
T146 |
11 |
|
T86 |
14 |