Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115741549

1

T1

2541

T2

37352

T3

11828

auto[1]

1496053

1

T4

99

T9

99

T11

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115760804

1

T1

2541

T2

37352

T3

11632

auto[1]

1476798

1

T3

196

T4

198

T9

396

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8081709	1			T1	110		T2	978		T3	357
auto[IdleSt]	23669464	1			T1	2431		T2	274		T3	8709
auto[ClkMuxSt]	38548	1			T2	12		T3	2		T4	3
auto[CntIncrSt]	38302	1			T2	10		T3	2		T4	3
auto[CntProgSt]	1600166	1			T2	294		T3	34		T4	872
auto[TransCheckSt]	29664	1			T2	10		T8	20		T9	8
auto[TokenHashSt]	48189890	1			T2	34701		T8	390		T9	5973
auto[FlashRmaSt]	39655	1			T2	51		T8	119		T9	8
auto[TokenCheck0St]	14026	1			T2	10		T8	20		T9	8
auto[TokenCheck1St]	10397	1			T2	10		T8	20		T9	8
auto[TransProgSt]	470585	1			T2	223		T8	306		T9	29
auto[PostTransSt]	14194313	1			T2	779		T3	1586		T4	245
auto[ScrapSt]	198168	1			T14	4		T39	10		T40	8
auto[EscalateSt]	7516781	1			T3	1138		T4	384		T9	1203
auto[InvalidSt]	13143789	1			T9	795		T11	1021		T37	1331

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2145	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	13143789	1			T9	795		T11	1021		T37	1331
EscalateSt	7516781	1			T3	1138		T4	384		T9	1203
ScrapSt	198168	1			T14	4		T39	10		T40	8
PostTransSt	14194313	1			T2	779		T3	1586		T4	245
TransProgSt	470585	1			T2	223		T8	306		T9	29
TokenCheck1St	10397	1			T2	10		T8	20		T9	8
TokenCheck0St	14026	1			T2	10		T8	20		T9	8
FlashRmaSt	39655	1			T2	51		T8	119		T9	8
TokenHashSt	48189890	1			T2	34701		T8	390		T9	5973
TransCheckSt	29664	1			T2	10		T8	20		T9	8
CntProgSt	1600166	1			T2	294		T3	34		T4	872
CntIncrSt	38302	1			T2	10		T3	2		T4	3
ClkMuxSt	38548	1			T2	12		T3	2		T4	3
IdleSt	23669464	1			T1	2431		T2	274		T3	8709
ResetSt	8081709	1			T1	110		T2	978		T3	357
arcs[ResetSt=>IdleSt]	58737	1			T1	1		T2	10		T3	3
arcs[IdleSt=>ScrapSt]	323	1			T14	1		T39	1		T40	2
arcs[IdleSt=>ClkMuxSt]	38328	1			T2	10		T3	2		T4	3
arcs[ClkMuxSt=>CntIncrSt]	38302	1			T2	10		T3	2		T4	3
arcs[CntIncrSt=>PostTransSt]	2043	1			T34	10		T17	7		T35	10
arcs[CntIncrSt=>CntProgSt]	36203	1			T2	10		T3	2		T4	3
arcs[CntProgSt=>PostTransSt]	5587	1			T3	2		T4	3		T37	13
arcs[CntProgSt=>TransCheckSt]	29664	1			T2	10		T8	20		T9	8
arcs[TransCheckSt=>PostTransSt]	3847	1			T13	36		T34	12		T17	11
arcs[TransCheckSt=>TokenHashSt]	25694	1			T2	10		T8	20		T9	8
arcs[TokenHashSt=>PostTransSt]	10711	1			T10	92		T13	11		T37	7
arcs[TokenHashSt=>FlashRmaSt]	14064	1			T2	10		T8	20		T9	8
arcs[FlashRmaSt=>TokenCheck0St]	14026	1			T2	10		T8	20		T9	8
arcs[TokenCheck0St=>PostTransSt]	3590	1			T13	8		T37	16		T34	8
arcs[TokenCheck0St=>TokenCheck1St]	10397	1			T2	10		T8	20		T9	8
arcs[TokenCheck1St=>PostTransSt]	654	1			T13	11		T37	1		T35	2
arcs[TransProgSt=>PostTransSt]	9011	1			T2	10		T8	20		T9	8
arcs[IdleSt=>EscalateSt]	122	1			T40	9		T53	11		T56	10
arcs[ClkMuxSt=>EscalateSt]	26	1			T40	1		T53	2		T54	4
arcs[CntIncrSt=>EscalateSt]	56	1			T14	1		T40	1		T55	2
arcs[CntProgSt=>EscalateSt]	952	1			T14	3		T40	28		T55	38
arcs[TransCheckSt=>EscalateSt]	123	1			T14	5		T40	1		T55	1
arcs[TokenHashSt=>EscalateSt]	919	1			T14	38		T17	1		T40	15
arcs[FlashRmaSt=>EscalateSt]	38	1			T14	2		T40	2		T53	2
arcs[TokenCheck0St=>EscalateSt]	39	1			T14	1		T40	1		T54	1
arcs[TokenCheck1St=>EscalateSt]	33	1			T14	1		T40	2		T55	1
arcs[TransProgSt=>EscalateSt]	699	1			T14	9		T40	21		T55	11
arcs[PostTransSt=>EscalateSt]	5970	1			T3	2		T4	3		T14	15
arcs[InvalidSt=>EscalateSt]	15385	1			T9	5		T11	7		T37	9

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8081522	1			T1	110		T2	978		T3	357
auto[0]	auto[IdleSt]	23669378	1			T1	2431		T2	274		T3	8709
auto[0]	auto[ClkMuxSt]	38530	1			T2	12		T3	2		T4	3
auto[0]	auto[CntIncrSt]	38266	1			T2	10		T3	2		T4	3
auto[0]	auto[CntProgSt]	1599514	1			T2	294		T3	34		T4	872
auto[0]	auto[TransCheckSt]	29582	1			T2	10		T8	20		T9	8
auto[0]	auto[TokenHashSt]	48189289	1			T2	34701		T8	390		T9	5973
auto[0]	auto[FlashRmaSt]	39633	1			T2	51		T8	119		T9	8
auto[0]	auto[TokenCheck0St]	14001	1			T2	10		T8	20		T9	8
auto[0]	auto[TokenCheck1St]	10379	1			T2	10		T8	20		T9	8
auto[0]	auto[TransProgSt]	470113	1			T2	223		T8	306		T9	29
auto[0]	auto[PostTransSt]	14191230	1			T2	779		T3	1586		T4	244
auto[0]	auto[ScrapSt]	198130	1			T14	4		T39	10		T40	7
auto[0]	auto[EscalateSt]	6033765	1			T3	1138		T4	286		T9	1105
auto[0]	auto[InvalidSt]	13136072	1			T9	794		T11	1018		T37	1325
auto[1]	auto[ResetSt]	187	1			T14	3		T40	2		T55	6
auto[1]	auto[IdleSt]	86	1			T40	5		T53	7		T56	6
auto[1]	auto[ClkMuxSt]	18	1			T40	1		T53	2		T54	3
auto[1]	auto[CntIncrSt]	36	1			T14	1		T40	1		T53	1
auto[1]	auto[CntProgSt]	652	1			T14	3		T40	21		T55	28
auto[1]	auto[TransCheckSt]	82	1			T14	5		T40	1		T55	1
auto[1]	auto[TokenHashSt]	601	1			T14	24		T17	1		T40	9
auto[1]	auto[FlashRmaSt]	22	1			T40	1		T53	1		T54	1
auto[1]	auto[TokenCheck0St]	25	1			T14	1		T40	1		T54	1
auto[1]	auto[TokenCheck1St]	18	1			T14	1		T40	2		T55	1
auto[1]	auto[TransProgSt]	472	1			T14	6		T40	13		T55	5
auto[1]	auto[PostTransSt]	3083	1			T4	1		T14	7		T37	7
auto[1]	auto[ScrapSt]	38	1			T40	1		T54	1		T171	3
auto[1]	auto[EscalateSt]	1483016	1			T4	98		T9	98		T11	294
auto[1]	auto[InvalidSt]	7717	1			T9	1		T11	3		T37	6

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8081545	1			T1	110		T2	978		T3	357
auto[0]	auto[IdleSt]	23669388	1			T1	2431		T2	274		T3	8709
auto[0]	auto[ClkMuxSt]	38530	1			T2	12		T3	2		T4	3
auto[0]	auto[CntIncrSt]	38261	1			T2	10		T3	2		T4	3
auto[0]	auto[CntProgSt]	1599522	1			T2	294		T3	34		T4	872
auto[0]	auto[TransCheckSt]	29587	1			T2	10		T8	20		T9	8
auto[0]	auto[TokenHashSt]	48189274	1			T2	34701		T8	390		T9	5973
auto[0]	auto[FlashRmaSt]	39629	1			T2	51		T8	119		T9	8
auto[0]	auto[TokenCheck0St]	13994	1			T2	10		T8	20		T9	8
auto[0]	auto[TokenCheck1St]	10371	1			T2	10		T8	20		T9	8
auto[0]	auto[TransProgSt]	470111	1			T2	223		T8	306		T9	29
auto[0]	auto[PostTransSt]	14191307	1			T2	779		T3	1584		T4	243
auto[0]	auto[ScrapSt]	198131	1			T14	3		T39	10		T40	6
auto[0]	auto[EscalateSt]	6052888	1			T3	944		T4	188		T9	811
auto[0]	auto[InvalidSt]	13136121	1			T9	791		T11	1017		T37	1328
auto[1]	auto[ResetSt]	164	1			T14	6		T40	4		T55	5
auto[1]	auto[IdleSt]	76	1			T40	6		T53	6		T56	7
auto[1]	auto[ClkMuxSt]	18	1			T53	2		T54	3		T220	1
auto[1]	auto[CntIncrSt]	41	1			T14	1		T55	2		T53	1
auto[1]	auto[CntProgSt]	644	1			T14	1		T40	16		T55	28
auto[1]	auto[TransCheckSt]	77	1			T14	1		T55	1		T53	2
auto[1]	auto[TokenHashSt]	616	1			T14	28		T40	13		T55	8
auto[1]	auto[FlashRmaSt]	26	1			T14	2		T40	1		T53	2
auto[1]	auto[TokenCheck0St]	32	1			T14	1		T40	1		T221	1
auto[1]	auto[TokenCheck1St]	26	1			T14	1		T40	2		T53	1
auto[1]	auto[TransProgSt]	474	1			T14	5		T40	13		T55	10
auto[1]	auto[PostTransSt]	3006	1			T3	2		T4	2		T14	10
auto[1]	auto[ScrapSt]	37	1			T14	1		T40	2		T53	1
auto[1]	auto[EscalateSt]	1463893	1			T3	194		T4	196		T9	392
auto[1]	auto[InvalidSt]	7668	1			T9	4		T11	4		T37	3