Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

127751466

1

T1

58539

T2

4771

T3

13483

auto[1]

1509555

1

T1

495

T2

198

T3

98

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

127740065

1

T1

58143

T2

4870

T3

13385

auto[1]

1520956

1

T1

891

T2

99

T3

196

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8581447	1			T1	8523		T2	1655		T3	345
auto[IdleSt]	25060575	1			T1	9987		T2	1171		T3	9297
auto[ClkMuxSt]	38590	1			T1	86		T2	3		T3	3
auto[CntIncrSt]	38323	1			T1	86		T2	3		T3	3
auto[CntProgSt]	1804372	1			T1	20868		T2	6		T3	6
auto[TransCheckSt]	29925	1			T1	61		T2	3		T10	1
auto[TokenHashSt]	56063081	1			T1	1091		T2	34		T10	32
auto[FlashRmaSt]	38669	1			T1	111		T2	3		T10	1
auto[TokenCheck0St]	14033	1			T1	20		T2	3		T10	1
auto[TokenCheck1St]	10505	1			T1	8		T2	3		T10	1
auto[TransProgSt]	516810	1			T1	1525		T2	6		T10	2
auto[PostTransSt]	14725318	1			T1	14648		T2	761		T3	2233
auto[ScrapSt]	160735	1			T12	14		T5	1278		T44	4
auto[EscalateSt]	7818410	1			T1	2020		T2	827		T3	1694
auto[InvalidSt]	14357845	1			T2	491		T4	78744		T5	89598

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2383	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	14357845	1			T2	491		T4	78744		T5	89598
EscalateSt	7818410	1			T1	2020		T2	827		T3	1694
ScrapSt	160735	1			T12	14		T5	1278		T44	4
PostTransSt	14725318	1			T1	14648		T2	761		T3	2233
TransProgSt	516810	1			T1	1525		T2	6		T10	2
TokenCheck1St	10505	1			T1	8		T2	3		T10	1
TokenCheck0St	14033	1			T1	20		T2	3		T10	1
FlashRmaSt	38669	1			T1	111		T2	3		T10	1
TokenHashSt	56063081	1			T1	1091		T2	34		T10	32
TransCheckSt	29925	1			T1	61		T2	3		T10	1
CntProgSt	1804372	1			T1	20868		T2	6		T3	6
CntIncrSt	38323	1			T1	86		T2	3		T3	3
ClkMuxSt	38590	1			T1	86		T2	3		T3	3
IdleSt	25060575	1			T1	9987		T2	1171		T3	9297
ResetSt	8581447	1			T1	8523		T2	1655		T3	345
arcs[ResetSt=>IdleSt]	59910	1			T1	87		T2	10		T3	4
arcs[IdleSt=>ScrapSt]	373	1			T12	1		T5	2		T44	1
arcs[IdleSt=>ClkMuxSt]	38342	1			T1	86		T2	3		T3	3
arcs[ClkMuxSt=>CntIncrSt]	38323	1			T1	86		T2	3		T3	3
arcs[CntIncrSt=>PostTransSt]	2081	1			T1	11		T5	12		T16	11
arcs[CntIncrSt=>CntProgSt]	36184	1			T1	75		T2	3		T3	3
arcs[CntProgSt=>PostTransSt]	5319	1			T1	14		T3	3		T5	58
arcs[CntProgSt=>TransCheckSt]	29925	1			T1	61		T2	3		T10	1
arcs[TransCheckSt=>PostTransSt]	3885	1			T1	13		T5	14		T15	39
arcs[TransCheckSt=>TokenHashSt]	25910	1			T1	48		T2	3		T10	1
arcs[TokenHashSt=>PostTransSt]	10965	1			T1	28		T5	40		T15	13
arcs[TokenHashSt=>FlashRmaSt]	14084	1			T1	20		T2	3		T10	1
arcs[FlashRmaSt=>TokenCheck0St]	14033	1			T1	20		T2	3		T10	1
arcs[TokenCheck0St=>PostTransSt]	3471	1			T1	12		T5	12		T15	14
arcs[TokenCheck0St=>TokenCheck1St]	10505	1			T1	8		T2	3		T10	1
arcs[TokenCheck1St=>PostTransSt]	674	1			T1	2		T5	1		T15	7
arcs[TransProgSt=>PostTransSt]	9115	1			T1	6		T2	3		T10	1
arcs[IdleSt=>EscalateSt]	130	1			T44	7		T67	4		T73	8
arcs[ClkMuxSt=>EscalateSt]	19	1			T44	1		T65	1		T66	1
arcs[CntIncrSt=>EscalateSt]	58	1			T67	1		T68	1		T69	3
arcs[CntProgSt=>EscalateSt]	940	1			T44	25		T67	33		T68	29
arcs[TransCheckSt=>EscalateSt]	130	1			T44	2		T67	1		T68	2
arcs[TokenHashSt=>EscalateSt]	861	1			T5	2		T44	5		T67	8
arcs[FlashRmaSt=>EscalateSt]	51	1			T70	1		T71	1		T72	1
arcs[TokenCheck0St=>EscalateSt]	57	1			T44	1		T68	2		T70	1
arcs[TokenCheck1St=>EscalateSt]	32	1			T44	1		T67	1		T71	1
arcs[TransProgSt=>EscalateSt]	684	1			T44	8		T67	28		T68	15
arcs[PostTransSt=>EscalateSt]	5680	1			T1	14		T3	3		T5	58
arcs[InvalidSt=>EscalateSt]	16358	1			T2	3		T4	62		T5	67

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8581278	1			T1	8523		T2	1655		T3	345
auto[0]	auto[IdleSt]	25060499	1			T1	9987		T2	1171		T3	9297
auto[0]	auto[ClkMuxSt]	38577	1			T1	86		T2	3		T3	3
auto[0]	auto[CntIncrSt]	38286	1			T1	86		T2	3		T3	3
auto[0]	auto[CntProgSt]	1803765	1			T1	20868		T2	6		T3	6
auto[0]	auto[TransCheckSt]	29835	1			T1	61		T2	3		T10	1
auto[0]	auto[TokenHashSt]	56062534	1			T1	1091		T2	34		T10	32
auto[0]	auto[FlashRmaSt]	38636	1			T1	111		T2	3		T10	1
auto[0]	auto[TokenCheck0St]	13990	1			T1	20		T2	3		T10	1
auto[0]	auto[TokenCheck1St]	10488	1			T1	8		T2	3		T10	1
auto[0]	auto[TransProgSt]	516350	1			T1	1525		T2	6		T10	2
auto[0]	auto[PostTransSt]	14722413	1			T1	14643		T2	761		T3	2232
auto[0]	auto[ScrapSt]	160693	1			T12	14		T5	1278		T44	3
auto[0]	auto[EscalateSt]	6322122	1			T1	1530		T2	631		T3	1597
auto[0]	auto[InvalidSt]	14349617	1			T2	489		T4	78712		T5	89562
auto[1]	auto[ResetSt]	169	1			T44	1		T67	3		T68	2
auto[1]	auto[IdleSt]	76	1			T44	5		T67	2		T73	7
auto[1]	auto[ClkMuxSt]	13	1			T215	1		T216	1		T217	3
auto[1]	auto[CntIncrSt]	37	1			T67	1		T68	1		T69	3
auto[1]	auto[CntProgSt]	607	1			T44	18		T67	18		T68	20
auto[1]	auto[TransCheckSt]	90	1			T44	1		T68	2		T72	5
auto[1]	auto[TokenHashSt]	547	1			T5	2		T44	2		T67	5
auto[1]	auto[FlashRmaSt]	33	1			T70	1		T72	1		T73	1
auto[1]	auto[TokenCheck0St]	43	1			T44	1		T68	2		T72	1
auto[1]	auto[TokenCheck1St]	17	1			T218	1		T219	1		T220	1
auto[1]	auto[TransProgSt]	460	1			T44	5		T67	20		T68	10
auto[1]	auto[PostTransSt]	2905	1			T1	5		T3	1		T5	22
auto[1]	auto[ScrapSt]	42	1			T44	1		T67	1		T68	2
auto[1]	auto[EscalateSt]	1496288	1			T1	490		T2	196		T3	97
auto[1]	auto[InvalidSt]	8228	1			T2	2		T4	32		T5	36

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8581262	1			T1	8523		T2	1655		T3	345
auto[0]	auto[IdleSt]	25060481	1			T1	9987		T2	1171		T3	9297
auto[0]	auto[ClkMuxSt]	38579	1			T1	86		T2	3		T3	3
auto[0]	auto[CntIncrSt]	38282	1			T1	86		T2	3		T3	3
auto[0]	auto[CntProgSt]	1803723	1			T1	20868		T2	6		T3	6
auto[0]	auto[TransCheckSt]	29851	1			T1	61		T2	3		T10	1
auto[0]	auto[TokenHashSt]	56062486	1			T1	1091		T2	34		T10	32
auto[0]	auto[FlashRmaSt]	38638	1			T1	111		T2	3		T10	1
auto[0]	auto[TokenCheck0St]	13995	1			T1	20		T2	3		T10	1
auto[0]	auto[TokenCheck1St]	10479	1			T1	8		T2	3		T10	1
auto[0]	auto[TransProgSt]	516353	1			T1	1525		T2	6		T10	2
auto[0]	auto[PostTransSt]	14722431	1			T1	14639		T2	761		T3	2231
auto[0]	auto[ScrapSt]	160686	1			T12	14		T5	1278		T44	4
auto[0]	auto[EscalateSt]	6310721	1			T1	1138		T2	729		T3	1500
auto[0]	auto[InvalidSt]	14349715	1			T2	490		T4	78714		T5	89567
auto[1]	auto[ResetSt]	185	1			T67	4		T68	2		T70	4
auto[1]	auto[IdleSt]	94	1			T44	5		T67	3		T73	2
auto[1]	auto[ClkMuxSt]	11	1			T44	1		T65	1		T66	1
auto[1]	auto[CntIncrSt]	41	1			T68	1		T69	2		T221	1
auto[1]	auto[CntProgSt]	649	1			T44	19		T67	26		T68	20
auto[1]	auto[TransCheckSt]	74	1			T44	2		T67	1		T72	2
auto[1]	auto[TokenHashSt]	595	1			T44	4		T67	6		T68	8
auto[1]	auto[FlashRmaSt]	31	1			T71	1		T220	3		T216	1
auto[1]	auto[TokenCheck0St]	38	1			T68	2		T70	1		T72	1
auto[1]	auto[TokenCheck1St]	26	1			T44	1		T67	1		T71	1
auto[1]	auto[TransProgSt]	457	1			T44	5		T67	18		T68	11
auto[1]	auto[PostTransSt]	2887	1			T1	9		T3	2		T5	36
auto[1]	auto[ScrapSt]	49	1			T67	2		T68	4		T70	1
auto[1]	auto[EscalateSt]	1507689	1			T1	882		T2	98		T3	194
auto[1]	auto[InvalidSt]	8130	1			T2	1		T4	30		T5	31