Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109109380

1

T1

32710

T2

33798

T3

412974

auto[1]

1400645

1

T2

3465

T3

594

T4

594

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109114795

1

T1

32710

T2

33897

T3

413271

auto[1]

1395230

1

T2

3366

T3

297

T4

396

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7545921	1			T1	1653		T2	13041		T3	6864
auto[IdleSt]	22934987	1			T1	18931		T2	1386		T3	225616
auto[ClkMuxSt]	37191	1			T1	17		T3	75		T8	12
auto[CntIncrSt]	36958	1			T1	17		T3	75		T8	12
auto[CntProgSt]	1528044	1			T1	34		T3	1422		T8	336
auto[TransCheckSt]	28955	1			T1	17		T3	56		T8	12
auto[TokenHashSt]	44677677	1			T1	8591		T3	3152		T8	244
auto[FlashRmaSt]	36541	1			T1	49		T3	44		T8	55
auto[TokenCheck0St]	13371	1			T1	17		T3	18		T8	12
auto[TokenCheck1St]	9899	1			T1	17		T3	13		T8	12
auto[TransProgSt]	387479	1			T1	34		T3	339		T8	312
auto[PostTransSt]	13761447	1			T1	3063		T3	166373		T8	666
auto[ScrapSt]	305221	1			T1	270		T37	2372		T35	292
auto[EscalateSt]	7024316	1			T2	10094		T3	9521		T4	4497
auto[InvalidSt]	12180041	1			T2	12729		T4	1014		T9	2799

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1977	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12180041	1			T2	12729		T4	1014		T9	2799
EscalateSt	7024316	1			T2	10094		T3	9521		T4	4497
ScrapSt	305221	1			T1	270		T37	2372		T35	292
PostTransSt	13761447	1			T1	3063		T3	166373		T8	666
TransProgSt	387479	1			T1	34		T3	339		T8	312
TokenCheck1St	9899	1			T1	17		T3	13		T8	12
TokenCheck0St	13371	1			T1	17		T3	18		T8	12
FlashRmaSt	36541	1			T1	49		T3	44		T8	55
TokenHashSt	44677677	1			T1	8591		T3	3152		T8	244
TransCheckSt	28955	1			T1	17		T3	56		T8	12
CntProgSt	1528044	1			T1	34		T3	1422		T8	336
CntIncrSt	36958	1			T1	17		T3	75		T8	12
ClkMuxSt	37191	1			T1	17		T3	75		T8	12
IdleSt	22934987	1			T1	18931		T2	1386		T3	225616
ResetSt	7545921	1			T1	1653		T2	13041		T3	6864
arcs[ResetSt=>IdleSt]	55484	1			T1	18		T2	78		T3	76
arcs[IdleSt=>ScrapSt]	301	1			T1	1		T37	1		T35	1
arcs[IdleSt=>ClkMuxSt]	36991	1			T1	17		T3	75		T8	12
arcs[ClkMuxSt=>CntIncrSt]	36958	1			T1	17		T3	75		T8	12
arcs[CntIncrSt=>PostTransSt]	1995	1			T3	10		T4	5		T13	14
arcs[CntIncrSt=>CntProgSt]	34900	1			T1	17		T3	65		T8	12
arcs[CntProgSt=>PostTransSt]	4956	1			T3	9		T4	4		T9	15
arcs[CntProgSt=>TransCheckSt]	28955	1			T1	17		T3	56		T8	12
arcs[TransCheckSt=>PostTransSt]	3816	1			T3	5		T4	10		T13	8
arcs[TransCheckSt=>TokenHashSt]	25010	1			T1	17		T3	51		T8	12
arcs[TokenHashSt=>PostTransSt]	10681	1			T3	33		T4	12		T9	14
arcs[TokenHashSt=>FlashRmaSt]	13417	1			T1	17		T3	18		T8	12
arcs[FlashRmaSt=>TokenCheck0St]	13371	1			T1	17		T3	18		T8	12
arcs[TokenCheck0St=>PostTransSt]	3430	1			T3	5		T4	9		T9	11
arcs[TokenCheck0St=>TokenCheck1St]	9899	1			T1	17		T3	13		T8	12
arcs[TokenCheck1St=>PostTransSt]	626	1			T3	2		T14	1		T16	1
arcs[TransProgSt=>PostTransSt]	8526	1			T1	17		T3	11		T8	12
arcs[IdleSt=>EscalateSt]	137	1			T51	6		T52	10		T53	7
arcs[ClkMuxSt=>EscalateSt]	33	1			T51	3		T52	2		T53	2
arcs[CntIncrSt=>EscalateSt]	63	1			T54	1		T55	1		T52	1
arcs[CntProgSt=>EscalateSt]	989	1			T36	31		T51	5		T54	25
arcs[TransCheckSt=>EscalateSt]	129	1			T51	5		T54	4		T55	4
arcs[TokenHashSt=>EscalateSt]	912	1			T35	1		T36	9		T51	22
arcs[FlashRmaSt=>EscalateSt]	46	1			T36	3		T51	2		T54	1
arcs[TokenCheck0St=>EscalateSt]	42	1			T36	1		T51	2		T55	1
arcs[TokenCheck1St=>EscalateSt]	34	1			T36	1		T54	1		T58	1
arcs[TransProgSt=>EscalateSt]	713	1			T36	17		T51	5		T54	17
arcs[PostTransSt=>EscalateSt]	5348	1			T3	9		T4	4		T9	15
arcs[InvalidSt=>EscalateSt]	13933	1			T2	69		T4	6		T9	18

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7545740	1			T1	1653		T2	13041		T3	6864
auto[0]	auto[IdleSt]	22934895	1			T1	18931		T2	1386		T3	225616
auto[0]	auto[ClkMuxSt]	37169	1			T1	17		T3	75		T8	12
auto[0]	auto[CntIncrSt]	36915	1			T1	17		T3	75		T8	12
auto[0]	auto[CntProgSt]	1527369	1			T1	34		T3	1422		T8	336
auto[0]	auto[TransCheckSt]	28873	1			T1	17		T3	56		T8	12
auto[0]	auto[TokenHashSt]	44677067	1			T1	8591		T3	3152		T8	244
auto[0]	auto[FlashRmaSt]	36507	1			T1	49		T3	44		T8	55
auto[0]	auto[TokenCheck0St]	13348	1			T1	17		T3	18		T8	12
auto[0]	auto[TokenCheck1St]	9879	1			T1	17		T3	13		T8	12
auto[0]	auto[TransProgSt]	386994	1			T1	34		T3	339		T8	312
auto[0]	auto[PostTransSt]	13758733	1			T1	3063		T3	166367		T8	666
auto[0]	auto[ScrapSt]	305180	1			T1	270		T37	2372		T35	292
auto[0]	auto[EscalateSt]	5635647	1			T2	6664		T3	8933		T4	3909
auto[0]	auto[InvalidSt]	12173087	1			T2	12694		T4	1012		T9	2790
auto[1]	auto[ResetSt]	181	1			T36	1		T51	4		T54	3
auto[1]	auto[IdleSt]	92	1			T51	5		T52	7		T53	4
auto[1]	auto[ClkMuxSt]	22	1			T51	1		T52	1		T53	2
auto[1]	auto[CntIncrSt]	43	1			T54	1		T52	1		T53	2
auto[1]	auto[CntProgSt]	675	1			T36	23		T51	4		T54	16
auto[1]	auto[TransCheckSt]	82	1			T51	3		T54	2		T55	1
auto[1]	auto[TokenHashSt]	610	1			T35	1		T36	6		T51	15
auto[1]	auto[FlashRmaSt]	34	1			T36	2		T51	2		T54	1
auto[1]	auto[TokenCheck0St]	23	1			T36	1		T51	2		T52	2
auto[1]	auto[TokenCheck1St]	20	1			T58	1		T206	2		T207	1
auto[1]	auto[TransProgSt]	485	1			T36	15		T51	4		T54	9
auto[1]	auto[PostTransSt]	2714	1			T3	6		T4	4		T9	7
auto[1]	auto[ScrapSt]	41	1			T36	1		T54	2		T58	1
auto[1]	auto[EscalateSt]	1388669	1			T2	3430		T3	588		T4	588
auto[1]	auto[InvalidSt]	6954	1			T2	35		T4	2		T9	9

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7545769	1			T1	1653		T2	13041		T3	6864
auto[0]	auto[IdleSt]	22934895	1			T1	18931		T2	1386		T3	225616
auto[0]	auto[ClkMuxSt]	37168	1			T1	17		T3	75		T8	12
auto[0]	auto[CntIncrSt]	36914	1			T1	17		T3	75		T8	12
auto[0]	auto[CntProgSt]	1527395	1			T1	34		T3	1422		T8	336
auto[0]	auto[TransCheckSt]	28870	1			T1	17		T3	56		T8	12
auto[0]	auto[TokenHashSt]	44677075	1			T1	8591		T3	3152		T8	244
auto[0]	auto[FlashRmaSt]	36515	1			T1	49		T3	44		T8	55
auto[0]	auto[TokenCheck0St]	13337	1			T1	17		T3	18		T8	12
auto[0]	auto[TokenCheck1St]	9877	1			T1	17		T3	13		T8	12
auto[0]	auto[TransProgSt]	386991	1			T1	34		T3	339		T8	312
auto[0]	auto[PostTransSt]	13758686	1			T1	3063		T3	166370		T8	666
auto[0]	auto[ScrapSt]	305185	1			T1	270		T37	2372		T35	292
auto[0]	auto[EscalateSt]	5641079	1			T2	6762		T3	9227		T4	4105
auto[0]	auto[InvalidSt]	12173062	1			T2	12695		T4	1010		T9	2790
auto[1]	auto[ResetSt]	152	1			T51	3		T54	3		T55	2
auto[1]	auto[IdleSt]	92	1			T51	4		T52	6		T53	5
auto[1]	auto[ClkMuxSt]	23	1			T51	3		T52	1		T206	1
auto[1]	auto[CntIncrSt]	44	1			T55	1		T52	1		T53	2
auto[1]	auto[CntProgSt]	649	1			T36	19		T51	3		T54	18
auto[1]	auto[TransCheckSt]	85	1			T51	3		T54	2		T55	3
auto[1]	auto[TokenHashSt]	602	1			T36	9		T51	15		T54	17
auto[1]	auto[FlashRmaSt]	26	1			T36	1		T54	1		T55	1
auto[1]	auto[TokenCheck0St]	34	1			T51	1		T55	1		T52	2
auto[1]	auto[TokenCheck1St]	22	1			T36	1		T54	1		T52	1
auto[1]	auto[TransProgSt]	488	1			T36	14		T51	3		T54	10
auto[1]	auto[PostTransSt]	2761	1			T3	3		T9	8		T13	4
auto[1]	auto[ScrapSt]	36	1			T36	1		T51	1		T54	2
auto[1]	auto[EscalateSt]	1383237	1			T2	3332		T3	294		T4	392
auto[1]	auto[InvalidSt]	6979	1			T2	34		T4	4		T9	9