Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58599 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
2008 |
1 |
|
|
T5 |
4 |
|
T6 |
60 |
|
T16 |
30 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59812 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
795 |
1 |
|
|
T50 |
23 |
|
T51 |
12 |
|
T52 |
15 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58294 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
2313 |
1 |
|
|
T6 |
63 |
|
T13 |
7 |
|
T16 |
9 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58283 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
2324 |
1 |
|
|
T6 |
79 |
|
T13 |
8 |
|
T16 |
11 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58271 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
2336 |
1 |
|
|
T6 |
60 |
|
T13 |
6 |
|
T16 |
15 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
54823 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
no_err_inj |
5784 |
1 |
|
|
T5 |
18 |
|
T6 |
134 |
|
T13 |
26 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58674 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
1933 |
1 |
|
|
T5 |
6 |
|
T6 |
53 |
|
T16 |
24 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59805 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
802 |
1 |
|
|
T50 |
13 |
|
T51 |
6 |
|
T52 |
23 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40538 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
20069 |
1 |
|
|
T5 |
10 |
|
T6 |
793 |
|
T13 |
12 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58226 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
2381 |
1 |
|
|
T6 |
55 |
|
T13 |
5 |
|
T16 |
12 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58208 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
2399 |
1 |
|
|
T6 |
73 |
|
T13 |
7 |
|
T16 |
12 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58336 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
2271 |
1 |
|
|
T6 |
58 |
|
T13 |
10 |
|
T16 |
8 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58732 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
1875 |
1 |
|
|
T5 |
7 |
|
T6 |
73 |
|
T16 |
26 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58034 |
1 |
|
|
T3 |
79 |
|
T4 |
62 |
|
T5 |
71 |
auto[1] |
2573 |
1 |
|
|
T2 |
6 |
|
T10 |
3 |
|
T6 |
79 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59839 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
768 |
1 |
|
|
T50 |
20 |
|
T51 |
18 |
|
T52 |
22 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59806 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
801 |
1 |
|
|
T50 |
25 |
|
T51 |
11 |
|
T52 |
15 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59808 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
799 |
1 |
|
|
T50 |
10 |
|
T51 |
15 |
|
T52 |
18 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57513 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
3094 |
1 |
|
|
T6 |
121 |
|
T16 |
23 |
|
T75 |
15 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56671 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T5 |
71 |
auto[1] |
3936 |
1 |
|
|
T4 |
62 |
|
T15 |
72 |
|
T39 |
97 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58242 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
2365 |
1 |
|
|
T6 |
68 |
|
T13 |
8 |
|
T16 |
12 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58205 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
2402 |
1 |
|
|
T6 |
74 |
|
T13 |
4 |
|
T16 |
12 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58254 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
2353 |
1 |
|
|
T6 |
63 |
|
T13 |
6 |
|
T16 |
5 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58594 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
2013 |
1 |
|
|
T5 |
7 |
|
T6 |
56 |
|
T16 |
26 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54929 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
5678 |
1 |
|
|
T5 |
6 |
|
T6 |
54 |
|
T16 |
33 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56869 |
1 |
|
|
T2 |
6 |
|
T4 |
62 |
|
T5 |
71 |
auto[1] |
3738 |
1 |
|
|
T3 |
79 |
|
T11 |
88 |
|
T28 |
70 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
60607 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58635 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
1972 |
1 |
|
|
T5 |
8 |
|
T6 |
47 |
|
T16 |
30 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58577 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
2030 |
1 |
|
|
T5 |
9 |
|
T6 |
64 |
|
T16 |
28 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58649 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[1] |
1958 |
1 |
|
|
T5 |
6 |
|
T6 |
53 |
|
T16 |
31 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
53340 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
no_err_inj |
4173 |
1 |
|
|
T5 |
18 |
|
T6 |
78 |
|
T13 |
26 |
auto[1] |
err_inj |
1483 |
1 |
|
|
T6 |
65 |
|
T16 |
8 |
|
T75 |
10 |
auto[1] |
no_err_inj |
1611 |
1 |
|
|
T6 |
56 |
|
T16 |
15 |
|
T75 |
5 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
55286 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
auto[1] |
2227 |
1 |
|
|
T6 |
68 |
|
T13 |
4 |
|
T16 |
11 |
auto[1] |
auto[0] |
2919 |
1 |
|
|
T6 |
115 |
|
T16 |
22 |
|
T75 |
13 |
auto[1] |
auto[1] |
175 |
1 |
|
|
T6 |
6 |
|
T16 |
1 |
|
T75 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
55280 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
auto[1] |
2233 |
1 |
|
|
T6 |
63 |
|
T13 |
7 |
|
T16 |
9 |
auto[1] |
auto[0] |
2928 |
1 |
|
|
T6 |
111 |
|
T16 |
20 |
|
T75 |
13 |
auto[1] |
auto[1] |
166 |
1 |
|
|
T6 |
10 |
|
T16 |
3 |
|
T75 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
55348 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
auto[1] |
2165 |
1 |
|
|
T6 |
58 |
|
T13 |
6 |
|
T16 |
5 |
auto[1] |
auto[0] |
2906 |
1 |
|
|
T6 |
116 |
|
T16 |
23 |
|
T75 |
13 |
auto[1] |
auto[1] |
188 |
1 |
|
|
T6 |
5 |
|
T75 |
2 |
|
T74 |
2 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
55345 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
auto[1] |
2168 |
1 |
|
|
T6 |
67 |
|
T13 |
8 |
|
T16 |
11 |
auto[1] |
auto[0] |
2938 |
1 |
|
|
T6 |
109 |
|
T16 |
23 |
|
T75 |
15 |
auto[1] |
auto[1] |
156 |
1 |
|
|
T6 |
12 |
|
T74 |
1 |
|
T199 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
55324 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
auto[1] |
2189 |
1 |
|
|
T6 |
49 |
|
T13 |
6 |
|
T16 |
14 |
auto[1] |
auto[0] |
2947 |
1 |
|
|
T6 |
110 |
|
T16 |
22 |
|
T75 |
14 |
auto[1] |
auto[1] |
147 |
1 |
|
|
T6 |
11 |
|
T16 |
1 |
|
T75 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
55378 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
auto[1] |
2135 |
1 |
|
|
T6 |
55 |
|
T13 |
7 |
|
T16 |
8 |
auto[1] |
auto[0] |
2916 |
1 |
|
|
T6 |
113 |
|
T16 |
22 |
|
T75 |
15 |
auto[1] |
auto[1] |
178 |
1 |
|
|
T6 |
8 |
|
T16 |
1 |
|
T76 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39459 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
auto[1] |
1079 |
1 |
|
|
T5 |
4 |
|
T6 |
13 |
|
T16 |
19 |
auto[1] |
auto[0] |
19140 |
1 |
|
|
T5 |
10 |
|
T6 |
746 |
|
T13 |
12 |
auto[1] |
auto[1] |
929 |
1 |
|
|
T6 |
47 |
|
T16 |
11 |
|
T18 |
12 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39500 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
auto[1] |
1038 |
1 |
|
|
T5 |
6 |
|
T6 |
14 |
|
T16 |
12 |
auto[1] |
auto[0] |
19174 |
1 |
|
|
T5 |
10 |
|
T6 |
754 |
|
T13 |
12 |
auto[1] |
auto[1] |
895 |
1 |
|
|
T6 |
39 |
|
T16 |
12 |
|
T18 |
9 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39108 |
1 |
|
|
T3 |
79 |
|
T4 |
62 |
|
T5 |
61 |
auto[0] |
auto[1] |
1430 |
1 |
|
|
T2 |
6 |
|
T10 |
3 |
|
T6 |
63 |
auto[1] |
auto[0] |
18926 |
1 |
|
|
T5 |
10 |
|
T6 |
777 |
|
T13 |
10 |
auto[1] |
auto[1] |
1143 |
1 |
|
|
T6 |
16 |
|
T13 |
2 |
|
T16 |
5 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39506 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
auto[1] |
1032 |
1 |
|
|
T5 |
7 |
|
T6 |
29 |
|
T16 |
20 |
auto[1] |
auto[0] |
19226 |
1 |
|
|
T5 |
10 |
|
T6 |
749 |
|
T13 |
12 |
auto[1] |
auto[1] |
843 |
1 |
|
|
T6 |
44 |
|
T16 |
6 |
|
T18 |
10 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35797 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
auto[1] |
4741 |
1 |
|
|
T5 |
6 |
|
T6 |
12 |
|
T16 |
23 |
auto[1] |
auto[0] |
19132 |
1 |
|
|
T5 |
10 |
|
T6 |
751 |
|
T13 |
12 |
auto[1] |
auto[1] |
937 |
1 |
|
|
T6 |
42 |
|
T16 |
10 |
|
T18 |
4 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39175 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
auto[1] |
1363 |
1 |
|
|
T6 |
17 |
|
T13 |
4 |
|
T16 |
11 |
auto[1] |
auto[0] |
19030 |
1 |
|
|
T5 |
10 |
|
T6 |
736 |
|
T13 |
12 |
auto[1] |
auto[1] |
1039 |
1 |
|
|
T6 |
57 |
|
T16 |
1 |
|
T19 |
3 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39178 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
auto[1] |
1360 |
1 |
|
|
T6 |
28 |
|
T13 |
8 |
|
T16 |
12 |
auto[1] |
auto[0] |
19064 |
1 |
|
|
T5 |
10 |
|
T6 |
753 |
|
T13 |
12 |
auto[1] |
auto[1] |
1005 |
1 |
|
|
T6 |
40 |
|
T19 |
8 |
|
T74 |
17 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39165 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
auto[1] |
1373 |
1 |
|
|
T6 |
27 |
|
T13 |
7 |
|
T16 |
9 |
auto[1] |
auto[0] |
19043 |
1 |
|
|
T5 |
10 |
|
T6 |
747 |
|
T13 |
12 |
auto[1] |
auto[1] |
1026 |
1 |
|
|
T6 |
46 |
|
T16 |
3 |
|
T19 |
5 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39191 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
auto[1] |
1347 |
1 |
|
|
T6 |
22 |
|
T13 |
5 |
|
T16 |
11 |
auto[1] |
auto[0] |
19035 |
1 |
|
|
T5 |
10 |
|
T6 |
760 |
|
T13 |
12 |
auto[1] |
auto[1] |
1034 |
1 |
|
|
T6 |
33 |
|
T16 |
1 |
|
T19 |
3 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39181 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
auto[1] |
1357 |
1 |
|
|
T6 |
31 |
|
T13 |
8 |
|
T16 |
11 |
auto[1] |
auto[0] |
19102 |
1 |
|
|
T5 |
10 |
|
T6 |
745 |
|
T13 |
12 |
auto[1] |
auto[1] |
967 |
1 |
|
|
T6 |
48 |
|
T19 |
6 |
|
T74 |
15 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39233 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
auto[1] |
1305 |
1 |
|
|
T6 |
28 |
|
T13 |
7 |
|
T16 |
8 |
auto[1] |
auto[0] |
19061 |
1 |
|
|
T5 |
10 |
|
T6 |
758 |
|
T13 |
12 |
auto[1] |
auto[1] |
1008 |
1 |
|
|
T6 |
35 |
|
T16 |
1 |
|
T19 |
9 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39489 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
auto[1] |
1049 |
1 |
|
|
T5 |
6 |
|
T6 |
18 |
|
T16 |
21 |
auto[1] |
auto[0] |
19160 |
1 |
|
|
T5 |
10 |
|
T6 |
758 |
|
T13 |
12 |
auto[1] |
auto[1] |
909 |
1 |
|
|
T6 |
35 |
|
T16 |
10 |
|
T18 |
7 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39435 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
auto[1] |
1103 |
1 |
|
|
T5 |
9 |
|
T6 |
19 |
|
T16 |
20 |
auto[1] |
auto[0] |
19142 |
1 |
|
|
T5 |
10 |
|
T6 |
748 |
|
T13 |
12 |
auto[1] |
auto[1] |
927 |
1 |
|
|
T6 |
45 |
|
T16 |
8 |
|
T18 |
14 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38756 |
1 |
|
|
T2 |
6 |
|
T3 |
79 |
|
T4 |
62 |
auto[0] |
auto[1] |
1782 |
1 |
|
|
T6 |
71 |
|
T75 |
15 |
|
T74 |
21 |
auto[1] |
auto[0] |
18757 |
1 |
|
|
T5 |
10 |
|
T6 |
743 |
|
T13 |
12 |
auto[1] |
auto[1] |
1312 |
1 |
|
|
T6 |
50 |
|
T16 |
23 |
|
T76 |
11 |