Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

129429747

1

T1

1303

T2

2424

T3

23968

auto[1]

1611022

1

T2

297

T4

7630

T5

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

129420242

1

T1

1303

T2

2424

T3

23968

auto[1]

1620527

1

T2

297

T4

8757

T5

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8442555	1			T1	82		T2	634		T3	7458
auto[IdleSt]	25933056	1			T1	212		T2	1000		T3	2883
auto[ClkMuxSt]	38226	1			T2	6		T3	79		T4	51
auto[CntIncrSt]	37930	1			T2	6		T3	79		T4	51
auto[CntProgSt]	1844930	1			T2	18		T3	158		T4	102
auto[TransCheckSt]	29547	1			T3	79		T4	49		T5	56
auto[TokenHashSt]	54479689	1			T3	1140		T4	12941		T5	504707
auto[FlashRmaSt]	40039	1			T3	37		T4	54		T5	94
auto[TokenCheck0St]	14024	1			T3	25		T4	26		T5	29
auto[TokenCheck1St]	10537	1			T3	10		T4	22		T5	23
auto[TransProgSt]	527358	1			T4	43		T5	2841		T6	7758
auto[PostTransSt]	15555506	1			T1	1009		T2	378		T3	12020
auto[ScrapSt]	225576	1			T4	8		T5	399		T6	36
auto[EscalateSt]	8331991	1			T2	679		T4	13011		T5	575
auto[InvalidSt]	15527333	1			T6	407205		T13	8432		T16	31527

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2472	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	15527333	1			T6	407205		T13	8432		T16	31527
EscalateSt	8331991	1			T2	679		T4	13011		T5	575
ScrapSt	225576	1			T4	8		T5	399		T6	36
PostTransSt	15555506	1			T1	1009		T2	378		T3	12020
TransProgSt	527358	1			T4	43		T5	2841		T6	7758
TokenCheck1St	10537	1			T3	10		T4	22		T5	23
TokenCheck0St	14024	1			T3	25		T4	26		T5	29
FlashRmaSt	40039	1			T3	37		T4	54		T5	94
TokenHashSt	54479689	1			T3	1140		T4	12941		T5	504707
TransCheckSt	29547	1			T3	79		T4	49		T5	56
CntProgSt	1844930	1			T2	18		T3	158		T4	102
CntIncrSt	37930	1			T2	6		T3	79		T4	51
ClkMuxSt	38226	1			T2	6		T3	79		T4	51
IdleSt	25933056	1			T1	212		T2	1000		T3	2883
ResetSt	8442555	1			T1	82		T2	634		T3	7458
arcs[ResetSt=>IdleSt]	60569	1			T1	1		T2	7		T3	80
arcs[IdleSt=>ScrapSt]	350	1			T4	2		T5	2		T6	4
arcs[IdleSt=>ClkMuxSt]	37973	1			T2	6		T3	79		T4	51
arcs[ClkMuxSt=>CntIncrSt]	37930	1			T2	6		T3	79		T4	51
arcs[CntIncrSt=>PostTransSt]	2031	1			T5	9		T6	64		T16	28
arcs[CntIncrSt=>CntProgSt]	35833	1			T2	6		T3	79		T4	51
arcs[CntProgSt=>PostTransSt]	5343	1			T2	6		T5	4		T10	3
arcs[CntProgSt=>TransCheckSt]	29547	1			T3	79		T4	49		T5	56
arcs[TransCheckSt=>PostTransSt]	3804	1			T3	42		T5	6		T6	53
arcs[TransCheckSt=>TokenHashSt]	25625	1			T3	37		T4	46		T5	50
arcs[TokenHashSt=>PostTransSt]	10633	1			T3	12		T5	21		T6	157
arcs[TokenHashSt=>FlashRmaSt]	14068	1			T3	25		T4	27		T5	29
arcs[FlashRmaSt=>TokenCheck0St]	14024	1			T3	25		T4	26		T5	29
arcs[TokenCheck0St=>PostTransSt]	3419	1			T3	15		T5	6		T6	48
arcs[TokenCheck0St=>TokenCheck1St]	10537	1			T3	10		T4	22		T5	23
arcs[TokenCheck1St=>PostTransSt]	682	1			T3	10		T6	5		T11	10
arcs[TransProgSt=>PostTransSt]	9038	1			T4	13		T5	23		T6	206
arcs[IdleSt=>EscalateSt]	192	1			T4	3		T39	3		T40	6
arcs[ClkMuxSt=>EscalateSt]	43	1			T39	1		T40	2		T41	2
arcs[CntIncrSt=>EscalateSt]	66	1			T15	2		T39	2		T40	2
arcs[CntProgSt=>EscalateSt]	943	1			T4	2		T15	8		T39	31
arcs[TransCheckSt=>EscalateSt]	118	1			T4	3		T15	4		T39	1
arcs[TokenHashSt=>EscalateSt]	924	1			T4	19		T15	30		T39	12
arcs[FlashRmaSt=>EscalateSt]	44	1			T4	1		T39	2		T40	1
arcs[TokenCheck0St=>EscalateSt]	68	1			T4	4		T15	2		T39	1
arcs[TokenCheck1St=>EscalateSt]	25	1			T39	2		T45	1		T46	2
arcs[TransProgSt=>EscalateSt]	792	1			T4	9		T15	10		T39	29
arcs[PostTransSt=>EscalateSt]	5739	1			T2	6		T4	13		T5	4
arcs[InvalidSt=>EscalateSt]	17337	1			T6	472		T13	45		T16	83

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8442352	1			T1	82		T2	634		T3	7458
auto[0]	auto[IdleSt]	25932933	1			T1	212		T2	1000		T3	2883
auto[0]	auto[ClkMuxSt]	38201	1			T2	6		T3	79		T4	51
auto[0]	auto[CntIncrSt]	37888	1			T2	6		T3	79		T4	51
auto[0]	auto[CntProgSt]	1844310	1			T2	18		T3	158		T4	101
auto[0]	auto[TransCheckSt]	29467	1			T3	79		T4	46		T5	56
auto[0]	auto[TokenHashSt]	54479085	1			T3	1140		T4	12929		T5	504707
auto[0]	auto[FlashRmaSt]	40013	1			T3	37		T4	54		T5	94
auto[0]	auto[TokenCheck0St]	13979	1			T3	25		T4	24		T5	29
auto[0]	auto[TokenCheck1St]	10523	1			T3	10		T4	22		T5	23
auto[0]	auto[TransProgSt]	526829	1			T4	36		T5	2841		T6	7758
auto[0]	auto[PostTransSt]	15552562	1			T1	1009		T2	375		T3	12020
auto[0]	auto[ScrapSt]	225536	1			T4	7		T5	399		T6	36
auto[0]	auto[EscalateSt]	6734881	1			T2	385		T4	5419		T5	379
auto[0]	auto[InvalidSt]	15518716	1			T6	406995		T13	8410		T16	31493
auto[1]	auto[ResetSt]	203	1			T4	1		T15	4		T39	5
auto[1]	auto[IdleSt]	123	1			T4	3		T39	3		T40	4
auto[1]	auto[ClkMuxSt]	25	1			T39	1		T40	1		T193	3
auto[1]	auto[CntIncrSt]	42	1			T15	1		T39	1		T194	1
auto[1]	auto[CntProgSt]	620	1			T4	1		T15	5		T39	23
auto[1]	auto[TransCheckSt]	80	1			T4	3		T15	3		T39	1
auto[1]	auto[TokenHashSt]	604	1			T4	12		T15	17		T39	8
auto[1]	auto[FlashRmaSt]	26	1			T39	2		T195	1		T193	2
auto[1]	auto[TokenCheck0St]	45	1			T4	2		T39	1		T40	1
auto[1]	auto[TokenCheck1St]	14	1			T196	2		T197	1		T198	1
auto[1]	auto[TransProgSt]	529	1			T4	7		T15	5		T39	17
auto[1]	auto[PostTransSt]	2944	1			T2	3		T4	8		T5	2
auto[1]	auto[ScrapSt]	40	1			T4	1		T39	2		T41	1
auto[1]	auto[EscalateSt]	1597110	1			T2	294		T4	7592		T5	196
auto[1]	auto[InvalidSt]	8617	1			T6	210		T13	22		T16	34

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8442357	1			T1	82		T2	634		T3	7458
auto[0]	auto[IdleSt]	25932924	1			T1	212		T2	1000		T3	2883
auto[0]	auto[ClkMuxSt]	38196	1			T2	6		T3	79		T4	51
auto[0]	auto[CntIncrSt]	37878	1			T2	6		T3	79		T4	51
auto[0]	auto[CntProgSt]	1844317	1			T2	18		T3	158		T4	100
auto[0]	auto[TransCheckSt]	29463	1			T3	79		T4	47		T5	56
auto[0]	auto[TokenHashSt]	54479077	1			T3	1140		T4	12930		T5	504707
auto[0]	auto[FlashRmaSt]	40007	1			T3	37		T4	53		T5	94
auto[0]	auto[TokenCheck0St]	13977	1			T3	25		T4	22		T5	29
auto[0]	auto[TokenCheck1St]	10519	1			T3	10		T4	22		T5	23
auto[0]	auto[TransProgSt]	526833	1			T4	37		T5	2841		T6	7758
auto[0]	auto[PostTransSt]	15552609	1			T1	1009		T2	375		T3	12020
auto[0]	auto[ScrapSt]	225529	1			T4	6		T5	399		T6	36
auto[0]	auto[EscalateSt]	6725471	1			T2	385		T4	4295		T5	379
auto[0]	auto[InvalidSt]	15518613	1			T6	406943		T13	8409		T16	31478
auto[1]	auto[ResetSt]	198	1			T4	6		T15	5		T39	4
auto[1]	auto[IdleSt]	132	1			T4	1		T39	2		T40	5
auto[1]	auto[ClkMuxSt]	30	1			T40	1		T41	2		T195	1
auto[1]	auto[CntIncrSt]	52	1			T15	1		T39	2		T40	2
auto[1]	auto[CntProgSt]	613	1			T4	2		T15	4		T39	18
auto[1]	auto[TransCheckSt]	84	1			T4	2		T15	4		T39	1
auto[1]	auto[TokenHashSt]	612	1			T4	11		T15	20		T39	8
auto[1]	auto[FlashRmaSt]	32	1			T4	1		T39	1		T40	1
auto[1]	auto[TokenCheck0St]	47	1			T4	4		T15	2		T40	1
auto[1]	auto[TokenCheck1St]	18	1			T39	2		T45	1		T46	2
auto[1]	auto[TransProgSt]	525	1			T4	6		T15	9		T39	20
auto[1]	auto[PostTransSt]	2897	1			T2	3		T4	6		T5	2
auto[1]	auto[ScrapSt]	47	1			T4	2		T39	1		T194	3
auto[1]	auto[EscalateSt]	1606520	1			T2	294		T4	8716		T5	196
auto[1]	auto[InvalidSt]	8720	1			T6	262		T13	23		T16	49